Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e870c6fc104598bc571dbaa29503ae2
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

Add support for PM API SYS to get the chip ID from the target.
The API calls the IPI command to read the Chip idcode and revision.

Change-Id: Id4d7d812cbf77c5e2fc7785b8afb379214f8dd19
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

* changes:
  fix(versal): fix BLXX memory limits for user defined values
  fix(zynqmp): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1).  However, the linker
file aligns section on a page boundary. So having the -1 in
the size calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

While at it fix all other occurences of predefined values that were
calculated with -1.

Fixes: 1d333e69

 ("feat(versal-net): add support for Xilinx
Versal NET platform")
Change-Id: I4455f63ee3ad52369f517a7d8d3627faf0b28c0f
Signed-off-by: Michal Simek <michal.simek@amd.com>

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1).  However, the linker file
aligns section on a page boundary.  So having the -1 in the size
calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

While at it fix all other occurences of predefined values that were
calculated with -1

Fixes: commit f91c3cb1

 ("arm64: versal: Add support for new Xilinx Versal ACAPs")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ica1f97867b701e7fcd60ea8ea07d2ae96c485443

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1).  However, the linker file
aligns section on a page boundary.  So having the -1 in the size
calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

Commit 9b4ed0af ("feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM'")
applied a similar fix, but only in the predefined for BL31LIMIT/BASE.

While at it fix all other occurences of predefined values that were
calculated with -1

Fixes: 01555332

 ("zynqmp: Revise memory configuration options")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ic96e36808d01f6bb92e6839cec92fc52320dd3f3

* changes:
  feat(intel): restructure sys mgr for S10/N5X
  feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I385455671413e154d04a879d33fdd774fcfefbd6

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb

Add checking on the size of source data does not exceed source size
when using memcpy and memset.

Add checking on the size of source data in FPGA Crypto Service does
not exceed the maximum of expected data size and does not meet the
minimum of expected data size.

Signed-off-by: Phui Kei Wong <phui.kei.wong@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idb18f05c18d9142fbe703c3f4075341d179d8bad

Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I0618dfcdc86a7c1e0c8047b7214d369866dd2281

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I8d3966e230609f9da4c313201ed0cb0f46f27200

The feature support overview is meant to list all the major features
present in TF-A. It should be precise, non-exhaustive and up-to-date.

Updated the document with new features and removed few unnecessary
details.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I28b378f405a6b9d8f86e7b44e435c33625e3d260

Pin poetry to version 1.3.2, which is currently used in CI, to ensure
that all builds are consistent. Also, fix typo in `doc` group name.

Change-Id: Id0c1aa88ac7ffcc241a51c693570e87abacf7ebc
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

Change-Id: Ic8cd82c5424af422feedefdc001d291001817a8b
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

Change-Id: Id22715cb1d36edf6cb8719f3a0415993f067e7c9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

* changes:
  fix(morello): remove platform specific pwr_domain_suspend wrapper
  fix(n1sdp): remove platform specific pwr_domain_suspend wrapper

Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platform specific
psci pwr_domain_suspend handler.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I0a307cc140447e91fd0808fcfb309593f24c14ca

Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platform specific
psci pwr_domain_suspend handler.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ic2ad5a561be29eee9229a5cc11aa3c9320a51cb7

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I433488ecbaf7773a9e062223599fb0d3bc892f94

Update the documentation related with memory region nodes
of SP's FF-A manifest, to relate to changes from patches [1].

[1] https://review.trustedfirmware.org/q/topic:%22ja%252Fmem_region_fix%22+(status:open%20OR%20status:merged)



Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I16595ec581b0ad9d2c20fca8dab64b6fd9ad001a

Add results from running the TFTF test suite Runtime Instrumentation on Juno.

Change-Id: I4c5b64e1a80b5b88e42835f0700294a02edc8032
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

The commit 3e14df6f removed clearing of argument registers even when
BL31 is the first stage. In that case the registers are left in a random
state. TI platforms check that the arguments have been zero'd in early
setup and so all TI platforms are not broken. Not sure why this check was
here at all, so simply remove it to fix boot.

Fixes: 3e14df6f

 ("fix(bl31): avoid clearing of argument registers in RESET_TO_BL31 case")
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I02bdd16b67fb5facc4c47ec596a42f110a663377

Update to use the following software:

- mbed TLS == 3.4.0
- (DTC) >= 1.4.7
- Ubuntu 22.04 for builds.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I384aab4dfee9cae9453eebf4091abe82ef9ccfaa

* changes:
  docs(spm): threat model for memory sharing functionality
  docs(spm): add memory sharing documentation