- Apr 24, 2019
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Alan Tull authored
Enable the LTC2497 driver to support the two LTC2497's that are on the SoCFPGA Arria10 Devkit. Signed-off-by:
Alan Tull <atull@kernel.org> Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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- Apr 18, 2019
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Miquel Raynal authored
MTD_NAND is large and encloses much more than what the symbol is actually used for: raw NAND. Clarify the symbol by naming it MTD_RAW_NAND instead. Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com>
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- Apr 02, 2019
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Thor Thayer authored
Add System Manager driver by default for SOCFPGA ARM32 platforms. Signed-off-by:
Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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- Mar 28, 2019
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Andrey Zhizhikin authored
Enable CONFIG_LBDAF, which is required by ext4 fs. This option could handle both ext3 and ext4, with ext4 requires this option to be enabled, otherwise the filesystem is mounted RO mode. Since the LBDAF is enabled by default for 32-bit systems, simply removing the current "not set" entry enables the support. Signed-off-by:
Andrey Zhizhikin <andrey.z@gmail.com> Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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- Feb 04, 2019
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Dinh Nguyen authored
Add CONFIG_BLK_DEV_LOOP and clean up socfpga_defconfig by make savedefconfig. Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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- Apr 16, 2018
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Thor Thayer authored
Remove QSPI Sector 4K size force which is causing QSPI boot problems with the JFFS2 root filesystem. Fixes the following error: "Magic bitmask 0x1985 not found at ..." Cc: stable@vger.kernel.org Signed-off-by:
Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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- Mar 16, 2017
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Jia Jie Ho authored
This patch enables Altera TSE support in socfpga_defconfig Signed-off-by:
Jia Jie Ho <ho.jia.jie@intel.com> Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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- Jan 03, 2017
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Dinh Nguyen authored
MARVELL_PHY - support for the Marvell PHY that is on most of the devkits EEPROM_AT24 - support for I2C EEPROMs on the devkits GPIO_ALTERA - support for Altera's GPIO driver NAND - support for the Denali NAND controller along with MTD subsystem SPI_DESIGNWARE - support for SPI that is on SoCFPGA SPI_DW_MMIO - support for the memory-mapped io interface for the DW SPI core OF_CONFIGFS - SoCFPGA makes use of DT overlays using configfs, enable it GPIO_ALTERA_A10SR - support for the newly added Altera HWMON driver LEDS - support for the GPIO LEDs on the SoCFPGA devkits RTC - support for the DS1307 RTC JFFS2_FS - support for the JFFS2 filesystem NFS_V4 - supports for v4 NFS FUNCTION_TRACER - supports debug function tracing Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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- Nov 09, 2016
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Dinh Nguyen authored
systemd on the Angstrom root file system expects AUTOFS to be configured as a module and NFSD to be statically linked into the kernel. This patch adds the necessary configuration to get rid two "FAILED" error messages during systemd startup. Signed-off-by:
Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org> --- v2: provide a more descriptive changelog
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- Nov 02, 2016
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Alan Tull authored
This patch enables the following in the socfpga_defconfig: +CONFIG_OF_OVERLAY=y Enable support for Device Tree Overlays +CONFIG_FPGA_REGION=y Enable device tree overlay support for FPGA programming +CONFIG_FPGA_MGR_SOCFPGA_A10=y Enable partial reconfiguration for Altera Arria 10 FPGA +CONFIG_FPGA_BRIDGE=y Enable the FPGA Bridges framework +CONFIG_SOCFPGA_FPGA_BRIDGE=y Enable support for SoCFPGA hardware bridges +CONFIG_ALTERA_FREEZE_BRIDGE=y Enable support for the Altera Soft IP Freeze bridges Signed-off-by:
Alan Tull <atull@opensource.altera.com>
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- Oct 25, 2016
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Dinh Nguyen authored
All of the SoCFPGA boards have at least 1GB of RAM, so enabling HIGHMEM is necessary to avoid the following warning: [ 0.000000] Truncating RAM at 0x00000000-0x40000000 to -0x30000000 [ 0.000000] Consider using a HIGHMEM enabled kernel. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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- Oct 18, 2016
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Steffen Trumtrar authored
Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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- Jun 20, 2016
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Dinh Nguyen authored
Enable the PL330 DMA and DMATEST on SoCFPGA. make savedefconfig says CONFIG_FHANDLE is not needed in the defconfig, remove it. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Also enable DMATEST as a kernel module
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Ley Foon Tan authored
Enable Altera PCIe host driver, Altera MSI driver and PCIe devices. CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCIE_ALTERA=y CONFIG_PCIE_ALTERA_MSI=y CONFIG_BLK_DEV_NVME=m CONFIG_E1000E=m CONFIG_IGB=m CONFIG_IXGBE=m Signed-off-by:
Ley Foon Tan <lftan@altera.com> Signed-off-by:
Tien Hock Loh <thloh@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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- Jun 14, 2016
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Marek Vasut authored
Enable the following bits: CONFIG_TOUCHSCREEN_STMPE - STMPE touchscreen support, needed on MCVEVK as it contains the chip. This also enables the STMPE MFD device and touchscreen input support. CONFIG_USB_STORAGE - USB storage support is often used, so enable it. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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- Feb 19, 2016
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Dinh Nguyen authored
Enable CONFIG_BLK_DEV_INITRD. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by:
Kevin Hilman <khilman@baylibre.com>
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- Dec 03, 2015
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Dinh Nguyen authored
Enable USB OTG dual-role and a bit of clean up by using make savedefconfig. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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- Oct 13, 2015
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Alan Tull authored
Enable fpga manager framework and low level driver for socfpga in socfpga_defconfig Signed-off-by:
Alan Tull <atull@opensource.altera.com> Reviewed-by:
Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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- Oct 24, 2014
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Dinh Nguyen authored
Clean up the socfpga_defconfig file by doing: make socfpga_defconfig make make savedefconfig Then add the following to socfpga_defconfig: CONFIG_SIGNALFD=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_SRAM=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_CONFIGFS_FS=y CONFIG_PMBUS=y CONFIG_SENSORS_PMBUS=y CONFIG_SENSORS_LTC2978=y CONFIG_SENSORS_LTC2978_REGULATOR=y CONFIG_PRINTK_TIME=y CONFIG_EXT4_FS=y Signed-off-by:
Thor Thayer <tthayer@opensource.altera.com> Signed-off-by:
Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by:
Alan Tull <atull@opensource.altera.com> Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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- Jul 15, 2014
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Vince Bridgers authored
CONFIG_PM=y CONFIG_SUSPEND=y CONFIG_MMC_UNSAFE_RESUME=y CONFIG_DWMAC_SOCFPGA=y CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_DWC2_HOST=y CONFIG_USB_DWC2_PLATFORM=y CONFIG_FHANDLE=y CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_CORE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_CHARDEV=y CONFIG_CAN=y CONFIG_CAN_RAW=y CONFIG_CAN_BCM=y CONFIG_CAN_GW=y CONFIG_CAN_DEV=y CONFIG_CAN_CALC_BITTIMING=y CONFIG_CAN_C_CAN=y CONFIG_CAN_C_CAN_PLATFORM=y CONFIG_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_DWAPB=y CONFIG_PPS=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_PTP_1588_CLOCK=y CONFIG_VLAN_8021Q=y CONFIG_VLAN_8021Q_GVRP=y CONFIG_GARP=y CONFIG_IPV6=y CONFIG_HOTPLUG=y Signed-off-by:
Vince Bridgers <vbridgers2013@gmail.com> Signed-off-by:
Alan Tull <atull@altera.com> Signed-off-by:
Thor Thayer <tthayer@altera.com> Signed-off-by:
Dinh Nguyen <dinguyen@altear.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Mar 02, 2014
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Dinh Nguyen authored
CONFIG_MICREL_PHY=y CONFIG_EXT3_FS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_MMC=y CONFIG_MMC_DW=y Signed-off-by:
Dinh Nguyen <dinguyen@altera.com>
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- Oct 26, 2012
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Dinh Nguyen authored
Enable SMP for the SOCFPGA platform. Signed-off-by:
Pavel Machek <pavel@denx.de> Signed-off-by:
Dinh Nguyen <dinguyen@altera.com> Reviewed-by:
Rob Herring <rob.herring@calxeda.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Jul 19, 2012
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Dinh Nguyen authored
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by:
Dinh Nguyen <dinguyen@altera.com> Reviewed-by:
Pavel Machek <pavel@denx.de> Reviewed-by:
Rob Herring <rob.herring@calxeda.com> Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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