RISC-V: Atomic and Locking Code
This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Reviewed-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Palmer Dabbelt <palmer@dabbelt.com>
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- arch/riscv/include/asm/atomic.h 375 additions, 0 deletionsarch/riscv/include/asm/atomic.h
- arch/riscv/include/asm/barrier.h 68 additions, 0 deletionsarch/riscv/include/asm/barrier.h
- arch/riscv/include/asm/bitops.h 218 additions, 0 deletionsarch/riscv/include/asm/bitops.h
- arch/riscv/include/asm/cacheflush.h 39 additions, 0 deletionsarch/riscv/include/asm/cacheflush.h
- arch/riscv/include/asm/cmpxchg.h 134 additions, 0 deletionsarch/riscv/include/asm/cmpxchg.h
- arch/riscv/include/asm/io.h 303 additions, 0 deletionsarch/riscv/include/asm/io.h
- arch/riscv/include/asm/spinlock.h 165 additions, 0 deletionsarch/riscv/include/asm/spinlock.h
- arch/riscv/include/asm/spinlock_types.h 33 additions, 0 deletionsarch/riscv/include/asm/spinlock_types.h
- arch/riscv/include/asm/tlb.h 24 additions, 0 deletionsarch/riscv/include/asm/tlb.h
- arch/riscv/include/asm/tlbflush.h 64 additions, 0 deletionsarch/riscv/include/asm/tlbflush.h
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