clk: tegra: Fix xusb_hs_src clock hierarchy
Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by:Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
Showing
- drivers/clk/tegra/clk-id.h 1 addition, 0 deletionsdrivers/clk/tegra/clk-id.h
- drivers/clk/tegra/clk-tegra-periph.c 6 additions, 0 deletionsdrivers/clk/tegra/clk-tegra-periph.c
- drivers/clk/tegra/clk-tegra114.c 5 additions, 10 deletionsdrivers/clk/tegra/clk-tegra114.c
- drivers/clk/tegra/clk-tegra124.c 5 additions, 10 deletionsdrivers/clk/tegra/clk-tegra124.c
- include/dt-bindings/clock/tegra114-car.h 2 additions, 1 deletioninclude/dt-bindings/clock/tegra114-car.h
- include/dt-bindings/clock/tegra124-car.h 2 additions, 1 deletioninclude/dt-bindings/clock/tegra124-car.h
Please register or sign in to comment