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Commit fb6f54ec authored by Robert Nelson's avatar Robert Nelson
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merge: overlays form 6.6.x


Signed-off-by: default avatarRobert Nelson <robertcnelson@gmail.com>
parent 2baa4268
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
/*
* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
&{/chosen} {
overlays {
AM335X-PRU-UIO-00A0.kernel = __TIMESTAMP__;
};
};
&pruss_tm {
status = "okay";
};
&pruss {
compatible = "ti,pruss-v2";
ti,pintc-offset = <0x20000>;
interrupt-parent = <&intc>;
interrupts = <20 21 22 23 24 25 26 27>;
};
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/*
* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
&{/chosen} {
overlays {
AM57XX-PRU-UIO-00A0.kernel = __TIMESTAMP__;
};
};
&pruss1_tm {
status = "okay";
};
&pruss1 {
compatible = "ti,pruss-v2";
ti,pintc-offset = <0x20000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
pruss-instance = "pruss1";
};
&pruss2_tm {
status = "okay";
};
&pruss2 {
compatible = "ti,pruss-v2";
ti,pintc-offset = <0x20000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
pruss-instance = "pruss2";
};
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
/*
* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
&{/chosen} {
overlays {
BB-ADC-00A0.kernel = __TIMESTAMP__;
};
};
&tscadc {
status = "okay";
adc {
// Configure one or more (up to 8) steps for the adc to execute:
// For each step, the channel to sample.
// range: 0 .. 7
ti,adc-channels = <0 1 2 3 4 5 6 7>;
//
// BeagleBone Black (and most other variants):
// ch 0 P9.39
// ch 1 P9.40
// ch 2 P9.37
// ch 3 P9.38
// ch 4 P9.33
// ch 5 P9.36
// ch 6 P9.35
// ch 7 measures 0.5 * VDD_3V3B with 2.4 kΩ source impedance
//
// PocketBeagle:
// ch 0 P1.19
// ch 1 P1.21
// ch 2 P1.23
// ch 3 P1.25
// ch 4 P1.27
// ch 5 P2.35 via 10k/10k voltage divider
// ch 6 P1.02 via 10k/10k voltage divider
// ch 7 P2.36 via pmic mux
//
// The divider used on PocketBeagle channels 5 and 6 makes the effective voltage V_eff and
// source impedance Z_eff seen by the adc on these channels depend on the voltage V_src and
// impedance Z_src of the source connected to the corresponding pin as follows:
//
// V_eff = V_src / (2 + Z_src / (10 kΩ))
// Z_eff = 5 kΩ * (1 + Z_src / (Z_src + 20 kΩ))
// ≈ 5 kΩ + Z_src / 4 for small values of Z_src (up to 2 kΩ or so)
// For each step, number of adc clock cycles to wait between setting up muxes and sampling.
// range: 0 .. 262143
// optional, default is 152 (XXX but why?!)
ti,chan-step-opendelay = <152 152 152 152 152 152 152 152>;
//`
// XXX is there any purpose to set this nonzero other than to fine-tune the sample rate?
// For each step, how many times it should sample to average.
// range: 1 .. 16, must be power of two (i.e. 1, 2, 4, 8, or 16)
// optional, default is 16
ti,chan-step-avg = <16 16 16 16 16 16 16 16>;
//
// If you're using periodic sampling (using the iio block device rather than sysfs) then
// you should consider setting this to 1 and if desired reduce the samplerate in userspace
// instead since averaging isn't a particularly good low-pass filter.
//
// If you're using sysfs to occasionally read a value, then the default value of 16 will
// still get you the most accurate readings.
// For each step, number of adc clock cycles to sample minus two.
// range: 0 .. 255 (resulting in sampling time of 2 .. 257 cycles)
// optional, default is 0
ti,chan-step-sampledelay = <0 0 0 0 0 0 0 0>;
//
// If this is set too low, accuracy will deteriorate when the thing you're measuring has a
// high source impedance. The maximum source impedance recommended (by erratum 1.0.32) is:
// (2 + sampledelay) * 2.873 kΩ - 0.2 kΩ
// which means that the default should be fine for source impedance up to 5.5 kΩ.
//
// (This seems to ensure the sampling time is at least 21 times the RC constant, based on
// the 5.5 pF nominal capacitance specified in the datasheet.)
// After sampling, conversion time is 13 adc clock cycles.
//
// The adc clock frequency is 3 MHz, therefore the total time per step in microseconds is:
// ( opendelay + avg * ( 2 + sampledelay + 13 ) ) / 3
//
// If all steps use the same timings then the sample rate will be:
// 3 MHz / ( opendelay + avg * ( 2 + sampledelay + 13 ) ) / number_of_steps
//
// The highest samplerate obtainable (avg=1, opendelay=0, sampledelay=0) is therefore:
// 200 kHz / number_of_steps
// = 25 kHz when using all 8 steps.
//
// Using avg=16 reduces that to:
// 12.5 kHz / number_of_steps
// = 1.5625 kHz when using all 8 steps.
//
// Using the default values (avg=16, opendelay=152, sampledelay=0) reduces that to:
// 7.653 kHz / number_of_steps
// = 0.9566 kHz when using all 8 steps.
};
};
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
/*
* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
&{/chosen} {
overlays {
BB-BONE-eMMC1-01-00A0.kernel = __TIMESTAMP__;
};
};
/*
* Free up the pins used by the cape from the pinmux helpers.
*/
&ocp {
P8_21_pinmux { status = "disabled"; }; /* mmc1_clk */
P8_20_pinmux { status = "disabled"; }; /* mmc1_cmd */
P8_25_pinmux { status = "disabled"; }; /* mmc1_dat0 */
P8_24_pinmux { status = "disabled"; }; /* mmc1_dat1 */
P8_05_pinmux { status = "disabled"; }; /* mmc1_dat2 */
P8_06_pinmux { status = "disabled"; }; /* mmc1_dat3 */
P8_23_pinmux { status = "disabled"; }; /* mmc1_dat4 */
P8_22_pinmux { status = "disabled"; }; /* mmc1_dat5 */
P8_03_pinmux { status = "disabled"; }; /* mmc1_dat6 */
P8_04_pinmux { status = "disabled"; }; /* mmc1_dat7 */
};
&am33xx_pinmux {
emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>;
};
};
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
status = "okay";
non-removable;
};
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012,2019 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2015 Robert Nelson <robertcnelson@gmail.com>
* Copyright (C) 2015 Sebastian Jegerås
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/gpio/gpio.h>
/*
* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
&{/chosen} {
overlays {
BBORG_COMMS-00A2.kernel = __TIMESTAMP__;
};
};
/*
* Free up the pins used by the cape from the pinmux helpers.
*/
&ocp {
P9_24_pinmux { status = "disabled"; }; /* P9_24: uart1_txd.d_can1_rx */
P9_26_pinmux { status = "disabled"; }; /* P9_26: uart1_rxd.d_can1_tx */
P9_13_pinmux { status = "disabled"; }; /* P9_13: gpmc_wpn.uart4_txd_mux2 */
P9_11_pinmux { status = "disabled"; }; /* P9_11: gpmc_wait0.uart4_rxd_mux2 */
};
&bone_can_1 {
status = "okay";
};
&bone_uart_4 {
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 Deepak Khatri <deepaklorkhatri7@gmail.com>
* See Cape Interface Spec page for more info on Bone Buses
* https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
*
* Virtual cape for Bone ADC
*/
/dts-v1/;
/plugin/;
/*
* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
*/
&{/chosen} {
overlays {
BONE-ADC.kernel = __TIMESTAMP__;
};
};
/*
* See these files for the phandles (&bone_*) and other bone bus nodes
* am335x-bbb-bone-buses.dtsi
*/
&bone_adc {
status = "okay";
};
......@@ -4,6 +4,7 @@
* Copyright (C) 2021 Robert Nelson <robertcnelson@gmail.com>
* See Cape Interface Spec page for more info on Bone Buses
* https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
* https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html
*/
#include <dt-bindings/gpio/gpio.h>
......@@ -21,60 +22,17 @@
// For compatible bone pinmuxing
bone_pinmux: &am33xx_pinmux {
emmc_pins: emmc-pins {
bborg_comms_can_pins: pinmux_comms_can_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* P9_24: uart1_txd.d_can1_rx */
0x180 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* P9_26: uart1_rxd.d_can1_tx */
>;
};
nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins {
bborg_comms_rs485_pins: pinmux_comms_rs485_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
>;
};
nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
>;
};
mcasp0_pins: mcasp0_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
0x074 (PIN_OUTPUT | MUX_MODE6) /* P9_13: gpmc_wpn.uart4_txd_mux2 */
0x070 (PIN_INPUT | MUX_MODE6) /* P9_11: gpmc_wait0.uart4_rxd_mux2 */
>;
};
};
......@@ -83,3 +41,29 @@ bone_pinmux: &am33xx_pinmux {
bone_adc: &tscadc {
};
// CAN
// https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#can
bone_can_1: &dcan1 {
symlink = "bone/can/1";
status = "disabled";
pinctrl-names = "default";
// pinctrl-0 = <
// &P9_26_can_pin /* tx */
// &P9_24_can_pin /* rx */
// >;
pinctrl-0 = <&bborg_comms_can_pins>;
};
// UART
// https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#uart
bone_uart_4: &uart4 {
symlink = "bone/uart/4";
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&bborg_comms_rs485_pins>;
//rs485-rts-delay = <0 0>;
//rts-gpio = <&gpio3 19 1>; /* GPIO_ACTIVE_HIGH>; */
//rs485-rts-active-high;
//linux,rs485-enabled-at-boot-time;
};
\ No newline at end of file
......@@ -3,6 +3,8 @@
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am335x-bbb-bone-buses.dtsi"
/ {
cpus {
cpu@0 {
......
......@@ -17,3 +17,151 @@
base_dtb_timestamp = __TIMESTAMP__;
};
};
&gpio0 {
gpio-line-names =
"[mdio_data]",
"[mdio_clk]",
"P9_22 [spi0_sclk]",
"P9_21 [spi0_d0]",
"P9_18 [spi0_d1]",
"P9_17 [spi0_cs0]",
"[mmc0_cd]",
"P9_42A [ecappwm0]",
"P8_35 [lcd d12]",
"P8_33 [lcd d13]",
"P8_31 [lcd d14]",
"P8_32 [lcd d15]",
"P9_20 [i2c2_sda]",
"P9_19 [i2c2_scl]",
"P9_26 [uart1_rxd]",
"P9_24 [uart1_txd]",
"[rmii1_txd3]",
"[rmii1_txd2]",
"[usb0_drvvbus]",
"[hdmi cec]",
"P9_41B",
"[rmii1_txd1]",
"P8_19 [ehrpwm2a]",
"P8_13 [ehrpwm2b]",
"NC",
"NC",
"P8_14",
"P8_17",
"[rmii1_txd0]",
"[rmii1_refclk]",
"P9_11 [uart4_rxd]",
"P9_13 [uart4_txd]";
};
&gpio1 {
gpio-line-names =
"P8_25 [mmc1_dat0]",
"[mmc1_dat1]",
"P8_5 [mmc1_dat2]",
"P8_6 [mmc1_dat3]",
"P8_23 [mmc1_dat4]",
"P8_22 [mmc1_dat5]",
"P8_3 [mmc1_dat6]",
"P8_4 [mmc1_dat7]",
"NC",
"NC",
"NC",
"NC",
"P8_12",
"P8_11",
"P8_16",
"P8_15",
"P9_15A",
"P9_23",
"P9_14 [ehrpwm1a]",
"P9_16 [ehrpwm1b]",
"[emmc rst]",
"[usr0 led]",
"[usr1 led]",
"[usr2 led]",
"[usr3 led]",
"[hdmi irq]",
"[usb vbus oc]",
"[hdmi audio]",
"P9_12",
"P8_26",
"P8_21 [emmc]",
"P8_20 [emmc]";
};
&gpio2 {
gpio-line-names =
"P9_15B",
"P8_18",
"P8_7",
"P8_8",
"P8_10",
"P8_9",
"P8_45",
"P8_46",
"P8_43",
"P8_44",
"P8_41",
"P8_42",
"P8_39",
"P8_40",
"P8_37",
"P8_38",
"P8_36",
"P8_34",
"[rmii1_rxd3]",
"[rmii1_rxd2]",
"[rmii1_rxd1]",
"[rmii1_rxd0]",
"P8_27",
"P8_29",
"P8_28",
"P8_30",
"[mmc0_dat3]",
"[mmc0_dat2]",
"[mmc0_dat1]",
"[mmc0_dat0]",
"[mmc0_clk]",
"[mmc0_cmd]";
};
&gpio3 {
gpio-line-names =
"[mii col]",
"[mii crs]",
"[mii rx err]",
"[mii tx en]",
"[mii rx dv]",
"[i2c0 sda]",
"[i2c0 scl]",
"[jtag emu0]",
"[jtag emu1]",
"[mii tx clk]",
"[mii rx clk]",
"NC",
"NC",
"[usb vbus en]",
"P9_31 [spi1_sclk]",
"P9_29 [spi1_d0]",
"P9_30 [spi1_d1]",
"P9_28 [spi1_cs0]",
"P9_42B [ecappwm0]",
"P9_27",
"P9_41A",
"P9_25",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC";
};
&baseboard_eeprom {
vcc-supply = <&ldo4_reg>;
};
......@@ -854,7 +854,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x300000 0x80000>;
status = "disabled";
status = "okay";
pruss: pruss@0 {
compatible = "ti,am3356-pruss";
......
......@@ -644,6 +644,11 @@
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
gpu: gpu@0 {
compatible = "ti,am3352-sgx530", "img,sgx530";
reg = <0x0 0x10000>;
interrupts = <37>;
};
};
};
};
......
......@@ -856,6 +856,12 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
gpu: gpu@0 {
compatible = "ti,dra7-sgx544", "img,sgx544";
reg = <0x0 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
};
};
crossbar_mpu: crossbar@4a002a48 {
......
......@@ -170,6 +170,12 @@
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
sgx: gpu@0 {
compatible = "ti,omap3530-sgx530", "img,sgx530";
reg = <0x0 0x10000>; /* 64kB */
interrupts = <21>;
};
};
};
......
......@@ -505,6 +505,12 @@
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
gpu@0 {
compatible = "ti,omap4430-sgx540", "img,sgx540";
reg = <0x0 0x2000000>; /* 32MB */
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
};
/*
......
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