sources/FPGA-design/script_support/components/CAPE/DEFAULT/CoreAPB3_CAPE.tcl

+# Exporting Component Description of CoreAPB3_CAPE to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreAPB3_CAPE
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
+"APB_DWIDTH:32"  \
+"APBSLOT0ENABLE:true"  \
+"APBSLOT1ENABLE:true"  \
+"APBSLOT2ENABLE:true"  \
+"APBSLOT3ENABLE:false"  \
+"APBSLOT4ENABLE:true"  \
+"APBSLOT5ENABLE:true"  \
+"APBSLOT6ENABLE:false"  \
+"APBSLOT7ENABLE:false"  \
+"APBSLOT8ENABLE:false"  \
+"APBSLOT9ENABLE:false"  \
+"APBSLOT10ENABLE:false"  \
+"APBSLOT11ENABLE:false"  \
+"APBSLOT12ENABLE:false"  \
+"APBSLOT13ENABLE:false"  \
+"APBSLOT14ENABLE:false"  \
+"APBSLOT15ENABLE:false"  \
+"IADDR_OPTION:0"  \
+"MADDR_BITS:24"  \
+"SC_0:false"  \
+"SC_1:false"  \
+"SC_2:false"  \
+"SC_3:false"  \
+"SC_4:false"  \
+"SC_5:false"  \
+"SC_6:false"  \
+"SC_7:false"  \
+"SC_8:false"  \
+"SC_9:false"  \
+"SC_10:false"  \
+"SC_11:false"  \
+"SC_12:false"  \
+"SC_13:false"  \
+"SC_14:false"  \
+"SC_15:false"  \
+"UPR_NIBBLE_POSN:5"   }
+# Exporting Component Description of CoreAPB3_CAPE to TCL done

script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HSIO_CoreGPIO_C0.tcl → sources/FPGA-design/script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl

-# Exporting Component Description of HSIO_CoreGPIO_C0 to TCL
+# Exporting Component Description of CoreGPIO_P8_UPPER to TCL
 # Family: PolarFireSoC
 # Part Number: MPFS025T-FCVG484E
-# Create and Configure the core component HSIO_CoreGPIO_C0
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {HSIO_CoreGPIO_C0} -params {\
+# Create and Configure the core component CoreGPIO_P8_UPPER
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_P8_UPPER} -params {\
 "APB_WIDTH:32"  \
 "FIXED_CONFIG_0:true"  \
 "FIXED_CONFIG_1:true"  \
@@ -86,10 +86,10 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
 "IO_TYPE_13:2"  \
 "IO_TYPE_14:2"  \
 "IO_TYPE_15:2"  \
-"IO_TYPE_16:0"  \
-"IO_TYPE_17:0"  \
-"IO_TYPE_18:0"  \
-"IO_TYPE_19:0"  \
+"IO_TYPE_16:2"  \
+"IO_TYPE_17:2"  \
+"IO_TYPE_18:2"  \
+"IO_TYPE_19:2"  \
 "IO_TYPE_20:0"  \
 "IO_TYPE_21:0"  \
 "IO_TYPE_22:0"  \
@@ -135,4 +135,4 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
 "IO_VAL_30:0"  \
 "IO_VAL_31:0"  \
 "OE_TYPE:0"   }
-# Exporting Component Description of HSIO_CoreGPIO_C0 to TCL done
+# Exporting Component Description of CoreGPIO_P8_UPPER to TCL done

script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl → sources/FPGA-design/script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl

-# Exporting Component Description of CoreGPIO_LCD to TCL
+# Exporting Component Description of CoreGPIO_P9 to TCL
 # Family: PolarFireSoC
 # Part Number: MPFS025T-FCVG484E
-# Create and Configure the core component CoreGPIO_LCD
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_LCD} -params {\
+# Create and Configure the core component CoreGPIO_P9
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_P9} -params {\
 "APB_WIDTH:32"  \
 "FIXED_CONFIG_0:true"  \
 "FIXED_CONFIG_1:true"  \
@@ -24,7 +24,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
 "FIXED_CONFIG_17:true"  \
 "FIXED_CONFIG_18:true"  \
 "FIXED_CONFIG_19:true"  \
-"FIXED_CONFIG_20:false"  \
+"FIXED_CONFIG_20:true"  \
 "FIXED_CONFIG_21:false"  \
 "FIXED_CONFIG_22:false"  \
 "FIXED_CONFIG_23:false"  \
@@ -69,7 +69,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
 "IO_INT_TYPE_29:7"  \
 "IO_INT_TYPE_30:7"  \
 "IO_INT_TYPE_31:7"  \
-"IO_NUM:24"  \
+"IO_NUM:21"  \
 "IO_TYPE_0:2"  \
 "IO_TYPE_1:2"  \
 "IO_TYPE_2:2"  \
@@ -90,7 +90,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
 "IO_TYPE_17:2"  \
 "IO_TYPE_18:2"  \
 "IO_TYPE_19:2"  \
-"IO_TYPE_20:0"  \
+"IO_TYPE_20:2"  \
 "IO_TYPE_21:0"  \
 "IO_TYPE_22:0"  \
 "IO_TYPE_23:0"  \
@@ -135,4 +135,4 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
 "IO_VAL_30:0"  \
 "IO_VAL_31:0"  \
 "OE_TYPE:0"   }
-# Exporting Component Description of CoreGPIO_LCD to TCL done
+# Exporting Component Description of CoreGPIO_P9 to TCL done

sources/FPGA-design/script_support/components/CAPE/DEFAULT/Readme.md

+#  Default Cape
+
+## P8 Header
+
+| Signal | Control                    | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P8_1   | n/a                        |  n/a  | GND         |
+| P8_2   | n/a                        |  n/a  | GND         |
+| P8_3   | MSS GPIO_2[0]              |   53  | User LED 0  |
+| P8_4   | MSS GPIO_2[1]              |   53  | User LED 1  |
+| P8_5   | MSS GPIO_2[2]              |   53  | User LED 2  |
+| P8_6   | MSS GPIO_2[3]              |   53  | User LED 3  |
+| P8_7   | MSS GPIO_2[4]              |   53  | User LED 4  |
+| P8_8   | MSS GPIO_2[5]              |   53  | User LED 5  |
+| P8_9   | MSS GPIO_2[6]              |   53  | User LED 6  |
+| P8_10  | MSS GPIO_2[7]              |   53  | User LED 7  |
+| P8_11  | MSS GPIO_2[8]              |   53  | User LED 8  |
+| P8_12  | MSS GPIO_2[9]              |   53  | User LED 9  |
+| P8_13  | core_pwm[1] @ 0x41500000   |  n/a  | PWM_2:1     |
+| P8_14  | MSS GPIO_2[11]             |   53  | User LED 11 |
+| P8_15  | MSS GPIO_2[12]             |   53  | GPIO        |
+| P8_16  | MSS GPIO_2[13]             |   53  | GPIO        |
+| P8_17  | MSS GPIO_2[14]             |   53  | GPIO        |
+| P8_18  | MSS GPIO_2[15]             |   53  | GPIO        |
+| P8_19  | core_pwm[0] @ 0x41500000   |  n/a  | PWM_2:0     |
+| P8_20  | MSS GPIO_2[17]             |   53  | GPIO        |
+| P8_21  | MSS GPIO_2[18]             |   53  | GPIO        |
+| P8_22  | MSS GPIO_2[19]             |   53  | GPIO        |
+| P8_23  | MSS GPIO_2[20]             |   53  | GPIO        |
+| P8_24  | MSS GPIO_2[21]             |   53  | GPIO        |
+| P8_25  | MSS GPIO_2[22]             |   53  | GPIO        |
+| P8_26  | MSS GPIO_2[23]             |   53  | GPIO        |
+| P8_27  | MSS GPIO_2[24]             |   53  | GPIO        |
+| P8_28  | MSS GPIO_2[25]             |   53  | GPIO        |
+| P8_29  | MSS GPIO_2[26]             |   53  | GPIO        |
+| P8_30  | MSS GPIO_2[27]             |   53  | GPIO        |
+| P8_31  | core_gpio[0] @ 0x41100000  |  126  | GPIO        |
+| P8_32  | core_gpio[1] @ 0x41100000  |  127  | GPIO        |
+| P8_33  | core_gpio[2] @ 0x41100000  |  128  | GPIO        |
+| P8_34  | core_gpio[3] @ 0x41100000  |  129  | GPIO        |
+| P8_35  | core_gpio[4] @ 0x41100000  |  130  | GPIO        |
+| P8_36  | core_gpio[5] @ 0x41100000  |  131  | GPIO        |
+| P8_37  | core_gpio[6] @ 0x41100000  |  132  | GPIO        |
+| P8_38  | core_gpio[7] @ 0x41100000  |  133  | GPIO        |
+| P8_39  | core_gpio[8] @ 0x41100000  |  134  | GPIO        |
+| P8_40  | core_gpio[9] @ 0x41100000  |  135  | GPIO        |
+| P8_41  | core_gpio[10] @ 0x41100000 |  136  | GPIO        |
+| P8_42  | core_gpio[11] @ 0x41100000 |  137  | GPIO        |
+| P8_43  | core_gpio[12] @ 0x41100000 |  138  | GPIO        |
+| P8_44  | core_gpio[13] @ 0x41100000 |  139  | GPIO        |
+| P8_45  | core_gpio[14] @ 0x41100000 |  140  | GPIO        |
+| P8_46  | core_gpio[15] @ 0x41100000 |  141  | GPIO        |
+
+## P9 Header
+
+| Signal | Control                    | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P9_1   | n/a                        |  n/a  | GND         |
+| P9_2   | n/a                        |  n/a  | GND         |
+| P9_3   | n/a                        |  n/a  | VCC 3.3V    |
+| P9_4   | n/a                        |  n/a  | VCC 3.3V    |
+| P9_5   | n/a                        |  n/a  | VDD 5V      |
+| P9_6   | n/a                        |  n/a  | VDD 5V      |
+| P9_7   | n/a                        |  n/a  | SYS 5V      |
+| P9_8   | n/a                        |  n/a  | SYS 5V      |
+| P9_9   | n/a                        |  n/a  | NC          |
+| P9_10  | n/a                        |  n/a  | SYS_RSTN    |
+| P9_11  | MMUART4                    |   94  | UART4 RX    |
+| P9_12  | core_gpio[1] @ 0x41200000  |  143  | GPIO        |
+| P9_13  | MMUART4                    |   94  | UART4 TX    |
+| P9_14  | core_pwm[0] @ 0x41400000   |  n/a  | PWM_1:0     |
+| P9_15  | core_gpio[4] @ 0x41200000  |  146  | GPIO        |
+| P9_16  | core_pwm[1] @ 0x41400000   |  n/a  | PWM_1:1     |
+| P9_17  | MSS SPI0                   |   54  | SPI0 CS     |
+| P9_18  | MSS SPI0                   |   54  | SPI0 DI     |
+| P9_19  | MSS I2C0                   |   58  | I2C0 SCL    |
+| P9_20  | MSS I2C0                   |   58  | I2C0 SDA    |
+| P9_21  | MSS SPI0                   |   54  | SPI0 DO     |
+| P9_22  | MSS SPI0                   |   54  | SPI0 SCLK   |
+| P9_23  | core_gpio[10] @ 0x41200000 |  152  | GPIO        |
+| P9_24  | MMUART2                    |   92  | UART1 TX    |
+| P9_25  | core_gpio[12] @ 0x41200000 |  154  | GPIO        |
+| P9_26  | MMUART2                    |   92  | UART2 RX    |
+| P9_27  | core_gpio[14] @ 0x41200000 |  156  | GPIO        |
+| P9_28  | MSS SPI1                   |   55  | SPI1 CS     |
+| P9_29  | MSS SPI1                   |   55  | SPI1 DO     |
+| P9_30  | core_gpio[17] @ 0x41200000 |  159  | GPIO        |
+| P9_31  | MSS SPI1                   |   55  | SPI1 SCLK   |
+| P9_32  | n/a                        |  n/a  | VDD ADC     |
+| P9_33  | n/a                        |  n/a  | ADC input 4 |
+| P9_34  | n/a                        |  n/a  | AGND        |
+| P9_35  | n/a                        |  n/a  | ADC input 6 |
+| P9_36  | n/a                        |  n/a  | ADC input 5 |
+| P9_37  | n/a                        |  n/a  | ADC input 2 |
+| P9_38  | n/a                        |  n/a  | ADC input 3 |
+| P9_39  | n/a                        |  n/a  | ADC input 0 |
+| P9_40  | n/a                        |  n/a  | ADC input 1 |
+| P9_41  | core_gpio[19] @ 0x41200000 |  161  | GPIO        |
+| P9_42  | core_pwm[0] @ 0x41000000   |  n/a  | PWM_0:0     |
+| P9_43  | n/a                        |  n/a  | GND         |
+| P9_44  | n/a                        |  n/a  | GND         |
+| P9_45  | n/a                        |  n/a  | GND         |
+| P9_46  | n/a                        |  n/a  | GND         |

sources/FPGA-design/script_support/components/CAPE/GPIOS/CoreAPB3_CAPE.tcl

+# Exporting Component Description of CoreAPB3_CAPE to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreAPB3_CAPE
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
+"APB_DWIDTH:32"  \
+"APBSLOT0ENABLE:true"  \
+"APBSLOT1ENABLE:true"  \
+"APBSLOT2ENABLE:true"  \
+"APBSLOT3ENABLE:false"  \
+"APBSLOT4ENABLE:true"  \
+"APBSLOT5ENABLE:true"  \
+"APBSLOT6ENABLE:false"  \
+"APBSLOT7ENABLE:false"  \
+"APBSLOT8ENABLE:false"  \
+"APBSLOT9ENABLE:false"  \
+"APBSLOT10ENABLE:false"  \
+"APBSLOT11ENABLE:false"  \
+"APBSLOT12ENABLE:false"  \
+"APBSLOT13ENABLE:false"  \
+"APBSLOT14ENABLE:false"  \
+"APBSLOT15ENABLE:false"  \
+"IADDR_OPTION:0"  \
+"MADDR_BITS:24"  \
+"SC_0:false"  \
+"SC_1:false"  \
+"SC_2:false"  \
+"SC_3:false"  \
+"SC_4:false"  \
+"SC_5:false"  \
+"SC_6:false"  \
+"SC_7:false"  \
+"SC_8:false"  \
+"SC_9:false"  \
+"SC_10:false"  \
+"SC_11:false"  \
+"SC_12:false"  \
+"SC_13:false"  \
+"SC_14:false"  \
+"SC_15:false"  \
+"UPR_NIBBLE_POSN:5"   }
+# Exporting Component Description of CoreAPB3_CAPE to TCL done