debian/compat

+10

debian/control

+Source: bbb.io-gateware
+Section: misc
+Priority: extra
+Maintainer: Robert Nelson <robertcnelson@gmail.com>
+Build-Depends:
+ debhelper (>= 10)
+Standards-Version: 4.5.1
+
+Package: bbb.io-gateware
+Architecture: all
+Depends:
+ ${shlibs:Depends}
+ , ${misc:Depends}
+ , mtd-utils
+Description: bbb.io-gateware
+ bbb.io-gateware

debian/mcp356x_read.py

+#!/bin/env python3
+
+#
+# This script is intended to be run with python 3
+#
+
+import time
+import os
+import re
+import subprocess
+import functools
+
+voltage_raws = []
+
+voltage_differential_raws = []
+
+voltage_scales = [ "in_voltage-voltage_scale" ]
+
+hw_gain = [ "hardwaregain" ]
+
+hw_gain_available = [ hw_gain[0] + "_available" ]
+
+calib_bias = [ "calibbias" ]
+
+calib_bias_available = [ calib_bias[0] + "_available" ]
+
+calib_scale = [ "calibscale" ]
+
+calib_scale_available = [ calib_scale[0] + "_available" ]
+
+oversampling_ratio = [ "oversampling_ratio" ]
+
+oversampling_ratio_available = [ oversampling_ratio[0] + "_available" ]
+temperature_raws = [ "in_temp_raw" ]
+
+temperature_scale = [ "in_temp_scale" ]
+
+DIR_PATH="/sys/bus/iio/devices/"
+device = []
+mcp_devices = []
+
+device2channels ={}
+
+
+new_line = '\n'
+
+def mult(file1_name, file2_name):
+    global ABS_PATH
+    file1 = open(ABS_PATH+file1_name,'r')
+    val1 = int(file1.read())
+    file1.close()
+    file2 = open(ABS_PATH+file2_name,'r')
+    val2 = float(file2.read())
+    file2.close()
+    return (val1 * val2)
+
+
+def print_attribute(file_name):
+    global ABS_PATH
+    attr_file = open(ABS_PATH + file_name,'r')
+    string = attr_file.read()
+    attr_file.close()
+    # clean the string for printing
+    string = string.replace("0000000", "")
+    return string
+
+def calculate_temperature(file1_name):
+    global ABS_PATH
+
+    name_file = open(ABS_PATH + "name",'r')
+    device_name_string = name_file.read()
+    name_file.close()
+
+    temperature = open(ABS_PATH+file1_name,'r')
+    temperature_val = int(temperature.read())
+    temperature.close()
+
+    if ( 'mcp3564\n' == device_name_string ):
+        return temperature_val * 4.0096 * 0.0001 * 2.4 - 269.13
+    else:
+        return 0
+
+def write_attribute(file_name, value):
+    global ABS_PATH
+    attr_file = open(ABS_PATH + file_name,'w')
+    attr_file.write(value)
+    attr_file.close()
+    return 0
+
+def get_name(file_name):
+    global ABS_PATH
+    attr_file = open(file_name,'r')
+    string = attr_file.read()
+    attr_file.close()
+    return string
+
+
+
+
+if not os.path.isdir(DIR_PATH):
+    print('IIO is not enabled')
+    exit()
+
+proc = subprocess.Popen("ls -1 " + DIR_PATH + "| grep device", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+stdout, stderr =  proc.communicate()
+
+lines = stdout.decode('utf-8').split('\n')
+
+print('Search for devices:')
+for line in lines:
+    path=DIR_PATH + line
+    if os.path.exists(path):
+        if os.path.exists(path + "/name"):
+            device_name= get_name(path + "/name")
+
+            print('------------->', device_name)
+
+            if re.search(r"mcp3[45]6[124][rR]", device_name):
+                device_index = re.findall(r'\d+', line)
+                if device_index:
+                    mcp_devices.append(device_index[0])
+
+                    # get voltage_raws*
+                    proc_channels = subprocess.Popen("ls -1 " + path + "/ | grep in_voltage* | grep -v scale | grep -v \"-\"", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+                    stdout_channels, stderr_channels =  proc_channels.communicate()
+                    voltage_raws = stdout_channels.decode('utf-8').split('\n')
+                    voltage_raws = voltage_raws[:-1]
+
+                    # get voltage_differential_raws
+                    proc_channels = subprocess.Popen("ls -1 " + path + "/ | grep in_voltage* | grep -v scale | grep \"-\"", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+                    stdout_channels, stderr_channels =  proc_channels.communicate()
+                    voltage_differential_raws = stdout_channels.decode('utf-8').split('\n')
+                    voltage_differential_raws = voltage_differential_raws[:-1]
+
+
+for mcp_device in mcp_devices:
+    ABS_PATH = f'{DIR_PATH}iio:device{mcp_device}/'
+
+    print('--------------------------------')
+    print('--------------------------------')
+    print('--------------------------------')
+    print(f'Device:  {print_attribute("name")}')
+    print('--------------------------------')
+
+    print(f'Available Voltage Oversampling Ratio:')
+    oversampling_ratio_string = print_attribute(oversampling_ratio_available[0])
+    oversampling_ratio_list = oversampling_ratio_string.split()
+    print(f'    {oversampling_ratio_string}')
+
+    print('--------------------------------')
+    print(f'Current Voltage Oversampling Ratio:  %s' % (print_attribute(oversampling_ratio[0])))
+    print('--------------------------------')
+
+    print(f'Available Voltage Hardware Gain:')
+    hw_gain_string = print_attribute(hw_gain_available[0])
+    hw_gain_list = hw_gain_string.split()
+    print(f'    {hw_gain_string}')
+
+    print('--------------------------------')
+    print(f'Current Voltage Hardware Gain:  %s' % (print_attribute(hw_gain[0])))
+    print('--------------------------------')
+
+    print(f'Available Voltage Calibration Bias {new_line} [    Low, Step, High  ] {new_line}  %s' % (print_attribute(calib_bias_available[0]).replace(" ", "  ")))
+
+    print('--------------------------------')
+    print(f'Current Voltage Calibration Bias:  %s' % (print_attribute(calib_bias[0])))
+    print('--------------------------------')
+
+    print(f'Available Voltage Calibration Scale {new_line}  [ Low, Step, High  ] {new_line}  %s' % (print_attribute(calib_scale_available[0]).replace(" ", "    ")))
+
+    print('--------------------------------')
+    print(f'Current Voltage Calibration Scale:  %s' % (print_attribute(calib_scale[0])))
+    print('--------------------------------')
+
+    print('--------------------------------')
+    # Measured voltage in millivolts
+    # U = in2_raw * in_scale
+
+    print('\n Voltage')
+    print('=========')
+
+    print(f'      Channel             V              mV')
+    for raw in voltage_raws:
+        # Voltage Scale is in mV
+        voltage_mv = mult(raw,voltage_scales[0])
+        voltage = voltage_mv/1000
+        print('---------------------------------------------------------------------')
+        print(f'    {raw}:    %2.4f   |   %5.6f' % (voltage, voltage_mv))
+
+    print('\n\n--------------------------------')
+
+
+    print('\n Differential Voltage')
+    print('======================')
+
+    print(f'            Channel                   V                   mV')
+    for raw in voltage_differential_raws:
+        # Voltage Scale is in mV
+        voltage_mv = mult(raw,voltage_scales[0])
+        voltage = voltage_mv/1000
+        print('---------------------------------------------------------------------')
+        print(f'    {raw}:    %8.4f     |  %15.6f' % (voltage, voltage_mv))
+
+    print('\n\n--------------------------------')
+    print('\n\n Temperature(',u'\xb0\x43','): %8.4f' % calculate_temperature(temperature_raws[0]))
+    print('\n\n--------------------------------')
+
+    if os.geteuid()==0:
+        print('\n\n================================')
+        print ('Running as root.')
+        print('================================\n\n')
+
+        # Testing Hardware Gain
+        current_hw_gain = print_attribute(hw_gain[0])
+        print(f'   Current Voltage Hardware Gain:    x{current_hw_gain}')
+
+
+        print('\n================================')
+        print(f'   Testing Hardware gain settings: {hw_gain_string}')
+        print('================================\n')
+        print('--------------------------------')
+
+        for hw_gain_value in hw_gain_list:
+            print(f' {new_line} Set Voltage Hardware Gain: x{hw_gain_value}')
+
+            write_attribute(hw_gain[0], hw_gain_value)
+
+            print(f'      Channel                       V              mV')
+            voltage_mv = mult(voltage_differential_raws[0], voltage_scales[0])
+            voltage = voltage_mv/1000
+            print('---------------------------------------------------------------------')
+            print(f'    {voltage_differential_raws[0]}:    %2.4f   |   %5.6f   -> Hw Gain: x%s' % (voltage, voltage_mv, print_attribute(hw_gain[0])))
+            print('---------------------------------------------------------------------------------------------------------------------')
+
+        # set back the Hardware Gain
+        write_attribute(hw_gain[0], current_hw_gain)
+        print('--------------------------------')
+
+        # Testing Oversampling Ratio
+        current_oversampling_ratio = print_attribute(oversampling_ratio[0])
+        print(f'   Current Oversampling Ratio:    x{current_oversampling_ratio}')
+
+        print(f' {new_line}')
+        print('\n================================')
+        print(f'   Testing Oversampling Ratio settings: {oversampling_ratio_string}')
+        print('================================\n')
+        print('--------------------------------')
+
+        for oversampling_ratio_value in oversampling_ratio_list:
+            print(f' {new_line} Set Oversampling Ratio: x{oversampling_ratio_value}')
+
+            write_attribute(oversampling_ratio[0], oversampling_ratio_value)
+
+            print(f'      Channel                       V              mV')
+            voltage_mv = mult(voltage_differential_raws[0], voltage_scales[0])
+            voltage = voltage_mv/1000
+            print('---------------------------------------------------------------------')
+            print(f'    {voltage_differential_raws[0]}:    %2.4f   |   %5.6f   -> Oversampling Ratio: x%s' % (voltage, voltage_mv, print_attribute(oversampling_ratio[0])))
+            print('---------------------------------------------------------------------------------------------------------------------')
+
+        # set back the Oversampling Ratio
+        write_attribute(oversampling_ratio[0], current_oversampling_ratio)
+        print('\n--------------------------------')
+
+        # Testing Calibration BIAS
+        current_calib_bias = print_attribute(calib_bias[0])
+        print(f'{new_line}   Current Calibration BIAS:    {current_calib_bias}')
+
+        print('\n\n================================')
+        print(f'   Testing Calibration Bias settings')
+        print('================================\n')
+        print('--------------------------------\n')
+
+        calib_bias_value = "50000"
+        print(f' {new_line} Set Calibration BIAS: {calib_bias_value}')
+
+        write_attribute(calib_bias[0], calib_bias_value)
+
+        print(f'      Channel                       V              mV')
+        voltage_mv = mult(voltage_differential_raws[0], voltage_scales[0])
+        voltage = voltage_mv/1000
+        print('---------------------------------------------------------------------')
+        print(f'    {voltage_differential_raws[0]}:    %2.4f   |   %5.6f   -> Calibration BIAS: %s' % (voltage, voltage_mv, print_attribute(calib_bias[0])))
+        print('---------------------------------------------------------------------------------------------------------------------')
+
+        # set back the Calibration Bias
+        write_attribute(calib_bias[0], "0")
+        print('\n--------------------------------')
+
+        # Testing Calibration Scale
+        calib_scale_x1_gain = 8388608
+
+        current_calib_scale = print_attribute(calib_scale[0])
+        print(f'{new_line}   Current Calibration Scale:    {int(current_calib_scale)/calib_scale_x1_gain}')
+
+        print('\n\n================================')
+        print(f'   Testing Calibration Scale settings')
+        print('================================\n')
+        print('--------------------------------')
+
+        calib_scale_value = 4194304;
+        print(f' {new_line} Set Calibration Scale: {calib_scale_value/calib_scale_x1_gain}')
+
+        write_attribute(calib_scale[0], str(calib_scale_value))
+
+        print(f'      Channel                       V              mV')
+        voltage_mv = mult(voltage_differential_raws[0], voltage_scales[0])
+        voltage = voltage_mv/1000
+        print('---------------------------------------------------------------------')
+        calib_scale_string = print_attribute(calib_scale[0])
+        calib_scale_int = int(calib_scale_string)
+        print(f'    {voltage_differential_raws[0]}:    %2.4f   |   %5.6f   -> Calibration Scale: x%2.6f' % (voltage, voltage_mv, calib_scale_int/calib_scale_x1_gain))
+        print('*********************************************************************************************************************')
+        print('*********************************************************************************************************************')
+        print('*********************************************************************************************************************')
+
+        # set back the Calibration Scale
+        write_attribute(calib_scale[0], str(calib_scale_x1_gain))
+
+    else:
+        print ('User is not root.\n')
+        print ('Changing the user configurable settings must by done by root user.\n')
\ No newline at end of file

debian/rules

+#!/usr/bin/make -f
+# See debhelper(7) (uncomment to enable)
+# output every command that modifies files on the build system.
+DH_VERBOSE = 1
+
+%:
+	dh $@
+
+override_dh_builddeb:
+	dh_builddeb -- -Zxz

debian/update-gateware.sh

+#!/bin/bash
+echo "================================================================================"
+echo "|                            FPGA Gateware Update                              |"
+echo "|                                                                              |"
+echo "|   Please ensure that the mpfs_bitstream.spi file containing the gateware     |"
+echo "|   update has been copied to directory /lib/firmware.                         |"
+echo "|                                                                              |"
+echo "|                 !!! This will take a couple of minutes. !!!                  |"
+echo "|                                                                              |"
+echo "|               Give the system a few minutes to reboot itself                 |"
+echo "|                        after Linux has shutdown.                             |"
+echo "|                                                                              |"
+echo "================================================================================"
+
+if [ ! -f /lib/firmware/mpfs_bitstream.spi ] ; then
+	echo "Missing: /lib/firmware/mpfs_bitstream.spi"
+	exit 2
+fi
+
+#read -rsp $'Press any key to continue...\n' -n1 key
+
+if [ ! -f /sys/kernel/debug/fpga/microchip_exec_update ] ; then
+	/usr/bin/mount -t debugfs none /sys/kernel/debug
+fi
+
+# Trash exisitng device tree overlay in case the rest of the process fails:
+/usr/sbin/mtd_debug erase /dev/mtd0 0x0 0x10000
+
+# Write device tree overlay
+dtbo_ls=$(ls -l /lib/firmware/mpfs_dtbo.spi)
+dtbo_size=$(echo $dtbo_ls | cut -d " "  -f 5)
+
+echo "Writing mpfs_dtbo.spi to /dev/mtd0"
+/usr/sbin/mtd_debug write /dev/mtd0 0x400 $dtbo_size /lib/firmware/mpfs_dtbo.spi > /dev/zero
+
+# Fake the presence of a golden image for now.
+/usr/sbin/mtd_debug write /dev/mtd0 0 4 /dev/zero > /dev/zero
+
+# Initiate FPGA update.
+echo "Triggering FPGA Gateware Update (/sys/kernel/debug/fpga/microchip_exec_update)"
+echo 1 > /sys/kernel/debug/fpga/microchip_exec_update
+
+# Reboot Linux for the gateware update to take effect.
+# FPGA reprogramming takes places between Linux shut-down and HSS restarting the board.
+/usr/sbin/reboot

gather_dtso.py

+# Gather device tree overlay dtso files from the gateware's
+# script_support/components/<component-name>/<build-option-name>/device-tree-overlay
+# directories into the bitstream builder's work/dtbo/context-0/<component-name>
+# directories.
+import os
+import shutil
+import sys
+
+
+def gather_dtso(gateware_dir, work_dir, build_options):
+    context_dir = os.path.join(gateware_dir, "script_support", "components")
+
+    build_options_dict = {}
+    if build_options != 'NONE':
+        options = build_options.split()
+        for option in options:
+            opt = option.split(':')
+            le = len("_OPTION")
+            component_dir = opt[0][:-le]
+            option_dir = opt[1]
+            build_options_dict[component_dir] = option_dir
+
+    dtbo_dir = os.path.join(work_dir, "dtbo")
+    if not os.path.exists(dtbo_dir):
+        os.makedirs(dtbo_dir)
+    context_0_dir = os.path.join(dtbo_dir, "context-0")
+    if not os.path.exists(context_0_dir):
+        os.makedirs(context_0_dir)
+
+    for root, dirs, files in os.walk(context_dir):
+        for file in files:
+            if file.endswith(".dtso"):
+                dir_filename = os.path.split(root)
+                if dir_filename[1] == 'device-tree-overlay':
+                    option_name = os.path.split(dir_filename[0])[1]
+                    component_name = os.path.split(os.path.split(dir_filename[0])[0])[1]
+                    if component_name in build_options_dict:
+                        desired_option = build_options_dict[component_name]
+                    else:
+                        desired_option = 'DEFAULT'
+                    if option_name == desired_option:
+                        print("  Device tree overlay selected:")
+                        print("    component:                ", component_name)
+                        print("    build option:             ", option_name)
+                        print("    device tree overlay file: ", file)
+                        component_dir = os.path.join(context_0_dir, component_name)
+                        if not os.path.exists(component_dir):
+                            os.makedirs(component_dir)
+                        src_path = os.path.join(root, file)
+                        dst_path = os.path.join(component_dir, file)
+                        shutil.copy(src_path, dst_path)
+
+
+if __name__ == '__main__':
+    if len(sys.argv) < 3:
+        print("Two arguments expected: gateware and work directory paths.")
+        exit()
+
+    argumentList = sys.argv[1:]
+    gateware_dir = argumentList[0]
+    work_dir = argumentList[1]
+
+    if os.path.exists(gateware_dir):
+        if os.path.exists(work_dir):
+            gather_dtso(gateware_dir, work_dir, argumentList[2:])
+        else:
+            print("Invalid bitstream builder work directory.")
+    else:
+        print("Gateware directory does not exist.")

generate_gateware_overlays.py

+import os
+import struct
+import ctypes
+import sys
+import subprocess
+
+from gather_dtso import gather_dtso
+
+global dtbo_info
+
+
+def gen_magic():
+    global dtbo_info
+    struct.pack_into('cccc', dtbo_info, 0, b'M', b'C', b'H', b'P')
+
+
+def gen_descriptor_length(no_of_contexts, no_of_dtbo):
+    global dtbo_info
+    descriptor_length = 12 + (4 * no_of_contexts) + (4 * no_of_dtbo)
+    struct.pack_into('I', dtbo_info, 4, descriptor_length)
+
+
+# 2 bytes longs version number
+def gen_version():
+    global dtbo_info
+    version = 0
+    struct.pack_into('H', dtbo_info, 8, version)
+
+
+def gen_number_of_contexts(no_of_contexts):
+    global dtbo_info
+    in_number_of_contexts = no_of_contexts
+    struct.pack_into('H', dtbo_info, 10, in_number_of_contexts)
+
+
+def get_dtbo_files_list():
+    initial_directory = os.getcwd()
+    context_dir = os.path.join(initial_directory, "work", "dtbo", "context-0")
+    dtbo_files_list = []
+    for root, dirs, files in os.walk(context_dir):
+        for file in files:
+            if file.endswith(".dtbo"):
+                dtbo_files_list.append(os.path.join(root, file))
+    return dtbo_files_list
+
+
+def get_dtbo_total_size(dtbo_list):
+    size = 0
+    for dtbo_file in dtbo_list:
+        size = size + os.path.getsize(dtbo_file)
+    return size
+
+
+def gen_dtbo_info(overlay_dir_path, no_of_contexts, dtbo_list):
+    dtbo_desc_list_start_offset = 12 + (no_of_contexts * 4)
+    struct.pack_into('I', dtbo_info, 12, dtbo_desc_list_start_offset)
+    no_of_dtbo = len(dtbo_list)
+    struct.pack_into('I', dtbo_info, 16, no_of_dtbo)
+    dtbo_data_offset = 20 + (no_of_dtbo * 12)
+    dtbo_idx = 0
+    for dtbo_file in dtbo_list:
+        size = os.path.getsize(dtbo_file)
+        struct.pack_into('I', dtbo_info, 20 + (dtbo_idx * 12), dtbo_data_offset)
+        struct.pack_into('I', dtbo_info, 24 + (dtbo_idx * 12), dtbo_data_offset + size)
+        struct.pack_into('I', dtbo_info, 28 + (dtbo_idx * 12), size)
+        dtbo_data_offset += size
+        dtbo_idx += 1
+
+    dtbo_full_path = os.path.join(overlay_dir_path, "mpfs_dtbo.spi")
+    with open(dtbo_full_path, "wb") as mpfs_dtbo:
+        mpfs_dtbo.write(dtbo_info)
+
+    #
+    # Append the actual dtbo files to the dtbo_file
+    #
+    with open(dtbo_full_path, "ab") as mpfs_dtbo:
+        for dtbo_file in dtbo_list:
+            with open(dtbo_file, "rb") as in_dtbo_file:
+                mpfs_dtbo.write(in_dtbo_file.read())
+
+
+def create_dtbo_info(overlay_dir_path):
+    global dtbo_info
+
+    dtbo_list = get_dtbo_files_list()
+    print("number of gateware device tree overlays: ", len(dtbo_list))
+    for dtbo_file in dtbo_list:
+        print(dtbo_file)
+    no_of_contexts = 1
+    no_of_dtbo = len(dtbo_list)
+
+    #
+    # Generate the DTBO info binary.
+    #
+    dtbo_info_length = 12 + (8 * no_of_contexts) + (12 * no_of_dtbo)
+
+    dtbo_info = ctypes.create_string_buffer(dtbo_info_length)
+    gen_magic()
+    gen_descriptor_length(no_of_contexts, no_of_dtbo)
+    gen_version()
+    gen_number_of_contexts(no_of_contexts)
+    gen_dtbo_info(overlay_dir_path, no_of_contexts, dtbo_list)
+    print(dtbo_info[:])
+
+
+def get_gateware_git_version(work_dir):
+    try:
+        git_hash = subprocess.check_output(['git', 'describe', '--tags'])
+    except subprocess.CalledProcessError as e:
+        git_hash = b"\n"
+    return git_hash.decode('ascii').strip("'").strip("\n")
+
+
+def inject_git_info_into_src_dtso(dtso_file, git_version):
+    with open(dtso_file, "r") as f:
+        dtso = f.read()
+        dtso = dtso.replace('GATEWARE_GIT_VERSION', git_version)
+        with open(dtso_file, "w") as fout:
+            fout.write(dtso)
+
+
+def compile_dtso(work_dir):
+    root_dir = os.path.join(work_dir, 'dtbo', 'context-0')
+    git_version = get_gateware_git_version(work_dir)
+    for root, dirs, files in os.walk(root_dir):
+        for file in files:
+            if file.endswith(".dtso"):
+                dtso_file = os.path.join(root, file)
+                inject_git_info_into_src_dtso(dtso_file, git_version)
+                dtbo_file = os.path.splitext(dtso_file)[0] + '.dtbo'
+                cmd = 'dtc -O dtb -I dts -o ' + dtbo_file + ' ' + dtso_file
+                os.system(cmd)
+
+
+def generate_device_tree_overlays(overlay_dir_path, build_options_list):
+    print("================================================================================")
+    print("                            Generate Device Tree Overlays")
+    print("================================================================================\r\n", flush=True)
+    bitstream_builder_root = os.getcwd()
+    gateware_dir = os.path.join(bitstream_builder_root, 'sources', 'FPGA-design')
+    work_dir = os.path.join(bitstream_builder_root, 'work')
+    gather_dtso(gateware_dir, work_dir, build_options_list)
+    compile_dtso(work_dir)
+    create_dtbo_info(overlay_dir_path)
+
+
+def generate_gateware_overlays(overlay_dir_path, build_options_list):
+    generate_device_tree_overlays(overlay_dir_path, build_options_list)
+
+
+if __name__ == '__main__':
+    if len(sys.argv) > 1:
+        argument_list = sys.argv[1:]
+    else:
+        argument_list = 'NONE'
+    generate_device_tree_overlays(argument_list)

recipes/libero-project/configure.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+source ./recipes/libero-project/functions.tcl
+set local_dir [pwd]
+set project_name libero_project
+set output_directory "$local_dir/output"
+set libero_project_directory "$output_directory/$project_name"
+set artifact_directory "$output_directory/final-files"
+
+# Set variables from arguments
+if { $::argc > 0 } {
+    set i 1
+    foreach arg $::argv {
+        if {[string match "*:*" $arg]} { 
+            set temp [split $arg ":"]
+            puts "Setting parameter [lindex $temp 0] to [lindex $temp 1]"
+            set [lindex $temp 0] "[lindex $temp 1]"
+        } else {
+            set $arg 1
+            puts "set $arg to 1"
+        }
+        incr i
+    }
+}

recipes/libero-project/constraints.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+create_links \
+         -convert_EDN_to_HDL 0 \
+         -io_pdc ./sources/HDL/Constraints/mmuart0.pdc
+
+organize_tool_files \
+    -tool {PLACEROUTE} \
+    -file ./sources/HDL/Constraints/mmuart0.pdc \
+    -module {base::work} \
+    -input_type {constraint}
+    

recipes/libero-project/export-data.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+source ./recipes/libero-project/configure.tcl
+
+open_project -file {./output/libero_project/libero_project.prjx} -do_backup_on_convert 1 -backup_file {./output/libero_project/libero_project.zip} 
+
+run_tool -name {GENERATEPROGRAMMINGFILE} 
+
+run_tool -name {GENERATEDEBUGDATA} 
+
+export_bitstream_file \
+         -file_name {bitstream_file} \
+         -export_dir $artifact_directory \
+         -format {DAT PPD} \
+         -for_ihp 0 \
+         -limit_SVF_file_size 0 \
+         -limit_SVF_file_by_max_filesize_or_vectors {} \
+         -svf_max_filesize {} \
+         -svf_max_vectors {} \
+         -master_file 0 \
+         -master_file_components {} \
+         -encrypted_uek1_file 0 \
+         -encrypted_uek1_file_components {} \
+         -encrypted_uek2_file 0 \
+         -encrypted_uek2_file_components {} \
+         -trusted_facility_file 1 \
+         -trusted_facility_file_components {FABRIC_SNVM} \
+         -zeroization_likenew_action 0 \
+         -zeroization_unrecoverable_action 0 \
+         -master_backlevel_bypass 0 \
+         -uek1_backlevel_bypass 0 \
+         -uek2_backlevel_bypass 0 \
+         -master_include_plaintext_passkey 0 \
+         -uek1_include_plaintext_passkey 0 \
+         -uek2_include_plaintext_passkey 0 \
+         -sanitize_snvm 0 \
+         -sanitize_envm 0 \
+         -trusted_facility_keep_fabric_operational 0 \
+         -trusted_facility_skip_startup_seq 0 \
+         -uek1_keep_fabric_operational 0 \
+         -uek1_skip_startup_seq 0 \
+         -uek2_keep_fabric_operational 0 \
+         -uek2_skip_startup_seq 0 
+
+export_prog_job \
+         -job_file_name {programming_job} \
+         -export_dir $artifact_directory \
+         -bitstream_file_type {TRUSTED_FACILITY} \
+         -bitstream_file_components {FABRIC_SNVM} \
+         -zeroization_likenew_action 0 \
+         -zeroization_unrecoverable_action 0 \
+         -program_design 1 \
+         -program_spi_flash 0 \
+         -include_plaintext_passkey 0 \
+         -design_bitstream_format {PPD} \
+         -prog_optional_procedures {} \
+         -skip_recommended_procedures {} \
+         -sanitize_snvm 0 \
+         -sanitize_envm 0 
+
+export_spiflash_image \
+    -file_name {spi-flash-image} \
+    -export_dir $artifact_directory
+
+export_pin_reports \
+         -export_dir $artifact_directory \
+         -pin_report_by_name 1 \
+         -pin_report_by_pkg_pin 1 \
+         -bank_report 1 \
+         -io_report 1 
+
+export_bsdl_file \
+         -file $artifact_directory
+
+update_and_run_tool -name {EXPORTDEVMEMINIT} 
+
+export_dev_mem_init_report \
+         -export_dir $artifact_directory
+
+export_smart_debug_data \
+         -file_name {smart-debug-data} \
+         -export_dir $artifact_directory \
+         -probes 1 \
+         -package_pins 0 \
+         -memory_blocks 1 \
+         -envm_data 0 \
+         -security_data 1 \
+         -display_security_in_smartdebug 0 \
+         -chain 1 \
+         -programmer_settings 1 \
+         -ios_states 1 \
+         -generate_bitstream 0 \
+         -bitstream_format {PPD} \
+         -bitstream_security 0 \
+         -bitstream_fabric 0 \
+         -bitstream_envm 0 \
+         -sanitize_envm 0 \
+         -bitstream_snvm 0 \
+         -sanitize_snvm 0 \
+         -master_include_plaintext_passkey 0 \
+         -snvm_data 1 
+
+
+export_prog_job \
+         -job_file_name {fp-job} \
+         -export_dir $artifact_directory \
+         -bitstream_file_type {TRUSTED_FACILITY} \
+         -bitstream_file_components {ENVM FABRIC_SNVM} \
+         -zeroization_likenew_action 0 \
+         -zeroization_unrecoverable_action 0 \
+         -program_design 1 \
+         -program_spi_flash 0 \
+         -include_plaintext_passkey 0 \
+         -design_bitstream_format {PPD} \
+         -prog_optional_procedures {} \
+         -skip_recommended_procedures {} \
+         -sanitize_snvm 0 \
+         -sanitize_envm 0
+         
+save_project 

recipes/libero-project/functions.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+proc create_eNVM_config {config client} {
+    set envm_config [open $config w]
+    
+    puts $envm_config "set_plain_text_client \\"
+    puts $envm_config "-client_name {BOOT_MODE_1_ENVM_CLIENT} \\"
+    puts $envm_config "-number_of_bytes 117248 \\"
+    puts $envm_config "-content_type {MEMORY_FILE} \\"
+    puts $envm_config "-content_file_format {Intel-Hex} \\"
+    puts $envm_config "-content_file {$client} \\"
+    puts $envm_config "-mem_file_base_address {0x20220000} \\"
+    puts $envm_config "-start_page 0 \\"
+    puts $envm_config "-use_for_simulation 0 \\"
+    puts $envm_config "-reprogram 1 \\"
+    puts $envm_config "-use_as_rom 0 \\"
+    puts $envm_config "-fabric_access_read 1 \\"
+    puts $envm_config "-fabric_access_write 0 \\"
+    puts $envm_config "-mss_access_read 1 \\"
+    puts $envm_config "-mss_access_write 0"
+
+    close $envm_config
+}
+
+proc create_spi_config {config client} {
+    set spi_config [open $config w]
+    
+    puts $spi_config "set_auto_update_mode {0} "
+    puts $spi_config "set_spi_flash_memory_size {134217728} "
+    puts $spi_config "set_client \\"
+    puts $spi_config "	 -client_name    {baremetal} \\"
+    puts $spi_config "	 -client_type    {FILE_DATA_STORAGE_PLAIN_BIN} \\"
+    puts $spi_config "	 -content_type   {MEMORY_FILE} \\"
+    puts $spi_config "	 -content_file   {$client} \\"
+    puts $spi_config "	 -start_address  {1024} \\"
+    puts $spi_config "	 -client_size    {16496} \\"
+    puts $spi_config "	 -program        {1}"
+
+    close $spi_config
+}

recipes/libero-project/generate-project.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+source ./recipes/libero-project/configure.tcl
+
+# Make the project
+new_project \
+    -location $libero_project_directory \
+    -name $project_name \
+    -project_description {} \
+    -block_mode 0 \
+    -standalone_peripheral_initialization 0 \
+    -instantiate_in_smartdesign 1 \
+    -ondemand_build_dh 1 \
+    -use_relative_path 0 \
+    -linked_files_root_dir_env {} \
+    -hdl {VERILOG} \
+    -family {PolarFireSoC} \
+    -die {MPFS250T_ES} \
+    -package {FCVG484} \
+    -speed {STD} \
+    -die_voltage {1.05} \
+    -part_range {EXT} \
+    -adv_options {IO_DEFT_STD:LVCMOS 1.8V} \
+    -adv_options {RESTRICTPROBEPINS:1} \
+    -adv_options {RESTRICTSPIPINS:0} \
+    -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} \
+    -adv_options {TEMPR:EXT} \
+    -adv_options {VCCI_1.2_VOLTR:EXT} \
+    -adv_options {VCCI_1.5_VOLTR:EXT} \
+    -adv_options {VCCI_1.8_VOLTR:EXT} \
+    -adv_options {VCCI_2.5_VOLTR:EXT} \
+    -adv_options {VCCI_3.3_VOLTR:EXT} \
+    -adv_options {VOLTR:EXT}
+
+# Make and import HDL sources
+import_mss_component -file "./output/MSS/test_mss.cxz"
+
+# Generate SmartDesign
+cd ./sources/HDL/base
+source ./base_recursive.tcl
+set_root -module {base::work} 
+cd ../../../
+
+# Import constraints
+source ./recipes/libero-project/constraints.tcl
+
+save_project 

recipes/libero-project/import-clients.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+source ./recipes/libero-project/configure.tcl
+
+open_project -file {./output/libero_project/libero_project.prjx} -do_backup_on_convert 1 -backup_file {./output/libero_project/libero_project.zip} 
+
+# Import clients
+create_eNVM_config "output/clients/HSS_ENVM.cfg" "../../output/HSS/hss-envm-wrapper-bm1-p0.hex"
+configure_envm -cfg_file "./output/clients/HSS_ENVM.cfg"
+
+create_spi_config "output/clients/bare_metal_spi.cfg" "../../output/payload/spi.bin"
+configure_spiflash -cfg_file "./output/clients/bare_metal_spi.cfg"
+generate_design_initialization_data 
+
+save_project 

recipes/libero-project/program-device.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+open_project -file {./output/libero_project/libero_project.prjx} -do_backup_on_convert 1 -backup_file {./output/libero_project/libero_project.zip} 
+
+# configure_tool \
+         -name {IO_PROGRAMMING_STATE} \
+         -params {ios_file:} 
+
+# configure_tool \
+         -name {CONFIGURE_PROG_OPTIONS} \
+         -params {back_level_version:0} \
+         -params {design_version:0} \
+         -params {silicon_signature:} 
+
+# configure_tool \
+         -name {SPM} \
+         -params {back_level_protection:true} \
+         -params {debug_passkey:} \
+         -params {disable_authenticate_action:false} \
+         -params {disable_autoprog_iap_services:false} \
+         -params {disable_debug_jtag_boundary_scan:false} \
+         -params {disable_debug_read_temp_volt:false} \
+         -params {disable_debug_ujtag:false} \
+         -params {disable_ext_zeroization:false} \
+         -params {disable_external_digest_check:false} \
+         -params {disable_jtag:false} \
+         -params {disable_program_action:false} \
+         -params {disable_puf_emulation:false} \
+         -params {disable_smartdebug_debug:false} \
+         -params {disable_smartdebug_live_probe:false} \
+         -params {disable_smartdebug_snvm:false} \
+         -params {disable_spi_slave:false} \
+         -params {disable_user_encryption_key_1:false} \
+         -params {disable_user_encryption_key_2:false} \
+         -params {disable_verify_action:false} \
+         -params {envm_update_protection:open} \
+         -params {fabric_update_protection:open} \
+         -params {security_factory_access:open} \
+         -params {security_key_mode:default} \
+         -params {user_encryption_key_1:} \
+         -params {user_encryption_key_2:} \
+         -params {user_passkey_1:} \
+         -params {user_passkey_2:} 
+
+run_tool -name {GENERATEPROGRAMMINGFILE} 
+
+# Program the SPI first so the device is reset after bitstream programming to boot the payload
+run_tool -name {GENERATE_SPI_FLASH_IMAGE} 
+run_tool -name {PROGRAM_SPI_FLASH_IMAGE} 
+
+configure_tool -name {CONFIGURE_ACTION_PROCEDURES} \
+         -params {prog_optional_procedures:""} \
+         -params {skip_recommended_procedures:""} 
+
+run_tool -name {PROGRAMDEVICE}
+
+save_project 

recipes/libero-project/run-flow.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+open_project -file {./output/libero_project/libero_project.prjx} -do_backup_on_convert 1 -backup_file {./output/libero_project/libero_project.zip} 
+
+# organize_tool_files -tool {SIM_PRESYNTH} \
+    -file {} \
+    -module {base::work} \
+    -input_type {stimulus} 
+
+# run_tool -name {SIM_PRESYNTH}
+
+# Configure synthesis options
+# configure_tool \
+     -name {SYNTHESIZE} \
+     -params {ACTIVE_IMPLEMENTATION:synthesis} \
+     -params {AUTO_COMPILE_POINT:true} \
+     -params {BLOCK_MODE:false} \
+     -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} \
+     -params {BLOCK_ROUTING_CONFLICTS:LOCK} \
+     -params {CDC_MIN_NUM_SYNC_REGS:2} \
+     -params {CDC_REPORT:true} \
+     -params {CLOCK_ASYNC:800} \
+     -params {CLOCK_DATA:5000} \
+     -params {CLOCK_GATE_ENABLE:false} \
+     -params {CLOCK_GATE_ENABLE_THRESHOLD_GLOBAL:1000} \
+     -params {CLOCK_GATE_ENABLE_THRESHOLD_ROW:100} \
+     -params {CLOCK_GLOBAL:2} \
+     -params {CREATE_IMPLEMENTATION_IDENTIFY:} \
+     -params {CREATE_IMPLEMENTATION_SYNTHESIS:synthesis} \
+     -params {PA4_GB_COUNT:36} \
+     -params {PA4_GB_MAX_RCLKINT_INSERTION:16} \
+     -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:1000} \
+     -params {RAM_OPTIMIZED_FOR_POWER:0} \
+     -params {RETIMING:false} \
+     -params {ROM_TO_LOGIC:true} \
+     -params {SEQSHIFT_TO_URAM:1} \
+     -params {SYNPLIFY_OPTIONS:} \
+     -params {SYNPLIFY_TCL_FILE:} 
+
+# Run synthesis
+run_tool -name {SYNTHESIZE}
+
+# organize_tool_files -tool {SIM_POSTSYNTH} \
+    -file {} \
+    -module {base::work} \
+    -input_type {stimulus} 
+
+# run_tool -name {SIM_POSTSYNTH}
+
+# Export the netlist
+# run_tool -name {EXPORTNETLIST}
+
+# Timing verification 
+# Max timing work first - no high effort, no min delay
+configure_tool -name {PLACEROUTE} \
+    -params {DELAY_ANALYSIS:MAX} \
+    -params {EFFORT_LEVEL:false} \
+    -params {GB_DEMOTION:true} \
+    -params {INCRPLACEANDROUTE:false} \
+    -params {IOREG_COMBINING:false} \
+    -params {MULTI_PASS_CRITERIA:VIOLATIONS} \
+    -params {MULTI_PASS_LAYOUT:false} \
+    -params {NUM_MULTI_PASSES:5} \
+    -params {PDPR:false} \
+    -params {RANDOM_SEED:0} \
+    -params {REPAIR_MIN_DELAY:true} \
+    -params {REPLICATION:false} \
+    -params {SLACK_CRITERIA:WORST_SLACK} \
+    -params {SPECIFIC_CLOCK:} \
+    -params {START_SEED_INDEX:1} \
+    -params {STOP_ON_FIRST_PASS:false} \
+    -params {TDPR:true} 
+
+run_tool -name {PLACEROUTE} 
+
+# Check for max delay and min delay violations using timing verification
+
+run_tool -name {VERIFYTIMING}
+
+# if no max violations continue...
+
+# Min delay next in incremental
+configure_tool -name {PLACEROUTE} \
+    -params {DELAY_ANALYSIS:MAX} \
+    -params {EFFORT_LEVEL:false} \
+    -params {GB_DEMOTION:true} \
+    -params {INCRPLACEANDROUTE:true} \
+    -params {IOREG_COMBINING:false} \
+    -params {MULTI_PASS_CRITERIA:VIOLATIONS} \
+    -params {MULTI_PASS_LAYOUT:false} \
+    -params {NUM_MULTI_PASSES:25} \
+    -params {PDPR:false} \
+    -params {RANDOM_SEED:7} \
+    -params {REPAIR_MIN_DELAY:true} \
+    -params {REPLICATION:false} \
+    -params {SLACK_CRITERIA:WORST_SLACK} \
+    -params {SPECIFIC_CLOCK:} \
+    -params {START_SEED_INDEX:9} \
+    -params {STOP_ON_FIRST_PASS:true} \
+    -params {TDPR:true}
+
+run_tool -name {PLACEROUTE}
+
+# Finial timing check - should stop here on violations
+run_tool -name {VERIFYTIMING}
+
+run_tool -name {VERIFYPOWER}
+
+# run_tool -name {EXPORTSDF}
+
+# organize_tool_files -tool {SIM_POSTLAYOUT} \
+    -file {} \
+    -module {base::work} \
+    -input_type {stimulus} 
+
+# run_tool -name {SIM_POSTLAYOUT}
+
+# run_tool -name {CONFIGURE_CHAIN}
+
+# select_programmer -programmer_id {S2011K1YJJ}
+
+run_tool -name {GENERATEPROGRAMMINGDATA}
+
+save_project 

script_support/components/CAPE/DEFAULT/CAPE.tcl

-# Creating SmartDesign CAPE
-set sd_name {CAPE}
-create_smartdesign -sd_name ${sd_name}
-
-#-------------------------------------------------------------------------------
-# Create APB Bus
-#-------------------------------------------------------------------------------
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
-"APBSLOT0ENABLE:true" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:false" "APBSLOT3ENABLE:false" \
-"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
-"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
-"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
-"APB_DWIDTH:32" \
-"IADDR_OPTION:0" \
-"MADDR_BITS:24" \
-"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
-"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
-"SC_12:false" "SC_13:false" "SC_14:false" \
-"SC_15:false" \
-"UPR_NIBBLE_POSN:5"}
-
-sd_instantiate_component -sd_name {CAPE} -component_name {CoreAPB3_CAPE} -instance_name {} 
-
-#-------------------------------------------------------------------------------
-# Create APB Bus Converter
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
-
-#-------------------------------------------------------------------------------
-# Add Default Cape GPIOs
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_DEFAULT_GPIOS} -instance_name {CAPE_DEFAULT_GPIOS}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OUT} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OE} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_IN} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_20}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P9_12}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P9_15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P9_17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P9_18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P9_21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P9_22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P9_23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P9_24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P9_25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P9_26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P9_27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P9_28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P9_29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P9_30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P9_31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P9_41}
-
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_4}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_28_PAD} -new_port_name {P8_5}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_29_PAD} -new_port_name {P8_6}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_30_PAD} -new_port_name {P8_7}
-
-
-#-------------------------------------------------------------------------------
-# LCD interface stub
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_LCD} -instance_name {CAPE_LCD_STUB}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PRESETN} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PCLK} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA0} -new_port_name {P8_31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA1} -new_port_name {P8_32}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA2} -new_port_name {P8_33}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA3} -new_port_name {P8_34}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA4} -new_port_name {P8_35}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA5} -new_port_name {P8_36}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA6} -new_port_name {P8_37}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA7} -new_port_name {P8_38}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA8} -new_port_name {P8_39}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA9} -new_port_name {P8_40}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA10} -new_port_name {P8_41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA11} -new_port_name {P8_42}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA12} -new_port_name {P8_43}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA13} -new_port_name {P8_44}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA14} -new_port_name {P8_45}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA15} -new_port_name {P8_46}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_HSYNC} -new_port_name {P8_29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_AC_BIAS} -new_port_name {P8_30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_VSYNC} -new_port_name {P8_27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_PCLK} -new_port_name {P8_28}
-
-
-#-------------------------------------------------------------------------------
-# PWM
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_0}
-
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_0} -port_name {} 
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_1} -port_name {} 
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_2} -port_name {} 
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_3} -port_name {} 
-
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_0_0} -new_port_name {P9_42} 
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_1} -new_port_name {P9_14} 
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_2} -new_port_name {P9_16} 
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_3} -new_port_name {P8_19} 
-
-
-#-------------------------------------------------------------------------------
-# Connections
-#-------------------------------------------------------------------------------
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "PWM_0:PRESETN"} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "PWM_0:PCLK"} 
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave"} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_LCD_STUB:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"} 
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {APB_BUS_CONVERTER_0:APB_SLAVE} -port_name {} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster"} 
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE
-generate_component -component_name ${sd_name}

script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl

-# Creating SmartDesign CAPE_PWM
-set sd_name {CAPE_PWM}
-create_smartdesign -sd_name ${sd_name}
-
-
-create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -component_name {corepwm_C1} -params {\
-"APB_DWIDTH:32" "CONFIG_MODE:0" \
-"DAC_MODE1:false" "DAC_MODE2:false" "DAC_MODE3:false" "DAC_MODE4:false" "DAC_MODE5:false" \
-"DAC_MODE6:false" "DAC_MODE7:false" "DAC_MODE8:false" "DAC_MODE9:false" "DAC_MODE10:false" \
-"DAC_MODE11:false" "DAC_MODE12:false" "DAC_MODE13:false" "DAC_MODE14:false" "DAC_MODE15:false" \
-"DAC_MODE16:false" \
-"FIXED_PERIOD:1" "FIXED_PERIOD_EN:false" "FIXED_PRESCALE:0" "FIXED_PRESCALE_EN:false" \
-"FIXED_PWM_NEGEDGE1:0" "FIXED_PWM_NEGEDGE2:0" "FIXED_PWM_NEGEDGE3:0" "FIXED_PWM_NEGEDGE4:0" "FIXED_PWM_NEGEDGE5:0" \
-"FIXED_PWM_NEGEDGE6:0" "FIXED_PWM_NEGEDGE7:0" "FIXED_PWM_NEGEDGE8:0" "FIXED_PWM_NEGEDGE9:0" "FIXED_PWM_NEGEDGE10:0" \
-"FIXED_PWM_NEGEDGE11:0" "FIXED_PWM_NEGEDGE12:0" "FIXED_PWM_NEGEDGE13:0" "FIXED_PWM_NEGEDGE14:0" "FIXED_PWM_NEGEDGE15:0" \
-"FIXED_PWM_NEGEDGE16:0" \
-"FIXED_PWM_NEG_EN1:false" "FIXED_PWM_NEG_EN2:false" "FIXED_PWM_NEG_EN3:false" "FIXED_PWM_NEG_EN4:false" "FIXED_PWM_NEG_EN5:false" \
-"FIXED_PWM_NEG_EN6:false" "FIXED_PWM_NEG_EN7:false" "FIXED_PWM_NEG_EN8:false" "FIXED_PWM_NEG_EN9:false" "FIXED_PWM_NEG_EN10:false" \
-"FIXED_PWM_NEG_EN11:false" "FIXED_PWM_NEG_EN12:false" "FIXED_PWM_NEG_EN13:false" "FIXED_PWM_NEG_EN14:false" "FIXED_PWM_NEG_EN15:false" \
-"FIXED_PWM_NEG_EN16:false" \
-"FIXED_PWM_POSEDGE1:0" "FIXED_PWM_POSEDGE2:0" "FIXED_PWM_POSEDGE3:0" "FIXED_PWM_POSEDGE4:0" "FIXED_PWM_POSEDGE5:0" \
-"FIXED_PWM_POSEDGE6:0" "FIXED_PWM_POSEDGE7:0" "FIXED_PWM_POSEDGE8:0" "FIXED_PWM_POSEDGE9:0" "FIXED_PWM_POSEDGE10:0" \
-"FIXED_PWM_POSEDGE11:0" "FIXED_PWM_POSEDGE12:0" "FIXED_PWM_POSEDGE13:0" "FIXED_PWM_POSEDGE14:0" "FIXED_PWM_POSEDGE15:0" \
-"FIXED_PWM_POSEDGE16:0" \
-"FIXED_PWM_POS_EN1:false" "FIXED_PWM_POS_EN2:false" "FIXED_PWM_POS_EN3:false" "FIXED_PWM_POS_EN4:false" "FIXED_PWM_POS_EN5:false" \
-"FIXED_PWM_POS_EN6:true" "FIXED_PWM_POS_EN7:true" "FIXED_PWM_POS_EN8:true" "FIXED_PWM_POS_EN9:true" "FIXED_PWM_POS_EN10:true" \
-"FIXED_PWM_POS_EN11:true" "FIXED_PWM_POS_EN12:true" "FIXED_PWM_POS_EN13:true" "FIXED_PWM_POS_EN14:true" "FIXED_PWM_POS_EN15:true" \
-"FIXED_PWM_POS_EN16:true" \
-"PWM_NUM:4" \
-"PWM_STRETCH_VALUE1:false" "PWM_STRETCH_VALUE2:false" "PWM_STRETCH_VALUE3:false" "PWM_STRETCH_VALUE4:false" "PWM_STRETCH_VALUE5:false" \
-"PWM_STRETCH_VALUE6:false" "PWM_STRETCH_VALUE7:false" "PWM_STRETCH_VALUE8:false" "PWM_STRETCH_VALUE9:false" "PWM_STRETCH_VALUE10:false" \
-"PWM_STRETCH_VALUE11:false" "PWM_STRETCH_VALUE12:false" "PWM_STRETCH_VALUE13:false" "PWM_STRETCH_VALUE14:false" "PWM_STRETCH_VALUE15:false" \
-"PWM_STRETCH_VALUE16:false" \
-"SEPARATE_PWM_CLK:false" \
-"SHADOW_REG_EN1:false" "SHADOW_REG_EN2:false" "SHADOW_REG_EN3:false" "SHADOW_REG_EN4:false" "SHADOW_REG_EN5:false" \
-"SHADOW_REG_EN6:false" "SHADOW_REG_EN7:false" "SHADOW_REG_EN8:false" "SHADOW_REG_EN9:false" \
-"SHADOW_REG_EN10:false" "SHADOW_REG_EN11:false" "SHADOW_REG_EN12:false" "SHADOW_REG_EN13:false" \
-"SHADOW_REG_EN14:false" "SHADOW_REG_EN15:false" "SHADOW_REG_EN16:false" \
-"TACHINT_ACT_LEVEL:false" \
-"TACH_EDGE1:false" "TACH_EDGE2:false" "TACH_EDGE3:false" "TACH_EDGE4:false" "TACH_EDGE5:false" \
-"TACH_EDGE6:false" "TACH_EDGE7:false" "TACH_EDGE8:false" "TACH_EDGE9:false" "TACH_EDGE10:false" \
-"TACH_EDGE11:false" "TACH_EDGE12:false" "TACH_EDGE13:false" "TACH_EDGE14:false" "TACH_EDGE15:false" \
-"TACH_EDGE16:false" \
-"TACH_NUM:1"} 
-
-sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {} 
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[3:3]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[2:2]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[1:1]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[0:0]"} 
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:APBslave} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PRESETN} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PCLK} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[0:0]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[3:3]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[2:2]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[1:1]} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_2} -new_port_name {PWM_3}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_1} -new_port_name {PWM_2}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_0} -new_port_name {PWM_1}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM} -new_port_name {PWM_0}
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE_PWM
-generate_component -component_name ${sd_name}

script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl

-# Creating SmartDesign P8_GPIO_LCD
-set sd_name {P8_GPIO_LCD}
-create_smartdesign -sd_name ${sd_name}
-
-auto_promote_pad_pins -promote_all 1
-
-# Add GPIO BIBUFs
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_0_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_1_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_2_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_3_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_4_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_5_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_6_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_7_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_8_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_9_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_10_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_11_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_12_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_13_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_14_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_15_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_16_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_17_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_18_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_HSYNC_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_AC_BIAS_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_VSYNC_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_PCLK_GPIO_BIBUF}
-
-
-
-
-
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_LCD} -params {\
-"APB_WIDTH:32" \
-"FIXED_CONFIG_0:true" "FIXED_CONFIG_1:true" "FIXED_CONFIG_2:true" "FIXED_CONFIG_3:true" "FIXED_CONFIG_4:true" \
-"FIXED_CONFIG_5:true" "FIXED_CONFIG_6:true" "FIXED_CONFIG_7:true" "FIXED_CONFIG_8:true" "FIXED_CONFIG_9:true" \
-"FIXED_CONFIG_10:true" "FIXED_CONFIG_11:true" "FIXED_CONFIG_12:true" "FIXED_CONFIG_13:true" "FIXED_CONFIG_14:true" \
-"FIXED_CONFIG_15:true" "FIXED_CONFIG_16:true" "FIXED_CONFIG_17:true" "FIXED_CONFIG_18:true" "FIXED_CONFIG_19:true" \
-"FIXED_CONFIG_20:false" "FIXED_CONFIG_21:false" "FIXED_CONFIG_22:false" "FIXED_CONFIG_23:false" "FIXED_CONFIG_24:false" \
-"FIXED_CONFIG_25:false" "FIXED_CONFIG_26:false" "FIXED_CONFIG_27:false" "FIXED_CONFIG_28:false" "FIXED_CONFIG_29:false" \
-"FIXED_CONFIG_30:false" "FIXED_CONFIG_31:false" \
-"INT_BUS:0" \
-"IO_INT_TYPE_0:7" "IO_INT_TYPE_1:7" "IO_INT_TYPE_2:7" "IO_INT_TYPE_3:7" "IO_INT_TYPE_4:7" \
-"IO_INT_TYPE_5:7" "IO_INT_TYPE_6:7" "IO_INT_TYPE_7:7" "IO_INT_TYPE_8:7" "IO_INT_TYPE_9:7" \
-"IO_INT_TYPE_10:7" "IO_INT_TYPE_11:7" "IO_INT_TYPE_12:7" "IO_INT_TYPE_13:7" "IO_INT_TYPE_14:7" \
-"IO_INT_TYPE_15:7" "IO_INT_TYPE_16:7" "IO_INT_TYPE_17:7" "IO_INT_TYPE_18:7" "IO_INT_TYPE_19:7" \
-"IO_INT_TYPE_20:7" "IO_INT_TYPE_21:7" "IO_INT_TYPE_22:7" "IO_INT_TYPE_23:7" "IO_INT_TYPE_24:7" \
-"IO_INT_TYPE_25:7" "IO_INT_TYPE_26:7" "IO_INT_TYPE_27:7" "IO_INT_TYPE_28:7" "IO_INT_TYPE_29:7" \
-"IO_INT_TYPE_30:7" "IO_INT_TYPE_31:7" \
-"IO_NUM:20" \
-"IO_TYPE_0:2" "IO_TYPE_1:2"  "IO_TYPE_2:2" "IO_TYPE_3:2" "IO_TYPE_4:2" "IO_TYPE_5:2" "IO_TYPE_6:2" "IO_TYPE_7:2" "IO_TYPE_8:2" "IO_TYPE_9:2" \
-"IO_TYPE_10:2" "IO_TYPE_11:2" "IO_TYPE_12:2" "IO_TYPE_13:2" "IO_TYPE_14:2" "IO_TYPE_15:2" "IO_TYPE_16:2" "IO_TYPE_17:2" "IO_TYPE_18:2" "IO_TYPE_19:2" \
-"IO_TYPE_20:0" "IO_TYPE_21:0" "IO_TYPE_22:0" "IO_TYPE_23:0" "IO_TYPE_24:0" "IO_TYPE_25:0" "IO_TYPE_26:0" "IO_TYPE_27:0" "IO_TYPE_28:0" "IO_TYPE_29:0" \
-"IO_TYPE_30:0" "IO_TYPE_31:0" \
-"IO_VAL_0:0" "IO_VAL_1:0" "IO_VAL_2:0" "IO_VAL_3:0" "IO_VAL_4:0" "IO_VAL_5:0" "IO_VAL_6:0" "IO_VAL_7:0" "IO_VAL_8:0" "IO_VAL_9:0" \
-"IO_VAL_10:0" "IO_VAL_11:0" "IO_VAL_12:0" "IO_VAL_13:0" "IO_VAL_14:0" "IO_VAL_15:0" "IO_VAL_16:0" "IO_VAL_17:0" "IO_VAL_18:0" "IO_VAL_19:0" \
-"IO_VAL_20:0" "IO_VAL_21:0" "IO_VAL_22:0" "IO_VAL_23:0" "IO_VAL_24:0" "IO_VAL_25:0" "IO_VAL_26:0" "IO_VAL_27:0" "IO_VAL_28:0" "IO_VAL_29:0" \
-"IO_VAL_30:0" "IO_VAL_31:0" \
-"OE_TYPE:0"} 
-
-sd_instantiate_component -sd_name {P8_GPIO_LCD} -component_name {CoreGPIO_LCD} -instance_name {} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[19:19]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[18:18]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[17:17]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[16:16]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[15:15]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[14:14]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[13:13]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[12:12]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[11:11]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[10:10]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[9:9]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[8:8]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[7:7]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[6:6]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[5:5]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[4:4]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[3:3]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[2:2]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[1:1]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[0:0]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[19:19]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[18:18]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[17:17]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[16:16]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[15:15]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[14:14]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[13:13]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[12:12]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[11:11]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[10:10]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[9:9]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[8:8]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[7:7]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[6:6]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[5:5]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[4:4]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[3:3]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[2:2]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[1:1]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[0:0]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[19:19]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[18:18]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[17:17]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[16:16]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[15:15]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[14:14]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[13:13]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[12:12]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[11:11]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[10:10]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[9:9]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[8:8]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[7:7]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[6:6]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[5:5]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[4:4]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[3:3]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[2:2]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[1:1]"} 
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[0:0]"} 
-
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[0:0]" "LCD_GPIO_0_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[0:0]" "LCD_GPIO_0_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[0:0]" "LCD_GPIO_0_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[1:1]" "LCD_GPIO_1_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[1:1]" "LCD_GPIO_1_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[1:1]" "LCD_GPIO_1_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[2:2]" "LCD_GPIO_2_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[2:2]" "LCD_GPIO_2_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[2:2]" "LCD_GPIO_2_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[3:3]" "LCD_GPIO_3_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[3:3]" "LCD_GPIO_3_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[3:3]" "LCD_GPIO_3_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[4:4]" "LCD_GPIO_4_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[4:4]" "LCD_GPIO_4_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[4:4]" "LCD_GPIO_4_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[5:5]" "LCD_GPIO_5_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[5:5]" "LCD_GPIO_5_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[5:5]" "LCD_GPIO_5_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[6:6]" "LCD_GPIO_6_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[6:6]" "LCD_GPIO_6_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[6:6]" "LCD_GPIO_6_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[7:7]" "LCD_GPIO_7_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[7:7]" "LCD_GPIO_7_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[7:7]" "LCD_GPIO_7_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[8:8]" "LCD_GPIO_8_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[8:8]" "LCD_GPIO_8_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[8:8]" "LCD_GPIO_8_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[9:9]" "LCD_GPIO_9_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[9:9]" "LCD_GPIO_9_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[9:9]" "LCD_GPIO_9_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[10:10]" "LCD_GPIO_10_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[10:10]" "LCD_GPIO_10_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[10:10]" "LCD_GPIO_10_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[11:11]" "LCD_GPIO_11_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[11:11]" "LCD_GPIO_11_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[11:11]" "LCD_GPIO_11_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[12:12]" "LCD_GPIO_12_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[12:12]" "LCD_GPIO_12_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[12:12]" "LCD_GPIO_12_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[13:13]" "LCD_GPIO_13_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[13:13]" "LCD_GPIO_13_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[13:13]" "LCD_GPIO_13_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[14:14]" "LCD_GPIO_14_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[14:14]" "LCD_GPIO_14_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[14:14]" "LCD_GPIO_14_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[15:15]" "LCD_GPIO_15_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[15:15]" "LCD_GPIO_15_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[15:15]" "LCD_GPIO_15_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[16:16]" "LCD_HSYNC_GPIO_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[16:16]" "LCD_HSYNC_GPIO_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[16:16]" "LCD_HSYNC_GPIO_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[18:18]" "LCD_VSYNC_GPIO_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[18:18]" "LCD_VSYNC_GPIO_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[18:18]" "LCD_VSYNC_GPIO_BIBUF:E"} 
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[19:19]" "LCD_PCLK_GPIO_BIBUF:D"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[19:19]" "LCD_PCLK_GPIO_BIBUF:Y"} 
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[19:19]" "LCD_PCLK_GPIO_BIBUF:E"} 
-
-
-
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD} -new_port_name {LCD_DATA0}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_0} -new_port_name {LCD_DATA1}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_1} -new_port_name {LCD_DATA2}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_2} -new_port_name {LCD_DATA3}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_3} -new_port_name {LCD_DATA4}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_4} -new_port_name {LCD_DATA5}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_5} -new_port_name {LCD_DATA6}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_6} -new_port_name {LCD_DATA7}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_7} -new_port_name {LCD_DATA8}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_8} -new_port_name {LCD_DATA9}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_9} -new_port_name {LCD_DATA10}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_10} -new_port_name {LCD_DATA11}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_11} -new_port_name {LCD_DATA12}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_12} -new_port_name {LCD_DATA13}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_13} -new_port_name {LCD_DATA14}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_14} -new_port_name {LCD_DATA15}
-
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_15} -new_port_name {LCD_HSYNC}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_16} -new_port_name {LCD_AC_BIAS}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_17} -new_port_name {LCD_VSYNC}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_18} -new_port_name {LCD_PCLK}
-
-
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PRESETN} -port_name {} 
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PCLK} -port_name {} 
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:APB_bif} -port_name {} 
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign P8_GPIO_LCD
-generate_component -component_name ${sd_name}

script_support/components/CAPE/GPIOS/CAPE.tcl

-# Creating SmartDesign CAPE
-set sd_name {CAPE}
-create_smartdesign -sd_name ${sd_name}
-
-#-------------------------------------------------------------------------------
-# Create APB Bus
-#-------------------------------------------------------------------------------
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
-"APBSLOT0ENABLE:true" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:false" "APBSLOT3ENABLE:false" \
-"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
-"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
-"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
-"APB_DWIDTH:32" \
-"IADDR_OPTION:0" \
-"MADDR_BITS:24" \
-"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
-"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
-"SC_12:false" "SC_13:false" "SC_14:false" \
-"SC_15:false" \
-"UPR_NIBBLE_POSN:5"}
-
-sd_instantiate_component -sd_name {CAPE} -component_name {CoreAPB3_CAPE} -instance_name {} 
-
-#-------------------------------------------------------------------------------
-# Create APB Bus Converter
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
-
-#-------------------------------------------------------------------------------
-# Add Default Cape GPIOs
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_DEFAULT_GPIOS} -instance_name {CAPE_DEFAULT_GPIOS}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OUT} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OE} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_IN} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_20}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P9_12}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P9_15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P9_17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P9_18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P9_21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P9_22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P9_23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P9_24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P9_25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P9_26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P9_27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P9_28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P9_29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P9_30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P9_31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P9_41}
-
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_4}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_28_PAD} -new_port_name {P8_5}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_29_PAD} -new_port_name {P8_6}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_30_PAD} -new_port_name {P8_7}
-
-
-#-------------------------------------------------------------------------------
-# LCD interface stub
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_LCD} -instance_name {CAPE_LCD_STUB}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PRESETN} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PCLK} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA0} -new_port_name {P8_31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA1} -new_port_name {P8_32}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA2} -new_port_name {P8_33}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA3} -new_port_name {P8_34}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA4} -new_port_name {P8_35}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA5} -new_port_name {P8_36}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA6} -new_port_name {P8_37}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA7} -new_port_name {P8_38}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA8} -new_port_name {P8_39}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA9} -new_port_name {P8_40}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA10} -new_port_name {P8_41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA11} -new_port_name {P8_42}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA12} -new_port_name {P8_43}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA13} -new_port_name {P8_44}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA14} -new_port_name {P8_45}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA15} -new_port_name {P8_46}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_HSYNC} -new_port_name {P8_29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_AC_BIAS} -new_port_name {P8_30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_VSYNC} -new_port_name {P8_27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_PCLK} -new_port_name {P8_28}
-
-
-#-------------------------------------------------------------------------------
-# PWM
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_0}
-
-sd_mark_pins_unused -sd_name {CAPE} -pin_names {PWM_0:PWM_0} 
-sd_mark_pins_unused -sd_name {CAPE} -pin_names {PWM_0:PWM_1} 
-sd_mark_pins_unused -sd_name {CAPE} -pin_names {PWM_0:PWM_2} 
-sd_mark_pins_unused -sd_name {CAPE} -pin_names {PWM_0:PWM_3} 
-
-
-#-------------------------------------------------------------------------------
-# Connections
-#-------------------------------------------------------------------------------
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "PWM_0:PRESETN"} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "PWM_0:PCLK"} 
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave"} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_LCD_STUB:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"} 
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {APB_BUS_CONVERTER_0:APB_SLAVE} -port_name {} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster"} 
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE
-generate_component -component_name ${sd_name}

script_support/components/CAPE/GPIOS/CAPE_PWM.tcl

-# Creating SmartDesign CAPE_PWM
-set sd_name {CAPE_PWM}
-create_smartdesign -sd_name ${sd_name}
-
-
-create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -component_name {corepwm_C1} -params {\
-"APB_DWIDTH:32" "CONFIG_MODE:0" \
-"DAC_MODE1:false" "DAC_MODE2:false" "DAC_MODE3:false" "DAC_MODE4:false" "DAC_MODE5:false" \
-"DAC_MODE6:false" "DAC_MODE7:false" "DAC_MODE8:false" "DAC_MODE9:false" "DAC_MODE10:false" \
-"DAC_MODE11:false" "DAC_MODE12:false" "DAC_MODE13:false" "DAC_MODE14:false" "DAC_MODE15:false" \
-"DAC_MODE16:false" \
-"FIXED_PERIOD:1" "FIXED_PERIOD_EN:false" "FIXED_PRESCALE:0" "FIXED_PRESCALE_EN:false" \
-"FIXED_PWM_NEGEDGE1:0" "FIXED_PWM_NEGEDGE2:0" "FIXED_PWM_NEGEDGE3:0" "FIXED_PWM_NEGEDGE4:0" "FIXED_PWM_NEGEDGE5:0" \
-"FIXED_PWM_NEGEDGE6:0" "FIXED_PWM_NEGEDGE7:0" "FIXED_PWM_NEGEDGE8:0" "FIXED_PWM_NEGEDGE9:0" "FIXED_PWM_NEGEDGE10:0" \
-"FIXED_PWM_NEGEDGE11:0" "FIXED_PWM_NEGEDGE12:0" "FIXED_PWM_NEGEDGE13:0" "FIXED_PWM_NEGEDGE14:0" "FIXED_PWM_NEGEDGE15:0" \
-"FIXED_PWM_NEGEDGE16:0" \
-"FIXED_PWM_NEG_EN1:false" "FIXED_PWM_NEG_EN2:false" "FIXED_PWM_NEG_EN3:false" "FIXED_PWM_NEG_EN4:false" "FIXED_PWM_NEG_EN5:false" \
-"FIXED_PWM_NEG_EN6:false" "FIXED_PWM_NEG_EN7:false" "FIXED_PWM_NEG_EN8:false" "FIXED_PWM_NEG_EN9:false" "FIXED_PWM_NEG_EN10:false" \
-"FIXED_PWM_NEG_EN11:false" "FIXED_PWM_NEG_EN12:false" "FIXED_PWM_NEG_EN13:false" "FIXED_PWM_NEG_EN14:false" "FIXED_PWM_NEG_EN15:false" \
-"FIXED_PWM_NEG_EN16:false" \
-"FIXED_PWM_POSEDGE1:0" "FIXED_PWM_POSEDGE2:0" "FIXED_PWM_POSEDGE3:0" "FIXED_PWM_POSEDGE4:0" "FIXED_PWM_POSEDGE5:0" \
-"FIXED_PWM_POSEDGE6:0" "FIXED_PWM_POSEDGE7:0" "FIXED_PWM_POSEDGE8:0" "FIXED_PWM_POSEDGE9:0" "FIXED_PWM_POSEDGE10:0" \
-"FIXED_PWM_POSEDGE11:0" "FIXED_PWM_POSEDGE12:0" "FIXED_PWM_POSEDGE13:0" "FIXED_PWM_POSEDGE14:0" "FIXED_PWM_POSEDGE15:0" \
-"FIXED_PWM_POSEDGE16:0" \
-"FIXED_PWM_POS_EN1:false" "FIXED_PWM_POS_EN2:false" "FIXED_PWM_POS_EN3:false" "FIXED_PWM_POS_EN4:false" "FIXED_PWM_POS_EN5:false" \
-"FIXED_PWM_POS_EN6:true" "FIXED_PWM_POS_EN7:true" "FIXED_PWM_POS_EN8:true" "FIXED_PWM_POS_EN9:true" "FIXED_PWM_POS_EN10:true" \
-"FIXED_PWM_POS_EN11:true" "FIXED_PWM_POS_EN12:true" "FIXED_PWM_POS_EN13:true" "FIXED_PWM_POS_EN14:true" "FIXED_PWM_POS_EN15:true" \
-"FIXED_PWM_POS_EN16:true" \
-"PWM_NUM:4" \
-"PWM_STRETCH_VALUE1:false" "PWM_STRETCH_VALUE2:false" "PWM_STRETCH_VALUE3:false" "PWM_STRETCH_VALUE4:false" "PWM_STRETCH_VALUE5:false" \
-"PWM_STRETCH_VALUE6:false" "PWM_STRETCH_VALUE7:false" "PWM_STRETCH_VALUE8:false" "PWM_STRETCH_VALUE9:false" "PWM_STRETCH_VALUE10:false" \
-"PWM_STRETCH_VALUE11:false" "PWM_STRETCH_VALUE12:false" "PWM_STRETCH_VALUE13:false" "PWM_STRETCH_VALUE14:false" "PWM_STRETCH_VALUE15:false" \
-"PWM_STRETCH_VALUE16:false" \
-"SEPARATE_PWM_CLK:false" \
-"SHADOW_REG_EN1:false" "SHADOW_REG_EN2:false" "SHADOW_REG_EN3:false" "SHADOW_REG_EN4:false" "SHADOW_REG_EN5:false" \
-"SHADOW_REG_EN6:false" "SHADOW_REG_EN7:false" "SHADOW_REG_EN8:false" "SHADOW_REG_EN9:false" \
-"SHADOW_REG_EN10:false" "SHADOW_REG_EN11:false" "SHADOW_REG_EN12:false" "SHADOW_REG_EN13:false" \
-"SHADOW_REG_EN14:false" "SHADOW_REG_EN15:false" "SHADOW_REG_EN16:false" \
-"TACHINT_ACT_LEVEL:false" \
-"TACH_EDGE1:false" "TACH_EDGE2:false" "TACH_EDGE3:false" "TACH_EDGE4:false" "TACH_EDGE5:false" \
-"TACH_EDGE6:false" "TACH_EDGE7:false" "TACH_EDGE8:false" "TACH_EDGE9:false" "TACH_EDGE10:false" \
-"TACH_EDGE11:false" "TACH_EDGE12:false" "TACH_EDGE13:false" "TACH_EDGE14:false" "TACH_EDGE15:false" \
-"TACH_EDGE16:false" \
-"TACH_NUM:1"} 
-
-sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {} 
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[3:3]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[2:2]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[1:1]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[0:0]"} 
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:APBslave} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PRESETN} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PCLK} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[0:0]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[3:3]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[2:2]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[1:1]} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_2} -new_port_name {PWM_3}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_1} -new_port_name {PWM_2}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_0} -new_port_name {PWM_1}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM} -new_port_name {PWM_0}
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE_PWM
-generate_component -component_name ${sd_name}