Libero version: Update PCIe block IP version for Libero 2022.3.

B_V_F_REFERENCE_DESIGN.tcl

@@ -136,7 +136,7 @@ download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {w
 download_core -vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SgCore:PF_DRI:1.1.104} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SgCore:PF_NGMUX:1.0.101} -location {www.microchip-ip.com/repositories/SgCore}
-download_core -vlnv {Actel:SgCore:PF_PCIE:2.0.116} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SgCore:PF_PCIE:*} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}

script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl

@@ -2,7 +2,7 @@
 # Family: PolarFireSoC
 # Part Number: MPFS025T-FCVG484E
 # Create and Configure the core component PF_PCIE_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:2.0.116} -component_name {PF_PCIE_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:*} -component_name {PF_PCIE_C0} -params {\
 "EXPOSE_ALL_DEBUG_PORTS:false"  \
 "UI_DLL_JITTER_TOLERANCE:Medium_Low"  \
 "UI_EXPOSE_LANE_DRI_PORTS:true"  \