From c8df714d6758a989daff83b36f9f92c4da74edad Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sat, 5 Mar 2022 22:00:03 +0000
Subject: [PATCH] M.2: Add remaining M.2 interface signals.
---
B_V_F_REFERENCE_DESIGN.tcl | 2 -
.../components/B_V_F_BASE_DESIGN.tcl | 16 +-
script_support/components/M2_INTERFACE.tcl | 36 ++++-
script_support/constraints/M2.pdc | 141 ++++++++++++++++++
4 files changed, 186 insertions(+), 9 deletions(-)
diff --git a/B_V_F_REFERENCE_DESIGN.tcl b/B_V_F_REFERENCE_DESIGN.tcl
index 2dc9d4c..159fb2c 100644
--- a/B_V_F_REFERENCE_DESIGN.tcl
+++ b/B_V_F_REFERENCE_DESIGN.tcl
@@ -147,7 +147,6 @@ import_files \
-io_pdc "${constraint_path}/cape.pdc" \
-io_pdc "${constraint_path}/M2.pdc" \
-io_pdc "${constraint_path}/MIPI_CSI_INTERFACE.pdc" \
- -io_pdc "${constraint_path}/ICICLE_PCIE.pdc" \
-io_pdc "${constraint_path}/ICICLE_USB.pdc"
#
@@ -160,7 +159,6 @@ organize_tool_files \
-file "${project_dir}/constraint/io/cape.pdc" \
-file "${project_dir}/constraint/io/M2.pdc" \
-file "${project_dir}/constraint/io/MIPI_CSI_INTERFACE.pdc" \
- -file "${project_dir}/constraint/io/ICICLE_PCIE.pdc" \
-file "${project_dir}/constraint/io/ICICLE_USB.pdc" \
-module {B_V_F_BASE_DESIGN::work} \
-input_type {constraint}
diff --git a/script_support/components/B_V_F_BASE_DESIGN.tcl b/script_support/components/B_V_F_BASE_DESIGN.tcl
index 4737249..205bbb0 100644
--- a/script_support/components/B_V_F_BASE_DESIGN.tcl
+++ b/script_support/components/B_V_F_BASE_DESIGN.tcl
@@ -52,7 +52,7 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD0_P} -port_
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD0_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD0_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD0_N} -port_direction {OUT} -port_is_pad {1}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_1_PERST_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PERST0n} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPI_0_CLK_M2F} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPI_0_DO_M2F} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPI_0_SS1_M2F} -port_direction {OUT}
@@ -262,10 +262,19 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:PCIe_CLK_125M
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:MSS_INT_F2M[1:1]" "M2_INTERFACE_0:PCIE_INTERRUPT"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_INTERFACE_0:PCIE_PERST_N" "PCIE_1_PERST_N"}
-
+sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_INTERFACE_0:M2_PERST0n" "M2_PERST0n"}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_PCM_OUT} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_PCM_CLK} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_PCM_SYNC} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_PCM_IN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_UART_WAKEn} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_CLKREQ0n} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_W_DISABLE1n} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_W_DISABLE2n} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_PEWAKEn} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_I2C_ALTn} -port_name {}
# Add SW1_OR_GPIO_2_28 instance
@@ -328,7 +337,6 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:I2C_0_SDA_OE_M2F" "I2
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:MSS_RESET_N_M2F" "CLOCKS_AND_RESETS:EXT_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_PLL_LOCKS:Y" "CLOCKS_AND_RESETS:MSS_PLL_LOCKS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ODT" "B_V_F_MSS:ODT" }
-#sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIE_1_PERST_N" "PCIE_1_PERST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD0_N" "M2_INTERFACE_0:PCIESS_LANE_RXD0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD0_P" "M2_INTERFACE_0:PCIESS_LANE_RXD0_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD1_N" "M2_INTERFACE_0:PCIESS_LANE_RXD1_N" }
diff --git a/script_support/components/M2_INTERFACE.tcl b/script_support/components/M2_INTERFACE.tcl
index 5cbed8a..3335818 100644
--- a/script_support/components/M2_INTERFACE.tcl
+++ b/script_support/components/M2_INTERFACE.tcl
@@ -17,7 +17,19 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_REF_CLK} -port_direct
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_INTERRUPT} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_PERST_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PERST0n} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PCM_CLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PCM_SYNC} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PCM_IN} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PCM_OUT} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_UART_WAKEn} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_CLKREQ0n} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_W_DISABLE1n} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_W_DISABLE2n} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PEWAKEn} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_I2C_ALTn} -port_direction {IN}
#-------------------------------------------------------------------------------
# Instantiate components
@@ -59,14 +71,13 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIESS_LANE3_DRI_SLAVE" "R
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_REF_CLK" "PCIE:PCIESS_LANE1_CDR_REF_CLK_0" "PCIE:PCIESS_LANE2_CDR_REF_CLK_0" "PCIE:PCIESS_LANE3_CDR_REF_CLK_0" "PCIE:PCIESS_LANE0_CDR_REF_CLK_0" }
-#sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIE_1_PERST_N" "PCIE_1_PERST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_INTERRUPT" "PCIE:PCIE_1_INTERRUPT_OUT" }
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RECONFIGURATION_INTERFACE_0:PINTERRUPT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RECONFIGURATION_INTERFACE_0:PTIMEOUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RECONFIGURATION_INTERFACE_0:BUSERROR}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PCIE_PERST_N} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {M2_PERST0n} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PCIE:PCIE_1_PERST_N} -value {VCC}
#-------------------------------------------------------------------------------
@@ -86,6 +97,25 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {PCIE:AXI_1_SLAVE} -port_na
sd_rename_port -sd_name ${sd_name} -current_port_name {AXI_1_SLAVE} -new_port_name {AXI_TARGET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RECONFIGURATION_INTERFACE_0:PLL0_SW_DRI}
+#-------------------------------------------------------------------------------
+# Temporary - rework once pin assignment confirmed.
+#-------------------------------------------------------------------------------
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND4} -instance_name {AND4_0}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:Y" "M2_PCM_OUT"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:A" "M2_PCM_CLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:B" "M2_PCM_SYNC"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:C" "M2_PCM_IN"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:D" "M2_UART_WAKEn"}
+
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "M2_W_DISABLE1n"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "M2_CLKREQ0n"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "M2_PEWAKEn"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_I2C_ALTn" "M2_W_DISABLE2n"}
+
+#-------------------------------------------------------------------------------
+
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
diff --git a/script_support/constraints/M2.pdc b/script_support/constraints/M2.pdc
index d9c3e95..09c382a 100644
--- a/script_support/constraints/M2.pdc
+++ b/script_support/constraints/M2.pdc
@@ -20,3 +20,144 @@ set_io -port_name M2_UART_RTS \
-pin_name U13 \
-fixed true \
-DIRECTION OUTPUT
+
+
+set_io -port_name M2_PCM_CLK \
+ -pin_name U19 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name M2_PCM_SYNC \
+ -pin_name T16 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name M2_PCM_IN \
+ -pin_name T17 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name M2_PCM_OUT \
+ -pin_name U17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name M2_UART_WAKEn \
+ -pin_name T15 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name M2_PERST0n \
+ -pin_name E18 \
+ -fixed true \
+ -DIRECTION OUTPUT \
+ -io_std LVCMOS33
+
+
+set_io -port_name M2_CLKREQ0n \
+ -pin_name D18 \
+ -fixed true \
+ -DIRECTION INPUT \
+ -io_std LVCMOS33
+
+
+set_io -port_name M2_W_DISABLE1n \
+ -pin_name R16 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name M2_W_DISABLE2n \
+ -pin_name R15 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name M2_PEWAKEn \
+ -pin_name R14 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name M2_I2C_ALTn \
+ -pin_name U15 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name PCIESS_LANE_RXD0_N \
+ -pin_name G19 \
+ -DIRECTION INPUT
+
+set_io -port_name PCIESS_LANE_RXD0_P \
+ -pin_name G20 \
+ -DIRECTION INPUT
+
+set_io -port_name PCIESS_LANE_RXD1_N \
+ -pin_name K21 \
+ -DIRECTION INPUT
+
+set_io -port_name PCIESS_LANE_RXD1_P \
+ -pin_name K22 \
+ -DIRECTION INPUT
+
+set_io -port_name PCIESS_LANE_RXD2_N \
+ -pin_name M21 \
+ -DIRECTION INPUT
+
+set_io -port_name PCIESS_LANE_RXD2_P \
+ -pin_name M22 \
+ -DIRECTION INPUT
+
+set_io -port_name PCIESS_LANE_RXD3_N \
+ -pin_name R19 \
+ -DIRECTION INPUT
+
+set_io -port_name PCIESS_LANE_RXD3_P \
+ -pin_name R20 \
+ -DIRECTION INPUT
+
+set_io -port_name PCIESS_LANE_TXD0_N \
+ -pin_name F21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name PCIESS_LANE_TXD0_P \
+ -pin_name F22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name PCIESS_LANE_TXD1_N \
+ -pin_name H21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name PCIESS_LANE_TXD1_P \
+ -pin_name H22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name PCIESS_LANE_TXD2_N \
+ -pin_name P21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name PCIESS_LANE_TXD2_P \
+ -pin_name P22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name PCIESS_LANE_TXD3_N \
+ -pin_name T21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name PCIESS_LANE_TXD3_P \
+ -pin_name T22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name REF_CLK_PAD_P \
+ -pin_name L19 \
+ -DIRECTION INPUT
+
+set_io -port_name REF_CLK_PAD_N \
+ -pin_name L20 \
+ -DIRECTION INPUT
--
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