From 35fe1b3a53bcaf9f375180d6dec84d0d0c9639ac Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Mon, 6 Jun 2022 18:17:52 +0100
Subject: [PATCH] Design structure: Move cape into distinct TCL script.

---
 script_support/components/ADD_CAPE.tcl        | 274 +++++++++++++++++
 .../components/B_V_F_BASE_DESIGN.tcl          | 280 ++----------------
 2 files changed, 291 insertions(+), 263 deletions(-)
 create mode 100644 script_support/components/ADD_CAPE.tcl

diff --git a/script_support/components/ADD_CAPE.tcl b/script_support/components/ADD_CAPE.tcl
new file mode 100644
index 0000000..ce31048
--- /dev/null
+++ b/script_support/components/ADD_CAPE.tcl
@@ -0,0 +1,274 @@
+set sd_name {B_V_F_BASE_DESIGN}
+
+#-------------------------------------------------------------------------------
+# Cape pins
+#-------------------------------------------------------------------------------
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_27} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_28} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_29} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_30} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_31} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_32} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_33} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_34} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_35} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_36} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_37} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_38} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_39} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_40} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_41} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_42} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_43} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_44} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_45} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_46} -port_direction {INOUT}
+
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_13} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_19} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_11} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_13} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_14} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_16} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_42} -port_direction {OUT}
+
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN37} -port_direction {IN}
+
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN23} -port_direction {IN}
+
+
+
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN38} -port_direction {OUT}
+
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {OUT}
+
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_41} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_14} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_17} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_12} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_11} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_16} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_15} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_15} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_23} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_12} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_26} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_18} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_7} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_8} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_10} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_9} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_30} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_27} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_25} -port_direction {INOUT}
+
+
+
+#-------------------------------------------------------------------------------
+# Instantiate.
+#-------------------------------------------------------------------------------
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE} -instance_name {CAPE}
+
+#-------------------------------------------------------------------------------
+# Connections.
+#-------------------------------------------------------------------------------
+
+
+# Clocks and resets
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "CAPE:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "CAPE:PRESETN" }
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MMUART_4_TXD" "P9_13"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MMUART_4_RXD" "P9_11"}
+
+# Connect Default Cape GPIOs
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[18]}
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[0:0]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_0"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[1:1]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_1"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[2:2]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_2"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[3:3]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_3"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[4:4]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_4"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[5:5]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_5"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[6:6]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_6"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[7:7]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_7"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[8:8]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_8"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[9:9]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_9"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[10:10]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_10"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[11:11]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_11"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[12:12]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_12"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[13:13]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_13"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[14:14]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_14"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[15:15]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_15"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[16:16]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_16"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[17:17]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_17"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[18:18]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_18"}
+
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[18]}
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[0:0]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_0"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[1:1]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_1"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[2:2]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_2"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[3:3]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_3"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[4:4]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_4"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[5:5]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_5"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[6:6]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_6"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[7:7]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_7"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[8:8]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_8"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[9:9]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_9"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[10:10]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_10"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[11:11]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_11"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[12:12]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_12"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[13:13]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_13"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[14:14]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_14"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[15:15]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_15"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[16:16]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_16"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[17:17]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_17"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[18:18]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_18"}
+
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[18]}
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[0:0]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_0"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[1:1]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_1"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[2:2]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_2"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[3:3]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_3"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[4:4]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_4"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[5:5]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_5"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[6:6]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_6"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[7:7]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_7"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[8:8]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_8"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[9:9]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_9"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[10:10]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_10"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[11:11]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_11"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[12:12]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_12"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[13:13]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_13"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[14:14]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_14"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[15:15]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_15"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[16:16]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_16"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[17:17]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_17"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[18:18]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_18"}
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_41" "P9_41"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_14" "P8_14"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_17" "P8_17"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_12" "P8_12"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_11" "P8_11"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_16" "P8_16"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_15" "P8_15"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_15" "P9_15"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_23" "P9_23"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_12" "P9_12"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_26" "P8_26"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_18" "P8_18"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_7" "P8_7"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_8" "P8_8"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_10" "P8_10"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_9" "P8_9"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_30" "P9_30"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_27" "P9_27"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_25" "P9_25"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_27" "P8_27"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_28" "P8_28"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_29" "P8_29"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_30" "P8_30"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_31" "P8_31"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_32" "P8_32"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_33" "P8_33"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_34" "P8_34"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_35" "P8_35"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_36" "P8_36"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_37" "P8_37"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_38" "P8_38"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_39" "P8_39"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_40" "P8_40"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_41" "P8_41"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_42" "P8_42"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_43" "P8_43"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_44" "P8_44"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_45" "P8_45"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_46" "P8_46"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_13" "P8_13"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_19" "P8_19"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_14" "P9_14"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_16" "P9_16"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_42" "P9_42"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
+
diff --git a/script_support/components/B_V_F_BASE_DESIGN.tcl b/script_support/components/B_V_F_BASE_DESIGN.tcl
index 29b96d3..b53ccac 100644
--- a/script_support/components/B_V_F_BASE_DESIGN.tcl
+++ b/script_support/components/B_V_F_BASE_DESIGN.tcl
@@ -77,6 +77,9 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT}
 sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
 sd_create_bus_port -sd_name ${sd_name} -port_name {DM} -port_direction {OUT} -port_range {[3:0]} -port_is_pad {1}
 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_19} -port_direction {INOUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_20} -port_direction {INOUT}
+
 
 #-------------------------------------------------------------------------------
 # Analog to Digital Converter pins (for cape analog inputs)
@@ -88,83 +91,6 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_MISO} -port_direction
 sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_IRQn} -port_direction {IN}
 sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_MCLK} -port_direction {OUT}
 
-#-------------------------------------------------------------------------------
-# Cape pins
-#-------------------------------------------------------------------------------
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_27} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_28} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_29} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_30} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_31} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_32} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_33} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_34} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_35} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_36} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_37} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_38} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_39} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_40} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_41} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_42} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_43} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_44} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_45} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_46} -port_direction {INOUT}
-
-
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_13} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_19} -port_direction {OUT}
-
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_11} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_13} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_14} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_16} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_42} -port_direction {OUT}
-
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_19} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_20} -port_direction {INOUT}
-
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN37} -port_direction {IN}
-
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN23} -port_direction {IN}
-
-
-
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN38} -port_direction {OUT}
-
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {OUT}
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {OUT}
-
-
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_41} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_14} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_17} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_12} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_11} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_16} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_15} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_15} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_23} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_12} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_26} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_18} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_7} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_8} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_10} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_9} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_30} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_27} -port_direction {INOUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_25} -port_direction {INOUT}
 
 #-------------------------------------------------------------------------------
 # Ethernet PHY top level ports
@@ -185,9 +111,6 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {BVF_RISCV_SUBSYSTE
 # Add CLOCKS_AND_RESETS instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {CLOCKS_AND_RESETS} -instance_name {CLOCKS_AND_RESETS}
 
-# Add Default Cape GPIOs
-sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE} -instance_name {CAPE}
-
 
 # Add FIC0_INITIATOR instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {FIC0_INITIATOR} -instance_name {FIC0_INITIATOR}
@@ -258,9 +181,11 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_INTERFACE_0:USB1_DATA7" "USB
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_0_ACLK" "BVF_RISCV_SUBSYSTEM:FIC_0_ACLK" "FIC0_INITIATOR:ACLK"}
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_1_ACLK" "BVF_RISCV_SUBSYSTEM:FIC_1_ACLK"}
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_2_ACLK" "BVF_RISCV_SUBSYSTEM:FIC_2_ACLK"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "BVF_RISCV_SUBSYSTEM:FIC_3_PCLK" "CAPE:PCLK"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "BVF_RISCV_SUBSYSTEM:FIC_3_PCLK" "CAPE:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "BVF_RISCV_SUBSYSTEM:FIC_3_PCLK"}
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_0_FABRIC_RESET_N" "USB1_RESETB" "USB0_RESETB" "FIC0_INITIATOR:ARESETN" "PHY_RSTn"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "BVF_RISCV_SUBSYSTEM:presetn" "CAPE:PRESETN" }
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "BVF_RISCV_SUBSYSTEM:presetn" "CAPE:PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "BVF_RISCV_SUBSYSTEM:presetn"}
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CLOCKS_AND_RESETS:FIC_1_FABRIC_RESET_N}
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CLOCKS_AND_RESETS:FIC_2_FABRIC_RESET_N}
 
@@ -399,187 +324,6 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "BVF_RISCV_SUBSYSTEM:DQS
 sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC0_INITIATOR:AXI4mmaster0" "BVF_RISCV_SUBSYSTEM:FIC_0_AXI4_INITIATOR" }
 
 
-#-------------------------------------------------------------------------------
-# Cape
-#-------------------------------------------------------------------------------
-sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MMUART_4_TXD" "P9_13"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MMUART_4_RXD" "P9_11"}
-
-# Connect Default Cape GPIOs
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[0]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[1]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[2]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[3]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[4]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[5]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[6]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[7]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[8]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[9]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[10]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[11]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[12]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[13]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[14]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[15]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[16]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[17]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OE} -pin_slices {[18]}
-
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[0:0]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_0"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[1:1]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_1"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[2:2]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_2"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[3:3]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_3"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[4:4]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_4"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[5:5]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_5"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[6:6]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_6"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[7:7]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_7"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[8:8]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_8"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[9:9]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_9"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[10:10]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_10"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[11:11]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_11"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[12:12]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_12"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[13:13]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_13"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[14:14]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_14"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[15:15]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_15"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[16:16]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_16"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[17:17]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_17"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OE[18:18]" "BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F_18"}
-
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[0]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[1]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[2]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[3]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[4]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[5]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[6]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[7]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[8]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[9]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[10]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[11]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[12]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[13]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[14]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[15]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[16]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[17]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_OUT} -pin_slices {[18]}
-
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[0:0]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_0"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[1:1]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_1"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[2:2]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_2"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[3:3]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_3"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[4:4]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_4"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[5:5]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_5"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[6:6]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_6"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[7:7]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_7"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[8:8]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_8"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[9:9]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_9"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[10:10]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_10"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[11:11]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_11"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[12:12]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_12"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[13:13]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_13"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[14:14]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_14"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[15:15]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_15"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[16:16]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_16"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[17:17]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_17"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_OUT[18:18]" "BVF_RISCV_SUBSYSTEM:GPIO_2_M2F_18"}
-
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[0]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[1]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[2]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[3]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[4]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[5]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[6]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[7]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[8]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[9]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[10]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[11]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[12]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[13]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[14]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[15]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[16]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[17]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CAPE:GPIO_IN} -pin_slices {[18]}
-
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[0:0]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_0"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[1:1]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_1"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[2:2]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_2"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[3:3]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_3"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[4:4]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_4"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[5:5]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_5"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[6:6]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_6"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[7:7]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_7"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[8:8]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_8"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[9:9]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_9"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[10:10]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_10"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[11:11]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_11"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[12:12]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_12"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[13:13]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_13"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[14:14]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_14"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[15:15]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_15"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[16:16]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_16"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[17:17]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_17"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:GPIO_IN[18:18]" "BVF_RISCV_SUBSYSTEM:GPIO_2_F2M_18"}
-
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_41" "P9_41"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_14" "P8_14"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_17" "P8_17"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_12" "P8_12"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_11" "P8_11"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_16" "P8_16"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_15" "P8_15"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_15" "P9_15"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_23" "P9_23"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_12" "P9_12"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_26" "P8_26"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_18" "P8_18"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_7" "P8_7"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_8" "P8_8"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_10" "P8_10"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_9" "P8_9"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_30" "P9_30"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_27" "P9_27"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_25" "P9_25"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_27" "P8_27"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_28" "P8_28"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_29" "P8_29"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_30" "P8_30"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_31" "P8_31"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_32" "P8_32"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_33" "P8_33"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_34" "P8_34"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_35" "P8_35"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_36" "P8_36"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_37" "P8_37"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_38" "P8_38"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_39" "P8_39"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_40" "P8_40"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_41" "P8_41"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_42" "P8_42"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_43" "P8_43"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_44" "P8_44"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_45" "P8_45"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_46" "P8_46"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_13" "P8_13"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_19" "P8_19"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_14" "P9_14"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_16" "P9_16"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_42" "P9_42"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
 
 #-------------------------------------------------------------------------------
 # MIPI CSI-2 RX interface
@@ -632,6 +376,16 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {FIC0_INITIATOR:AXI4mslave1}
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {FIC0_INITIATOR:AXI4mslave2}
 
 
+#-------------------------------------------------------------------------------
+
+source script_support/components//ADD_CAPE.tcl 
+
+
+#-------------------------------------------------------------------------------
+
+
+
+
 # Re-enable auto promotion of pins of type 'pad'
 auto_promote_pad_pins -promote_all 1
 # Save the smartDesign
-- 
GitLab