diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/ADD_HIGH_SPEED_CONNECTOR.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/ADD_HIGH_SPEED_CONNECTOR.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1514892356ca6fe4fda7d5f51fe9ae59ae5f0641
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/ADD_HIGH_SPEED_CONNECTOR.tcl
@@ -0,0 +1,117 @@
+
+puts "======== Add High Speed Connector option: BOARD_VALIDATION_SEEED_STUDIO ========"
+
+# Import source files
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/pattern_chk.v}
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/pattern_gen.v}
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/startup.v}
+
+build_design_hierarchy
+create_hdl_core -file $project_dir/hdl/startup.v -module {STARTUP} -library {work} -package {}
+create_hdl_core -file $project_dir/hdl/pattern_chk.v -module {PATTERN_CHK} -library {work} -package {}
+create_hdl_core -file $project_dir/hdl/pattern_gen.v -module {PATTERN_GEN} -library {work} -package {}
+
+
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CCC_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_sync_rx.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_sync_tx.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_Block.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
+
+
+
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_CCC_C1.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_XCVR_REF_CLK_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HSIO_CoreGPIO_C0.tcl
+#source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HSIO_PWM_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HIGH_SPEED_INTERFACE.tcl
+
+
+
+
+set sd_name {B_V_F_BASE_DESIGN}
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {HIGH_SPEED_INTERFACE} -instance_name {HIGH_SPEED_INTERFACE_0}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_RESET_N_M2F" "HIGH_SPEED_INTERFACE_0:EXT_RST_N"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "HIGH_SPEED_INTERFACE_0:DEVICE_INIT_DONE"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:XCVR_INIT_DONE" "HIGH_SPEED_INTERFACE_0:XCVR_INIT_DONE"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:RCOSC_160MHZ_GL" "HIGH_SPEED_INTERFACE_0:RCOSC_160MHZ_GL"}
+
+
+sd_delete_nets -sd_name ${sd_name} -net_names {BVF_RISCV_SUBSYSTEM_USER_LED_GPIO_OUT}
+sd_delete_nets -sd_name ${sd_name} -net_names {BVF_RISCV_SUBSYSTEM_USER_LED_GPIO_OE}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_OE}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {USER_LED_PADS_0:USER_LED_GPIO_OE} -value {VCC}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[0:0]"}
+
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_RX_VALID" "USER_LED_PADS_0:USER_LED_GPIO_OUT[3:3]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_LOCK" "USER_LED_PADS_0:USER_LED_GPIO_OUT[4:4]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_ERROR" "USER_LED_PADS_0:USER_LED_GPIO_OUT[5:5]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_RX_VALID" "USER_LED_PADS_0:USER_LED_GPIO_OUT[6:6]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_LOCK" "USER_LED_PADS_0:USER_LED_GPIO_OUT[7:7]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_ERROR" "USER_LED_PADS_0:USER_LED_GPIO_OUT[8:8]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:TEST_MODE_0_LED" "USER_LED_PADS_0:USER_LED_GPIO_OUT[9:9]"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0C_REFCLK_PLL_LOCK" "USER_LED_PADS_0:USER_LED_GPIO_OUT[11:11]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0C_REFCLK_CCC_OUT" "USER_LED_PADS_0:USER_LED_GPIO_OUT[10:10]"}
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_3_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_2_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_1_LED}
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO82P} -port_name {}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDI_F2M}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDI_F2M" "HIGH_SPEED_INTERFACE_0:MAC_1_MDI_F2M"}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDO_M2F}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDO_OE_M2F}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDC_M2F}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDC_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDC_M2F"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDO_OE_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDO_OE_M2F"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDO_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDO_M2F"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "HIGH_SPEED_INTERFACE_0:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "HIGH_SPEED_INTERFACE_0:PRESETN"}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:HSI_APB_MTARGET}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:HSI_APB_MTARGET" "HIGH_SPEED_INTERFACE_0:APB_TARGET"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_0_FABRIC_RESET_N" "HIGH_SPEED_INTERFACE_0:SYS_RESET_N"}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO83N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO70P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO71P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO73P_C2P_CLKP} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO81N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO83P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO70N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO71N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO73N_C2P_CLKN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO81P} -port_name {}
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {USER_LED_PADS_0:USER_LED_GPIO_OUT[0:0]} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {USER_LED_PADS_0:USER_LED_GPIO_OUT[2:2]} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {USER_LED_PADS_0:USER_LED_GPIO_OUT[1:1]} -value {GND}
+
+# Override software control of VIO.
+sd_delete_nets -sd_name ${sd_name} -net_names {VIO_ENABLE}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:VIO_ENABLE}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VIO_ENABLE} -value {VCC}
+
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HIGH_SPEED_INTERFACE.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HIGH_SPEED_INTERFACE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..fbbf0237d4de16168b38e2d5280155b48504ada5
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HIGH_SPEED_INTERFACE.tcl
@@ -0,0 +1,258 @@
+# Creating SmartDesign HIGH_SPEED_INTERFACE
+set sd_name {HIGH_SPEED_INTERFACE}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO70P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO71P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO73P_C2P_CLKP} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO81N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO83P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDC_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDO_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDO_OE_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RCOSC_160MHZ_GL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_RESET_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REFCLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REFCLK_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX2_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX2_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX3_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX3_P} -port_direction {IN} -port_is_pad {1}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO70N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO71N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO73N_C2P_CLKN} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO81P} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO82P} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO83N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDI_F2M} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_0_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_1_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_2_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_3_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_RX_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_RX_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_CCC_OUT} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_PLL_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX2_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX2_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX3_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX3_P} -port_direction {OUT} -port_is_pad {1}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO82N} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_TARGET} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_TARGET_PADDR" \
+"PSELx:APB_TARGET_PSEL" \
+"PENABLE:APB_TARGET_PENABLE" \
+"PWRITE:APB_TARGET_PWRITE" \
+"PRDATA:APB_TARGET_PRDATA" \
+"PWDATA:APB_TARGET_PWDATA" \
+"PREADY:APB_TARGET_PREADY" \
+"PSLVERR:APB_TARGET_PSLVERR" }
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add BIBUF_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}
+
+
+
+# Add HSIO_CoreGPIO_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {HSIO_CoreGPIO_C0} -instance_name {HSIO_CoreGPIO_C0_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[13:13]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[13:13]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[14:14]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[14:14]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[4:4]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[4:4]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[5:5]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[5:5]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[6:6]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[6:6]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:INT}
+
+
+
+# Add PF_CCC_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {PF_CCC_C0_0}
+
+
+
+# Add PF_CCC_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C1} -instance_name {PF_CCC_C1_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_CCC_C1_0:PLL_POWERDOWN_N_0} -value {VCC}
+
+
+
+# Add PF_CLK_DIV_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0}
+
+
+
+# Add PF_TX_PLL_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_0} -instance_name {PF_TX_PLL_0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_0_0:CLK_125}
+
+
+
+# Add PF_XCVR_REF_CLK_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_0} -instance_name {PF_XCVR_REF_CLK_0_0}
+
+
+
+# Add PF_XCVR_REF_CLK_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_REF_CLK_C0_0:REF_CLK}
+
+
+
+# Add XCVR_LOOPBACK_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_LOOPBACK} -instance_name {XCVR_LOOPBACK_0}
+
+
+
+# Add XCVR_LOOPBACK_2 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_LOOPBACK} -instance_name {XCVR_LOOPBACK_2}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_0_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_1_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_2_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_3_LED}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_CCC_C0_0:PLL_LOCK_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "PF_TX_PLL_0_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "XCVR_LOOPBACK_0:XCVR_REF_CLK_LOCK" "XCVR_LOOPBACK_2:XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70P" "HSIO_CoreGPIO_C0_0:GPIO_IN[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71P" "HSIO_CoreGPIO_C0_0:GPIO_IN[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73N_C2P_CLKN" "HSIO_CoreGPIO_C0_0:GPIO_OUT[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73P_C2P_CLKP" "HSIO_CoreGPIO_C0_0:GPIO_IN[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81N" "HSIO_CoreGPIO_C0_0:GPIO_IN[15:15]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81P" "SYS_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO82N" "BIBUF_0:PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO82P" "MAC_1_MDC_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83P" "HSIO_CoreGPIO_C0_0:GPIO_IN[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:D" "MAC_1_MDO_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "MAC_1_MDO_OE_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "MAC_1_MDI_F2M" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "XCVR_LOOPBACK_0:DEVICE_INIT_DONE" "XCVR_LOOPBACK_2:DEVICE_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "XCVR_LOOPBACK_0:EXT_RST_N" "XCVR_LOOPBACK_2:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[10:10]" "XCVR3_RX_VALID" "XCVR_LOOPBACK_0:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[11:11]" "XCVR3_LOCK" "XCVR_LOOPBACK_0:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[12:12]" "XCVR3_ERROR" "XCVR_LOOPBACK_0:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[7:7]" "XCVR2_RX_VALID" "XCVR_LOOPBACK_2:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[8:8]" "XCVR2_LOCK" "XCVR_LOOPBACK_2:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[9:9]" "XCVR2_ERROR" "XCVR_LOOPBACK_2:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:OUT0_FABCLK_0" "PF_TX_PLL_0_0:FAB_REF_CLK" "XCVR_LOOPBACK_0:XCVR_REF_CLK" "XCVR_LOOPBACK_2:XCVR_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:REF_CLK_0" "PF_XCVR_REF_CLK_0_0:REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:OUT0_FABCLK_0" "XCVR_0C_REFCLK_CCC_OUT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:PLL_LOCK_0" "XCVR_0C_REFCLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:FAB_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_IN" "RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_OUT" "XCVR_LOOPBACK_0:RCOSC_160MHZ_GL" "XCVR_LOOPBACK_2:RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_N" "XCVR_0B_REFCLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_P" "XCVR_0B_REFCLK_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "XCVR_0C_REFCLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "XCVR_0C_REFCLK_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_0_LED" "XCVR_LOOPBACK_0:TEST_MODE_0_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_1_LED" "XCVR_LOOPBACK_0:TEST_MODE_1_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_2_LED" "XCVR_LOOPBACK_0:TEST_MODE_2_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_3_LED" "XCVR_LOOPBACK_0:TEST_MODE_3_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_INIT_DONE" "XCVR_LOOPBACK_0:XCVR_INIT_DONE" "XCVR_LOOPBACK_2:XCVR_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_0:LANE0_RXD_N" "XCVR_RX3_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_0:LANE0_RXD_P" "XCVR_RX3_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_0:LANE0_TXD_N" "XCVR_TX3_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_0:LANE0_TXD_P" "XCVR_TX3_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_RXD_N" "XCVR_RX2_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_RXD_P" "XCVR_RX2_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_TXD_N" "XCVR_TX2_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_TXD_P" "XCVR_TX2_P" }
+
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_TARGET" "HSIO_CoreGPIO_C0_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_0_0:CLKS_TO_XCVR" "XCVR_LOOPBACK_0:CLKS_FROM_TXPLL_0" "XCVR_LOOPBACK_2:CLKS_FROM_TXPLL_0" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign HIGH_SPEED_INTERFACE
+generate_component -component_name ${sd_name}
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HSIO_CoreGPIO_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HSIO_CoreGPIO_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c766113412c5e253a31e1da2918467ab2597479f
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/HSIO_CoreGPIO_C0.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of HSIO_CoreGPIO_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component HSIO_CoreGPIO_C0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {HSIO_CoreGPIO_C0} -params {\
+"APB_WIDTH:32" \
+"FIXED_CONFIG_0:true" \
+"FIXED_CONFIG_1:true" \
+"FIXED_CONFIG_2:true" \
+"FIXED_CONFIG_3:true" \
+"FIXED_CONFIG_4:true" \
+"FIXED_CONFIG_5:true" \
+"FIXED_CONFIG_6:true" \
+"FIXED_CONFIG_7:true" \
+"FIXED_CONFIG_8:true" \
+"FIXED_CONFIG_9:true" \
+"FIXED_CONFIG_10:true" \
+"FIXED_CONFIG_11:true" \
+"FIXED_CONFIG_12:true" \
+"FIXED_CONFIG_13:true" \
+"FIXED_CONFIG_14:true" \
+"FIXED_CONFIG_15:true" \
+"FIXED_CONFIG_16:false" \
+"FIXED_CONFIG_17:false" \
+"FIXED_CONFIG_18:false" \
+"FIXED_CONFIG_19:false" \
+"FIXED_CONFIG_20:false" \
+"FIXED_CONFIG_21:false" \
+"FIXED_CONFIG_22:false" \
+"FIXED_CONFIG_23:false" \
+"FIXED_CONFIG_24:false" \
+"FIXED_CONFIG_25:false" \
+"FIXED_CONFIG_26:false" \
+"FIXED_CONFIG_27:false" \
+"FIXED_CONFIG_28:false" \
+"FIXED_CONFIG_29:false" \
+"FIXED_CONFIG_30:false" \
+"FIXED_CONFIG_31:false" \
+"INT_BUS:0" \
+"IO_INT_TYPE_0:7" \
+"IO_INT_TYPE_1:7" \
+"IO_INT_TYPE_2:7" \
+"IO_INT_TYPE_3:7" \
+"IO_INT_TYPE_4:7" \
+"IO_INT_TYPE_5:7" \
+"IO_INT_TYPE_6:7" \
+"IO_INT_TYPE_7:7" \
+"IO_INT_TYPE_8:7" \
+"IO_INT_TYPE_9:7" \
+"IO_INT_TYPE_10:7" \
+"IO_INT_TYPE_11:7" \
+"IO_INT_TYPE_12:7" \
+"IO_INT_TYPE_13:7" \
+"IO_INT_TYPE_14:7" \
+"IO_INT_TYPE_15:7" \
+"IO_INT_TYPE_16:7" \
+"IO_INT_TYPE_17:7" \
+"IO_INT_TYPE_18:7" \
+"IO_INT_TYPE_19:7" \
+"IO_INT_TYPE_20:7" \
+"IO_INT_TYPE_21:7" \
+"IO_INT_TYPE_22:7" \
+"IO_INT_TYPE_23:7" \
+"IO_INT_TYPE_24:7" \
+"IO_INT_TYPE_25:7" \
+"IO_INT_TYPE_26:7" \
+"IO_INT_TYPE_27:7" \
+"IO_INT_TYPE_28:7" \
+"IO_INT_TYPE_29:7" \
+"IO_INT_TYPE_30:7" \
+"IO_INT_TYPE_31:7" \
+"IO_NUM:16" \
+"IO_TYPE_0:2" \
+"IO_TYPE_1:2" \
+"IO_TYPE_2:2" \
+"IO_TYPE_3:2" \
+"IO_TYPE_4:2" \
+"IO_TYPE_5:2" \
+"IO_TYPE_6:2" \
+"IO_TYPE_7:2" \
+"IO_TYPE_8:2" \
+"IO_TYPE_9:2" \
+"IO_TYPE_10:2" \
+"IO_TYPE_11:2" \
+"IO_TYPE_12:2" \
+"IO_TYPE_13:2" \
+"IO_TYPE_14:2" \
+"IO_TYPE_15:2" \
+"IO_TYPE_16:0" \
+"IO_TYPE_17:0" \
+"IO_TYPE_18:0" \
+"IO_TYPE_19:0" \
+"IO_TYPE_20:0" \
+"IO_TYPE_21:0" \
+"IO_TYPE_22:0" \
+"IO_TYPE_23:0" \
+"IO_TYPE_24:0" \
+"IO_TYPE_25:0" \
+"IO_TYPE_26:0" \
+"IO_TYPE_27:0" \
+"IO_TYPE_28:0" \
+"IO_TYPE_29:0" \
+"IO_TYPE_30:0" \
+"IO_TYPE_31:0" \
+"IO_VAL_0:0" \
+"IO_VAL_1:0" \
+"IO_VAL_2:0" \
+"IO_VAL_3:0" \
+"IO_VAL_4:0" \
+"IO_VAL_5:0" \
+"IO_VAL_6:0" \
+"IO_VAL_7:0" \
+"IO_VAL_8:0" \
+"IO_VAL_9:0" \
+"IO_VAL_10:0" \
+"IO_VAL_11:0" \
+"IO_VAL_12:0" \
+"IO_VAL_13:0" \
+"IO_VAL_14:0" \
+"IO_VAL_15:0" \
+"IO_VAL_16:0" \
+"IO_VAL_17:0" \
+"IO_VAL_18:0" \
+"IO_VAL_19:0" \
+"IO_VAL_20:0" \
+"IO_VAL_21:0" \
+"IO_VAL_22:0" \
+"IO_VAL_23:0" \
+"IO_VAL_24:0" \
+"IO_VAL_25:0" \
+"IO_VAL_26:0" \
+"IO_VAL_27:0" \
+"IO_VAL_28:0" \
+"IO_VAL_29:0" \
+"IO_VAL_30:0" \
+"IO_VAL_31:0" \
+"OE_TYPE:0" }
+# Exporting Component Description of HSIO_CoreGPIO_C0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_CCC_C1.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_CCC_C1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..80c6d891a1dba3234089dae034d704247ce98884
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_CCC_C1.tcl
@@ -0,0 +1,249 @@
+# Exporting Component Description of PF_CCC_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_CCC_C1
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.214} -component_name {PF_CCC_C1} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:133" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:12" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:25" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:2" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:true" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:125" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:8" \
+"PLL_LOCK_COUNT_1:8" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:1" \
+"PLL_REFDIV_1:1" \
+"PLL_RESET_ON_LOCK_0:true" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_C1 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_XCVR_REF_CLK_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_XCVR_REF_CLK_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e8dc11d935415b2de275f5d20811d9e3493a7727
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_XCVR_REF_CLK_C0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_XCVR_REF_CLK_C0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
+"ENABLE_FAB_CLK_0:true" \
+"ENABLE_FAB_CLK_1:false" \
+"ENABLE_REF_CLK_0:true" \
+"ENABLE_REF_CLK_1:false" \
+"REF_CLK_MODE_0:DIFFERENTIAL" \
+"REF_CLK_MODE_1:LVCMOS" }
+# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CCC_01.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CCC_01.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8598cc9a6acf1070bd8ea93f98f3ee2d4095d2d2
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CCC_01.tcl
@@ -0,0 +1,248 @@
+# Exporting Component Description of PF_CCC_01 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_CCC_01
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CCC:$PF_CCCver -component_name {PF_CCC_01} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:1" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:10" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:125" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:0" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:false" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:160" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:0" \
+"PLL_LOCK_COUNT_1:0" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:4" \
+"PLL_REFDIV_1:1" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_01 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CCC_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CCC_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..25176efffbdbbca9432bfef9a4796c096379703b
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CCC_C0.tcl
@@ -0,0 +1,249 @@
+# Exporting Component Description of PF_CCC_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_CCC_C0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.214} -component_name {PF_CCC_C0} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:133" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:8" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:156.25" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:2" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:false" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:100" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:8" \
+"PLL_LOCK_COUNT_1:8" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:1" \
+"PLL_REFDIV_1:1" \
+"PLL_RESET_ON_LOCK_0:true" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_C0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c4e5dec04541294c821ace45859f296e784aadbc
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
@@ -0,0 +1,9 @@
+# Exporting Component Description of PF_CLK_DIV_C0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_CLK_DIV_C0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:1.0.103 -component_name {PF_CLK_DIV_C0} -params {\
+"DIVIDER:4" \
+"ENABLE_BIT_SLIP:false" \
+"ENABLE_SRESET:false" }
+# Exporting Component Description of PF_CLK_DIV_C0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_OSC_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_OSC_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..88eb2d4072a45ccdda19a665e4fcebd20be9ef48
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_OSC_0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_OSC_0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_OSC_0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_OSC:1.0.102 -component_name {PF_OSC_0} -params {\
+"RCOSC_2MHZ_CLK_DIV_EN:false" \
+"RCOSC_2MHZ_GL_EN:false" \
+"RCOSC_2MHZ_NGMUX_EN:false" \
+"RCOSC_160MHZ_CLK_DIV_EN:false" \
+"RCOSC_160MHZ_GL_EN:true" \
+"RCOSC_160MHZ_NGMUX_EN:false" }
+# Exporting Component Description of PF_OSC_0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_TX_PLL_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d13849b11c0207d5003568859480bc98aeae07b0
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
@@ -0,0 +1,35 @@
+# Exporting Component Description of PF_TX_PLL_0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_TX_PLL_0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_0} -params {\
+"CORE:PF_TX_PLL" \
+"INIT:0x0" \
+"TxPLL_AUX_LOW_SEL:true" \
+"TxPLL_AUX_OUT:125" \
+"TxPLL_BANDWIDTH:Low" \
+"TxPLL_CLK_125_EN:true" \
+"TxPLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"TxPLL_EXT_WAVE_SEL:0" \
+"TxPLL_FAB_LOCK_EN:false" \
+"TxPLL_FAB_REF:200" \
+"TxPLL_INTEGER_MODE:false" \
+"TxPLL_JITTER_MODE_AT_POWERUP:true" \
+"TxPLL_JITTER_MODE_CUT_OFF_FREQ:5000" \
+"TxPLL_JITTER_MODE_OPTIMIZE_FOR:0" \
+"TxPLL_JITTER_MODE_REFCLK_FREQ:125" \
+"TxPLL_JITTER_MODE_REFCLK_SEL:DEDICATED" \
+"TxPLL_JITTER_MODE_SEL:10G SyncE 32Bit" \
+"TxPLL_JITTER_MODE_WANDER:15" \
+"TxPLL_MODE:NORMAL" \
+"TxPLL_OUT:2500.000" \
+"TxPLL_REF:156.25" \
+"TxPLL_RN_FILTER:false" \
+"TxPLL_SOURCE:FABRIC" \
+"TxPLL_SSM_DEPTH:0" \
+"TxPLL_SSM_DIVVAL:1" \
+"TxPLL_SSM_DOWN_SPREAD:false" \
+"TxPLL_SSM_FREQ:64" \
+"TxPLL_SSM_RAND_PATTERN:0" \
+"VCOFREQUENCY:1600" }
+# Exporting Component Description of PF_TX_PLL_0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..efa10b031f536d45ba96950ef37298d62a198287
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_0.tcl
@@ -0,0 +1,55 @@
+# Exporting Component Description of PF_XCVR_0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_XCVR_0
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_0} -params {\
+"EXPOSE_ALL_DEBUG_PORTS:false" \
+"EXPOSE_FWF_EN_PORTS:false" \
+"SHOW_UNIVERSAL_SOLN_PORTS:true" \
+"UI_CDR_LOCK_MODE:Lock to data" \
+"UI_CDR_REFERENCE_CLK_FREQ:156.25" \
+"UI_CDR_REFERENCE_CLK_SOURCE:Fabric" \
+"UI_CDR_REFERENCE_CLK_TOLERANCE:1" \
+"UI_ENABLE_32BIT_DATA_WIDTH:false" \
+"UI_ENABLE_64B66B:true" \
+"UI_ENABLE_64B67B:false" \
+"UI_ENABLE_64B6XB_MODE:false" \
+"UI_ENABLE_8B10B_MODE:true" \
+"UI_ENABLE_BER:false" \
+"UI_ENABLE_DISPARITY:false" \
+"UI_ENABLE_FIBRE_CHANNEL_DISPARITY:false" \
+"UI_ENABLE_PHASE_COMP_MODE:false" \
+"UI_ENABLE_PIPE_MODE:false" \
+"UI_ENABLE_PMA_MODE:false" \
+"UI_ENABLE_SCRAMBLING:false" \
+"UI_ENABLE_SWITCH_BETWEEN_CDR_REFCLKS:false" \
+"UI_ENABLE_SWITCH_BETWEEN_TXPLLS:false" \
+"UI_EXPOSE_APBLINK_PORTS:false" \
+"UI_EXPOSE_CDR_BITSLIP_PORT:false" \
+"UI_EXPOSE_DYNAMIC_RECONFIGURATION_PORTS:false" \
+"UI_EXPOSE_JA_CLOCK_PORT:false" \
+"UI_EXPOSE_RX_READY_VAL_CDR_PORT:false" \
+"UI_EXPOSE_TX_BYPASS_DATA:false" \
+"UI_EXPOSE_TX_ELEC_IDLE:false" \
+"UI_INTERFACE_RXCLOCK:Regional" \
+"UI_INTERFACE_TXCLOCK:Regional" \
+"UI_IS_CONFIGURED:true" \
+"UI_NUMBER_OF_LANES:1" \
+"UI_PCS_ARST_N:RX Only" \
+"UI_PIPE_PROTOCOL_USED:PCIe" \
+"UI_PMA_ARST_N:TX and RX PMA" \
+"UI_PROTOCOL_PRESET_USED:None" \
+"UI_RX_DATA_RATE:5000" \
+"UI_RX_PCS_FAB_IF_WIDTH:32" \
+"UI_SATA_IDLE_BURST_TIMING:MAC" \
+"UI_TX_CLK_DIV_FACTOR:1" \
+"UI_TX_DATA_RATE:5000" \
+"UI_TX_PCS_FAB_IF_WIDTH:32" \
+"UI_TX_RX_MODE:Duplex" \
+"UI_USE_INTERFACE_CLK_AS_PLL_REFCLK:false" \
+"UI_XCVR_RX_CALIBRATION:None (CDR)" \
+"UI_XCVR_RX_DATA_EYE_CALIBRATION:false" \
+"UI_XCVR_RX_DFE_COEFF_CALIBRATION:false" \
+"UI_XCVR_RX_ENHANCED_MANAGEMENT:true" \
+"XT_ES_DEVICE:false" }
+# Exporting Component Description of PF_XCVR_0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ea07e4507db8fbbaefb9664e73236980cad6b8b0
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_XCVR_REF_CLK_0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_XCVR_REF_CLK_0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:1.0.103 -component_name {PF_XCVR_REF_CLK_0} -params {\
+"ENABLE_FAB_CLK_0:false" \
+"ENABLE_FAB_CLK_1:false" \
+"ENABLE_REF_CLK_0:true" \
+"ENABLE_REF_CLK_1:false" \
+"REF_CLK_MODE_0:DIFFERENTIAL" \
+"REF_CLK_MODE_1:LVCMOS" }
+# Exporting Component Description of PF_XCVR_REF_CLK_0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_Block.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_Block.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..56de848720c5d43c065759644c92e70c6782d462
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_Block.tcl
@@ -0,0 +1,66 @@
+puts "vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv"
+puts "vvvvvvvvvvvvvvvvvvvvvv Create Transceivers Reset Block vvvvvvvvvvvvvvvvvvvvvvv"
+puts "vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv"
+
+# Creating SmartDesign Reset_Block
+set sd_name {Reset_Block}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_x_VDDI_STATUS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_y_VDDI_STATUS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_clk} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_ready} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_clk_stable} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_clk} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {Pattern_chk_rst_n} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {Pattern_gen_rst_n} -port_direction {OUT}
+
+
+
+# Add Reset_sync_rx_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_sync_rx} -instance_name {Reset_sync_rx_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:PLL_POWERDOWN_B}
+
+
+
+# Add Reset_sync_tx_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_sync_tx} -instance_name {Reset_sync_tx_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:PLL_POWERDOWN_B}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BANK_x_VDDI_STATUS" "Reset_sync_rx_0:BANK_x_VDDI_STATUS" "Reset_sync_tx_0:BANK_x_VDDI_STATUS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BANK_y_VDDI_STATUS" "Reset_sync_rx_0:BANK_y_VDDI_STATUS" "Reset_sync_tx_0:BANK_y_VDDI_STATUS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "Reset_sync_rx_0:EXT_RST_N" "Reset_sync_tx_0:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_DONE" "Reset_sync_rx_0:INIT_DONE" "Reset_sync_tx_0:INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Pattern_chk_rst_n" "Reset_sync_rx_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Pattern_gen_rst_n" "Reset_sync_tx_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RX_clk" "Reset_sync_rx_0:CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RX_ready" "Reset_sync_rx_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_sync_tx_0:CLK" "TX_clk" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_sync_tx_0:PLL_LOCK" "TX_clk_stable" }
+
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign Reset_Block
+generate_component -component_name ${sd_name}
+
+puts "^^^^^^^^^^^^^^^^^ Create Transceivers Reset Block Complete ^^^^^^^^^^^^^^^^^^^"
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_sync_rx.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_sync_rx.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b2fad00b4abf0284cf96a6d818a9063461164458
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_sync_rx.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of Reset_sync_rx to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component Reset_sync_rx
+create_and_configure_core -core_vlnv Actel:DirectCore:CORERESET_PF:2.3.100 -component_name {Reset_sync_rx} -params { }
+# Exporting Component Description of Reset_sync_rx to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_sync_tx.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_sync_tx.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..18005a52b4bca08c839151364cbee8fd0e5992c0
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/Reset_sync_tx.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of Reset_sync_tx to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component Reset_sync_tx
+create_and_configure_core -core_vlnv Actel:DirectCore:CORERESET_PF:2.3.100 -component_name {Reset_sync_tx} -params { }
+# Exporting Component Description of Reset_sync_tx to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..31bb785f784c55164af87ad1e9e07f4bae8a1e01
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
@@ -0,0 +1,151 @@
+# Creating SmartDesign XCVR_LOOPBACK
+set sd_name {XCVR_LOOPBACK}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_BIT_CLK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_PLL_LOCK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_PLL_REF_CLK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RCOSC_160MHZ_GL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_REF_CLK_LOCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_REF_CLK} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_0_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_1_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_2_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_3_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {error_o} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {lock_o} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_val_o} -port_direction {OUT}
+
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0} -port_bif_vlnv {Actel:busdef.clock:PF_TXPLL_XCVR_CLK:1.0} -port_bif_role {slave} -port_bif_mapping {\
+"LOCK:CLKS_FROM_TXPLL_0_TX_PLL_LOCK_0" \
+"BIT_CLK:CLKS_FROM_TXPLL_0_TX_BIT_CLK_0" \
+"REF_CLK_TO_LANE:CLKS_FROM_TXPLL_0_TX_PLL_REF_CLK_0" }
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add pattern_chk_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {PATTERN_CHK} -instance_name {pattern_chk_0}
+# Exporting Parameters of instance pattern_chk_0
+sd_configure_core_instance -sd_name ${sd_name} -instance_name {pattern_chk_0} -params {\
+"g_DATA_WID:32" \
+"STATE_0:0" \
+"STATE_1:1" \
+"STATE_2:2" \
+"STATE_3:3" \
+"STATE_4:4" \
+"STATE_5:5" }\
+-validate_rules 0
+sd_save_core_instance_config -sd_name ${sd_name} -instance_name {pattern_chk_0}
+sd_update_instance -sd_name ${sd_name} -instance_name {pattern_chk_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[2:2]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:RESET_EN} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:generate_err} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:LANE_ARST_N}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:start_i} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:clear_i} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:error_count_o}
+
+
+
+# Add pattern_gen_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {PATTERN_GEN} -instance_name {pattern_gen_0}
+# Exporting Parameters of instance pattern_gen_0
+sd_configure_core_instance -sd_name ${sd_name} -instance_name {pattern_gen_0} -params {\
+"g_DATA_WID:32" \
+"STATE_0:0" \
+"STATE_1:1" \
+"STATE_2:2" \
+"STATE_3:3" \
+"STATE_4:4" \
+"STATE_5:5" }\
+-validate_rules 0
+sd_save_core_instance_config -sd_name ${sd_name} -instance_name {pattern_gen_0}
+sd_update_instance -sd_name ${sd_name} -instance_name {pattern_gen_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_gen_0:generate_err_i} -value {GND}
+
+
+
+# Add PF_XCVR_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_0} -instance_name {PF_XCVR_0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_IDLE}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_LOS} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_TX_DISPFNC} -value {GND}
+
+
+
+# Add Reset_Block_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_Block} -instance_name {Reset_Block_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_Block_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_Block_0:BANK_y_VDDI_STATUS} -value {VCC}
+
+
+
+# Add startup_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {STARTUP} -instance_name {startup_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_XCVR_0_0:LANE0_TX_CLK_STABLE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "Reset_Block_0:TX_clk_stable" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "Reset_Block_0:INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "Reset_Block_0:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_0_0:LANE0_RXD_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_0_0:LANE0_RXD_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_0_0:LANE0_TXD_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_0_0:LANE0_TXD_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:CTRL_ARST_N" "PF_XCVR_0_0:LANE0_PCS_ARST_N" "PF_XCVR_0_0:LANE0_PMA_ARST_N" "XCVR_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:CTRL_CLK" "RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_CDR_REF_CLK_FAB" "XCVR_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_CLK_R" "Reset_Block_0:RX_clk" "pattern_chk_0:clk_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_READY" "Reset_Block_0:RX_ready" "pattern_chk_0:RX_READY" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_VAL" "pattern_chk_0:rx_val_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_CLK_R" "Reset_Block_0:TX_clk" "pattern_gen_0:clk_i" "startup_0:tx_clk_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_Block_0:Pattern_chk_rst_n" "TEST_MODE_3_LED" "pattern_chk_0:ARST_N" "pattern_chk_0:reset_n_i" "startup_0:pattern_chk_n_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_Block_0:Pattern_gen_rst_n" "startup_0:pattern_gen_n_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_0_LED" "pattern_chk_0:s_count[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_1_LED" "pattern_chk_0:s_count[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_2_LED" "pattern_chk_0:s_count[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"error_o" "pattern_chk_0:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"lock_o" "pattern_chk_0:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_chk_0:rx_val_o" "rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_0:reset_n_i" "startup_0:start_gen_o" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_8B10B_RX_K" "pattern_chk_0:Rx_K_Char_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_8B10B_TX_K" "pattern_gen_0:Tx_K_Char_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_CODE_VIOLATION" "pattern_chk_0:LCV_ERR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DATA" "pattern_chk_0:data_in_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DISPARITY_ERROR" "pattern_chk_0:DISP_ERR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_DATA" "pattern_gen_0:data_out_o" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKS_FROM_TXPLL_0" "PF_XCVR_0_0:CLKS_FROM_TXPLL_0" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign XCVR_LOOPBACK
+generate_component -component_name ${sd_name}
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/constraints/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/constraints/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000000000000000000000000000000000000..d574933b2fbc2aac368ceec9263e76476909954a
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/constraints/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1,148 @@
+#set_io -port_name XCVR_TX1_N \
+# -pin_name H21 \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name XCVR_TX1_P \
+# -pin_name H22 \
+# -DIRECTION OUTPUT
+#
+set_io -port_name XCVR_TX2_N \
+ -pin_name P21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX2_P \
+ -pin_name P22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX3_N \
+ -pin_name T21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX3_P \
+ -pin_name T22 \
+ -DIRECTION OUTPUT
+
+
+#set_io -port_name XCVR_RX1_N \
+# -pin_name K21 \
+# -DIRECTION INPUT
+#
+#set_io -port_name XCVR_RX1_P \
+# -pin_name K22 \
+# -DIRECTION INPUT
+
+set_io -port_name XCVR_RX2_N \
+ -pin_name M21 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX2_P \
+ -pin_name M22 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX3_N \
+ -pin_name R19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX3_P \
+ -pin_name R20 \
+ -DIRECTION INPUT
+
+
+#set_io -port_name XCVR_0A_REFCLK_P \
+# -pin_name L19 \
+# -DIRECTION INPUT
+#
+#set_io -port_name XCVR_0A_REFCLK_N \
+# -pin_name L20 \
+# -DIRECTION INPUT
+
+
+set_io -port_name XCVR_0B_REFCLK_P \
+ -pin_name N19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_0B_REFCLK_N \
+ -pin_name N20 \
+ -DIRECTION INPUT
+
+
+set_io -port_name XCVR_0C_REFCLK_P \
+ -pin_name J19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_0C_REFCLK_N \
+ -pin_name J20 \
+ -DIRECTION INPUT
+
+
+
+set_io -port_name B0_HSIO70N \
+ -pin_name AB20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO70P \
+ -pin_name AB19 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO71N \
+ -pin_name AA20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO71P \
+ -pin_name AB21 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO73N_C2P_CLKN \
+ -pin_name U17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO73P_C2P_CLKP \
+ -pin_name T17 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO81N \
+ -pin_name AA17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO81P \
+ -pin_name AB17 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO82N \
+ -pin_name Y16 \
+ -fixed true \
+ -DIRECTION INOUT
+
+
+set_io -port_name B0_HSIO82P \
+ -pin_name AA16 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO83N \
+ -pin_name W17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO83P \
+ -pin_name W16 \
+ -fixed true \
+ -DIRECTION INPUT