From 18247787ba26a91c20cd79ebd1e3344ad373e64e Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Mon, 21 Feb 2022 16:11:52 +0000
Subject: [PATCH] Ethernet: Connect to PHY
- Connect Ethernet management interface to PHY.
- Connect PHY reset input to FPGA system reset.
- Connect PHY interrupt to MSS F2M fabric interrupt 2.
---
script_support/PF_SoC_MSS_Icicle.cfg | 4 +-
.../components/B_V_F_BASE_DESIGN.tcl | 28 +++++-----
script_support/constraints/base_design.pdc | 51 +++++--------------
3 files changed, 31 insertions(+), 52 deletions(-)
diff --git a/script_support/PF_SoC_MSS_Icicle.cfg b/script_support/PF_SoC_MSS_Icicle.cfg
index 0d91f41..e1e3bd8 100644
--- a/script_support/PF_SoC_MSS_Icicle.cfg
+++ b/script_support/PF_SoC_MSS_Icicle.cfg
@@ -1089,9 +1089,9 @@ LPDDR4_ZQ_CAL_TIME 1
LP_STATE UNUSED
M2F_MONITOR UNUSED
MAC_0 SGMII_IO_B5
-MAC_0_MANAGEMENT UNUSED
+MAC_0_MANAGEMENT MSSIO_B2_B
MAC_0_OTHER UNUSED
-MAC_0_TSU INCREMENT_MODE
+MAC_0_TSU UNUSED
MAC_1 UNUSED
MAC_1_MANAGEMENT UNUSED
MAC_1_OTHER UNUSED
diff --git a/script_support/components/B_V_F_BASE_DESIGN.tcl b/script_support/components/B_V_F_BASE_DESIGN.tcl
index 3800c53..2fd831d 100644
--- a/script_support/components/B_V_F_BASE_DESIGN.tcl
+++ b/script_support/components/B_V_F_BASE_DESIGN.tcl
@@ -235,16 +235,6 @@ sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {B_V_F_MSS:MSS_INT_F2
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {B_V_F_MSS:SPI_0_SS_F2M} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {B_V_F_MSS:SPI_0_CLK_F2M} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MSS_INT_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_SOF_TX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_SYNC_FRAME_TX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_DELAY_REQ_TX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_PDELAY_REQ_TX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_PDELAY_RESP_TX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_SOF_RX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_SYNC_FRAME_RX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_DELAY_REQ_RX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_PDELAY_REQ_RX_M2F}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:MAC_0_TSU_PDELAY_RESP_RX_M2F}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {B_V_F_MSS:FIC_2_AXI4_TARGET}
@@ -379,10 +369,25 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "CLOCKS_AND_RESE
sd_connect_pins -sd_name ${sd_name} -pin_names {"REFCLK" "B_V_F_MSS:REFCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REFCLK_N" "B_V_F_MSS:REFCLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RESET_N" "B_V_F_MSS:RESET_N" }
+
+#-------------------------------------------------------------------------------
+# Ethernet PHY connections
+#-------------------------------------------------------------------------------
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_RSTn} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_INTn} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDC} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDIO} -port_direction {INOUT}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PHY_MDIO" "B_V_F_MSS:MAC_0_MDIO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PHY_MDC" "B_V_F_MSS:MAC_0_MDC" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PHY_INTn" "B_V_F_MSS:MSS_INT_F2M[2:2]" }
+
sd_connect_pins -sd_name ${sd_name} -pin_names {"SGMII_RX0_N" "B_V_F_MSS:SGMII_RX0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SGMII_RX0_P" "B_V_F_MSS:SGMII_RX0_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SGMII_TX0_N" "B_V_F_MSS:SGMII_TX0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SGMII_TX0_P" "B_V_F_MSS:SGMII_TX0_P" }
+
+#-------------------------------------------------------------------------------
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:SPI_0_CLK_M2F" "SPI_0_CLK_M2F" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:SPI_0_DI_F2M" "SPI_0_DI_F2M" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:SPI_0_DO_M2F" "SPI_0_DO_M2F" }
@@ -399,7 +404,7 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:USB_DATA7" "USB_DATA7
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:USB_DIR" "USB_DIR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:USB_NXT" "USB_NXT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_V_F_MSS:USB_STP" "USB_STP" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"USB_ULPI_RESET" "FIC0_INITIATOR:ARESETN" "CLOCKS_AND_RESETS:RESETN_CLK_125MHz"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"USB_ULPI_RESET" "FIC0_INITIATOR:ARESETN" "CLOCKS_AND_RESETS:RESETN_CLK_125MHz" "PHY_RSTn"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"SD_CLK_EMMC_CLK" "B_V_F_MSS:SD_CLK_EMMC_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SD_CMD_EMMC_CMD" "B_V_F_MSS:SD_CMD_EMMC_CMD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SD_DATA0_EMMC_DATA0" "B_V_F_MSS:SD_DATA0_EMMC_DATA0" }
@@ -659,7 +664,6 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D3_N" "MIPI_CSI_INTERFACE_0
#-------------------------------------------------------------------------------
# Temporary connections to allow running through complete flow.
#-------------------------------------------------------------------------------
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {B_V_F_MSS:MSS_INT_F2M[2:2]} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {B_V_F_MSS:MSS_INT_F2M[4:4]} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {B_V_F_MSS:MSS_INT_F2M[3:3]} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {B_V_F_MSS:MSS_RESET_N_F2M} -value {VCC}
diff --git a/script_support/constraints/base_design.pdc b/script_support/constraints/base_design.pdc
index 1da36e7..e08a0f5 100644
--- a/script_support/constraints/base_design.pdc
+++ b/script_support/constraints/base_design.pdc
@@ -2,43 +2,18 @@ set_iobank -bank_name Bank1 \
-vcci 3.30 \
-fixed true \
-update_iostd true
-
-#set_io -port_name SW1 \
-# -pin_name V19 \
-# -fixed true \
-# -DIRECTION INPUT
-
-#set_io -port_name SW2 \
-# -pin_name U18 \
-# -fixed true \
-# -DIRECTION INPUT
-#set_io -port_name SW3 \
-# -pin_name W19 \
-# -fixed true \
-# -DIRECTION INPUT
-
-#set_io -port_name SW4 \
-# -pin_name W18 \
-# -fixed true \
-# -DIRECTION INPUT
-#set_io -port_name LED0 \
-# -pin_name V14 \
-# -fixed true \
-# -DIRECTION OUTPUT
-
-#set_io -port_name LED1 \
-# -pin_name U13 \
-# -fixed true \
-# -DIRECTION OUTPUT
-
-#set_io -port_name LED2 \
-# -pin_name T12 \
-# -fixed true \
-# -DIRECTION OUTPUT
-
-#set_io -port_name LED3 \
-# -pin_name AB19 \
-# -fixed true \
-# -DIRECTION OUTPUT
+set_io -port_name PHY_RSTn \
+ -pin_name B4 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name PHY_INTn \
+ -pin_name C4 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
--
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