diff --git a/B_V_F_REFERENCE_DESIGN.tcl b/B_V_F_REFERENCE_DESIGN.tcl
index 4d960692fc68086527549902cf11b0105a2d4902..2598e187ecf48413c02cf035181809b2cd0d6b87 100644
--- a/B_V_F_REFERENCE_DESIGN.tcl
+++ b/B_V_F_REFERENCE_DESIGN.tcl
@@ -128,6 +128,7 @@ download_core -vlnv {Actel:Simulation:RESET_GEN:1.0.1} -location {www.microchip-
 download_core -vlnv {Actel:DirectCore:corepwm:4.5.100} -location {www.microchip-ip.com/repositories/DirectCore} 
 download_core -vlnv {Actel:DirectCore:COREI2C:7.2.101} -location {www.microchip-ip.com/repositories/DirectCore} 
 download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.106} -location {www.microchip-ip.com/repositories/SgCore}
 
 #
 # // Generate base design
@@ -143,6 +144,7 @@ import_files \
     -convert_EDN_to_HDL 0 \
     -io_pdc "${constraint_path}/base_design.pdc" \
     -io_pdc "${constraint_path}/cape.pdc" \
+    -io_pdc "${constraint_path}/MIPI_CSI_INTERFACE.pdc" \
     -io_pdc "${constraint_path}/ICICLE_PCIE.pdc" \
     -io_pdc "${constraint_path}/ICICLE_USB.pdc"
 
@@ -154,6 +156,7 @@ organize_tool_files \
     -tool {PLACEROUTE} \
     -file "${project_dir}/constraint/io/base_design.pdc" \
     -file "${project_dir}/constraint/io/cape.pdc" \
+    -file "${project_dir}/constraint/io/MIPI_CSI_INTERFACE.pdc" \
     -file "${project_dir}/constraint/io/ICICLE_PCIE.pdc" \
     -file "${project_dir}/constraint/io/ICICLE_USB.pdc" \
     -module {B_V_F_BASE_DESIGN::work} \
diff --git a/script_support/B_V_F_recursive.tcl b/script_support/B_V_F_recursive.tcl
index 1c05293ca0f4fbe69e8cb16074fcd6684cdff9b0..0b24ef8a7f0d735c515fbb4856e80366dcf9e350 100644
--- a/script_support/B_V_F_recursive.tcl
+++ b/script_support/B_V_F_recursive.tcl
@@ -5,6 +5,8 @@ file mkdir $local_dir/script_support/components/MSS
 exec $mss_config_loc -CONFIGURATION_FILE:$local_dir/script_support/PF_SoC_MSS_Icicle.cfg -OUTPUT_DIR:$local_dir/script_support/components/MSS
 import_mss_component -file "$local_dir/script_support/components/MSS/B_V_F_MSS.cxz"
 source script_support/hdl_source.tcl
+source script_support/components/MIPI_CSI2_RX_IOD.tcl 
+source script_support/components/MIPI_CSI_INTERFACE.tcl 
 source script_support/components/CORERESET_0.tcl
 source script_support/components/INIT_MONITOR.tcl 
 source script_support/components/PCIE_INITIATOR.tcl 
diff --git a/script_support/components/B_V_F_BASE_DESIGN.tcl b/script_support/components/B_V_F_BASE_DESIGN.tcl
index c4e144e0b48fafd4d3b5a4e2402075d62293e00e..d74e99e963e1f4ce3ffd6817cde4a499813481cc 100644
--- a/script_support/components/B_V_F_BASE_DESIGN.tcl
+++ b/script_support/components/B_V_F_BASE_DESIGN.tcl
@@ -197,7 +197,7 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {FIC3_INITIATOR} -i
 
 
 # Add APB_ARBITER instance
-sd_instantiate_hdl_core -sd_name {B_V_F_BASE_DESIGN} -hdl_core_name {APB_ARBITER} -instance_name {} 
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {APB_ARBITER} -instance_name {} 
 
 
 
@@ -214,7 +214,7 @@ sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {I2C0_SDA_BIBUF:D} -v
 
 
 # Add IHC_SUBSYSTEM instance
-sd_instantiate_component -sd_name {B_V_F_BASE_DESIGN} -component_name {IHC_SUBSYSTEM} -instance_name {IHC_SUBSYSTEM_0} 
+sd_instantiate_component -sd_name ${sd_name} -component_name {IHC_SUBSYSTEM} -instance_name {IHC_SUBSYSTEM_0} 
 
 
 # Add MSS instance
@@ -304,7 +304,7 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {RECONFIGURATION_IN
 
 
 # Add AXI_ADDRESS_SHIM instance
-sd_instantiate_hdl_core -sd_name {B_V_F_BASE_DESIGN} -hdl_core_name {AXI_ADDRESS_SHIM} -instance_name {AXI_ADDRESS_SHIM_0} 
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI_ADDRESS_SHIM} -instance_name {AXI_ADDRESS_SHIM_0} 
 
 
 
@@ -636,6 +636,44 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_42" "P9_42"}
 
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "FIC3_INITIATOR:APBmslave1"}
 
+#-------------------------------------------------------------------------------
+# MIPI CSI-2 RX interface
+#-------------------------------------------------------------------------------
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_N} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_P} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_D0_N} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_D0_P} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_D1_N} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_D1_P} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_D2_N} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_D2_P} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_D3_N} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_D3_P} -port_direction {IN} 
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {MIPI_CSI_INTERFACE} -instance_name {MIPI_CSI_INTERFACE_0} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:CSI1_PWND} -port_name {} 
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:RXD_N} -pin_slices {"[3:3]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:RXD_N} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:RXD_N} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:RXD_N} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:RXD} -pin_slices {"[3:3]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:RXD} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:RXD} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI_INTERFACE_0:RXD} -pin_slices {"[0:0]"} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_N" "MIPI_CSI_INTERFACE_0:RX_CLK_N"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_P" "MIPI_CSI_INTERFACE_0:RX_CLK_P"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D0_P" "MIPI_CSI_INTERFACE_0:RXD[0:0]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D0_N" "MIPI_CSI_INTERFACE_0:RXD_N[0:0]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D1_P" "MIPI_CSI_INTERFACE_0:RXD[1:1]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D1_N" "MIPI_CSI_INTERFACE_0:RXD_N[1:1]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D2_N" "MIPI_CSI_INTERFACE_0:RXD_N[2:2]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D2_P" "MIPI_CSI_INTERFACE_0:RXD[2:2]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D3_P" "MIPI_CSI_INTERFACE_0:RXD[3:3]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D3_N" "MIPI_CSI_INTERFACE_0:RXD_N[3:3]"} 
+
+
 #-------------------------------------------------------------------------------
 # Temporary connections to allow running through complete flow.
 #-------------------------------------------------------------------------------
diff --git a/script_support/components/MIPI_CSI2_RX_IOD.tcl b/script_support/components/MIPI_CSI2_RX_IOD.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f73b9ed9cafbb3ab0bd4269c8025894f789b49ea
--- /dev/null
+++ b/script_support/components/MIPI_CSI2_RX_IOD.tcl
@@ -0,0 +1,44 @@
+# Exporting Component Description of MIPI_CSI2_RX_IOD to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T-FCVG484E
+# Create and Configure the core component MIPI_CSI2_RX_IOD
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.106} -component_name {MIPI_CSI2_RX_IOD} -params {\
+"CLOCK_DELAY_VALUE:0" \
+"DATA_RATE:250" \
+"DATA_RATIO:2" \
+"DATA_WIDTH:1" \
+"DDR_MODE:DDR" \
+"DELAY_LINE_SIMULATION_MODE_EN:false" \
+"DYN_USE_WIDE_MODE:false" \
+"EXPOSE_CLK_TRAIN_PORTS:false" \
+"EXPOSE_DYNAMIC_DELAY_CTRL:false" \
+"EXPOSE_EXTRA_TRAINING_PORTS:false" \
+"EXPOSE_FA_CLK_DATA:false" \
+"EXPOSE_RX_RAW_DATA:false" \
+"FABRIC_CLK_SOURCE:GLOBAL" \
+"FRACTIONAL_CLOCK_RATIO:RATIO" \
+"ICB_BCLK_OFFSET:0" \
+"ICB_USE_WIDE_MODE:true" \
+"IO_NUMBER:4" \
+"NEED_LANECTRL:false" \
+"NEED_TIP:false" \
+"PLL_BCLK_OFFSET:3" \
+"RATIO:1" \
+"RXCTL_SPLIT_WIDTH:1" \
+"RXD_LVDS_FAILSAFE_EN:false" \
+"RXD_SPLIT_WIDTH:4" \
+"RX_BIT_SLIP_EN:false" \
+"RX_CLK_DIFFERENTIAL:true" \
+"RX_CLK_LVDS_FAILSAFE_EN:false" \
+"RX_CLK_SOURCE:FABRIC" \
+"RX_CLK_TO_DATA:ALIGNED" \
+"RX_DATA_BUS_MODE:RX_DATA_PER_IO" \
+"RX_DATA_DIFFERENTIAL:true" \
+"RX_ENABLED:true" \
+"RX_INTERFACE_NAME:RX_DDR_G_A" \
+"RX_IOG_ARCHETYPE:RX_DDR_GR" \
+"RX_MIPI_MODE:false" \
+"SIMULATION_MODE:FULL" \
+"USE_SHARED_PLL:false" \
+"X1_ADD_DELAY_LINE_ON_CLOCK:false" }
+# Exporting Component Description of MIPI_CSI2_RX_IOD to TCL done
diff --git a/script_support/components/MIPI_CSI_INTERFACE.tcl b/script_support/components/MIPI_CSI_INTERFACE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..919b8661c4ff0ab48fc7f4da3d135bd8be11091e
--- /dev/null
+++ b/script_support/components/MIPI_CSI_INTERFACE.tcl
@@ -0,0 +1,99 @@
+#-------------------------------------------------------------------------------
+# MIPI CSI interface
+# This is currently a glitch generator for the purpose of IO placement.
+#-------------------------------------------------------------------------------
+
+
+
+# Creating SmartDesign MIPI_CSI_INTERFACE
+set sd_name {MIPI_CSI_INTERFACE}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_P} -port_direction {IN} -port_is_pad {1}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI1_PWND} -port_direction {OUT}
+
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+sd_create_bus_port -sd_name ${sd_name} -port_name {RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add AND2_1 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}
+
+
+
+# Add AND2_2 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_2}
+
+
+
+# Add AND2_3 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_3}
+
+
+
+# Add AND2_4 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_4}
+
+
+
+# Add AND4_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND4} -instance_name {AND4_0}
+
+
+
+# Add MIPI_CSI2_RX_IOD_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {MIPI_CSI2_RX_IOD} -instance_name {MIPI_CSI2_RX_IOD_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI2_RX_IOD_0:L0_RXD_DATA} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI2_RX_IOD_0:L0_RXD_DATA} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI2_RX_IOD_0:L1_RXD_DATA} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI2_RX_IOD_0:L1_RXD_DATA} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI2_RX_IOD_0:L2_RXD_DATA} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI2_RX_IOD_0:L2_RXD_DATA} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI2_RX_IOD_0:L3_RXD_DATA} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIPI_CSI2_RX_IOD_0:L3_RXD_DATA} -pin_slices {[1:1]}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "AND4_0:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "MIPI_CSI2_RX_IOD_0:RX_CLK_G" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CSI1_PWND" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "MIPI_CSI2_RX_IOD_0:L0_RXD_DATA[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "MIPI_CSI2_RX_IOD_0:L0_RXD_DATA[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "AND4_0:A" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:A" "MIPI_CSI2_RX_IOD_0:L1_RXD_DATA[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:B" "MIPI_CSI2_RX_IOD_0:L1_RXD_DATA[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:Y" "AND4_0:B" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_3:A" "MIPI_CSI2_RX_IOD_0:L2_RXD_DATA[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_3:B" "MIPI_CSI2_RX_IOD_0:L2_RXD_DATA[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_3:Y" "AND4_0:C" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_4:A" "MIPI_CSI2_RX_IOD_0:L3_RXD_DATA[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_4:B" "MIPI_CSI2_RX_IOD_0:L3_RXD_DATA[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_4:Y" "AND4_0:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MIPI_CSI2_RX_IOD_0:RX_CLK_N" "RX_CLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MIPI_CSI2_RX_IOD_0:RX_CLK_P" "RX_CLK_P" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MIPI_CSI2_RX_IOD_0:RXD" "RXD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MIPI_CSI2_RX_IOD_0:RXD_N" "RXD_N" }
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign MIPI_CSI_INTERFACE
+generate_component -component_name ${sd_name}
diff --git a/script_support/constraints/MIPI_CSI_INTERFACE.pdc b/script_support/constraints/MIPI_CSI_INTERFACE.pdc
new file mode 100644
index 0000000000000000000000000000000000000000..19929e158ee8c768dbaa6df4dd91b62f93c9f1d9
--- /dev/null
+++ b/script_support/constraints/MIPI_CSI_INTERFACE.pdc
@@ -0,0 +1,68 @@
+# TODO: figure out optimum pin assignment for these signals.
+
+set_io -port_name CAM_C_N  \
+    -pin_name AB13         \
+    -fixed true            \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_C_P  \
+    -pin_name AA13         \
+    -fixed true            \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_D0_N  \
+    -pin_name AB12          \
+    -fixed true             \
+    -io_std SUBLVDS18       \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_D0_P  \
+    -pin_name AA12          \
+    -fixed true             \
+    -io_std SUBLVDS18       \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_D1_N  \
+    -pin_name Y16           \
+    -fixed true             \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_D1_P  \
+    -pin_name AA16          \
+    -fixed true             \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_D2_N  \
+    -pin_name AA22          \
+    -fixed true             \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_D2_P  \
+    -pin_name AA21          \
+    -fixed true             \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_D3_N  \
+    -pin_name AB15          \
+    -fixed true             \
+    -DIRECTION INPUT
+
+
+set_io -port_name CAM_D3_P  \
+    -pin_name AB14          \
+    -fixed true             \
+    -DIRECTION INPUT
+
+
+set_io -port_name CSI1_PWND \
+    -pin_name AA20          \
+    -fixed true             \
+    -DIRECTION INPUT