diff --git a/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl b/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
index 7d826f4eb9de6c5b0996ccba422c18275a2dc422..088b93a8a6bf64d8e9762e29f6385bea58dbe7f3 100644
--- a/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
+++ b/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
@@ -4,12 +4,14 @@ puts "======== Add cape option: DEFAULT ========"
# Build cape's submodules
#-------------------------------------------------------------------------------
source script_support/components/CAPE/DEFAULT/APB_BUS_CONVERTER.tcl
-source script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl
+source script_support/components/CAPE/DEFAULT/CoreAPB3_CAPE.tcl
+#source script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl
source script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl
source script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
source script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl
source script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
source script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
+source script_support/components/CAPE/DEFAULT/corepwm_C1.tcl
source script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
source script_support/components/CAPE/DEFAULT/CAPE.tcl
diff --git a/script_support/components/CAPE/DEFAULT/CAPE.tcl b/script_support/components/CAPE/DEFAULT/CAPE.tcl
index 71f6f4815934559de9598e0a3493b1614ec27717..f655bd5943bcd681317bb286108bfa0b169f1b99 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE.tcl
@@ -118,6 +118,17 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance
# Add PWM_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PWM_0:PWM_1}
+
+
+
+# Add PWM_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_1}
+
+
+
+# Add PWM_2 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_2}
@@ -164,10 +175,10 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_6_PAD" "P8
sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_7_PAD" "P8_PIN38" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_8_PAD" "P8_PIN39" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_9_PAD" "P8_PIN40" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PCLK" "P9_GPIO_0:PCLK" "PCLK" "PWM_0:PCLK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PRESETN" "P9_GPIO_0:PRESETN" "PRESETN" "PWM_0:PRESETN" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_PIN13_USER_LED_10" "PWM_0:PWM_3" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_PIN19" "PWM_0:PWM_4" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PCLK" "P9_GPIO_0:PCLK" "PCLK" "PWM_0:PCLK" "PWM_1:PCLK" "PWM_2:PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PRESETN" "P9_GPIO_0:PRESETN" "PRESETN" "PWM_0:PRESETN" "PWM_1:PRESETN" "PWM_2:PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_PIN13_USER_LED_10" "PWM_2:PWM_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_PIN19" "PWM_2:PWM_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_10_PAD" "P9_PIN23" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_12_PAD" "P9_PIN25" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_14_PAD" "P9_PIN27" }
@@ -175,8 +186,8 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_17_PAD" "P9_PIN3
sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_19_PAD" "P9_PIN41" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_1_PAD" "P9_PIN12" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_4_PAD" "P9_PIN15" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN14" "PWM_0:PWM_1" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN16" "PWM_0:PWM_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN14" "PWM_1:PWM_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN16" "PWM_1:PWM_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN42" "PWM_0:PWM_0" }
# Add bus net connections
@@ -190,6 +201,8 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_SLAVE"
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave1" "P8_GPIO_UPPER_0:APB_bif" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave2" "P9_GPIO_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave4" "PWM_1:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave5" "PWM_2:APBslave" }
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
diff --git a/script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl b/script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
index 69ddf92e5456b5fca2b1a08cf948c8de61df78e8..e59a793e700e3bf6b651a30c8b44e610d721aa0a 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
@@ -2,71 +2,57 @@
set sd_name {CAPE_PWM}
create_smartdesign -sd_name ${sd_name}
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
-create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -component_name {corepwm_C1} -params {\
-"APB_DWIDTH:32" "CONFIG_MODE:0" \
-"DAC_MODE1:false" "DAC_MODE2:false" "DAC_MODE3:false" "DAC_MODE4:false" "DAC_MODE5:false" \
-"DAC_MODE6:false" "DAC_MODE7:false" "DAC_MODE8:false" "DAC_MODE9:false" "DAC_MODE10:false" \
-"DAC_MODE11:false" "DAC_MODE12:false" "DAC_MODE13:false" "DAC_MODE14:false" "DAC_MODE15:false" \
-"DAC_MODE16:false" \
-"FIXED_PERIOD:1" "FIXED_PERIOD_EN:false" "FIXED_PRESCALE:0" "FIXED_PRESCALE_EN:false" \
-"FIXED_PWM_NEGEDGE1:0" "FIXED_PWM_NEGEDGE2:0" "FIXED_PWM_NEGEDGE3:0" "FIXED_PWM_NEGEDGE4:0" "FIXED_PWM_NEGEDGE5:0" \
-"FIXED_PWM_NEGEDGE6:0" "FIXED_PWM_NEGEDGE7:0" "FIXED_PWM_NEGEDGE8:0" "FIXED_PWM_NEGEDGE9:0" "FIXED_PWM_NEGEDGE10:0" \
-"FIXED_PWM_NEGEDGE11:0" "FIXED_PWM_NEGEDGE12:0" "FIXED_PWM_NEGEDGE13:0" "FIXED_PWM_NEGEDGE14:0" "FIXED_PWM_NEGEDGE15:0" \
-"FIXED_PWM_NEGEDGE16:0" \
-"FIXED_PWM_NEG_EN1:false" "FIXED_PWM_NEG_EN2:false" "FIXED_PWM_NEG_EN3:false" "FIXED_PWM_NEG_EN4:false" "FIXED_PWM_NEG_EN5:false" \
-"FIXED_PWM_NEG_EN6:false" "FIXED_PWM_NEG_EN7:false" "FIXED_PWM_NEG_EN8:false" "FIXED_PWM_NEG_EN9:false" "FIXED_PWM_NEG_EN10:false" \
-"FIXED_PWM_NEG_EN11:false" "FIXED_PWM_NEG_EN12:false" "FIXED_PWM_NEG_EN13:false" "FIXED_PWM_NEG_EN14:false" "FIXED_PWM_NEG_EN15:false" \
-"FIXED_PWM_NEG_EN16:false" \
-"FIXED_PWM_POSEDGE1:0" "FIXED_PWM_POSEDGE2:0" "FIXED_PWM_POSEDGE3:0" "FIXED_PWM_POSEDGE4:0" "FIXED_PWM_POSEDGE5:0" \
-"FIXED_PWM_POSEDGE6:0" "FIXED_PWM_POSEDGE7:0" "FIXED_PWM_POSEDGE8:0" "FIXED_PWM_POSEDGE9:0" "FIXED_PWM_POSEDGE10:0" \
-"FIXED_PWM_POSEDGE11:0" "FIXED_PWM_POSEDGE12:0" "FIXED_PWM_POSEDGE13:0" "FIXED_PWM_POSEDGE14:0" "FIXED_PWM_POSEDGE15:0" \
-"FIXED_PWM_POSEDGE16:0" \
-"FIXED_PWM_POS_EN1:false" "FIXED_PWM_POS_EN2:false" "FIXED_PWM_POS_EN3:false" "FIXED_PWM_POS_EN4:false" "FIXED_PWM_POS_EN5:false" \
-"FIXED_PWM_POS_EN6:true" "FIXED_PWM_POS_EN7:true" "FIXED_PWM_POS_EN8:true" "FIXED_PWM_POS_EN9:true" "FIXED_PWM_POS_EN10:true" \
-"FIXED_PWM_POS_EN11:true" "FIXED_PWM_POS_EN12:true" "FIXED_PWM_POS_EN13:true" "FIXED_PWM_POS_EN14:true" "FIXED_PWM_POS_EN15:true" \
-"FIXED_PWM_POS_EN16:true" \
-"PWM_NUM:5" \
-"PWM_STRETCH_VALUE1:false" "PWM_STRETCH_VALUE2:false" "PWM_STRETCH_VALUE3:false" "PWM_STRETCH_VALUE4:false" "PWM_STRETCH_VALUE5:false" \
-"PWM_STRETCH_VALUE6:false" "PWM_STRETCH_VALUE7:false" "PWM_STRETCH_VALUE8:false" "PWM_STRETCH_VALUE9:false" "PWM_STRETCH_VALUE10:false" \
-"PWM_STRETCH_VALUE11:false" "PWM_STRETCH_VALUE12:false" "PWM_STRETCH_VALUE13:false" "PWM_STRETCH_VALUE14:false" "PWM_STRETCH_VALUE15:false" \
-"PWM_STRETCH_VALUE16:false" \
-"SEPARATE_PWM_CLK:false" \
-"SHADOW_REG_EN1:false" "SHADOW_REG_EN2:false" "SHADOW_REG_EN3:false" "SHADOW_REG_EN4:false" "SHADOW_REG_EN5:false" \
-"SHADOW_REG_EN6:false" "SHADOW_REG_EN7:false" "SHADOW_REG_EN8:false" "SHADOW_REG_EN9:false" \
-"SHADOW_REG_EN10:false" "SHADOW_REG_EN11:false" "SHADOW_REG_EN12:false" "SHADOW_REG_EN13:false" \
-"SHADOW_REG_EN14:false" "SHADOW_REG_EN15:false" "SHADOW_REG_EN16:false" \
-"TACHINT_ACT_LEVEL:false" \
-"TACH_EDGE1:false" "TACH_EDGE2:false" "TACH_EDGE3:false" "TACH_EDGE4:false" "TACH_EDGE5:false" \
-"TACH_EDGE6:false" "TACH_EDGE7:false" "TACH_EDGE8:false" "TACH_EDGE9:false" "TACH_EDGE10:false" \
-"TACH_EDGE11:false" "TACH_EDGE12:false" "TACH_EDGE13:false" "TACH_EDGE14:false" "TACH_EDGE15:false" \
-"TACH_EDGE16:false" \
-"TACH_NUM:1"}
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
-sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PWM_0} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PWM_1} -port_direction {OUT}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[0:0]"}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:APBslave} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PCLK} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[0:0]} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[4:4]} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[3:3]} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[2:2]} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[1:1]} -port_name {}
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APBslave_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APBslave_PWDATA} -port_direction {IN} -port_range {[31:0]}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_3} -new_port_name {PWM_4}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_2} -new_port_name {PWM_3}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_1} -new_port_name {PWM_2}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_0} -new_port_name {PWM_1}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM} -new_port_name {PWM_0}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APBslave_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APBslave} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APBslave_PADDR" \
+"PSELx:APBslave_PSEL" \
+"PENABLE:APBslave_PENABLE" \
+"PWRITE:APBslave_PWRITE" \
+"PRDATA:APBslave_PRDATA" \
+"PWDATA:APBslave_PWDATA" \
+"PREADY:APBslave_PREADY" \
+"PSLVERR:APBslave_PSLVERR" }
+
+# Add corepwm_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {corepwm_C1_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {[1:1]}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "corepwm_C1_0:PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "corepwm_C1_0:PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PWM_0" "corepwm_C1_0:PWM[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PWM_1" "corepwm_C1_0:PWM[1:1]" }
+
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APBslave" "corepwm_C1_0:APBslave" }
+
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
diff --git a/script_support/components/CAPE/DEFAULT/CoreAPB3_CAPE.tcl b/script_support/components/CAPE/DEFAULT/CoreAPB3_CAPE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ab9b81e998527110100572f6008a0373b7ecbfe8
--- /dev/null
+++ b/script_support/components/CAPE/DEFAULT/CoreAPB3_CAPE.tcl
@@ -0,0 +1,42 @@
+# Exporting Component Description of CoreAPB3_CAPE to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreAPB3_CAPE
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
+"APB_DWIDTH:32" \
+"APBSLOT0ENABLE:true" \
+"APBSLOT1ENABLE:true" \
+"APBSLOT2ENABLE:true" \
+"APBSLOT3ENABLE:false" \
+"APBSLOT4ENABLE:true" \
+"APBSLOT5ENABLE:true" \
+"APBSLOT6ENABLE:false" \
+"APBSLOT7ENABLE:false" \
+"APBSLOT8ENABLE:false" \
+"APBSLOT9ENABLE:false" \
+"APBSLOT10ENABLE:false" \
+"APBSLOT11ENABLE:false" \
+"APBSLOT12ENABLE:false" \
+"APBSLOT13ENABLE:false" \
+"APBSLOT14ENABLE:false" \
+"APBSLOT15ENABLE:false" \
+"IADDR_OPTION:0" \
+"MADDR_BITS:24" \
+"SC_0:false" \
+"SC_1:false" \
+"SC_2:false" \
+"SC_3:false" \
+"SC_4:false" \
+"SC_5:false" \
+"SC_6:false" \
+"SC_7:false" \
+"SC_8:false" \
+"SC_9:false" \
+"SC_10:false" \
+"SC_11:false" \
+"SC_12:false" \
+"SC_13:false" \
+"SC_14:false" \
+"SC_15:false" \
+"UPR_NIBBLE_POSN:5" }
+# Exporting Component Description of CoreAPB3_CAPE to TCL done
diff --git a/script_support/components/CAPE/DEFAULT/corepwm_C1.tcl b/script_support/components/CAPE/DEFAULT/corepwm_C1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0eb4a5100d4aeb9dc728774e2b24026b50fe1c41
--- /dev/null
+++ b/script_support/components/CAPE/DEFAULT/corepwm_C1.tcl
@@ -0,0 +1,144 @@
+# Exporting Component Description of corepwm_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component corepwm_C1
+create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -component_name {corepwm_C1} -params {\
+"APB_DWIDTH:32" \
+"CONFIG_MODE:0" \
+"DAC_MODE1:false" \
+"DAC_MODE2:false" \
+"DAC_MODE3:false" \
+"DAC_MODE4:false" \
+"DAC_MODE5:false" \
+"DAC_MODE6:false" \
+"DAC_MODE7:false" \
+"DAC_MODE8:false" \
+"DAC_MODE9:false" \
+"DAC_MODE10:false" \
+"DAC_MODE11:false" \
+"DAC_MODE12:false" \
+"DAC_MODE13:false" \
+"DAC_MODE14:false" \
+"DAC_MODE15:false" \
+"DAC_MODE16:false" \
+"FIXED_PERIOD:1" \
+"FIXED_PERIOD_EN:false" \
+"FIXED_PRESCALE:0" \
+"FIXED_PRESCALE_EN:false" \
+"FIXED_PWM_NEG_EN1:false" \
+"FIXED_PWM_NEG_EN2:false" \
+"FIXED_PWM_NEG_EN3:false" \
+"FIXED_PWM_NEG_EN4:false" \
+"FIXED_PWM_NEG_EN5:false" \
+"FIXED_PWM_NEG_EN6:false" \
+"FIXED_PWM_NEG_EN7:false" \
+"FIXED_PWM_NEG_EN8:false" \
+"FIXED_PWM_NEG_EN9:false" \
+"FIXED_PWM_NEG_EN10:false" \
+"FIXED_PWM_NEG_EN11:false" \
+"FIXED_PWM_NEG_EN12:false" \
+"FIXED_PWM_NEG_EN13:false" \
+"FIXED_PWM_NEG_EN14:false" \
+"FIXED_PWM_NEG_EN15:false" \
+"FIXED_PWM_NEG_EN16:false" \
+"FIXED_PWM_NEGEDGE1:0" \
+"FIXED_PWM_NEGEDGE2:0" \
+"FIXED_PWM_NEGEDGE3:0" \
+"FIXED_PWM_NEGEDGE4:0" \
+"FIXED_PWM_NEGEDGE5:0" \
+"FIXED_PWM_NEGEDGE6:0" \
+"FIXED_PWM_NEGEDGE7:0" \
+"FIXED_PWM_NEGEDGE8:0" \
+"FIXED_PWM_NEGEDGE9:0" \
+"FIXED_PWM_NEGEDGE10:0" \
+"FIXED_PWM_NEGEDGE11:0" \
+"FIXED_PWM_NEGEDGE12:0" \
+"FIXED_PWM_NEGEDGE13:0" \
+"FIXED_PWM_NEGEDGE14:0" \
+"FIXED_PWM_NEGEDGE15:0" \
+"FIXED_PWM_NEGEDGE16:0" \
+"FIXED_PWM_POS_EN1:false" \
+"FIXED_PWM_POS_EN2:false" \
+"FIXED_PWM_POS_EN3:false" \
+"FIXED_PWM_POS_EN4:false" \
+"FIXED_PWM_POS_EN5:false" \
+"FIXED_PWM_POS_EN6:true" \
+"FIXED_PWM_POS_EN7:true" \
+"FIXED_PWM_POS_EN8:true" \
+"FIXED_PWM_POS_EN9:true" \
+"FIXED_PWM_POS_EN10:true" \
+"FIXED_PWM_POS_EN11:true" \
+"FIXED_PWM_POS_EN12:true" \
+"FIXED_PWM_POS_EN13:true" \
+"FIXED_PWM_POS_EN14:true" \
+"FIXED_PWM_POS_EN15:true" \
+"FIXED_PWM_POS_EN16:true" \
+"FIXED_PWM_POSEDGE1:0" \
+"FIXED_PWM_POSEDGE2:0" \
+"FIXED_PWM_POSEDGE3:0" \
+"FIXED_PWM_POSEDGE4:0" \
+"FIXED_PWM_POSEDGE5:0" \
+"FIXED_PWM_POSEDGE6:0" \
+"FIXED_PWM_POSEDGE7:0" \
+"FIXED_PWM_POSEDGE8:0" \
+"FIXED_PWM_POSEDGE9:0" \
+"FIXED_PWM_POSEDGE10:0" \
+"FIXED_PWM_POSEDGE11:0" \
+"FIXED_PWM_POSEDGE12:0" \
+"FIXED_PWM_POSEDGE13:0" \
+"FIXED_PWM_POSEDGE14:0" \
+"FIXED_PWM_POSEDGE15:0" \
+"FIXED_PWM_POSEDGE16:0" \
+"PWM_NUM:2" \
+"PWM_STRETCH_VALUE1:false" \
+"PWM_STRETCH_VALUE2:false" \
+"PWM_STRETCH_VALUE3:false" \
+"PWM_STRETCH_VALUE4:false" \
+"PWM_STRETCH_VALUE5:false" \
+"PWM_STRETCH_VALUE6:false" \
+"PWM_STRETCH_VALUE7:false" \
+"PWM_STRETCH_VALUE8:false" \
+"PWM_STRETCH_VALUE9:false" \
+"PWM_STRETCH_VALUE10:false" \
+"PWM_STRETCH_VALUE11:false" \
+"PWM_STRETCH_VALUE12:false" \
+"PWM_STRETCH_VALUE13:false" \
+"PWM_STRETCH_VALUE14:false" \
+"PWM_STRETCH_VALUE15:false" \
+"PWM_STRETCH_VALUE16:false" \
+"SEPARATE_PWM_CLK:false" \
+"SHADOW_REG_EN1:true" \
+"SHADOW_REG_EN2:true" \
+"SHADOW_REG_EN3:false" \
+"SHADOW_REG_EN4:false" \
+"SHADOW_REG_EN5:false" \
+"SHADOW_REG_EN6:false" \
+"SHADOW_REG_EN7:false" \
+"SHADOW_REG_EN8:false" \
+"SHADOW_REG_EN9:false" \
+"SHADOW_REG_EN10:false" \
+"SHADOW_REG_EN11:false" \
+"SHADOW_REG_EN12:false" \
+"SHADOW_REG_EN13:false" \
+"SHADOW_REG_EN14:false" \
+"SHADOW_REG_EN15:false" \
+"SHADOW_REG_EN16:false" \
+"TACH_EDGE1:false" \
+"TACH_EDGE2:false" \
+"TACH_EDGE3:false" \
+"TACH_EDGE4:false" \
+"TACH_EDGE5:false" \
+"TACH_EDGE6:false" \
+"TACH_EDGE7:false" \
+"TACH_EDGE8:false" \
+"TACH_EDGE9:false" \
+"TACH_EDGE10:false" \
+"TACH_EDGE11:false" \
+"TACH_EDGE12:false" \
+"TACH_EDGE13:false" \
+"TACH_EDGE14:false" \
+"TACH_EDGE15:false" \
+"TACH_EDGE16:false" \
+"TACH_NUM:1" \
+"TACHINT_ACT_LEVEL:false" }
+# Exporting Component Description of corepwm_C1 to TCL done
diff --git a/script_support/components/CAPE/DEFAULT/device-tree-overlay/cape-gpios.dtso b/script_support/components/CAPE/DEFAULT/device-tree-overlay/cape-gpios.dtso
index 289b7b60b6ec90009da028ca9c70153caadb721b..ffa69a707ca70c5159fe19dd1f473ce2a79951ce 100644
--- a/script_support/components/CAPE/DEFAULT/device-tree-overlay/cape-gpios.dtso
+++ b/script_support/components/CAPE/DEFAULT/device-tree-overlay/cape-gpios.dtso
@@ -10,7 +10,7 @@
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x41000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
clocks = <&fabric_clk3>;
status = "okay";
};
@@ -43,6 +43,24 @@
"", "", "P9_30", "", "P9_41",
"";
};
+
+ cape_pwm1: pwm@41400000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ reg = <0x0 0x41400000 0x0 0xF0>;
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ #pwm-cells = <3>;
+ status = "okay";
+ clocks = <&fabric_clk3>;
+ };
+
+ cape_pwm2: pwm@41500000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ reg = <0x0 0x41500000 0x0 0xF0>;
+ microchip,sync-update-mask = /bits/ 32 <0>;
+ #pwm-cells = <3>;
+ status = "okay";
+ clocks = <&fabric_clk3>;
+ };
};
};