From 3fd277f2a021d02d58bd239017f7420b01a37363 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Tue, 8 Nov 2022 21:31:51 +0000
Subject: [PATCH] Cape: Correct memory map for CorePWM and CoreGPIO.
Changed APB bus address decoding as follows:
- CorePWM: base address 0x41000000
- CoreGPIO: base address 0x41100000
---
script_support/components/CAPE/DEFAULT/CAPE.tcl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/script_support/components/CAPE/DEFAULT/CAPE.tcl b/script_support/components/CAPE/DEFAULT/CAPE.tcl
index d2f5125..8154e93 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE.tcl
@@ -12,12 +12,12 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -compon
"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
"APB_DWIDTH:32" \
"IADDR_OPTION:0" \
-"MADDR_BITS:28" \
+"MADDR_BITS:24" \
"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
"SC_12:false" "SC_13:false" "SC_14:false" \
"SC_15:false" \
-"UPR_NIBBLE_POSN:6"}
+"UPR_NIBBLE_POSN:5"}
sd_instantiate_component -sd_name {CAPE} -component_name {CoreAPB3_CAPE} -instance_name {}
--
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