From 03c53e61119f308c4590c546537245a86ee53279 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Wed, 27 Sep 2023 19:13:49 +0100
Subject: [PATCH] Cape: Add missing GPIOs to P9 default configuration.
---
.../components/CAPE/DEFAULT/ADD_CAPE.tcl | 3 +
.../components/CAPE/DEFAULT/CAPE.tcl | 280 +++++++++++-------
.../components/CAPE/DEFAULT/CAPE_CoreAPB.tcl | 13 +
.../components/CAPE/DEFAULT/CoreGPIO_P9.tcl | 138 +++++++++
.../components/CAPE/DEFAULT/P9_GPIO.tcl | 231 +++++++++++++++
.../CAPE/DEFAULT/constraints/cape.pdc | 42 +++
6 files changed, 602 insertions(+), 105 deletions(-)
create mode 100644 script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl
create mode 100644 script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl
create mode 100644 script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
diff --git a/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl b/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
index 8105274..7d826f4 100644
--- a/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
+++ b/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
@@ -4,8 +4,11 @@ puts "======== Add cape option: DEFAULT ========"
# Build cape's submodules
#-------------------------------------------------------------------------------
source script_support/components/CAPE/DEFAULT/APB_BUS_CONVERTER.tcl
+source script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl
source script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl
source script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+source script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl
+source script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
source script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
source script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
source script_support/components/CAPE/DEFAULT/CAPE.tcl
diff --git a/script_support/components/CAPE/DEFAULT/CAPE.tcl b/script_support/components/CAPE/DEFAULT/CAPE.tcl
index 72e2641..71f6f48 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE.tcl
@@ -2,124 +2,194 @@
set sd_name {CAPE}
create_smartdesign -sd_name ${sd_name}
-#-------------------------------------------------------------------------------
-# Create APB Bus
-#-------------------------------------------------------------------------------
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
-"APBSLOT0ENABLE:true" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:false" "APBSLOT3ENABLE:false" \
-"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
-"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
-"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
-"APB_DWIDTH:32" \
-"IADDR_OPTION:0" \
-"MADDR_BITS:24" \
-"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
-"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
-"SC_12:false" "SC_13:false" "SC_14:false" \
-"SC_15:false" \
-"UPR_NIBBLE_POSN:5"}
-
-sd_instantiate_component -sd_name {CAPE} -component_name {CoreAPB3_CAPE} -instance_name {}
-
-#-------------------------------------------------------------------------------
-# Create APB Bus Converter
-#-------------------------------------------------------------------------------
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN13_USER_LED_10} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN19} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN14} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN16} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN42} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN10_USER_LED_7} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN11_USER_LED_8} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN12_USER_LED_9} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN14_USER_LED_11} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN15} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN16} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN17} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN18} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN20} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN21} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN22} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN23} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN24} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN25} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN26} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN27} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN28} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN29} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN30} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN31} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN34} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN35} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN37} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN38} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN3_USER_LED_0} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN4_USER_LED_1} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN5_USER_LED_2} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN6_USER_LED_3} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN7_USER_LED_4} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN8_USER_LED_5} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN9_USER_LED_6} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN12} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN15} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN23} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN25} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN27} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN30} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN41} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PADDR} -port_direction {IN} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PWDATA} -port_direction {IN} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OE} -port_direction {IN} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[27:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_SLAVE_SLAVE_PADDR" \
+"PSELx:APB_SLAVE_SLAVE_PSEL" \
+"PENABLE:APB_SLAVE_SLAVE_PENABLE" \
+"PWRITE:APB_SLAVE_SLAVE_PWRITE" \
+"PRDATA:APB_SLAVE_SLAVE_PRDATA" \
+"PWDATA:APB_SLAVE_SLAVE_PWDATA" \
+"PREADY:APB_SLAVE_SLAVE_PREADY" \
+"PSLVERR:APB_SLAVE_SLAVE_PSLVERR" }
+
+# Add APB_BUS_CONVERTER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
-#-------------------------------------------------------------------------------
-# Add Default Cape GPIOs
-#-------------------------------------------------------------------------------
+
+
+# Add CAPE_DEFAULT_GPIOS instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_DEFAULT_GPIOS} -instance_name {CAPE_DEFAULT_GPIOS}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OUT} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OE} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_IN} -port_name {}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN3_USER_LED_0}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN4_USER_LED_1}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN5_USER_LED_2}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN6_USER_LED_3}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN7_USER_LED_4}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN8_USER_LED_5}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN9_USER_LED_6}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN10_USER_LED_7}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN11_USER_LED_8}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN12_USER_LED_9}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN14_USER_LED_11}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P8_PIN20}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P8_PIN21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P8_PIN22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P8_PIN23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P8_PIN24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P8_PIN25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P8_PIN26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P8_PIN27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P8_PIN28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P8_PIN29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_PIN30}
-
-
-#-------------------------------------------------------------------------------
-# P8
-#-------------------------------------------------------------------------------
+
+
+# Add CoreAPB3_CAPE_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_CAPE} -instance_name {CoreAPB3_CAPE_0}
+
+
+
+# Add P8_GPIO_UPPER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PCLK} -port_name {}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN32}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN33}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN34}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN35}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN36}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN37}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN38}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN39}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN40}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_PIN41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN42}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN43}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN44}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN45}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN46}
-
-
-
-#-------------------------------------------------------------------------------
-# PWM
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_0}
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_0} -port_name {}
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_1} -port_name {}
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_2} -port_name {}
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_3} -port_name {}
-sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_4} -port_name {}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_0_0} -new_port_name {P9_PIN42}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_1} -new_port_name {P9_PIN14}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_2} -new_port_name {P9_PIN16}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_3} -new_port_name {P8_PIN13_USER_LED_10}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_4} -new_port_name {P8_PIN19}
+# Add P9_GPIO_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance_name {P9_GPIO_0}
-#-------------------------------------------------------------------------------
-# Connections
-#-------------------------------------------------------------------------------
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "PWM_0:PRESETN"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "PWM_0:PCLK"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"}
+# Add PWM_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_0}
+
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {APB_BUS_CONVERTER_0:APB_SLAVE} -port_name {}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster"}
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_0_PAD" "P8_PIN3_USER_LED_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_11_PAD" "P8_PIN14_USER_LED_11" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_12_PAD" "P8_PIN15" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_13_PAD" "P8_PIN16" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_14_PAD" "P8_PIN17" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_15_PAD" "P8_PIN18" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_17_PAD" "P8_PIN20" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_18_PAD" "P8_PIN21" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_19_PAD" "P8_PIN22" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_1_PAD" "P8_PIN4_USER_LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_20_PAD" "P8_PIN23" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_21_PAD" "P8_PIN24" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_22_PAD" "P8_PIN25" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_23_PAD" "P8_PIN26" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_24_PAD" "P8_PIN27" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_25_PAD" "P8_PIN28" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_26_PAD" "P8_PIN29" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_27_PAD" "P8_PIN30" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_2_PAD" "P8_PIN5_USER_LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_3_PAD" "P8_PIN6_USER_LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_4_PAD" "P8_PIN7_USER_LED_4" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_5_PAD" "P8_PIN8_USER_LED_5" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_6_PAD" "P8_PIN9_USER_LED_6" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_7_PAD" "P8_PIN10_USER_LED_7" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_8_PAD" "P8_PIN11_USER_LED_8" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_9_PAD" "P8_PIN12_USER_LED_9" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_0_PAD" "P8_PIN31" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_10_PAD" "P8_PIN41" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_11_PAD" "P8_PIN42" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_12_PAD" "P8_PIN43" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_13_PAD" "P8_PIN44" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_14_PAD" "P8_PIN45" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_15_PAD" "P8_PIN46" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_1_PAD" "P8_PIN32" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_2_PAD" "P8_PIN33" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_3_PAD" "P8_PIN34" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_4_PAD" "P8_PIN35" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_5_PAD" "P8_PIN36" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_6_PAD" "P8_PIN37" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_7_PAD" "P8_PIN38" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_8_PAD" "P8_PIN39" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_9_PAD" "P8_PIN40" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PCLK" "P9_GPIO_0:PCLK" "PCLK" "PWM_0:PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PRESETN" "P9_GPIO_0:PRESETN" "PRESETN" "PWM_0:PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_PIN13_USER_LED_10" "PWM_0:PWM_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_PIN19" "PWM_0:PWM_4" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_10_PAD" "P9_PIN23" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_12_PAD" "P9_PIN25" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_14_PAD" "P9_PIN27" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_17_PAD" "P9_PIN30" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_19_PAD" "P9_PIN41" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_1_PAD" "P9_PIN12" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_4_PAD" "P9_PIN15" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN14" "PWM_0:PWM_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN16" "PWM_0:PWM_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN42" "PWM_0:PWM_0" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_IN" "GPIO_IN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OE" "GPIO_OE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OUT" "GPIO_OUT" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_SLAVE" "APB_SLAVE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave1" "P8_GPIO_UPPER_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave2" "P9_GPIO_0:APB_bif" }
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
diff --git a/script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl b/script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl
new file mode 100644
index 0000000..1ad5060
--- /dev/null
+++ b/script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl
@@ -0,0 +1,13 @@
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
+"APBSLOT0ENABLE:true" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:true" "APBSLOT3ENABLE:false" \
+"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
+"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
+"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
+"APB_DWIDTH:32" \
+"IADDR_OPTION:0" \
+"MADDR_BITS:24" \
+"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
+"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
+"SC_12:false" "SC_13:false" "SC_14:false" \
+"SC_15:false" \
+"UPR_NIBBLE_POSN:5"}
diff --git a/script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl b/script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl
new file mode 100644
index 0000000..1516b5a
--- /dev/null
+++ b/script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of CoreGPIO_P9 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreGPIO_P9
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_P9} -params {\
+"APB_WIDTH:32" \
+"FIXED_CONFIG_0:true" \
+"FIXED_CONFIG_1:true" \
+"FIXED_CONFIG_2:true" \
+"FIXED_CONFIG_3:true" \
+"FIXED_CONFIG_4:true" \
+"FIXED_CONFIG_5:true" \
+"FIXED_CONFIG_6:true" \
+"FIXED_CONFIG_7:true" \
+"FIXED_CONFIG_8:true" \
+"FIXED_CONFIG_9:true" \
+"FIXED_CONFIG_10:true" \
+"FIXED_CONFIG_11:true" \
+"FIXED_CONFIG_12:true" \
+"FIXED_CONFIG_13:true" \
+"FIXED_CONFIG_14:true" \
+"FIXED_CONFIG_15:true" \
+"FIXED_CONFIG_16:true" \
+"FIXED_CONFIG_17:true" \
+"FIXED_CONFIG_18:true" \
+"FIXED_CONFIG_19:true" \
+"FIXED_CONFIG_20:true" \
+"FIXED_CONFIG_21:false" \
+"FIXED_CONFIG_22:false" \
+"FIXED_CONFIG_23:false" \
+"FIXED_CONFIG_24:false" \
+"FIXED_CONFIG_25:false" \
+"FIXED_CONFIG_26:false" \
+"FIXED_CONFIG_27:false" \
+"FIXED_CONFIG_28:false" \
+"FIXED_CONFIG_29:false" \
+"FIXED_CONFIG_30:false" \
+"FIXED_CONFIG_31:false" \
+"INT_BUS:0" \
+"IO_INT_TYPE_0:7" \
+"IO_INT_TYPE_1:7" \
+"IO_INT_TYPE_2:7" \
+"IO_INT_TYPE_3:7" \
+"IO_INT_TYPE_4:7" \
+"IO_INT_TYPE_5:7" \
+"IO_INT_TYPE_6:7" \
+"IO_INT_TYPE_7:7" \
+"IO_INT_TYPE_8:7" \
+"IO_INT_TYPE_9:7" \
+"IO_INT_TYPE_10:7" \
+"IO_INT_TYPE_11:7" \
+"IO_INT_TYPE_12:7" \
+"IO_INT_TYPE_13:7" \
+"IO_INT_TYPE_14:7" \
+"IO_INT_TYPE_15:7" \
+"IO_INT_TYPE_16:7" \
+"IO_INT_TYPE_17:7" \
+"IO_INT_TYPE_18:7" \
+"IO_INT_TYPE_19:7" \
+"IO_INT_TYPE_20:7" \
+"IO_INT_TYPE_21:7" \
+"IO_INT_TYPE_22:7" \
+"IO_INT_TYPE_23:7" \
+"IO_INT_TYPE_24:7" \
+"IO_INT_TYPE_25:7" \
+"IO_INT_TYPE_26:7" \
+"IO_INT_TYPE_27:7" \
+"IO_INT_TYPE_28:7" \
+"IO_INT_TYPE_29:7" \
+"IO_INT_TYPE_30:7" \
+"IO_INT_TYPE_31:7" \
+"IO_NUM:21" \
+"IO_TYPE_0:2" \
+"IO_TYPE_1:2" \
+"IO_TYPE_2:2" \
+"IO_TYPE_3:2" \
+"IO_TYPE_4:2" \
+"IO_TYPE_5:2" \
+"IO_TYPE_6:2" \
+"IO_TYPE_7:2" \
+"IO_TYPE_8:2" \
+"IO_TYPE_9:2" \
+"IO_TYPE_10:2" \
+"IO_TYPE_11:2" \
+"IO_TYPE_12:2" \
+"IO_TYPE_13:2" \
+"IO_TYPE_14:2" \
+"IO_TYPE_15:2" \
+"IO_TYPE_16:2" \
+"IO_TYPE_17:2" \
+"IO_TYPE_18:2" \
+"IO_TYPE_19:2" \
+"IO_TYPE_20:0" \
+"IO_TYPE_21:0" \
+"IO_TYPE_22:0" \
+"IO_TYPE_23:0" \
+"IO_TYPE_24:0" \
+"IO_TYPE_25:0" \
+"IO_TYPE_26:0" \
+"IO_TYPE_27:0" \
+"IO_TYPE_28:0" \
+"IO_TYPE_29:0" \
+"IO_TYPE_30:0" \
+"IO_TYPE_31:0" \
+"IO_VAL_0:0" \
+"IO_VAL_1:0" \
+"IO_VAL_2:0" \
+"IO_VAL_3:0" \
+"IO_VAL_4:0" \
+"IO_VAL_5:0" \
+"IO_VAL_6:0" \
+"IO_VAL_7:0" \
+"IO_VAL_8:0" \
+"IO_VAL_9:0" \
+"IO_VAL_10:0" \
+"IO_VAL_11:0" \
+"IO_VAL_12:0" \
+"IO_VAL_13:0" \
+"IO_VAL_14:0" \
+"IO_VAL_15:0" \
+"IO_VAL_16:0" \
+"IO_VAL_17:0" \
+"IO_VAL_18:0" \
+"IO_VAL_19:0" \
+"IO_VAL_20:0" \
+"IO_VAL_21:0" \
+"IO_VAL_22:0" \
+"IO_VAL_23:0" \
+"IO_VAL_24:0" \
+"IO_VAL_25:0" \
+"IO_VAL_26:0" \
+"IO_VAL_27:0" \
+"IO_VAL_28:0" \
+"IO_VAL_29:0" \
+"IO_VAL_30:0" \
+"IO_VAL_31:0" \
+"OE_TYPE:0" }
+# Exporting Component Description of CoreGPIO_P9 to TCL done
diff --git a/script_support/components/CAPE/DEFAULT/P9_GPIO.tcl b/script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
new file mode 100644
index 0000000..bb4d161
--- /dev/null
+++ b/script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
@@ -0,0 +1,231 @@
+# Creating SmartDesign P9_GPIO
+set sd_name {P9_GPIO}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSLVERR} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_10_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_12_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_14_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_17_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_19_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_1_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_4_PAD} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_bif} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_bif_PADDR" \
+"PSELx:APB_bif_PSEL" \
+"PENABLE:APB_bif_PENABLE" \
+"PWRITE:APB_bif_PWRITE" \
+"PRDATA:APB_bif_PRDATA" \
+"PWDATA:APB_bif_PWDATA" \
+"PREADY:APB_bif_PREADY" \
+"PSLVERR:APB_bif_PSLVERR" }
+
+# Add CoreGPIO_P9_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P9} -instance_name {CoreGPIO_P9_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[0:0]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[0:0]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[11:11]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[11:11]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[13:13]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[13:13]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[15:15]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[15:15]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[16:16]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[16:16]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[18:18]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[18:18]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[20:20]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[20:20]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[2:2]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[2:2]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[3:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[3:3]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[5:5]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[5:5]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[6:6]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[6:6]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[7:7]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[7:7]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[8:8]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[8:8]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[9:9]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[9:9]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[16:16]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[18:18]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[20:20]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[20:20]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[0:0]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[11:11]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[13:13]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[15:15]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[16:16]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[18:18]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[20:20]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[20:20]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[2:2]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[3:3]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[5:5]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[6:6]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[7:7]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[8:8]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:INT}
+
+
+
+# Add GPIO_1_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+
+
+
+# Add GPIO_4_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+
+
+
+# Add GPIO_10_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+
+
+
+# Add GPIO_12_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+
+
+
+# Add GPIO_14_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+
+
+
+# Add GPIO_17_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_17_BIBUF}
+
+
+
+# Add GPIO_19_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_19_BIBUF}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[17:17]" "GPIO_17_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[19:19]" "GPIO_19_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[17:17]" "GPIO_17_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[19:19]" "GPIO_19_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[17:17]" "GPIO_17_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[19:19]" "GPIO_19_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_10_BIBUF:PAD" "GPIO_10_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_12_BIBUF:PAD" "GPIO_12_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_14_BIBUF:PAD" "GPIO_14_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_17_BIBUF:PAD" "GPIO_17_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_19_BIBUF:PAD" "GPIO_19_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_1_BIBUF:PAD" "GPIO_1_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_4_BIBUF:PAD" "GPIO_4_PAD" }
+
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_bif" "CoreGPIO_P9_0:APB_bif" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign P9_GPIO
+generate_component -component_name ${sd_name}
diff --git a/script_support/components/CAPE/DEFAULT/constraints/cape.pdc b/script_support/components/CAPE/DEFAULT/constraints/cape.pdc
index 39b8ae4..32935b6 100644
--- a/script_support/components/CAPE/DEFAULT/constraints/cape.pdc
+++ b/script_support/components/CAPE/DEFAULT/constraints/cape.pdc
@@ -5,6 +5,12 @@ set_io -port_name P9_11 \
-io_std LVCMOS33 \
-DIRECTION INOUT
+set_io -port_name P9_PIN12 \
+ -pin_name C5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
set_io -port_name P9_13 \
-pin_name D19 \
-fixed true \
@@ -17,12 +23,48 @@ set_io -port_name P9_PIN14 \
-io_std LVCMOS33 \
-DIRECTION OUT
+set_io -port_name P9_PIN15 \
+ -pin_name A5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
set_io -port_name P9_PIN16 \
-pin_name A6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
+set_io -port_name P9_PIN23 \
+ -pin_name C12 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_PIN25 \
+ -pin_name B7 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_PIN27 \
+ -pin_name D11 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_PIN30 \
+ -pin_name F16 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_PIN41 \
+ -pin_name E15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
set_io -port_name P9_PIN42 \
-pin_name E14 \
-fixed true \
--
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