proposals/2024/index.rst

+.. _gsoc-2024-proposals:
+
+:far:`calendar-days` 2024
+##########################
+
+.. toctree::
+    :maxdepth: 1
+    
+    ijc/index
+    aryan_nanda/index
+    roger18/index
+    melta101/index
\ No newline at end of file

proposals/2024/melta101/index.rst

+.. _gsoc-proposal-melta101:
+
+Upstream Zephyr Support on BeagleBone AI-64 R5 - Dhruv Menon
+############################################################
+
+Introduction
+*************
+
+Introducing Zephyr RTOS support for the BeagleBone AI-64 platform, with the aim of upstreaming it to the Zephyr repository. Our focus will be on enhancing driver 
+support for essential communication protocols on the TDA4VM SoC. Additionally, we plan to implement inter-process communication (IPC) mechanisms 
+to facilitate message queuing between the A72 core and R5 cores, thereby enabling efficient communication and coordination within the system. This endeavor seeks to empower developers 
+with a robust real-time operating system foundation and comprehensive hardware support for embedded applications on the BeagleBone AI-64 platform.
+
+
+Summary links
+=============
+
+- **Contributor:** `Dhruv Menon <https://forum.beagleboard.org/u/malto101/summary>`_
+- **Mentors:** `Dhruva Gole <https://forum.beagleboard.org/u/dhruvag2000>`_, `Nishanth Menon <https://forum.beagleboard.org/u/nishanth_menon>`_, `Andrew Davis <https://github.com/glneo>`_
+- **Code:** TBD
+- **Documentation:** TBD
+- **GSoC:** NA
+
+Status
+=======
+
+This project is currently just a proposal.
+
+Proposal
+========
+
+- Created accounts across `OpenBeagle <https://openbeagle.org/melta101>`_, `Discord <https://discord.com/users/748434262146940950>`_ and `Beagle Forum <https://forum.beagleboard.org/u/malto101/summary>`_.
+- The PR Request for Cross Compilation: `#184 <https://github.com/jadonk/gsoc-application/pull/184>`_  
+- Created a project proposal using the `proposed template <https://gsoc.beagleboard.io/proposals/template.html>`_.
+
+About 
+=====
+
+- **Forum:** :fab:`discourse` `u/malto101 (Dhruv Menon) <https://forum.beagleboard.org/u/malto101/summary>`_
+- **OpenBeagle:** :fab:`gitlab` `melta101 (Dhruv Menon) <https://openbeagle.org/melta101>`_
+- **Github:** :fab:`github` `malto101 (Dhruv Menon) <https://github.com/malto101>`_
+- **School:** :fas:`school` `Manipal Institute of Technology <https://www.manipal.edu/mit.html>`_
+- **Country:** :fas:`flag` India
+- **Primary language:** :fas:`language` Englsih
+- **Typical work hours:** :fas:`clock` 8AM-5PM Indian Standard Time
+- **Previous GSoC participation:** :fab:`google` N/A
+
+Project
+********
+
+**Project name:** Upstream Zephyr Support on BeagleBone AI-64 R5
+
+Description
+============
+
+The `Beaglebone AI 64 <https://www.beagleboard.org/boards/beaglebone-ai-64>`_ platform is a formidable tool for developing embedded systems, Zephyr OS support will allow it to reach even greater potential. 
+Zephyr is a lightweight real-time operating system that improves embedded applications' scalability, flexibility, and dependability.
+
+Part of the `Beaglebone AI 64 <https://www.beagleboard.org/boards/beaglebone-ai-64>`_ platform, the    System-on-Chip (SoC) has an intricate architecture that includes two Arm Cortex-A72 cores and four 
+Arm Cortex-R5F cores. An addditional two Arm Cortex-R5F cores are located on a different MCU island. Such configurations epitomize asymmetric multiprocessing (AMP), 
+facilitating the concurrent operation of a full-fledged operating system (OS) alongside a real-time operating system (RTOS).
+
+The suggested approach uses :ref:`remoteproc<RemoteProc>` from the Linux-powered A72 core to load the Zephyr RTOS onto the BeagleBone AI 64. Upstreaming Zephyr support for the BeagleBone AI 64
+platform is the main goal of this project, which builds on the foundation set by the previous Google Summer of Code (GSoC) contributor which already includes crucial support for 
+features like the `VIM interrupt controller <https://github.com/zephyrproject-rtos/zephyr/pull/60856>`_, `DM timer <https://github.com/zephyrproject-rtos/zephyr/pull/61020>`_ for 
+systick, and `Davinci <https://github.com/zephyrproject-rtos/zephyr/pull/61316>`_ GPIO controller on the J721E SoC. Defining Kconfig based existing board support and using the current
+`Hardware Model v2(HWMv2) <https://github.com/zephyrproject-rtos/zephyr/issues/51831>`_ instead of previous OOT(Out of the Tree) model while Adding major drivers to allow seemless interaction such as I2C, SPI, mailbox. In addition, the project attempts to show seamless communication 
+across cores by introducing example instances of Inter-Process Communication (IPC) for example, we could use message queues to synchronize events.
+
+.. admonition:: Defination
+
+  - **Vectored Interrupt Manager (VIM)**: interrupts to Cortex R5F are managed through VIM in TDA4VM.
+  - **DM Timer**: The DM timer module generates the system tick. The interupt is caused by overflowing, compare or capture.
+  - **Davinci GPIO controller**: The controller provides functionality for managing digital input and output signals, allowing the SoC to interact with external devices and peripherals.
+
+Motivation
+===========
+
+1. Extend Platform capabilities by offloading some services(for example DSP) on the MCU.
+2. Manage diversity of services on a single link.
+3. Introduces fault isolation by segragating critical tasks onto dedicated cores.
+
+But why Zephyr?
+================
+
+`Zephyr RTOS <https://docs.zephyrproject.org/latest/index.html>`_ (Real time Operating System) is a robust and flexible option for developing embedded systems, including real-time functionality, scalability, portability, security, flexibility, 
+and a vibrant community. Zephyr offers the essential capabilities and tools to develop embedded applications effectively and dependably, regardless of the complexity 
+of the device—from basic sensor nodes to intricate IoT devices. The Cortex R5 processor core present on the TDS4VM are built to provide deeply embedded **real-time and 
+safety-critical systems**. Thus, adding Zephyr RTOS support for R5 cores in TDA4VM will be very helpful for the product developers.
+
+.. important:: 
+
+  Zephyr recently began supporting `AMP <https://en.wikipedia.org/wiki/Asymmetric_multiprocessing>`_ System-on-Chip (SoC) architectures, exemplified by the introduction of the `Hardware Model v2 (HWMv2) <https://github.com/zephyrproject-rtos/zephyr/pull/69607>`_. 
+  This is significant as AMP architectures, like TDA4VM, feature heterogeneous cores with varying processing capabilities, allowing for efficient distribution of tasks between different cores based on their strengths.
+
+.. image:: images/Test_OpenAMP.png
+  :alt: Workflow
+  :align: center
+
+.. centered:: 
+  [1]
+ 
+
+.. _RemoteProc:
+
+remoteproc
+==========
+
+The remote processor (`rproc <https://docs.kernel.org/staging/remoteproc.html>`_) framework serves as a robust solution for managing remote processor devices within modern System-on-Chips (SoCs) and is particularly geared towards heterogeneous multicore processing (HMP) setups. 
+This innovative framework provides the means to control various aspects of remote processors, such as **loading and executing firmware**, all while effectively abstracting the underlying hardware differences. Furthermore, it extends 
+its utility by offering services for monitoring remote coprocessors, thereby ensuring management and operation.
+
+The Linux running on the Cortex-A72 uses the remoteproc framework to manage the Cortex-R5F co-processor. Therefore, the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc.
+
+.. _RPMsg:
+
+Remote Processor Messaging (rpmsg) Framework
+=============================================
+
+Typically AMP(Asymmetric Multiprocessing Processor) remote processors employ dedicated DSP codecs and multimedia hardware accelerators, and therefore are often used to offload CPU-intensive multimedia tasks from the main application processor.
+These remote processors could also be used to control latency-sensitive sensors, drive random hardware blocks, or just perform background tasks while the main CPU is idling. Rpmsg is a **virtio-based messaging bus** 
+that allows kernel drivers to communicate with remote processors available on the system. In turn, drivers could then expose appropriate user space interfaces, if needed. is a message passing mechanism that requests 
+resources through :ref:`remoteproc <RemoteProc>` and builds on top of the virtio framework. Shared buffers are requested through the resource_table and provided by the remoteproc module during Zephyr firmware loading
+
+.. image:: images/RPMSG.png
+  :alt: RPMsg
+  :align: center
+
+.. centered:: 
+  [2]
+
+.. admonition:: Defination
+
+  - **Vring**: SW queue that is based on shared memory and is used to keep messages while they are being exchanged between two CPUs.
+  - **HW Mailbox**: Hardware mechanism that notifies two CPUs of an interrupt
+
+.. _OpenAMP:
+
+Open Asymmetric multiprocessing(OpenAMP) Framework
+==================================================
+
+The OpenAMP framework provides software components that enable development of software applications for Asymmetric Multiprocessing (AMP) systems. The framework provides key capabilities such as **Life Cycle Management**, and **Inter Processor Communication** capabilities and Provides a stand alone library usable with zephyr environments
+Life Cycle Management (LCM) in OpenAMP is provided by the :ref:`remoteproc<RemoteProc>` component. Remoteproc APIs allow software applications running on the master processor to manage the life cycle of a remote processor and its software context while IPC(Inter Process Communication) a mechanism that allows processes to communicate with each other and synchronize their actions. 
+The communication between these processes can be seen as a method of co-operation between them. Processes can communicate with each other through both: Shared Memory and Message passing
+
+.. _TISCI:
+
+TI-SCI(Texas Instruments System Controller Interface)
+======================================================
+
+SCI is one the primary communication protocol for a TDA4VM processor from which the host uses multiple threads to communicate with the systems firmware. This is a set of message formats and operation sequence required to talk to the system service in the SoC.
+
+
+.. image:: images/TI-SCI.png
+  :alt: TI-SCI
+  :align: center
+
+.. centered:: 
+  [3]
+
+The Cortex-R5F core acts as the SCI server, which means it hosts the TISCI firmware responsible for managing system resources and peripherals while The Cortex-A72 core acts as the SCI client, interacting with the TISCI firmware running on the Cortex-R5F core.
+
+- Upon boot up, The SCI client (A72) will initialize the communication channels with the SCI server (R5F), ensuring bidirectional communication for sending commands and receiving responses.
+- Client can request resource allocation, set clock frequencies, manage power domains, configure interrupt controllers, and control peripheral devices on the system.
+- The Client can also query with the SCI server for status of the device.
+
+.. important::
+  Upon implementation of SCI, we can add device management support to either control the state of a module or control the frequency of the clock to a module/(device reset control). In addition to the above messages, the TISCI also supports certain general messages.
+
+The base scenario will be where MCU1_0 having the Zephyr RTOS will act as the SCI server and allow other client to communicate with it. TO begin, we will be providing the support for SCI client.
+
+Expected System architecture
+============================
+
+The scope of the project by the end is shown below:
+
+.. image:: images/systemarch.png
+  :alt: System Architecture
+  :align: center
+
+
+Software
+=========
+
+- C
+- Zephyr RTOS
+
+Hardware
+========
+
+- `Beaglebone AI 64 <https://www.beagleboard.org/boards/beaglebone-ai-64>`_
+
+Timeline summary
+******************
+
+.. table:: 
+
+    +------------------------+----------------------------------------------------------------------------------------+
+    | Date                   | Activity                                                                               |                                  
+    +========================+========================================================================================+
+    | February 26            | Connect with possible mentors and request review on first draft                        |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | March 4                | Complete prerequisites, verify value to community and request review on second draft   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | March 11               | Finalized timeline and request review on final draft                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | March 21               | Submit application                                                                     |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | May 1                  | Start bonding                                                                          |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | May 27                 | Start coding and introductory video                                                    |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | June 3                 | :ref:`ZR5Milestone1`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | June 10                | :ref:`ZR5Milestone2`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | June 17                | :ref:`ZR5Milestone3`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | June 24                | :ref:`ZR5Milestone4`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | July 1                 | :ref:`ZR5Milestone5`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | July 8                 | :ref:`ZR5Midterm`                                                                      |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | July 15                | :ref:`ZR5Milestone6`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | July 22                | :ref:`ZR5Milestone7`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | July 29                | :ref:`ZR5Milestone8`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | August 5               | :ref:`ZR5Milestone9`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | August 12              | :ref:`ZR5Milestone10`                                                                  |
+    +------------------------+----------------------------------------------------------------------------------------+
+    | August 19              | :ref:`ZR5FinalVideo`                                                                   |
+    +------------------------+----------------------------------------------------------------------------------------+
+
+Timeline detailed
+*******************
+
+Community Bonding Period (May 1st - May 26th)
+==============================================
+
+- Acquiring the `Board <https://www.beagleboard.org/boards/beaglebone-ai-64>`_ and hardware ready.
+- interaction with mentor for feedback.
+- Mastering the hardware nuances and intricacies of the `Zephyr codebase <https://github.com/zephyrproject-rtos/zephyr>`_.
+- look deeper into `Prashanth.S <https://github.com/zephyrproject-rtos/zephyr/pull/59191>`_ commits
+
+Coding begins (May 27th)
+=========================
+
+- Setting up Zephyr Environment.
+- Flash the linux image on the A72 core.
+- Boot the Cortex R5 firmware remotely from a Linux instance running on the A72 core using remoteproc.
+
+.. _ZR5Milestone1:
+
+Milestone #1, Introductory YouTube video (June 3rd)
+===================================================
+
+- Include a introductory video.
+- Write basic hello world on the board.
+- Leverage resources from previous GSoC contributions to create the board directory .
+  for the Beaglebone AI-64. This includes Kconfig configuration files and Device Tree (DT) definitions according to the HWMv2.
+- Integrate `west toolchain manager <https://docs.zephyrproject.org/latest/develop/west/index.html>`_ with the Zephyr build system for streamlined package management and compilation.
+- Prepare Documentation.
+- Add DM Timer support based out of `Prashanth DM Timer <https://github.com/zephyrproject-rtos/zephyr/pull/61020>`_.
+
+.. _ZR5Milestone2:
+
+Milestone #2 (June 10th)
+==========================
+
+- UART controller support in Zephyr for the SoC and bring up the shell through that. Configure the DT to 
+  enable the chosen UART port and integrate the driver with the board code. This will enable a serial console 
+  for debugging and interaction.
+- Test using the `UART echo <https://docs.zephyrproject.org/latest/samples/drivers/uart/echo_bot/README.html>`_ sample.
+- Add Support to GPIO controller based out of `Prashanth Davinci GPIO controller <https://github.com/zephyrproject-rtos/zephyr/pull/61316>`_.
+
+.. _ZR5Milestone3:
+
+Milestone #3 (June 17th)
+=========================
+
+- Add additional perpheral support for I2C, SPI.
+- Test I2C, SPI using sensor examples from zephyr (For example: `MPU6050 <https://docs.zephyrproject.org/latest/samples/sensor/mpu6050/README.html>`_ or use another MCU to interface with it) 
+
+.. _ZR5Milestone4:
+
+Milestone #4 (June 24th)
+==========================
+
+- Develop message passing protocols, shared memory regions, and synchronization primitives.This framework should include
+  functional device drivers, appropriate SoC configurations, and tested communication mechanisms ready for further development and refinement in subsequent milestones.
+ 
+
+.. _ZR5Milestone5:
+
+Milestone #5 (July 1st)
+========================
+
+- Provide basic support for IPC between RTOS and the Linux subsystem by introducing the drivers and SoC config for IPC. Either using Message queues or the shared memory approach.
+
+.. _ZR5Midterm:
+
+Submit midterm evaluations (July 8th)
+=====================================
+
+.. important:: 
+    
+    **July 12 - 18:00 UTC:** Midterm evaluation deadline (standard coding period) 
+
+- Clean up the documentation.
+
+.. _ZR5Milestone6:
+
+Milestone #6 (July 15th)
+=========================
+
+- Provide Mailbox(Secure Proxy) support for BeagleBone AI 64.
+
+.. admonition:: Defination
+
+  - **Mailbox**: A mailbox is a kernel object that provides enhanced message queue capabilities that go beyond the capabilities of a message queue object. A mailbox allows threads to send and receive messages of any size synchronously or asynchronously.
+  - **Secure Proxy Mailbox**: Texas Instruments own mailbox controller
+
+.. _ZR5Milestone7:
+
+Milestone #7 (July 22nd)
+=========================
+
+- Develop a Zephyr driver for the TI-SCI (System Control Interface) according to Zephyr's 
+  Hardware Abstraction Layer (HAL) standard with refernce to `TI PSDK-J721E <https://www.ti.com/tool/PROCESSOR-SDK-J721E>`_. This enables a more portable and reusable driver implementation.
+
+.. _ZR5Milestone8:
+
+Milestone #8 (July 29th)
+=========================
+
+- Provide Support for TI-SCI(System Control Interface)
+
+.. _ZR5Milestone9:
+
+Milestone #9 (Aug 5th)
+=======================
+
+- While adding SCI support, Include a interrupt routing support which can let Zephyr effectively handle hardware interrupts.
+
+.. _ZR5Milestone10:
+
+Milestone #10 (Aug 12th)
+========================
+
+- Include support for the Arm Cortex-R5F to control clocks via the device manager using Ti-SCI.
+
+.. _ZR5FinalVideo:
+
+Final YouTube video (Aug 19th)
+===============================
+
+- Submit final project video, submit final work to GSoC site 
+  and complete final mentor evaluation
+- Provide few examples to help kickstart other member of the community. 
+
+Final Submission (Aug 24nd)
+============================
+
+.. important::
+
+    **August 19 - 26 - 18:00 UTC:** Final week: GSoC contributors submit their final work 
+    product and their final mentor evaluation (standard coding period)
+
+    **August 26 - September 2 - 18:00 UTC:** Mentors submit final GSoC contributor 
+    evaluations (standard coding period)
+
+Initial results (September 3)
+=============================
+
+.. important:: 
+    **September 3 - November 4:** GSoC contributors with extended timelines continue coding
+
+    **November 4 - 18:00 UTC:** Final date for all GSoC contributors to submit their final work product and final evaluation
+
+    **November 11 - 18:00 UTC:** Final date for mentors to submit evaluations for GSoC contributor projects with extended deadline
+
+Experience and approach
+***********************
+
+- Was successful in utilizing remoteproc to load firmware into the BeagleBone AI-64's R5 core.
+- Part of the Deveopment for a custom AD9364 Transciever device driver in a Zynq MPSoC Evaluation kit.
+- Successfully done board bring-up for mainly `32-bit MCUs <https://github.com/malto101/Basic_STM32_mouse_Firmware>`_, integrating crucial functionalities such as USB, UART, I2C, and SPI protocols.
+- Developed device (character and user-mode) drivers for prominent platforms including Beaglebone, Nvidia Jetson, and Raspberry Pi.
+- Freelanced a `HID over GATT <https://github.com/malto101/USB_BLE_HID>`_ (HoG) firmware capable of mouse control controled through USB connectivity using **Zephyr RTOS**.
+- Engineered a system enabling seamless communication between a QT application and GNU Radio backend, leveraging a HackRF device and STM32MP1. This system facilitates dynamic adjustment of modulation schemes.
+
+Contingency
+===========
+
+Upon encountering a roadblock in my project without access to my mentor, I'll leverage online resources, documentation, and peer forums from both BeagleBoard and Zephyr community to troubleshoot
+and find a solution independently. I have also been in contact with people who have themselves upstreamed zephyr support for SBCs(Single Board Computer).
+
+Benefit
+========
+
+- Zephyr being a popular RTOS option, can help users with BeagleBone AI-64 use Zephyr without touching the lower level code and concentrate on thier application
+- Adding Zephyr support will also increase the interoperability with other devices and systems
+- Operating RTOS and Linux side by side can lead to a wide range of application which are time constrained.
+
+References
+============
+
+- [1] https://www.google.com/url?sa=i&url=https%3A%2F%2Fwww.openampproject.org%2Fdocs%2Fwhitepapers%2FIntroduction_to_OpenAMPlib_v1.1a.pdf&psig=AOvVaw2EJ_cAYMdy7vgQ-Zdrykff&ust=1711958394883000&source=images&cd=vfe&opi=89978449&ved=0CBUQ3YkBahcKEwiIq7ORhJ6FAxUAAAAAHQAAAAAQFQ
+- [2] https://medium.com/@warrierabhinav/a-novel-communication-stack-for-a-heterogeneous-multicore-system-with-asymmetric-multiprocessing-fcd93523ee77
+- [3] https://software-dl.ti.com/tisci/esd/latest/1_intro/TISCI.html
+- https://github.com/zephyrproject-rtos/zephyr/pull/59191
+- https://github.com/zephyrproject-rtos/zephyr
+- https://docs.zephyrproject.org/latest/kernel/services/data_passing/mailboxes.html
+- https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/07_02_00_06/exports/docs/pdk_jacinto_07_01_05_14/docs/userguide/jacinto/overview.html
+- https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/09_00_00_02/exports/docs/pdk_jacinto_09_00_00_45/docs/apiguide/j721e/html/index.html
+- https://github.com/OpenAMP/open-amp/wiki

proposals/2024/roger18/index.rst

+.. _gsoc-2024-proposal-roger18:
+
+Low-latency I/O RISC-V CPU core in FPGA fabric - Atharva Kashalkar
+##################################################################
+
+Introduction
+*************
+
+Implementation of PRU subsystem on BeagleV-Fire's FPGA fabric, resulting in a real-time microcontroller system working alongside the main CPU, providing low-latency access to I/O .
+
+Summary links
+=============
+
+- **Contributor:** `Atharva Kashalkar <https://forum.beagleboard.org/u/roger18>`_
+- **Mentors:** `Jason Kridner <https://forum.beagleboard.org/u/jkridner>`_, `Cyril Jean <https://forum.beagleboard.org/u/vauban>`_
+- **Code Repository:**
+- - *Upstream Repository:* `BeagleV-Fire gateware <https://openbeagle.org/beaglev-fire/gateware>`_
+- - *Daily Code Check-in Repository:* `Fork for BeagleV-Fire gateware <https://openbeagle.org/Roger18/gateware>`_
+- **Weekly/biweekly Updates Forums Thread:** `Progress Reports <https://forum.beagleboard.org/t/weekly-progress-report-low-latency-i-o-risc-v-cpu-core-in-fpga-fabric/38488>`_
+- **Blog:** `TechTales <https://rapidroger18.github.io/>`_
+
+Status
+=======
+
+This project is selected for GSOC 2024.
+
+Proposal
+========
+
+| Accounts created across `OpenBeagle <https://openbeagle.org/Roger18>`_, `Discord <https://discordapp.com/users/539789356228018200>`_ and `Beagle Forum <https://forum.beagleboard.org/u/roger18>`_
+| PR was created for the cross-compilation task.
+
+About 
+=====
+
+- **Resume:** Find my resume `here <https://docs.google.com/document/d/1NK4dAuWjMRkkG4YJrMSHrUTxJs0s7_JUR-DipmuclWQ/edit?usp=sharing>`_
+- **Forum:** :fab:`discourse` `u/roger18 (Atharva Kashalkar) <https://forum.beagleboard.org/u/roger18>`_
+- **OpenBeagle:** :fab:`gitlab` `Roger18 (Atharva Kashalkar) <https://openbeagle.org/Roger18>`_
+- **Github:** :fab:`github` `RapidRoger18 (Atharva Kashalkar) <https://github.com/RapidRoger18>`_
+- **School:** :fas:`school` Veermata Jijabai Technological Institute (VJTI)
+- **Country:** :fas:`flag` India
+- **Primary language:** :fas:`language` English Hindi
+- **Typical work hours:** :fas:`clock` 9 AM-11 PM Indian Standard Time
+- **Previous GSoC participation:** :fab:`google` First Time Applicant
+
+Project
+********
+
+**Project name:** Low-latency I/O RISC-V CPU core in FPGA fabric.
+
+Description
+============
+To provide the capability of a Programmable Real-time Unit Industrial Control SubSystem (PRU-ICSS), which is present on several BeagleBone boards, I propose to deploy an existing RISC-V 32IM core with a customized Instruction Set on FPGA Fabric present on BeagleV-Fire. The goal of this deployment is to provide high bandwidth between the CPU and I/O, resulting in a on-board microcontroller.
+
+Goals and Objectives
+====================
+
+The main aim of this project is to deploy a soft core subsystem on BeagleV-Fire’s FPGA fabric, functionally equivalent to PRU subsystem on BeagleBone Black. The core will feature RISC-V ISA customised to perform ultra low-latency I/O operations, i.e., single-cycle execution. This deployment will provide high-bandwidth data transfer in main CPU and I/O and also ensure high speed data processing similar to a microcontroller.
+
+The programmable nature of the PRU, along with its access to pins, events, and all SoC resources, provides flexibility in implementing fast real-time responses, specialised data handling operations, custom peripheral interfaces, and in offloading tasks from the main processor cores of the system-on-chip (SoC).
+
+.. image:: images/PRU_diagram.png 
+
+Based on the requirements of the project, it is most efficient to use PicoRV (an open source RISC-V based processor) as a base and modify it to perform high speed I/O operations. The PicoRV possesses excellent compiler support and diverse instruction set but lacks I/O support and single-cycle execution for some instructions.
+
+This problem will be resolved within the first stage of the project, which will focus on making the core I/O compatible and modifying its execution flow to ensure single-cycle execution for all instructions. Some present soft processor IPs like AMD’s Microblaze used in Vivado Design Suite and Microchip’s Mi-V used in Libero Design suite can provide good insights on how a functioning soft core IP will look like.
+As the Stage-1 of this project concludes with deployment of the RV core, Stage-2 will focus on establishing a communication medium between the PRU and the main CPU. This will ensure the ‘on-the-fly’ programming for the PRU and high bandwidth data transfer from I/O to the main CPU.
+
+*riscv64-unknown-elf-gcc* compiler will compile the C program into bare-metal RISC-V based binary instructions within the linux booted on the main CPU. The communication between main CPU and PRU will be used to send these instructions into the program memory of PRU without needing to flash the FPGA each time.
+
+This connection can be established in multiple ways: 
+
+1. The Program Memory of the PRU can be written into SPI flash that contains FPGA logic, and the data transfer will take place through 32-bit interconnecting AXI bus.
+2. Shared memory between PRU and Main CPU can be used of PRU memory and Data Transfer.
+3. 32-bit interconnecting AXI bus can be used to write instructions into Program memory of PRU which will be printed on FPGA logic, the same AXI bus will be used for other Data Transfers.
+
+The 32-bit interconnecting AXI bus is more suitable for burst write data to RAMs, thus using shared memory or SPI flash makes suitable method to serve as a communication medium between PRU and CPU to ensure efficient and smooth processing.
+
+At the conclusion of the project, BeagleV-Fire will host a fully functional PRU system that can be controlled and programmed through the main CPU.
+
+Software
+=========
+
+ - Verilog HDL.
+ - Verilator.
+ - Libero SoC suite.
+ - Microchip Softconsole
+ - ModelSim ME.
+ - Linux.
+ - OpenBeagle CI.
+ 
+Hardware
+========
+
+Ability to program BeagleV-Fire using serial port and set up JTAG for effective debugging. 
+
+Timeline
+********
+
+Timeline summary
+=================
+
+.. table:: 
+
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | Date                   | Activity                                                                                           |                                  
+    +========================+====================================================================================================+
+    | April                  | Understand detailed use cases of existing cores and shortlist them based on requirements           |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | May 1                  | Start bonding - Discussing implementation methods with Mentors                                     |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | May 15                 | College Examinations                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | June 1                 | Start coding and introductory video                                                                |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | June 3                 | :ref:`RVFMilestone1`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | June 10                | :ref:`RVFMilestone2`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | June 17                | :ref:`RVFMilestone3`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | June 24                | :ref:`RVFMilestone4`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | July 1                 | :ref:`RVFMilestone5`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | July 8                 | Submit midterm evaluations                                                                         |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | July 15                | :ref:`RVFMilestone6`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | July 22                | :ref:`RVFMilestone7`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | July 29                | :ref:`RVFMilestone8`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | August 5               | :ref:`RVFMilestone9`                                                                               |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | August 12              | :ref:`RVFMilestone10`                                                                              |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+    | August 19              | Submit final project video, submit final work to GSoC site, and complete final mentor evaluation   |
+    +------------------------+----------------------------------------------------------------------------------------------------+
+
+Timeline detailed
+=================
+
+Community Bonding Period (May 1st - May 15th)
+-------------------------------------------------------
+
+ - Get to know mentors and discuss project implementation.
+ - read documentation, and get up to speed to begin working on the projects
+ - shortlisting pre-existing cores based on initial assessment, by reading available documentation. 
+
+Coding begins (May 27th)
+-------------------------------------------------------
+
+.. _RVFMilestone1:
+
+Milestone #1, Introductory YouTube video (June 3rd)
+-----------------------------------------------------
+ - Make an introductory video
+ - Researching through other soft core IPs to understand the I/O interfacing used in the core.
+ - Setting up remote access on BeagleV-Fire and completing the LED-blink tutorial given in the documentation.
+
+.. _RVFMilestone2:
+
+Milestone #2, Modifiying RV core of I/O(June 10th)
+-------------------------------------------------------
+ - Modification of the PicoRV core to interface GPIOs and memory.
+ - Removing unnecessary extensions to reduce size and complexity, without changing its efficiency.
+
+.. _RVFMilestone3:
+
+Milestone #3, Modifying RV core for single-cycle execution(June 17th)
+-------------------------------------------------------------------------
+ - Modification of the PicoRV core for single-cycle execution of all instructions.
+ - This is to make sure the PRU functions as required after modifications.  
+
+.. _RVFMilestone4:
+
+Milestone #4, BeagleV-Fire setup (June 24th)
+-------------------------------------------------------
+ - Integration of PRU core with BeagleV-Fire gateware to ensure PRU deployment through gateware.
+ - Temporary setup the program memory on FPGA logic for testing and verification of the core.
+
+.. _RVFMilestone5:
+
+Milestone #5, Verification of the core (July 1st)
+-------------------------------------------------------
+ - Verification of all modifications to ensure correct instruction execution. This will be done using predefined verification methods.
+ - Ensuring stable PRU workflow.
+
+Submit midterm evaluations (July 8th)
+-------------------------------------------------------
+ - Complete pending Stage 1 tasks, if any.
+
+.. important:: 
+    
+    **July 12 - 18:00 UTC:** Midterm evaluation deadline (standard coding period) 
+
+.. _RVFMilestone6:
+
+Milestone #6, Establishing communication (July 15th)
+-------------------------------------------------------
+ - Setup the program memory of the PRU within SPI flash as FPGA.
+ - Setting AXI bus access for data transfer.
+
+.. _RVFMilestone7:
+
+Milestone #7, Establishing communication (July 22nd)
+-------------------------------------------------------
+ - Using Shared memory for data transfer and comparing the results with using AXI bus and selecting faster and reliable option.
+
+.. _RVFMilestone8:
+
+Milestone #8, Setup Access (July 29th)
+-------------------------------------------------------
+ - Setting up a easy build script to compile the C program and send it to PRU's Program Memory.
+ - Necessary changes to TCL scripts and Device Tree. 
+
+.. _RVFMilestone9:
+
+Milestone #9, Testing and Verification(Aug 5th)
+-------------------------------------------------------
+ - Setting up gitlab CI/CD to include necessary files in the archives.
+ - Testing smooth and easy workflow from C program to execution in PRU.
+ - Testing the GPIO bandwidth and CPU resources with and without the use of PRU. 
+
+.. _RVFMilestone10:
+
+Milestone #10, Documentation and Tutorial(Aug 12th)
+-------------------------------------------------------
+ - Documenting the project and ways to access PRU on docs.beagleboard.org.
+ - Having an LED Blink tutorial for users to familiarize themselves with the PRU.
+
+Final YouTube video (Aug 19th)
+-------------------------------------------------------
+
+Submit final project video, submit final work to GSoC site, and complete final mentor evaluation
+
+Final Submission (Aug 24th)
+-------------------------------------------------------
+
+.. important::
+
+    **August 19 - 26 - 18:00 UTC:** Final week: GSoC contributors submit their final work 
+    product and their final mentor evaluation (standard coding period)
+
+    **August 26 - September 2 - 18:00 UTC:** Mentors submit final GSoC contributor 
+    evaluations (standard coding period)
+
+Initial results (September 3)
+-------------------------------------------------------
+
+.. important:: 
+    **September 3 - November 4:** GSoC contributors with extended timelines continue coding
+
+    **November 4 - 18:00 UTC:** Final date for all GSoC contributors to submit their final work product and final evaluation
+
+    **November 11 - 18:00 UTC:** Final date for mentors to submit evaluations for GSoC contributor projects with an extended deadline
+
+Experience
+***********
+
+This project will require prior knowledge of Risc-V ISA, FPGA programming, Assembly, and Verilog.
+
+| I have previously worked on a project `Risc-V 32IM core <https://github.com/NachtSpyder04/RISC-V-Eklavya-23>`_ where I contributed towards the synthesis of a Risc-V core using Vivado Design suite and flashed it on UPduino FPGA using Yosys framework. This CPU was successfully able to run operations like the Fibonacci series and factorial of a number.
+| I was a Team Leader of the Semi-finalist Team in `E-Yantra Robotics Competition (eYRC) <https://portal.e-yantra.org/>`_, IIT Bombay on Theme "AstroTinker Bot", where we had to develop a single cycle Risc-V 32I core that was capable of implementing Dijktra Algorithm written in C code and cross-compiled to Risc-V binary instructions. This Competition exposed me to various debugging methods using JTAG connection through Quartus Prime Lite software. DE0-NANO development board with Cyclone IV FPGA was used to control the bot. The bot used PID-based Line Following and Electromagnet to pick and place blocks through an arena representing a Space Station. Verilog HDL codes for the project can be found on `E-yantra_Astrotinker-bot github repo. <https://github.com/RapidRoger18/E-yantra_Astrotinker-bot>`_
+| I have prior experience with ESP32 microcontrollers for small projects.
+
+Approach
+*********
+| As a starting point, I have forked the BeagleV-Fire gateware Repository and completed the `Blinky Tutorial <https://openbeagle.org/Roger18/gateware/-/tree/main/sources/FPGA-design/script_support/components/CAPE/BLINKY_TRY>`_ as specified on `BeagleBoard Docs <https://docs.beagleboard.org/latest/boards/beaglev/fire/demos-and-tutorials/gateware/customize-cape-gateware-verilog.html>`_ 
+| Continuing on this I have set up Libero SoC suite and Softconsole on my Local machine that will provide an easy debugging method using JTAG. I have tested this setup by implementing a simple UART receiver and simulating it in ModelSim ME using a simple testbench.
+
+| The concept of having a microprocessor and a microcontroller on a single SoC is amazing. I can see a variety of applications where a SoC like BeagleV-Fire would be ideal. This inspires me to take on this project and give my contribution to the open-source community. I have my full commitment to this project and am willing to put in complete efforts to complete the project within the allocated time.
+| I would also like to keep improving with the project after GSoC.
+
+Contingency
+===========
+
+If I get stuck on my project and my mentor isn’t around, I will use the following resources:-
+ - `BeagleV-Fire <https://docs.beagleboard.io/latest/boards/beaglev/fire/index.html>`_
+ - `PRU-Documentation <https://inst.eecs.berkeley.edu/~ee192/sp20/files/am335x-pru.pdf>`_
+ - `Picorv32 Docs <https://github.com/YosysHQ/picorv32/blob/master/README.md>`_ 
+ - `PRU cookbook <https://docs.beagleboard.org/books/pru-cookbook/index.html>`_
+ - `TI PRU documentation <https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/09_00_00_03/exports/docs/linux/Foundational_Components_PRU_Subsystem.html>`_
+ 
+Moreover, the BeagleBoard community is very helpful in resolving doubts, I will use OpenBeagle forums to clarify any doubts left after referring to the above resources.
+
+Benefit
+========
+This project will not only improve the use cases of BeagleV-Fire but also provide a very fast real-time subsystem that can be used as a microcontroller. It will provide the following functionalities: -
+ - Reduce memory and I/O resource consumption on the main CPU by performing basic computations in PRU itself thus providing more resources to perform complex tasks.
+ - Provide a real-time interface for fast, deterministic operations.
+ - Reprogammability of FPGA will allow to deployment of PRU only when necessary, thus providing additional logical elements when PRU is not being used.
+ - The configurable nature of FPGA will allow multiple levels of customizations and configurations on PRU, enabling the user to efficiently meet their requirements in the lowest possible resources.   
+
+The success of this project will result in an all-in-one SoC meeting all the requirements of `BeagleBoard.org <https://www.beagleboard.org/>`_ community.
+
+Misc
+====
+
+PR request for cross-compilation task `#182 <https://github.com/jadonk/gsoc-application/pull/182>`_ 

proposals/2025/index.rst

+.. _gsoc-2025-projects:
+
+:far:`calendar-days` 2025
+##########################
+
+Start writing your proposal for GSoC 2025 today and add it here!
+
+.. toctree::
+    :maxdepth: 1

proposals/index.rst

-.. _proposals:
+.. _gsoc-proposals:
 
 Proposals
 #########
@@ -7,9 +7,20 @@ Proposals
 
     Checkout :ref:`gsoc-project-ideas` page to explore ideas and :ref:`gsoc-proposal-guide` page to write your own proposal.
 
+.. toctree:: 
+    :maxdepth: 1
+    :caption: Current proposals
+
+    2025/index
 
 .. toctree:: 
-    :hidden:
+    :maxdepth: 1
+    :caption: Proposal template
+
+    template
+
+.. toctree::
+    :maxdepth: 1
+    :caption: Past Proposals
 
-    commercial_detection_and_replacement.rst
-    template
+    2024/index
\ No newline at end of file
\ No newline at end of file

proposals/template.rst

 .. _gsoc-proposal-template:
 
-Proposal template 
-#################
+Proposal template - Author
+##########################
 
 Introduction
 *************
@@ -85,91 +85,119 @@ Timeline summary
     +------------------------+----------------------------------------------------------------------------------------------------+
     | March 21               | Submit application                                                                                 |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | May 1                  | Start bonding                                                                                      |
+    | May 1                  | :ref:`gsoc-template-bonding`                                                                       |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | May 27                 | Start coding and introductory video                                                                |
+    | May 27                 | :ref:`gsoc-template-coding`                                                                        |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | June 3                 | Release introductory video and complete milestone #1                                               |
+    | June 3                 | :ref:`gsoc-template-m1`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | June 10                | Complete milestone #2                                                                              |
+    | June 10                | :ref:`gsoc-template-m2`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | June 17                | Complete milestone #3                                                                              |
+    | June 17                | :ref:`gsoc-template-m3`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | June 24                | Complete milestone #4                                                                              |
+    | June 24                | :ref:`gsoc-template-m4`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | July 1                 | Complete milestone #5                                                                              |
+    | July 1                 | :ref:`gsoc-template-m5`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | July 8                 | Submit midterm evaluations                                                                         |
+    | July 8                 | :ref:`gsoc-template-midterm`                                                                       |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | July 15                | Complete milestone #6                                                                              |
+    | July 15                | :ref:`gsoc-template-m6`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | July 22                | Complete milestone #7                                                                              |
+    | July 22                | :ref:`gsoc-template-m7`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | July 29                | Complete milestone #8                                                                              |
+    | July 29                | :ref:`gsoc-template-m8`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | August 5               | Complete milestone #9                                                                              |
+    | August 5               | :ref:`gsoc-template-m9`                                                                            |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | August 12              | Complete milestone #10                                                                             |
+    | August 12              | :ref:`gsoc-template-m10`                                                                           |
     +------------------------+----------------------------------------------------------------------------------------------------+
-    | August 19              | Submit final project video, submit final work to GSoC site and complete final mentor evaluation    |
+    | August 19              | :ref:`gsoc-template-final`                                                                         |
     +------------------------+----------------------------------------------------------------------------------------------------+
 
 Timeline detailed
 =================
 
+.. _gsoc-template-bonding:
+
 Community Bonding Period (May 1st - May 26th)
-==============================================
+----------------------------------------------------------
 
 GSoC contributors get to know mentors, read documentation, get up to speed to begin working on their projects
 
+.. _gsoc-template-coding:
+
 Coding begins (May 27th)
-=========================
+----------------------------------------------------------
+
+.. _gsoc-template-m1:
 
 Milestone #1, Introductory YouTube video (June 3rd)
-===================================================
+----------------------------------------------------------
+
+.. _gsoc-template-m2:
 
 Milestone #2 (June 10th)
-==========================
+----------------------------------------------------------
+
+.. _gsoc-template-m3:
 
 Milestone #3 (June 17th)
-=========================
+----------------------------------------------------------
+
+.. _gsoc-template-m4:
 
 Milestone #4 (June 24th)
-==========================
+----------------------------------------------------------
+
+.. _gsoc-template-m5:
 
 Milestone #5 (July 1st)
-========================
+----------------------------------------------------------
+
+.. _gsoc-template-midterm:
 
 Submit midterm evaluations (July 8th)
-=====================================
+----------------------------------------------------------
 
 .. important:: 
     
     **July 12 - 18:00 UTC:** Midterm evaluation deadline (standard coding period) 
 
+.. _gsoc-template-m6:
+
 Milestone #6 (July 15th)
-=========================
+----------------------------------------------------------
+
+.. _gsoc-template-m7:
 
 Milestone #7 (July 22nd)
-=========================
+----------------------------------------------------------
+
+.. _gsoc-template-m8:
 
 Milestone #8 (July 29th)
-=========================
+----------------------------------------------------------
+
+.. _gsoc-template-m9:
 
 Milestone #9 (Aug 5th)
-=======================
+----------------------------------------------------------
+
+.. _gsoc-template-m10:
 
 Milestone #10 (Aug 12th)
-========================
+----------------------------------------------------------
+
+.. _gsoc-template-final:
 
-Final YouTube video (Aug 19th)
-===============================
+Final YouTube video and work upload to GSoC site (Aug 19th)
+-----------------------------------------------------------
 
 Submit final project video, submit final work to GSoC site 
 and complete final mentor evaluation
 
 Final Submission (Aug 24nd)
-============================
+-----------------------------
 
 .. important::
 
@@ -180,7 +208,7 @@ Final Submission (Aug 24nd)
     evaluations (standard coding period)
 
 Initial results (September 3)
-=============================
+-----------------------------
 
 .. important:: 
     **September 3 - November 4:** GSoC contributors with extended timelines continue coding
@@ -189,7 +217,7 @@ Initial results (September 3)
 
     **November 11 - 18:00 UTC:** Final date for mentors to submit evaluations for GSoC contributor projects with extended deadline
 
-Experience and approch
+Experience and approach
 ***********************
 
 In 5-15 sentences, convince us you will be able to successfully complete your project in the timeline you have described.

requirements.txt

@@ -24,6 +24,7 @@ sphinx_design==0.5.0
 sphinxcontrib-applehelp==1.0.8
 sphinxcontrib-devhelp==1.0.6
 sphinxcontrib-htmlhelp==2.0.5
+sphinxcontrib-images==0.9.4
 sphinxcontrib-jsmath==1.0.1
 sphinxcontrib-qthelp==1.0.7
 sphinxcontrib-serializinghtml==1.1.10
@@ -32,3 +33,5 @@ tornado==6.4
 typing_extensions==4.9.0
 urllib3==2.2.0
 sphinx-copybutton==0.5.2
+setuptools==75.8.0
+sphinx-serve==1.0.1
\ No newline at end of file