From bd073bac01a8ff6639085b6d1950d13aa57fac21 Mon Sep 17 00:00:00 2001 From: NachtSpyder04 <sskarole.1504@gmail.com> Date: Thu, 21 Mar 2024 10:32:31 +0530 Subject: [PATCH] Updated information about Verilator and Microchip --- proposals/drone_cape_for_beagle-v-fire.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/proposals/drone_cape_for_beagle-v-fire.rst b/proposals/drone_cape_for_beagle-v-fire.rst index e658d4d..9a29bca 100644 --- a/proposals/drone_cape_for_beagle-v-fire.rst +++ b/proposals/drone_cape_for_beagle-v-fire.rst @@ -53,9 +53,9 @@ This will be acheived by following technologies:- - Verilog - Verilog HDL, as the name suggest, is an Hardware Description Language that is used to describe digital systems and circuits in the form of code. It is widely used for design and verification of application-specific Integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) and supports a range of level of abstraction, from structural to behavioral, and is used for both simulation-based design and synthesis based design -- Verilator (For Verification)- Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle. Verilator can also be used with MATLAB as C++ library could be compiled into a MEX file using MATLAB interface to C++. This is how Verilog designs can be directly simulated from MATLAB. Using compiled C++ models with MATLAB is faster than using co-simulation interfaces with a separate HDL simulator. There is an open-source project called vmodel that compiles Verilog into a MEX file using Verilator and provides a set of functions for model simulation from MATLAB. We can test multiple test cases for specified HDL file which will verify the given file +- Verilator (For Verification)- Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle. We can test multiple test cases for specified HDL file which will verify the given file -- Microchip FPGA tools- The SoftConsole and Libero tools from Microchip are required by the bitstream builder. Instances of Libero are on git.beagleboard.org’s gitlab-runners so we do not need to install the tools on our local machine. +- Microchip FPGA tools- The SoftConsole and Libero tools from Microchip are required by the bitstream builder. Instances of Libero are on git.beagleboard.org’s gitlab-runners. - C++ / Python - C++ or Python will be used to generate scripts of converting images into matrix for image processing and generatng test cases for verification of RTL design -- GitLab