diff --git a/proposals/drone_cape_for_beagle-v-fire.rst b/proposals/drone_cape_for_beagle-v-fire.rst index 8c25cc47df773f3a03088fe401046caab977937a..6785b239cdc898713da712e61d91b0c3937a9226 100644 --- a/proposals/drone_cape_for_beagle-v-fire.rst +++ b/proposals/drone_cape_for_beagle-v-fire.rst @@ -1,19 +1,18 @@ .. _gsoc-proposal-template: -Proposal template +Drone Cape for BeagleV-Fire ################# Introduction ************* +PolarFire SoC platform will allow to create a powerful Drone cape with multiple motors control (octocopter) in FPGA fabric, avionics / flight control on one of Risc-V cores and image processing/ML on FPGA fabric Summary links ============= -- **Contributor:** `Ayush Singh <https://forum.beagleboard.org/u/ayush1325>`_ -- **Mentors:** `Jason Kridner <https://forum.beagleboard.org/u/jkridner>`_, `Vaishnav Acath <https://forum.beagleboard.org/u/vaishnav>`_ -- **Code:** `Google Summer of Code / greybus / cc1352-firmware · GitLab <https://openbeagle.org/gsoc/greybus/cc1352-firmware>`_ -- **Documentation:** `Ayush Singh / docs.beagleboard.io · GitLab <https://openbeagle.org/ayush1325/docs.beagleboard.io>`_ -- **GSoC:** `Google Summer of Code <https://summerofcode.withgoogle.com/archive/2023/projects/iTfGBkDk>`_ +- **Contributor:** `Saish Karole <https://forum.beagleboard.org/u/saish_karole>`_ +- **Mentors:** `Jason Kridner <https://forum.beagleboard.org/u/jkridner>`_ +- **GSoC:** `Proposal Request`_ Status ======= @@ -23,42 +22,58 @@ This project is currently just a proposal. Proposal ======== -Please complete the requirements listed on :ref:`gsoc-contributor-guide` -and fill out this template. +-Completed all the requirements listed on the ideas page. +- The PR request for cross-compilation `task <https://github.com/jadonk/gsoc-application/pull/181>`_ About ===== -- **Forum:** :fab:`discourse` `u/ayush1325 (Ayush Singh) <https://forum.beagleboard.org/u/ayush1325>`_ -- **OpenBeagle:** :fab:`gitlab` `ayush1325 (Ayush Singh) <https://openbeagle.org/ayush1325>`_ -- **IRC:** :fas:`comments` `jkridner (Jason Kridner) <https://web.libera.chat/gamja/#beagle>`_ -- **Github:** :fab:`github` `jadonk (Jason Kridner) <https://github.com/jadonk>`_ -- **School:** :fas:`school` Greatest University -- **Country:** :fas:`flag` Worldistan -- **Primary language:** :fas:`language` Igpay Atinlay -- **Typical work hours:** :fas:`clock` 8AM-5PM US Eastern -- **Previous GSoC participation:** :fab:`google` N/A +- **Forum:** :fab:`discourse` `u/saish_karole (Saish Karole) <https://forum.beagleboard.org/u/saish_karole>`_ +- **OpenBeagle:** :fab:`gitlab` `NachtSpyder04 (Saish Karole) <https://openbeagle.org/NachtSpyder04>`_ +- **Github:** :fab:`github` `NachtSpyder04 (Saish Karole) <https://github.com/NachtSpyder04>`_ +- **School:** :fas:`school` `Veermata Jijabai Technological Institute (VJTI), Mumbai <https://vjti.ac.in/>`_ +- **Country:** :fas:`flag` India +- **Primary language:** :fas:`language` English, Hindi, Marathi +- **Typical work hours:** :fas:`clock` 10AM-7PM Indian Standard Time +- **Previous GSoC participation:** :fab:`google` This is my first time participating in GSoC. Project ******** -**Project name:** About my super cool project. +**Project name:** Drone Cape for BeagleV-Fire Description ============ -In 10-20 sentences, what are you making, for whom, why and with what technologies -(programming languages, etc.)? (We are looking for open source SOFTWARE submissions. By the way, Verilog for programming an FPGA is considered software by us.) +Drones, an aerial vehicle that receives remote commands from a pilot or relies on software on autonomous flight. This unmanned vehicle, although sounds easy to build, but in reality is a difficult bird to soar. A Drone Cape designed for BeagleV-Fire, by using its PolarFire SOC platform and on-board FPGA fabric to generate a stable PWM for multiple motors across the Drone to help it acheive a stable flight and can land and take off easily. Image Detection algorithms or ML models can be used to process Images on FPGA fabric for obstracle detection during mid-air flight. + +This will be acheived by following technologies:- + +-Verilog - Verilog HDL, as the name suggest, is an Hardware Description Language that is used to describe digital systems and circuits in the form of code. It is widely used for design and verification of application-specific Integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) and supports a range of level of abstraction, from structural to behavioral, and is used for both simulation-based design and synthesis based design + +-Verilator (For Verification)- Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC. The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle. Verilator can also be used with MATLAB as C++ library could be compiled into a MEX file using MATLAB interface to C++. This is how Verilog designs can be directly simulated from MATLAB. Using compiled C++ models with MATLAB is faster than using co-simulation interfaces with a separate HDL simulator. There is an open-source project called vmodel that compiles Verilog into a MEX file using Verilator and provides a set of functions for model simulation from MATLAB. We can test multiple test cases for specified HDL file which will verify the given file + +-Microchip FPGA tools- The SoftConsole and Libero tools from Microchip are required by the bitstream builder. Instances of Libero are on git.beagleboard.org’s gitlab-runners so we do not need to install the tools on our local machine. + +-C++ / Python - C++ or Python will be used to generate scripts of converting images into matrix for image processing and generatng test cases for verification of RTL design Software ========= -Which software or technology stack are you going to use to complete this project. +-Verilog +-Verilator +-Microchip FPGA tools +- C++/Python +-Linux +-OpenBeagle CI Hardware ======== -A list of hardware that you are going to use for this project. +- BeagleV-Fire +- MPU9250 IMU board +- MS5611 barometer board +- HC-SR04 Ultrasonic sensor Timeline ********