diff --git a/proposals/drone_cape_for_beagle-v-fire.rst b/proposals/drone_cape_for_beagle-v-fire.rst
index 381069c8f9e6a4f50624079a7b67ee2673a7796b..e658d4d5a09fa2595ce8927eeed3c5c65e7bd1c5 100644
--- a/proposals/drone_cape_for_beagle-v-fire.rst
+++ b/proposals/drone_cape_for_beagle-v-fire.rst
@@ -163,7 +163,7 @@ Milestone #2 (June 10th)
 Milestone #3 (June 17th)
 =========================
 
-- Completing RTL designs and start Verification of individual designs following documentation given on `Verilator. <https://veripool.org/verilator/documentation/>`_
+- Completing RTL designs and start Verification of individual designs following documentation given on `Verilator <https://veripool.org/verilator/documentation>`_
 
 Milestone #4 (June 24th)
 ==========================
@@ -243,7 +243,7 @@ Experience and approch
 
 This project requires knowledge about Verilog, FPGA programming and Verification
 
-- I have previously worked on a `RISC-V CPU project <https://github.com/NachtSpyder04/RISC-V-Eklavya-23>`_, and have a good idea about Verilog syntax and RTL designing.
+- I have previously worked on a `RISC-V-CPU project <https://github.com/NachtSpyder04/RISC-V-Eklavya-23>`_ , and have a good idea about Verilog syntax and RTL designing.
 - I have also participated in E-yantra robotics competition in which a RISC-V-CPU was implemented that will traverse the maze on the shortest path between two points. Hence, I have a good idea how to generate PWM and drive motors using Verilog and how to get sensor values through GPIOs of the board which will be converted to an ADC for further utilization.
 - I am passionate Open Source enthusiast and I will do the work wholeheartedly. I have my commitment to GSoC and I would do everything in my power to finish the project idea within the allotted time.
 - I will keep contributing to the project after GSoC and will be interacting with the community often.