diff --git a/proposals/assets_drone_cape/workflow_image.png b/proposals/assets_drone_cape/workflow_image.png deleted file mode 100644 index 79e0a32d26a8716a04cf75945e9520f61a31bb73..0000000000000000000000000000000000000000 Binary files a/proposals/assets_drone_cape/workflow_image.png and /dev/null differ diff --git a/proposals/assets_drone_cape/workflow_image_processing.png b/proposals/assets_drone_cape/workflow_image_processing.png new file mode 100644 index 0000000000000000000000000000000000000000..ee54dcae73bd1150f35b5a3908948c802792ff43 Binary files /dev/null and b/proposals/assets_drone_cape/workflow_image_processing.png differ diff --git a/proposals/drone_cape_for_beagle-v-fire.rst b/proposals/drone_cape_for_beagle-v-fire.rst index 1930802a94825770a175feea36a26a6ce6ff4845..c114ef26f10e0aa7ea5611f3085a4d16f6377b58 100644 --- a/proposals/drone_cape_for_beagle-v-fire.rst +++ b/proposals/drone_cape_for_beagle-v-fire.rst @@ -73,7 +73,7 @@ This will be acheived by following technologies:- - This will done by converting the given image in greyscale and pixels of greyscaled image into which will be sent to FPGA fabric according to interrupts sent by FPGA to the host CPU. This acquistion of acquring image from Host CPU's memory to the CPU will be performed by C++ script. - The image will be convoluted with 3x3 predefined kernel in the RTL design file and the resultant pixels values will be send back to on-board RISC-V CPU and will be displayed by the CPU. -.. image:: assets_drone_cape/workflow_image.png +.. image:: assets_drone_cape/workflow_image_processing.png :alt: workflow_image_processing Software