From 3e9eeb1c50ef236fea86eff4215d1530bdc5f0c3 Mon Sep 17 00:00:00 2001
From: Deepak Khatri <lorforlinux@beagleboard.org>
Date: Mon, 8 Jan 2024 19:07:50 +0530
Subject: [PATCH] Restructure BBAI chapters
---
.../ai/{ch03.rst => 01-introduction.rst} | 45 +-
boards/beaglebone/ai/02-quick-start.rst | 4 +
...6.rst => 03-design-and-specifications.rst} | 16 +-
.../ai/{ch07.rst => 04-expansion.rst} | 571 +++++++++++++++++-
.../beaglebone/ai/05-demos-and-tutorials.rst | 4 +
.../ai/{ch11.rst => 06-support.rst} | 6 +-
boards/beaglebone/ai/ch01.rst | 20 -
boards/beaglebone/ai/ch04.rst | 65 --
boards/beaglebone/ai/ch05.rst | 310 ----------
boards/beaglebone/ai/ch08.rst | 189 ------
boards/beaglebone/ai/index.rst | 137 ++++-
.../BB_AI_3pin_cable_500px.jpg | Bin
.../BB_AI_3pincableattach_500px.jpg | Bin
.../BB_AI_3pinconnector_cable_500px.jpg | Bin
.../BB_AI_AM5729_blockdiagram.jpg | Bin
.../{images => media}/BB_AI_Antenna_500px.jpg | Bin
.../BB_AI_Antenna_placement_500px.jpg | Bin
.../ai/{images => media}/BB_AI_Back.jpg | Bin
.../BB_AI_BeautyAngle_800px.jpg | Bin
.../BB_AI_Blockdiagram_1000px.jpg | Bin
.../BB_AI_CoaxConn__250px.png | Bin
.../BB_AI_Connectorplacement_800px.png | Bin
.../BB_AI_Connectorplacement_back_800px.png | Bin
.../ai/{images => media}/BB_AI_EVEmodule.jpg | Bin
.../ai/{images => media}/BB_AI_Front.jpg | Bin
.../BB_AI_Headerplacement_800px.png | Bin
.../BB_AI_Heatsinkon_750px.jpg | Bin
.../BB_AI_ICPlacement_800px.png | Bin
.../BB_AI_PMIC_schematicpg3_900px.png | Bin
.../BB_AI_PRU_block_diagram.jpg | Bin
.../{images => media}/BB_AI_PlugIn_500px.jpg | Bin
.../BB_AI_Standalone_setup_1000px.jpg | Bin
.../BB_AI_Standalone_setup_750px.jpg | Bin
.../BB_AI_USBC_and_3pin_500px.png | Bin
.../BB_AI_USERLEDS_800px.png | Bin
.../BB_AI_Userinterface_500px.png | Bin
.../BB_AI_Userinterface_800px.png | Bin
.../BB_AI_antenna_heat_sink_place_500px.jpg | Bin
.../BB_AI_asadrive_500px.jpg | Bin
.../{images => media}/BB_AI_beautyangle.jpg | Bin
.../BB_AI_connectedscreen_500px.jpg | Bin
.../BB_AI_connectingUSBC_500px.jpg | Bin
.../BB_AI_handheld_500px.jpg | Bin
.../BB_AI_outofbox_box_500px.jpg | Bin
.../BB_AI_overview_image.jpg | Bin
.../BB_AI_starthtm_500px.png | Bin
.../{images => media}/OSHW_mark_US000169.png | Bin
.../{images => media}/OSHW_mark_US000169.svg | 0
.../{images => media}/OSHW_mark_US000169.webp | Bin
.../ai/{images => media}/cc-by-sa-88x31.png | Bin
.../chapter-thumbnails}/01-introduction.jpg | Bin
.../chapter-thumbnails}/02-quick-start.jpg | Bin
.../03-design-and-specifications.jpg | Bin
.../chapter-thumbnails/04-expansion.jpg} | Bin
.../05-demos-and-tutorials.jpg | Bin
.../chapter-thumbnails/06-support.jpg} | Bin
.../getting-started-image.png | Bin
.../ai/{images => media}/reva1-bottom.pdf | Bin
.../ai/{images => media}/reva1-bottom.svg | 0
.../ai/{images => media}/reva1-top.pdf | Bin
.../ai/{images => media}/reva1-top.svg | 0
.../ai/{images => media}/vscode.png | Bin
index.rst | 2 +-
63 files changed, 738 insertions(+), 631 deletions(-)
rename boards/beaglebone/ai/{ch03.rst => 01-introduction.rst} (82%)
create mode 100644 boards/beaglebone/ai/02-quick-start.rst
rename boards/beaglebone/ai/{ch06.rst => 03-design-and-specifications.rst} (99%)
rename boards/beaglebone/ai/{ch07.rst => 04-expansion.rst} (86%)
create mode 100644 boards/beaglebone/ai/05-demos-and-tutorials.rst
rename boards/beaglebone/ai/{ch11.rst => 06-support.rst} (97%)
delete mode 100644 boards/beaglebone/ai/ch01.rst
delete mode 100644 boards/beaglebone/ai/ch04.rst
delete mode 100644 boards/beaglebone/ai/ch05.rst
delete mode 100644 boards/beaglebone/ai/ch08.rst
rename boards/beaglebone/ai/{images => media}/BB_AI_3pin_cable_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_3pincableattach_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_3pinconnector_cable_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_AM5729_blockdiagram.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Antenna_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Antenna_placement_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Back.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_BeautyAngle_800px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Blockdiagram_1000px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_CoaxConn__250px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Connectorplacement_800px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Connectorplacement_back_800px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_EVEmodule.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Front.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Headerplacement_800px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Heatsinkon_750px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_ICPlacement_800px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_PMIC_schematicpg3_900px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_PRU_block_diagram.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_PlugIn_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Standalone_setup_1000px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Standalone_setup_750px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_USBC_and_3pin_500px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_USERLEDS_800px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Userinterface_500px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_Userinterface_800px.png (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_antenna_heat_sink_place_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_asadrive_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_beautyangle.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_connectedscreen_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_connectingUSBC_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_handheld_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_outofbox_box_500px.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_overview_image.jpg (100%)
rename boards/beaglebone/ai/{images => media}/BB_AI_starthtm_500px.png (100%)
rename boards/beaglebone/ai/{images => media}/OSHW_mark_US000169.png (100%)
rename boards/beaglebone/ai/{images => media}/OSHW_mark_US000169.svg (100%)
rename boards/beaglebone/ai/{images => media}/OSHW_mark_US000169.webp (100%)
rename boards/beaglebone/ai/{images => media}/cc-by-sa-88x31.png (100%)
rename boards/beaglebone/ai/{images/demos-and-tutorials => media/chapter-thumbnails}/01-introduction.jpg (100%)
rename boards/beaglebone/ai/{images/demos-and-tutorials => media/chapter-thumbnails}/02-quick-start.jpg (100%)
rename boards/beaglebone/ai/{images/demos-and-tutorials => media/chapter-thumbnails}/03-design-and-specifications.jpg (100%)
rename boards/beaglebone/ai/{images/demos-and-tutorials/04-connectors-and-pinouts.jpg => media/chapter-thumbnails/04-expansion.jpg} (100%)
rename boards/beaglebone/ai/{images/demos-and-tutorials => media/chapter-thumbnails}/05-demos-and-tutorials.jpg (100%)
rename boards/beaglebone/ai/{images/demos-and-tutorials/06-support-documents.jpg => media/chapter-thumbnails/06-support.jpg} (100%)
rename boards/beaglebone/ai/{images => media}/getting-started-image.png (100%)
rename boards/beaglebone/ai/{images => media}/reva1-bottom.pdf (100%)
rename boards/beaglebone/ai/{images => media}/reva1-bottom.svg (100%)
rename boards/beaglebone/ai/{images => media}/reva1-top.pdf (100%)
rename boards/beaglebone/ai/{images => media}/reva1-top.svg (100%)
rename boards/beaglebone/ai/{images => media}/vscode.png (100%)
diff --git a/boards/beaglebone/ai/ch03.rst b/boards/beaglebone/ai/01-introduction.rst
similarity index 82%
rename from boards/beaglebone/ai/ch03.rst
rename to boards/beaglebone/ai/01-introduction.rst
index ae24689a..1b4d1d4a 100644
--- a/boards/beaglebone/ai/ch03.rst
+++ b/boards/beaglebone/ai/01-introduction.rst
@@ -1,7 +1,22 @@
-.. _beaglebone-ai-connecting:
-
-Connecting Up Your BeagleBone AI
-################################
+.. _bbai-introduction:
+
+Introduction
+#############
+
+Built on the proven BeagleBoard.org® open source Linux approach,
+BeagleBone® AI fills the gap between small SBCs and more powerful
+industrial computers. Based on the Texas Instruments AM5729, developers
+have access to the powerful SoC with the ease of BeagleBone® Black
+header and mechanical compatibility. BeagleBone® AI makes it easy to
+explore how artificial intelligence (AI) can be used in everyday life
+via TI C66x digital-signal-processor (DSP) cores and
+embedded-vision-engine (EVE) cores supported through an optimized TIDL
+machine learning OpenCL API with pre-installed tools. Focused on
+everyday automation in industrial, commercial and home applications.
+
+.. image:: media/BB_AI_BeautyAngle_800px.jpg
+ :align: center
+ :alt: BeagleBone AI Beauty Angle
What’s In the Box
*****************
@@ -16,7 +31,7 @@ distribution. In the box you will find:
TODO: Add links to the design materials for both
-.. image:: images/BB_AI_antenna_heat_sink_place_500px.jpg
+.. image:: media/BB_AI_antenna_heat_sink_place_500px.jpg
:align: center
:alt: BeagleBone AI Overview
@@ -88,19 +103,19 @@ loaded on your BeagleBone® AI.
1. Locate the USB Type-C connector on BeagleBone® AI
-.. image:: images/BB_AI_USBC_and_3pin_500px.png
+.. image:: media/BB_AI_USBC_and_3pin_500px.png
:align: center
:alt: USB connector and serial debug.
2. Connect a USB type-C cable to BeagleBone® AI USB type-C port.
-.. image:: images/BB_AI_connectingUSBC_500px.jpg
+.. image:: media/BB_AI_connectingUSBC_500px.jpg
:align: center
:alt: Connecting serial cable.
3. Connect the other end of the USB cable to the PC USB 3 port.
-.. image:: images/BB_AI_PlugIn_500px.jpg
+.. image:: media/BB_AI_PlugIn_500px.jpg
:align: center
:alt: connecting to PC
@@ -110,23 +125,23 @@ loaded on your BeagleBone® AI.
6. Look for a new mass storage drive to appear on the PC.
-.. image:: images/BB_AI_asadrive_500px.jpg
+.. image:: media/BB_AI_asadrive_500px.jpg
:align: center
:alt: BeagleBone storage drive options
7. Open the drive and open START.HTM with your web browser.
-.. image:: images/BB_AI_starthtm_500px.png
+.. image:: media/BB_AI_starthtm_500px.png
:align: center
:alt: BeagleBone drive
-.. image:: images/BB_AI_connectedscreen_500px.jpg
+.. image:: media/BB_AI_connectedscreen_500px.jpg
:align: center
:alt: Getting started
8. Follow the instructions in the browser window.
-.. image:: images/vscode.png
+.. image:: media/vscode.png
:align: center
:alt: BeagleBone instructions
@@ -136,7 +151,7 @@ loaded on your BeagleBone® AI.
Standalone w/Display and Keyboard/Mouse
****************************************
-.. image:: images/BB_AI_Standalone_setup_750px.jpg
+.. image:: media/BB_AI_Standalone_setup_750px.jpg
:align: center
:alt: BeagleBone AI Overview
@@ -180,7 +195,7 @@ Cables: https://git.beagleboard.org/beagleboard/beaglebone-ai/-/wikis/Frequently
Locate the 3 PIN debug header on BeagleBone® AI, near the USB C connection.
-.. image:: images/BB_AI_USBC_and_3pin_500px.png
+.. image:: media/BB_AI_USBC_and_3pin_500px.png
:align: center
:alt: BeagleBone AI Overview
@@ -190,6 +205,6 @@ Press the small white connector into the 3 PIN debug header. The pinout is:
- Pin 2: UART1_RX (i.e. this is a BB-AI input pin)
- Pin 3: UART1_TX (i.e. BB-AI transmits out on this pin)
-.. image:: images/BB_AI_3pincableattach_500px.jpg
+.. image:: media/BB_AI_3pincableattach_500px.jpg
:align: center
:alt: BeagleBone AI Overview
\ No newline at end of file
diff --git a/boards/beaglebone/ai/02-quick-start.rst b/boards/beaglebone/ai/02-quick-start.rst
new file mode 100644
index 00000000..f44451de
--- /dev/null
+++ b/boards/beaglebone/ai/02-quick-start.rst
@@ -0,0 +1,4 @@
+.. _bbai-quick-start:
+
+Quick start
+###########
\ No newline at end of file
diff --git a/boards/beaglebone/ai/ch06.rst b/boards/beaglebone/ai/03-design-and-specifications.rst
similarity index 99%
rename from boards/beaglebone/ai/ch06.rst
rename to boards/beaglebone/ai/03-design-and-specifications.rst
index ecd6c0b1..3204e7bd 100644
--- a/boards/beaglebone/ai/ch06.rst
+++ b/boards/beaglebone/ai/03-design-and-specifications.rst
@@ -1,6 +1,6 @@
-.. _beaglebone-ai-design:
+.. _bbai-design-and-specifications:
-Detailed Hardware Design
+Design and specifications
#########################
This section provides a detailed description of the Hardware design.
@@ -12,7 +12,7 @@ those who may be concerned, this is the same figure found in section 5.
It is placed here again for convenience so it is closer to the topics to
follow.
-.. image:: images/BB_AI_Blockdiagram_1000px.jpg
+.. image:: media/BB_AI_Blockdiagram_1000px.jpg
:align: center
:alt: beaglebone ai component placement
@@ -61,7 +61,7 @@ resources. Power request signals enable power mode control for power
optimization. The device includes a general-purpose sigma-delta
analog-to-digital converter (GPADC) with three external input channels.
-.. image:: images/BB_AI_PMIC_schematicpg3_900px.png
+.. image:: media/BB_AI_PMIC_schematicpg3_900px.png
:align: center
:alt: beaglebone ai user interface placement
@@ -75,7 +75,7 @@ Below image shows how the USB-C power input is connected to the **TPS6590379**.
Power Button
=============
-.. image:: images/BB_AI_Userinterface_800px.png
+.. image:: media/BB_AI_Userinterface_800px.png
:alt: beaglebone ai user interface placement
.. _eMMC-flash-memory:
@@ -253,7 +253,7 @@ PRU-ICSS Block Diagram
Below is a high level block diagram of one of the PRU-ICSS Subsystems
-.. image:: images/BB_AI_PRU_block_diagram.jpg
+.. image:: media/BB_AI_PRU_block_diagram.jpg
:align: center
:alt: beaglebone ai component placement
@@ -1971,7 +1971,7 @@ User LEDs
There are 5 User Programmable LEDs on BeagleBone® AI. These are
connected to GPIO pins on the processor.
-.. image:: images/BB_AI_USERLEDS_800px.png
+.. image:: media/BB_AI_USERLEDS_800px.png
:align: center
:alt: beaglebone ai connector placement
@@ -1993,4 +1993,4 @@ assigned in the device tree for BeagleBone® AI:
+-----------------------+-----------------------+-----------------------+
| D8 | GPIO3_7 | WiFi/Bluetooth |
| | | Activity |
-+-----------------------+-----------------------+-----------------------+
++-----------------------+-----------------------+-----------------------+
\ No newline at end of file
diff --git a/boards/beaglebone/ai/ch07.rst b/boards/beaglebone/ai/04-expansion.rst
similarity index 86%
rename from boards/beaglebone/ai/ch07.rst
rename to boards/beaglebone/ai/04-expansion.rst
index 14204b1a..a17b153a 100644
--- a/boards/beaglebone/ai/ch07.rst
+++ b/boards/beaglebone/ai/04-expansion.rst
@@ -1,12 +1,386 @@
-.. _beaglebone-ai-connectors:
+.. _bbai-expansion:
+
+Expansion
+#########
+
+.. _beaglebone-ai-overview:
+
+BeagleBone AI Overview
+======================
+
+.. image:: media/BB_AI_overview_image.*
+ :align: center
+ :alt: BeagleBone AI Overview
+
+BeagleBone® AI Features
+************************
+
+Main Processor Features of the AM5729 Within BeagleBone® AI
+============================================================
+
+- Dual 1.5GHz ARM® Cortex®-A15 with out-of-order speculative issue
+ 3-way superscalar execution pipeline for the fastest execution of
+ existing 32-bit code
+- 2 C66x Floating-Point VLIW DSP supported by OpenCL
+- 4 Embedded Vision Engines (EVEs) supported by TIDL machine learning
+ library
+- 2x Dual-Core Programmable Real-Time Unit (PRU) subsystems (4 PRUs
+ total) for ultra low-latency control and software generated
+ peripherals
+- 2x Dual ARM® Cortex®-M4 co-processors for real-time control
+- IVA-HD subsystem with support for 4K @ 15fps H.264 encode/decode and
+ other codecs @ 1080p60
+- Vivante® GC320 2D graphics accelerator
+- Dual-Core PowerVR® SGX544™ 3D GPU
+
+Communications
+===============
+
+- BeagleBone Black header and mechanical compatibility
+- 16-bit LCD interfaces
+- 4+ UARTs
+- 2 I2C ports
+- 2 SPI ports
+- Lots of PRU I/O pins
+
+Memory
+=======
+
+- 1GB DDR3L
+- 16GB on-board eMMC flash
+
+Connectors
+===========
+
+- USB Type-C connector for power and SuperSpeed dual-role controller
+- Gigabit Ethernet
+- 802.11ac 2.4/5GHz WiFi via the AzureWave AW-CM256SM
+
+Out of Box Software
+====================
+
+- Zero-download out of box software environment
+
+Board Component Locations
+**************************
+
+.. image:: media/BB_AI_ICPlacement_800px.png
+ :align: center
+ :alt: beaglebone ai component placement
+
+This section provides the high level specification of BeagleBone® AI
+
+Block Diagram
+**************
+
+The figure below is the high level block diagram of BeagleBone® AI. For
+detailed layout information please check the schematics.
+
+.. image:: media/BB_AI_Blockdiagram_1000px.jpg
+ :align: center
+ :alt: beaglebone ai component placement
+
+AM572x Sitaraâ„¢ Processor
+*************************
+
+The Texas Instruments AM572x Sitaraâ„¢ processor family of SOC devices
+brings high processing performance through the maximum flexibility of a
+fully integrated mixed processor solution. The devices also combine
+programmable video processing with a highly integrated peripheral set
+ideal for AI applications. The AM5729 used on BeagleBone® AI is the
+super-set device of the family.
+
+Programmability is provided by dual-core ARM® Cortex®-A15 RISC CPUs with
+Arm® Neon™ extension, and two TI C66x VLIW floating-point DSP core, and
+Vision AccelerationPac (with 4x EVEs). The Arm allows developers to keep
+control functions separate from other algorithms programmed on the DSPs
+and coprocessors, thus reducing the complexity of the system software.
+
+Texas Instruments AM572x Sitaraâ„¢ Processor Family Block Diagram\*
+
+.. image:: media/BB_AI_AM5729_blockdiagram.jpg
+ :align: center
+ :alt: beaglebone ai component placement
+
+**MPU Subsystem** The Dual Cortex-A15 MPU subsystem integrates the
+following submodules:
+
+- ARM Cortex-A15 MPCore
+
+ - Two central processing units (CPUs)
+
+ - ARM Version 7 ISA: Standard ARM instruction set plus Thumb®-2,
+ Jazelle® RCT Java™ accelerator, hardware virtualization support,
+ and large physical address extensions (LPAE)
+
+ - Neonâ„¢ SIMD coprocessor and VFPv4 per CPU
+
+ - Interrupt controller with up to 160 interrupt requests
+
+ - One general-purpose timer and one watchdog timer per CPU – Debug
+ and trace features
+
+ - 32-KiB instruction and 32-KiB data level 1 (L1) cache per CPU
+
+- Shared 2-MiB level 2 (L2) cache
+
+- 48-KiB bootable ROM
+
+- Local power, reset, and clock management (PRCM) module
+
+- Emulation features
+
+- Digital phase-locked loop (DPLL)
+
+**DSP Subsystems** There are two DSP subsystems in the device. Each DSP
+subsystem contains the following submodules:
+
+- TMS320C66xâ„¢ Floating-Point VLIW DSP core for audio processing, and
+ general-purpose imaging and video processing. It extends the
+ performance of existing C64x+â„¢ and C647xâ„¢ DSPs through enhancements
+ and new features.
+
+ - 32-KiB L1D and 32-KiB L1P cache or addressable SRAM
+
+ - 288-KiB L2 cache
+
+- 256-KiB configurable as cache or SRAM
+
+- 32-KiB SRAM
+
+- Enhanced direct memory access (EDMA) engine for video and audio data
+ transfer
+
+- Memory management units (MMU) for address management.
+
+- Interrupt controller (INTC)
+
+- Emulation capabilities
+
+- Supported by OpenCL
+
+**EVE Subsystems**
+
+- 4 Embedded Vision Engines (EVEs) supported by TIDL machine learning
+ library
+
+.. image:: media/BB_AI_EVEmodule.jpg
+ :align: center
+ :alt: BeagleBone AI component placement
+
+The Embedded Vision Engine (EVE) module is a programmable imaging and
+vision processing engine. Software support for the EVE module is
+available through OpenCL Custom Device model with fixed set of
+functions. More information is available
+http://www.ti.com/lit/wp/spry251/spry251.pdf
+
+**PRU-ICSS Subsystems**
+
+- 2x Dual-Core Programmable Real-Time Unit (PRU) subsystems (4 PRUs
+ total) for ultra low-latency control and software generated
+ peripherals. Access to these powerful subsystems is available through
+ through the P8 and P9 headers. These are detailed in Section 7.
+
+**IPU Subsystems** There are two Dual Cortex-M4 IPU subsystems in the
+device available for general purpose usage, particularly real-time
+control. Each IPU subsystem includes the following components:
+
+- Two Cortex-M4 CPUs
+
+- ARMv7E-M and Thumb-2 instruction set architectures
+
+- Hardware division and single-cycle multiplication acceleration
+
+- Dedicated INTC with up to 63 physical interrupt events with 16-level
+ priority
+
+- Two-level memory subsystem hierarchy
+
+ - L1 (32-KiB shared cache memory)
+
+ - L2 ROM + RAM
+
+- 64-KiB RAM
+
+- 16-KiB bootable ROM
+
+- MMU for address translation
+
+- Integrated power management
+
+- Emulation feature embedded in the Cortex-M4
+
+**IVA-HD Subsystem**
+
+- IVA-HD subsystem with support for 4K @ 15fps H.264 encode/decode and
+ other codecs @ 1080p60 The IVA-HD subsystem is a set of video encoder
+ and decoder hardware accelerators. The list of supported codecs can
+ be found in the software development kit (SDK) documentation.
+
+**BB2D Graphics Accelerator Subsystem** The Vivante® GC320 2D graphics
+accelerator is the 2D BitBlt (BB2D) graphics accelerator subsystem on
+the device with the following features:
+
+- API support:
+
+ - OpenWFâ„¢, DirectFB
+
+ - GDI/DirectDraw
+
+- BB2D architecture:
+
+ - BitBlt and StretchBlt
+
+ - DirectFB hardware acceleration
+
+ - ROP2, ROP3, ROP4 full alpha blending and transparency
+
+ - Clipping rectangle support
+
+ - Alpha blending includes Java 2 Porter-Duff compositing rules
+
+ - 90-, 180-, 270-degree rotation on every primitive
+
+ - YUV-to-RGB color space conversion
+
+ - Programmable display format conversion with 14 source and 7
+ destination formats
+
+ - High-quality, 9-tap, 32-phase filter for image and video scaling
+ at 1080p
+
+ - Monochrome expansion for text rendering
+
+ - 32K × 32K coordinate system
+
+**Dual-Core PowerVR® SGX544™ 3D GPU** The 3D graphics processing unit
+(GPU) subsystem is based on POWERVR® SGX544 subsystem from Imagination
+Technologies. It supports general embedded applications. The GPU can
+process different data types simultaneously, such as: pixel data, vertex
+data, video data, and general-purpose data. The GPU subsystem has the
+following features:
+
+- Multicore GPU architecture: two SGX544 cores.
+
+- Shared system level cache of 128 KiB
+
+- Tile-based deferred rendering architecture
+
+- Second-generation universal scalable shader engines (USSE2),
+ multithreaded engines incorporating pixel and vertex shader
+ functionality
+
+- Present and texture load accelerators
+
+ - Enables to move, rotate, twiddle, and scale texture surfaces.
+
+ - Supports RGB, ARGB, YUV422, and YUV420 surface formats.
+
+ - Supports bilinear upscale.
+
+ - Supports source colorkey.
+
+- Fine-grained task switching, load balancing, and power management
+
+- Programmable high-quality image antialiasing
+
+- Bilinear, trilinear, anisotropic texture filtering
+
+- Advanced geometry DMA driven operation for minimum CPU interaction
+
+- Fully virtualized memory addressing for OS operation in a unified
+ memory architecture (MMU)
+
+Memory
+********
+
+.. _bbai_ddr:
+
+1GB DDR3L
+==========
+
+Dual 256M x 16 DDR3L memory devices are used, one on each side of the
+board, for a total of 1 GB. They will each operate at a clock frequency
+of up to 533 MHz yielding an effective rate of 1066Mb/s on the DDR3L bus
+allowing for 4GB/s of DDR3L memory bandwidth.
+
+16GB Embedded MMC
+===================
+
+A single 16GB embedded MMC (eMMC) device is on the board.
+
+
+microSD Connector
+==================
+
+The board is equipped with a single microSD connector to act as a
+secondary boot source for the board and, if selected as such, can be the
+primary booth source. The connector will support larger capacity microSD
+cards. The microSD card is not provided with the board.
+
+Boot Modes
+*************
+
+.. todo:: Need info on BBAI boot mode settings
+
+Power Management
+******************
+
+.. todo:: Need info on BBAI power management
+
+Connectivity
+******************
+
+.. todo:: Add WiFi/Bluetooth/Ethernet
+
+BeagleBone® AI supports the majority of the functions of the AM5729 SOC
+through connectors or expansion header pin accessibility. See section 7
+for more information on expansion header pinouts. There are a few
+functions that are not accessible which are: (TBD)
+
+.. todo:: This text needs to go somewhere.
+
+.. table:: On-board I2C Devices
+
+ +---------+--------------+-----------------+
+ | Address | Identifier | Description |
+ +=========+==============+=================+
+ | 0x12 | U3 | TPS6590379 PMIC |
+ | | | DVS |
+ +---------+--------------+-----------------+
+ | 0x41 | U78 | STMPE811Q ADC |
+ | | | and GPIO |
+ | | | expander |
+ +---------+--------------+-----------------+
+ | 0x47 | U13 | HD3SS3220 USB |
+ | | | Type-C DRP port |
+ | | | controller |
+ +---------+--------------+-----------------+
+ | 0x50 | U9 | 24LC32 board ID |
+ | | | EEPROM |
+ +---------+--------------+-----------------+
+ | 0x58 | U3 | TPS6590379 PMIC |
+ | | | power registers |
+ +---------+--------------+-----------------+
+ | 0x5a | U3 | TPS6590379 PMIC |
+ | | | interfaces and |
+ | | | auxiliaries |
+ +---------+--------------+-----------------+
+ | 0x5c | U3 | TPS6590379 PMIC |
+ | | | trimming and |
+ | | | test |
+ +---------+--------------+-----------------+
+ | 0x5e | U3 | TPS6590379 PMIC |
+ | | | OTP |
+ +---------+--------------+-----------------+
Connectors
############
-.. image:: images/BB_AI_Connectorplacement_800px.png
+.. image:: media/BB_AI_Connectorplacement_800px.png
:align: center
-.. image:: images/BB_AI_Connectorplacement_back_800px.png
+.. image:: media/BB_AI_Connectorplacement_back_800px.png
:align: center
Expansion Connectors
@@ -27,7 +401,7 @@ are **3.3V** unless otherwise indicated.
**Figure ?** shows the location of the expansion connectors.
-.. image:: images/BB_AI_Headerplacement_800px.png
+.. image:: media/BB_AI_Headerplacement_800px.png
:align: center
:alt: beaglebone ai header placement
@@ -1624,3 +1998,192 @@ microHDMI
***********
.. todo:: Need info on BealgeBone AI uHDMI connection
+
+
+Cape Board Support
+#####################
+
+There is a `Cape Headers Google
+Spreadsheet <https://docs.google.com/spreadsheets/d/1fE-AsDZvJ-bBwzNBj1_sPDrutvEvsmARqFwvbw_HkrE/edit?usp=sharing>`__
+which has a lot of detail regarding various boards and cape add-on
+boards.
+
+See also https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
+
+TODO
+
+BeagleBone® Black Cape Compatibility
+**************************************
+
+TODO
+
+See https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec for
+now.
+
+EEPROM
+************
+
+TODO
+
+Pin Usage Consideration
+************************
+
+TODO
+
+GPIO
+*********
+
+TODO
+
+I2C
+*********
+
+TODO
+
+UART or PRU UART
+*******************
+
+This section is about both UART pins on the header and PRU UART pins on
+the headers we will include a chart and later some code
+
+.. table:: UART
+
+ +-------------+--------+-----------+-------------------+-------+
+ | Function | Pin | ABC Ball | Pinctrl Register | Mode |
+ +=============+========+===========+===================+=======+
+ | uart3_txd | P9.21 | B22 | 0x17C4 | 1 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart3_rxd | P9.22 | A26 | 0x17C0 | 1 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart5_txd | P9.13 | C17 | 0x1730 | 4 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart5_rxd | P9.11 | B19 | 0x172C | 4 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart5_ctsn | P8.05 | AC9 | 0x178C | 2 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart5_rtsn | P8.06 | AC3 | 0x1790 | 2 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart8_txd | P8.37 | A21 | 0x1738 | 3 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart8_rxd | P8.38 | C18 | 0x1734 | 3 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart8_ctsn | P8.31 | G16 | 0x173C | 3 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart8_rtsn | P8.32 | D17 | 0x1740 | 3 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart10_txd | P9.24 | F20 | 0x168C | 3 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart10_rxd | P9.26 | E21 | 0x1688 | 3 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart10_ctsn | P8.03 | AB8 | 0x179C | 2 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart10_rtsn | P8.04 | AB5 | 0x17A0 | 2 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart10_txd | P9.24 | F20 | 0x168C | 3 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart10_rxd | P9.26 | E21 | 0x1688 | 3 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart10_ctsn | P9.20 | D2 | 0x1578 | 8 |
+ +-------------+--------+-----------+-------------------+-------+
+ | uart10_rtsn | P9.19 | F4 | 0x157C | 8 |
+ +-------------+--------+-----------+-------------------+-------+
+
+.. table:: PRU UART
+
+ +------------------+--------+-----------+-------------------+-------+
+ | Function | Pin | ABC Ball | Pinctrl Register | Mode |
+ +==================+========+===========+===================+=======+
+ | pr2_uart0_txd | P8.31 | C8 | 0x1614 | 10 |
+ +------------------+--------+-----------+-------------------+-------+
+ | pr2_uart0_rxd | P8.33 | C6 | 0x1610 | 10 |
+ +------------------+--------+-----------+-------------------+-------+
+ | pr2_uart0_cts_n | P8.34 | D8 | 0x1608 | 10 |
+ +------------------+--------+-----------+-------------------+-------+
+ | pr2_uart0_rts_n | P8.35 | A5 | 0x160C | 10 |
+ +------------------+--------+-----------+-------------------+-------+
+ | pr1_uart0_rxd | P8.43 | F10 | 0x15E4 | 10 |
+ +------------------+--------+-----------+-------------------+-------+
+ | pr1_uart0_txd | P8.44 | G11 | 0x15E8 | 10 |
+ +------------------+--------+-----------+-------------------+-------+
+ | pr1_uart0_cts_n | P8.45 | F11 | 0x15DC | 10 |
+ +------------------+--------+-----------+-------------------+-------+
+ | pr1_uart0_rts_n | P8.46 | G10 | 0x15E0 | 10 |
+ +------------------+--------+-----------+-------------------+-------+
+
+
+TODO
+
+SPI
+****
+
+TODO
+
+Analog
+********
+
+TODO
+
+.. _pwm-timer-ecap-or-pru-pwm-ecap:
+
+PWM, TIMER, eCAP or PRU PWM/eCAP
+**********************************
+
+TODO
+
+eQEP
+******
+
+TODO
+
+CAN
+*****
+
+TODO
+
+.. _mcasp-audio-serial-like-i2c-and-ac97:
+
+McASP (audio serial like I2S and AC97)
+****************************************
+
+TODO
+
+MMC
+*****
+
+TODO
+
+LCD
+*****
+
+TODO
+
+PRU GPIO
+**********
+
+TODO
+
+CLKOUT
+********
+
+TODO
+
+Expansion Connector Headers
+******************************
+
+TODO: discuss header options for working with the expansion connectors per
+https://git.beagleboard.org/beagleboard/beaglebone-black/-/wikis/System-Reference-Manual#section-7-1
+
+Signal Usage
+****************
+
+TODO
+
+Cape Power
+************
+
+TODO
+
+Mechanical
+************
+
+TODO
diff --git a/boards/beaglebone/ai/05-demos-and-tutorials.rst b/boards/beaglebone/ai/05-demos-and-tutorials.rst
new file mode 100644
index 00000000..0790f6d4
--- /dev/null
+++ b/boards/beaglebone/ai/05-demos-and-tutorials.rst
@@ -0,0 +1,4 @@
+.. _bbai-demos-and-tutorials:
+
+Demos & Tutorials
+#################
\ No newline at end of file
diff --git a/boards/beaglebone/ai/ch11.rst b/boards/beaglebone/ai/06-support.rst
similarity index 97%
rename from boards/beaglebone/ai/ch11.rst
rename to boards/beaglebone/ai/06-support.rst
index a509a261..94219b30 100644
--- a/boards/beaglebone/ai/ch11.rst
+++ b/boards/beaglebone/ai/06-support.rst
@@ -1,4 +1,4 @@
-.. _beaglebone-ai-support:
+.. _bbai-support:
Additional Support Information
##############################
@@ -112,8 +112,8 @@ Proposed changes.
Pictures
*********
-.. image:: images/BB_AI_Front.jpg
+.. image:: media/BB_AI_Front.jpg
:align: center
-.. image:: images/BB_AI_Back.jpg
+.. image:: media/BB_AI_Back.jpg
:align: center
diff --git a/boards/beaglebone/ai/ch01.rst b/boards/beaglebone/ai/ch01.rst
deleted file mode 100644
index 37cc36c0..00000000
--- a/boards/beaglebone/ai/ch01.rst
+++ /dev/null
@@ -1,20 +0,0 @@
-.. _beaglebone-ai-intro:
-
-Introduction
-##############
-
-Built on the proven BeagleBoard.org® open source Linux approach,
-BeagleBone® AI fills the gap between small SBCs and more powerful
-industrial computers. Based on the Texas Instruments AM5729, developers
-have access to the powerful SoC with the ease of BeagleBone® Black
-header and mechanical compatibility. BeagleBone® AI makes it easy to
-explore how artificial intelligence (AI) can be used in everyday life
-via TI C66x digital-signal-processor (DSP) cores and
-embedded-vision-engine (EVE) cores supported through an optimized TIDL
-machine learning OpenCL API with pre-installed tools. Focused on
-everyday automation in industrial, commercial and home applications.
-
-.. image:: images/BB_AI_BeautyAngle_800px.jpg
- :align: center
- :alt: BeagleBone AI Beauty Angle
-
diff --git a/boards/beaglebone/ai/ch04.rst b/boards/beaglebone/ai/ch04.rst
deleted file mode 100644
index 2ae65f61..00000000
--- a/boards/beaglebone/ai/ch04.rst
+++ /dev/null
@@ -1,65 +0,0 @@
-.. _beaglebone-ai-overview:
-
-BeagleBone AI Overview
-########################
-
-.. image:: images/BB_AI_overview_image.*
- :align: center
- :alt: BeagleBone AI Overview
-
-BeagleBone® AI Features
-************************
-
-Main Processor Features of the AM5729 Within BeagleBone® AI
-============================================================
-
-- Dual 1.5GHz ARM® Cortex®-A15 with out-of-order speculative issue
- 3-way superscalar execution pipeline for the fastest execution of
- existing 32-bit code
-- 2 C66x Floating-Point VLIW DSP supported by OpenCL
-- 4 Embedded Vision Engines (EVEs) supported by TIDL machine learning
- library
-- 2x Dual-Core Programmable Real-Time Unit (PRU) subsystems (4 PRUs
- total) for ultra low-latency control and software generated
- peripherals
-- 2x Dual ARM® Cortex®-M4 co-processors for real-time control
-- IVA-HD subsystem with support for 4K @ 15fps H.264 encode/decode and
- other codecs @ 1080p60
-- Vivante® GC320 2D graphics accelerator
-- Dual-Core PowerVR® SGX544™ 3D GPU
-
-Communications
-===============
-
-- BeagleBone Black header and mechanical compatibility
-- 16-bit LCD interfaces
-- 4+ UARTs
-- 2 I2C ports
-- 2 SPI ports
-- Lots of PRU I/O pins
-
-Memory
-=======
-
-- 1GB DDR3L
-- 16GB on-board eMMC flash
-
-Connectors
-===========
-
-- USB Type-C connector for power and SuperSpeed dual-role controller
-- Gigabit Ethernet
-- 802.11ac 2.4/5GHz WiFi via the AzureWave AW-CM256SM
-
-Out of Box Software
-====================
-
-- Zero-download out of box software environment
-
-Board Component Locations
-**************************
-
-.. image:: images/BB_AI_ICPlacement_800px.png
- :align: center
- :alt: beaglebone ai component placement
-
diff --git a/boards/beaglebone/ai/ch05.rst b/boards/beaglebone/ai/ch05.rst
deleted file mode 100644
index e1b1e14c..00000000
--- a/boards/beaglebone/ai/ch05.rst
+++ /dev/null
@@ -1,310 +0,0 @@
-.. _beaglebone-ai-specs:
-
-BeagleBone AI High Level Specification
-###########################################
-
-This section provides the high level specification of BeagleBone® AI
-
-Block Diagram
-**************
-
-The figure below is the high level block diagram of BeagleBone® AI. For
-detailed layout information please check the schematics.
-
-.. image:: images/BB_AI_Blockdiagram_1000px.jpg
- :align: center
- :alt: beaglebone ai component placement
-
-AM572x Sitaraâ„¢ Processor
-*************************
-
-The Texas Instruments AM572x Sitaraâ„¢ processor family of SOC devices
-brings high processing performance through the maximum flexibility of a
-fully integrated mixed processor solution. The devices also combine
-programmable video processing with a highly integrated peripheral set
-ideal for AI applications. The AM5729 used on BeagleBone® AI is the
-super-set device of the family.
-
-Programmability is provided by dual-core ARM® Cortex®-A15 RISC CPUs with
-Arm® Neon™ extension, and two TI C66x VLIW floating-point DSP core, and
-Vision AccelerationPac (with 4x EVEs). The Arm allows developers to keep
-control functions separate from other algorithms programmed on the DSPs
-and coprocessors, thus reducing the complexity of the system software.
-
-Texas Instruments AM572x Sitaraâ„¢ Processor Family Block Diagram\*
-
-.. image:: images/BB_AI_AM5729_blockdiagram.jpg
- :align: center
- :alt: beaglebone ai component placement
-
-**MPU Subsystem** The Dual Cortex-A15 MPU subsystem integrates the
-following submodules:
-
-- ARM Cortex-A15 MPCore
-
- - Two central processing units (CPUs)
-
- - ARM Version 7 ISA: Standard ARM instruction set plus Thumb®-2,
- Jazelle® RCT Java™ accelerator, hardware virtualization support,
- and large physical address extensions (LPAE)
-
- - Neonâ„¢ SIMD coprocessor and VFPv4 per CPU
-
- - Interrupt controller with up to 160 interrupt requests
-
- - One general-purpose timer and one watchdog timer per CPU – Debug
- and trace features
-
- - 32-KiB instruction and 32-KiB data level 1 (L1) cache per CPU
-
-- Shared 2-MiB level 2 (L2) cache
-
-- 48-KiB bootable ROM
-
-- Local power, reset, and clock management (PRCM) module
-
-- Emulation features
-
-- Digital phase-locked loop (DPLL)
-
-**DSP Subsystems** There are two DSP subsystems in the device. Each DSP
-subsystem contains the following submodules:
-
-- TMS320C66xâ„¢ Floating-Point VLIW DSP core for audio processing, and
- general-purpose imaging and video processing. It extends the
- performance of existing C64x+â„¢ and C647xâ„¢ DSPs through enhancements
- and new features.
-
- - 32-KiB L1D and 32-KiB L1P cache or addressable SRAM
-
- - 288-KiB L2 cache
-
-- 256-KiB configurable as cache or SRAM
-
-- 32-KiB SRAM
-
-- Enhanced direct memory access (EDMA) engine for video and audio data
- transfer
-
-- Memory management units (MMU) for address management.
-
-- Interrupt controller (INTC)
-
-- Emulation capabilities
-
-- Supported by OpenCL
-
-**EVE Subsystems**
-
-- 4 Embedded Vision Engines (EVEs) supported by TIDL machine learning
- library
-
-.. image:: images/BB_AI_EVEmodule.jpg
- :align: center
- :alt: BeagleBone AI component placement
-
-The Embedded Vision Engine (EVE) module is a programmable imaging and
-vision processing engine. Software support for the EVE module is
-available through OpenCL Custom Device model with fixed set of
-functions. More information is available
-http://www.ti.com/lit/wp/spry251/spry251.pdf
-
-**PRU-ICSS Subsystems**
-
-- 2x Dual-Core Programmable Real-Time Unit (PRU) subsystems (4 PRUs
- total) for ultra low-latency control and software generated
- peripherals. Access to these powerful subsystems is available through
- through the P8 and P9 headers. These are detailed in Section 7.
-
-**IPU Subsystems** There are two Dual Cortex-M4 IPU subsystems in the
-device available for general purpose usage, particularly real-time
-control. Each IPU subsystem includes the following components:
-
-- Two Cortex-M4 CPUs
-
-- ARMv7E-M and Thumb-2 instruction set architectures
-
-- Hardware division and single-cycle multiplication acceleration
-
-- Dedicated INTC with up to 63 physical interrupt events with 16-level
- priority
-
-- Two-level memory subsystem hierarchy
-
- - L1 (32-KiB shared cache memory)
-
- - L2 ROM + RAM
-
-- 64-KiB RAM
-
-- 16-KiB bootable ROM
-
-- MMU for address translation
-
-- Integrated power management
-
-- Emulation feature embedded in the Cortex-M4
-
-**IVA-HD Subsystem**
-
-- IVA-HD subsystem with support for 4K @ 15fps H.264 encode/decode and
- other codecs @ 1080p60 The IVA-HD subsystem is a set of video encoder
- and decoder hardware accelerators. The list of supported codecs can
- be found in the software development kit (SDK) documentation.
-
-**BB2D Graphics Accelerator Subsystem** The Vivante® GC320 2D graphics
-accelerator is the 2D BitBlt (BB2D) graphics accelerator subsystem on
-the device with the following features:
-
-- API support:
-
- - OpenWFâ„¢, DirectFB
-
- - GDI/DirectDraw
-
-- BB2D architecture:
-
- - BitBlt and StretchBlt
-
- - DirectFB hardware acceleration
-
- - ROP2, ROP3, ROP4 full alpha blending and transparency
-
- - Clipping rectangle support
-
- - Alpha blending includes Java 2 Porter-Duff compositing rules
-
- - 90-, 180-, 270-degree rotation on every primitive
-
- - YUV-to-RGB color space conversion
-
- - Programmable display format conversion with 14 source and 7
- destination formats
-
- - High-quality, 9-tap, 32-phase filter for image and video scaling
- at 1080p
-
- - Monochrome expansion for text rendering
-
- - 32K × 32K coordinate system
-
-**Dual-Core PowerVR® SGX544™ 3D GPU** The 3D graphics processing unit
-(GPU) subsystem is based on POWERVR® SGX544 subsystem from Imagination
-Technologies. It supports general embedded applications. The GPU can
-process different data types simultaneously, such as: pixel data, vertex
-data, video data, and general-purpose data. The GPU subsystem has the
-following features:
-
-- Multicore GPU architecture: two SGX544 cores.
-
-- Shared system level cache of 128 KiB
-
-- Tile-based deferred rendering architecture
-
-- Second-generation universal scalable shader engines (USSE2),
- multithreaded engines incorporating pixel and vertex shader
- functionality
-
-- Present and texture load accelerators
-
- - Enables to move, rotate, twiddle, and scale texture surfaces.
-
- - Supports RGB, ARGB, YUV422, and YUV420 surface formats.
-
- - Supports bilinear upscale.
-
- - Supports source colorkey.
-
-- Fine-grained task switching, load balancing, and power management
-
-- Programmable high-quality image antialiasing
-
-- Bilinear, trilinear, anisotropic texture filtering
-
-- Advanced geometry DMA driven operation for minimum CPU interaction
-
-- Fully virtualized memory addressing for OS operation in a unified
- memory architecture (MMU)
-
-Memory
-********
-
-.. _bbai_ddr:
-
-1GB DDR3L
-==========
-
-Dual 256M x 16 DDR3L memory devices are used, one on each side of the
-board, for a total of 1 GB. They will each operate at a clock frequency
-of up to 533 MHz yielding an effective rate of 1066Mb/s on the DDR3L bus
-allowing for 4GB/s of DDR3L memory bandwidth.
-
-16GB Embedded MMC
-===================
-
-A single 16GB embedded MMC (eMMC) device is on the board.
-
-
-microSD Connector
-==================
-
-The board is equipped with a single microSD connector to act as a
-secondary boot source for the board and, if selected as such, can be the
-primary booth source. The connector will support larger capacity microSD
-cards. The microSD card is not provided with the board.
-
-Boot Modes
-*************
-
-.. todo:: Need info on BBAI boot mode settings
-
-Power Management
-******************
-
-.. todo:: Need info on BBAI power management
-
-Connectivity
-******************
-
-.. todo:: Add WiFi/Bluetooth/Ethernet
-
-BeagleBone® AI supports the majority of the functions of the AM5729 SOC
-through connectors or expansion header pin accessibility. See section 7
-for more information on expansion header pinouts. There are a few
-functions that are not accessible which are: (TBD)
-
-.. todo:: This text needs to go somewhere.
-
-.. table:: On-board I2C Devices
-
- +---------+--------------+-----------------+
- | Address | Identifier | Description |
- +=========+==============+=================+
- | 0x12 | U3 | TPS6590379 PMIC |
- | | | DVS |
- +---------+--------------+-----------------+
- | 0x41 | U78 | STMPE811Q ADC |
- | | | and GPIO |
- | | | expander |
- +---------+--------------+-----------------+
- | 0x47 | U13 | HD3SS3220 USB |
- | | | Type-C DRP port |
- | | | controller |
- +---------+--------------+-----------------+
- | 0x50 | U9 | 24LC32 board ID |
- | | | EEPROM |
- +---------+--------------+-----------------+
- | 0x58 | U3 | TPS6590379 PMIC |
- | | | power registers |
- +---------+--------------+-----------------+
- | 0x5a | U3 | TPS6590379 PMIC |
- | | | interfaces and |
- | | | auxiliaries |
- +---------+--------------+-----------------+
- | 0x5c | U3 | TPS6590379 PMIC |
- | | | trimming and |
- | | | test |
- +---------+--------------+-----------------+
- | 0x5e | U3 | TPS6590379 PMIC |
- | | | OTP |
- +---------+--------------+-----------------+
diff --git a/boards/beaglebone/ai/ch08.rst b/boards/beaglebone/ai/ch08.rst
deleted file mode 100644
index 7201fc38..00000000
--- a/boards/beaglebone/ai/ch08.rst
+++ /dev/null
@@ -1,189 +0,0 @@
-.. _beaglebone-ai-cape-support:
-
-Cape Board Support
-#####################
-
-There is a `Cape Headers Google
-Spreadsheet <https://docs.google.com/spreadsheets/d/1fE-AsDZvJ-bBwzNBj1_sPDrutvEvsmARqFwvbw_HkrE/edit?usp=sharing>`__
-which has a lot of detail regarding various boards and cape add-on
-boards.
-
-See also https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
-
-TODO
-
-BeagleBone® Black Cape Compatibility
-**************************************
-
-TODO
-
-See https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec for
-now.
-
-EEPROM
-************
-
-TODO
-
-Pin Usage Consideration
-************************
-
-TODO
-
-GPIO
-*********
-
-TODO
-
-I2C
-*********
-
-TODO
-
-UART or PRU UART
-*******************
-
-This section is about both UART pins on the header and PRU UART pins on
-the headers we will include a chart and later some code
-
-.. table:: UART
-
- +-------------+--------+-----------+-------------------+-------+
- | Function | Pin | ABC Ball | Pinctrl Register | Mode |
- +=============+========+===========+===================+=======+
- | uart3_txd | P9.21 | B22 | 0x17C4 | 1 |
- +-------------+--------+-----------+-------------------+-------+
- | uart3_rxd | P9.22 | A26 | 0x17C0 | 1 |
- +-------------+--------+-----------+-------------------+-------+
- | uart5_txd | P9.13 | C17 | 0x1730 | 4 |
- +-------------+--------+-----------+-------------------+-------+
- | uart5_rxd | P9.11 | B19 | 0x172C | 4 |
- +-------------+--------+-----------+-------------------+-------+
- | uart5_ctsn | P8.05 | AC9 | 0x178C | 2 |
- +-------------+--------+-----------+-------------------+-------+
- | uart5_rtsn | P8.06 | AC3 | 0x1790 | 2 |
- +-------------+--------+-----------+-------------------+-------+
- | uart8_txd | P8.37 | A21 | 0x1738 | 3 |
- +-------------+--------+-----------+-------------------+-------+
- | uart8_rxd | P8.38 | C18 | 0x1734 | 3 |
- +-------------+--------+-----------+-------------------+-------+
- | uart8_ctsn | P8.31 | G16 | 0x173C | 3 |
- +-------------+--------+-----------+-------------------+-------+
- | uart8_rtsn | P8.32 | D17 | 0x1740 | 3 |
- +-------------+--------+-----------+-------------------+-------+
- | uart10_txd | P9.24 | F20 | 0x168C | 3 |
- +-------------+--------+-----------+-------------------+-------+
- | uart10_rxd | P9.26 | E21 | 0x1688 | 3 |
- +-------------+--------+-----------+-------------------+-------+
- | uart10_ctsn | P8.03 | AB8 | 0x179C | 2 |
- +-------------+--------+-----------+-------------------+-------+
- | uart10_rtsn | P8.04 | AB5 | 0x17A0 | 2 |
- +-------------+--------+-----------+-------------------+-------+
- | uart10_txd | P9.24 | F20 | 0x168C | 3 |
- +-------------+--------+-----------+-------------------+-------+
- | uart10_rxd | P9.26 | E21 | 0x1688 | 3 |
- +-------------+--------+-----------+-------------------+-------+
- | uart10_ctsn | P9.20 | D2 | 0x1578 | 8 |
- +-------------+--------+-----------+-------------------+-------+
- | uart10_rtsn | P9.19 | F4 | 0x157C | 8 |
- +-------------+--------+-----------+-------------------+-------+
-
-.. table:: PRU UART
-
- +------------------+--------+-----------+-------------------+-------+
- | Function | Pin | ABC Ball | Pinctrl Register | Mode |
- +==================+========+===========+===================+=======+
- | pr2_uart0_txd | P8.31 | C8 | 0x1614 | 10 |
- +------------------+--------+-----------+-------------------+-------+
- | pr2_uart0_rxd | P8.33 | C6 | 0x1610 | 10 |
- +------------------+--------+-----------+-------------------+-------+
- | pr2_uart0_cts_n | P8.34 | D8 | 0x1608 | 10 |
- +------------------+--------+-----------+-------------------+-------+
- | pr2_uart0_rts_n | P8.35 | A5 | 0x160C | 10 |
- +------------------+--------+-----------+-------------------+-------+
- | pr1_uart0_rxd | P8.43 | F10 | 0x15E4 | 10 |
- +------------------+--------+-----------+-------------------+-------+
- | pr1_uart0_txd | P8.44 | G11 | 0x15E8 | 10 |
- +------------------+--------+-----------+-------------------+-------+
- | pr1_uart0_cts_n | P8.45 | F11 | 0x15DC | 10 |
- +------------------+--------+-----------+-------------------+-------+
- | pr1_uart0_rts_n | P8.46 | G10 | 0x15E0 | 10 |
- +------------------+--------+-----------+-------------------+-------+
-
-
-TODO
-
-SPI
-****
-
-TODO
-
-Analog
-********
-
-TODO
-
-.. _pwm-timer-ecap-or-pru-pwm-ecap:
-
-PWM, TIMER, eCAP or PRU PWM/eCAP
-**********************************
-
-TODO
-
-eQEP
-******
-
-TODO
-
-CAN
-*****
-
-TODO
-
-.. _mcasp-audio-serial-like-i2c-and-ac97:
-
-McASP (audio serial like I2S and AC97)
-****************************************
-
-TODO
-
-MMC
-*****
-
-TODO
-
-LCD
-*****
-
-TODO
-
-PRU GPIO
-**********
-
-TODO
-
-CLKOUT
-********
-
-TODO
-
-Expansion Connector Headers
-******************************
-
-TODO: discuss header options for working with the expansion connectors per
-https://git.beagleboard.org/beagleboard/beaglebone-black/-/wikis/System-Reference-Manual#section-7-1
-
-Signal Usage
-****************
-
-TODO
-
-Cape Power
-************
-
-TODO
-
-Mechanical
-************
-
-TODO
diff --git a/boards/beaglebone/ai/index.rst b/boards/beaglebone/ai/index.rst
index 9f47f699..0fb75508 100644
--- a/boards/beaglebone/ai/index.rst
+++ b/boards/beaglebone/ai/index.rst
@@ -1,16 +1,21 @@
-.. _beaglebone-ai-home:
+.. _bbai-home:
BeagleBone AI
###############
-BeagleBone AI is based on the Texas Instruments AM5729 dual-core Cortex-A15 SoC with flexible BeagleBone Black header and mechanical compatibility. BeagleBone AI makes it easy to explore how artificial intelligence (AI) can be used in everyday life via the TI C66x digital-signal-processor (DSP) cores and embedded-vision-engine (EVE) cores supported through an optimized TIDL machine learning OpenCL API with pre-installed tools. Focused on everyday automation in industrial, commercial and home applications.
+BeagleBone AI is based on the Texas Instruments `AM5729 <https://www.ti.com/product/AM5729>`_ dual-core
+Cortex-A15 SoC with flexible BeagleBone Black header and mechanical compatibility. BeagleBone AI makes
+it easy to explore how artificial intelligence (AI) can be used in everyday life via the TI C66x
+digital-signal-processor (DSP) cores and embedded-vision-engine (EVE) cores supported through an
+optimized TIDL machine learning OpenCL API with pre-installed tools. Focused on everyday
+automation in industrial, commercial and home applications.
.. grid:: 2
.. grid-item::
:columns: 12 12 12 4
- .. figure:: images/OSHW_mark_US000169.*
+ .. figure:: media/OSHW_mark_US000169.*
:width: 200
:target: https://certification.oshwa.org/us000169.html
:alt: BeagleBone AI OSHW Mark
@@ -24,22 +29,122 @@ BeagleBone AI is based on the Texas Instruments AM5729 dual-core Cortex-A15 SoC
* Design materials and license can be found in the `git repository <https://git.beagleboard.org/beagleboard/beaglebone-ai>`__
* Use of the boards or design materials constitutes an agreement to the :ref:`boards-terms-and-conditions`
* Software images and purchase links available on the `board page <https://www.beagleboard.org/boards/beaglebone-ai>`__
- * For export, emissions and other compliance, see :ref:`beaglebone-ai-support`
+ * For export, emissions and other compliance, see :ref:`bbai-support`
-.. image:: images/BB_AI_handheld_500px.jpg
- :width: 500
+.. image:: media/BB_AI_handheld_500px.jpg
+ :width: 740
:align: center
:alt: BeagleBone AI
+.. only:: html
+
+ .. grid:: 1 1 2 3
+ :margin: 4 4 0 0
+ :gutter: 4
+
+ .. grid-item-card::
+ :link: bbai-introduction
+ :link-type: ref
+
+ **1. Introduction**
+ ^^^
+
+ .. image:: media/chapter-thumbnails/01-introduction.*
+ :align: center
+ :alt: BeagleBone AI Chapter01 thumbnail
+
+ +++
+
+ Introduction to BeagleBone AI board with information on each component
+ location on both front and back of the board.
+
+ .. grid-item-card::
+ :link: bbai-quick-start
+ :link-type: ref
+
+ **2. Quick start**
+ ^^^
+
+ .. image:: media/chapter-thumbnails/02-quick-start.*
+ :align: center
+ :alt: BeagleBone AI Chapter02 thumbnail
+
+ +++
+
+ Getting started guide to enable you to start building your projects
+ in no time.
+
+ .. grid-item-card::
+ :link: bbai-design-and-specifications
+ :link-type: ref
+
+ **3. Design & Specifications**
+ ^^^
+
+ .. image:: media/chapter-thumbnails/03-design-and-specifications.*
+ :align: center
+ :alt: BeagleBone AI Chapter03 thumbnail
+
+ +++
+
+ Hardware and mechanical design and specifications of BeagleBone AI board
+ for those who want to know their board inside and out.
+
+ .. grid-item-card::
+ :link: bbai-expansion
+ :link-type: ref
+
+ **4. Expansion**
+ ^^^
+
+ .. image:: media/chapter-thumbnails/04-expansion.*
+ :align: center
+ :alt: BeagleBone AI Chapter04 thumbnail
+
+ +++
+
+ Connector pinout diagrams with expansion details so that you can
+ easily debug your connections and create custom expansion hardware.
+
+ .. grid-item-card::
+ :link: bbai-demos-and-tutorials
+ :link-type: ref
+
+ **5. Demos**
+ ^^^
+
+ .. image:: media/chapter-thumbnails/05-demos-and-tutorials.*
+ :align: center
+ :alt: BeagleBone AI Chapter5 thumbnail
+
+ +++
+
+ Demos and tutorials to quickly learn about BeagleBone AI capabilities.
+
+ .. grid-item-card::
+ :link: bbai-support
+ :link-type: ref
+
+ **6. Support**
+ ^^^
+
+ .. image:: media/chapter-thumbnails/06-support.*
+ :align: center
+ :alt: BeagleBone AI Chapter6 thumbnail
+
+ +++
+
+ Additional supporting information, images, documents, change history and
+ hardware & software repositories including issue trackers.
+
.. toctree::
- :maxdepth: 1
-
- ch01
- ch03
- ch04
- ch05
- ch06
- ch07
- ch08
- ch11
+ :maxdepth: 1
+ :hidden:
+
+ 01-introduction
+ 02-quick-start
+ 03-design-and-specifications
+ 04-expansion
+ 05-demos-and-tutorials
+ 06-support
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diff --git a/index.rst b/index.rst
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--- a/index.rst
+++ b/index.rst
@@ -176,7 +176,7 @@ from source using appropriate design tools.
IIoT projects to the next level with a full Linux computer the size of a mint tin.
.. grid-item-card::
- :link: beaglebone-ai-home
+ :link: bbai-home
:link-type: ref
**BeagleBone® AI**
--
GitLab