diff --git a/Makefile b/Makefile
index 78a1646c16f02b4af5f3eae2b5d58f1e6c3e62e3..98e3ceab64e97fd89beba22ede84a6b6c4b35ef0 100644
--- a/Makefile
+++ b/Makefile
@@ -19,6 +19,9 @@ submodule:
librobotcontrol:
cd projects/librobotcontrol/docs/ ; doxygen
+livehtml:
+ sphinx-autobuild "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
.PHONY: help Makefile submodule librobotcontrol
# Catch-all target: route all unknown targets to Sphinx using the new
diff --git a/accessories/cables.rst b/accessories/cables.rst
index 3b5158f0b2b065a59e7a4b2d028ebe4dc7fccb07..3c6f678ec20edd0ae0df378d54cc193e69500ce8 100644
--- a/accessories/cables.rst
+++ b/accessories/cables.rst
@@ -155,12 +155,49 @@ JTAG debug Cables
TagConnect (JTAG)
==================
-Boards like :ref:`beagleconnect_freedom_home` and :ref:`beagleplay-home` use the TagConnect
-interface which allows you to perform firmware updates and JTAG hardware debugging. To use the
-interface, the the parts below from `tag-connect <https://www.tag-connect.com>`_ are required.
+Boards like :ref:`beagleconnect_freedom_home`, :ref:`beaglev-ahead-home`, :ref:`beaglev-fire-home`, and :ref:`beagleplay-home` use the TagConnect
+interface which allows you to perform firmware updates and JTAG hardware debugging. To use the interface, the the parts below from
+`tag-connect <https://www.tag-connect.com>`_ are required.
-1. `10pin TagConnect (no legs) ribbon cable. <https://www.tag-connect.com/product/tc2050-idc-nl-10-pin-no-legs-cable-with-ribbon-connector>`_
-2. `TagConnect retaining clip. <https://www.tag-connect.com/product/tc2050-clip-3pack-retaining-clip>`_
+.. note::
+ You need both the cable and the retaining clip to properly use/connect the cable with the boards.
+ There is an option to 3D print protective cap and retaining cap which you can try.
+
+TC2050 debug cable
+-------------------
+
+.. image:: images/tc2050-idc-nl-10-pin-debug-cable.jpg
+ :align: center
+ :width: 420
+ :alt: TC2050 10pin debug cable
+
+1. `TC2050 cable (tag-connect.com) <https://www.tag-connect.com/product/tc2050-idc-nl-10-pin-no-legs-cable-with-ribbon-connector>`_
+2. `TC2050 cable (DigiKey) <https://www.digikey.com/en/products/detail/tag-connect-llc/TC2050-IDC-NL/2605367>`_
+
+
+
+TC2050 retaining clip
+----------------------
+
+.. image:: images/TC2050-CLIP.jpg
+ :align: center
+ :width: 420
+ :alt: TC2050 retaining clip
+
+1. `TC2050 retaining clip (tag-connect.com) <https://www.tag-connect.com/product/tc2050-clip-3pack-retaining-clip>`_
+2. `TC2050 retaining clip (DigiKey) <https://www.digikey.com/en/products/detail/tag-connect-llc/TC2050-CLIP-3PACK/12318009>`_
+
+3D printable cap & clip (Optional)
+-----------------------------------
+
+.. image:: images/TC2050-protective-cap.jpg
+ :align: center
+ :width: 420
+ :alt: 3D printable TC2050 protective cap
+
+
+1. `Protective cap (Thingiverse) <https://www.thingiverse.com/thing:3025584>`_
+2. `Retaining clip (Thingiverse) <https://www.thingiverse.com/thing:3035278>`_
HDMI Cables
diff --git a/accessories/images/TC2050-CLIP.jpg b/accessories/images/TC2050-CLIP.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..361b838b853faf3fe0aa91e24d277d32f2d9e8e5
Binary files /dev/null and b/accessories/images/TC2050-CLIP.jpg differ
diff --git a/accessories/images/TC2050-protective-cap.jpg b/accessories/images/TC2050-protective-cap.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..78513c26d9b676965c9cf8d0dc873b7c93f5a08c
Binary files /dev/null and b/accessories/images/TC2050-protective-cap.jpg differ
diff --git a/accessories/images/tc2050-idc-nl-10-pin-debug-cable.jpg b/accessories/images/tc2050-idc-nl-10-pin-debug-cable.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..c9dd86cb951fd0b048c4b56e6f4982b7a1ae6ceb
Binary files /dev/null and b/accessories/images/tc2050-idc-nl-10-pin-debug-cable.jpg differ
diff --git a/boards/beaglev/ahead/04-expansion.rst b/boards/beaglev/ahead/04-expansion.rst
index 009f0ab064a8717bc4957f9e773c375a7c20ea82..b7c04143e0dd63d042e8b7d8c585eb12a9948ae6 100644
--- a/boards/beaglev/ahead/04-expansion.rst
+++ b/boards/beaglev/ahead/04-expansion.rst
@@ -482,7 +482,7 @@ The **GPIO** row is the expected gpio identifier number in the Linux
kernel.
Each row includes the gpiochipX and pinY in the format of
-`X Y`. You can use these values to direcly control the GPIO pins with the
+`X Y`. You can use these values to directly control the GPIO pins with the
commands shown below.
.. code:: bash
diff --git a/boards/beaglev/fire/05-demos.rst b/boards/beaglev/fire/05-demos.rst
index c318c38ca1cfd58905562383f2583d855daf2092..52a0c62c4094a140b6e5006c816742b27fcf7766 100644
--- a/boards/beaglev/fire/05-demos.rst
+++ b/boards/beaglev/fire/05-demos.rst
@@ -20,3 +20,4 @@ Demos
demos-and-tutorials/gateware/how-to-find-out-whats-on-the-board
demos-and-tutorials/gateware/gateware-full-flow
demos-and-tutorials/gateware/gateware-tcl-scripts-structure
+ demos-and-tutorials/gateware/customize-cape-gateware-verilog
diff --git a/boards/beaglev/fire/demos-and-tutorials/gateware/customize-cape-gateware-verilog.rst b/boards/beaglev/fire/demos-and-tutorials/gateware/customize-cape-gateware-verilog.rst
new file mode 100644
index 0000000000000000000000000000000000000000..43554b4c4276f446c1b934f772894e00aa4213e0
--- /dev/null
+++ b/boards/beaglev/fire/demos-and-tutorials/gateware/customize-cape-gateware-verilog.rst
@@ -0,0 +1,411 @@
+.. _beaglev-fire-customize-cape-gateware-verilog:
+
+Customize BeagleV-Fire Cape Gateware Using Verilog
+###################################################
+
+This document describes how to customize gateware attached to BeagleV-Fire's cape interface using
+Verilog as primary language. The methodolgy described can also be applied when using other HDL
+languages.
+
+It will describe:
+
+- How to generate programming bitstreams without requiring the installation of the Libero FPGA toolchain on your development machine.
+- How to use the cape Verilog template
+- How to use the git.beagleboard.org CI infrastruture to generate programming bitstreams for your custom gateware
+
+
+Steps:
+
+1. Fork BeagleV-Fire gateware repository on git.beagleboard.org
+2. Create a custom gateware build option
+3. Rename a copy of the cape gateware Verilog template
+4. Customize the cape's Verilog source code
+5. Commit and push changes to your forked repository
+6. Retrieve the forked repositories artifacts
+7. Program BeagleV-Fire with your custom bitstream
+
+
+Fork BeagleV-Fire Gateware Repository
+**************************************
+
+Navigate to BeagleV-Fire's `gateware source code repository <https://git.beagleboard.org/beaglev-fire/gateware>`_.
+
+Click on the ``Forks`` button on the top-right corner.
+
+.. figure:: media/gateware-beaglev-fire-fork.png
+ :align: center
+ :width: 1040
+ :alt: BeagleV-Fire gateware repo fork button
+
+ BeagleV-Fire gateware repo fork button
+
+
+On the Fork Project page, select your namespace and adjust the project name to help you manage multiple
+custom gateware (e.g. ``my-lovely-gateware``). Click the ``Fork project`` button.
+
+.. figure:: media/verilog-gateware-fork.png
+ :align: center
+ :width: 1040
+ :alt: Create gateware fork
+
+ Create gateware fork
+
+Clone the forked repository
+===========================
+
+.. code-block:: shell
+
+ git clone git@git.beagleboard.org:<MY-NAMESPACE>/my-lovely-gateware.git
+
+Where ``<MY-NAMESPACE>`` is your Gitlab username or namespace.
+
+Create A Custom Gateware Build Option
+**************************************
+
+BeagleV-Fire's gateware build system uses "build configuration" YAML files to describe the combination
+of gateware components options that will be used to build the gateware programming bitstream. You need
+to create one such file to describe to the gateware build system that you want your own custom gateware
+to be built. You need to have one such file describing your gateware in directory ``custom-fpga-design``.
+
+Let's modify the ``./custom-fpga-design/my_custom_fpga_design.yaml`` build configuration file to
+specify that your custom cape gateware should be included in the gateware bitstream. In this instance will
+call our custom cape gateware ``MY_LOVELY_CAPE``.
+
+.. callout::
+
+ .. code-block:: yaml
+
+ HSS:
+ type: git
+ link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
+ branch: develop-beaglev-fire
+ board: bvf
+ gateware:
+ type: sources
+ build-args: "M2_OPTION:NONE CAPE_OPTION:MY_LOVELY_CAPE" # <1>
+ unique-design-version: 9.0.2
+
+ .. annotations::
+
+ <1> On the gateware build-args line, replace VERILOG_TUTORIAL with MY_LOVELY_CAPE.
+
+.. note::
+ The **custom-fpga-design** directory has a special meaning for the Beagleboard Gitlab CI system.
+ Any build configuration found in this directory will be built by the CI system. This allows generating
+ FPGA programming bitstreams without the requirement for having the Microchip FPGA toolchain installed
+ on your computer.
+
+
+Rename A Copy Of The Cape Gateware Verilog Template
+****************************************************
+
+Move to the cape gateware source code
+=====================================
+
+.. code-block:: shell
+
+ cd my-lovely-gateware/sources/FPGA-design/script_support/components/CAPE
+
+Create a directory that will contain your custom cape gateware source code
+===========================================================================
+
+.. code-block:: shell
+
+ mkdir MY_LOVELY_CAPE
+
+Copy the cape Verilog template
+===============================
+
+.. code-block:: shell
+
+ cp -r VERILOG_TEMPLATE/* ./MY_LOVELY_CAPE/
+
+
+Customize The Cape's Verilog Source Code
+*****************************************
+
+Move to your custom gateware source directory
+=============================================
+
+.. code-block:: shell
+
+ cd MY_LOVELY_CAPE
+
+You will need to first edit the ``ADD_CAPE.tcl`` TCL script to use your source code within your custom
+gateware directory and not the Verilog template source code. In this example this means using source
+code within the ``MY_LOVELY_CAPE`` directory rather the VERILOG_TEMPLATE directory.
+
+Edit ADD_CAPE.tcl
+==================
+
+Replace ``VERILOG_TEMPLATE`` with ``MY_LOVELY_CAPE`` in file ``ADD_CAPE.tcl``.
+
+.. code-block:: tcl
+
+ #-------------------------------------------------------------------------------
+ # Import HDL source files
+ #-------------------------------------------------------------------------------
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/apb_ctrl_status.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P8_IOPADS.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_11_18_IOPADS.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_21_31_IOPADS.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_41_42_IOPADS.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/CAPE.v}
+
+Add the path to your additional Verilog source code files.
+
+.. callout::
+
+ .. code-block:: tcl
+
+ #-------------------------------------------------------------------------------
+ # Import HDL source files
+ #-------------------------------------------------------------------------------
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/blinky.v} // <1>
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/apb_ctrl_status.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P8_IOPADS.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_11_18_IOPADS.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_21_31_IOPADS.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_41_42_IOPADS.v}
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/CAPE.v}
+
+ .. annotations::
+
+ <1> In our case we will be adding a new Verilog source file called blinky.v.
+
+You will only need to revisit the content of ``ADD_CAPE.tcl`` if you want to add more Verilog source files
+or want to modify how the cape interfaces with the rest of the gateware (RISC-V processor subsystem,
+clock and reset blocks).
+
+Customize The Cape's Verilog source code
+=========================================
+
+We will add a simple Verilog source file, ``blinky.v``, in the ``MY_LOVELY_CAPE`` directory. Code below:
+
+.. code-block:: verilog
+
+ `timescale 1ns/100ps
+ module blinky(
+ input clk,
+ input resetn,
+ output blink
+ );
+
+
+ reg [22:0] counter;
+
+ assign blink = counter[22];
+
+ always@(posedge clk or negedge resetn)
+ begin
+ if(~resetn)
+ begin
+ counter <= 16'h0000;
+ end
+ else
+ begin
+ counter <= counter + 1;
+ end
+ end
+ endmodule
+
+Let's connect the blinky Verilog module within the cape by editing the ``CAPE.v`` file.
+
+Add the instantiation of the blinky module:
+
+.. callout::
+
+ .. code-block:: devicetree
+
+ //--------P9_41_42_IOPADS
+ P9_41_42_IOPADS P9_41_42_IOPADS_0(
+ // Inputs
+ .GPIO_OE ( GPIO_OE_const_net_3 ),
+ .GPIO_OUT ( GPIO_OUT_const_net_3 ),
+ // Outputs
+ .GPIO_IN ( ),
+ // Inouts
+ .P9_41 ( P9_41 ),
+ .P9_42 ( P9_42 )
+ );
+
+ //--------blinky
+ blinky blinky_0( // <1>
+ .clk ( PCLK ), // <2>
+ .resetn ( PRESETN ), // <3>
+ .blink ( BLINK ) // <4>
+ );
+
+ endmodule
+
+ .. annotations::
+
+ <1> Create a blinky module instance called blinky_0.
+
+ <2> Connect the clock using the existing PCLK wire.
+
+ <3> Connect the reset using the exisitng PRESETS wire.
+
+ <4> Connect the blinky's blink output using the BLINK wire. This BLINK wire needs to be declared.
+
+Add the BLINK wire:
+
+.. callout::
+
+ .. code-block:: verilog
+
+ wire PCLK;
+ wire PRESETN;
+ wire BLINK; // <1>
+ wire [31:0] APB_SLAVE_PRDATA_net_0;
+ wire [27:0] GPIO_IN_net_1;
+
+ .. annotations::
+
+ <1> Create a wire called BLINK.
+
+The BLINK wire will be used to connect the blinky module's output to a top level output connected
+to an LED. Do you see where this is going?
+
+Now for the complicated part. We are going to change the wiring of the bi-directional buffers
+controlling the cape I/Os including the user LEDs.
+
+The original code populates two 43 bits wide wires for controlling the output-enable and output
+values of the P8 cape connector I/Os. The bottom 28 bits being controlled by the microprocessor
+subsystem's GPIO block.
+
+ .. code-block:: verilog
+
+ //--------------------------------------------------------------------
+ // Concatenation assignments
+ //--------------------------------------------------------------------
+ assign GPIO_OE_net_0 = { 16'h0000 , GPIO_OE };
+ assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT };
+
+We are going to hijack the 6th I/O with our blinky's output:
+
+.. callout::
+
+ .. code-block:: verilog
+
+ //--------------------------------------------------------------------
+ // Concatenation assignments
+ //--------------------------------------------------------------------
+ assign GPIO_OE_net_0 = { 16'h0000, GPIO_OE[27:6], 1'b1, GPIO_OE[4:0] }; // <1>
+ assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT[27:6], BLINK, GPIO_OUT[4:0] }; // <2>
+
+ .. annotations::
+
+ <1> Tie high the output-enable of the 6th bit to constantly enable that output.
+
+ <2> Control the 6th output from the blink module through the WIRE wire.
+
+
+Edit The Cape's Device Tree Overlay
+=====================================
+
+You should always have a device tree overlay associated with your gateware even if there is limited
+control from Linux. The device tree overlay is very useful to identify which gateware is currently
+programmed on your BeagleV-Fire.
+
+.. callout::
+
+ .. code-block:: devicetree
+
+ /dts-v1/;
+ /plugin/;
+
+ &{/chosen} {
+ overlays {
+ MY-LOVELY-CAPE-GATEWARE = "GATEWARE_GIT_VERSION"; // <1>
+ };
+ };
+
+ .. annotations::
+
+ <1> Replace VERILOG-CAPE-GATEWARE with MY-LOVELY-CAPE-GATEWARE.
+
+This change will result in ``MY-LOVELY-CAPE-GATEWARE`` being visible in ``/proc/device-tree/chosen/overlays``
+at run-time, allowing to check that my lovely gateware is successfully programmed on BeagleV-Fire.
+
+
+Commit And Push Changes To Your Forked Repository
+**************************************************
+
+Move back up to the root directory of your gateware project. This is the my-lovely-gateware directory in our current example.
+
+Add the ``my-lovely-gateware/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE`` directory content to your git repository.
+
+.. code:: shell
+
+ git add sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/
+
+Commit changes to ``my-lovely-gateware/custom-fpga-design/my_custom_fpga_design.yaml``
+
+.. code:: shell
+
+ git commit -m "Add my lovely gateware."
+
+Push changes to your beagleboard Gitlab repository:
+
+.. code:: shell
+
+ git push
+
+
+Retrieve The Forked Repositories Artifacts
+*******************************************
+
+Navigate to your forked repository. Click Pipelines in the left pane then the Download Artifacts
+button on the right handside. Select ``build-job:archive``. This will result in an ``artifacts.zip`` file
+being downloaded.
+
+.. figure:: media/gateware-pipeline.png
+ :align: center
+ :width: 1040
+ :alt: gateware pipeline
+
+ gateware pipeline
+
+Program BeagleV-Fire With Your Custom Bitstream
+************************************************
+
+Unzip the downloaded ``artifacts.zip`` file. Go to the ``gateware-builds-tester/artifacts/bitstreams`` directory:
+
+.. code:: shell
+
+ cd gateware-builds-tester/artifacts/bitstreams
+
+On your Linux host development computer, use the scp command to copy the bitstream to BeagleV-Fire
+home directory, replacing ``<IP_ADDRESS>`` with the IP address of your BeagleV-Fire.
+
+.. code:: shell
+
+ scp -r ./my_custom_fpga_design beagle@<IP_ADDRESS>:/home/beagle/
+
+On BeagleV-Fire, initiate the reprogramming of the FPGA with your gateware bitstream:
+
+.. code:: shell
+
+ sudo /usr/share/beagleboard/gateware/changes-gateware.sh ./my_custom_fpga_design
+
+Wait for a couple of minutes for the BeagleV-Fire to reprogram itself.
+
+You will see the 6th user LED flash once the board is reprogrammed. That's the Verilog you added
+blinking the LED.
+
+On BeagleV-Fire, You can check that your gateware was loaded using the following command to see the
+device tree overlays:
+
+.. code:: shell
+
+ tree /proc/device-tree/chosen/overlays/
+
+.. figure:: media/gateware-lovely-overlay.png
+ :align: center
+ :width: 740
+ :alt: gateware lovely overlay
+
+ gateware lovely overlay
+
+
diff --git a/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-beaglev-fire-fork.png b/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-beaglev-fire-fork.png
new file mode 100644
index 0000000000000000000000000000000000000000..04829b7d72c69bd6e25de5cc9bf20703abfe0938
Binary files /dev/null and b/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-beaglev-fire-fork.png differ
diff --git a/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-lovely-overlay.png b/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-lovely-overlay.png
new file mode 100644
index 0000000000000000000000000000000000000000..db841f5484d5de15f63621708d38a0dbde1e835c
Binary files /dev/null and b/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-lovely-overlay.png differ
diff --git a/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-pipeline.png b/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-pipeline.png
new file mode 100644
index 0000000000000000000000000000000000000000..219510bcf63a65ddba57712e55e455d068be788e
Binary files /dev/null and b/boards/beaglev/fire/demos-and-tutorials/gateware/media/gateware-pipeline.png differ
diff --git a/boards/beaglev/fire/demos-and-tutorials/gateware/media/verilog-gateware-fork.png b/boards/beaglev/fire/demos-and-tutorials/gateware/media/verilog-gateware-fork.png
new file mode 100644
index 0000000000000000000000000000000000000000..5488a4dd28f324fefc9c2cbf8ce99752c316da5c
Binary files /dev/null and b/boards/beaglev/fire/demos-and-tutorials/gateware/media/verilog-gateware-fork.png differ
diff --git a/books/beaglebone-cookbook/01basics/basics.rst b/books/beaglebone-cookbook/01basics/basics.rst
index f96f0876f209c605136ae3d93dbac24f893a346a..d1bc345671159bd6f3c50bd7f3a1f528333d9ca4 100644
--- a/books/beaglebone-cookbook/01basics/basics.rst
+++ b/books/beaglebone-cookbook/01basics/basics.rst
@@ -428,7 +428,7 @@ in a way that you'd like to preserve or share.
Solution
---------
-The `eLinux wiki <The http://elinux.org/Beagleboard>`_ page on `BeagleBone Black Extracting eMMC contents <http://bit.ly/1C57I0a>`_
+The `eLinux wiki <http://elinux.org/Beagleboard>`_ page on `BeagleBone Black Extracting eMMC contents <http://bit.ly/1C57I0a>`_
provides some simple steps for copying the contents of the onboard flash to a file on a microSD card:
- Get a 4 GB or larger microSD card that is FAT formatted.
@@ -448,7 +448,7 @@ provides some simple steps for copying the contents of the onboard flash to a fi
.. tip::
- The `eLinux wiki <The http://elinux.org/Beagleboard>`_ is the
+ The `eLinux wiki <http://elinux.org/Beagleboard>`_ is the
definitive place for the BeagleBoard.org community to
share information about the Beagles. Spend some time
looking around for other helpful information.
diff --git a/books/beaglebone-cookbook/11misc/misc.rst b/books/beaglebone-cookbook/11misc/misc.rst
index 2fdb0b5b758ff8c5131cdb1883e6c29486894ace..8e0e5c6431f8335f4d608fe2a732db0b4b7cb486 100644
--- a/books/beaglebone-cookbook/11misc/misc.rst
+++ b/books/beaglebone-cookbook/11misc/misc.rst
@@ -811,6 +811,12 @@ To preview docs on your local machine:
bone$ sphinx-serve
+For hot reload in development:
+
+.. code-block:: bash
+
+ bone$ make livehtml
+
Then point your browser to localhost:8081.
.. tip::
diff --git a/conf.py b/conf.py
index 2c0b4efdb786055b21436a0ddcb9c918b3915a27..0b60e726eeb13c3397d21ca61df1aead98cb9f0f 100644
--- a/conf.py
+++ b/conf.py
@@ -87,7 +87,7 @@ navigation_with_keys = True
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This pattern also affects html_static_path and html_extra_path.
-exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store', 'env']
+exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store', 'env', ".venv"]
html_theme = 'sphinx_rtd_theme'
html_show_sphinx = False
diff --git a/requirements.txt b/requirements.txt
index 767efb557c21b578eddbd908547bc6c7696fe097..05dcb1eeaf8bc105cbd268cbf8ce9284a48f97e1 100644
--- a/requirements.txt
+++ b/requirements.txt
@@ -3,19 +3,23 @@ Babel==2.13.1
breathe==4.35.0
certifi==2023.11.17
charset-normalizer==3.3.2
+colorama==0.4.6
docutils==0.18.1
graphviz==0.20.1
idna==3.6
imagesize==1.4.1
Jinja2==3.1.2
+livereload==2.6.3
MarkupSafe==2.1.3
packaging==23.2
Pillow==10.1.0
Pygments==2.17.2
requests==2.31.0
setuptools==69.0.2
+six==1.16.0
snowballstemmer==2.2.0
Sphinx==7.2.6
+sphinx-autobuild==2021.3.14
sphinx-copybutton==0.5.2
sphinx-rtd-theme==2.0.0
sphinx-serve==1.0.1
@@ -30,4 +34,5 @@ sphinxcontrib-jsmath==1.0.1
sphinxcontrib-qthelp==1.0.6
sphinxcontrib-serializinghtml==1.1.9
sphinxcontrib-svg2pdfconverter==1.2.2
+tornado==6.4
urllib3==2.1.0