recipes/libero-project/program-device.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+open_project -file {./output/libero_project/libero_project.prjx} -do_backup_on_convert 1 -backup_file {./output/libero_project/libero_project.zip} 
+
+# configure_tool \
+         -name {IO_PROGRAMMING_STATE} \
+         -params {ios_file:} 
+
+# configure_tool \
+         -name {CONFIGURE_PROG_OPTIONS} \
+         -params {back_level_version:0} \
+         -params {design_version:0} \
+         -params {silicon_signature:} 
+
+# configure_tool \
+         -name {SPM} \
+         -params {back_level_protection:true} \
+         -params {debug_passkey:} \
+         -params {disable_authenticate_action:false} \
+         -params {disable_autoprog_iap_services:false} \
+         -params {disable_debug_jtag_boundary_scan:false} \
+         -params {disable_debug_read_temp_volt:false} \
+         -params {disable_debug_ujtag:false} \
+         -params {disable_ext_zeroization:false} \
+         -params {disable_external_digest_check:false} \
+         -params {disable_jtag:false} \
+         -params {disable_program_action:false} \
+         -params {disable_puf_emulation:false} \
+         -params {disable_smartdebug_debug:false} \
+         -params {disable_smartdebug_live_probe:false} \
+         -params {disable_smartdebug_snvm:false} \
+         -params {disable_spi_slave:false} \
+         -params {disable_user_encryption_key_1:false} \
+         -params {disable_user_encryption_key_2:false} \
+         -params {disable_verify_action:false} \
+         -params {envm_update_protection:open} \
+         -params {fabric_update_protection:open} \
+         -params {security_factory_access:open} \
+         -params {security_key_mode:default} \
+         -params {user_encryption_key_1:} \
+         -params {user_encryption_key_2:} \
+         -params {user_passkey_1:} \
+         -params {user_passkey_2:} 
+
+run_tool -name {GENERATEPROGRAMMINGFILE} 
+
+# Program the SPI first so the device is reset after bitstream programming to boot the payload
+run_tool -name {GENERATE_SPI_FLASH_IMAGE} 
+run_tool -name {PROGRAM_SPI_FLASH_IMAGE} 
+
+configure_tool -name {CONFIGURE_ACTION_PROCEDURES} \
+         -params {prog_optional_procedures:""} \
+         -params {skip_recommended_procedures:""} 
+
+run_tool -name {PROGRAMDEVICE}
+
+save_project 

recipes/libero-project/run-flow.tcl

+# The Microchip Bitstream Builder is released under the following software licese:
+
+#  Copyright 2021 Microchip Corporation.
+#  SPDX-License-Identifier: MIT
+
+#  Permission is hereby granted, free of charge, to any person obtaining a copy
+#  of this software and associated documentation files (the "Software"), to
+#  deal in the Software without restriction, including without limitation the
+#  rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+#  sell copies of the Software, and to permit persons to whom the Software is
+#  furnished to do so, subject to the following conditions:
+
+#  The above copyright notice and this permission notice shall be included in
+#  all copies or substantial portions of the Software.
+
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+#  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+#  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+#  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+#  IN THE SOFTWARE.
+
+open_project -file {./output/libero_project/libero_project.prjx} -do_backup_on_convert 1 -backup_file {./output/libero_project/libero_project.zip} 
+
+# organize_tool_files -tool {SIM_PRESYNTH} \
+    -file {} \
+    -module {base::work} \
+    -input_type {stimulus} 
+
+# run_tool -name {SIM_PRESYNTH}
+
+# Configure synthesis options
+# configure_tool \
+     -name {SYNTHESIZE} \
+     -params {ACTIVE_IMPLEMENTATION:synthesis} \
+     -params {AUTO_COMPILE_POINT:true} \
+     -params {BLOCK_MODE:false} \
+     -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} \
+     -params {BLOCK_ROUTING_CONFLICTS:LOCK} \
+     -params {CDC_MIN_NUM_SYNC_REGS:2} \
+     -params {CDC_REPORT:true} \
+     -params {CLOCK_ASYNC:800} \
+     -params {CLOCK_DATA:5000} \
+     -params {CLOCK_GATE_ENABLE:false} \
+     -params {CLOCK_GATE_ENABLE_THRESHOLD_GLOBAL:1000} \
+     -params {CLOCK_GATE_ENABLE_THRESHOLD_ROW:100} \
+     -params {CLOCK_GLOBAL:2} \
+     -params {CREATE_IMPLEMENTATION_IDENTIFY:} \
+     -params {CREATE_IMPLEMENTATION_SYNTHESIS:synthesis} \
+     -params {PA4_GB_COUNT:36} \
+     -params {PA4_GB_MAX_RCLKINT_INSERTION:16} \
+     -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:1000} \
+     -params {RAM_OPTIMIZED_FOR_POWER:0} \
+     -params {RETIMING:false} \
+     -params {ROM_TO_LOGIC:true} \
+     -params {SEQSHIFT_TO_URAM:1} \
+     -params {SYNPLIFY_OPTIONS:} \
+     -params {SYNPLIFY_TCL_FILE:} 
+
+# Run synthesis
+run_tool -name {SYNTHESIZE}
+
+# organize_tool_files -tool {SIM_POSTSYNTH} \
+    -file {} \
+    -module {base::work} \
+    -input_type {stimulus} 
+
+# run_tool -name {SIM_POSTSYNTH}
+
+# Export the netlist
+# run_tool -name {EXPORTNETLIST}
+
+# Timing verification 
+# Max timing work first - no high effort, no min delay
+configure_tool -name {PLACEROUTE} \
+    -params {DELAY_ANALYSIS:MAX} \
+    -params {EFFORT_LEVEL:false} \
+    -params {GB_DEMOTION:true} \
+    -params {INCRPLACEANDROUTE:false} \
+    -params {IOREG_COMBINING:false} \
+    -params {MULTI_PASS_CRITERIA:VIOLATIONS} \
+    -params {MULTI_PASS_LAYOUT:false} \
+    -params {NUM_MULTI_PASSES:5} \
+    -params {PDPR:false} \
+    -params {RANDOM_SEED:0} \
+    -params {REPAIR_MIN_DELAY:true} \
+    -params {REPLICATION:false} \
+    -params {SLACK_CRITERIA:WORST_SLACK} \
+    -params {SPECIFIC_CLOCK:} \
+    -params {START_SEED_INDEX:1} \
+    -params {STOP_ON_FIRST_PASS:false} \
+    -params {TDPR:true} 
+
+run_tool -name {PLACEROUTE} 
+
+# Check for max delay and min delay violations using timing verification
+
+run_tool -name {VERIFYTIMING}
+
+# if no max violations continue...
+
+# Min delay next in incremental
+configure_tool -name {PLACEROUTE} \
+    -params {DELAY_ANALYSIS:MAX} \
+    -params {EFFORT_LEVEL:false} \
+    -params {GB_DEMOTION:true} \
+    -params {INCRPLACEANDROUTE:true} \
+    -params {IOREG_COMBINING:false} \
+    -params {MULTI_PASS_CRITERIA:VIOLATIONS} \
+    -params {MULTI_PASS_LAYOUT:false} \
+    -params {NUM_MULTI_PASSES:25} \
+    -params {PDPR:false} \
+    -params {RANDOM_SEED:7} \
+    -params {REPAIR_MIN_DELAY:true} \
+    -params {REPLICATION:false} \
+    -params {SLACK_CRITERIA:WORST_SLACK} \
+    -params {SPECIFIC_CLOCK:} \
+    -params {START_SEED_INDEX:9} \
+    -params {STOP_ON_FIRST_PASS:true} \
+    -params {TDPR:true}
+
+run_tool -name {PLACEROUTE}
+
+# Finial timing check - should stop here on violations
+run_tool -name {VERIFYTIMING}
+
+run_tool -name {VERIFYPOWER}
+
+# run_tool -name {EXPORTSDF}
+
+# organize_tool_files -tool {SIM_POSTLAYOUT} \
+    -file {} \
+    -module {base::work} \
+    -input_type {stimulus} 
+
+# run_tool -name {SIM_POSTLAYOUT}
+
+# run_tool -name {CONFIGURE_CHAIN}
+
+# select_programmer -programmer_id {S2011K1YJJ}
+
+run_tool -name {GENERATEPROGRAMMINGDATA}
+
+save_project 

script_support/B_V_F_recursive.tcl

-if {[file isdirectory $local_dir/script_support/components/MSS]} {
-    file delete -force $local_dir/script_support/components/MSS
-}
-file mkdir $local_dir/script_support/components/MSS
-exec $mss_config_loc -GENERATE -CONFIGURATION_FILE:$local_dir/script_support/MSS_Configuration.cfg -OUTPUT_DIR:$local_dir/script_support/components/MSS
-import_mss_component -file "$local_dir/script_support/components/MSS/PF_SOC_MSS.cxz"
-source script_support/hdl_source.tcl
-source script_support/components/CLOCKS_AND_RESETS/CORERESET_0.tcl
-source script_support/components/CLOCKS_AND_RESETS/INIT_MONITOR.tcl 
-source script_support/components/CLOCKS_AND_RESETS/FPGA_CCC_C0.tcl
-source script_support/components/FIC0_INITIATOR.tcl 
-source script_support/components/CLOCKS_AND_RESETS/CLK_DIV.tcl 
-source script_support/components/CLOCKS_AND_RESETS/GLITCHLESS_MUX.tcl 
-source script_support/components/CLOCKS_AND_RESETS/TRANSMIT_PLL.tcl 
-source script_support/components/CLOCKS_AND_RESETS/PCIE_REF_CLK.tcl 
-source script_support/components/FIC3_INITIATOR.tcl
-source script_support/components/CLOCKS_AND_RESETS/OSCILLATOR_160MHz.tcl
-source script_support/components/CLOCKS_AND_RESETS/ADC_MCLK_CCC.tcl 
-source script_support/components/CLOCKS_AND_RESETS/CLOCKS_AND_RESETS.tcl 
-source script_support/components/IHC_APB.tcl
-source script_support/components/IHC_SUBSYSTEM.tcl
-source script_support/components/BVF_RISCV_SUBSYSTEM.tcl
-source script_support/components/BVF_GATEWARE.tcl 
-set_root -module ${top_level_name}::work 

script_support/components/CAPE/DEFAULT/device-tree-overlay/cape-gpios.dtso

-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-/dts-v1/;
-/plugin/;
-
-&{/chosen} {
-	overlays {
-		DEFAULT-CAPE-GATEWARE = "Mon Oct  2 18:00:17 2023";
-	};
-};
-
-&{/} {
-	fabric-bus@40000000 {
-		core_pwm0: pwm@41000000 {
-			compatible = "microchip,corepwm-rtl-v4";
-			reg = <0x0 0x41000000 0x0 0xF0>;
-			microchip,sync-update-mask = /bits/ 32 <0>;
-			#pwm-cells = <3>;
-			clocks = <&fabric_clk3>;
-			status = "okay";
-		};
-
-		cape_gpios_p8: gpio@41100000 {
-			compatible = "microchip,core-gpio";
-			reg = <0x0 0x41100000 0x0 0x1000>;
-			clocks = <&fabric_clk3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios=<16>;
-			status = "okay";
-			gpio-line-names = "P8_31", "P8_32", "P8_33", "P8_34",
-			                  "P8_35", "P8_36", "P8_37", "P8_38",
-			                  "P8_39", "P8_40", "P8_41", "P8_42",
-			                  "P8_43", "P8_44", "P8_45", "P8_46";
-		};
-
-		cape_gpios_p9: gpio@41200000 {
-			compatible = "microchip,core-gpio";
-			reg = <0x0 0x41200000 0x0 0x1000>;
-			clocks = <&fabric_clk3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios=<21>;
-			status = "okay";
-			gpio-line-names = "", "P9_12", "", "", "P9_15",
-			                  "", "", "", "", "",
-			                  "P9_23", "", "P9_25", "", "P9_27",
-			                  "", "", "P9_30", "", "P9_41",
-			                  "";
-		};
-
-		bone_pwm_1: pwm@41400000 {
-			compatible = "microchip,corepwm-rtl-v4";
-			reg = <0x0 0x41400000 0x0 0xF0>;
-			microchip,sync-update-mask = /bits/ 32 <0>;
-			#pwm-cells = <3>;
-            status = "okay";
-			clocks = <&fabric_clk3>;
-		};
-
-		bone_pwm_2: pwm@41500000 {
-			compatible = "microchip,corepwm-rtl-v4";
-			reg = <0x0 0x41500000 0x0 0xF0>;
-			microchip,sync-update-mask = /bits/ 32 <0>;
-			#pwm-cells = <3>;
-            status = "okay";
-			clocks = <&fabric_clk3>;
-		};
-	};
-};
-
-&gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
-	gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
-					"P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
-					"P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
-					"P8_PIN12_USER_LED_9", "", "P8_PIN14_USER_LED_11",
-					"P8_15", "P8_16", "P8_17", "P8_18", "",
-					"P8_20", "P8_21", "P8_22",	"P8_23", "P8_24",
-					"P8_25", "P8_26", "P8_27", "P8_28", "P8_29",
-					"P8_30",
-					"M2_W_DISABLE1", "M2_W_DISABLE2",
-					"VIO_ENABLE", "SD_DET";
-	status = "okay";
-
-	vio_enable {
-		gpio-hog;
-		gpios = <30 30>;
-		output_high;
-		line-name = "VIO_ENABLE";
-	};
-
-	sd_det {
-		gpio-hog;
-		gpios = <31 31>;
-		input;
-		line-name = "SD_DET";
-	};
-};
-
-&mmuart4 {
-	status = "okay";
-};

script_support/components/CAPE/GPIOS/CAPE.tcl

-# Creating SmartDesign CAPE
-set sd_name {CAPE}
-create_smartdesign -sd_name ${sd_name}
-
-#-------------------------------------------------------------------------------
-# Create APB Bus
-#-------------------------------------------------------------------------------
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
-"APBSLOT0ENABLE:false" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:true" "APBSLOT3ENABLE:false" \
-"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
-"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
-"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
-"APB_DWIDTH:32" \
-"IADDR_OPTION:0" \
-"MADDR_BITS:24" \
-"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
-"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
-"SC_12:false" "SC_13:false" "SC_14:false" \
-"SC_15:false" \
-"UPR_NIBBLE_POSN:5"}
-
-sd_instantiate_component -sd_name {CAPE} -component_name {CoreAPB3_CAPE} -instance_name {} 
-
-#-------------------------------------------------------------------------------
-# Create APB Bus Converter
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
-
-#-------------------------------------------------------------------------------
-# Add Default Cape GPIOs
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_DEFAULT_GPIOS} -instance_name {CAPE_DEFAULT_GPIOS}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OUT} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OE} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_IN} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN3_USER_LED_0}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN4_USER_LED_1}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN5_USER_LED_2}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN6_USER_LED_3}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN7_USER_LED_4}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN8_USER_LED_5}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN9_USER_LED_6}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN10_USER_LED_7}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN11_USER_LED_8}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN12_USER_LED_9}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_PIN13_USER_LED_10}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN14_USER_LED_11}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P8_PIN19}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P8_PIN20}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P8_PIN21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P8_PIN22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P8_PIN23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P8_PIN24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P8_PIN25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P8_PIN26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P8_PIN27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P8_PIN28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P8_PIN29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_PIN30}
-
-
-#-------------------------------------------------------------------------------
-# P8
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PRESETN} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PCLK} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN32}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN33}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN34}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN35}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN36}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN37}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN38}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN39}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN40}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_PIN41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN42}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN43}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN44}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN45}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN46}
-
-#-------------------------------------------------------------------------------
-# P9
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance_name {P9_GPIO_0}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P9_PIN11}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P9_PIN12}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P9_PIN13}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P9_PIN14}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P9_PIN15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P9_PIN16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P9_PIN17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P9_PIN18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P9_PIN21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P9_PIN22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P9_PIN23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P9_PIN24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P9_PIN25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P9_PIN26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P9_PIN27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P9_PIN28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P9_PIN29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P9_PIN30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P9_PIN31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P9_PIN41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P9_PIN42}
-
-#-------------------------------------------------------------------------------
-# Connections
-#-------------------------------------------------------------------------------
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "P9_GPIO_0:PRESETN"} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "P9_GPIO_0:PCLK"} 
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:APB_bif" "CoreAPB3_CAPE_0:APBmslave2"} 
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {APB_BUS_CONVERTER_0:APB_SLAVE} -port_name {} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster"} 
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE
-generate_component -component_name ${sd_name}

script_support/components/CAPE/GPIOS/CAPE_PWM.tcl

-# Creating SmartDesign CAPE_PWM
-set sd_name {CAPE_PWM}
-create_smartdesign -sd_name ${sd_name}
-
-
-create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -component_name {corepwm_C1} -params {\
-"APB_DWIDTH:32" "CONFIG_MODE:0" \
-"DAC_MODE1:false" "DAC_MODE2:false" "DAC_MODE3:false" "DAC_MODE4:false" "DAC_MODE5:false" \
-"DAC_MODE6:false" "DAC_MODE7:false" "DAC_MODE8:false" "DAC_MODE9:false" "DAC_MODE10:false" \
-"DAC_MODE11:false" "DAC_MODE12:false" "DAC_MODE13:false" "DAC_MODE14:false" "DAC_MODE15:false" \
-"DAC_MODE16:false" \
-"FIXED_PERIOD:1" "FIXED_PERIOD_EN:false" "FIXED_PRESCALE:0" "FIXED_PRESCALE_EN:false" \
-"FIXED_PWM_NEGEDGE1:0" "FIXED_PWM_NEGEDGE2:0" "FIXED_PWM_NEGEDGE3:0" "FIXED_PWM_NEGEDGE4:0" "FIXED_PWM_NEGEDGE5:0" \
-"FIXED_PWM_NEGEDGE6:0" "FIXED_PWM_NEGEDGE7:0" "FIXED_PWM_NEGEDGE8:0" "FIXED_PWM_NEGEDGE9:0" "FIXED_PWM_NEGEDGE10:0" \
-"FIXED_PWM_NEGEDGE11:0" "FIXED_PWM_NEGEDGE12:0" "FIXED_PWM_NEGEDGE13:0" "FIXED_PWM_NEGEDGE14:0" "FIXED_PWM_NEGEDGE15:0" \
-"FIXED_PWM_NEGEDGE16:0" \
-"FIXED_PWM_NEG_EN1:false" "FIXED_PWM_NEG_EN2:false" "FIXED_PWM_NEG_EN3:false" "FIXED_PWM_NEG_EN4:false" "FIXED_PWM_NEG_EN5:false" \
-"FIXED_PWM_NEG_EN6:false" "FIXED_PWM_NEG_EN7:false" "FIXED_PWM_NEG_EN8:false" "FIXED_PWM_NEG_EN9:false" "FIXED_PWM_NEG_EN10:false" \
-"FIXED_PWM_NEG_EN11:false" "FIXED_PWM_NEG_EN12:false" "FIXED_PWM_NEG_EN13:false" "FIXED_PWM_NEG_EN14:false" "FIXED_PWM_NEG_EN15:false" \
-"FIXED_PWM_NEG_EN16:false" \
-"FIXED_PWM_POSEDGE1:0" "FIXED_PWM_POSEDGE2:0" "FIXED_PWM_POSEDGE3:0" "FIXED_PWM_POSEDGE4:0" "FIXED_PWM_POSEDGE5:0" \
-"FIXED_PWM_POSEDGE6:0" "FIXED_PWM_POSEDGE7:0" "FIXED_PWM_POSEDGE8:0" "FIXED_PWM_POSEDGE9:0" "FIXED_PWM_POSEDGE10:0" \
-"FIXED_PWM_POSEDGE11:0" "FIXED_PWM_POSEDGE12:0" "FIXED_PWM_POSEDGE13:0" "FIXED_PWM_POSEDGE14:0" "FIXED_PWM_POSEDGE15:0" \
-"FIXED_PWM_POSEDGE16:0" \
-"FIXED_PWM_POS_EN1:false" "FIXED_PWM_POS_EN2:false" "FIXED_PWM_POS_EN3:false" "FIXED_PWM_POS_EN4:false" "FIXED_PWM_POS_EN5:false" \
-"FIXED_PWM_POS_EN6:true" "FIXED_PWM_POS_EN7:true" "FIXED_PWM_POS_EN8:true" "FIXED_PWM_POS_EN9:true" "FIXED_PWM_POS_EN10:true" \
-"FIXED_PWM_POS_EN11:true" "FIXED_PWM_POS_EN12:true" "FIXED_PWM_POS_EN13:true" "FIXED_PWM_POS_EN14:true" "FIXED_PWM_POS_EN15:true" \
-"FIXED_PWM_POS_EN16:true" \
-"PWM_NUM:4" \
-"PWM_STRETCH_VALUE1:false" "PWM_STRETCH_VALUE2:false" "PWM_STRETCH_VALUE3:false" "PWM_STRETCH_VALUE4:false" "PWM_STRETCH_VALUE5:false" \
-"PWM_STRETCH_VALUE6:false" "PWM_STRETCH_VALUE7:false" "PWM_STRETCH_VALUE8:false" "PWM_STRETCH_VALUE9:false" "PWM_STRETCH_VALUE10:false" \
-"PWM_STRETCH_VALUE11:false" "PWM_STRETCH_VALUE12:false" "PWM_STRETCH_VALUE13:false" "PWM_STRETCH_VALUE14:false" "PWM_STRETCH_VALUE15:false" \
-"PWM_STRETCH_VALUE16:false" \
-"SEPARATE_PWM_CLK:false" \
-"SHADOW_REG_EN1:false" "SHADOW_REG_EN2:false" "SHADOW_REG_EN3:false" "SHADOW_REG_EN4:false" "SHADOW_REG_EN5:false" \
-"SHADOW_REG_EN6:false" "SHADOW_REG_EN7:false" "SHADOW_REG_EN8:false" "SHADOW_REG_EN9:false" \
-"SHADOW_REG_EN10:false" "SHADOW_REG_EN11:false" "SHADOW_REG_EN12:false" "SHADOW_REG_EN13:false" \
-"SHADOW_REG_EN14:false" "SHADOW_REG_EN15:false" "SHADOW_REG_EN16:false" \
-"TACHINT_ACT_LEVEL:false" \
-"TACH_EDGE1:false" "TACH_EDGE2:false" "TACH_EDGE3:false" "TACH_EDGE4:false" "TACH_EDGE5:false" \
-"TACH_EDGE6:false" "TACH_EDGE7:false" "TACH_EDGE8:false" "TACH_EDGE9:false" "TACH_EDGE10:false" \
-"TACH_EDGE11:false" "TACH_EDGE12:false" "TACH_EDGE13:false" "TACH_EDGE14:false" "TACH_EDGE15:false" \
-"TACH_EDGE16:false" \
-"TACH_NUM:1"} 
-
-sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {} 
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[3:3]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[2:2]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[1:1]"} 
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[0:0]"} 
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:APBslave} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PRESETN} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PCLK} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[0:0]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[3:3]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[2:2]} -port_name {} 
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[1:1]} -port_name {} 
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_2} -new_port_name {PWM_3}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_1} -new_port_name {PWM_2}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_0} -new_port_name {PWM_1}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM} -new_port_name {PWM_0}
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE_PWM
-generate_component -component_name ${sd_name}

script_support/components/CAPE/GPIOS/device-tree-overlay/cape-gpios.dtso

-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-/dts-v1/;
-/plugin/;
-
-&{/} {
-	fabric-bus@40000000 {
-		cape_gpios_p8: gpio@41100000 {
-			compatible = "microchip,core-gpio";
-			reg = <0x0 0x41100000 0x0 0x1000>;
-			clocks = <&fabric_clk3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios=<16>;
-			status = "okay";
-			gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
-			                  "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
-			                  "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
-							  "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
-		};
-
-		cape_gpios_p9: gpio@41200000 {
-			compatible = "microchip,core-gpio";
-			reg = <0x0 0x41200000 0x0 0x1000>;
-			clocks = <&fabric_clk3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios=<21>;
-			status = "okay";
-			gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
-			                  "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
-			                  "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
-			                  "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
-							  "P9_PIN29", "P9_PIN30", "P9_PIN31", "P9_PIN41", 
-							  "P9_PIN42";
-		};
-	};
-};
-
-&gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
-	gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
-					"P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
-					"P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
-					"P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
-					"P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19",
-					"P8_PIN20", "P8_PIN21", "P8_PIN22",	"P8_PIN23", "P8_PIN24",
-					"P8_PIN25", "P8_PIN26", "P8_PIN27", "P8_PIN28", "P8_PIN29",
-					"P8_PIN30",
-					"M2_W_DISABLE1", "M2_W_DISABLE2",
-					"VIO_ENABLE", "SD_DET";
-	status = "okay";
-
-	vio_enable {
-		gpio-hog;
-		gpios = <30 30>;
-		output_high;
-		line-name = "VIO_ENABLE";
-	};
-
-	sd_det {
-		gpio-hog;
-		gpios = <31 31>;
-		input;
-		line-name = "SD_DET";
-	};
-};

script_support/components/CAPE/NONE/constraints/cape.pdc

-set_io -port_name P9_11  \
-    -pin_name B5        \
-    -io_std LVCMOS33  \
-    -fixed true          \
-    -DIRECTION INPUT
-
-set_io -port_name P9_13  \
-    -pin_name D19        \
-    -io_std LVCMOS33  \
-    -fixed true          \
-    -DIRECTION OUTPUT

script_support/components/CAPE/ROBOTICS/device-tree-overlay/robotics-cape.dtso

-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2023 Microchip Technology Inc */
-
-/dts-v1/;
-/plugin/;
-
-&{/chosen} {
-	overlays {
-		ROBOTICS-CAPE-GATEWARE = "Mon Oct  2 18:00:17 2023";
-	};
-};
-
-&{/} {
-
-	fabric-bus@40000000 {
-
-		cape_gpios_p8: gpio@41100000 {
-			compatible = "microchip,core-gpio";
-			reg = <0x0 0x41100000 0x0 0x1000>;
-			clocks = <&fabric_clk3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios=<16>;
-			status = "okay";
-			gpio-line-names = "P8_31", "P8_32", "", "P8_34",
-							  "", "P8_36", "P8_37", "P8_38",
-							  "P8_39", "P8_40", "P8_41", "P8_42",
-							  "P8_43", "P8_44", "P8_45", "P8_46";
-		};
-
-		cape_gpios_p9: gpio@41200000 {
-			compatible = "microchip,core-gpio";
-			reg = <0x0 0x41200000 0x0 0x1000>;
-			clocks = <&fabric_clk3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios=<21>;
-			status = "okay";
-			gpio-line-names = "P9_12", "P9_15", "P9_23", "P9_25", "P9_30",
-							  "P9_41", "P9_13";
-		};
-
-		bone_pwm_1: pwm@41400000 {
-			compatible = "microchip,corepwm-rtl-v4";
-			reg = <0x0 0x41400000 0x0 0xF0>;
-			microchip,sync-update-mask = /bits/ 32 <0>;
-			#pwm-cells = <3>;
-            status = "okay";
-			clocks = <&fabric_clk3>;
-		};
-
-		bone_pwm_2: pwm@41500000 {
-			compatible = "microchip,corepwm-rtl-v4";
-			reg = <0x0 0x41500000 0x0 0xF0>;
-			microchip,sync-update-mask = /bits/ 32 <0>;
-			#pwm-cells = <3>;
-            status = "okay";
-			clocks = <&fabric_clk3>;
-		};
-	};
-};
-

script_support/components/M2/BOARD_TESTS/device-tree-overlay/pcie.dtso

-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-/dts-v1/;
-/plugin/;
-
-
-&{/} {
-	fabric-bus@40000000 {
-		m2_test_gpios: gpio@43000000 {
-			compatible = "microchip,core-gpio";
-			reg = <0x0 0x41100000 0x0 0x1000>;
-			clocks = <&fabric_clk3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios=<16>;
-			status = "okay";
-			gpio-line-names = "M2_PERST0N", "M2_UART_WAKEN", "M2_W_DISABLE1", "M2_W_DISABLE2",
-			                  "M2_CLKREQ0N", "M2_PEWAKEN", "M2_I2C_ALTN";
-		};
-	};
-};

BUILD_BVF_GATEWARE.tcl → sources/FPGA-design/BUILD_BVF_GATEWARE.tcl

@@ -9,11 +9,18 @@
 set libero_release [split [get_libero_version] .]
 
 if {[string compare [lindex $libero_release 0] "2022"] == 0 && [string compare [lindex $libero_release 1] "3"] == 0} {
-    puts "Libero v2022.2 detected."
+    puts "Libero v2022.3 detected."
+} elseif {[string compare [lindex $libero_release 0] "2023"] == 0 && [string compare [lindex $libero_release 1] "2"] == 0} {
+    puts "Libero v2023.2 detected."
+} elseif {[string compare [lindex $libero_release 0] "2024"] == 0 && [string compare [lindex $libero_release 1] "1"] == 0} {
+    puts "Libero v2024.1 detected."
+} elseif {[string compare [lindex $libero_release 0] "2024"] == 0 && [string compare [lindex $libero_release 1] "2"] == 0} {
+    puts "Libero v2024.2 detected."
 } else {
-    error "Incorrect Libero version detected. Please use Libero v2022.2 to run these scripts."
+    error "Incorrect Libero version detected. Please use Libero v2023.2, v2022.3, v2024.1 or v2024.2 to run these scripts."
 }
 
+
 if { [lindex $tcl_platform(os) 0]  == "Windows" } {
     if {[string length [pwd]] < 90} {
         puts "Project path length ok."
@@ -66,6 +73,8 @@ if {[info exists FPE_EXPORT_PATH]} {
     set fpe_export_path $prog_export_path/FlashProExpress
 }
 
+set directc_export_path $prog_export_path/DirectC
+
 if {[info exists TOP_LEVEL_NAME]} {
     set top_level_name $TOP_LEVEL_NAME
 } else {
@@ -111,18 +120,60 @@ if {[info exists PROJECT_LOCATION]} {
 } else {
     set project_dir "$local_dir/$project_name"
 }
+puts "PROJECT_LOCATION: $project_dir"
 
 if {[info exists DESIGN_VERSION]} {
     set gateware_design_version "$DESIGN_VERSION"
 } else {
     set gateware_design_version "1"
 }
+puts "DESIGN_VERSION: $gateware_design_version"
 
 if {[info exists SILICON_SIGNATURE]} {
     set gateware_silicon_signature "$SILICON_SIGNATURE"
 } else {
     set gateware_silicon_signature "bea913b0"
 }
+puts "SILICON_SIGNATURE: $gateware_silicon_signature"
+
+
+################# Board , Die , Package #######################
+
+if {[info exists BOARD]} {
+    set board "$BOARD"
+} else {
+    set board "bvf"
+}
+puts "BOARD: $board"
+
+if {[info exists DIE]} {
+    set die "$DIE"
+} else {
+    set die "MPFS025T"
+}
+puts "DIE: $die"
+
+if {[info exists PACKAGE]} {
+    set package "$PACKAGE"
+} else {
+    set package "FCVG484"
+}
+puts "PACKAGE: $package"
+
+if {[info exists DIE_VOLTAGE]} {
+    set die_voltage "$DIE_VOLTAGE"
+} else {
+    set die_voltage 1.0
+}
+puts "DIE_VOLTAGE: $die_voltage"
+
+if {[info exists PART_RANGE]} {
+    set part_range "$PART_RANGE"
+} else {
+    set part_range "EXT"
+}
+puts "PART_RANGE: $part_range"
+
 
 source ./script_support/additional_configurations/functions.tcl
 
@@ -142,23 +193,28 @@ new_project \
     -linked_files_root_dir_env {} \
     -hdl {VERILOG} \
     -family {PolarFireSoC} \
-    -die {MPFS025T} \
-    -package {FCVG484} \
+    -die $die \
+    -package $package \
+    -die $die \
+    -package $package \
     -speed {STD} \
-    -die_voltage {1.0} \
-    -part_range {EXT} \
+    -die_voltage $die_voltage \
+    -part_range $part_range \
+    -die_voltage $die_voltage \
+    -part_range $part_range \
     -adv_options {IO_DEFT_STD:LVCMOS 1.8V} \
     -adv_options {RESTRICTPROBEPINS:0} \
     -adv_options {RESTRICTSPIPINS:0} \
     -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} \
     -adv_options {TARGETDEVICESFORMIGRATION:MPFS095T;MPFS160T;MPFS095TL;MPFS160TL;} \
-    -adv_options {TEMPR:EXT} \
-    -adv_options {VCCI_1.2_VOLTR:EXT} \
-    -adv_options {VCCI_1.5_VOLTR:EXT} \
-    -adv_options {VCCI_1.8_VOLTR:EXT} \
-    -adv_options {VCCI_2.5_VOLTR:EXT} \
-    -adv_options {VCCI_3.3_VOLTR:EXT} \
-    -adv_options {VOLTR:EXT}
+    -adv_options "TEMPR:$part_range" \
+    -adv_options "VCCI_1.2_VOLTR:$part_range" \
+    -adv_options "VCCI_1.5_VOLTR:$part_range" \
+    -adv_options "VCCI_1.8_VOLTR:$part_range" \
+    -adv_options "VCCI_2.5_VOLTR:$part_range" \
+    -adv_options "VCCI_3.3_VOLTR:$part_range" \
+    -adv_options "VOLTR:$part_range"
+
 
 #
 # // Download required cores
@@ -191,26 +247,31 @@ download_core -vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -location
 #
 # // Generate base design
 #
+safe_source ./script_support/B_V_F_recursive.tcl
 
-source ./script_support/B_V_F_recursive.tcl
+#
+# // Ensure no open-ended AXI4 BIF
+#
+if {[info exists AXI_STOP_CAP]} {
+    safe_source ./script_support/axi_stop_cap.tcl
+}
 
 #
 # // Import I/O constraints
 #
-
 set import_pdc_files "-io_pdc \"./constraints/base_design.pdc\""
 set place_route_pdc_files "-file \"${project_dir}/constraint/io/base_design.pdc\""
 
 import_files \
     -convert_EDN_to_HDL 0 \
-    -io_pdc "${constraint_path}/base_design.pdc" \
-    -fp_pdc "${constraint_path}/NW_PLL.pdc" \
-    -fp_pdc "./script_support/components/SYZYGY/$syzygy_option/constraints/fp/SYZYGY.pdc" \
-    -sdc "${constraint_path}/fic_clocks.sdc" \
-    -io_pdc "./script_support/components/CAPE/$cape_option/constraints/cape.pdc" \
-    -io_pdc "./script_support/components/M2/$m2_option/constraints/M2.pdc" \
-    -io_pdc "./script_support/components/SYZYGY/$syzygy_option/constraints/SYZYGY.pdc" \
-    -io_pdc "./script_support/components/MIPI_CSI/$mipi_csi_option/constraints/MIPI_CSI_INTERFACE.pdc"
+    -io_pdc "${constraint_path}/$board/$die/$package/base_design.pdc" \
+    -fp_pdc "${constraint_path}/$board/$die/$package/NW_PLL.pdc" \
+    -sdc "${constraint_path}/$board/$die/$package/fic_clocks.sdc" \
+    -fp_pdc "./script_support/components/SYZYGY/$syzygy_option/constraints/fp/$board/$die/$package/SYZYGY.pdc" \
+    -io_pdc "./script_support/components/CAPE/$cape_option/constraints/$board/$die/$package/cape.pdc" \
+    -io_pdc "./script_support/components/M2/$m2_option/constraints/$board/$die/$package/M2.pdc" \
+    -io_pdc "./script_support/components/SYZYGY/$syzygy_option/constraints/$board/$die/$package/SYZYGY.pdc" \
+    -io_pdc "./script_support/components/MIPI_CSI/$mipi_csi_option/constraints/$board/$die/$package/MIPI_CSI_INTERFACE.pdc"
 
 #
 # // Associate imported constraints with the design flow
@@ -270,11 +331,12 @@ if !{[info exists ONLY_CREATE_DESIGN]} {
         create_eNVM_config "$local_dir/script_support/components/MSS/ENVM.cfg" "$HSS_IMAGE_PATH"
         run_tool -name {GENERATEPROGRAMMINGDATA}
         configure_envm -cfg_file {script_support/components/MSS/ENVM.cfg}
-        source ./script_support/export_spi_prog_file.tcl
+        safe_source ./script_support/export_fns/export_spi_prog_file.tcl
        configure_spiflash -cfg_file {./script_support/spiflash.cfg} 
         run_tool -name {GENERATEPROGRAMMINGFILE} 
 #       run_tool -name {GENERATE_SPI_FLASH_IMAGE} 
-        source ./script_support/export_flashproexpress.tcl
+        safe_source ./script_support/export_fns/export_flashproexpress.tcl
+        safe_source ./script_support/export_fns/export_directc.tcl
     } else {
         run_tool -name {GENERATEPROGRAMMINGDATA}
         puts "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"

Readme.md → sources/FPGA-design/Readme.md

@@ -2,9 +2,9 @@
 
 ## Description
 
-This repository is used to generate the BeagleV Fire FPGA design. The scripts in this repository concentrate on generating the FPGA digital logic content and generating bitstreams. The complete gateware for the BeagleV Fire also includes a first stage bootloader (HSS) which configures the entire PolarFire SoC device. It is therefore recommended to use the **BeagleV Fire Bitstream Builder** to generate the complete gateware including the HSS for the BeagleV Fire. The BeagleV Fire Bitstream Builder is availabe [here](https://git.beagleboard.org/beaglev-fire/bitstream-builder)
+This repository is used to generate the BeagleV Fire FPGA design. The scripts in this repository concentrate on generating the FPGA digital logic content and generating bitstreams. The complete gateware for the BeagleV Fire also includes a first stage bootloader (HSS) which configures the entire PolarFire SoC device. It is therefore recommended to use the **BeagleV Fire Bitstream Builder** to generate the complete gateware including the HSS for the BeagleV Fire. The BeagleV Fire Bitstream Builder is available [here](https://openbeagle.org/beaglev-fire/bitstream-builder)
 
-**The scripts contained in this repository are only recommended to be used in isolation when modifying the FPGA digital logic.** Otherwise please use the [BeagleV Fire Bitstream Builder](https://git.beagleboard.org/beaglev-fire/bitstream-builder).
+**The scripts contained in this repository are only recommended to be used in isolation when modifying the FPGA digital logic.** Otherwise please use the [BeagleV Fire Bitstream Builder](https://openbeagle.org/beaglev-fire/bitstream-builder).
 
 A set of Libero SoC Tcl scripts are provided to generate the FPGA design using Libero SoC along with device specific I/O constraints.
 
@@ -24,16 +24,16 @@ libero SCRIPT:BUILD_BVF_GATEWARE.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:
 ### Available arguments:
 
 #### ONLY_CREATE_DESIGN
-Stops the FPGA flow before running synthesis. This is useful to inspect the generated FPGA design before running throught the Synthesis/Place and route/Bitstream FPGA flow.
+Stops the FPGA flow before running synthesis. This is useful to inspect the generated FPGA design before running through the Synthesis/Place and route/Bitstream FPGA flow.
 
 #### CAPE_OPTION
-Specifes the build option for the digital logic attached to the cape connectors. Valid values are the directory names in ./script_support/components/CAPE. If you wish to create an alternate build option, add a new directory in ./script_support/components/CAPE using one of the existing ones as template. This is a good place to start if you want to play with FPGA digital logic.
+Specifies the build option for the digital logic attached to the cape connectors. Valid values are the directory names in ./script_support/components/CAPE. If you wish to create an alternate build option, add a new directory in ./script_support/components/CAPE using one of the existing ones as template. This is a good place to start if you want to play with FPGA digital logic.
 
 #### M2_OPTION
-Specifes the build option for the digital logic attached to the M.2 connector. Options are DEFAULT to enable the wi-fi interface or NONE if you do not need wi-fi and want to use the third transceiver on the SYZYGY connector..
+Specifies the build option for the digital logic attached to the M.2 connector. Options are DEFAULT to enable the wi-fi interface or NONE if you do not need wi-fi and want to use the third transceiver on the SYZYGY connector..
 
 #### SYZYGY_OPTION
-Specifes the build option for the digital logic attached to the SYZYGY high speed connector. Valid values are the directory names in ./script_support/components/SYZYGY. If you wish to create an alternate build option, add a new directory in ./script_support/components/SYZYGY using one of the existing ones as template. This is a good place to experiment if you want to use wired communications up to 12.5Gbps.
+Specifies the build option for the digital logic attached to the SYZYGY high speed connector. Valid values are the directory names in ./script_support/components/SYZYGY. If you wish to create an alternate build option, add a new directory in ./script_support/components/SYZYGY using one of the existing ones as template. This is a good place to experiment if you want to use wired communications up to 12.5Gbps.
 
 #### MIPI_CSI_OPTION
 Specifies the build option associated with the camera interface. Valid values are the directory names in ./script_support/components/MIPI_CSI. If you wish to create an alternate build option, add a new directory using one of the existing ones as template.
@@ -48,4 +48,4 @@ Specifies the name of the gateware's top level module. This will also be the nam
 Specifies the location where the programming files will be exported.
 
 #### DESIGN_VERSION
-Used to specfy the FPGA design version which will be included in the programming bitstream. Please note that care must be taken in selecting a version number if you wish to use program the generated gateware from Linux. Version numbers must be different for gateware programming from Linux to be successfull.
+Used to specify the FPGA design version which will be included in the programming bitstream. Please note that care must be taken in selecting a version number if you wish to use program the generated gateware from Linux. Version numbers must be different for gateware programming from Linux to be successful.

sources/FPGA-design/script_support/B_V_F_recursive.tcl

+if {[file isdirectory $local_dir/script_support/components/MSS]} {
+    file delete -force $local_dir/script_support/components/MSS
+}
+file mkdir $local_dir/script_support/components/MSS
+
+set cfg_file [glob -nocomplain $local_dir/../MSS_Configuration/$board/$die/$package/*.cfg]
+exec $mss_config_loc -GENERATE -CONFIGURATION_FILE:$cfg_file -OUTPUT_DIR:$local_dir/script_support/components/MSS
+
+set mss_component_file [glob -nocomplain $local_dir/script_support/components/MSS/*.cxz]
+set mss_component_name [file rootname [file tail $mss_component_file]]
+
+puts "MSS filename: $mss_component_name"
+
+import_mss_component -file $mss_component_file
+::safe_source script_support/hdl_source.tcl
+::safe_source script_support/components/CLOCKS_AND_RESETS/CORERESET_0.tcl
+::safe_source script_support/components/CLOCKS_AND_RESETS/INIT_MONITOR.tcl 
+::safe_source script_support/components/CLOCKS_AND_RESETS/FPGA_CCC_C0.tcl
+::safe_source script_support/components/FIC0_INITIATOR.tcl 
+::safe_source script_support/components/CLOCKS_AND_RESETS/CLK_DIV.tcl 
+::safe_source script_support/components/CLOCKS_AND_RESETS/GLITCHLESS_MUX.tcl 
+::safe_source script_support/components/CLOCKS_AND_RESETS/TRANSMIT_PLL.tcl 
+::safe_source script_support/components/CLOCKS_AND_RESETS/PCIE_REF_CLK.tcl 
+::safe_source script_support/components/FIC3_INITIATOR.tcl
+::safe_source script_support/components/CLOCKS_AND_RESETS/OSCILLATOR_160MHz.tcl
+::safe_source script_support/components/CLOCKS_AND_RESETS/ADC_MCLK_CCC.tcl 
+::safe_source script_support/components/CLOCKS_AND_RESETS/CLOCKS_AND_RESETS.tcl 
+::safe_source script_support/components/IHC_APB.tcl
+::safe_source script_support/components/IHC_SUBSYSTEM.tcl
+::safe_source script_support/components/BVF_RISCV_SUBSYSTEM.tcl
+::safe_source script_support/components/BVF_GATEWARE.tcl 
+set_root -module ${top_level_name}::work
\ No newline at end of file