From c480802b02ea8a9d7304bb469057f3b4ecb200bb Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Mon, 4 Dec 2023 19:21:14 +0000
Subject: [PATCH] Cape: Verilog template: Simplify APB interface.
---
.../CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl | 2 -
.../CAPE/VERILOG_TEMPLATE/HDL/CAPE.v | 14 --
.../VERILOG_TEMPLATE/HDL/apb_ctrl_status.v | 120 +++++++++++-------
3 files changed, 73 insertions(+), 63 deletions(-)
diff --git a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
index 15a49b9..a652488 100644
--- a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
@@ -21,8 +21,6 @@ hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_n
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PWRITE} -core_signal_name {APB_SLAVE_SLAVE_PWRITE}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PRDATA} -core_signal_name {APB_SLAVE_SLAVE_PRDATA}
hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PWDATA} -core_signal_name {APB_SLAVE_SLAVE_PWDATA}
-hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PREADY} -core_signal_name {APB_SLAVE_SLAVE_PREADY}
-hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PSLVERR} -core_signal_name {APB_SLAVE_SLAVE_PSLVERR}
hdl_core_rename_bif -hdl_core_name {CAPE} -current_bif_name {BIF_1} -new_bif_name {APB_TARGET}
#-------------------------------------------------------------------------------
diff --git a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
index bae27cc..88ced63 100644
--- a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
+++ b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
@@ -19,8 +19,6 @@ module CAPE(
PRESETN,
// Outputs
APB_SLAVE_SLAVE_PRDATA,
- APB_SLAVE_SLAVE_PREADY,
- APB_SLAVE_SLAVE_PSLVERR,
GPIO_IN,
INT,
// Inouts
@@ -107,8 +105,6 @@ input PRESETN;
// Output
//--------------------------------------------------------------------
output [31:0] APB_SLAVE_SLAVE_PRDATA;
-output APB_SLAVE_SLAVE_PREADY;
-output APB_SLAVE_SLAVE_PSLVERR;
output [27:0] GPIO_IN;
output [23:0] INT;
//--------------------------------------------------------------------
@@ -185,9 +181,7 @@ inout P9_42;
wire [31:0] apb_ctrl_status_0_control;
wire APB_SLAVE_SLAVE_PENABLE;
wire [31:0] APB_SLAVE_PRDATA;
-wire APB_SLAVE_PREADY;
wire APB_SLAVE_SLAVE_PSEL;
-wire APB_SLAVE_PSLVERR;
wire [31:0] APB_SLAVE_SLAVE_PWDATA;
wire APB_SLAVE_SLAVE_PWRITE;
wire [30:3] GPIO_IN_net_0;
@@ -260,8 +254,6 @@ wire P9_41;
wire P9_42;
wire PCLK;
wire PRESETN;
-wire APB_SLAVE_PREADY_net_0;
-wire APB_SLAVE_PSLVERR_net_0;
wire [31:0] APB_SLAVE_PRDATA_net_0;
wire [27:0] GPIO_IN_net_1;
wire [46:31] GPIO_IN_slice_0;
@@ -305,10 +297,6 @@ assign INT[23:0] = 24'h000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
-assign APB_SLAVE_PREADY_net_0 = APB_SLAVE_PREADY;
-assign APB_SLAVE_SLAVE_PREADY = APB_SLAVE_PREADY_net_0;
-assign APB_SLAVE_PSLVERR_net_0 = APB_SLAVE_PSLVERR;
-assign APB_SLAVE_SLAVE_PSLVERR = APB_SLAVE_PSLVERR_net_0;
assign APB_SLAVE_PRDATA_net_0 = APB_SLAVE_PRDATA;
assign APB_SLAVE_SLAVE_PRDATA[31:0] = APB_SLAVE_PRDATA_net_0;
assign GPIO_IN_net_1 = GPIO_IN_net_0;
@@ -344,8 +332,6 @@ apb_ctrl_status apb_ctrl_status_0(
.pwdata ( APB_SLAVE_SLAVE_PWDATA ),
.status ( apb_ctrl_status_0_control ),
// Outputs
- .pslverr ( APB_SLAVE_PSLVERR ),
- .pready ( APB_SLAVE_PREADY ),
.prdata ( APB_SLAVE_PRDATA ),
.control ( apb_ctrl_status_0_control )
);
diff --git a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/apb_ctrl_status.v b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/apb_ctrl_status.v
index e5cb886..f6e0b08 100644
--- a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/apb_ctrl_status.v
+++ b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/apb_ctrl_status.v
@@ -1,47 +1,73 @@
-
-
-module apb_ctrl_status
- (
- input presetn,
- input pclk,
- input psel,
- input penable,
- input pwrite,
- output pslverr,
- output pready,
- input [7:0] paddr,
- input [31:0] pwdata,
- output [31:0] prdata,
- input [31:0] status,
- output [31:0] control
- );
-
- reg [31:0] control_value;
- reg [31:0] status_value_o;
-
- assign pslverr = 1'b0;
- assign pready = 1'b1;
- assign control = control_value;
-
- assign prdata = ((paddr[7:0] == 8'h20)) ? status_value_o[31:0] : 32'h00000000;
-
- //---------------------------------------------------------------------------
- always @(negedge pclk)
- begin
- if ((psel == 1'b1) & (pwrite == 1'b1) & (penable == 1'b1))
- begin
- case (paddr)
- 8'h00: control_value <= 32'h00000001;
- 8'h10: control_value <= 32'h00000002;
- default: control_value <= 32'h00000000;
- endcase
- end
- end
-
- //---------------------------------------------------------------------------
- always @(negedge pclk)
- begin
- status_value_o <= status;
- end
-
-endmodule
+`timescale 1ns/100ps
+module apb_ctrl_status(
+ input pclk,
+ input presetn,
+ input penable,
+ input psel,
+ input [7:0] paddr,
+ input pwrite,
+ input [31:0] pwdata,
+ output reg [31:0] prdata,
+ output reg [31:0] control,
+ input [31:0] status
+ );
+
+
+ localparam [7:0] STATUS = 8'h20; // READ-ONLY REGISTER
+ localparam [7:0] CONTROL_1 = 8'h10; // READ/WRITE Register
+ localparam [7:0] CONTROL_0 = 8'h00; // READ_ONLY DEADBEEF REGISTER
+
+ reg [31:0] control_value;
+
+ wire rd_enable;
+ wire wr_enable;
+
+ assign wr_enable = (penable && pwrite && psel);
+ assign rd_enable = (!pwrite && psel);
+
+ always@(posedge pclk or negedge presetn)
+ begin
+ if(~presetn)
+ begin
+ prdata <= 'b0;
+ control_value <= 32'h00000000;
+ control <= 32'h00000000;
+ end
+ else
+ begin
+ case(paddr[7:0])
+ STATUS:
+ begin
+ if (rd_enable)
+ begin
+ prdata <= status;
+ end
+ end
+ CONTROL_0:
+ begin
+ if (rd_enable)
+ begin
+ prdata <= 32'hdeadbeef;
+ control <= 32'hdeadbeef;
+ end
+ end
+ CONTROL_1:
+ begin
+ if (rd_enable)
+ begin
+ prdata <= control_value;
+ control <= control_value;
+ end
+ else if (wr_enable)
+ begin
+ control_value <= pwdata;
+ end
+ end
+ default:
+ begin
+ prdata <= 32'b0;
+ end
+ endcase
+ end
+ end
+endmodule
\ No newline at end of file
--
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