From 936bbe030f60bd0a0eb041ce279d11803953b1dc Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Mon, 11 Mar 2024 18:49:39 +0000
Subject: [PATCH] Rename git.beagleboard.org -> openbeagle.org.
---
.gitlab-ci.yml | 2 +-
README.md | 2 +-
build-options/board-tests.yaml | 2 +-
build-options/default.yaml | 2 +-
build-options/minimal.yaml | 2 +-
build-options/robotics.yaml | 2 +-
custom-fpga-design/my_custom_fpga_design.yaml | 2 +-
sources/FPGA-design/Readme.md | 14 +++++++-------
8 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index ac8bf43..506eca0 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -19,7 +19,7 @@ build-job: # This job runs in the build stage, which runs first.
- echo "Cloning the tester and gateware..."
- export
- source ~/Microchip/Microchip-FPGA-Tools-Setup/setup-microchip-tools.sh
- - git clone https://git.beagleboard.org/beaglev-fire/gateware-builds-tester.git
+ - git clone https://openbeagle.org/beaglev-fire/gateware-builds-tester.git
- cd gateware-builds-tester
- git clone $REPO_UNDER_TEST -b $BRANCH_UNDER_TEST
- echo "Building the gateware..."
diff --git a/README.md b/README.md
index 25a4a5b..fb16f27 100644
--- a/README.md
+++ b/README.md
@@ -24,7 +24,7 @@ The following environment variables are required for the bitstream builder to us
- LIBERO_INSTALL_DIR
- LM_LICENSE_FILE
-An example script for setting up the environment is available [here](https://git.beagleboard.org/beaglev-fire/Microchip-FPGA-Tools-Setup).
+An example script for setting up the environment is available [here](https://openbeagle.org/beaglev-fire/Microchip-FPGA-Tools-Setup).
## Usage
diff --git a/build-options/board-tests.yaml b/build-options/board-tests.yaml
index 9c79666..13d99e6 100644
--- a/build-options/board-tests.yaml
+++ b/build-options/board-tests.yaml
@@ -1,7 +1,7 @@
---
HSS:
type: git
- link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
+ link: https://openbeagle.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
diff --git a/build-options/default.yaml b/build-options/default.yaml
index 194ef4c..0ea89bb 100644
--- a/build-options/default.yaml
+++ b/build-options/default.yaml
@@ -1,7 +1,7 @@
---
HSS:
type: git
- link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
+ link: https://openbeagle.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
diff --git a/build-options/minimal.yaml b/build-options/minimal.yaml
index cac091b..60b5c3b 100644
--- a/build-options/minimal.yaml
+++ b/build-options/minimal.yaml
@@ -1,7 +1,7 @@
---
HSS:
type: git
- link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
+ link: https://openbeagle.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
diff --git a/build-options/robotics.yaml b/build-options/robotics.yaml
index badef12..e90b58a 100644
--- a/build-options/robotics.yaml
+++ b/build-options/robotics.yaml
@@ -1,7 +1,7 @@
---
HSS:
type: git
- link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
+ link: https://openbeagle.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
diff --git a/custom-fpga-design/my_custom_fpga_design.yaml b/custom-fpga-design/my_custom_fpga_design.yaml
index cde4a26..6d1eb78 100644
--- a/custom-fpga-design/my_custom_fpga_design.yaml
+++ b/custom-fpga-design/my_custom_fpga_design.yaml
@@ -1,7 +1,7 @@
---
HSS:
type: git
- link: https://git.beagleboard.org/beaglev-fire/hart-software-services.git
+ link: https://openbeagle.org/beaglev-fire/hart-software-services.git
branch: develop-beaglev-fire
board: bvf
gateware:
diff --git a/sources/FPGA-design/Readme.md b/sources/FPGA-design/Readme.md
index 7d8eda0..54b60a3 100644
--- a/sources/FPGA-design/Readme.md
+++ b/sources/FPGA-design/Readme.md
@@ -2,9 +2,9 @@
## Description
-This repository is used to generate the BeagleV Fire FPGA design. The scripts in this repository concentrate on generating the FPGA digital logic content and generating bitstreams. The complete gateware for the BeagleV Fire also includes a first stage bootloader (HSS) which configures the entire PolarFire SoC device. It is therefore recommended to use the **BeagleV Fire Bitstream Builder** to generate the complete gateware including the HSS for the BeagleV Fire. The BeagleV Fire Bitstream Builder is availabe [here](https://git.beagleboard.org/beaglev-fire/bitstream-builder)
+This repository is used to generate the BeagleV Fire FPGA design. The scripts in this repository concentrate on generating the FPGA digital logic content and generating bitstreams. The complete gateware for the BeagleV Fire also includes a first stage bootloader (HSS) which configures the entire PolarFire SoC device. It is therefore recommended to use the **BeagleV Fire Bitstream Builder** to generate the complete gateware including the HSS for the BeagleV Fire. The BeagleV Fire Bitstream Builder is available [here](https://openbeagle.org/beaglev-fire/bitstream-builder)
-**The scripts contained in this repository are only recommended to be used in isolation when modifying the FPGA digital logic.** Otherwise please use the [BeagleV Fire Bitstream Builder](https://git.beagleboard.org/beaglev-fire/bitstream-builder).
+**The scripts contained in this repository are only recommended to be used in isolation when modifying the FPGA digital logic.** Otherwise please use the [BeagleV Fire Bitstream Builder](https://openbeagle.org/beaglev-fire/bitstream-builder).
A set of Libero SoC Tcl scripts are provided to generate the FPGA design using Libero SoC along with device specific I/O constraints.
@@ -24,16 +24,16 @@ libero SCRIPT:BUILD_BVF_GATEWARE.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:
### Available arguments:
#### ONLY_CREATE_DESIGN
-Stops the FPGA flow before running synthesis. This is useful to inspect the generated FPGA design before running throught the Synthesis/Place and route/Bitstream FPGA flow.
+Stops the FPGA flow before running synthesis. This is useful to inspect the generated FPGA design before running through the Synthesis/Place and route/Bitstream FPGA flow.
#### CAPE_OPTION
-Specifes the build option for the digital logic attached to the cape connectors. Valid values are the directory names in ./script_support/components/CAPE. If you wish to create an alternate build option, add a new directory in ./script_support/components/CAPE using one of the existing ones as template. This is a good place to start if you want to play with FPGA digital logic.
+Specifies the build option for the digital logic attached to the cape connectors. Valid values are the directory names in ./script_support/components/CAPE. If you wish to create an alternate build option, add a new directory in ./script_support/components/CAPE using one of the existing ones as template. This is a good place to start if you want to play with FPGA digital logic.
#### M2_OPTION
-Specifes the build option for the digital logic attached to the M.2 connector. Options are DEFAULT to enable the wi-fi interface or NONE if you do not need wi-fi and want to use the third transceiver on the SYZYGY connector..
+Specifies the build option for the digital logic attached to the M.2 connector. Options are DEFAULT to enable the wi-fi interface or NONE if you do not need wi-fi and want to use the third transceiver on the SYZYGY connector..
#### SYZYGY_OPTION
-Specifes the build option for the digital logic attached to the SYZYGY high speed connector. Valid values are the directory names in ./script_support/components/SYZYGY. If you wish to create an alternate build option, add a new directory in ./script_support/components/SYZYGY using one of the existing ones as template. This is a good place to experiment if you want to use wired communications up to 12.5Gbps.
+Specifies the build option for the digital logic attached to the SYZYGY high speed connector. Valid values are the directory names in ./script_support/components/SYZYGY. If you wish to create an alternate build option, add a new directory in ./script_support/components/SYZYGY using one of the existing ones as template. This is a good place to experiment if you want to use wired communications up to 12.5Gbps.
#### MIPI_CSI_OPTION
Specifies the build option associated with the camera interface. Valid values are the directory names in ./script_support/components/MIPI_CSI. If you wish to create an alternate build option, add a new directory using one of the existing ones as template.
@@ -48,4 +48,4 @@ Specifies the name of the gateware's top level module. This will also be the nam
Specifies the location where the programming files will be exported.
#### DESIGN_VERSION
-Used to specfy the FPGA design version which will be included in the programming bitstream. Please note that care must be taken in selecting a version number if you wish to use program the generated gateware from Linux. Version numbers must be different for gateware programming from Linux to be successfull.
+Used to specify the FPGA design version which will be included in the programming bitstream. Please note that care must be taken in selecting a version number if you wish to use program the generated gateware from Linux. Version numbers must be different for gateware programming from Linux to be successful.
--
GitLab