diff --git a/sources/FPGA-design/BUILD_BVF_GATEWARE.tcl b/sources/FPGA-design/BUILD_BVF_GATEWARE.tcl
index e0ac7b7bd9e69c185435db9b22731c9072b61a1f..84ac3beb1457da2378f2a018a5be8dbe73ef8f80 100644
--- a/sources/FPGA-design/BUILD_BVF_GATEWARE.tcl
+++ b/sources/FPGA-design/BUILD_BVF_GATEWARE.tcl
@@ -169,6 +169,7 @@ new_project \
     -adv_options {VCCI_3.3_VOLTR:EXT} \
     -adv_options {VOLTR:EXT}
 
+
 #
 # // Download required cores
 #
@@ -200,13 +201,18 @@ download_core -vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -location
 #
 # // Generate base design
 #
-
 safe_source ./script_support/B_V_F_recursive.tcl
 
 #
-# // Import I/O constraints
+# // Ensure no open-ended AXI4 BIF
 #
+if {[info exists AXI_STOP_CAP]} {
+    safe_source ./script_support/axi_stop_cap.tcl
+}
 
+#
+# // Import I/O constraints
+#
 set import_pdc_files "-io_pdc \"./constraints/base_design.pdc\""
 set place_route_pdc_files "-file \"${project_dir}/constraint/io/base_design.pdc\""
 
diff --git a/sources/FPGA-design/script_support/axi_stop_cap.tcl b/sources/FPGA-design/script_support/axi_stop_cap.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a4f141d8c5d83ba6f3c8db1da665787e958242ee
--- /dev/null
+++ b/sources/FPGA-design/script_support/axi_stop_cap.tcl
@@ -0,0 +1,74 @@
+puts "Running AXI stopper script" 
+
+set workFolder "$project_dir/component/work"
+puts "Workfolder: $workFolder"
+
+set xmlContent ""
+
+set drcFiles [glob -nocomplain "$workFolder/*/*_DRC.xml"]
+
+if {[llength $drcFiles]} {
+    set unconnectedPinsBySD {}
+    
+    foreach xmlFilePath $drcFiles {
+        set sd_name [file tail [file dirname $xmlFilePath]]
+        set xmlFile [open $xmlFilePath r]
+        set fileContent [read $xmlFile]
+        close $xmlFile
+        set xmlLines [split $fileContent "\n"]
+
+        foreach line $xmlLines {
+            if {[string match "*Unconnected bus interface pin*" $line]} {
+                if {[regexp {Unconnected bus interface pin (.+)</detail>} $line match pin]} {
+                    lappend unconnectedPinsBySD [list $sd_name $pin]
+                }
+            }
+        }
+    }
+
+    puts "Unconnected bus interface pins (by SmartDesign):"
+    foreach pinInfo $unconnectedPinsBySD {
+        lassign $pinInfo sd_name pin
+        puts "SmartDesign: $sd_name, Pin: $pin"
+    }
+
+    set basePins {
+        AWREADY
+        WREADY
+        BID
+        BRESP
+        BVALID
+        ARREADY
+        RID
+        RDATA
+        RRESP
+        RLAST
+        RVALID
+        BUSER
+        RUSER
+    }
+
+    foreach pinInfo $unconnectedPinsBySD {
+        lassign $pinInfo sd_name pin
+
+        if {[regexp {(.+):AXI4mslave(\d+)} $pin match baseName slaveNum]} {
+            set slaveName "${baseName}:SLAVE${slaveNum}"
+
+            foreach basePin $basePins {
+                set fullPinName "${slaveName}_${basePin}"
+
+                sd_connect_pins_to_constant -sd_name $sd_name -pin_names $fullPinName -value {GND}
+                puts "Connected: $fullPinName in $sd_name"
+            }
+
+            generate_component -component_name ${sd_name}
+            puts "Generated SmartDesign: $sd_name"
+        }
+    }
+
+    auto_promote_pad_pins -promote_all 1
+    save_project
+
+} else {
+    puts "No _DRC.xml files found."
+}