This change replaces cz-conventional-changelog with cz-commitlint, which
automatically configures Commitizen using our commitlint configuration
file. Currently, we use some manual Javascript magic to load our
Commitizen configuration into commitlint (the opposite of what's
introduced by this change), which can be removed.

With this change, we also move our commitlint configuration into a
new `changelog.yaml` file. This file holds the same data as `.cz.json`
previously did.

Change-Id: I14ff2308f1a0b2b293c2128b28ca2df578ce9c1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

This change simply reorders the `body-max-line-length` and
`header-max-line-length` fields to be in the order that most people
mentally expect. This has no actual function impact.

Change-Id: Ice0db951e4049baaf4de9372255407adc4e3bf66
Signed-off-by: Chris Kay <chris.kay@arm.com>

These fields were not updated accidentally on the v2.6.0 release.

Change-Id: I215105da618ff6f72057eaa40a34ff4b24f7ee36
Signed-off-by: Chris Kay <chris.kay@arm.com>

* changes:
  refactor(st-ddr): move basic tests in a dedicated file
  refactor(st-ddr): reorganize generic and specific elements
  feat(stm32mp1): allow configuration of DDR AXI ports number
  refactor(st-ddr): update parameter array initialization
  feat(st-ddr): add read valid training support
  refactor(stm32mp1): remove the support of calibration result
  fix(st-ddr): correct DDR warnings

* changes:
  docs(allwinner): update SoC list and build options
  docs(allwinner): add SUNXI_SETUP_REGULATORS build option

* changes:
  fix(morello): include errata workaround for 1868343
  fix(errata): workaround for Rainier erratum 1868343

As the UART is already initialized, no need to check for UART clock
or reset in next BL. An issue can appear if the next BL device tree
(e.g HW_CONFIG) doesn't use the same clocks or resets (like SCMI ones).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I044ef2386abe2d3dba5a53c3685440d64ca50a4f

This patch includes the errata workaround for erratum
1868343 for the Morello platform.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: Ifea8148e10946db2276560f90bf2f32bf12b9dcc

Rainier CPU is based on Neoverse N1 R4P0 version which exhibits
the erratum 1868343. This patch inherits the workaround from
neoverse_n1.S file into rainier.S file for erratum 1868343.

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Change-Id: I735595229716a77d26369943086de08384cafa70

* changes:
  feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
  feat(plat/rcar3): modify type for Internal function argument
  feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
  fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53

These basic tests are generic and should be used independently of the
driver, depending on the plaftorm characteristics.

Change-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>

stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32mp_ddr_size moves to the generic side.
stm32mp1_ddr_priv contains platform private data.

stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to
retrieve data from DT. They are located in new generic c/h files in
which stm32mp_ddr_param structure is declared. Platform makefile
is updated.

Adapt driver with this new classification.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I4187376c9fff1a30e7a94407d188391547107997

A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.

Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Force alignment of the size of parameters array with the expected
value by the binding.
The registers dynamic structs are removed as not used in TF-A.

Change-Id: I7a41f355a435f54fbf23f468cca87c7f8f7e69e8
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2

The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.

The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.

This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
  the optional "st,phy-cal"

After this patch the built-in calibration is always executed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159

Replace %d with %u in logs, to avoid warning when
-Wformat-signedness is enabled.
And correct the order of includes.

Change-Id: I7c711a37fc1deceb8853831a8a09ae50422859c9
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

* changes:
  fix(stm32mp1): do not reopen debug features
  refactor(stm32mp1): improve DGBMCU driver
  fix(stm32mp1): set reset pulse duration to 31ms

Refactor the GPIO code to use a small lookup table instead of redundant or
repetitive code.

Signed-off-by: Jona Stubbe <tf-a@jona-stubbe.de>
Change-Id: Icf60385095efc1f506e4215d497b60f90e16edfd
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

The issue was reported by Coverity [1]. The return of the functions
regulator_disable() and regulator_enable() was not checked.
If they fail, this means there is an issue either with PMIC or I2C.
The board should the stop booting with a panic().

[1] https://scan4.scan.coverity.com/reports.htm#v47771/p11439/mergedDefectId=374565



Change-Id: If5dfd5643c210e03ae4b1f4cab0168c0db89f60e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

On closed chips, it is not allowed to open debug. The BSEC debug
register can not be rewritten.
On open chips, the debug is already open, no need to rewrite this
register. This part of code is just removed.
An INFO message is displayed if debug is disabled.
The freeze of the watchdog during debug is also removed.
In case of debug, this must be managed by the software that enables
the debugger.

Change-Id: I19fbd3c487bb1018db30fd599cfa94fe5090899f
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

Add function headers to improve readability.
Add asserts when required.
Use RCC_BASE address.

Change-Id: Ia545293f00167b6276331a986ea7aa08c006e004
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

According to ST Application note AN5256 [1], the minimum reset pulse
duration should be set to 31ms on boards powered with discrete
regulators.

[1] https://www.st.com/resource/en/application_note/dm00561921.pdf



Change-Id: Ib6ed029ee8a4b95f75a80948fdd2154b4ebe484f
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

We don't use mbox drivers which are implemented in these files for
mcdi, so remove related files from mcdi folder.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Idea5ebe5b25f91066ebd653cdcdafe65ca292b0f

The utrd struct is allocated on the stack by ufs_check_resp's caller.
Invalidating the utrd struct is unnecessary since it's only read from,
and can cause other values stored on the stack (e.g. link register) to
be inadvertently invalidated.

Change-Id: Icd455b52beb2677fafc083d68d0bfa0645b7194b
Signed-off-by: Wing Li <wingers@google.com>

Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to the build target names.
Also add some explanation about the recently introduced PSCI power
management providers.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icf5e304562c3082552bf08d7b26904caf9074936

For somewhat historical reasons we are doing some initial PMIC regulator
setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked
fine so far, but there is at least one board (OrangePi 3) that gets upset,
because the Ethernet PHY needs some *coordinated* bringup of *two*
regulators.

To avoid custom hacks, let's introduce a build option to keep doing the
regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break
support for some devices on some boards in U-Boot (Ethernet and HDMI),
but will allow to bring up the OrangePi 3 in Linux correctly. We keep
the default at 1 to not change the behaviour for all other boards.

After U-Boot gained proper PMIC support at some point in the future, we
will probably change the default to 0, to get rid of the less optimal
PMIC code in TF-A.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7

Document the newly introduced SUNXI_SETUP_REGULATORS build option, that
allows to disable PMIC regulator setup at build time.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie5fb0b7220426b67cfffc95df4cabb31a6ec174a

* changes:
  feat(st-sdmmc2): manage cards power cycle
  feat(stm32mp1): register fixed regulator
  feat(st-drivers): introduce fixed regulator driver
  refactor(st): update CPU and VDD voltage get
  refactor(stm32mp1-fdts): update regulator description
  refactor(st-pmic): use regulator framework for DDR init
  feat(st-pmic): register the PMIC to regulator framework
  refactor(st-pmic): split initialize_pmic()
  feat(stm32mp1): add regulator framework compilation
  feat(regulator): add a regulator framework
  feat(stpmic1): add new services
  feat(stpmic1): add USB OTG regulators
  refactor(st-pmic): improve driver usage
  refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean
  refactor(stm32mp1): re-order drivers init