Husky v8 adds the `husky init` subcommand, and v9 changes how it handles
hooks. We no longer need the Husky preamble in our hooks, so update to
the new `init` subcommand and remove the preambles.

Change-Id: I18ea1bbaedbb4213cc04c21413d75c9757ff7986
Signed-off-by: Chris Kay <chris.kay@arm.com>

* changes:
  fix(cpus): workaround for Cortex-A715 erratum 2331818
  fix(cpus): workaround for Cortex-A715 erratum 2420947

GIC600 erratum 2384374 is a Category B erratum. Part 1 is fixed
in this patch, and the Part 1 failure mode is described as
'If the packet to be sent is a SET packet, then a higher priority SET
may not be sent when it should be until an unblocking event occurs.'

This is handled by calling gicv3_apply_errata_wa_2384374() in the
ehf_deactivate_priority() path, so that when EHF restores the priority
to the original priority, the interrupt packet buffered
in the GIC can be sent.

gicv3_apply_errata_wa_2384374() is the workaround for
the Part 2 of erratum 2384374 which flush packets from the GIC buffer
and is being used in this patch.

SDEN can be found here:
https://developer.arm.com/documentation/sden892601/latest/



Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4bb6dcf86c94125cbc574e0dc5119abe43e84731

Cortex-A715 erratum 2331818 is a cat B erratum that applies to
revisions r0p0 and r1p0 and is fixed in r1p1. The workaround is to
set bit[20] of CPUACTLR2_EL1. Setting this bit is expected to have
a negligible performance impact.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2148827/latest



Change-Id: If3b1ed78b145ab6515cdd41135314350ed556381
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

There are some CI configs which apply patch on the fly to test some
unusual test scenarios. After commit c864af98

 there is one patch which
does not apply cleanly into arm_bl31_plat_runtime_setup().

To fix this issue move console flush/switch into the caller of this
function.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I4116044d53bef349a707c977cf26d1df65200045

Cortex-A715 erratum 2420947 is a cat B erratum that applies only
to revision r1p0 and is fixed in r1p1. The workaround is to set
bit[33] of CPUACTLR2_EL1. This will prevent store and store-release
to merge inside the write buffer, and it is not expected to have
much performance impacts.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2148827/latest



Change-Id: I01a71b878cd958e742ff8357f8cdfbfc5625de47
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

* changes:
  feat(drtm): update DRTM version to 1.0
  feat(drtm): update references to DRTM beta0
  feat(drtm): for TPM features fw hash algorithm should be 16-bits
  feat(drtm): add ACPI table region size to the DLME header
  feat(drtm): update return code if secondary PE is not off
  feat(drtm): add additional return codes

* changes:
  chore: rearrange the fvp_cpu_errata.mk file
  fix(cpus): add erratum 2701951 to Cortex-X3's list
  refactor(errata-abi): workaround platforms non-arm interconnect
  refactor(errata-abi): optimize errata ABI using errata framework

Update DRTM version from 0.1 to 1.0.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Ic37fd29e4c2de1a29c2808870addba049d488773

Update all references to DRTM beta0 to be 1.0 instead.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Ieda70f26f3be42f4705e9b267706674c94f120f2

The DRTM 1.0 spec changed the Firmware hash algorithm field
size from 32-bits to 16-bits.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: I713e32e01b1983bf21d97c93bbb28c77dc94a541

The DRTM 1.0 spec defines an additional field in the DLME
header for an optional region in the DLME to hold ACPI tables.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Idba7fa6bd0fb4ef2bdffc24f4588720e1661e58c

DRTM 1.0 specifies that if any secondary PEs are not off
during a dynamic launch the return code must be
SECONDARY_PE_NOT_OFF.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Idcb1f3c60daa63a5bc994bdeacca8aab7066f628

Add additional return codes defined in the DRTM 1.0 spec.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: I1620e098edf4f070ac759a26ce3c7272faf2d8b2

Change-Id: I3959bdf5852c5714f2238f61493a931b3c857a20
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest



Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP flag. The ABI helps assist the
Kernel in the process of mitigation for the following errata:

Cortex-A715:   erratum 2701951
Neoverse V2:   erratum 2719103
Cortex-A710:   erratum 2701952
Cortex-X2:     erratum 2701952
Neoverse N2:   erratum 2728475
Neoverse V1:   erratum 2701953
Cortex-A78:    erratum 2712571
Cortex-A78AE:  erratum 2712574
Cortex-A78C:   erratum 2712575

Change-Id: Ie86b7212d731a79e2a0c07649e69234e733cd78d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structures created by the errata framework.

Change-Id: I1a60d3e4f116b6254fb45426f43ff1b21771af89
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

This change introduces a lazily-evaluated condition on `ENABLE_LTO` to
the `LTO_CFLAGS` variable as opposed to evaluating the condition
eagerly.

This concludes a recent request on the mailing list:

    https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/EU3XR4VB3RP2NQB372QPZ4VRP57ANNLC/



Change-Id: Ie1f73352eb51fb2ceb2385232336312216ef87fc
Signed-off-by: Chris Kay <chris.kay@arm.com>

Add myself as co-maintainer for SynQuacer platform,
as I'm currently working on it.

Change-Id: I149830bf7f635f72df808214e8fd23730fde7212
Signed-off-by: Masahisa Kojima <kojima.masahisa@socionext.com>

* changes:
  refactor(allwinner): console runtime switch on bl31 exit
  refactor(arm): console runtime switch on bl31 exit
  refactor(console): flush before console_switch_state

* changes:
  build(fpga): correctly handle gcc as linker for LTO
  fix(build): enforce single partition for LTO build
  fix(rockchip): add support for building with LTO enabled

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch only affects the Allwinner platform.

Change-Id: I15b4a459a280822a01c60e3b0c856b530db6efab
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

Any BL31 setup and Runtime initialization within BL31 is still part of
the BOOT process. As such, the console flush and switch must be the
last calls before BL31 exit. Flush the console print buffer before
switching to runtime. This is so that there is no lingering chars in
the print buffer when we move to the runtime console.

This patch adds console flush before switching to runtime in
bl31_plat_runtime_setup() function (before BL31 exits). The plan is to
move flush and switch calls to bl31_main before BL31 exits, until then
console_flush() in bl31_main.c has been left as is.

This patch affects the Arm platform only.

Change-Id: I4d367b9e9640686ac15246ad24318ae4685c12c5
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

TF-A plans to move console_flush() and
console_switch_state(CONSOLE_FLAG_RUNTIME) to the end of bl31_main()
before BL31 exits.

Add console_flush() in the generic implementation of
bl31_plat_runtime_setup() call so that platforms can implement or
follow the generic pattern to test this implementation before
console_flush() and console_switch_state() move to bl31_main().

This patch affects the generic implementation of
bl31_plat_runtime_setup()

Change-Id: I92b4176022bfb84558dec5a83386e8ecef49516a
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

* changes:
  style(fwu): change the metadata fields to align with specification
  style(partition): use GUID values for GPT partition fields
  feat(st): add logic to boot the platform from an alternate bank
  feat(st): add a function to clear the FWU trial state counter
  feat(fwu): add a function to obtain an alternate FWU bank to boot
  feat(fwu): add some sanity checks for the FWU metadata
  feat(fwu): modify the check for getting the FWU bank's state
  feat(st): get the state of the active bank directly
  feat(fwu): add a config flag for including image info in the FWU metadata
  feat(fwu): migrate FWU metadata structure to version 2
  feat(fwu): document the config flag for including image info in the FWU metadata
  feat(fwu): update the URL links for the FWU specification

* changes:
  refactor(sgi): replace references to "SGI"/"sgi" for neoverse_rd
  refactor(sgi): rename "CSS_SGI"" macro prefixes to "NRD"
  refactor(sgi): move apis and types to "nrd" prefix
  refactor(sgi): replace build-option prefix to "NRD"
  refactor(sgi): move neoverse_rd out of css
  refactor(sgi): move from "sgi" to "neoverse_rd"
  feat(sgi): remove unused SGI_PLAT build-option
  fix(sgi): align to misra rule for braces
  feat(rde1edge): remove support for RD-E1-Edge
  fix(rdn2): populate TOS_CONFIG only when SPMC_AT_EL3 is enabled
  fix(board): update spi_id max for sgi multichip platforms

Cortex-A715 erratum 2429384 is a cat B erratum that applies to
revision r1p0 and is fixed in r1p1. The workaround is to set
bit[27] of CPUACTLR2_EL1. There is no workaround for revision
r0p0.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2148827/latest



Change-Id: I3cdb1b71567542174759f6946e9c81f77d0d993d
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

* changes:
  feat(smmu): separate out smmuv3_security_init from smmuv3_init
  feat(smmu): fix to perform INV_ALL before enabling GPC

* changes:
  docs(maintainers): add the maintainers for imx8ulp
  docs(imx8ulp): add imx8ulp platform
  fix(imx8ulp): increase the mmap region num
  feat(imx8ulp): adjust the dram mapped region
  feat(imx8ulp): ddrc switch auto low power and software interface
  feat(imx8ulp): add some delay before cmc1 access
  feat(imx8ulp): add a flag check for the ddr status
  fix(imx8ulp): add sw workaround for csi/hotplug test hang
  feat(imx8ulp): adjust the voltage when sys dvfs enabled
  feat(imx8ulp): enable the DDR frequency scaling support
  fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only
  feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID
  feat(imx8ulp): add memory region policy
  feat(imx8ulp): protect TEE region for secure access only
  feat(imx8ulp): add trusty support
  feat(imx8ulp): add OPTEE support
  feat(imx8ulp): update the upower config for power optimization
  feat(imx8ulp): allow RTD to reset APD through MU
  feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD
  feat(imx8ulp): add system power off support
  feat(imx8ulp): add APD power down mode(PD) support in system suspend
  feat(imx8ulp): add the basic support for idle & system suspned
  feat(imx8ulp): enable 512KB cache after resume on imx8ulp
  feat(imx8ulp): add the initial XRDC support
  feat(imx8ulp): allocated caam did for the non secure world
  feat(imx8ulp): add i.MX8ULP basic support
  build(changelog): add new scopes for nxp imx8ulp platform
  feat(scmi): add scmi sensor support