From d9c1795bcf6d8fc1475abd97d6b87c4038abf46d Mon Sep 17 00:00:00 2001
From: Robert Nelson <robertcnelson@gmail.com>
Date: Fri, 18 Nov 2022 17:33:52 -0600
Subject: [PATCH] Add BeagleBoard.org Device Tree Changes
https://git.beagleboard.org/beagleboard/BeagleBoard-DeviceTrees/-/tree/v5.10.x-ti-unified
https://git.beagleboard.org/beagleboard/BeagleBoard-DeviceTrees/-/commit/cbad981e7f6bcdd2fc5dd6e0b757f12ba585c6c1
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm64/boot/dts/ti/Makefile | 2 +
.../k3-j721e-beagleboneai64-bone-buses.dtsi | 1348 +++++++++++++++++
.../k3-j721e-beagleboneai64-no-shared-mem.dts | 1209 +++++++++++++++
.../boot/dts/ti/k3-j721e-beagleboneai64.dts | 1209 +++++++++++++++
.../dts/ti/k3-j721e-common-proc-board.dts | 117 --
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 29 +
.../boot/dts/ti/k3-j721e-rtos-memory-map.dtsi | 12 +-
.../boot/dts/ti/overlays/BB-I2C2-MPU6050.dts | 39 +
.../dts/ti/overlays/BBAI64-CSI0-imx219.dts | 107 ++
.../dts/ti/overlays/BBAI64-CSI1-imx219.dts | 98 ++
.../overlays/BBAI64-DSI-RPi-7inch-panel.dts | 149 ++
.../ti/overlays/BBAI64-P8_37-ehrpwm5_a.dts | 20 +
.../ti/overlays/BBAI64-P9_25-ehrpwm4_b.dts | 20 +
.../boot/dts/ti/overlays/BBORG_LOAD-00A2.dts | 96 ++
.../boot/dts/ti/overlays/BBORG_RELAY-00A2.dts | 54 +
arch/arm64/boot/dts/ti/overlays/BONE-FAN.dts | 139 ++
arch/arm64/boot/dts/ti/overlays/BONE-I2C1.dts | 22 +
arch/arm64/boot/dts/ti/overlays/BONE-I2C2.dts | 22 +
arch/arm64/boot/dts/ti/overlays/BONE-I2C3.dts | 22 +
arch/arm64/boot/dts/ti/overlays/BONE-PWM0.dts | 22 +
arch/arm64/boot/dts/ti/overlays/BONE-PWM1.dts | 22 +
arch/arm64/boot/dts/ti/overlays/BONE-PWM2.dts | 22 +
.../boot/dts/ti/overlays/BONE-SPI0_0.dts | 42 +
.../boot/dts/ti/overlays/BONE-SPI0_1.dts | 42 +
.../arm64/boot/dts/ti/overlays/BONE-UART1.dts | 23 +
.../boot/dts/ti/overlays/BONE-USB0-host.dts | 20 +
.../dts/ti/overlays/J721E-PRU-UIO-00A0.dts | 42 +
arch/arm64/boot/dts/ti/overlays/Makefile | 31 +
...3-j721e-beagleboneai64-RPi-7inch-panel.dts | 149 ++
.../boot/dts/ti/overlays/robotics-cape.dts | 264 ++++
.../dt-bindings/board/am335x-bbw-bbb-base.h | 103 ++
include/dt-bindings/board/am335x-bone-pins.h | 253 ++++
include/dt-bindings/board/am572x-bone-pins.h | 179 +++
.../dt-bindings/board/k3-j721e-bone-pins.h | 242 +++
include/dt-bindings/clock/dra7.h | 4 +
include/dt-bindings/clock/omap5.h | 2 +
include/dt-bindings/pinctrl/omap.h | 4 +-
37 files changed, 6055 insertions(+), 125 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-bone-buses.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-no-shared-mem.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BB-I2C2-MPU6050.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BBAI64-CSI0-imx219.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BBAI64-CSI1-imx219.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BBAI64-DSI-RPi-7inch-panel.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BBAI64-P8_37-ehrpwm5_a.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BBAI64-P9_25-ehrpwm4_b.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BBORG_LOAD-00A2.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BBORG_RELAY-00A2.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-FAN.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-I2C1.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-I2C2.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-I2C3.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-PWM0.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-PWM1.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-PWM2.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-SPI0_0.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-SPI0_1.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-UART1.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/BONE-USB0-host.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/J721E-PRU-UIO-00A0.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/Makefile
create mode 100644 arch/arm64/boot/dts/ti/overlays/k3-j721e-beagleboneai64-RPi-7inch-panel.dts
create mode 100644 arch/arm64/boot/dts/ti/overlays/robotics-cape.dts
create mode 100644 include/dt-bindings/board/am335x-bbw-bbb-base.h
create mode 100644 include/dt-bindings/board/am335x-bone-pins.h
create mode 100644 include/dt-bindings/board/am572x-bone-pins.h
create mode 100644 include/dt-bindings/board/k3-j721e-bone-pins.h
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 457b5275b1e24..072aca03b911c 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -80,3 +80,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-fpdlink-imx390-rcm-1-2.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-fpdlink-imx390-rcm-1-3.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64-no-shared-mem.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-bone-buses.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-bone-buses.dtsi
new file mode 100644
index 0000000000000..da93b812b52aa
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-bone-buses.dtsi
@@ -0,0 +1,1348 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/board/k3-j721e-bone-pins.h>
+
+/********/
+/* LEDs */
+/********/
+&{/} {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+
+ bone_led_P8_03: led_P8_03 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_03 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_04: led_P8_04 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_04 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_05: led_P8_05 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_05 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_06: led_P8_06 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_06 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_07: led_P8_07 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_07 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_08: led_P8_08 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_08 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_09: led_P8_09 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_09 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_10: led_P8_10 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_10 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_11: led_P8_11 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_11 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_12: led_P8_12 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_12 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_13: led_P8_13 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_13 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_14: led_P8_14 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_14 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_15: led_P8_15 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_15 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_16: led_P8_16 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_16 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_17: led_P8_17 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_17 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_18: led_P8_18 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_18 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_19: led_P8_19 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_19 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_20: led_P8_20 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_20 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_21: led_P8_21 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_21 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_22: led_P8_22 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_22 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_23: led_P8_23 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_23 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_24: led_P8_24 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_24 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_25: led_P8_25 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_25 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_26: led_P8_26 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_26 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_27: led_P8_27 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_27 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_28: led_P8_28 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_28 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_29: led_P8_29 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_29 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_30: led_P8_30 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_30 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_31: led_P8_31 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_31 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_32: led_P8_32 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_32 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_33: led_P8_33 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_33 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_34: led_P8_34 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_34 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_35: led_P8_35 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_35 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_36: led_P8_36 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_36 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_37: led_P8_37 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_37 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_38: led_P8_38 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_38 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_39: led_P8_39 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_39 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_40: led_P8_40 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_40 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_41: led_P8_41 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_41 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_42: led_P8_42 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_42 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_43: led_P8_43 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_43 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_44: led_P8_44 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_44 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_45: led_P8_45 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_45 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P8_46: led_P8_46 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_46 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_11: led_P9_11 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_11 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_12: led_P9_12 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_12 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_13: led_P9_13 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_13 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_14: led_P9_14 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_14 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_15: led_P9_15 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_15 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_16: led_P9_16 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_16 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_17: led_P9_17 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_17 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_18: led_P9_18 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_18 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_19: led_P9_19 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_19 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_20: led_P9_20 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_20 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_21: led_P9_21 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_21 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_22: led_P9_22 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_22 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_23: led_P9_23 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_23 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_24: led_P9_24 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_24 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_25: led_P9_25 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_25 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_26: led_P9_26 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_26 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_27: led_P9_27 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_27 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_28: led_P9_28 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_28 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_29: led_P9_29 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_29 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_30: led_P9_30 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_30 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_31: led_P9_31 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_31 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_33: led_P9_33 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_33 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_35: led_P9_35 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_35 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_36: led_P9_36 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_36 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_37: led_P9_37 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_37 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_38: led_P9_38 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_38 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_39: led_P9_39 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_39 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_40: led_P9_40 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_40 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_41: led_P9_41 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_41 GPIO_ACTIVE_HIGH>;
+ };
+
+ bone_led_P9_42: led_P9_42 {
+ status = "disabled";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P9_42 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ /* Dummy driver to request setup for cape header pins */
+ cape_header: pinmux_dummy {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P8_03_default_pin
+ &P8_04_default_pin
+ &P8_05_default_pin
+ &P8_06_default_pin
+ &P8_07_default_pin
+ &P8_08_default_pin
+ &P8_09_default_pin
+ &P8_10_default_pin
+ &P8_11_default_pin
+ &P8_12_default_pin
+ &P8_13_default_pin
+ &P8_14_default_pin
+ &P8_15_default_pin
+ &P8_16_default_pin
+ &P8_17_default_pin
+ &P8_18_default_pin
+ &P8_19_default_pin
+ &P8_20_default_pin
+ &P8_21_default_pin
+ &P8_22_default_pin
+ &P8_23_default_pin
+ &P8_24_default_pin
+ &P8_25_default_pin
+ &P8_26_default_pin
+ &P8_27_default_pin
+ &P8_28_default_pin
+ &P8_29_default_pin
+ &P8_30_default_pin
+ &P8_31_default_pin
+ &P8_32_default_pin
+ &P8_33_default_pin
+ &P8_34_default_pin
+ &P8_35_default_pin
+ &P8_36_default_pin
+ &P8_37_default_pin
+ &P8_38_default_pin
+ &P8_39_default_pin
+ &P8_40_default_pin
+ &P8_41_default_pin
+ &P8_42_default_pin
+ &P8_43_default_pin
+ &P8_44_default_pin
+ &P8_45_default_pin
+ &P8_46_default_pin
+ &P9_11_default_pin
+ &P9_12_default_pin
+ &P9_13_default_pin
+ &P9_14_default_pin
+ &P9_15_default_pin
+ &P9_16_default_pin
+ &P9_17_default_pin
+ &P9_18_default_pin
+ &P9_19_default_pin
+ &P9_20_default_pin
+ &P9_21_default_pin
+ &P9_22_default_pin
+ &P9_23_default_pin
+ &P9_24_default_pin
+ &P9_25_default_pin
+ &P9_26_default_pin
+ &P9_27_default_pin
+ &P9_28_default_pin
+ &P9_29_default_pin
+ &P9_30_default_pin
+ &P9_31_default_pin
+ &P9_33_default_pin
+ &P9_35_default_pin
+ &P9_36_default_pin
+ &P9_37_default_pin
+ &P9_38_default_pin
+ &P9_39_default_pin
+ &P9_40_default_pin
+ &P9_41_default_pin
+ &P9_42_default_pin
+ >;
+ };
+};
+
+
+
+ocp: &main_pmx0 {
+/* macro: BONE_PIN( <pin>, <mode_name>, <register_value_macro(s)> */
+#define BONE_PIN(XX,ZZ,QQ) \
+ XX##_##ZZ##_pin: pinmux_##XX##_##ZZ##_pin { pinctrl-single,pins = < QQ >; };
+
+ /* I2C : https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#I2C */
+ /* i2c6 P9.17 P9.18 */
+ /* i2c2 P9.19 P9.20 */
+ /* i2c4 P9.24 P9.26 */
+
+ /* CAN : https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#CAN */
+ /* mcan0 P9.20 P9.19 */
+ /* mcan4 P9.26 P9.24 */
+ /* mcan5 P8.08 P8.07 */
+
+ /* SPI : https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#SPI */
+ /* spi6 P9.18 P9.21 P9.22 P9.16 P9.23 */
+ /* spi7 P9.30 P9.29 P9.31 P9.29 P9.42 */
+
+ /* UART : https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#UART */
+ /* uart0 P9.13 P9.11 */
+ /* uart2 P9.24 P9.22 */
+ /* uart5 P8.37 P8.38 P8.32 P8.31 */
+
+ /* PWM: https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#PWM */
+ /* ehrpwm1 P9.22 P9.21 */
+ /* ehrpwm2 P9.14 P9.16 */
+ /* ehrpwm0 P8.19 P8.13 */
+
+ /* Full P8/P9 header mode definitions */
+ /* P8_01 - GND */
+ /* P8_02 - GND */
+
+ /* P8_03 (AH21) PRG1_PRU0_GPO19 (gpio0_20) AH21_MCAN6_TX */
+ BONE_PIN(P8_03, default, P8_03(PIN_INPUT, 7))
+ BONE_PIN(P8_03, pruout, P8_03(PIN_OUTPUT, 0)) /* prg1_pru0_gpo19 */
+ BONE_PIN(P8_03, pruin, P8_03(PIN_INPUT, 1)) /* prg1_pru0_gpi19 */
+ BONE_PIN(P8_03, gpio, P8_03(PIN_INPUT, 7))
+ BONE_PIN(P8_03, gpio_pu, P8_03(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_03, gpio_pd, P8_03(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_04 (AC29) PRG0_PRU0_GPO5 (gpio0_48) AC29_SYS_BOOTMODE2 */
+ BONE_PIN(P8_04, default, P8_04(PIN_INPUT, 7))
+ BONE_PIN(P8_04, pruout, P8_04(PIN_OUTPUT, 0)) /* prg0_pru0_gpo5 */
+ BONE_PIN(P8_04, pruin, P8_04(PIN_INPUT, 1)) /* prg0_pru0_gpi5 */
+ BONE_PIN(P8_04, gpio, P8_04(PIN_INPUT, 7))
+ BONE_PIN(P8_04, gpio_pu, P8_04(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_04, gpio_pd, P8_04(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_05 (AH25) PRG1_PRU1_GPO12 (gpio0_33) AH25_MCAN7_TX */
+ BONE_PIN(P8_05, default, P8_05(PIN_INPUT, 7))
+ BONE_PIN(P8_05, pruout, P8_05(PIN_OUTPUT, 0)) /* prg1_pru1_gpo12 */
+ BONE_PIN(P8_05, pruin, P8_05(PIN_INPUT, 1)) /* prg1_pru1_gpi12 */
+ BONE_PIN(P8_05, gpio, P8_05(PIN_INPUT, 7))
+ BONE_PIN(P8_05, gpio_pu, P8_05(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_05, gpio_pd, P8_05(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_06 (AG25) PRG1_PRU1_GPO13 (gpio0_34) AG25_MCAN7_RX */
+ BONE_PIN(P8_06, default, P8_06(PIN_INPUT, 7))
+ BONE_PIN(P8_06, pruout, P8_06(PIN_OUTPUT, 0)) /* prg1_pru1_gpo13 */
+ BONE_PIN(P8_06, pruin, P8_06(PIN_INPUT, 1)) /* prg1_pru1_gpi13 */
+ BONE_PIN(P8_06, gpio, P8_06(PIN_INPUT, 7))
+ BONE_PIN(P8_06, gpio_pu, P8_06(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_06, gpio_pd, P8_06(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_07 (AD24) PRG1_PRU0_GPO14 (gpio0_15) AD24_MCAN5_RX */
+ BONE_PIN(P8_07, default, P8_07(PIN_INPUT, 7))
+ BONE_PIN(P8_07, pruout, P8_07(PIN_OUTPUT, 0)) /* prg1_pru0_gpo14 */
+ BONE_PIN(P8_07, pruin, P8_07(PIN_INPUT, 1)) /* prg1_pru0_gpi14 */
+ BONE_PIN(P8_07, can, P8_07(PIN_INPUT, 6)) /* mcan5_rx */
+ BONE_PIN(P8_07, gpio, P8_07(PIN_INPUT, 7))
+ BONE_PIN(P8_07, gpio_pu, P8_07(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_07, gpio_pd, P8_07(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_08 (AG24) PRG1_PRU0_GPO13 (gpio0_14) AG24_MCAN5_TX */
+ BONE_PIN(P8_08, default, P8_08(PIN_INPUT, 7))
+ BONE_PIN(P8_08, pruout, P8_08(PIN_OUTPUT, 0)) /* prg1_pru0_gpo13 */
+ BONE_PIN(P8_08, pruin, P8_08(PIN_INPUT, 1)) /* prg1_pru0_gpi13 */
+ BONE_PIN(P8_08, can, P8_08(PIN_OUTPUT, 6)) /* mcan5_tx */
+ BONE_PIN(P8_08, gpio, P8_08(PIN_INPUT, 7))
+ BONE_PIN(P8_08, gpio_pu, P8_08(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_08, gpio_pd, P8_08(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_09 (AE24) PRG1_PRU0_GPO16 (gpio0_17) AE24_MCAN6_RX */
+ BONE_PIN(P8_09, default, P8_09(PIN_INPUT, 7))
+ BONE_PIN(P8_09, pruout, P8_09(PIN_OUTPUT, 0)) /* prg1_pru0_gpo16 */
+ BONE_PIN(P8_09, pruin, P8_09(PIN_INPUT, 1)) /* prg1_pru0_gpi16 */
+ BONE_PIN(P8_09, gpio, P8_09(PIN_INPUT, 7))
+ BONE_PIN(P8_09, gpio_pu, P8_09(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_09, gpio_pd, P8_09(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_10 (AC24) PRG1_PRU0_GPO15 (gpio0_16) AC24_MCAN6_TX */
+ BONE_PIN(P8_10, default, P8_10(PIN_INPUT, 7))
+ BONE_PIN(P8_10, pruout, P8_10(PIN_OUTPUT, 0)) /* prg1_pru0_gpo15 */
+ BONE_PIN(P8_10, pruin, P8_10(PIN_INPUT, 1)) /* prg1_pru0_gpi15 */
+ BONE_PIN(P8_10, gpio, P8_10(PIN_INPUT, 7))
+ BONE_PIN(P8_10, gpio_pu, P8_10(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_10, gpio_pd, P8_10(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_11 (AB24) PRG0_PRU0_GPO17 (gpio0_60) AB24_SYS_BOOTMODE7 */
+ BONE_PIN(P8_11, default, P8_11(PIN_INPUT, 7))
+ BONE_PIN(P8_11, pruout, P8_11(PIN_OUTPUT, 0)) /* prg0_pru0_gpo17 */
+ BONE_PIN(P8_11, pruin, P8_11(PIN_INPUT, 1)) /* prg0_pru0_gpi17 */
+ BONE_PIN(P8_11, gpio, P8_11(PIN_INPUT, 7))
+ BONE_PIN(P8_11, gpio_pu, P8_11(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_11, gpio_pd, P8_11(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_12 (AH28) PRG0_PRU0_GPO16 (gpio0_59) AH28_PRG0_PWM0_A2 */
+ BONE_PIN(P8_12, default, P8_12(PIN_INPUT, 7))
+ BONE_PIN(P8_12, pruout, P8_12(PIN_OUTPUT, 0)) /* prg0_pru0_gpo16 */
+ BONE_PIN(P8_12, pruin, P8_12(PIN_INPUT, 1)) /* prg0_pru0_gpi16 */
+ BONE_PIN(P8_12, gpio, P8_12(PIN_INPUT, 7))
+ BONE_PIN(P8_12, gpio_pu, P8_12(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_12, gpio_pd, P8_12(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_13 (V27) RGMII5_TD1 (gpio0_89) V27_EHRPWM0_B */
+ BONE_PIN(P8_13, default, P8_13(PIN_INPUT, 7))
+ BONE_PIN(P8_13, gpio, P8_13(PIN_INPUT, 7))
+ BONE_PIN(P8_13, gpio_pu, P8_13(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_13, gpio_pd, P8_13(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P8_13, pwm, P8_13(PIN_OUTPUT, 6)) /* ehrpwm0_b */
+
+ /* P8_14 (AF27) PRG0_PRU1_GPO12 (gpio0_75) AF27_PRG0_PWM1_A0 */
+ BONE_PIN(P8_14, default, P8_14(PIN_INPUT, 7))
+ BONE_PIN(P8_14, pruout, P8_14(PIN_OUTPUT, 0)) /* prg0_pru1_gpo12 */
+ BONE_PIN(P8_14, pruin, P8_14(PIN_INPUT, 1)) /* prg0_pru1_gpi12 */
+ BONE_PIN(P8_14, gpio, P8_14(PIN_INPUT, 7))
+ BONE_PIN(P8_14, gpio_pu, P8_14(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_14, gpio_pd, P8_14(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_15 (AB29) PRG0_PRU0_GPO18 (gpio0_61) AB29_PRG0_ECAP0_IN_APWM_OUT */
+ BONE_PIN(P8_15, default, P8_15(PIN_INPUT, 7))
+ BONE_PIN(P8_15, pruout, P8_15(PIN_OUTPUT, 0)) /* prg0_pru0_gpo18 */
+ BONE_PIN(P8_15, pruin, P8_15(PIN_INPUT, 1)) /* prg0_pru0_gpi18 */
+ BONE_PIN(P8_15, gpio, P8_15(PIN_INPUT, 7))
+ BONE_PIN(P8_15, gpio_pu, P8_15(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_15, gpio_pd, P8_15(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_16 (AB28) PRG0_PRU0_GPO19 (gpio0_62) AB28_PRG0_PWM0_TZ_OUT */
+ BONE_PIN(P8_16, default, P8_16(PIN_INPUT, 7))
+ BONE_PIN(P8_16, pruout, P8_16(PIN_OUTPUT, 0)) /* prg0_pru0_gpo19 */
+ BONE_PIN(P8_16, pruin, P8_16(PIN_INPUT, 1)) /* prg0_pru0_gpi19 */
+ BONE_PIN(P8_16, gpio, P8_16(PIN_INPUT, 7))
+ BONE_PIN(P8_16, gpio_pu, P8_16(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_16, gpio_pd, P8_16(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_17 (AF22) PRG1_PRU0_GPO2 (gpio0_3) AF22_PRG1_PWM2_A0 */
+ BONE_PIN(P8_17, default, P8_17(PIN_INPUT, 7))
+ BONE_PIN(P8_17, pruout, P8_17(PIN_OUTPUT, 0)) /* prg1_pru0_gpo2 */
+ BONE_PIN(P8_17, pruin, P8_17(PIN_INPUT, 1)) /* prg1_pru0_gpi2 */
+ BONE_PIN(P8_17, gpio, P8_17(PIN_INPUT, 7))
+ BONE_PIN(P8_17, gpio_pu, P8_17(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_17, gpio_pd, P8_17(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_18 (AJ23) PRG1_PRU0_GPO3 (gpio0_4) AJ23_PRG1_PWM3_A2 */
+ BONE_PIN(P8_18, default, P8_18(PIN_INPUT, 7))
+ BONE_PIN(P8_18, pruout, P8_18(PIN_OUTPUT, 0)) /* prg1_pru0_gpo3 */
+ BONE_PIN(P8_18, pruin, P8_18(PIN_INPUT, 1)) /* prg1_pru0_gpi3 */
+ BONE_PIN(P8_18, gpio, P8_18(PIN_INPUT, 7))
+ BONE_PIN(P8_18, gpio_pu, P8_18(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_18, gpio_pd, P8_18(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_19 (V29) RGMII5_TD2 (gpio0_88) V29_EHRPWM0_A */
+ BONE_PIN(P8_19, default, P8_19(PIN_INPUT, 7))
+ BONE_PIN(P8_19, gpio, P8_19(PIN_INPUT, 7))
+ BONE_PIN(P8_19, gpio_pu, P8_19(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_19, gpio_pd, P8_19(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P8_19, pwm, P8_19(PIN_OUTPUT, 6)) /* ehrpwm0_a */
+
+ /* P8_20 (AF26) PRG0_PRU1_GPO13 (gpio0_76) AF26_PRG0_PWM1_B0 */
+ BONE_PIN(P8_20, default, P8_20(PIN_INPUT, 7))
+ BONE_PIN(P8_20, pruout, P8_20(PIN_OUTPUT, 0)) /* prg0_pru1_gpo13 */
+ BONE_PIN(P8_20, pruin, P8_20(PIN_INPUT, 1)) /* prg0_pru1_gpi13 */
+ BONE_PIN(P8_20, gpio, P8_20(PIN_INPUT, 7))
+ BONE_PIN(P8_20, gpio_pu, P8_20(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_20, gpio_pd, P8_20(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_21 (AF21) PRG1_PRU1_GPO9 (gpio0_30) AF21_MCAN8_TX */
+ BONE_PIN(P8_21, default, P8_21(PIN_INPUT, 7))
+ BONE_PIN(P8_21, pruout, P8_21(PIN_OUTPUT, 0)) /* prg1_pru1_gpo9 */
+ BONE_PIN(P8_21, pruin, P8_21(PIN_INPUT, 1)) /* prg1_pru1_gpi9 */
+ BONE_PIN(P8_21, gpio, P8_21(PIN_INPUT, 7))
+ BONE_PIN(P8_21, gpio_pu, P8_21(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_21, gpio_pd, P8_21(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P8_21, spi, P8_21(PIN_OUTPUT, 4)) /* spi6_cs3 */
+
+ /* P8_22 (AH23) PRG1_PRU0_GPO4 (gpio0_5) AH23_UART2_RXD */
+ BONE_PIN(P8_22, default, P8_22(PIN_INPUT, 7))
+ BONE_PIN(P8_22, pruout, P8_22(PIN_OUTPUT, 0)) /* prg1_pru0_gpo4 */
+ BONE_PIN(P8_22, pruin, P8_22(PIN_INPUT, 1)) /* prg1_pru0_gpi4 */
+ BONE_PIN(P8_22, gpio, P8_22(PIN_INPUT, 7))
+ BONE_PIN(P8_22, gpio_pu, P8_22(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_22, gpio_pd, P8_22(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P8_22, uart, P8_22(PIN_INPUT, 14)) /* uart2_rxd */
+
+ /* P8_23 (AB23) PRG1_PRU1_GPO10 (gpio0_31) AB23_MCAN8_RX */
+ BONE_PIN(P8_23, default, P8_23(PIN_INPUT, 7))
+ BONE_PIN(P8_23, pruout, P8_23(PIN_OUTPUT, 0)) /* prg1_pru1_gpo10 */
+ BONE_PIN(P8_23, pruin, P8_23(PIN_INPUT, 1)) /* prg1_pru1_gpi10 */
+ BONE_PIN(P8_23, pruuart, P8_23(PIN_OUTPUT, 2))
+ BONE_PIN(P8_23, gpio, P8_23(PIN_INPUT, 7))
+ BONE_PIN(P8_23, gpio_pu, P8_23(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_23, gpio_pd, P8_23(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_24 (AD20) PRG1_PRU0_GPO5 (gpio0_6) AD20_SYS_BOOTMODE0 */
+ BONE_PIN(P8_24, default, P8_24(PIN_INPUT, 7))
+ BONE_PIN(P8_24, pruout, P8_24(PIN_OUTPUT, 0)) /* prg1_pru0_gpo5 */
+ BONE_PIN(P8_24, pruin, P8_24(PIN_INPUT, 1)) /* prg1_pru0_gpi5 */
+ BONE_PIN(P8_24, gpio, P8_24(PIN_INPUT, 7))
+ BONE_PIN(P8_24, gpio_pu, P8_24(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_24, gpio_pd, P8_24(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_25 (AH26) PRG1_PRU1_GPO14 (gpio0_35) AH26_PRG1_PRU1_GPO14 */
+ BONE_PIN(P8_25, default, P8_25(PIN_INPUT, 7))
+ BONE_PIN(P8_25, pruout, P8_25(PIN_OUTPUT, 0)) /* prg1_pru1_gpo14 */
+ BONE_PIN(P8_25, pruin, P8_25(PIN_INPUT, 1)) /* prg1_pru1_gpi14 */
+ BONE_PIN(P8_25, gpio, P8_25(PIN_INPUT, 7))
+ BONE_PIN(P8_25, gpio_pu, P8_25(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_25, gpio_pd, P8_25(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_26 (AC27) PRG0_PRU0_GPO8 (gpio0_51) AC27_PRG0_PWM2_A1 */
+ BONE_PIN(P8_26, default, P8_26(PIN_INPUT, 7))
+ BONE_PIN(P8_26, pruout, P8_26(PIN_OUTPUT, 0)) /* prg0_pru0_gpo8 */
+ BONE_PIN(P8_26, pruin, P8_26(PIN_INPUT, 1)) /* prg0_pru0_gpi8 */
+ BONE_PIN(P8_26, gpio, P8_26(PIN_INPUT, 7))
+ BONE_PIN(P8_26, gpio_pu, P8_26(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_26, gpio_pd, P8_26(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_27 (AA28) PRG0_PRU1_GPO8 (gpio0_71) AA28_PRG0_PRU1_GPO8 */
+ BONE_PIN(P8_27, default, P8_27(PIN_INPUT, 7))
+ BONE_PIN(P8_27, pruout, P8_27(PIN_OUTPUT, 0)) /* prg0_pru1_gpo8 */
+ BONE_PIN(P8_27, pruin, P8_27(PIN_INPUT, 1)) /* prg0_pru1_gpi8 */
+ BONE_PIN(P8_27, gpio, P8_27(PIN_INPUT, 7))
+ BONE_PIN(P8_27, gpio_pu, P8_27(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_27, gpio_pd, P8_27(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_28 (Y24) PRG0_PRU1_GPO9 (gpio0_72) Y24_PRG0_UART0_RXD */
+ BONE_PIN(P8_28, default, P8_28(PIN_INPUT, 7))
+ BONE_PIN(P8_28, pruout, P8_28(PIN_OUTPUT, 0)) /* prg0_pru1_gpo9 */
+ BONE_PIN(P8_28, pruin, P8_28(PIN_INPUT, 1)) /* prg0_pru1_gpi9 */
+ BONE_PIN(P8_28, gpio, P8_28(PIN_INPUT, 7))
+ BONE_PIN(P8_28, gpio_pu, P8_28(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_28, gpio_pd, P8_28(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_29 (AA25) PRG0_PRU1_GPO10 (gpio0_73) AA25_PRG0_UART0_TXD */
+ BONE_PIN(P8_29, default, P8_29(PIN_INPUT, 7))
+ BONE_PIN(P8_29, pruout, P8_29(PIN_OUTPUT, 0)) /* prg0_pru1_gpo10 */
+ BONE_PIN(P8_29, pruin, P8_29(PIN_INPUT, 1)) /* prg0_pru1_gpi10 */
+ BONE_PIN(P8_29, gpio, P8_29(PIN_INPUT, 7))
+ BONE_PIN(P8_29, gpio_pu, P8_29(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_29, gpio_pd, P8_29(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_30 (AG26) PRG0_PRU1_GPO11 (gpio0_74) AG26_PRG0_PRU1_GPO11 */
+ BONE_PIN(P8_30, default, P8_30(PIN_INPUT, 7))
+ BONE_PIN(P8_30, pruout, P8_30(PIN_OUTPUT, 0)) /* prg0_pru1_gpo11 */
+ BONE_PIN(P8_30, pruin, P8_30(PIN_INPUT, 1)) /* prg0_pru1_gpi11 */
+ BONE_PIN(P8_30, gpio, P8_30(PIN_INPUT, 7))
+ BONE_PIN(P8_30, gpio_pu, P8_30(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_30, gpio_pd, P8_30(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_31 (AJ25/AE29) PRG1_PRU1_GPO11/PRG0_PRU1_GPO0 (gpio0_32/gpio0_63) AJ25_AE29 */
+ BONE_PIN(P8_31, default, P8_31A(PIN_INPUT, 7) P8_31B(PIN_INPUT, 7))
+ BONE_PIN(P8_31, pruout, P8_31A(PIN_OUTPUT, 0) P8_31B(PIN_INPUT, 7))
+ BONE_PIN(P8_31, pruin, P8_31A(PIN_INPUT, 1) P8_31B(PIN_INPUT, 7))
+ BONE_PIN(P8_31, gpio, P8_31A(PIN_INPUT, 7) P8_31B(PIN_INPUT, 7)) /* gpio0_32 */
+ BONE_PIN(P8_31, gpio_pu, P8_31A(PIN_INPUT_PULLUP, 7) P8_31B(PIN_INPUT, 7))
+ BONE_PIN(P8_31, gpio_pd, P8_31A(PIN_INPUT_PULLDOWN, 7) P8_31B(PIN_INPUT, 7))
+ BONE_PIN(P8_31, qep, P8_31A(PIN_INPUT, 9) P8_31B(PIN_INPUT, 7)) /* eqep1_i */
+ BONE_PIN(P8_31, uart, P8_31A(PIN_INPUT, 7) P8_31B(PIN_INPUT, 14)) /* uart5_rxd */
+
+ /* P8_32 (AG21/AD28) PRG1_PRU1_GPO5/PRG0_PRU1_GPO1 (gpio0_26/gpio0_64) AG21_AD28 */
+ BONE_PIN(P8_32, default, P8_32A(PIN_INPUT, 7) P8_32B(PIN_INPUT, 7))
+ BONE_PIN(P8_32, pruout, P8_32A(PIN_OUTPUT, 0) P8_32B(PIN_INPUT, 7))
+ BONE_PIN(P8_32, pruin, P8_32A(PIN_INPUT, 1) P8_32B(PIN_INPUT, 7))
+ BONE_PIN(P8_32, gpio, P8_32A(PIN_INPUT, 7) P8_32B(PIN_INPUT, 7)) /* gpio0_26 */
+ BONE_PIN(P8_32, gpio_pu, P8_32A(PIN_INPUT_PULLUP, 7) P8_32B(PIN_INPUT, 7))
+ BONE_PIN(P8_32, gpio_pd, P8_32A(PIN_INPUT_PULLDOWN, 7) P8_32B(PIN_INPUT, 7))
+ BONE_PIN(P8_32, qep, P8_32A(PIN_INPUT, 9) P8_32B(PIN_INPUT, 7)) /* eqep1_s */
+ BONE_PIN(P8_32, uart, P8_32A(PIN_INPUT, 7) P8_32B(PIN_OUTPUT, 14)) /* uart5_txd */
+
+ /* P8_33 (AH24/AA2) PRG1_PRU1_GPO4/SPI0_CS0 (gpio0_25/gpio0_111) AH24_AA2 */
+ BONE_PIN(P8_33, default, P8_33A(PIN_INPUT, 7) P8_33B(PIN_INPUT, 7))
+ BONE_PIN(P8_33, pruout, P8_33A(PIN_OUTPUT, 0) P8_33B(PIN_INPUT, 7)) /* prg1_pru1_gpo4 */
+ BONE_PIN(P8_33, pruin, P8_33A(PIN_INPUT, 1) P8_33B(PIN_INPUT, 7)) /* prg1_pru1_gpi4 */
+ BONE_PIN(P8_33, gpio, P8_33A(PIN_INPUT, 7) P8_33B(PIN_INPUT, 7)) /* gpio0_25 */
+ BONE_PIN(P8_33, gpio_pu, P8_33A(PIN_INPUT_PULLUP, 7) P8_33B(PIN_INPUT, 7))
+ BONE_PIN(P8_33, gpio_pd, P8_33A(PIN_INPUT_PULLDOWN, 7) P8_33B(PIN_INPUT, 7))
+ BONE_PIN(P8_33, qep, P8_33A(PIN_INPUT, 9) P8_33B(PIN_INPUT, 7)) /* eqep1_b */
+
+ /* P8_34 (AD22) PRG1_PRU0_GPO6 (gpio0_7) AD22_UART2_TXD */
+ BONE_PIN(P8_34, default, P8_34(PIN_INPUT, 7))
+ BONE_PIN(P8_34, pruout, P8_34(PIN_OUTPUT, 0)) /* prg1_pru0_gpo6 */
+ BONE_PIN(P8_34, pruin, P8_34(PIN_INPUT, 1)) /* prg1_pru0_gpi6 */
+ BONE_PIN(P8_34, gpio, P8_34(PIN_INPUT, 7))
+ BONE_PIN(P8_34, gpio_pu, P8_34(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_34, gpio_pd, P8_34(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P8_34, uart, P8_34(PIN_OUTPUT, 14)) /* uart2_txd */
+
+ /* P8_35 (AD23/Y3) PRG1_PRU1_GPO3/SPI1_CS0 (gpio0_24/gpio0_116) AD23_Y3 */
+ BONE_PIN(P8_35, default, P8_35A(PIN_INPUT, 7) P8_35B(PIN_INPUT, 7))
+ BONE_PIN(P8_35, pruout, P8_35A(PIN_OUTPUT, 0) P8_35B(PIN_INPUT, 7)) /* prg1_pru1_gpo3 */
+ BONE_PIN(P8_35, pruin, P8_35A(PIN_INPUT, 1) P8_35B(PIN_INPUT, 7)) /* prg1_pru1_gpi3 */
+ BONE_PIN(P8_35, gpio, P8_35A(PIN_INPUT, 7) P8_35B(PIN_INPUT, 7)) /* gpio0_24 */
+ BONE_PIN(P8_35, gpio_pu, P8_35A(PIN_INPUT_PULLUP, 7) P8_35B(PIN_INPUT, 7))
+ BONE_PIN(P8_35, gpio_pd, P8_35A(PIN_INPUT_PULLDOWN, 7) P8_35B(PIN_INPUT, 7))
+ BONE_PIN(P8_35, qep, P8_35A(PIN_INPUT, 9) P8_35B(PIN_INPUT, 7)) /* eqep1_a */
+ BONE_PIN(P8_35, uart, P8_35A(PIN_INPUT, 7) P8_35B(PIN_INPUT, 3)) /* uart5_rxd */
+
+ /* P8_36 (AE20) PRG1_PRU0_GPO7 (gpio0_8) AE20_MCAN4_TX */
+ BONE_PIN(P8_36, default, P8_36(PIN_INPUT, 7))
+ BONE_PIN(P8_36, pruout, P8_36(PIN_OUTPUT, 0)) /* prg1_pru0_gpo7 */
+ BONE_PIN(P8_36, pruin, P8_36(PIN_INPUT, 1)) /* prg1_pru0_gpi7 */
+ BONE_PIN(P8_36, can, P8_36(PIN_OUTPUT, 6)) /* mcan4_tx */
+ BONE_PIN(P8_36, gpio, P8_36(PIN_INPUT, 7))
+ BONE_PIN(P8_36, gpio_pu, P8_36(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_36, gpio_pd, P8_36(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_37 (Y27/AD21) RGMII6_RD2/PRG1_PRU0_GPO10 (gpio0_106/gpio0_11) Y27_AD21 */
+ BONE_PIN(P8_37, default, P8_37A(PIN_INPUT, 7) P8_37B(PIN_INPUT, 7))
+ BONE_PIN(P8_37, pruout, P8_37A(PIN_INPUT, 7) P8_37B(PIN_OUTPUT, 0)) /* prg1_pru0_gpo10 */
+ BONE_PIN(P8_37, pruin, P8_37A(PIN_INPUT, 7) P8_37B(PIN_INPUT, 1)) /* prg1_pru0_gpi10 */
+ BONE_PIN(P8_37, gpio, P8_37A(PIN_INPUT, 7) P8_37B(PIN_INPUT, 7)) /* gpio0_106 */
+ BONE_PIN(P8_37, gpio_pu, P8_37A(PIN_INPUT_PULLUP, 7) P8_37B(PIN_INPUT, 7))
+ BONE_PIN(P8_37, gpio_pd, P8_37A(PIN_INPUT_PULLDOWN, 7) P8_37B(PIN_INPUT, 7))
+ BONE_PIN(P8_37, pwm, P8_37A(PIN_OUTPUT, 6) P8_37B(PIN_INPUT, 7)) /* ehrpwm5_a */
+ BONE_PIN(P8_37, spi, P8_37A(PIN_INPUT, 7) P8_37B(PIN_OUTPUT, 4)) /* spi6_cs2 */
+ BONE_PIN(P8_37, uart, P8_37A(PIN_OUTPUT, 3) P8_37B(PIN_INPUT, 7)) /* uart5_txd */
+
+ /* P8_38 (AJ20/Y29) PRG1_PRU0_GPO8/RGMII6_RD3 (gpio0_9/gpio0_105) Y29_AJ20 */
+ BONE_PIN(P8_38, default, P8_38A(PIN_INPUT, 7) P8_38B(PIN_INPUT, 7))
+ BONE_PIN(P8_38, pruout, P8_38A(PIN_OUTPUT, 0) P8_38B(PIN_INPUT, 7)) /* prg1_pru0_gpo8 */
+ BONE_PIN(P8_38, pruin, P8_38A(PIN_INPUT, 1) P8_38B(PIN_INPUT, 7)) /* prg1_pru0_gpi8 */
+ BONE_PIN(P8_38, can, P8_38A(PIN_INPUT, 6) P8_38B(PIN_INPUT, 7)) /* mcan4_rx */
+ BONE_PIN(P8_38, gpio, P8_38A(PIN_INPUT, 7) P8_38B(PIN_INPUT, 7)) /* gpio0_9 */
+ BONE_PIN(P8_38, gpio_pu, P8_38A(PIN_INPUT_PULLUP, 7) P8_38B(PIN_INPUT, 7))
+ BONE_PIN(P8_38, gpio_pd, P8_38A(PIN_INPUT_PULLDOWN, 7) P8_38B(PIN_INPUT, 7))
+ BONE_PIN(P8_38, uart, P8_38A(PIN_INPUT, 7) P8_38B(PIN_INPUT, 3)) /* uart5_rxd */
+
+ /* P8_39 (AC26) PRG0_PRU1_GPO6 (gpio0_69) AC26_PRG0_PRU1_GPO6 */
+ BONE_PIN(P8_39, default, P8_39(PIN_INPUT, 7))
+ BONE_PIN(P8_39, pruout, P8_39(PIN_OUTPUT, 0)) /* prg0_pru1_gpo6 */
+ BONE_PIN(P8_39, pruin, P8_39(PIN_INPUT, 1)) /* prg0_pru1_gpi6 */
+ BONE_PIN(P8_39, gpio, P8_39(PIN_INPUT, 7))
+ BONE_PIN(P8_39, gpio_pu, P8_39(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_39, gpio_pd, P8_39(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_40 (AA24) PRG0_PRU1_GPO7 (gpio0_70) AA24_PRG0_PRU1_GPO7 */
+ BONE_PIN(P8_40, default, P8_40(PIN_INPUT, 7))
+ BONE_PIN(P8_40, pruout, P8_40(PIN_OUTPUT, 0)) /* prg0_pru1_gpo7 */
+ BONE_PIN(P8_40, pruin, P8_40(PIN_INPUT, 1)) /* prg0_pru1_gpi7 */
+ BONE_PIN(P8_40, gpio, P8_40(PIN_INPUT, 7))
+ BONE_PIN(P8_40, gpio_pu, P8_40(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_40, gpio_pd, P8_40(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P8_40, uart, P8_40(PIN_OUTPUT, 14)) /* uart2_txd */
+
+ /* P8_41 (AD29) PRG0_PRU1_GPO4 (gpio0_67) AD29_PRG0_PRU1_GPO4 */
+ BONE_PIN(P8_41, default, P8_41(PIN_INPUT, 7))
+ BONE_PIN(P8_41, pruout, P8_41(PIN_OUTPUT, 0)) /* prg0_pru1_gpo4 */
+ BONE_PIN(P8_41, pruin, P8_41(PIN_INPUT, 1)) /* prg0_pru1_gpi4 */
+ BONE_PIN(P8_41, gpio, P8_41(PIN_INPUT, 7))
+ BONE_PIN(P8_41, gpio_pu, P8_41(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_41, gpio_pd, P8_41(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_42 (AB27) PRG0_PRU1_GPO5 (gpio0_68) AB27_SYS_BOOTMODE6 */
+ BONE_PIN(P8_42, default, P8_42(PIN_INPUT, 7))
+ BONE_PIN(P8_42, pruout, P8_42(PIN_OUTPUT, 0)) /* prg0_pru1_gpo5 */
+ BONE_PIN(P8_42, pruin, P8_42(PIN_INPUT, 1)) /* prg0_pru1_gpi5 */
+ BONE_PIN(P8_42, gpio, P8_42(PIN_INPUT, 7))
+ BONE_PIN(P8_42, gpio_pu, P8_42(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_42, gpio_pd, P8_42(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_43 (AD27) PRG0_PRU1_GPO2 (gpio0_65) AD27_PRG0_PRU1_GPO2 */
+ BONE_PIN(P8_43, default, P8_43(PIN_INPUT, 7))
+ BONE_PIN(P8_43, pruout, P8_43(PIN_OUTPUT, 0)) /* prg0_pru1_gpo2 */
+ BONE_PIN(P8_43, pruin, P8_43(PIN_INPUT, 1)) /* prg0_pru1_gpi2 */
+ BONE_PIN(P8_43, gpio, P8_43(PIN_INPUT, 7))
+ BONE_PIN(P8_43, gpio_pu, P8_43(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_43, gpio_pd, P8_43(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_44 (AC25) PRG0_PRU1_GPO3 (gpio0_66) AC25_PRG0_PRU1_GPO3 */
+ BONE_PIN(P8_44, default, P8_44(PIN_INPUT, 7))
+ BONE_PIN(P8_44, pruout, P8_44(PIN_OUTPUT, 0)) /* prg0_pru1_gpo3 */
+ BONE_PIN(P8_44, pruin, P8_44(PIN_INPUT, 1)) /* prg0_pru1_gpi3 */
+ BONE_PIN(P8_44, gpio, P8_44(PIN_INPUT, 7))
+ BONE_PIN(P8_44, gpio_pu, P8_44(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_44, gpio_pd, P8_44(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_45 (AG29) PRG0_PRU1_GPO16 (gpio0_79) AG29_PRG0_PRU1_GPO16 */
+ BONE_PIN(P8_45, default, P8_45(PIN_INPUT, 7))
+ BONE_PIN(P8_45, pruout, P8_45(PIN_OUTPUT, 0)) /* prg0_pru1_gpo16 */
+ BONE_PIN(P8_45, pruin, P8_45(PIN_INPUT, 1)) /* prg0_pru1_gpi16 */
+ BONE_PIN(P8_45, gpio, P8_45(PIN_INPUT, 7))
+ BONE_PIN(P8_45, gpio_pu, P8_45(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_45, gpio_pd, P8_45(PIN_INPUT_PULLDOWN, 7))
+
+ /* P8_46 (Y25) PRG0_PRU1_GPO17 (gpio0_80) Y25_SYS_BOOTMODE3 */
+ BONE_PIN(P8_46, default, P8_46(PIN_INPUT, 7))
+ BONE_PIN(P8_46, pruout, P8_46(PIN_OUTPUT, 0)) /* prg0_pru1_gpo17 */
+ BONE_PIN(P8_46, pruin, P8_46(PIN_INPUT, 1)) /* prg0_pru1_gpi17 */
+ BONE_PIN(P8_46, gpio, P8_46(PIN_INPUT, 7))
+ BONE_PIN(P8_46, gpio_pu, P8_46(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P8_46, gpio_pd, P8_46(PIN_INPUT_PULLDOWN, 7))
+
+ /* Full P9 header mode definitions */
+ /* P9_01 - GND */
+ /* P9_02 - GND */
+ /* P9_03 - VOUT_3V3 */
+ /* P9_04 - VOUT_3V3 */
+ /* P9_05 - VIN */
+ /* P9_06 - VIN */
+ /* P9_07 - VOUT_SYS */
+ /* P9_08 - VOUT_SYS */
+ /* P9_09 - RESET# */
+ /* P9_10 - POWER# */
+
+ /* P9_11 (AC23) PRG1_PRU0_GPO0 (gpio0_1) AC23_UART0_RXD */
+ BONE_PIN(P9_11, default, P9_11(PIN_INPUT, 7))
+ BONE_PIN(P9_11, pruout, P9_11(PIN_OUTPUT, 0)) /* prg1_pru0_gpo0 */
+ BONE_PIN(P9_11, pruin, P9_11(PIN_INPUT, 1)) /* prg1_pru0_gpi0 */
+ BONE_PIN(P9_11, gpio, P9_11(PIN_INPUT, 7))
+ BONE_PIN(P9_11, gpio_pu, P9_11(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_11, gpio_pd, P9_11(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P9_11, uart, P9_11(PIN_INPUT, 14)) /* uart0_rxd */
+
+ /* P9_12 (AE27) PRG0_PRU0_GPO2 (gpio0_45) AE27_MCASP0_ACLKR */
+ BONE_PIN(P9_12, default, P9_12(PIN_INPUT, 7))
+ BONE_PIN(P9_12, pruout, P9_12(PIN_OUTPUT, 0)) /* prg0_pru0_gpo2 */
+ BONE_PIN(P9_12, pruin, P9_12(PIN_INPUT, 1)) /* prg0_pru0_gpi2 */
+ BONE_PIN(P9_12, gpio, P9_12(PIN_INPUT, 7))
+ BONE_PIN(P9_12, gpio_pu, P9_12(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_12, gpio_pd, P9_12(PIN_INPUT_PULLDOWN, 7))
+
+ /* P9_13 (AG22) PRG1_PRU0_GPO1 (gpio0_2) AG22_UART0_TXD */
+ BONE_PIN(P9_13, default, P9_13(PIN_INPUT, 7))
+ BONE_PIN(P9_13, pruout, P9_13(PIN_OUTPUT, 0)) /* prg1_pru0_gpo1 */
+ BONE_PIN(P9_13, pruin, P9_13(PIN_INPUT, 1)) /* prg1_pru0_gpi1 */
+ BONE_PIN(P9_13, gpio, P9_13(PIN_INPUT, 7))
+ BONE_PIN(P9_13, gpio_pu, P9_13(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_13, gpio_pd, P9_13(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P9_13, uart, P9_13(PIN_OUTPUT, 14)) /* uart0_txd */
+
+ /* P9_14 (U27) RGMII5_RD3 (gpio0_93) U27_EHRPWM2_A */
+ BONE_PIN(P9_14, default, P9_14(PIN_INPUT, 7))
+ BONE_PIN(P9_14, gpio, P9_14(PIN_INPUT, 7))
+ BONE_PIN(P9_14, gpio_pu, P9_14(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_14, gpio_pd, P9_14(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P9_14, pwm, P9_14(PIN_OUTPUT, 6)) /* ehrpwm2_a */
+
+ /* P9_15 (AD25) PRG0_PRU0_GPO4 (gpio0_47) AD25_PRG0_PRU0_GPO4 */
+ BONE_PIN(P9_15, default, P9_15(PIN_INPUT, 7))
+ BONE_PIN(P9_15, pruout, P9_15(PIN_OUTPUT, 0)) /* prg0_pru0_gpo4 */
+ BONE_PIN(P9_15, pruin, P9_15(PIN_INPUT, 1)) /* prg0_pru0_gpi4 */
+ BONE_PIN(P9_15, gpio, P9_15(PIN_INPUT, 7))
+ BONE_PIN(P9_15, gpio_pu, P9_15(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_15, gpio_pd, P9_15(PIN_INPUT_PULLDOWN, 7))
+
+ /* P9_16 (U24) RGMII5_RD2 (gpio0_94) U24_EHRPWM2_B */
+ BONE_PIN(P9_16, default, P9_16(PIN_INPUT, 7))
+ BONE_PIN(P9_16, pruout, P9_16(PIN_OUTPUT, 0))
+ BONE_PIN(P9_16, pruin, P9_16(PIN_INPUT, 1))
+ BONE_PIN(P9_16, gpio, P9_16(PIN_INPUT, 7))
+ BONE_PIN(P9_16, gpio_pu, P9_16(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_16, gpio_pd, P9_16(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P9_16, pwm, P9_16(PIN_OUTPUT, 6)) /* ehrpwm2_b */
+
+ /* P9_17 (AC21/AA3) PRG1_PRU1_GPO7/SPI0_D1 (gpio0_28/gpio0_115) AC21_AA3 */
+ BONE_PIN(P9_17, default, P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT, 7))
+ BONE_PIN(P9_17, pruout, P9_17A(PIN_OUTPUT, 0) P9_17B(PIN_INPUT, 7)) /* prg1_pru1_gpo7 */
+ BONE_PIN(P9_17, pruin, P9_17A(PIN_INPUT, 1) P9_17B(PIN_INPUT, 7)) /* prg1_pru1_gpi7 */
+ BONE_PIN(P9_17, gpio, P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT, 7)) /* gpio0_28 */
+ BONE_PIN(P9_17, gpio_pu, P9_17A(PIN_INPUT_PULLUP, 7) P9_17B(PIN_INPUT, 7))
+ BONE_PIN(P9_17, gpio_pd, P9_17A(PIN_INPUT_PULLDOWN, 7) P9_17B(PIN_INPUT, 7))
+ BONE_PIN(P9_17, i2c, P9_17A(PIN_INPUT, 7) P9_17B(PIN_INPUT_PULLUP, 2)) /* i2c6_scl */
+ BONE_PIN(P9_17, spi, P9_17A(PIN_OUTPUT, 4) P9_17B(PIN_INPUT, 7)) /* spi6_cs0 */
+
+ /* P9_18 (AH22/Y2) PRG1_PRU1_GPO19/SPI1_D1 (gpio0_40/gpio0_120) AH22_Y2 */
+ BONE_PIN(P9_18, default, P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT, 7))
+ BONE_PIN(P9_18, pruout, P9_18A(PIN_OUTPUT, 0) P9_18B(PIN_INPUT, 7)) /* prg1_pru1_gpo19 */
+ BONE_PIN(P9_18, pruin, P9_18A(PIN_INPUT, 1) P9_18B(PIN_INPUT, 7)) /* prg1_pru1_gpi19 */
+ BONE_PIN(P9_18, gpio, P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT, 7)) /* gpio0_40 */
+ BONE_PIN(P9_18, gpio_pu, P9_18A(PIN_INPUT_PULLUP, 7) P9_18B(PIN_INPUT, 7))
+ BONE_PIN(P9_18, gpio_pd, P9_18A(PIN_INPUT_PULLDOWN, 7) P9_18B(PIN_INPUT, 7))
+ BONE_PIN(P9_18, i2c, P9_18A(PIN_INPUT, 7) P9_18B(PIN_INPUT_PULLUP, 2)) /* i2c6_sda */
+ BONE_PIN(P9_18, spi, P9_18A(PIN_INPUT, 4) P9_18B(PIN_INPUT, 7)) /* spi6_d1 (tested PIN_INPUT) */
+
+ /* P9_19 (W5/AF29) MCAN0_RX/PRG0_PRU1_GPO15 (gpio1_1/gpio0_78) W5_AF29 */
+ BONE_PIN(P9_19, default, P9_19A(PIN_INPUT, 7) P9_19B(PIN_INPUT, 7))
+ BONE_PIN(P9_19, pruout, P9_19A(PIN_INPUT, 7) P9_19B(PIN_OUTPUT, 0)) /* prg0_pru1_gpo15 */
+ BONE_PIN(P9_19, pruin, P9_19A(PIN_INPUT, 7) P9_19B(PIN_INPUT, 1)) /* prg0_pru1_gpi15 */
+ BONE_PIN(P9_19, can, P9_19A(PIN_INPUT, 0) P9_19B(PIN_INPUT, 7)) /* mcan0_rx */
+ BONE_PIN(P9_19, gpio, P9_19A(PIN_INPUT, 7) P9_19B(PIN_INPUT, 7)) /* gpio1_1 */
+ BONE_PIN(P9_19, gpio_pu, P9_19A(PIN_INPUT_PULLUP, 7) P9_19B(PIN_INPUT, 7))
+ BONE_PIN(P9_19, gpio_pd, P9_19A(PIN_INPUT_PULLDOWN, 7) P9_19B(PIN_INPUT, 7))
+ BONE_PIN(P9_19, i2c, P9_19A(PIN_INPUT_PULLUP, 4) P9_19B(PIN_INPUT, 7)) /* i2c2_scl */
+
+ /* P9_20 (W6/AE25) MCAN0_TX/PRG0_PRU1_GPO14 (gpio1_2/gpio0_77) W6_AE25 */
+ BONE_PIN(P9_20, default, P9_20A(PIN_INPUT, 7) P9_20B(PIN_INPUT, 7))
+ BONE_PIN(P9_20, pruout, P9_20A(PIN_INPUT, 7) P9_20B(PIN_OUTPUT, 0)) /* prg0_pru1_gpo14 */
+ BONE_PIN(P9_20, pruin, P9_20A(PIN_INPUT, 7) P9_20B(PIN_INPUT, 1)) /* prg0_pru1_gpi14 */
+ BONE_PIN(P9_20, can, P9_20A(PIN_OUTPUT, 0) P9_20B(PIN_INPUT, 7)) /* mcan0_tx */
+ BONE_PIN(P9_20, gpio, P9_20A(PIN_INPUT, 7) P9_20B(PIN_INPUT, 7)) /* gpio1_2 */
+ BONE_PIN(P9_20, gpio_pu, P9_20A(PIN_INPUT_PULLUP, 7) P9_20B(PIN_INPUT, 7))
+ BONE_PIN(P9_20, gpio_pd, P9_20A(PIN_INPUT_PULLDOWN, 7) P9_20B(PIN_INPUT, 7))
+ BONE_PIN(P9_20, i2c, P9_20A(PIN_INPUT_PULLUP, 4) P9_20B(PIN_INPUT, 7)) /* i2c2_sda */
+
+ /* P9_21 (AJ22/U28) PRG1_PRU1_GPO18/RGMII5_TD0 (gpio0_39/gpio0_90) AJ22_U28 */
+ BONE_PIN(P9_21, default, P9_21A(PIN_INPUT, 7) P9_21B(PIN_INPUT, 7))
+ BONE_PIN(P9_21, pruout, P9_21A(PIN_OUTPUT, 0) P9_21B(PIN_INPUT, 7)) /* prg1_pru1_gpo18 */
+ BONE_PIN(P9_21, pruin, P9_21A(PIN_INPUT, 1) P9_21B(PIN_INPUT, 7)) /* prg1_pru1_gpi18 */
+ BONE_PIN(P9_21, gpio, P9_21A(PIN_INPUT, 7) P9_21B(PIN_INPUT, 7)) /* gpio0_39 */
+ BONE_PIN(P9_21, gpio_pu, P9_21A(PIN_INPUT_PULLUP, 7) P9_21B(PIN_INPUT, 7))
+ BONE_PIN(P9_21, gpio_pd, P9_21A(PIN_INPUT_PULLDOWN, 7) P9_21B(PIN_INPUT, 7))
+ BONE_PIN(P9_21, pwm, P9_21A(PIN_INPUT, 7) P9_21B(PIN_OUTPUT, 6)) /* ehrpwm1_a */
+ BONE_PIN(P9_21, spi, P9_21A(PIN_OUTPUT, 4) P9_21B(PIN_INPUT, 7)) /* spi6_d0 */
+
+ /* P9_22 (AC22/U29) PRG1_PRU1_GPO17/RGMII5_TXC (gpio0_38/gpio0_91) AC22_U29 */
+ BONE_PIN(P9_22, default, P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT, 7))
+ BONE_PIN(P9_22, pruout, P9_22A(PIN_OUTPUT, 0) P9_22B(PIN_INPUT, 7)) /* prg1_pru1_gpo17 */
+ BONE_PIN(P9_22, pruin, P9_22A(PIN_INPUT, 1) P9_22B(PIN_INPUT, 7)) /* prg1_pru1_gpi17 */
+ BONE_PIN(P9_22, gpio, P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT, 7)) /* gpio0_38 */
+ BONE_PIN(P9_22, gpio_pu, P9_22A(PIN_INPUT_PULLUP, 7) P9_22B(PIN_INPUT, 7))
+ BONE_PIN(P9_22, gpio_pd, P9_22A(PIN_INPUT_PULLDOWN, 7) P9_22B(PIN_INPUT, 7))
+ BONE_PIN(P9_22, i2c, P9_22A(PIN_INPUT, 7) P9_22B(PIN_INPUT_PULLUP, 2)) /* i2c6_scl */
+ BONE_PIN(P9_22, pwm, P9_22A(PIN_INPUT, 7) P9_22B(PIN_OUTPUT, 6)) /* ehrpwm1_b */
+ BONE_PIN(P9_22, spi, P9_22A(PIN_OUTPUT, 4) P9_22B(PIN_INPUT, 7)) /* spi6_clk */
+
+ /* P9_23 (AG20) PRG1_PRU0_GPO9 (gpio0_10) AG20_SPI6_CS1 */
+ BONE_PIN(P9_23, default, P9_23(PIN_INPUT, 7))
+ BONE_PIN(P9_23, pruout, P9_23(PIN_OUTPUT, 0)) /* prg1_pru0_gpo9 */
+ BONE_PIN(P9_23, pruin, P9_23(PIN_INPUT, 1)) /* prg1_pru0_gpi9 */
+ BONE_PIN(P9_23, gpio, P9_23(PIN_INPUT, 7))
+ BONE_PIN(P9_23, gpio_pu, P9_23(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_23, gpio_pd, P9_23(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P9_23, spi, P9_23(PIN_OUTPUT, 4)) /* spi6_cs1 */
+
+ /* P9_24 (Y5/AJ24) SPI1_D0/PRG1_PRU0_GPO12 (gpio0_119/gpio0_13) Y5_AJ24 */
+ BONE_PIN(P9_24, default, P9_24A(PIN_INPUT, 7) P9_24B(PIN_INPUT, 7))
+ BONE_PIN(P9_24, pruout, P9_24A(PIN_INPUT, 7) P9_24B(PIN_OUTPUT, 0)) /* prg1_pru0_gpo12 */
+ BONE_PIN(P9_24, pruin, P9_24A(PIN_INPUT, 7) P9_24B(PIN_INPUT, 1)) /* prg1_pru0_gpi12 */
+ BONE_PIN(P9_24, can, P9_24A(PIN_INPUT, 7) P9_24B(PIN_INPUT, 6) ) /* mcan4_rx */
+ BONE_PIN(P9_24, gpio, P9_24A(PIN_INPUT, 7) P9_24B(PIN_INPUT, 7)) /* gpio0_119 */
+ BONE_PIN(P9_24, gpio_pu, P9_24A(PIN_INPUT_PULLUP, 7) P9_24B(PIN_INPUT, 7))
+ BONE_PIN(P9_24, gpio_pd, P9_24A(PIN_INPUT_PULLDOWN, 7) P9_24B(PIN_INPUT, 7))
+ BONE_PIN(P9_24, i2c, P9_24A(PIN_INPUT_PULLUP, 2) P9_24B(PIN_INPUT, 7)) /* i2c4_scl */
+ BONE_PIN(P9_24, uart, P9_24A(PIN_OUTPUT, 3) P9_24B(PIN_INPUT, 7)) /* uart2_txd */
+
+ /* P9_25 (AC4/W26) UART1_CTSn/RGMII6_RXC (gpio0_127/gpio0_104) AC4_W26 */
+ BONE_PIN(P9_25, default, P9_25A(PIN_INPUT, 7) P9_25B(PIN_INPUT, 7))
+ BONE_PIN(P9_25, gpio, P9_25A(PIN_INPUT, 7) P9_25B(PIN_INPUT, 7)) /* gpio0_127 */
+ BONE_PIN(P9_25, gpio_pu, P9_25A(PIN_INPUT_PULLUP, 7) P9_25B(PIN_INPUT, 7))
+ BONE_PIN(P9_25, gpio_pd, P9_25A(PIN_INPUT_PULLDOWN, 7) P9_25B(PIN_INPUT, 7))
+ BONE_PIN(P9_25, pwm, P9_25A(PIN_INPUT, 7) P9_25B(PIN_OUTPUT, 6)) /* ehrpwm4_b */
+ BONE_PIN(P9_25, qep, P9_25A(PIN_INPUT, 5) P9_25B(PIN_INPUT, 7)) /* eqep0_s */
+
+ /* P9_26 (Y1/AF24) SPI1_CLK/PRG1_PRU0_GPO11 (gpio0_118/gpio0_12) Y1_AF24 */
+ BONE_PIN(P9_26, default, P9_26A(PIN_INPUT, 7) P9_26B(PIN_INPUT, 7))
+ BONE_PIN(P9_26, pruout, P9_26A(PIN_INPUT, 7) P9_26B(PIN_OUTPUT, 0)) /* prg1_pru0_gpo11 */
+ BONE_PIN(P9_26, pruin, P9_26A(PIN_INPUT, 7) P9_26B(PIN_INPUT, 1)) /* prg1_pru0_gpi11 */
+ BONE_PIN(P9_26, can, P9_26A(PIN_INPUT, 7) P9_26B(PIN_OUTPUT, 6) ) /* mcan4_tx */
+ BONE_PIN(P9_26, gpio, P9_26A(PIN_INPUT, 7) P9_26B(PIN_INPUT, 7)) /* gpio0_118 */
+ BONE_PIN(P9_26, gpio_pu, P9_26A(PIN_INPUT_PULLUP, 7) P9_26B(PIN_INPUT, 7))
+ BONE_PIN(P9_26, gpio_pd, P9_26A(PIN_INPUT_PULLDOWN, 7) P9_26B(PIN_INPUT, 7))
+ BONE_PIN(P9_26, i2c, P9_26A(PIN_INPUT_PULLUP, 2) P9_26B(PIN_INPUT, 7)) /* i2c4_sda */
+ BONE_PIN(P9_26, uart, P9_26A(PIN_INPUT, 3) P9_26B(PIN_INPUT, 7)) /* uart2_rxd */
+
+ /* P9_27 (AD26/AB1) PRG0_PRU0_GPO3/UART0_RTSn (gpio0_46/gpio0_124) AD26_AB1 */
+ BONE_PIN(P9_27, default, P9_27A(PIN_INPUT, 7) P9_27B(PIN_INPUT, 7))
+ BONE_PIN(P9_27, pruout, P9_27A(PIN_OUTPUT, 0) P9_27B(PIN_INPUT, 7)) /* prg0_pru0_gpo3 */
+ BONE_PIN(P9_27, pruin, P9_27A(PIN_INPUT, 1) P9_27B(PIN_INPUT, 7)) /* prg0_pru0_gpi3 */
+ BONE_PIN(P9_27, gpio, P9_27A(PIN_INPUT, 7) P9_27B(PIN_INPUT, 7)) /* gpio0_46 */
+ BONE_PIN(P9_27, gpio_pu, P9_27A(PIN_INPUT_PULLUP, 7) P9_27B(PIN_INPUT, 7))
+ BONE_PIN(P9_27, gpio_pd, P9_27A(PIN_INPUT_PULLDOWN, 7) P9_27B(PIN_INPUT, 7))
+ BONE_PIN(P9_27, qep, P9_27A(PIN_INPUT, 7) P9_27B(PIN_INPUT, 5)) /* eqep0_b */
+
+ /* P9_28 (U2/AF28) ECAP0_IN_APWM_OUT/PRG0_PRU0_GPO0 (gpio1_11/gpio0_43) U2_AF28 */
+ BONE_PIN(P9_28, default, P9_28A(PIN_INPUT, 7) P9_28B(PIN_INPUT, 7))
+ BONE_PIN(P9_28, pruout, P9_28A(PIN_INPUT, 7) P9_28B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo0 */
+ BONE_PIN(P9_28, pruin, P9_28A(PIN_INPUT, 7) P9_28B(PIN_INPUT, 1)) /* prg0_pru0_gpi0 */
+ BONE_PIN(P9_28, gpio, P9_28A(PIN_INPUT, 7) P9_28B(PIN_INPUT, 7)) /* gpio1_11 */
+ BONE_PIN(P9_28, gpio_pu, P9_28A(PIN_INPUT_PULLUP, 7) P9_28B(PIN_INPUT, 7))
+ BONE_PIN(P9_28, gpio_pd, P9_28A(PIN_INPUT_PULLDOWN, 7) P9_28B(PIN_INPUT, 7))
+ BONE_PIN(P9_28, spi, P9_28A(PIN_OUTPUT, 6) P9_28B(PIN_INPUT, 7)) /* spi7_cs0 */
+
+ /* P9_29 (V5/AB25) TIMER_IO1/PRG0_PRU0_GPO10 (gpio1_14/gpio0_53) V5_AB25 */
+ BONE_PIN(P9_29, default, P9_29A(PIN_INPUT, 7) P9_29B(PIN_INPUT, 7))
+ BONE_PIN(P9_29, pruout, P9_29A(PIN_INPUT, 7) P9_29B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo10 */
+ BONE_PIN(P9_29, pruin, P9_29A(PIN_INPUT, 7) P9_29B(PIN_INPUT, 1)) /* prg0_pru0_gpi10 */
+ BONE_PIN(P9_29, gpio, P9_29A(PIN_INPUT, 7) P9_29B(PIN_INPUT, 7)) /* gpio1_14 */
+ BONE_PIN(P9_29, gpio_pu, P9_29A(PIN_INPUT_PULLUP, 7) P9_29B(PIN_INPUT, 7))
+ BONE_PIN(P9_29, gpio_pd, P9_29A(PIN_INPUT_PULLDOWN, 7) P9_29B(PIN_INPUT, 7))
+ BONE_PIN(P9_29, spi, P9_29A(PIN_OUTPUT, 6) P9_29B(PIN_INPUT, 7)) /* spi7_d1 */
+
+ /* P9_30 (V6/AE28) TIMER_IO0/PRG0_PRU0_GPO1 (gpio1_13/gpio0_44) V6_AE28 */
+ BONE_PIN(P9_30, default, P9_30A(PIN_INPUT, 7) P9_30B(PIN_INPUT, 7))
+ BONE_PIN(P9_30, pruout, P9_30A(PIN_INPUT, 7) P9_30B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo1 */
+ BONE_PIN(P9_30, pruin, P9_30A(PIN_INPUT, 7) P9_30B(PIN_INPUT, 1)) /* prg0_pru0_gpi1 */
+ BONE_PIN(P9_30, gpio, P9_30A(PIN_INPUT, 7) P9_30B(PIN_INPUT, 7)) /* gpio1_13 */
+ BONE_PIN(P9_30, gpio_pu, P9_30A(PIN_INPUT_PULLUP, 7) P9_30B(PIN_INPUT, 7))
+ BONE_PIN(P9_30, gpio_pd, P9_30A(PIN_INPUT_PULLDOWN, 7) P9_30B(PIN_INPUT, 7))
+ BONE_PIN(P9_30, spi, P9_30A(PIN_OUTPUT, 6) P9_30B(PIN_INPUT, 7)) /* spi7_d0 */
+
+ /* P9_31 (U3/AB26) EXT_REFCLK1/PRG0_PRU0_GPO9 (gpio1_12/gpio0_52) U3_AB26 */
+ BONE_PIN(P9_31, default, P9_31A(PIN_INPUT, 7) P9_31B(PIN_INPUT, 7))
+ BONE_PIN(P9_31, pruout, P9_31A(PIN_INPUT, 7) P9_31B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo9 */
+ BONE_PIN(P9_31, pruin, P9_31A(PIN_INPUT, 7) P9_31B(PIN_INPUT, 1)) /* prg0_pru0_gpi9 */
+ BONE_PIN(P9_31, gpio, P9_31A(PIN_INPUT, 7) P9_31B(PIN_INPUT, 7)) /* gpio1_12 */
+ BONE_PIN(P9_31, gpio_pu, P9_31A(PIN_INPUT_PULLUP, 7) P9_31B(PIN_INPUT, 7))
+ BONE_PIN(P9_31, gpio_pd, P9_31A(PIN_INPUT_PULLDOWN, 7) P9_31B(PIN_INPUT, 7))
+ BONE_PIN(P9_31, spi, P9_31A(PIN_OUTPUT, 6) P9_31B(PIN_INPUT, 7)) /* spi7_clk */
+
+ /* P9_32 - ADC_REF_OUT */
+
+ /* P9_33 (K24/AC28) MCU_ADC0_AIN4/PRG0_PRU0_GPO7 (gpio0_50) K24_AC28 */
+ BONE_PIN(P9_33, default, P9_33B(PIN_INPUT, 7))
+ BONE_PIN(P9_33, pruout, P9_33B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo7 */
+ BONE_PIN(P9_33, pruin, P9_33B(PIN_INPUT, 1)) /* prg0_pru0_gpi7 */
+ BONE_PIN(P9_33, gpio, P9_33B(PIN_INPUT, 7))
+ BONE_PIN(P9_33, gpio_pu, P9_33B(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_33, gpio_pd, P9_33B(PIN_INPUT_PULLDOWN, 7))
+
+ /* P9_34 - ADC_GND */
+
+ /* P9_35 (K29/AH27) MCU_ADC0_AIN6/PRG0_PRU0_GPO12 (gpio0_55) K29_AH27 */
+ BONE_PIN(P9_35, default, P9_35B(PIN_INPUT, 7))
+ BONE_PIN(P9_35, pruout, P9_35B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo12 */
+ BONE_PIN(P9_35, pruin, P9_35B(PIN_INPUT, 1)) /* prg0_pru0_gpi12 */
+ BONE_PIN(P9_35, gpio, P9_35B(PIN_INPUT, 7))
+ BONE_PIN(P9_35, gpio_pu, P9_35B(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_35, gpio_pd, P9_35B(PIN_INPUT_PULLDOWN, 7))
+
+ /* P9_36 (K27/AH29) MCU_ADC0_AIN5/PRG0_PRU0_GPO13 (gpio0_56) K27_AH29 */
+ BONE_PIN(P9_36, default, P9_36B(PIN_INPUT, 7))
+ BONE_PIN(P9_36, pruout, P9_36B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo13 */
+ BONE_PIN(P9_36, pruin, P9_36B(PIN_INPUT, 1)) /* prg0_pru0_gpi13 */
+ BONE_PIN(P9_36, gpio, P9_36B(PIN_INPUT, 7))
+ BONE_PIN(P9_36, gpio_pu, P9_36B(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_36, gpio_pd, P9_36B(PIN_INPUT_PULLDOWN, 7))
+
+ /* P9_37 (K28/AG28) MCU_ADC0_AIN2/PRG0_PRU0_GPO14 (gpio0_57) K28_AG28 */
+ BONE_PIN(P9_37, default, P9_37B(PIN_INPUT, 7))
+ BONE_PIN(P9_37, pruout, P9_37B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo14 */
+ BONE_PIN(P9_37, pruin, P9_37B(PIN_INPUT, 1)) /* prg0_pru0_gpi14 */
+ BONE_PIN(P9_37, gpio, P9_37B(PIN_INPUT, 7))
+ BONE_PIN(P9_37, gpio_pu, P9_37B(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_37, gpio_pd, P9_37B(PIN_INPUT_PULLDOWN, 7))
+
+ /* P9_38 (L28/AG27) MCU_ADC0_AIN3/PRG0_PRU0_GPO15 (gpio0_58) L28_AG27 */
+ BONE_PIN(P9_38, default, P9_38B(PIN_INPUT, 7))
+ BONE_PIN(P9_38, pruout, P9_38B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo15 */
+ BONE_PIN(P9_38, pruin, P9_38B(PIN_INPUT, 1)) /* prg0_pru0_gpi15 */
+ BONE_PIN(P9_38, gpio, P9_38B(PIN_INPUT, 7))
+ BONE_PIN(P9_38, gpio_pu, P9_38B(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_38, gpio_pd, P9_38B(PIN_INPUT_PULLDOWN, 7))
+
+ /* P9_39 (K25/AJ28) MCU_ADC0_AIN0/PRG0_PRU0_GPO11 (gpio0_54) K25_AJ28 */
+ BONE_PIN(P9_39, default, P9_39B(PIN_INPUT, 7))
+ BONE_PIN(P9_39, pruout, P9_39B(PIN_OUTPUT, 0)) /* prg0_pru0_gpo11 */
+ BONE_PIN(P9_39, pruin, P9_39B(PIN_INPUT, 1)) /* prg0_pru0_gpi11 */
+ BONE_PIN(P9_39, gpio, P9_39B(PIN_INPUT, 7))
+ BONE_PIN(P9_39, gpio_pu, P9_39B(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_39, gpio_pd, P9_39B(PIN_INPUT_PULLDOWN, 7))
+
+ /* P9_40 (K26/AA26) MCU_ADC0_AIN1/PRG0_PRU1_GPO18 (gpio0_81) K26_AA26 */
+ BONE_PIN(P9_40, default, P9_40B(PIN_INPUT, 7))
+ BONE_PIN(P9_40, pruout, P9_40B(PIN_OUTPUT, 0)) /* prg0_pru1_gpo18 */
+ BONE_PIN(P9_40, pruin, P9_40B(PIN_INPUT, 1)) /* prg0_pru1_gpi18 */
+ BONE_PIN(P9_40, gpio, P9_40B(PIN_INPUT, 7))
+ BONE_PIN(P9_40, gpio_pu, P9_40B(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_40, gpio_pd, P9_40B(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P9_40, uart, P9_40B(PIN_INPUT, 14)) /* uart2_rxd */
+
+ /* P9_41 (AD5) UART1_RTSn (gpio1_0) AD5_EQEP0_I */
+ BONE_PIN(P9_41, default, P9_41(PIN_INPUT, 7))
+ BONE_PIN(P9_41, pruout, P9_41(PIN_OUTPUT, 0))
+ BONE_PIN(P9_41, pruin, P9_41(PIN_INPUT, 1))
+ BONE_PIN(P9_41, gpio, P9_41(PIN_INPUT, 7))
+ BONE_PIN(P9_41, gpio_pu, P9_41(PIN_INPUT_PULLUP, 7))
+ BONE_PIN(P9_41, gpio_pd, P9_41(PIN_INPUT_PULLDOWN, 7))
+ BONE_PIN(P9_41, qep, P9_41(PIN_INPUT, 5)) /* eqep0_i */
+
+ /* P9_42 (AC2/AJ21) UART0_CTSn/PRG1_PRU0_GPO17 (gpio0_123/gpio0_18) AC2_AJ21 */
+ BONE_PIN(P9_42, default, P9_42A(PIN_INPUT, 7) P9_42B(PIN_INPUT, 7))
+ BONE_PIN(P9_42, pruout, P9_42A(PIN_INPUT, 7) P9_42B(PIN_OUTPUT, 0)) /* prg1_pru0_gpo17 */
+ BONE_PIN(P9_42, pruin, P9_42A(PIN_INPUT, 7) P9_42B(PIN_INPUT, 1)) /* prg1_pru0_gpi17 */
+ BONE_PIN(P9_42, can, P9_42A(PIN_INPUT, 7) P9_42B(PIN_OUTPUT, 6) ) /* mcan5_tx */
+ BONE_PIN(P9_42, gpio, P9_42A(PIN_INPUT, 7) P9_42B(PIN_INPUT, 7)) /* gpio0_123 */
+ BONE_PIN(P9_42, gpio_pu, P9_42A(PIN_INPUT_PULLUP, 7) P9_42B(PIN_INPUT, 7))
+ BONE_PIN(P9_42, gpio_pd, P9_42A(PIN_INPUT_PULLDOWN, 7) P9_42B(PIN_INPUT, 7))
+ BONE_PIN(P9_42, qep, P9_42A(PIN_INPUT, 5) P9_42B(PIN_INPUT, 7)) /* eqep0_a */
+
+ /* P9_43 - GND */
+ /* P9_44 - GND */
+ /* P9_45 - GND */
+ /* P9_46 - GND */
+};
+
+bone_i2c_1: &main_i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_18_i2c_pin /* i2c6_sda */
+ &P9_17_i2c_pin /* i2c6_scl */
+ >;
+ clock-frequency = <100000>;
+
+ symlink = "bone/i2c/1";
+ status = "disabled";
+};
+
+bone_i2c_2: &main_i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_20_i2c_pin /* i2c2_sda */
+ &P9_19_i2c_pin /* i2c2_scl */
+ >;
+ clock-frequency = <100000>;
+
+ symlink = "bone/i2c/2";
+ status = "disabled";
+};
+
+bone_i2c_3: &main_i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_26_i2c_pin /* i2c4_sda */
+ &P9_24_i2c_pin /* i2c4_scl */
+ >;
+ clock-frequency = <100000>;
+
+ symlink = "bone/i2c/3";
+ status = "disabled";
+};
+
+bone_pwm_0: &main_ehrpwm1 {
+ // location: /dev/bone/pwm/0
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_21_pwm_pin /* ehrpwm1_a */
+ &P9_22_pwm_pin /* ehrpwm1_b */
+ >;
+ status = "disabled";
+};
+
+bone_pwm_1: &main_ehrpwm2 {
+ // location: /dev/bone/pwm/1
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_14_pwm_pin /* ehrpwm2_a */
+ &P9_16_pwm_pin /* ehrpwm2_b */
+ >;
+ status = "disabled";
+};
+
+bone_pwm_2: &main_ehrpwm0 {
+ // location: /dev/bone/pwm/2
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P8_19_pwm_pin /* ehrpwm0_a */
+ &P8_13_pwm_pin /* ehrpwm0_b */
+ >;
+ status = "disabled";
+};
+
+&main_ehrpwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_25_pwm_pin /* ehrpwm4_b */
+ >;
+ status = "disabled";
+};
+
+&main_ehrpwm5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P8_37_pwm_pin /* ehrpwm5_a */
+ >;
+ status = "disabled";
+};
+
+bone_spi_0: &main_spi6 {
+};
+
+bone_uart_0: &main_uart0 {
+ /* TODO: also has option as "bone/uart/4" */
+ symlink = "bone/uart/0";
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+bone_uart_1: &main_uart2 {
+ /* tested with sudo agetty 115200 ttyS4 */
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_24_uart_pin /* uart2_txd */
+ &P9_26_uart_pin /* uart2_rxd */
+ >;
+ symlink = "bone/uart/1";
+ status = "disabled";
+};
+
+bone_uart_5: &main_uart5 {
+ symlink = "bone/uart/5";
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-no-shared-mem.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-no-shared-mem.dts
new file mode 100644
index 0000000000000..6d3b2ca91c7c0
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64-no-shared-mem.dts
@@ -0,0 +1,1209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+
+#include "k3-j721e-som-p0.dtsi"
+//#include "k3-j721e-rtos-memory-map.dtsi"
+#include "k3-j721e-beagleboneai64-bone-buses.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/board/k3-j721e-bone-pins.h>
+
+/ {
+ compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
+ model = "BeagleBoard.org BeagleBone AI-64";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ base_dtb = "k3-j721e-beagleboneai64.dts";
+ base_dtb_timestamp = __TIMESTAMP__;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_pwr_pins_default>;
+
+ button-1 {
+ label = "BOOT";
+ linux,code = <BTN_0>;
+ gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ button-2 {
+ label = "POWER";
+ linux,code = <KEY_POWER>;
+ gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_default>;
+
+ led-0 {
+ label = "beaglebone:green:usr0";
+ gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ };
+
+ led-1 {
+ label = "beaglebone:green:usr1";
+ gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ };
+
+ led-2 {
+ label = "beaglebone:green:usr2";
+ gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu";
+ function = LED_FUNCTION_CPU;
+ };
+
+ led-3 {
+ label = "beaglebone:green:usr3";
+ gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ };
+
+ led-4 {
+ label = "beaglebone:green:usr4";
+ gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ function = LED_FUNCTION_WLAN;
+ default-state = "off";
+ };
+ };
+
+ evm_12v0: regulator-0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: regulator-1 {
+ /* Output of LMS140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: regulator-2 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pwr_en_pins_default>;
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: regulator-4 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpio = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
+ compatible = "ti,j721e-cpsw-virt-mac";
+ dma-coherent;
+ ti,psil-base = <0x4a00>;
+ ti,remote-name = "mpu_1_0_ethswitch-device-0";
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ virt_emac_port {
+ ti,label = "virt-port";
+ /* local-mac-address = [0 0 0 0 0 0]; */
+ };
+ };
+
+ transceiver1: can-phy@0 {
+ status = "disabled";
+ };
+
+ transceiver2: can-phy@1 {
+ status = "disabled";
+ };
+
+ dp_pwr_3v3: regulator-5 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_3v3_en_pins_default>;
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
+ enable-active-high;
+
+ /* Always on for now, until dp-connector driver can handle this */
+ regulator-always-on;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp_pwr_3v3>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ led_pins_default: led-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
+ J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
+ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
+ J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ sd_pwr_en_pins_default: sd-pwr-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ >;
+ };
+
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
+ >;
+ };
+
+ tusb322_pins_default: tusb322-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x214, PIN_INPUT, 7) /* (V4) MCAN1_TX.GPIO1_4 -- USBC_INT */
+ >;
+ };
+
+ main_usbss1_pins_default: main-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
+ >;
+ };
+
+ dp0_3v3_en_pins_default:dp0-3v3-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
+ >;
+ };
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ main_i2c5_pins_default: main-i2c5-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ pcie1_rst_pins_default: pcie1-rst-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
+ >;
+ };
+
+ ehrpwm0_pins_default: ehrpwm0_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x164, PIN_OUTPUT, 6) /* (V29) RGMII5_TD2.EHRPWM0_A */
+ J721E_IOPAD(0x168, PIN_OUTPUT, 6) /* (V27) RGMII5_TD1.EHRPWM0_B */
+ >;
+ };
+
+ ehrpwm1_pins_default: ehrpwm1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x16c, PIN_OUTPUT, 6) /* (U28) RGMII5_TD0.EHRPWM1_A */
+ J721E_IOPAD(0x170, PIN_OUTPUT, 6) /* (U29) RGMII5_TXC.EHRPWM1_B */
+ >;
+ };
+
+ ehrpwm2_pins_default: ehrpwm2_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x178, PIN_OUTPUT, 6) /* (U27) RGMII5_RD3.EHRPWM2_A */
+ J721E_IOPAD(0x17c, PIN_OUTPUT, 6) /* (U24) RGMII5_RD2.EHRPWM2_B */
+ >;
+ };
+
+ ehrpwm3_pins_default: ehrpwm3_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x18c, PIN_OUTPUT, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */
+ J721E_IOPAD(0x190, PIN_OUTPUT, 6) /* (W23) RGMII6_TD3.EHRPWM3_B */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ eeprom_wp_pins_default: eeprom-wp-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
+ >;
+ };
+
+ mcu_adc0_pins_default: mcu-adc0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
+ J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
+ J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
+ J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
+ J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
+ J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ /* TODO: disable? */
+ J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
+ >;
+ };
+
+ mcu_adc1_pins_default: mcu-adc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
+ >;
+ };
+
+ mikro_bus_pins_default: mikro-bus-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
+ J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
+ J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
+ J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
+
+ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
+ J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
+ J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
+ J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
+
+ J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
+ J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
+
+ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
+ J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
+ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
+ J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ sw_pwr_pins_default: sw-pwr-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+
+ mcu_usbss1_pins_default: mcu-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by TIFS firmware. */
+ status = "reserved";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart3 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart6 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart7 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart8 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart9 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD Card */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+
+ tusb322@47 {
+ compatible = "ti,tusb322";
+ reg = <0x47>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tusb322_pins_default>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+};
+
+bone_i2c_0: &wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+};
+
+&main_gpio0 {
+ status = "okay";
+ gpio-line-names =
+ "NC",
+ "P9_11",
+ "P9_13",
+ "P8_17",
+ "P8_18", /* 0-4 */
+ "P8_22",
+ "P8_24",
+ "P8_34",
+ "P8_36",
+ "P8_38A", /* 5-9 */
+ "P9_23",
+ "P8_37B",
+ "P9_26B",
+ "P9_24B",
+ "P8_08", /* 10-14 */
+ "P8_07",
+ "P8_10",
+ "P8_09",
+ "P9_42B",
+ "NC", /* 15-19 */
+ "P8_03",
+ "TYPEC_PWR_ST",
+ "M2_RSTz",
+ "M2_I2C_ALERT#",
+ "P8_35A", /* 20-24 */
+ "P8_33A",
+ "P8_32A",
+ "NC",
+ "P9_17A",
+ "NC", /* 25-29 */
+ "P8_21",
+ "P8_23",
+ "P8_31A",
+ "P8_05",
+ "P8_06", /* 30-34 */
+ "P8_25",
+ "M2_W_DISABLE1#",
+ "M2_W_DISABLE2#",
+ "P9_22A (BOOTMODE1)",
+ "P9_21A", /* 35-39 */
+ "P9_18A",
+ "DSI_I2C_SCL",
+ "DSI_I2C_SDA",
+ "P9_28B",
+ "P9_30B", /* 40-44 */
+ "P9_12",
+ "P9_27A",
+ "P9_15",
+ "P8_04 (BOOTMODE2)",
+ "VCC_DP_EN", /* 45-49 */
+ "P9_33B",
+ "P8_26",
+ "P9_31B",
+ "P9_29B",
+ "P9_39B", /* 50-54 */
+ "P9_35B",
+ "P9_36B",
+ "P9_37B",
+ "P9_38B",
+ "P8_12", /* 55-59 */
+ "P8_11 (BOOTMODE7)",
+ "P8_15",
+ "P8_16",
+ "NC",
+ "NC", /* 60-64 */
+ "P8_43",
+ "P8_44",
+ "P8_41",
+ "P8_42 (BOOTMODE6)",
+ "P8_39", /* 65-69 */
+ "P8_40",
+ "P8_27",
+ "P8_28",
+ "P8_29",
+ "P8_30", /* 70-74 */
+ "P8_14",
+ "P8_20",
+ "P9_20B",
+ "P9_19B",
+ "P8_45", /* 75-79 */
+ "P8_46 (BOOTMODE3)",
+ "P9_40B",
+ "VDD_SD_EN",
+ "CSI_I2C_SCL",
+ "CSI_I2C_SDA", /* 80-84 */
+ "M2_I2S_SCK",
+ "M2_I2S_WS",
+ "M2_I2S_IN",
+ "P8_19",
+ "P8_13", /* 85-89 */
+ "P9_21B",
+ "P9_22B",
+ "M2_I2S_OUT",
+ "P9_14",
+ "P9_16", /* 90-94 */
+ "USR1",
+ "USR0",
+ "USR2",
+ "DSI_GPIO1",
+ "FAN_PWM", /* 95-99 */
+ "FAN_TACH",
+ "CSI1_GPIO1",
+ "CSI0_GPIO2",
+ "CSI0_GPIO1",
+ "P9_25B", /* 100-104 */
+ "P8_38B",
+ "P8_37A",
+ "CSI1_GPIO2",
+ "DSI_GPIO2",
+ "USR4", /* 105-109 */
+ "USR3",
+ "P8_33B",
+ "DP_HPD",
+ "M2_UART_CTSn",
+ "M2_UART_RTSn", /* 110-114 */
+ "P9_17B",
+ "P8_35B",
+ "VDD_SD_SEL",
+ "P9_26A",
+ "P9_24A", /* 115-119 */
+ "P9_18B",
+ "CONSOLE_RX",
+ "CONSOLE_TX",
+ "P9_42A",
+ "P9_27B", /* 120-124 */
+ "M2_UART_RX",
+ "M2_UART_TX",
+ "P9_25A"; /* 125-127 */
+};
+
+&main_gpio1 {
+ status = "okay";
+ gpio-line-names =
+ "P9_41",
+ "P9_19A",
+ "P9_20A",
+ "TYPEC_DIR",
+ "TYPEC_INT", /* 0-4 */
+ "M2_PCIE_WAKE#",
+ "M2_PCIE_CLKREQ#",
+ "M2_I2C_SCL",
+ "M2_I2C_SDA",
+ "TYPEC/CSI1_I2C_SCL", /* 5-9 */
+ "TYPEC/CSI1_I2C_SDA",
+ "P9_28A",
+ "P9_31A",
+ "P9_30A",
+ "P9_29A", /* 10-14 */
+ "uSD_DAT3",
+ "uSD_DAT2",
+ "uSD_DAT1",
+ "uSD_DAT0",
+ "uSD_CLK", /* 15-19 */
+ "uSD_CMD",
+ "uSD_SDCD",
+ "NC",
+ "M2_SDIO_DAT3",
+ "M2_SDIO_DAT2", /* 20-24 */
+ "M2_SDIO_DAT1",
+ "M2_SDIO_DAT0",
+ "M2_SDIO_CLK",
+ "M2_SDIO_CMD",
+ "USB1_DRVVBUS", /* 25-29 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* 30-34 */
+ "NC",
+ "NC"; /* 35-36 */
+};
+
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio3 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio5 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&main_gpio7 {
+ status = "disabled";
+};
+
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>;
+ gpio-line-names =
+ "MB_CLK/BOOT_BTN",
+ "MB_MISO",
+ "MB_MOSI",
+ "MB_CS",
+ "SOC_WAKE", /* 0-4 */
+ "EEPROM_WP",
+ "SOC_INT2z",
+ "H_MCU_INT#",
+ "MB_SCLA",
+ "MB_SDAA", /* 5-9 */
+ "MCU_RGMII_RST#",
+ "MB_PWM",
+ "MCU_BOOTMODE8",
+ "MCU_BOOTMODE9",
+ "MCU_BOOTMODE6", /* 10-14 */
+ "MCU_BOOTMODE7",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* 15-19 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* 20-24 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* 24-29 */
+ "USB_HUB_RST",
+ "NC",
+ "NC",
+ "MB_RX",
+ "MB_TX", /* 30-34 */
+ "MB_INT",
+ "NC",
+ "MB_RST",
+ "MII_TX_CTL",
+ "MII_RX_CTL", /* 35-39 */
+ "MII_TD3",
+ "MII_TD2",
+ "MII_TD1",
+ "MII_TD0",
+ "MII_TXC", /* 40-44 */
+ "MII_RXC",
+ "MII_RD3",
+ "MII_RD2",
+ "MII_RD1",
+ "MII_RD0", /* 45-49 */
+ "MDIO",
+ "MDC",
+ "MCU_BOOTMODE0",
+ "MCU_BOOTMODE1",
+ "MCU_BOOTMODE2", /* 50-54 */
+ "SYS_MCU_PWRDN",
+ "WKUP_UART_RX",
+ "WKUP_UART_TX",
+ "MII_RST#",
+ "MB_AN", /* 55-59 */
+ "MB_SCLB",
+ "MB_SDAB",
+ "WKUP_I2C0_SCL",
+ "WKUP_I2C0_SDA",
+ "MCU_I2C0_SCL", /* 60-64 */
+ "MCU_I2C0_SDA",
+ "MB_SDAPULLEN",
+ "PMIC_POWER_EN1"; /* 65-67 */
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
+&usb_serdes_mux {
+ idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, /* TODO: is this right? */
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, /* TODO: USB3_0 or USB3_1? */
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+ serdes3_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
+&mhdp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+ serdes2_usb_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz2 2>;
+ };
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes2_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+ /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&tscadc1 {
+ /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&dss {
+ /*
+ * These clock assignments are chosen to enable the following outputs:
+ *
+ * VP0 - DisplayPort SST
+ * VP1 - DPI0
+ * VP2 - DSI
+ * VP3 - DPI1
+ */
+
+ assigned-clocks = <&k3_clks 152 1>,
+ <&k3_clks 152 4>,
+ <&k3_clks 152 9>,
+ <&k3_clks 152 13>;
+ assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
+ <&k3_clks 152 6>, /* PLL19_HSDIV0 */
+ <&k3_clks 152 11>, /* PLL18_HSDIV0 */
+ <&k3_clks 152 18>; /* PLL23_HSDIV0 */
+};
+
+&dss_ports {
+ port@0 {
+ reg = <0>;
+
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp_connector_in>;
+ };
+ };
+};
+
+&mcasp0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp3 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp4 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp5 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp6 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp7 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp8 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp9 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp10 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp11 {
+ /* Unused */
+ status = "disabled";
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&pcie0_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie1_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_rst_pins_default>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ max-link-speed = <3>;
+ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie2_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_ep {
+ status = "disabled";
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie2_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcu_mcan0 {
+ status = "disabled";
+};
+
+&mcu_mcan1 {
+ status = "disabled";
+};
+
+&main_mcan0 {
+ status = "disabled";
+};
+
+&main_mcan1 {
+ status = "disabled";
+};
+
+&main_mcan2 {
+ status = "disabled";
+};
+
+&main_mcan3 {
+ status = "disabled";
+};
+
+&main_mcan4 {
+ status = "disabled";
+};
+
+&main_mcan5 {
+ status = "disabled";
+};
+
+&main_mcan6 {
+ status = "disabled";
+};
+
+&main_mcan7 {
+ status = "disabled";
+};
+
+&main_mcan8 {
+ status = "disabled";
+};
+
+&main_mcan9 {
+ status = "disabled";
+};
+
+&main_mcan10 {
+ status = "disabled";
+};
+
+&main_mcan11 {
+ status = "disabled";
+};
+
+&main_mcan12 {
+ status = "disabled";
+};
+
+&main_mcan13 {
+ status = "disabled";
+};
+
+&ufs_wrapper {
+ status = "disabled";
+};
+
+&csi0_port0 {
+ status = "disabled";
+};
+
+&csi0_port1 {
+ status = "disabled";
+};
+
+&csi0_port2 {
+ status = "disabled";
+};
+
+&csi0_port3 {
+ status = "disabled";
+};
+
+&csi0_port4 {
+ status = "disabled";
+};
+
+&csi1_port0 {
+ status = "disabled";
+};
+
+&csi1_port1 {
+ status = "disabled";
+};
+
+&csi1_port2 {
+ status = "disabled";
+};
+
+&csi1_port3 {
+ status = "disabled";
+};
+
+&csi1_port4 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
new file mode 100644
index 0000000000000..e189e16bf375e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -0,0 +1,1209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+
+#include "k3-j721e-som-p0.dtsi"
+#include "k3-j721e-rtos-memory-map.dtsi"
+#include "k3-j721e-beagleboneai64-bone-buses.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/board/k3-j721e-bone-pins.h>
+
+/ {
+ compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
+ model = "BeagleBoard.org BeagleBone AI-64";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ base_dtb = "k3-j721e-beagleboneai64.dts";
+ base_dtb_timestamp = __TIMESTAMP__;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_pwr_pins_default>;
+
+ button-1 {
+ label = "BOOT";
+ linux,code = <BTN_0>;
+ gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ button-2 {
+ label = "POWER";
+ linux,code = <KEY_POWER>;
+ gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_default>;
+
+ led-0 {
+ label = "beaglebone:green:usr0";
+ gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ };
+
+ led-1 {
+ label = "beaglebone:green:usr1";
+ gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ };
+
+ led-2 {
+ label = "beaglebone:green:usr2";
+ gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu";
+ function = LED_FUNCTION_CPU;
+ };
+
+ led-3 {
+ label = "beaglebone:green:usr3";
+ gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ };
+
+ led-4 {
+ label = "beaglebone:green:usr4";
+ gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ function = LED_FUNCTION_WLAN;
+ default-state = "off";
+ };
+ };
+
+ evm_12v0: regulator-0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: regulator-1 {
+ /* Output of LMS140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: regulator-2 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pwr_en_pins_default>;
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: regulator-4 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpio = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ cpsw9g_virt_mac: main_r5fss_cpsw9g_virt_mac0 {
+ compatible = "ti,j721e-cpsw-virt-mac";
+ dma-coherent;
+ ti,psil-base = <0x4a00>;
+ ti,remote-name = "mpu_1_0_ethswitch-device-0";
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ virt_emac_port {
+ ti,label = "virt-port";
+ /* local-mac-address = [0 0 0 0 0 0]; */
+ };
+ };
+
+ transceiver1: can-phy@0 {
+ status = "disabled";
+ };
+
+ transceiver2: can-phy@1 {
+ status = "disabled";
+ };
+
+ dp_pwr_3v3: regulator-5 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_3v3_en_pins_default>;
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
+ enable-active-high;
+
+ /* Always on for now, until dp-connector driver can handle this */
+ regulator-always-on;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp_pwr_3v3>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ led_pins_default: led-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
+ J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
+ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
+ J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ sd_pwr_en_pins_default: sd-pwr-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ >;
+ };
+
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
+ >;
+ };
+
+ tusb322_pins_default: tusb322-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x214, PIN_INPUT, 7) /* (V4) MCAN1_TX.GPIO1_4 -- USBC_INT */
+ >;
+ };
+
+ main_usbss1_pins_default: main-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
+ >;
+ };
+
+ dp0_3v3_en_pins_default:dp0-3v3-en-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
+ >;
+ };
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ main_i2c5_pins_default: main-i2c5-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ pcie1_rst_pins_default: pcie1-rst-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
+ >;
+ };
+
+ ehrpwm0_pins_default: ehrpwm0_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x164, PIN_OUTPUT, 6) /* (V29) RGMII5_TD2.EHRPWM0_A */
+ J721E_IOPAD(0x168, PIN_OUTPUT, 6) /* (V27) RGMII5_TD1.EHRPWM0_B */
+ >;
+ };
+
+ ehrpwm1_pins_default: ehrpwm1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x16c, PIN_OUTPUT, 6) /* (U28) RGMII5_TD0.EHRPWM1_A */
+ J721E_IOPAD(0x170, PIN_OUTPUT, 6) /* (U29) RGMII5_TXC.EHRPWM1_B */
+ >;
+ };
+
+ ehrpwm2_pins_default: ehrpwm2_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x178, PIN_OUTPUT, 6) /* (U27) RGMII5_RD3.EHRPWM2_A */
+ J721E_IOPAD(0x17c, PIN_OUTPUT, 6) /* (U24) RGMII5_RD2.EHRPWM2_B */
+ >;
+ };
+
+ ehrpwm3_pins_default: ehrpwm3_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x18c, PIN_OUTPUT, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */
+ J721E_IOPAD(0x190, PIN_OUTPUT, 6) /* (W23) RGMII6_TD3.EHRPWM3_B */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ eeprom_wp_pins_default: eeprom-wp-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
+ >;
+ };
+
+ mcu_adc0_pins_default: mcu-adc0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
+ J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
+ J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
+ J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
+ J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
+ J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ /* TODO: disable? */
+ J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
+ >;
+ };
+
+ mcu_adc1_pins_default: mcu-adc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
+ >;
+ };
+
+ mikro_bus_pins_default: mikro-bus-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
+ J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
+ J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
+ J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
+
+ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
+ J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
+ J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
+ J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
+
+ J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
+ J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
+
+ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
+ J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
+ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
+ J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ sw_pwr_pins_default: sw-pwr-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+
+ mcu_usbss1_pins_default: mcu-usbss1-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by TIFS firmware. */
+ status = "reserved";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart3 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart6 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart7 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart8 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart9 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD Card */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+
+ tusb322@47 {
+ compatible = "ti,tusb322";
+ reg = <0x47>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tusb322_pins_default>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+};
+
+bone_i2c_0: &wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+};
+
+&main_gpio0 {
+ status = "okay";
+ gpio-line-names =
+ "NC",
+ "P9_11",
+ "P9_13",
+ "P8_17",
+ "P8_18", /* 0-4 */
+ "P8_22",
+ "P8_24",
+ "P8_34",
+ "P8_36",
+ "P8_38A", /* 5-9 */
+ "P9_23",
+ "P8_37B",
+ "P9_26B",
+ "P9_24B",
+ "P8_08", /* 10-14 */
+ "P8_07",
+ "P8_10",
+ "P8_09",
+ "P9_42B",
+ "NC", /* 15-19 */
+ "P8_03",
+ "TYPEC_PWR_ST",
+ "M2_RSTz",
+ "M2_I2C_ALERT#",
+ "P8_35A", /* 20-24 */
+ "P8_33A",
+ "P8_32A",
+ "NC",
+ "P9_17A",
+ "NC", /* 25-29 */
+ "P8_21",
+ "P8_23",
+ "P8_31A",
+ "P8_05",
+ "P8_06", /* 30-34 */
+ "P8_25",
+ "M2_W_DISABLE1#",
+ "M2_W_DISABLE2#",
+ "P9_22A (BOOTMODE1)",
+ "P9_21A", /* 35-39 */
+ "P9_18A",
+ "DSI_I2C_SCL",
+ "DSI_I2C_SDA",
+ "P9_28B",
+ "P9_30B", /* 40-44 */
+ "P9_12",
+ "P9_27A",
+ "P9_15",
+ "P8_04 (BOOTMODE2)",
+ "VCC_DP_EN", /* 45-49 */
+ "P9_33B",
+ "P8_26",
+ "P9_31B",
+ "P9_29B",
+ "P9_39B", /* 50-54 */
+ "P9_35B",
+ "P9_36B",
+ "P9_37B",
+ "P9_38B",
+ "P8_12", /* 55-59 */
+ "P8_11 (BOOTMODE7)",
+ "P8_15",
+ "P8_16",
+ "NC",
+ "NC", /* 60-64 */
+ "P8_43",
+ "P8_44",
+ "P8_41",
+ "P8_42 (BOOTMODE6)",
+ "P8_39", /* 65-69 */
+ "P8_40",
+ "P8_27",
+ "P8_28",
+ "P8_29",
+ "P8_30", /* 70-74 */
+ "P8_14",
+ "P8_20",
+ "P9_20B",
+ "P9_19B",
+ "P8_45", /* 75-79 */
+ "P8_46 (BOOTMODE3)",
+ "P9_40B",
+ "VDD_SD_EN",
+ "CSI_I2C_SCL",
+ "CSI_I2C_SDA", /* 80-84 */
+ "M2_I2S_SCK",
+ "M2_I2S_WS",
+ "M2_I2S_IN",
+ "P8_19",
+ "P8_13", /* 85-89 */
+ "P9_21B",
+ "P9_22B",
+ "M2_I2S_OUT",
+ "P9_14",
+ "P9_16", /* 90-94 */
+ "USR1",
+ "USR0",
+ "USR2",
+ "DSI_GPIO1",
+ "FAN_PWM", /* 95-99 */
+ "FAN_TACH",
+ "CSI1_GPIO1",
+ "CSI0_GPIO2",
+ "CSI0_GPIO1",
+ "P9_25B", /* 100-104 */
+ "P8_38B",
+ "P8_37A",
+ "CSI1_GPIO2",
+ "DSI_GPIO2",
+ "USR4", /* 105-109 */
+ "USR3",
+ "P8_33B",
+ "DP_HPD",
+ "M2_UART_CTSn",
+ "M2_UART_RTSn", /* 110-114 */
+ "P9_17B",
+ "P8_35B",
+ "VDD_SD_SEL",
+ "P9_26A",
+ "P9_24A", /* 115-119 */
+ "P9_18B",
+ "CONSOLE_RX",
+ "CONSOLE_TX",
+ "P9_42A",
+ "P9_27B", /* 120-124 */
+ "M2_UART_RX",
+ "M2_UART_TX",
+ "P9_25A"; /* 125-127 */
+};
+
+&main_gpio1 {
+ status = "okay";
+ gpio-line-names =
+ "P9_41",
+ "P9_19A",
+ "P9_20A",
+ "TYPEC_DIR",
+ "TYPEC_INT", /* 0-4 */
+ "M2_PCIE_WAKE#",
+ "M2_PCIE_CLKREQ#",
+ "M2_I2C_SCL",
+ "M2_I2C_SDA",
+ "TYPEC/CSI1_I2C_SCL", /* 5-9 */
+ "TYPEC/CSI1_I2C_SDA",
+ "P9_28A",
+ "P9_31A",
+ "P9_30A",
+ "P9_29A", /* 10-14 */
+ "uSD_DAT3",
+ "uSD_DAT2",
+ "uSD_DAT1",
+ "uSD_DAT0",
+ "uSD_CLK", /* 15-19 */
+ "uSD_CMD",
+ "uSD_SDCD",
+ "NC",
+ "M2_SDIO_DAT3",
+ "M2_SDIO_DAT2", /* 20-24 */
+ "M2_SDIO_DAT1",
+ "M2_SDIO_DAT0",
+ "M2_SDIO_CLK",
+ "M2_SDIO_CMD",
+ "USB1_DRVVBUS", /* 25-29 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* 30-34 */
+ "NC",
+ "NC"; /* 35-36 */
+};
+
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio3 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio5 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&main_gpio7 {
+ status = "disabled";
+};
+
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>;
+ gpio-line-names =
+ "MB_CLK/BOOT_BTN",
+ "MB_MISO",
+ "MB_MOSI",
+ "MB_CS",
+ "SOC_WAKE", /* 0-4 */
+ "EEPROM_WP",
+ "SOC_INT2z",
+ "H_MCU_INT#",
+ "MB_SCLA",
+ "MB_SDAA", /* 5-9 */
+ "MCU_RGMII_RST#",
+ "MB_PWM",
+ "MCU_BOOTMODE8",
+ "MCU_BOOTMODE9",
+ "MCU_BOOTMODE6", /* 10-14 */
+ "MCU_BOOTMODE7",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* 15-19 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* 20-24 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* 24-29 */
+ "USB_HUB_RST",
+ "NC",
+ "NC",
+ "MB_RX",
+ "MB_TX", /* 30-34 */
+ "MB_INT",
+ "NC",
+ "MB_RST",
+ "MII_TX_CTL",
+ "MII_RX_CTL", /* 35-39 */
+ "MII_TD3",
+ "MII_TD2",
+ "MII_TD1",
+ "MII_TD0",
+ "MII_TXC", /* 40-44 */
+ "MII_RXC",
+ "MII_RD3",
+ "MII_RD2",
+ "MII_RD1",
+ "MII_RD0", /* 45-49 */
+ "MDIO",
+ "MDC",
+ "MCU_BOOTMODE0",
+ "MCU_BOOTMODE1",
+ "MCU_BOOTMODE2", /* 50-54 */
+ "SYS_MCU_PWRDN",
+ "WKUP_UART_RX",
+ "WKUP_UART_TX",
+ "MII_RST#",
+ "MB_AN", /* 55-59 */
+ "MB_SCLB",
+ "MB_SDAB",
+ "WKUP_I2C0_SCL",
+ "WKUP_I2C0_SDA",
+ "MCU_I2C0_SCL", /* 60-64 */
+ "MCU_I2C0_SDA",
+ "MB_SDAPULLEN",
+ "PMIC_POWER_EN1"; /* 65-67 */
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
+&usb_serdes_mux {
+ idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, /* TODO: is this right? */
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, /* TODO: USB3_0 or USB3_1? */
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+ serdes3_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
+&mhdp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+ serdes2_usb_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz2 2>;
+ };
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes2_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+ /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&tscadc1 {
+ /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&dss {
+ /*
+ * These clock assignments are chosen to enable the following outputs:
+ *
+ * VP0 - DisplayPort SST
+ * VP1 - DPI0
+ * VP2 - DSI
+ * VP3 - DPI1
+ */
+
+ assigned-clocks = <&k3_clks 152 1>,
+ <&k3_clks 152 4>,
+ <&k3_clks 152 9>,
+ <&k3_clks 152 13>;
+ assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
+ <&k3_clks 152 6>, /* PLL19_HSDIV0 */
+ <&k3_clks 152 11>, /* PLL18_HSDIV0 */
+ <&k3_clks 152 18>; /* PLL23_HSDIV0 */
+};
+
+&dss_ports {
+ port@0 {
+ reg = <0>;
+
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp_connector_in>;
+ };
+ };
+};
+
+&mcasp0 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp1 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp2 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp3 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp4 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp5 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp6 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp7 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp8 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp9 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp10 {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcasp11 {
+ /* Unused */
+ status = "disabled";
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&pcie0_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie1_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_rst_pins_default>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ max-link-speed = <3>;
+ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie2_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_ep {
+ status = "disabled";
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie2_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_rc {
+ /* Unused */
+ status = "disabled";
+};
+
+&pcie3_ep {
+ /* Unused */
+ status = "disabled";
+};
+
+&mcu_mcan0 {
+ status = "disabled";
+};
+
+&mcu_mcan1 {
+ status = "disabled";
+};
+
+&main_mcan0 {
+ status = "disabled";
+};
+
+&main_mcan1 {
+ status = "disabled";
+};
+
+&main_mcan2 {
+ status = "disabled";
+};
+
+&main_mcan3 {
+ status = "disabled";
+};
+
+&main_mcan4 {
+ status = "disabled";
+};
+
+&main_mcan5 {
+ status = "disabled";
+};
+
+&main_mcan6 {
+ status = "disabled";
+};
+
+&main_mcan7 {
+ status = "disabled";
+};
+
+&main_mcan8 {
+ status = "disabled";
+};
+
+&main_mcan9 {
+ status = "disabled";
+};
+
+&main_mcan10 {
+ status = "disabled";
+};
+
+&main_mcan11 {
+ status = "disabled";
+};
+
+&main_mcan12 {
+ status = "disabled";
+};
+
+&main_mcan13 {
+ status = "disabled";
+};
+
+&ufs_wrapper {
+ status = "disabled";
+};
+
+&csi0_port0 {
+ status = "disabled";
+};
+
+&csi0_port1 {
+ status = "disabled";
+};
+
+&csi0_port2 {
+ status = "disabled";
+};
+
+&csi0_port3 {
+ status = "disabled";
+};
+
+&csi0_port4 {
+ status = "disabled";
+};
+
+&csi1_port0 {
+ status = "disabled";
+};
+
+&csi1_port1 {
+ status = "disabled";
+};
+
+&csi1_port2 {
+ status = "disabled";
+};
+
+&csi1_port3 {
+ status = "disabled";
+};
+
+&csi1_port4 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index d9fc06f398da3..ead41fb2a928a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -288,13 +288,6 @@ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x1c8, PIN_INPUT_PULLUP, 2) /* (AB5) SPI0_CLK.I2C2_SCL */
- J721E_IOPAD(0x1cc, PIN_INPUT_PULLUP, 2) /* (AA1) SPI0_D0.I2C2_SDA */
- >;
- };
-
main_i2c3_pins_default: main-i2c3-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
@@ -613,14 +606,6 @@ exp2: gpio@22 {
gpio-controller;
#gpio-cells = <2>;
- p08-hog {
- /* P10 - PM_I2C_CTRL_OE */
- gpio-hog;
- gpios = <8 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "CTRL_PM_I2C_OE";
- };
-
p09-hog {
/* P11 - MCASP/TRACE_MUX_S0 */
gpio-hog;
@@ -658,108 +643,6 @@ exp4: gpio@20 {
};
};
-&main_i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c2_pins_default>;
- clock-frequency = <400000>;
-
- ina226@40 {
- compatible = "ti,ina226";
- reg = <0x40>;
- shunt-resistor = <10000>;
- };
-
- ina226@41 {
- compatible = "ti,ina226";
- reg = <0x41>;
- shunt-resistor = <10000>;
- };
-
- ina226@42 {
- compatible = "ti,ina226";
- reg = <0x42>;
- shunt-resistor = <10000>;
- };
-
- ina226@43 {
- compatible = "ti,ina226";
- reg = <0x43>;
- shunt-resistor = <10000>;
- };
-
- ina226@44 {
- compatible = "ti,ina226";
- reg = <0x44>;
- shunt-resistor = <10000>;
- };
-
- ina226@45 {
- compatible = "ti,ina226";
- reg = <0x45>;
- shunt-resistor = <5000>;
- };
-
- ina226@46 {
- compatible = "ti,ina226";
- reg = <0x46>;
- shunt-resistor = <10000>;
- };
-
- ina226@47 {
- compatible = "ti,ina226";
- reg = <0x47>;
- shunt-resistor = <10000>;
- };
-
- ina226@48 {
- compatible = "ti,ina226";
- reg = <0x48>;
- shunt-resistor = <10000>;
- };
-
- ina226@49 {
- compatible = "ti,ina226";
- reg = <0x49>;
- shunt-resistor = <10000>;
- };
-
- ina226@4a {
- compatible = "ti,ina226";
- reg = <0x4a>;
- shunt-resistor = <10000>;
- };
-
- ina226@4b {
- compatible = "ti,ina226";
- reg = <0x4b>;
- shunt-resistor = <10000>;
- };
-
- ina226@4c {
- compatible = "ti,ina226";
- reg = <0x4c>;
- shunt-resistor = <10000>;
- };
-
- ina226@4d {
- compatible = "ti,ina226";
- reg = <0x4d>;
- shunt-resistor = <10000>;
- };
-
- ina226@4e {
- compatible = "ti,ina226";
- reg = <0x4e>;
- shunt-resistor = <10000>;
- };
-
- ina226@4f {
- compatible = "ti,ina226";
- reg = <0x4f>;
- shunt-resistor = <10000>;
- };
-};
-
&k3_clks {
/* Confiure AUDIO_EXT_REFCLK2 pin as output */
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index a561e30fb1481..41b41dfb548e1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1662,6 +1662,23 @@ dp0_ports: ports {
};
};
+ dsi0: dsi@48000000 {
+ compatible = "ti,j721e-dsi";
+ reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
+ clocks = <&k3_clks 150 1>, <&k3_clks 150 5>;
+ clock-names = "dsi_p_clk", "dsi_sys_clk";
+ power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&dphy2>;
+ phy-names = "dphy";
+
+ dsi0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg =
@@ -2809,4 +2826,16 @@ dphy1: phy@4590000 {
#phy-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
};
+
+ dphy2: phy@4480000 {
+ compatible = "ti,j721e-dphy";
+ reg = <0x0 0x04480000 0x0 0x1000>;
+ clocks = <&k3_clks 296 1>, <&k3_clks 296 3>;
+ clock-names = "psm", "pll_ref";
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 296 3>;
+ assigned-clock-parents = <&k3_clks 296 4>;
+ assigned-clock-rates = <19200000>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-rtos-memory-map.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-rtos-memory-map.dtsi
index 3f5b7c4ca066a..dd9ad05e79795 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-rtos-memory-map.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-rtos-memory-map.dtsi
@@ -7,9 +7,6 @@
#include <dt-bindings/soc/ti,sci_pm_domain.h>
-/dts-v1/;
-/plugin/;
-
/ {
fragment@101 {
target-path = "/";
@@ -17,7 +14,7 @@ fragment@101 {
__overlay__ {
dma_buf_phys {
- compatible = "ti,dma_buf_phys";
+ compatible = "ti,dma-buf-phys";
};
};
};
@@ -252,11 +249,13 @@ &main_r5fss0_core0 {
<&vision_apps_main_r5fss0_core0_memory_region>,
<&vision_apps_main_r5fss0_core0_shared_memory_queue_region>,
<&vision_apps_main_r5fss0_core0_shared_memory_bufpool_region>;
+ firmware-name = "vision_apps_eaik/vx_app_rtos_linux_mcu2_0.dontload";
};
&main_r5fss0_core1 {
memory-region = <&vision_apps_main_r5fss0_core1_dma_memory_region>,
<&vision_apps_main_r5fss0_core1_memory_region>;
+ firmware-name = "vision_apps_eaik/vx_app_rtos_linux_mcu2_1.dontload";
};
&main_r5fss1_core0 {
@@ -272,16 +271,17 @@ &main_r5fss1_core1 {
&c66_0 {
memory-region = <&vision_apps_c66_0_dma_memory_region>,
<&vision_apps_c66_0_memory_region>;
+ firmware-name = "vision_apps_eaik/vx_app_rtos_linux_c6x_1.out";
};
&c66_1 {
memory-region = <&vision_apps_c66_1_dma_memory_region>,
<&vision_apps_c66_1_memory_region>;
+ firmware-name = "vision_apps_eaik/vx_app_rtos_linux_c6x_2.out";
};
&c71_0 {
memory-region = <&vision_apps_c71_0_dma_memory_region>,
<&vision_apps_c71_0_memory_region>;
+ firmware-name = "vision_apps_eaik/vx_app_rtos_linux_c7x_1.out";
};
-
-
diff --git a/arch/arm64/boot/dts/ti/overlays/BB-I2C2-MPU6050.dts b/arch/arm64/boot/dts/ti/overlays/BB-I2C2-MPU6050.dts
new file mode 100644
index 0000000000000..1e48db3858418
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BB-I2C2-MPU6050.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 Robert Nelson <robertcnelson@gmail.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/board/k3-j721e-bone-pins.h>
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BB-I2C2-MPU6050.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_i2c_2 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imu@68 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&P9_12_gpio_pin>;
+ compatible = "invensense,mpu6050";
+ reg = <0x68>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <45 IRQ_TYPE_EDGE_RISING>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BBAI64-CSI0-imx219.dts b/arch/arm64/boot/dts/ti/overlays/BBAI64-CSI0-imx219.dts
new file mode 100644
index 0000000000000..75abe844b48a8
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BBAI64-CSI0-imx219.dts
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * DT Overlay for RPi Camera V2.1 (Sony IMX219) interfaced with CSI0 on BBAI64 board.
+ *
+ * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/k3.h>
+
+/* CSI0 */
+/* W29_CSI0_GPIO1 */
+/* W27_CSI0_GPIO2 */
+/* Y26_I2C5_SCL */
+/* AA27_I2C5_SDA */
+
+/* CSI1 */
+/* V25_CSI1_GPIO1 */
+/* W24_CSI1_GPIO2 */
+/* Y6_I2C1_SCL */
+/* AA6_I2C1_SDA */
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BBAI64-CSI0-imx219.kernel = __TIMESTAMP__;
+ };
+};
+
+/ {
+ fragment@101 {
+ target-path = "/";
+
+ __overlay__ {
+ clk_csi0_imx219_fixed: csi0-imx219-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ main_i2c5_pins_default: main-i2c5-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ csi0_gpio_pins_default: csi0-gpio-pins-default {
+ pinctrl-single,pins = <
+ //J721E_IOPAD(0x19c, PIN_OUTPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1a0, PIN_OUTPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ >;
+ };
+};
+
+&main_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_imx219: csi0_sensor@10 {
+ status = "okay";
+ compatible = "sony,imx219";
+ reg = <0x10>;
+
+ clocks = <&clk_csi0_imx219_fixed>;
+ clock-names = "xclk";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi0_gpio_pins_default>;
+ //reset-gpios = <&main_gpio0 102 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&main_gpio0 103 GPIO_ACTIVE_HIGH>;
+
+ port {
+ csi2rx0_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ link-frequencies = /bits/ 64 <456000000>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&csi0_port0 {
+ status = "okay";
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2rx0_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BBAI64-CSI1-imx219.dts b/arch/arm64/boot/dts/ti/overlays/BBAI64-CSI1-imx219.dts
new file mode 100644
index 0000000000000..33b8aa97ac42f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BBAI64-CSI1-imx219.dts
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * DT Overlay for RPi Camera V2.1 (Sony IMX219) interfaced with CSI1 on BBAI64 board.
+ *
+ * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/k3.h>
+
+/* CSI0 */
+/* W29_CSI0_GPIO1 */
+/* W27_CSI0_GPIO2 */
+/* Y26_I2C5_SCL */
+/* AA27_I2C5_SDA */
+
+/* CSI1 */
+/* V25_CSI1_GPIO1 */
+/* W24_CSI1_GPIO2 */
+/* Y6_I2C1_SCL */
+/* AA6_I2C1_SDA */
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BBAI64-CSI1-imx219.kernel = __TIMESTAMP__;
+ };
+};
+
+/ {
+ fragment@101 {
+ target-path = "/";
+
+ __overlay__ {
+ clk_csi1_imx219_fixed: csi1-imx219-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ csi1_gpio_pins_default: csi1-gpio-pins-default {
+ pinctrl-single,pins = <
+ //J721E_IOPAD(0x198, PIN_OUTPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+ J721E_IOPAD(0x1b0, PIN_OUTPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ >;
+ };
+};
+
+&main_i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_imx219: csi1_sensor@10 {
+ status = "okay";
+ compatible = "sony,imx219";
+ reg = <0x10>;
+
+ clocks = <&clk_csi1_imx219_fixed>;
+ clock-names = "xclk";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi1_gpio_pins_default>;
+ //reset-gpios = <&main_gpio0 101 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&main_gpio0 107 GPIO_ACTIVE_HIGH>;
+
+ port {
+ csi2rx1_cam0: endpoint {
+ remote-endpoint = <&csi2rx1_in_sensor>;
+ link-frequencies = /bits/ 64 <456000000>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&csi1_port0 {
+ status = "okay";
+ csi2rx1_in_sensor: endpoint {
+ remote-endpoint = <&csi2rx1_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BBAI64-DSI-RPi-7inch-panel.dts b/arch/arm64/boot/dts/ti/overlays/BBAI64-DSI-RPi-7inch-panel.dts
new file mode 100644
index 0000000000000..6b159379001ab
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BBAI64-DSI-RPi-7inch-panel.dts
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on
+ * beagleboneai64 board.
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/k3.h>
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BBAI64-DSI-RPi-7inch-panel.kernel = __TIMESTAMP__;
+ };
+};
+
+/ {
+ fragment@101 {
+ target-path = "/";
+
+ __overlay__ {
+ reg_bridge: reg_bridge@0 {
+ reg = <0 0 0x0 0x0>;
+ compatible = "regulator-fixed";
+ regulator-name = "bridge_reg";
+ gpio = <®_display 0 0>;
+ vin-supply = <®_display>;
+ enable-active-high;
+ };
+
+ panel_disp0: panel_disp1@0 {
+ reg = <0 0 0x0 0x0>;
+ compatible = "raspberrypi,7inch-dsi", "simple-panel";
+ backlight = <®_display>;
+ power-supply = <®_display>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&panel_bridge_out>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ main_i2c4_pins_default: main-i2c-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xa8, PIN_INPUT_PULLUP, 2) /* (AD19) PRG1_MDIO0_MDIO.I2C4_SCL */
+ J721E_IOPAD(0xac, PIN_INPUT_PULLUP, 2) /* (AD18) PRG1_MDIO0_MDC.I2C4_SDA */
+ >;
+ };
+};
+
+&main_i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
+
+ reg_display: reg_display@45 {
+ compatible = "raspberrypi,7inch-touchscreen-panel-regulator";
+ reg = <0x45>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ft5406: ts@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+
+ touchscreen-size-x = < 800 >;
+ touchscreen-size-y = < 480 >;
+
+ vcc-supply = <®_display>;
+ reset-gpio = <®_display 1 1>;
+
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+};
+
+&dsi0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_bridge_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+ };
+
+ bridge@0 {
+ compatible = "toshiba,tc358762";
+ reg = <0>;
+ vddc-supply = <®_bridge>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ panel_bridge_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ panel_bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BBAI64-P8_37-ehrpwm5_a.dts b/arch/arm64/boot/dts/ti/overlays/BBAI64-P8_37-ehrpwm5_a.dts
new file mode 100644
index 0000000000000..b3238e00c8520
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BBAI64-P8_37-ehrpwm5_a.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BBAI64-P8_37-ehrpwm5_a.kernel = __TIMESTAMP__;
+ };
+};
+
+&main_ehrpwm5 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BBAI64-P9_25-ehrpwm4_b.dts b/arch/arm64/boot/dts/ti/overlays/BBAI64-P9_25-ehrpwm4_b.dts
new file mode 100644
index 0000000000000..354d88a2a9be4
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BBAI64-P9_25-ehrpwm4_b.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BBAI64-P9_25-ehrpwm4_b.kernel = __TIMESTAMP__;
+ };
+};
+
+&main_ehrpwm4 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BBORG_LOAD-00A2.dts b/arch/arm64/boot/dts/ti/overlays/BBORG_LOAD-00A2.dts
new file mode 100644
index 0000000000000..8031957834a16
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BBORG_LOAD-00A2.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2020 - 2022 Deepak Khatri <lorforlinux@beagleboard.org>
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://docs.beagleboard.org/0.0/boards/capes/cape-interface-spec.html#beaglebone-cape-interface-spec
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BBORG_LOAD-00A2 = __TIMESTAMP__;
+ };
+};
+
+/*
+ * Update the default pinmux of the pins.
+ * See these files for the phandles (&P9_* & &P8_*)
+ * BeagleBoard-DeviceTrees/v5.10.x-ti-unified/src/arm/am335x-bone-common-univ.dtsi
+ * BeagleBoard-DeviceTrees/v5.10.x-ti-unified/src/arm/am572x-bone-common-univ.dtsi
+ * BeagleBoard-DeviceTrees/v5.10.x-ti-unified/src/arm64/k3-j721e-beagleboneai64-bone-buses.dtsi
+ */
+&ocp {
+ P9_42_pinmux { pinctrl-0 = <&P9_42_gpio_pin>; }; /* Sink1 */
+ P9_41_pinmux { pinctrl-0 = <&P9_41_gpio_pin>; }; /* Sink2 */
+ P9_30_pinmux { pinctrl-0 = <&P9_30_gpio_pin>; }; /* Sink3 */
+ P9_27_pinmux { pinctrl-0 = <&P9_27_gpio_pin>; }; /* Sink4 */
+ P8_12_pinmux { pinctrl-0 = <&P8_12_gpio_pin>; }; /* Sink5 */
+ P8_11_pinmux { pinctrl-0 = <&P8_11_gpio_pin>; }; /* Sink6 */
+ P8_15_pinmux { pinctrl-0 = <&P8_15_gpio_pin>; }; /* Sink7 */
+ P8_17_pinmux { pinctrl-0 = <&P8_17_gpio_pin>; }; /* Sink8 */
+};
+
+/*
+ * Easy load control through sysfs (/sys/class/leds/) using gpio-leds driver
+ * See these files for the led_P8_#/led_P9_# definition
+ * https://git.beagleboard.org/beagleboard/BeagleBoard-DeviceTrees/-/blob/v5.10.x-ti-unified/src/arm/bbai-bone-buses.dtsi
+ * https://git.beagleboard.org/beagleboard/BeagleBoard-DeviceTrees/-/blob/v5.10.x-ti-unified/src/arm/bbb-bone-buses.dtsi
+ * https://git.beagleboard.org/beagleboard/BeagleBoard-DeviceTrees/-/blob/v5.10.x-ti-unified/src/arm64/k3-j721e-beagleboneai64-bone-buses.dtsi
+ *
+ */
+
+&bone_led_P9_42 {
+ status = "okay";
+ label = "load-sink1";
+ default-state = "keep";
+};
+
+&bone_led_P9_41 {
+ status = "okay";
+ label = "load-sink2";
+ default-state = "keep";
+};
+
+&bone_led_P9_30 {
+ status = "okay";
+ label = "load-sink3";
+ default-state = "keep";
+};
+
+&bone_led_P9_27 {
+ status = "okay";
+ label = "load-sink4";
+ default-state = "keep";
+};
+
+&bone_led_P8_12 {
+ status = "okay";
+ label = "load-sink5";
+ default-state = "keep";
+};
+
+&bone_led_P8_11 {
+ status = "okay";
+ label = "load-sink6";
+ default-state = "keep";
+};
+
+&bone_led_P8_15 {
+ status = "okay";
+ label = "load-sink7";
+ default-state = "keep";
+};
+
+&bone_led_P8_17 {
+ status = "okay";
+ label = "load-sink8";
+ default-state = "keep";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BBORG_RELAY-00A2.dts b/arch/arm64/boot/dts/ti/overlays/BBORG_RELAY-00A2.dts
new file mode 100644
index 0000000000000..1574691daaa1c
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BBORG_RELAY-00A2.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015 Robert Nelson <robertcnelson@gmail.com>
+ * Copyright (C) 2019 Amilcar Lucas <amilcar.lucas@iav.de>
+ * Copyright (C) 2020 - 2022 Deepak Khatri <lorforlinux@beagleboard.org>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/chosen} {
+ overlays {
+ BBORG_RELAY-00A2.kernel = __TIMESTAMP__;
+ };
+};
+
+&ocp {
+ P9_41_pinmux { pinctrl-0 = <&P9_41_gpio_pin>;};
+ P9_42_pinmux { pinctrl-0 = <&P9_42_gpio_pin>;};
+ P9_30_pinmux { pinctrl-0 = <&P9_30_gpio_pin>;};
+ P9_27_pinmux { pinctrl-0 = <&P9_27_gpio_pin>;};
+};
+
+// relay1
+&bone_led_P9_41 {
+ status = "okay";
+ // access: sys/class/leds/relay1
+ label = "relay1";
+ default-state = "keep";
+};
+
+// relay2
+&bone_led_P9_42 {
+ status = "okay";
+ // access: sys/class/leds/relay2
+ label = "relay2";
+ default-state = "keep";
+};
+
+// realy3
+&bone_led_P9_30 {
+ status = "okay";
+ // access: sys/class/leds/relay3
+ label = "relay3";
+ default-state = "keep";
+};
+
+// realy4
+&bone_led_P9_27 {
+ status = "okay";
+ // access: sys/class/leds/relay4
+ label = "relay4";
+ default-state = "keep";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-FAN.dts b/arch/arm64/boot/dts/ti/overlays/BONE-FAN.dts
new file mode 100644
index 0000000000000..504524514ed27
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-FAN.dts
@@ -0,0 +1,139 @@
+
+// SPDX-License-Identifier: GPL-2.0
+/*
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/k3.h>
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-FAN = __TIMESTAMP__;
+ };
+};
+
+&ehrpwm3_pins_default{
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x18c, PIN_OUTPUT, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */
+ J721E_IOPAD(0x190, PIN_OUTPUT, 6) /* (W23) RGMII6_TD3.EHRPWM3_B */
+ J721E_IOPAD(0x194, PIN_INPUT_PULLUP, 7) /* (W28) RGMII6_TD2.GPIO0_100 */
+ >;
+};
+
+&main_ehrpwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ehrpwm3_pins_default>;
+ status = "okay";
+};
+
+&{/} {
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ pwms = <&main_ehrpwm3 1 40000 0>;
+ cooling-levels = <100 140 180 220 254>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <100 1>;
+ pulses-per-revolution = <2>;
+ };
+};
+
+&thermal_zones{
+ wkup_thermal: wkup-thermal {
+ trips {
+ wkup_active1: wkup-active1 {
+ temperature = <35000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "active";
+ };
+ wkup_active2: wkup-active2 {
+ temperature = <42000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "active";
+ };
+ wkup_active3: wkup-active3 {
+ temperature = <50000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "active";
+ };
+ wkup_hot: wkup-hot {
+ temperature = <72000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "hot";
+ };
+ wkup_crit: wkup-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&wkup_active1>;
+ cooling-device = <&fan0 0 0>;
+ };
+ map2 {
+ trip = <&wkup_active2>;
+ cooling-device = <&fan0 0 1>;
+ };
+ map3 {
+ trip = <&wkup_active3>;
+ cooling-device = <&fan0 0 2>;
+ };
+ map4 {
+ trip = <&wkup_hot>;
+ cooling-device = <&fan0 0 3>;
+ };
+ map5 {
+ trip = <&wkup_crit>;
+ cooling-device = <&fan0 0 4>;
+ };
+ };
+ };
+
+ mpu_thermal: mpu-thermal {
+ trips {
+ mpu_crit: mpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ c7x_thermal: c7x-thermal {
+ trips {
+ c7x_crit: c7x-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ trips {
+ gpu_crit: gpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ r5f_thermal: r5f-thermal {
+ trips {
+ r5f_crit: r5f-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-I2C1.dts b/arch/arm64/boot/dts/ti/overlays/BONE-I2C1.dts
new file mode 100644
index 0000000000000..267835e09eb78
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-I2C1.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#I2C
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-I2C1.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_i2c_1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-I2C2.dts b/arch/arm64/boot/dts/ti/overlays/BONE-I2C2.dts
new file mode 100644
index 0000000000000..413f4a152f004
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-I2C2.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#I2C
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-I2C2.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_i2c_2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-I2C3.dts b/arch/arm64/boot/dts/ti/overlays/BONE-I2C3.dts
new file mode 100644
index 0000000000000..b5006a2983577
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-I2C3.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#I2C
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-I2C3.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_i2c_3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-PWM0.dts b/arch/arm64/boot/dts/ti/overlays/BONE-PWM0.dts
new file mode 100644
index 0000000000000..a9168adca9280
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-PWM0.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#PWM
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-PWM0.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_pwm_0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-PWM1.dts b/arch/arm64/boot/dts/ti/overlays/BONE-PWM1.dts
new file mode 100644
index 0000000000000..21790c3909f22
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-PWM1.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#PWM
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-PWM1.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_pwm_1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-PWM2.dts b/arch/arm64/boot/dts/ti/overlays/BONE-PWM2.dts
new file mode 100644
index 0000000000000..8519342a5b4f9
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-PWM2.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#PWM
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-PWM2.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_pwm_2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-SPI0_0.dts b/arch/arm64/boot/dts/ti/overlays/BONE-SPI0_0.dts
new file mode 100644
index 0000000000000..c8f862bdea641
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-SPI0_0.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#SPI
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-SPI0_0.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_spi_0 {
+ /* tested with: sudo ./spidev_test -v --device /dev/spidev0.0 */
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_17_spi_pin /* spi6_cs0 */
+ &P9_22_spi_pin /* spi6_clk */
+ &P9_21_spi_pin /* spi6_d0 */
+ &P9_18_spi_pin /* spi6_d1 */
+ >;
+ ti,spi-num-cs = <1>;
+ ti,pindir-d0-out-d1-in;
+
+ status = "okay";
+
+ spidev@0 {
+ symlink = "bone/spi/0.0";
+ compatible = "rohm,dh2228fv";
+ reg = <0>; /* CE0 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <125000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-SPI0_1.dts b/arch/arm64/boot/dts/ti/overlays/BONE-SPI0_1.dts
new file mode 100644
index 0000000000000..be7ee1f94919f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-SPI0_1.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#SPI
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-SPI0_1.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_spi_0 {
+ /* tested with: sudo ./spidev_test -v --device /dev/spidev0.1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P9_23_spi_pin /* spi6_cs1 */
+ &P9_22_spi_pin /* spi6_clk */
+ &P9_21_spi_pin /* spi6_d0 */
+ &P9_18_spi_pin /* spi6_d1 */
+ >;
+ ti,spi-num-cs = <2>;
+ ti,pindir-d0-out-d1-in;
+
+ status = "okay";
+
+ spidev@1 {
+ symlink = "bone/spi/0.1";
+ compatible = "rohm,dh2228fv";
+ reg = <1>; /* CE1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <125000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-UART1.dts b/arch/arm64/boot/dts/ti/overlays/BONE-UART1.dts
new file mode 100644
index 0000000000000..adc504d6826f6
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-UART1.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ *
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec#UART
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-UART1.kernel = __TIMESTAMP__;
+ };
+};
+
+&bone_uart_1 {
+ /* tested with sudo agetty 115200 ttyS4 */
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/BONE-USB0-host.dts b/arch/arm64/boot/dts/ti/overlays/BONE-USB0-host.dts
new file mode 100644
index 0000000000000..8fb94e1a5e9ea
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/BONE-USB0-host.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BeagleBoard.org - https://beagleboard.org/
+ */
+
+/dts-v1/;
+/plugin/;
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ BONE-USB0-host.kernel = __TIMESTAMP__;
+ };
+};
+
+&usb0 {
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/J721E-PRU-UIO-00A0.dts b/arch/arm64/boot/dts/ti/overlays/J721E-PRU-UIO-00A0.dts
new file mode 100644
index 0000000000000..bd71b6f6099ec
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/J721E-PRU-UIO-00A0.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ J721E-PRU-UIO-00A0.kernel = __TIMESTAMP__;
+ };
+};
+
+&icssg0 {
+ compatible = "ti,pruss-v2";
+ ti,pintc-offset = <0x20000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ pruss-instance = "pruss0";
+};
+
+&icssg1 {
+ compatible = "ti,pruss-v2";
+ ti,pintc-offset = <0x20000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ pruss-instance = "pruss1";
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/Makefile b/arch/arm64/boot/dts/ti/overlays/Makefile
new file mode 100644
index 0000000000000..76803ef953811
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/Makefile
@@ -0,0 +1,31 @@
+# Overlays for the BeagleBone platform
+
+dtbo-$(CONFIG_ARCH_K3) += \
+ BB-I2C2-MPU6050.dtbo \
+ BBAI64-CSI0-imx219.dtbo \
+ BBAI64-CSI1-imx219.dtbo \
+ BBAI64-DSI-RPi-7inch-panel.dtbo \
+ BBAI64-P8_37-ehrpwm5_a.dtbo \
+ BBAI64-P9_25-ehrpwm4_b.dtbo \
+ BBORG_RELAY-00A2.dtbo \
+ BBORG_LOAD-00A2.dtbo \
+ BONE-I2C1.dtbo \
+ BONE-I2C2.dtbo \
+ BONE-I2C3.dtbo \
+ BONE-FAN.dtbo \
+ BONE-PWM0.dtbo \
+ BONE-PWM1.dtbo \
+ BONE-PWM2.dtbo \
+ BONE-SPI0_0.dtbo \
+ BONE-SPI0_1.dtbo \
+ BONE-UART1.dtbo \
+ BONE-USB0-host.dtbo \
+ robotics-cape.dtbo \
+ k3-j721e-beagleboneai64-RPi-7inch-panel.dtbo \
+ J721E-PRU-UIO-00A0.dtbo
+
+targets += dtbs dtbs_install
+targets += $(dtbo-y)
+
+always-y := $(dtbo-y)
+clean-files := *.dtbo
diff --git a/arch/arm64/boot/dts/ti/overlays/k3-j721e-beagleboneai64-RPi-7inch-panel.dts b/arch/arm64/boot/dts/ti/overlays/k3-j721e-beagleboneai64-RPi-7inch-panel.dts
new file mode 100644
index 0000000000000..efd1237a5de1d
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/k3-j721e-beagleboneai64-RPi-7inch-panel.dts
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for RPi 7inch touchscreen panel interfaced with DSI on
+ * beagleboneai64 board.
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/k3.h>
+
+/*
+ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
+ */
+&{/chosen} {
+ overlays {
+ k3-j721e-beagleboneai64-RPi-7inch-panel.kernel = __TIMESTAMP__;
+ };
+};
+
+/ {
+ fragment@101 {
+ target-path = "/";
+
+ __overlay__ {
+ reg_bridge: reg_bridge@0 {
+ reg = <0 0 0x0 0x0>;
+ compatible = "regulator-fixed";
+ regulator-name = "bridge_reg";
+ gpio = <®_display 0 0>;
+ vin-supply = <®_display>;
+ enable-active-high;
+ };
+
+ panel_disp0: panel_disp1@0 {
+ reg = <0 0 0x0 0x0>;
+ compatible = "raspberrypi,7inch-dsi", "simple-panel";
+ backlight = <®_display>;
+ power-supply = <®_display>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&panel_bridge_out>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ main_i2c4_pins_default: main-i2c-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xa8, PIN_INPUT_PULLUP, 2) /* (AD19) PRG1_MDIO0_MDIO.I2C4_SCL */
+ J721E_IOPAD(0xac, PIN_INPUT_PULLUP, 2) /* (AD18) PRG1_MDIO0_MDC.I2C4_SDA */
+ >;
+ };
+};
+
+&main_i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
+
+ reg_display: reg_display@45 {
+ compatible = "raspberrypi,7inch-touchscreen-panel-regulator";
+ reg = <0x45>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ft5406: ts@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+
+ touchscreen-size-x = < 800 >;
+ touchscreen-size-y = < 480 >;
+
+ vcc-supply = <®_display>;
+ reset-gpio = <®_display 1 1>;
+
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+};
+
+&dsi0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_bridge_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+ };
+
+ bridge@0 {
+ compatible = "toshiba,tc358762";
+ reg = <0>;
+ vddc-supply = <®_bridge>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ panel_bridge_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ panel_bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/ti/overlays/robotics-cape.dts b/arch/arm64/boot/dts/ti/overlays/robotics-cape.dts
new file mode 100644
index 0000000000000..62808947a6a4a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/overlays/robotics-cape.dts
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/board/k3-j721e-bone-pins.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+&{/chosen} {
+ overlays {
+ BB-ROBOTICS-CAPE-00B0.kernel = __TIMESTAMP__;
+ };
+};
+
+&{/} {
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ cape_btn0: cape_btn0 {
+ label = "MODE";
+ linux,code = <KEY_MODE>;
+ gpios = <gpio_P9_31 GPIO_ACTIVE_LOW>;
+ };
+
+ cape_btn1: cape_btn1 {
+ label = "PAUSE";
+ linux,code = <KEY_PAUSE>;
+ gpios = <gpio_P9_41 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&bone_led_P9_14 {
+ status = "okay";
+ label = "green";
+ linux,default-trigger = "default-off";
+};
+
+&bone_led_P9_16 {
+ status = "okay";
+ label = "red";
+ linux,default-trigger = "default-off";
+};
+
+&bone_led_P8_18 {
+ status = "okay";
+ label = "bat25";
+ linux,default-trigger = "default-off";
+};
+
+&bone_led_P8_13 {
+ status = "okay";
+ label = "bat75";
+ linux,default-trigger = "default-off";
+};
+
+&bone_led_P8_21 {
+ status = "okay";
+ label = "capture_oe1";
+ linux,default-trigger = "default-off";
+ gpios = <gpio_P8_21 GPIO_ACTIVE_LOW>;
+};
+
+&bone_led_P8_23 {
+ status = "okay";
+ label = "capture_oe2";
+ linux,default-trigger = "default-on";
+ gpios = <gpio_P8_23 GPIO_ACTIVE_LOW>;
+};
+
+&cape_header {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &P8_03_gpio_pin /* Motor1_SLP# */
+ &P8_05_gpio_pin /* Motor1_FAULT# */
+ &P8_07_gpio_pin /* Motor1_OC# */
+ &P8_09_gpio_pin /* Motor4_FAULT# */
+ &P8_11_pruout_pin /* Motor4_PWM */
+ &P8_13_gpio_pin /* LED4 */
+ &P8_15_pruin_pin /* Capture4 */
+ &P8_17_gpio_pd_pin /* Motor4_IN1 */
+ &P8_19_gpio_pd_pin /* Motor4_IN2 */
+ &P8_21_gpio_pd_pin /* CAP_OE#1 */
+ &P8_23_gpio_pd_pin /* CAP_OE#2 */
+ &P8_25_pruin_pin /* Ultrasonic1 */
+ &P8_27_pruin_pin /* Ultrasonic2 */
+ &P8_29_uart_pin /* Lidar_RX - UART8_TX */
+ &P8_31_gpio_pin /* Motor3_FAULT# */
+ &P8_33_qep_pin /* QEP2_B - EQEP1_B */
+ &P8_35_qep_pin /* QEP2_A - EQEP1_A */
+ &P8_37_pruin_pin /* Ultrasonic3 */
+ &P8_39_pruin_pin /* Ultrasonic4 */
+ &P8_41_pruout_pin /* Servo7 */
+ &P8_43_pruout_pin /* Servo8 */
+ &P8_45_pruout_pin /* Servo9 */
+
+ &P8_04_pruout_pin /* Motor1_PWM */
+ &P8_06_gpio_pd_pin /* Motor1_IN1 */
+ &P8_08_gpio_pd_pin /* Motor1_IN2 */
+ &P8_10_gpio_pd_pin /* Motor3_IN1 */
+ &P8_12_pruout_pin /* Motor3_PWM */
+ &P8_14_pruout_pin /* Servo2 */
+ &P8_16_gpio_pd_pin /* Motor3_IN */
+ &P8_18_gpio_pin /* LED3 */
+ &P8_20_pruout_pin /* Servo5 */
+ &P8_22_uart_pin /* BCF_SERIAL_TX - UART2_RX */
+ &P8_24_pruout_pin /* Lidar_PWM */
+ &P8_26_pruout_pin /* Servo6 */
+ &P8_28_uart_pin /* Lidar_TX - UART8_RX */
+ &P8_30_gpio_pin /* Lidar_OE */
+ &P8_32_gpio_pin /* BCF_RST */
+ &P8_34_uart_pin /* BCF_SERIAL_RX - UART2_TX */
+ &P8_36_gpio_pin /* 6DOF_INT */
+ &P8_38_gpio_pd_pin /* Motor2_IN1 */
+ &P8_40_gpio_pd_pin /* Motor2_IN2 */
+ &P8_42_gpio_pin /* Motor234_nSLEEP */
+ &P8_44_gpio_pin /* Magnetometer_INT */
+
+ &P9_11_gpio_pin /* Motor2_FAULT# */
+ &P9_13_pruout_pin /* Motor2_PWM */
+ &P9_15_pruout_pin /* Servo10 */
+ &P9_17_spi_pin /* Barometer_CS# - SPI6_CS0 */
+ &P9_19_pruout_pin /* Servo1 */
+ &P9_21_spi_pin /* SPI6_D0 - SDO */
+ &P9_23_spi_pin /* IMU_CS# - SPI6_CS1 */
+ &P9_25_gpio_pin /* Magnetometer_CS# */
+ &P9_27_qep_pin /* QEP1_B - EQEP0_B */
+ &P9_29_pruin_pin /* Capture3 */
+ &P9_31_gpio_pin /* USER_BUTTON1 - MODE */
+ &P9_33_default_pin /* Motor2_Current - AIN4 */
+ &P9_35_default_pin /* Motor3_Current - AIN6 */
+ &P9_37_uart_pin /* GPS_TXD */
+ &P9_39_default_pin /* Battery_Voltage - AIN0 */
+ &P9_41_gpio_pin /* USER_BUTTON2 - PAUSE */
+
+ &P9_12_pruout_pin /* Servo4 */
+ &P9_14_gpio_pin /* LED1 */
+ &P9_16_gpio_pin /* LED2 */
+ &P9_18_spi_pin /* SPI6_D1 - SDI */
+ &P9_20_pruout_pin /* Servo3 */
+ &P9_22_spi_pin /* SPI6_CLK */
+ &P9_24_i2c_pin /* EEPROM_I2C_SCL */
+ &P9_26_i2c_pin /* EEPROM_I2C_SDA */
+ &P9_28_pruin_pin /* Capture1 */
+ &P9_30_pruin_pin /* Capture2 */
+ &P9_36_default_pin /* Motor4_Current - AIN5 */
+ &P9_38_uart_pin /* GPS_RXD */
+ &P9_40_default_pin /* Motor1_Current - AIN1 */
+ &P9_42_qep_pin /* QEP1_A - EQEP0_A */
+ >;
+};
+
+&bone_spi_0 {
+ ti,spi-num-cs = <3>;
+ ti,pindir-d0-out-d1-in;
+ cs-gpios = <0>, /* P9_17 */
+ <0>, /* P9_23 */
+ <gpio_P9_25 GPIO_ACTIVE_LOW>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@0 {
+ compatible = "bosch,bmp280";
+ reg = <0>; /* CE0 */
+ spi-max-frequency = <5000000>;
+ };
+
+ imu@1 {
+ compatible = "st,lsm6ds3tr-c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>; /* CE1 */
+ spi-max-frequency = <5000000>;
+ };
+
+ magn@2 {
+ compatible = "bosch,bmm150_magn";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>; /* CE2 */
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* TODO: the base for this should be in the board DT */
+ eqep0: qep@3200000 {
+ compatible = "ti,am3352-eqep";
+ reg = <0 0x3200000 0 0x100>;
+ power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 94 0>;
+ clock-names = "eqep0-ficlk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eqep0";
+ symlink = "bone/qep/0"; /* A - P9_42, B - P9_27 */
+
+ count_mode = <0>;
+ swap_input = <0>;
+ invert_qa = <1>;
+ invert_qb = <1>;
+ invert_qi = <0>;
+ invert_qs = <0>;
+ };
+
+ eqep1: qep@3210000 {
+ compatible = "ti,am3352-eqep";
+ reg = <0 0x3210000 0 0x100>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 95 0>;
+ clock-names = "eqep1-ficlk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eqep1";
+ symlink = "bone/qep/1"; /* A - P8_35, B - P8_33 */
+
+ count_mode = <0>;
+ swap_input = <0>;
+ invert_qa = <1>;
+ invert_qb = <1>;
+ invert_qi = <0>;
+ invert_qs = <0>;
+ };
+
+ eqep2: qep@3220000 {
+ status = "disabled";
+ compatible = "ti,am3352-eqep";
+ reg = <0 0x3220000 0 0x100>;
+ power-domains = <&k3_pds 96 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 96 0>;
+ clock-names = "eqep2-ficlk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eqep2";
+
+ count_mode = <0>;
+ swap_input = <0>;
+ invert_qa = <1>;
+ invert_qb = <1>;
+ invert_qi = <0>;
+ invert_qs = <0>;
+ };
+};
+
+/* TODO: this is not the standard bone/uart/1 pinout location */
+&bone_uart_1 {
+ status = "okay";
+
+ bcfserial {
+ compatible = "beagle,bcfserial";
+ };
+};
diff --git a/include/dt-bindings/board/am335x-bbw-bbb-base.h b/include/dt-bindings/board/am335x-bbw-bbb-base.h
new file mode 100644
index 0000000000000..35f6d57ef4923
--- /dev/null
+++ b/include/dt-bindings/board/am335x-bbw-bbb-base.h
@@ -0,0 +1,103 @@
+/*
+ * This header provides constants for bbw/bbb pinctrl bindings.
+ *
+ * Copyright (C) 2014 Robert Nelson <robertcnelson@gmail.com>
+ *
+ * Numbers Based on: https://github.com/derekmolloy/boneDeviceTree/tree/master/docs
+ */
+
+#ifndef _DT_BINDINGS_BOARD_AM335X_BBW_BBB_BASE_H
+#define _DT_BINDINGS_BOARD_AM335X_BBW_BBB_BASE_H
+
+#define BONE_P8_03 0x018
+#define BONE_P8_04 0x01C
+
+#define BONE_P8_05 0x008
+#define BONE_P8_06 0x00C
+#define BONE_P8_07 0x090
+#define BONE_P8_08 0x094
+
+#define BONE_P8_09 0x09C
+#define BONE_P8_10 0x098
+#define BONE_P8_11 0x034
+#define BONE_P8_12 0x030
+
+#define BONE_P8_13 0x024
+#define BONE_P8_14 0x028
+#define BONE_P8_15 0x03C
+#define BONE_P8_16 0x038
+
+#define BONE_P8_17 0x02C
+#define BONE_P8_18 0x08C
+#define BONE_P8_19 0x020
+#define BONE_P8_20 0x084
+
+#define BONE_P8_21 0x080
+#define BONE_P8_22 0x014
+#define BONE_P8_23 0x010
+#define BONE_P8_24 0x004
+
+#define BONE_P8_25 0x000
+#define BONE_P8_26 0x07C
+#define BONE_P8_27 0x0E0
+#define BONE_P8_28 0x0E8
+
+#define BONE_P8_29 0x0E4
+#define BONE_P8_30 0x0EC
+#define BONE_P8_31 0x0D8
+#define BONE_P8_32 0x0DC
+
+#define BONE_P8_33 0x0D4
+#define BONE_P8_34 0x0CC
+#define BONE_P8_35 0x0D0
+#define BONE_P8_36 0x0C8
+
+#define BONE_P8_37 0x0C0
+#define BONE_P8_38 0x0C4
+#define BONE_P8_39 0x0B8
+#define BONE_P8_40 0x0BC
+
+#define BONE_P8_41 0x0B0
+#define BONE_P8_42 0x0B4
+#define BONE_P8_43 0x0A8
+#define BONE_P8_44 0x0AC
+
+#define BONE_P8_45 0x0A0
+#define BONE_P8_46 0x0A4
+
+#define BONE_P9_11 0x070
+#define BONE_P9_12 0x078
+
+#define BONE_P9_13 0x074
+#define BONE_P9_14 0x048
+#define BONE_P9_15 0x040
+#define BONE_P9_16 0x04C
+
+#define BONE_P9_17 0x15C
+#define BONE_P9_18 0x158
+#define BONE_P9_19 0x17C
+#define BONE_P9_20 0x178
+
+#define BONE_P9_21 0x154
+#define BONE_P9_22 0x150
+#define BONE_P9_23 0x044
+#define BONE_P9_24 0x184
+
+#define BONE_P9_25 0x1AC
+#define BONE_P9_26 0x180
+#define BONE_P9_27 0x1A4
+#define BONE_P9_28 0x19C
+
+#define BONE_P9_29 0x194
+#define BONE_P9_30 0x198
+#define BONE_P9_31 0x190
+
+/* Shared P21 of P11 */
+#define BONE_P9_41A 0x1B4
+#define BONE_P9_41B 0x1A8
+
+/* Shared P22 of P11 */
+#define BONE_P9_42A 0x164
+#define BONE_P9_42B 0x1A0
+
+#endif
diff --git a/include/dt-bindings/board/am335x-bone-pins.h b/include/dt-bindings/board/am335x-bone-pins.h
new file mode 100644
index 0000000000000..54e92664ba793
--- /dev/null
+++ b/include/dt-bindings/board/am335x-bone-pins.h
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Deepak Khatri <deepaklorkhatri7@gmail.com>
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
+ */
+
+#ifndef _DT_BINDINGS_BOARD_AM335X_BONE_PINS_H
+#define _DT_BINDINGS_BOARD_AM335X_BONE_PINS_H
+
+#define bb_device 0
+#define board_soc AM335X
+
+#define gpio_P8_03 &gpio1 6
+#define gpio_P8_04 &gpio1 7
+#define gpio_P8_05 &gpio1 2
+#define gpio_P8_06 &gpio1 3
+#define gpio_P8_07 &gpio2 2
+#define gpio_P8_08 &gpio2 3
+#define gpio_P8_09 &gpio2 5
+#define gpio_P8_10 &gpio2 4
+#define gpio_P8_11 &gpio1 13
+#define gpio_P8_12 &gpio1 12
+#define gpio_P8_13 &gpio0 23
+#define gpio_P8_14 &gpio0 26
+#define gpio_P8_15 &gpio1 15
+#define gpio_P8_16 &gpio1 14
+#define gpio_P8_17 &gpio0 27
+#define gpio_P8_18 &gpio2 1
+#define gpio_P8_19 &gpio0 22
+#define gpio_P8_20 &gpio1 31
+#define gpio_P8_21 &gpio1 30
+#define gpio_P8_22 &gpio1 5
+#define gpio_P8_23 &gpio1 4
+#define gpio_P8_24 &gpio1 1
+#define gpio_P8_25 &gpio1 0
+#define gpio_P8_26 &gpio1 29
+#define gpio_P8_27 &gpio2 22
+#define gpio_P8_28 &gpio2 24
+#define gpio_P8_29 &gpio2 23
+#define gpio_P8_30 &gpio2 25
+#define gpio_P8_31 &gpio0 10
+#define gpio_P8_32 &gpio0 11
+#define gpio_P8_33 &gpio0 9
+#define gpio_P8_34 &gpio2 17
+#define gpio_P8_35 &gpio0 8
+#define gpio_P8_36 &gpio2 16
+#define gpio_P8_37 &gpio2 14
+#define gpio_P8_38 &gpio2 15
+#define gpio_P8_39 &gpio2 12
+#define gpio_P8_40 &gpio2 13
+#define gpio_P8_41 &gpio2 10
+#define gpio_P8_42 &gpio2 11
+#define gpio_P8_43 &gpio2 8
+#define gpio_P8_44 &gpio2 9
+#define gpio_P8_45 &gpio2 6
+#define gpio_P8_46 &gpio2 7
+#define gpio_P9_11 &gpio0 30
+#define gpio_P9_12 &gpio1 28
+#define gpio_P9_13 &gpio0 31
+#define gpio_P9_14 &gpio1 18
+#define gpio_P9_15 &gpio1 16
+#define gpio_P9_16 &gpio1 19
+#define gpio_P9_17 &gpio0 5
+#define gpio_P9_18 &gpio0 4
+#define gpio_P9_19 &gpio0 13
+#define gpio_P9_20 &gpio0 12
+#define gpio_P9_21 &gpio0 3
+#define gpio_P9_22 &gpio0 2
+#define gpio_P9_23 &gpio1 17
+#define gpio_P9_24 &gpio0 15
+#define gpio_P9_25 &gpio3 21
+#define gpio_P9_26 &gpio0 14
+#define gpio_P9_27 &gpio3 19
+#define gpio_P9_28 &gpio3 17
+#define gpio_P9_29 &gpio3 15
+#define gpio_P9_30 &gpio3 16
+#define gpio_P9_31 &gpio3 14
+#define gpio_P9_41 &gpio0 20
+#define gpio_P9_41A &gpio0 20
+#define gpio_P9_41B &gpio3 20
+#define gpio_P9_91 &gpio3 20
+#define gpio_P9_42 &gpio0 7
+#define gpio_P9_42A &gpio0 7
+#define gpio_P9_42B &gpio3 18
+#define gpio_P9_92 &gpio3 18
+#define gpio_A15 &gpio0 19
+
+#define P8_03(mode) AM33XX_IOPAD(0x0818, mode) /* R9: gpmc_ad6 */
+#define P8_04(mode) AM33XX_IOPAD(0x081c, mode) /* T9: gpmc_ad7 */
+#define P8_05(mode) AM33XX_IOPAD(0x0808, mode) /* R8: gpmc_ad2 */
+#define P8_06(mode) AM33XX_IOPAD(0x080c, mode) /* T8: gpmc_ad3 */
+#define P8_07(mode) AM33XX_IOPAD(0x0890, mode) /* R7: gpmc_advn_ale */
+#define P8_08(mode) AM33XX_IOPAD(0x0894, mode) /* T7: gpmc_oen_ren */
+#define P8_09(mode) AM33XX_IOPAD(0x089c, mode) /* T6: gpmc_be0n_cle */
+#define P8_10(mode) AM33XX_IOPAD(0x0898, mode) /* U6: gpmc_wen */
+#define P8_11(mode) AM33XX_IOPAD(0x0834, mode) /* R12: gpmc_ad13 */
+#define P8_12(mode) AM33XX_IOPAD(0x0830, mode) /* T12: gpmc_ad12 */
+#define P8_13(mode) AM33XX_IOPAD(0x0824, mode) /* T10: gpmc_ad9 */
+#define P8_14(mode) AM33XX_IOPAD(0x0828, mode) /* T11: gpmc_ad10 */
+#define P8_15(mode) AM33XX_IOPAD(0x083c, mode) /* U13: gpmc_ad15 */
+#define P8_16(mode) AM33XX_IOPAD(0x0838, mode) /* V13: gpmc_ad14 */
+#define P8_17(mode) AM33XX_IOPAD(0x082c, mode) /* U12: gpmc_ad11 */
+#define P8_18(mode) AM33XX_IOPAD(0x088c, mode) /* V12: gpmc_clk */
+#define P8_19(mode) AM33XX_IOPAD(0x0820, mode) /* U10: gpmc_ad8 */
+#define P8_20(mode) AM33XX_IOPAD(0x0884, mode) /* V9: gpmc_csn2 */
+#define P8_21(mode) AM33XX_IOPAD(0x0880, mode) /* U9: gpmc_csn1 */
+#define P8_22(mode) AM33XX_IOPAD(0x0814, mode) /* V8: gpmc_ad5 */
+#define P8_23(mode) AM33XX_IOPAD(0x0810, mode) /* U8: gpmc_ad4 */
+#define P8_24(mode) AM33XX_IOPAD(0x0804, mode) /* V7: gpmc_ad1 */
+#define P8_25(mode) AM33XX_IOPAD(0x0800, mode) /* U7: gpmc_ad0 */
+#define P8_26(mode) AM33XX_IOPAD(0x087c, mode) /* V6: gpmc_csn0 */
+#define P8_27(mode) AM33XX_IOPAD(0x08e0, mode) /* U5: lcd_vsync */
+#define P8_28(mode) AM33XX_IOPAD(0x08e8, mode) /* V5: lcd_pclk */
+#define P8_29(mode) AM33XX_IOPAD(0x08e4, mode) /* R5: lcd_hsync */
+#define P8_30(mode) AM33XX_IOPAD(0x08ec, mode) /* R6: lcd_ac_bias_en */
+#define P8_31(mode) AM33XX_IOPAD(0x08d8, mode) /* V4: lcd_data14 */
+#define P8_32(mode) AM33XX_IOPAD(0x08dc, mode) /* T5: lcd_data15 */
+#define P8_33(mode) AM33XX_IOPAD(0x08d4, mode) /* V3: lcd_data13 */
+#define P8_34(mode) AM33XX_IOPAD(0x08cc, mode) /* U4: lcd_data11 */
+#define P8_35(mode) AM33XX_IOPAD(0x08d0, mode) /* V2: lcd_data12 */
+#define P8_36(mode) AM33XX_IOPAD(0x08c8, mode) /* U3: lcd_data10 */
+#define P8_37(mode) AM33XX_IOPAD(0x08c0, mode) /* U1: lcd_data8 */
+#define P8_38(mode) AM33XX_IOPAD(0x08c4, mode) /* U2: lcd_data9 */
+#define P8_39(mode) AM33XX_IOPAD(0x08b8, mode) /* T3: lcd_data6 */
+#define P8_40(mode) AM33XX_IOPAD(0x08bc, mode) /* T4: lcd_data7 */
+#define P8_41(mode) AM33XX_IOPAD(0x08b0, mode) /* T1: lcd_data4 */
+#define P8_42(mode) AM33XX_IOPAD(0x08b4, mode) /* T2: lcd_data5 */
+#define P8_43(mode) AM33XX_IOPAD(0x08a8, mode) /* R3: lcd_data2 */
+#define P8_44(mode) AM33XX_IOPAD(0x08ac, mode) /* R4: lcd_data3 */
+#define P8_45(mode) AM33XX_IOPAD(0x08a0, mode) /* R1: lcd_data0 */
+#define P8_46(mode) AM33XX_IOPAD(0x08a4, mode) /* R2: lcd_data1 */
+#define P9_11(mode) AM33XX_IOPAD(0x0870, mode) /* T17: gpmc_wait0 */
+#define P9_12(mode) AM33XX_IOPAD(0x0878, mode) /* U18: gpmc_be1n */
+#define P9_13(mode) AM33XX_IOPAD(0x0874, mode) /* U17: gpmc_wpn */
+#define P9_14(mode) AM33XX_IOPAD(0x0848, mode) /* U14: gpmc_a2 */
+#define P9_15(mode) AM33XX_IOPAD(0x0840, mode) /* R13: gpmc_a0 */
+#define P9_16(mode) AM33XX_IOPAD(0x084c, mode) /* T14: gpmc_a3 */
+#define P9_17(mode) AM33XX_IOPAD(0x095c, mode) /* A16: spi0_cs0 */
+#define P9_18(mode) AM33XX_IOPAD(0x0958, mode) /* B16: spi0_d1 */
+#define P9_19(mode) AM33XX_IOPAD(0x097c, mode) /* D17: uart1_rtsn */
+#define P9_20(mode) AM33XX_IOPAD(0x0978, mode) /* D18: uart1_ctsn */
+#define P9_21(mode) AM33XX_IOPAD(0x0954, mode) /* B17: spi0_d0 */
+#define P9_22(mode) AM33XX_IOPAD(0x0950, mode) /* A17: spi0_sclk */
+#define P9_23(mode) AM33XX_IOPAD(0x0844, mode) /* V14: gpmc_a1 */
+#define P9_24(mode) AM33XX_IOPAD(0x0984, mode) /* D15: uart1_txd */
+#define P9_25(mode) AM33XX_IOPAD(0x09ac, mode) /* A14: mcasp0_ahclkx */
+#define P9_26(mode) AM33XX_IOPAD(0x0980, mode) /* D16: uart1_rxd */
+#define P9_27(mode) AM33XX_IOPAD(0x09a4, mode) /* C13: mcasp0_fsr */
+#define P9_28(mode) AM33XX_IOPAD(0x099c, mode) /* C12: mcasp0_ahclkr */
+#define P9_29(mode) AM33XX_IOPAD(0x0994, mode) /* B13: mcasp0_fsx */
+#define P9_30(mode) AM33XX_IOPAD(0x0998, mode) /* D12: mcasp0_axr0 */
+#define P9_31(mode) AM33XX_IOPAD(0x0990, mode) /* A13: mcasp0_aclkx */
+#define P9_41(mode) AM33XX_IOPAD(0x09b4, mode) /* D14: xdma_event_intr1 */
+#define P9_41A(mode) AM33XX_IOPAD(0x09b4, mode) /* D14: xdma_event_intr1 */
+#define P9_41B(mode) AM33XX_IOPAD(0x09a8, mode) /* D13: mcasp0_axr1 */
+#define P9_91(mode) AM33XX_IOPAD(0x09a8, mode) /* D13: mcasp0_axr1 */
+#define P9_42(mode) AM33XX_IOPAD(0x0964, mode) /* C18: P0_in_PWM0_out */
+#define P9_42A(mode) AM33XX_IOPAD(0x0964, mode) /* C18: P0_in_PWM0_out */
+#define P9_42B(mode) AM33XX_IOPAD(0x09a0, mode) /* B12: mcasp0_aclkr */
+#define P9_92(mode) AM33XX_IOPAD(0x09a0, mode) /* B12: mcasp0_aclkr */
+
+#define gpio_P1_02 &gpio2 23
+#define gpio_P1_04 &gpio2 25
+#define gpio_P1_06 &gpio0 5
+#define gpio_P1_08 &gpio0 2
+#define gpio_P1_10 &gpio0 3
+#define gpio_P1_12 &gpio0 4
+#define gpio_P1_20 &gpio0 20
+#define gpio_P1_26 &gpio0 12
+#define gpio_P1_28 &gpio0 13
+#define gpio_P1_29 &gpio3 21
+#define gpio_P1_30 &gpio1 11
+#define gpio_P1_31 &gpio3 18
+#define gpio_P1_32 &gpio1 10
+#define gpio_P1_33 &gpio3 15
+#define gpio_P1_34 &gpio0 26
+#define gpio_P1_35 &gpio2 24
+#define gpio_P1_36 &gpio3 14
+#define gpio_P2_01 &gpio1 18
+#define gpio_P2_02 &gpio1 27
+#define gpio_P2_03 &gpio0 23
+#define gpio_P2_04 &gpio1 26
+#define gpio_P2_05 &gpio0 30
+#define gpio_P2_06 &gpio1 25
+#define gpio_P2_07 &gpio0 31
+#define gpio_P2_08 &gpio1 28
+#define gpio_P2_09 &gpio0 15
+#define gpio_P2_10 &gpio1 20
+#define gpio_P2_11 &gpio0 14
+#define gpio_P2_17 &gpio2 1
+#define gpio_P2_18 &gpio1 15
+#define gpio_P2_19 &gpio0 27
+#define gpio_P2_20 &gpio2 0
+#define gpio_P2_22 &gpio1 14
+#define gpio_P2_24 &gpio1 12
+#define gpio_P2_25 &gpio1 9
+#define gpio_P2_27 &gpio1 8
+#define gpio_P2_28 &gpio3 20
+#define gpio_P2_29 &gpio0 7
+#define gpio_P2_30 &gpio3 17
+#define gpio_P2_31 &gpio0 19
+#define gpio_P2_32 &gpio3 16
+#define gpio_P2_33 &gpio1 13
+#define gpio_P2_34 &gpio3 19
+#define gpio_P2_35 &gpio2 22
+
+#define P1_02(mode) AM33XX_IOPAD(0x08e4, mode) /* R5: lcd_hsync */
+#define P1_04(mode) AM33XX_IOPAD(0x08ec, mode) /* R6: lcd_ac_bias_en */
+#define P1_06(mode) AM33XX_IOPAD(0x095c, mode) /* A16: spi0_cs0 */
+#define P1_08(mode) AM33XX_IOPAD(0x0950, mode) /* A17: spi0_sclk */
+#define P1_10(mode) AM33XX_IOPAD(0x0954, mode) /* B17: spi0_d0 */
+#define P1_12(mode) AM33XX_IOPAD(0x0958, mode) /* B16: spi0_d1 */
+#define P1_20(mode) AM33XX_IOPAD(0x09b4, mode) /* D14: xdma_event_intr1 */
+#define P1_26(mode) AM33XX_IOPAD(0x0978, mode) /* D18: uart1_ctsn */
+#define P1_28(mode) AM33XX_IOPAD(0x097c, mode) /* D17: uart1_rtsn */
+#define P1_29(mode) AM33XX_IOPAD(0x09ac, mode) /* A14: mcasp0_ahclkx */
+#define P1_30(mode) AM33XX_IOPAD(0x0974, mode) /* E16: uart0_txd */
+#define P1_31(mode) AM33XX_IOPAD(0x09a0, mode) /* B12: mcasp0_aclkr */
+#define P1_32(mode) AM33XX_IOPAD(0x0970, mode) /* E15: uart0_rxd */
+#define P1_33(mode) AM33XX_IOPAD(0x0994, mode) /* B13: mcasp0_fsx */
+#define P1_34(mode) AM33XX_IOPAD(0x0828, mode) /* T11: gpmc_ad10 */
+#define P1_35(mode) AM33XX_IOPAD(0x08e8, mode) /* V5: lcd_pclk */
+#define P1_36(mode) AM33XX_IOPAD(0x0990, mode) /* A13: mcasp0_aclkx */
+#define P2_01(mode) AM33XX_IOPAD(0x0848, mode) /* U14: gpmc_a2 */
+#define P2_02(mode) AM33XX_IOPAD(0x086c, mode) /* V17: gpmc_a11 */
+#define P2_03(mode) AM33XX_IOPAD(0x0824, mode) /* T10: gpmc_ad9 */
+#define P2_04(mode) AM33XX_IOPAD(0x0868, mode) /* T16: gpmc_a10 */
+#define P2_05(mode) AM33XX_IOPAD(0x0870, mode) /* T17: gpmc_wait0 */
+#define P2_06(mode) AM33XX_IOPAD(0x0864, mode) /* U16: gpmc_a9 */
+#define P2_07(mode) AM33XX_IOPAD(0x0874, mode) /* U17: gpmc_wpn */
+#define P2_08(mode) AM33XX_IOPAD(0x0878, mode) /* U18: gpmc_be1n */
+#define P2_09(mode) AM33XX_IOPAD(0x0984, mode) /* D15: uart1_txd */
+#define P2_10(mode) AM33XX_IOPAD(0x0850, mode) /* R14: gpmc_a4 */
+#define P2_11(mode) AM33XX_IOPAD(0x0980, mode) /* D16: uart1_rxd */
+#define P2_17(mode) AM33XX_IOPAD(0x088c, mode) /* V12: gpmc_clk */
+#define P2_18(mode) AM33XX_IOPAD(0x083c, mode) /* U13: gpmc_ad15 */
+#define P2_19(mode) AM33XX_IOPAD(0x082c, mode) /* U12: gpmc_ad11 */
+#define P2_20(mode) AM33XX_IOPAD(0x0888, mode) /* T13: gpmc_csn3 */
+#define P2_22(mode) AM33XX_IOPAD(0x0838, mode) /* V13: gpmc_ad14 */
+#define P2_24(mode) AM33XX_IOPAD(0x0830, mode) /* T12: gpmc_ad12 */
+#define P2_25(mode) AM33XX_IOPAD(0x096c, mode) /* E17: uart0_rtsn */
+#define P2_27(mode) AM33XX_IOPAD(0x0968, mode) /* E18: uart0_ctsn */
+#define P2_28(mode) AM33XX_IOPAD(0x09a8, mode) /* D13: mcasp0_axr1 */
+#define P2_29(mode) AM33XX_IOPAD(0x0964, mode) /* C18: eCAP0_in_PWM0_out */
+#define P2_30(mode) AM33XX_IOPAD(0x099c, mode) /* C12: mcasp0_ahclkr */
+#define P2_31(mode) AM33XX_IOPAD(0x09b0, mode) /* A15: xdma_event_intr0 */
+#define P2_32(mode) AM33XX_IOPAD(0x0998, mode) /* D12: mcasp0_axr0 */
+#define P2_33(mode) AM33XX_IOPAD(0x0834, mode) /* R12: gpmc_ad13 */
+#define P2_34(mode) AM33XX_IOPAD(0x09a4, mode) /* C13: mcasp0_fsr */
+#define P2_35(mode) AM33XX_IOPAD(0x08e0, mode) /* U5: lcd_vsync */
+
+#endif
diff --git a/include/dt-bindings/board/am572x-bone-pins.h b/include/dt-bindings/board/am572x-bone-pins.h
new file mode 100644
index 0000000000000..89f0704909a11
--- /dev/null
+++ b/include/dt-bindings/board/am572x-bone-pins.h
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Deepak Khatri <deepaklorkhatri7@gmail.com>
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
+ */
+
+#ifndef _DT_BINDINGS_BOARD_AM572X_BONE_PINS_H
+#define _DT_BINDINGS_BOARD_AM572X_BONE_PINS_H
+
+#define bb_device 1
+#define board_soc AM572X
+
+#define gpio_P8_03 &gpio1 24
+#define gpio_P8_04 &gpio1 25
+#define gpio_P8_05 &gpio7 1
+#define gpio_P8_06 &gpio7 2
+#define gpio_P8_07 &gpio6 5
+#define gpio_P8_08 &gpio6 6
+#define gpio_P8_09 &gpio6 18
+#define gpio_P8_10 &gpio6 4
+#define gpio_P8_11 &gpio3 11
+#define gpio_P8_12 &gpio3 10
+#define gpio_P8_13 &gpio4 11
+#define gpio_P8_14 &gpio4 13
+#define gpio_P8_15 &gpio4 3
+#define gpio_P8_16 &gpio4 29
+#define gpio_P8_17 &gpio8 18
+#define gpio_P8_18 &gpio4 9
+#define gpio_P8_19 &gpio4 10
+#define gpio_P8_20 &gpio6 30
+#define gpio_P8_21 &gpio6 29
+#define gpio_P8_22 &gpio1 23
+#define gpio_P8_23 &gpio1 22
+#define gpio_P8_24 &gpio7 0
+#define gpio_P8_25 &gpio6 31
+#define gpio_P8_26 &gpio4 28
+#define gpio_P8_27 &gpio4 23
+#define gpio_P8_28 &gpio4 19
+#define gpio_P8_29 &gpio4 22
+#define gpio_P8_30 &gpio4 20
+#define gpio_P8_31 &gpio8 14
+#define gpio_P8_32 &gpio8 15
+#define gpio_P8_33 &gpio8 13
+#define gpio_P8_34 &gpio8 11
+#define gpio_P8_35 &gpio8 12
+#define gpio_P8_36 &gpio8 10
+#define gpio_P8_37 &gpio8 8
+#define gpio_P8_38 &gpio8 9
+#define gpio_P8_39 &gpio8 6
+#define gpio_P8_40 &gpio8 7
+#define gpio_P8_41 &gpio8 4
+#define gpio_P8_42 &gpio8 5
+#define gpio_P8_43 &gpio8 2
+#define gpio_P8_44 &gpio8 3
+#define gpio_P8_45 &gpio8 0
+#define gpio_P8_46 &gpio8 1
+#define gpio_P9_11 &gpio8 17
+#define gpio_P9_12 &gpio5 0
+#define gpio_P9_13 &gpio6 12
+#define gpio_P9_14 &gpio4 25
+#define gpio_P9_15 &gpio3 12
+#define gpio_P9_16 &gpio4 26
+#define gpio_P9_17 &gpio7 17
+#define gpio_P9_18 &gpio7 16
+#define gpio_P9_19 &gpio7 3
+#define gpio_P9_20 &gpio7 4
+#define gpio_P9_21 &gpio3 3
+#define gpio_P9_22 &gpio6 19
+#define gpio_P9_23 &gpio7 11
+#define gpio_P9_24 &gpio6 15
+#define gpio_P9_25 &gpio6 17
+#define gpio_P9_26 &gpio6 14
+#define gpio_P9_27 &gpio4 15
+#define gpio_P9_28 &gpio4 17
+#define gpio_P9_29 &gpio5 11
+#define gpio_P9_30 &gpio5 12
+#define gpio_P9_31 &gpio5 10
+#define gpio_P9_41 &gpio6 20
+#define gpio_P9_42 &gpio4 18
+
+#define P8_03(mode) DRA7XX_CORE_IOPAD(0x379C, mode) /* AB8: mmc3_dat6 */
+#define P8_04(mode) DRA7XX_CORE_IOPAD(0x37A0, mode) /* AB5: mmc3_dat7 */
+#define P8_05(mode) DRA7XX_CORE_IOPAD(0x378C, mode) /* AC9: mmc3_dat2 */
+#define P8_06(mode) DRA7XX_CORE_IOPAD(0x3790, mode) /* AC3: mmc3_dat3 */
+#define P8_07(mode) DRA7XX_CORE_IOPAD(0x36EC, mode) /* G14: mcasp1_axr14 */
+#define P8_08(mode) DRA7XX_CORE_IOPAD(0x36F0, mode) /* F14: mcasp1_axr15 */
+#define P8_09(mode) DRA7XX_CORE_IOPAD(0x3698, mode) /* E17: xref_clk1 */
+#define P8_10(mode) DRA7XX_CORE_IOPAD(0x36E8, mode) /* A13: mcasp1_axr13 */
+#define P8_11(mode) DRA7XX_CORE_IOPAD(0x3510, mode) /* AH4: vin1a_d7 */
+#define P8_12(mode) DRA7XX_CORE_IOPAD(0x350C, mode) /* AG6: vin1a_d6 */
+#define P8_13(mode) DRA7XX_CORE_IOPAD(0x3590, mode) /* D3: vin2a_d10 */
+#define P8_14(mode) DRA7XX_CORE_IOPAD(0x3598, mode) /* D5: vin2a_d12 */
+#define P8_15A(mode) DRA7XX_CORE_IOPAD(0x3570, mode) /* D1: vin2a_d2 */
+#define P8_15B(mode) DRA7XX_CORE_IOPAD(0x35B4, mode) /* A3: vin2a_d19 */
+#define P8_16(mode) DRA7XX_CORE_IOPAD(0x35BC, mode) /* B4: vin2a_d21 */
+#define P8_17(mode) DRA7XX_CORE_IOPAD(0x3624, mode) /* A7: vout1_d18 */
+#define P8_18(mode) DRA7XX_CORE_IOPAD(0x3588, mode) /* F5: vin2a_d8 */
+#define P8_19(mode) DRA7XX_CORE_IOPAD(0x358C, mode) /* E6: vin2a_d9 */
+#define P8_20(mode) DRA7XX_CORE_IOPAD(0x3780, mode) /* AC4: mmc3_cmd */
+#define P8_21(mode) DRA7XX_CORE_IOPAD(0x377C, mode) /* AD4: mmc3_clk */
+#define P8_22(mode) DRA7XX_CORE_IOPAD(0x3798, mode) /* AD6: mmc3_dat5 */
+#define P8_23(mode) DRA7XX_CORE_IOPAD(0x3794, mode) /* AC8: mmc3_dat4 */
+#define P8_24(mode) DRA7XX_CORE_IOPAD(0x3788, mode) /* AC6: mmc3_dat1 */
+#define P8_25(mode) DRA7XX_CORE_IOPAD(0x3784, mode) /* AC7: mmc3_dat0 */
+#define P8_26(mode) DRA7XX_CORE_IOPAD(0x35B8, mode) /* B3: vin2a_d20 */
+#define P8_27A(mode) DRA7XX_CORE_IOPAD(0x35D8, mode) /* E11: vout1_vsync */
+#define P8_27B(mode) DRA7XX_CORE_IOPAD(0x3628, mode) /* A8: vout1_d19 */
+#define P8_28A(mode) DRA7XX_CORE_IOPAD(0x35C8, mode) /* D11: vout1_clk */
+#define P8_28B(mode) DRA7XX_CORE_IOPAD(0x362C, mode) /* C9: vout1_d20 */
+#define P8_29A(mode) DRA7XX_CORE_IOPAD(0x35D4, mode) /* C11: vout1_hsync */
+#define P8_29B(mode) DRA7XX_CORE_IOPAD(0x3630, mode) /* A9: vout1_d21 */
+#define P8_30A(mode) DRA7XX_CORE_IOPAD(0x35CC, mode) /* B10: vout1_de */
+#define P8_30B(mode) DRA7XX_CORE_IOPAD(0x3634, mode) /* B9: vout1_d22 */
+#define P8_31A(mode) DRA7XX_CORE_IOPAD(0x3614, mode) /* C8: vout1_d14 */
+#define P8_31B(mode) DRA7XX_CORE_IOPAD(0x373C, mode) /* G16: mcasp4_axr0 */
+#define P8_32A(mode) DRA7XX_CORE_IOPAD(0x3618, mode) /* C7: vout1_d15 */
+#define P8_32B(mode) DRA7XX_CORE_IOPAD(0x3740, mode) /* D17: mcasp4_axr1 */
+#define P8_33A(mode) DRA7XX_CORE_IOPAD(0x3610, mode) /* C6: vout1_d13 */
+#define P8_33B(mode) DRA7XX_CORE_IOPAD(0x34E8, mode) /* AF9: vin1a_fld0 */
+#define P8_34A(mode) DRA7XX_CORE_IOPAD(0x3608, mode) /* D8: vout1_d11 */
+#define P8_34B(mode) DRA7XX_CORE_IOPAD(0x3564, mode) /* G6: vin2a_vsync0 */
+#define P8_35A(mode) DRA7XX_CORE_IOPAD(0x360C, mode) /* A5: vout1_d12 */
+#define P8_35B(mode) DRA7XX_CORE_IOPAD(0x34E4, mode) /* AD9: vin1a_de0 */
+#define P8_36A(mode) DRA7XX_CORE_IOPAD(0x3604, mode) /* D7: vout1_d10 */
+#define P8_36B(mode) DRA7XX_CORE_IOPAD(0x3568, mode) /* F2: vin2a_d0 */
+#define P8_37A(mode) DRA7XX_CORE_IOPAD(0x35FC, mode) /* E8: vout1_d8 */
+#define P8_37B(mode) DRA7XX_CORE_IOPAD(0x3738, mode) /* A21: mcasp4_fsx */
+#define P8_38A(mode) DRA7XX_CORE_IOPAD(0x3600, mode) /* D9: vout1_d9 */
+#define P8_38B(mode) DRA7XX_CORE_IOPAD(0x3734, mode) /* C18: mcasp4_aclkx */
+#define P8_39(mode) DRA7XX_CORE_IOPAD(0x35F4, mode) /* F8: vout1_d6 */
+#define P8_40(mode) DRA7XX_CORE_IOPAD(0x35F8, mode) /* E7: vout1_d7 */
+#define P8_41(mode) DRA7XX_CORE_IOPAD(0x35EC, mode) /* E9: vout1_d4 */
+#define P8_42(mode) DRA7XX_CORE_IOPAD(0x35F0, mode) /* F9: vout1_d5 */
+#define P8_43(mode) DRA7XX_CORE_IOPAD(0x35E4, mode) /* F10: vout1_d2 */
+#define P8_44(mode) DRA7XX_CORE_IOPAD(0x35E8, mode) /* G11: vout1_d3 */
+#define P8_45A(mode) DRA7XX_CORE_IOPAD(0x35DC, mode) /* F11: vout1_d0 */
+#define P8_45B(mode) DRA7XX_CORE_IOPAD(0x361C, mode) /* B7: vout1_d16 */
+#define P8_46A(mode) DRA7XX_CORE_IOPAD(0x35E0, mode) /* G10: vout1_d1 */
+#define P8_46B(mode) DRA7XX_CORE_IOPAD(0x3638, mode) /* A10: vout1_d23 */
+#define P9_11A(mode) DRA7XX_CORE_IOPAD(0x372C, mode) /* B19: mcasp3_axr0 */
+#define P9_11B(mode) DRA7XX_CORE_IOPAD(0x3620, mode) /* B8: vout1_d17 */
+#define P9_12(mode) DRA7XX_CORE_IOPAD(0x36AC, mode) /* B14: mcasp1_aclkr */
+#define P9_13A(mode) DRA7XX_CORE_IOPAD(0x3730, mode) /* C17: mcasp3_axr1 */
+#define P9_13B(mode) DRA7XX_CORE_IOPAD(0x3680, mode) /* AB10: usb1_drvvbus */
+#define P9_14(mode) DRA7XX_CORE_IOPAD(0x35AC, mode) /* D6: vin2a_d17 */
+#define P9_15(mode) DRA7XX_CORE_IOPAD(0x3514, mode) /* AG4: vin1a_d8 */
+#define P9_16(mode) DRA7XX_CORE_IOPAD(0x35B0, mode) /* C5: vin2a_d18 */
+#define P9_17A(mode) DRA7XX_CORE_IOPAD(0x37CC, mode) /* B24: spi2_cs0 */
+#define P9_17B(mode) DRA7XX_CORE_IOPAD(0x36B8, mode) /* F12: mcasp1_axr1 */
+#define P9_18A(mode) DRA7XX_CORE_IOPAD(0x37C8, mode) /* G17: spi2_d0 */
+#define P9_18B(mode) DRA7XX_CORE_IOPAD(0x36B4, mode) /* G12: mcasp1_axr0 */
+#define P9_19A(mode) DRA7XX_CORE_IOPAD(0x3440, mode) /* R6: gpmc_a0.i2c4_scl */
+#define P9_19B(mode) DRA7XX_CORE_IOPAD(0x357C, mode) /* F4: vin2a_d5.pr1_pru1_gpi2 */
+#define P9_20A(mode) DRA7XX_CORE_IOPAD(0x3444, mode) /* T9: gpmc_a1.i2c4_sda */
+#define P9_20B(mode) DRA7XX_CORE_IOPAD(0x3578, mode) /* D2: vin2a_d4.pr1_pru1_gpi1 */
+#define P9_21A(mode) DRA7XX_CORE_IOPAD(0x34F0, mode) /* AF8: vin1a_vsync0 */
+#define P9_21B(mode) DRA7XX_CORE_IOPAD(0x37C4, mode) /* B22: spi2_d1 */
+#define P9_22A(mode) DRA7XX_CORE_IOPAD(0x369C, mode) /* B26: xref_clk2 */
+#define P9_22B(mode) DRA7XX_CORE_IOPAD(0x37C0, mode) /* A26: spi2_sclk */
+#define P9_23(mode) DRA7XX_CORE_IOPAD(0x37B4, mode) /* A22: spi1_cs1 */
+#define P9_24(mode) DRA7XX_CORE_IOPAD(0x368C, mode) /* F20: gpio6_15 */
+#define P9_25(mode) DRA7XX_CORE_IOPAD(0x3694, mode) /* D18: xref_clk0 */
+#define P9_26A(mode) DRA7XX_CORE_IOPAD(0x3688, mode) /* E21: gpio6_14 */
+#define P9_26B(mode) DRA7XX_CORE_IOPAD(0x3544, mode) /* AE2: vin1a_d20 */
+#define P9_27A(mode) DRA7XX_CORE_IOPAD(0x35A0, mode) /* C3: vin2a_d14 */
+#define P9_27B(mode) DRA7XX_CORE_IOPAD(0x36B0, mode) /* J14: mcasp1_fsr */
+#define P9_28(mode) DRA7XX_CORE_IOPAD(0x36E0, mode) /* A12: mcasp1_axr11 */
+#define P9_29A(mode) DRA7XX_CORE_IOPAD(0x36D8, mode) /* A11: mcasp1_axr9 */
+#define P9_29B(mode) DRA7XX_CORE_IOPAD(0x36A8, mode) /* D14: mcasp1_fsx */
+#define P9_30(mode) DRA7XX_CORE_IOPAD(0x36DC, mode) /* B13: mcasp1_axr10 */
+#define P9_31A(mode) DRA7XX_CORE_IOPAD(0x36D4, mode) /* B12: mcasp1_axr8 */
+#define P9_31B(mode) DRA7XX_CORE_IOPAD(0x36A4, mode) /* C14: mcasp1_aclkx */
+#define P9_41A(mode) DRA7XX_CORE_IOPAD(0x36A0, mode) /* C23: xref_clk3 */
+#define P9_41B(mode) DRA7XX_CORE_IOPAD(0x3580, mode) /* C1: vin2a_d6 */
+#define P9_42A(mode) DRA7XX_CORE_IOPAD(0x36E4, mode) /* E14: mcasp1_axr12 */
+#define P9_42B(mode) DRA7XX_CORE_IOPAD(0x359C, mode) /* C2: vin2a_d13 */
+
+#endif
diff --git a/include/dt-bindings/board/k3-j721e-bone-pins.h b/include/dt-bindings/board/k3-j721e-bone-pins.h
new file mode 100644
index 0000000000000..12d772347911f
--- /dev/null
+++ b/include/dt-bindings/board/k3-j721e-bone-pins.h
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Deepak Khatri <deepaklorkhatri7@gmail.com>
+ * Copyright (C) 2021 Jason Kridner <jkridner@beagleboard.org>
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
+ */
+
+#ifndef _DT_BINDINGS_BOARD_TDA4VM_BONE_PINS_H
+#define _DT_BINDINGS_BOARD_TDA4VM_BONE_PINS_H
+
+#define bb_device 1
+#define board_soc TDA4VM
+
+#define gpio_P8_03 &main_gpio0 20 /* AH21: PRG1_PRU0_GPO19 AH21_MCAN6_TX */
+#define gpio_P8_04 &main_gpio0 48 /* AC29: PRG0_PRU0_GPO5 AC29_SYS_BOOTMODE2 */
+#define gpio_P8_05 &main_gpio0 33 /* AH25: PRG1_PRU1_GPO12 AH25_MCAN7_TX */
+#define gpio_P8_06 &main_gpio0 34 /* AG25: PRG1_PRU1_GPO13 AG25_MCAN7_RX */
+#define gpio_P8_07 &main_gpio0 15 /* AD24: PRG1_PRU0_GPO14 AD24_MCAN5_RX */
+#define gpio_P8_08 &main_gpio0 14 /* AG24: PRG1_PRU0_GPO13 AG24_MCAN5_TX */
+#define gpio_P8_09 &main_gpio0 17 /* AE24: PRG1_PRU0_GPO16 AE24_MCAN6_RX */
+#define gpio_P8_10 &main_gpio0 16 /* AC24: PRG1_PRU0_GPO15 AC24_MCAN6_TX */
+#define gpio_P8_11 &main_gpio0 60 /* AB24: PRG0_PRU0_GPO17 AB24_SYS_BOOTMODE7 */
+#define gpio_P8_12 &main_gpio0 59 /* AH28: PRG0_PRU0_GPO16 AH28_PRG0_PWM0_A2 */
+#define gpio_P8_13 &main_gpio0 89 /* V27: RGMII5_TD1 V27_EHRPWM0_B */
+#define gpio_P8_14 &main_gpio0 75 /* AF27: PRG0_PRU1_GPO12 AF27_PRG0_PWM1_A0 */
+#define gpio_P8_15 &main_gpio0 61 /* AB29: PRG0_PRU0_GPO18 AB29_PRG0_ECAP0_IN_APWM_OUT */
+#define gpio_P8_16 &main_gpio0 62 /* AB28: PRG0_PRU0_GPO19 AB28_PRG0_PWM0_TZ_OUT */
+#define gpio_P8_17 &main_gpio0 3 /* AF22: PRG1_PRU0_GPO2 AF22_PRG1_PWM2_A0 */
+#define gpio_P8_18 &main_gpio0 4 /* AJ23: PRG1_PRU0_GPO3 AJ23_PRG1_PWM3_A2 */
+#define gpio_P8_19 &main_gpio0 88 /* V29: RGMII5_TD2 V29_EHRPWM0_A */
+#define gpio_P8_20 &main_gpio0 76 /* AF26: PRG0_PRU1_GPO13 AF26_PRG0_PWM1_B0 */
+#define gpio_P8_21 &main_gpio0 30 /* AF21: PRG1_PRU1_GPO9 AF21_MCAN8_TX */
+#define gpio_P8_22 &main_gpio0 5 /* AH23: PRG1_PRU0_GPO4 AH23_UART2_RXD */
+#define gpio_P8_23 &main_gpio0 31 /* AB23: PRG1_PRU1_GPO10 AB23_MCAN8_RX */
+#define gpio_P8_24 &main_gpio0 6 /* AD20: PRG1_PRU0_GPO5 AD20_SYS_BOOTMODE0 */
+#define gpio_P8_25 &main_gpio0 35 /* AH26: PRG1_PRU1_GPO14 AH26_PRG1_PRU1_GPO14 */
+#define gpio_P8_26 &main_gpio0 51 /* AC27: PRG0_PRU0_GPO8 AC27_PRG0_PWM2_A1 */
+#define gpio_P8_27 &main_gpio0 71 /* AA28: PRG0_PRU1_GPO8 AA28_PRG0_PRU1_GPO8 */
+#define gpio_P8_28 &main_gpio0 72 /* Y24: PRG0_PRU1_GPO9 Y24_PRG0_UART0_RXD */
+#define gpio_P8_29 &main_gpio0 73 /* AA25: PRG0_PRU1_GPO10 AA25_PRG0_UART0_TXD */
+#define gpio_P8_30 &main_gpio0 74 /* AG26: PRG0_PRU1_GPO11 AG26_PRG0_PRU1_GPO11 */
+#define gpio_P8_31 gpio_P8_31A
+#define gpio_P8_31A &main_gpio0 32 /* AJ25: PRG1_PRU1_GPO11 AJ25_AE29 */
+#define gpio_P8_31B &main_gpio0 63 /* AE29: PRG0_PRU1_GPO0 AJ25_AE29 */
+#define gpio_P8_32 gpio_P8_32A
+#define gpio_P8_32A &main_gpio0 26 /* AG21: PRG1_PRU1_GPO5 AG21_AD28 */
+#define gpio_P8_32B &main_gpio0 64 /* AD28: PRG0_PRU1_GPO1 AG21_AD28 */
+#define gpio_P8_33 gpio_P8_33A
+#define gpio_P8_33A &main_gpio0 25 /* AH24: PRG1_PRU1_GPO4 AH24_AA2 */
+#define gpio_P8_33B &main_gpio0 111 /* AA2: SPI0_CS0 AH24_AA2 */
+#define gpio_P8_34 &main_gpio0 7 /* AD22: PRG1_PRU0_GPO6 AD22_UART2_TXD */
+#define gpio_P8_35 gpio_P8_35A
+#define gpio_P8_35A &main_gpio0 24 /* AD23: PRG1_PRU1_GPO3 AD23_Y3 */
+#define gpio_P8_35B &main_gpio0 116 /* Y3: SPI1_CS0 AD23_Y3 */
+#define gpio_P8_36 &main_gpio0 8 /* AE20: PRG1_PRU0_GPO7 AE20_MCAN4_TX */
+#define gpio_P8_37 gpio_P8_37A
+#define gpio_P8_37A &main_gpio0 106 /* Y27: RGMII6_RD2 Y27_AD21 */
+#define gpio_P8_37B &main_gpio0 11 /* AD21: PRG1_PRU0_GPO10 Y27_AD21 */
+#define gpio_P8_38 gpio_P8_38A
+#define gpio_P8_38A &main_gpio0 9 /* AJ20: PRG1_PRU0_GPO8 Y29_AJ20 */
+#define gpio_P8_38B &main_gpio0 105 /* Y29: RGMII6_RD3 Y29_AJ20 */
+#define gpio_P8_39 &main_gpio0 69 /* AC26: PRG0_PRU1_GPO6 AC26_PRG0_PRU1_GPO6 */
+#define gpio_P8_40 &main_gpio0 70 /* AA24: PRG0_PRU1_GPO7 AA24_PRG0_PRU1_GPO7 */
+#define gpio_P8_41 &main_gpio0 67 /* AD29: PRG0_PRU1_GPO4 AD29_PRG0_PRU1_GPO4 */
+#define gpio_P8_42 &main_gpio0 68 /* AB27: PRG0_PRU1_GPO5 AB27_SYS_BOOTMODE6 */
+#define gpio_P8_43 &main_gpio0 65 /* AD27: PRG0_PRU1_GPO2 AD27_PRG0_PRU1_GPO2 */
+#define gpio_P8_44 &main_gpio0 66 /* AC25: PRG0_PRU1_GPO3 AC25_PRG0_PRU1_GPO3 */
+#define gpio_P8_45 &main_gpio0 79 /* AG29: PRG0_PRU1_GPO16 AG29_PRG0_PRU1_GPO16 */
+#define gpio_P8_46 &main_gpio0 80 /* Y25: PRG0_PRU1_GPO17 Y25_SYS_BOOTMODE3 */
+#define gpio_P9_11 &main_gpio0 1 /* AC23: PRG1_PRU0_GPO0 AC23_UART0_RXD */
+#define gpio_P9_12 &main_gpio0 45 /* AE27: PRG0_PRU0_GPO2 AE27_MCASP0_ACLKR */
+#define gpio_P9_13 &main_gpio0 2 /* AG22: PRG1_PRU0_GPO1 AG22_UART0_TXD */
+#define gpio_P9_14 &main_gpio0 93 /* U27: RGMII5_RD3 U27_EHRPWM2_A */
+#define gpio_P9_15 &main_gpio0 47 /* AD25: PRG0_PRU0_GPO4 AD25_PRG0_PRU0_GPO4 */
+#define gpio_P9_16 &main_gpio0 94 /* U24: RGMII5_RD2 U24_EHRPWM2_B */
+#define gpio_P9_17 gpio_P9_17A
+#define gpio_P9_17A &main_gpio0 28 /* AC21: PRG1_PRU1_GPO7 AC21_AA3 */
+#define gpio_P9_17B &main_gpio0 115 /* AA3: SPI0_D1 AC21_AA3 */
+#define gpio_P9_18 gpio_P9_18A
+#define gpio_P9_18A &main_gpio0 40 /* AH22: PRG1_PRU1_GPO19 AH22_Y2 */
+#define gpio_P9_18B &main_gpio0 120 /* Y2: SPI1_D1 AH22_Y2 */
+#define gpio_P9_19 gpio_P9_19A
+#define gpio_P9_19A &main_gpio1 1 /* W5: MCAN0_RX W5_AF29 */
+#define gpio_P9_19B &main_gpio0 78 /* AF29: PRG0_PRU1_GPO15 W5_AF29 */
+#define gpio_P9_20 gpio_P9_20A
+#define gpio_P9_20A &main_gpio1 2 /* W6: MCAN0_TX W6_AE25 */
+#define gpio_P9_20B &main_gpio0 77 /* AE25: PRG0_PRU1_GPO14 W6_AE25 */
+#define gpio_P9_21 gpio_P9_21A
+#define gpio_P9_21A &main_gpio0 39 /* AJ22: PRG1_PRU1_GPO18 AJ22_U28 */
+#define gpio_P9_21B &main_gpio0 90 /* U28: RGMII5_TD0 AJ22_U28 */
+#define gpio_P9_22 gpio_P9_22A
+#define gpio_P9_22A &main_gpio0 38 /* AC22: PRG1_PRU1_GPO17 AC22_U29 */
+#define gpio_P9_22B &main_gpio0 91 /* U29: RGMII5_TXC AC22_U29 */
+#define gpio_P9_23 &main_gpio0 10 /* AG20: PRG1_PRU0_GPO9 AG20_SPI6_CS1 */
+#define gpio_P9_24 gpio_P9_24A
+#define gpio_P9_24A &main_gpio0 119 /* Y5: SPI1_D0 Y5_AJ24 */
+#define gpio_P9_24B &main_gpio0 13 /* AJ24: PRG1_PRU0_GPO12 Y5_AJ24 */
+#define gpio_P9_25 gpio_P9_25A
+#define gpio_P9_25A &main_gpio0 127 /* AC4: UART1_CTSn AC4_W26 */
+#define gpio_P9_25B &main_gpio0 104 /* W26: RGMII6_RXC AC4_W26 */
+#define gpio_P9_26 gpio_P9_26A
+#define gpio_P9_26A &main_gpio0 118 /* Y1: SPI1_CLK Y1_AF24 */
+#define gpio_P9_26B &main_gpio0 12 /* AF24: PRG1_PRU0_GPO11 Y1_AF24 */
+#define gpio_P9_27 gpio_P9_27A
+#define gpio_P9_27A &main_gpio0 46 /* AD26: PRG0_PRU0_GPO3 AD26_AB1 */
+#define gpio_P9_27B &main_gpio0 124 /* AB1: UART0_RTSn AD26_AB1 */
+#define gpio_P9_28 gpio_P9_28A
+#define gpio_P9_28A &main_gpio1 11 /* U2: ECAP0_IN_APWM_OUT U2_AF28 */
+#define gpio_P9_28B &main_gpio0 43 /* AF28: PRG0_PRU0_GPO0 U2_AF28 */
+#define gpio_P9_29 gpio_P9_29A
+#define gpio_P9_29A &main_gpio1 14 /* V5: TIMER_IO1 V5_AB25 */
+#define gpio_P9_29B &main_gpio0 53 /* AB25: PRG0_PRU0_GPO10 V5_AB25 */
+#define gpio_P9_30 gpio_P9_30A
+#define gpio_P9_30A &main_gpio1 13 /* V6: TIMER_IO0 V6_AE28 */
+#define gpio_P9_30B &main_gpio0 44 /* AE28: PRG0_PRU0_GPO1 V6_AE28 */
+#define gpio_P9_31 gpio_P9_31A
+#define gpio_P9_31A &main_gpio1 12 /* U3: EXT_REFCLK1 U3_AB26 */
+#define gpio_P9_31B &main_gpio0 52 /* AB26: PRG0_PRU0_GPO9 U3_AB26 */
+#define gpio_P9_33 &main_gpio0 50
+#define gpio_P9_33B &main_gpio0 50 /* AC28: PRG0_PRU0_GPO7 K24_AC28 */
+#define gpio_P9_35 &main_gpio0 55
+#define gpio_P9_35B &main_gpio0 55 /* AH27: PRG0_PRU0_GPO12 K29_AH27 */
+#define gpio_P9_36 &main_gpio0 56
+#define gpio_P9_36B &main_gpio0 56 /* AH29: PRG0_PRU0_GPO13 K27_AH29 */
+#define gpio_P9_37 &main_gpio0 57
+#define gpio_P9_37B &main_gpio0 57 /* AG28: PRG0_PRU0_GPO14 K28_AG28 */
+#define gpio_P9_38 &main_gpio0 58
+#define gpio_P9_38B &main_gpio0 58 /* AG27: PRG0_PRU0_GPO15 L28_AG27 */
+#define gpio_P9_39 &main_gpio0 54
+#define gpio_P9_39B &main_gpio0 54 /* AJ28: PRG0_PRU0_GPO11 K25_AJ28 */
+#define gpio_P9_40 &main_gpio0 81
+#define gpio_P9_40B &main_gpio0 81 /* AA26: PRG0_PRU1_GPO18 K26_AA26 */
+#define gpio_P9_41 &main_gpio1 0 /* AD5: UART1_RTSn AD5_EQEP0_I */
+#define gpio_P9_42 gpio_P9_42A
+#define gpio_P9_42A &main_gpio0 123 /* AC2: UART0_CTSn AC2_AJ21 */
+#define gpio_P9_42B &main_gpio0 18 /* AJ21: PRG1_PRU0_GPO17 AC2_AJ21 */
+
+#define P8_03(mode, mux) J721E_IOPAD(0x54, mode, mux) /* AH21: PRG1_PRU0_GPO19 AH21_MCAN6_TX */
+#define P8_04(mode, mux) J721E_IOPAD(0xC4, mode, mux) /* AC29: PRG0_PRU0_GPO5 AC29_SYS_BOOTMODE2 */
+#define P8_05(mode, mux) J721E_IOPAD(0x88, mode, mux) /* AH25: PRG1_PRU1_GPO12 AH25_MCAN7_TX */
+#define P8_06(mode, mux) J721E_IOPAD(0x8C, mode, mux) /* AG25: PRG1_PRU1_GPO13 AG25_MCAN7_RX */
+#define P8_07(mode, mux) J721E_IOPAD(0x3C, mode, mux) /* AD24: PRG1_PRU0_GPO14 AD24_MCAN5_RX */
+#define P8_08(mode, mux) J721E_IOPAD(0x38, mode, mux) /* AG24: PRG1_PRU0_GPO13 AG24_MCAN5_TX */
+#define P8_09(mode, mux) J721E_IOPAD(0x44, mode, mux) /* AE24: PRG1_PRU0_GPO16 AE24_MCAN6_RX */
+#define P8_10(mode, mux) J721E_IOPAD(0x40, mode, mux) /* AC24: PRG1_PRU0_GPO15 AC24_MCAN6_TX */
+#define P8_11(mode, mux) J721E_IOPAD(0xF4, mode, mux) /* AB24: PRG0_PRU0_GPO17 AB24_SYS_BOOTMODE7 */
+#define P8_12(mode, mux) J721E_IOPAD(0xF0, mode, mux) /* AH28: PRG0_PRU0_GPO16 AH28_PRG0_PWM0_A2 */
+#define P8_13(mode, mux) J721E_IOPAD(0x168, mode, mux) /* V27: RGMII5_TD1 V27_EHRPWM0_B */
+#define P8_14(mode, mux) J721E_IOPAD(0x130, mode, mux) /* AF27: PRG0_PRU1_GPO12 AF27_PRG0_PWM1_A0 */
+#define P8_15(mode, mux) J721E_IOPAD(0xF8, mode, mux) /* AB29: PRG0_PRU0_GPO18 AB29_PRG0_ECAP0_IN_APWM_OUT */
+#define P8_16(mode, mux) J721E_IOPAD(0xFC, mode, mux) /* AB28: PRG0_PRU0_GPO19 AB28_PRG0_PWM0_TZ_OUT */
+#define P8_17(mode, mux) J721E_IOPAD(0xC, mode, mux) /* AF22: PRG1_PRU0_GPO2 AF22_PRG1_PWM2_A0 */
+#define P8_18(mode, mux) J721E_IOPAD(0x10, mode, mux) /* AJ23: PRG1_PRU0_GPO3 AJ23_PRG1_PWM3_A2 */
+#define P8_19(mode, mux) J721E_IOPAD(0x164, mode, mux) /* V29: RGMII5_TD2 V29_EHRPWM0_A */
+#define P8_20(mode, mux) J721E_IOPAD(0x134, mode, mux) /* AF26: PRG0_PRU1_GPO13 AF26_PRG0_PWM1_B0 */
+#define P8_21(mode, mux) J721E_IOPAD(0x7C, mode, mux) /* AF21: PRG1_PRU1_GPO9 AF21_MCAN8_TX */
+#define P8_22(mode, mux) J721E_IOPAD(0x14, mode, mux) /* AH23: PRG1_PRU0_GPO4 AH23_UART2_RXD */
+#define P8_23(mode, mux) J721E_IOPAD(0x80, mode, mux) /* AB23: PRG1_PRU1_GPO10 AB23_MCAN8_RX */
+#define P8_24(mode, mux) J721E_IOPAD(0x18, mode, mux) /* AD20: PRG1_PRU0_GPO5 AD20_SYS_BOOTMODE0 */
+#define P8_25(mode, mux) J721E_IOPAD(0x90, mode, mux) /* AH26: PRG1_PRU1_GPO14 AH26_PRG1_PRU1_GPO14 */
+#define P8_26(mode, mux) J721E_IOPAD(0xD0, mode, mux) /* AC27: PRG0_PRU0_GPO8 AC27_PRG0_PWM2_A1 */
+#define P8_27(mode, mux) J721E_IOPAD(0x120, mode, mux) /* AA28: PRG0_PRU1_GPO8 AA28_PRG0_PRU1_GPO8 */
+#define P8_28(mode, mux) J721E_IOPAD(0x124, mode, mux) /* Y24: PRG0_PRU1_GPO9 Y24_PRG0_UART0_RXD */
+#define P8_29(mode, mux) J721E_IOPAD(0x128, mode, mux) /* AA25: PRG0_PRU1_GPO10 AA25_PRG0_UART0_TXD */
+#define P8_30(mode, mux) J721E_IOPAD(0x12C, mode, mux) /* AG26: PRG0_PRU1_GPO11 AG26_PRG0_PRU1_GPO11 */
+#define P8_31A(mode, mux) J721E_IOPAD(0x84, mode, mux) /* AJ25: PRG1_PRU1_GPO11 AJ25_AE29 */
+#define P8_31B(mode, mux) J721E_IOPAD(0x100, mode, mux) /* AE29: PRG0_PRU1_GPO0 AJ25_AE29 */
+#define P8_32A(mode, mux) J721E_IOPAD(0x6C, mode, mux) /* AG21: PRG1_PRU1_GPO5 AG21_AD28 */
+#define P8_32B(mode, mux) J721E_IOPAD(0x104, mode, mux) /* AD28: PRG0_PRU1_GPO1 AG21_AD28 */
+#define P8_33A(mode, mux) J721E_IOPAD(0x68, mode, mux) /* AH24: PRG1_PRU1_GPO4 AH24_AA2 */
+#define P8_33B(mode, mux) J721E_IOPAD(0x1C0, mode, mux) /* AA2: SPI0_CS0 AH24_AA2 */
+#define P8_34(mode, mux) J721E_IOPAD(0x1C, mode, mux) /* AD22: PRG1_PRU0_GPO6 AD22_UART2_TXD */
+#define P8_35A(mode, mux) J721E_IOPAD(0x64, mode, mux) /* AD23: PRG1_PRU1_GPO3 AD23_Y3 */
+#define P8_35B(mode, mux) J721E_IOPAD(0x1D4, mode, mux) /* Y3: SPI1_CS0 AD23_Y3 */
+#define P8_36(mode, mux) J721E_IOPAD(0x20, mode, mux) /* AE20: PRG1_PRU0_GPO7 AE20_MCAN4_TX */
+#define P8_37A(mode, mux) J721E_IOPAD(0x1AC, mode, mux) /* Y27: RGMII6_RD2 Y27_AD21 */
+#define P8_37B(mode, mux) J721E_IOPAD(0x2C, mode, mux) /* AD21: PRG1_PRU0_GPO10 Y27_AD21 */
+#define P8_38A(mode, mux) J721E_IOPAD(0x24, mode, mux) /* AJ20: PRG1_PRU0_GPO8 Y29_AJ20 */
+#define P8_38B(mode, mux) J721E_IOPAD(0x1A8, mode, mux) /* Y29: RGMII6_RD3 Y29_AJ20 */
+#define P8_39(mode, mux) J721E_IOPAD(0x118, mode, mux) /* AC26: PRG0_PRU1_GPO6 AC26_PRG0_PRU1_GPO6 */
+#define P8_40(mode, mux) J721E_IOPAD(0x11C, mode, mux) /* AA24: PRG0_PRU1_GPO7 AA24_PRG0_PRU1_GPO7 */
+#define P8_41(mode, mux) J721E_IOPAD(0x110, mode, mux) /* AD29: PRG0_PRU1_GPO4 AD29_PRG0_PRU1_GPO4 */
+#define P8_42(mode, mux) J721E_IOPAD(0x114, mode, mux) /* AB27: PRG0_PRU1_GPO5 AB27_SYS_BOOTMODE6 */
+#define P8_43(mode, mux) J721E_IOPAD(0x108, mode, mux) /* AD27: PRG0_PRU1_GPO2 AD27_PRG0_PRU1_GPO2 */
+#define P8_44(mode, mux) J721E_IOPAD(0x10C, mode, mux) /* AC25: PRG0_PRU1_GPO3 AC25_PRG0_PRU1_GPO3 */
+#define P8_45(mode, mux) J721E_IOPAD(0x140, mode, mux) /* AG29: PRG0_PRU1_GPO16 AG29_PRG0_PRU1_GPO16 */
+#define P8_46(mode, mux) J721E_IOPAD(0x144, mode, mux) /* Y25: PRG0_PRU1_GPO17 Y25_SYS_BOOTMODE3 */
+#define P9_11(mode, mux) J721E_IOPAD(0x4, mode, mux) /* AC23: PRG1_PRU0_GPO0 AC23_UART0_RXD */
+#define P9_12(mode, mux) J721E_IOPAD(0xB8, mode, mux) /* AE27: PRG0_PRU0_GPO2 AE27_MCASP0_ACLKR */
+#define P9_13(mode, mux) J721E_IOPAD(0x8, mode, mux) /* AG22: PRG1_PRU0_GPO1 AG22_UART0_TXD */
+#define P9_14(mode, mux) J721E_IOPAD(0x178, mode, mux) /* U27: RGMII5_RD3 U27_EHRPWM2_A */
+#define P9_15(mode, mux) J721E_IOPAD(0xC0, mode, mux) /* AD25: PRG0_PRU0_GPO4 AD25_PRG0_PRU0_GPO4 */
+#define P9_16(mode, mux) J721E_IOPAD(0x17C, mode, mux) /* U24: RGMII5_RD2 U24_EHRPWM2_B */
+#define P9_17A(mode, mux) J721E_IOPAD(0x74, mode, mux) /* AC21: PRG1_PRU1_GPO7 AC21_AA3 */
+#define P9_17B(mode, mux) J721E_IOPAD(0x1D0, mode, mux) /* AA3: SPI0_D1 AC21_AA3 */
+#define P9_18A(mode, mux) J721E_IOPAD(0xA4, mode, mux) /* AH22: PRG1_PRU1_GPO19 AH22_Y2 */
+#define P9_18B(mode, mux) J721E_IOPAD(0x1E4, mode, mux) /* Y2: SPI1_D1 AH22_Y2 */
+#define P9_19A(mode, mux) J721E_IOPAD(0x208, mode, mux) /* W5: MCAN0_RX W5_AF29 */
+#define P9_19B(mode, mux) J721E_IOPAD(0x13C, mode, mux) /* AF29: PRG0_PRU1_GPO15 W5_AF29 */
+#define P9_20A(mode, mux) J721E_IOPAD(0x20C, mode, mux) /* W6: MCAN0_TX W6_AE25 */
+#define P9_20B(mode, mux) J721E_IOPAD(0x138, mode, mux) /* AE25: PRG0_PRU1_GPO14 W6_AE25 */
+#define P9_21A(mode, mux) J721E_IOPAD(0xA0, mode, mux) /* AJ22: PRG1_PRU1_GPO18 AJ22_U28 */
+#define P9_21B(mode, mux) J721E_IOPAD(0x16C, mode, mux) /* U28: RGMII5_TD0 AJ22_U28 */
+#define P9_22A(mode, mux) J721E_IOPAD(0x9C, mode, mux) /* AC22: PRG1_PRU1_GPO17 AC22_U29 */
+#define P9_22B(mode, mux) J721E_IOPAD(0x170, mode, mux) /* U29: RGMII5_TXC AC22_U29 */
+#define P9_23(mode, mux) J721E_IOPAD(0x28, mode, mux) /* AG20: PRG1_PRU0_GPO9 AG20_SPI6_CS1 */
+#define P9_24A(mode, mux) J721E_IOPAD(0x1E0, mode, mux) /* Y5: SPI1_D0 Y5_AJ24 */
+#define P9_24B(mode, mux) J721E_IOPAD(0x34, mode, mux) /* AJ24: PRG1_PRU0_GPO12 Y5_AJ24 */
+#define P9_25A(mode, mux) J721E_IOPAD(0x200, mode, mux) /* AC4: UART1_CTSn AC4_W26 */
+#define P9_25B(mode, mux) J721E_IOPAD(0x1A4, mode, mux) /* W26: RGMII6_RXC AC4_W26 */
+#define P9_26A(mode, mux) J721E_IOPAD(0x1DC, mode, mux) /* Y1: SPI1_CLK Y1_AF24 */
+#define P9_26B(mode, mux) J721E_IOPAD(0x30, mode, mux) /* AF24: PRG1_PRU0_GPO11 Y1_AF24 */
+#define P9_27A(mode, mux) J721E_IOPAD(0xBC, mode, mux) /* AD26: PRG0_PRU0_GPO3 AD26_AB1 */
+#define P9_27B(mode, mux) J721E_IOPAD(0x1F4, mode, mux) /* AB1: UART0_RTSn AD26_AB1 */
+#define P9_28A(mode, mux) J721E_IOPAD(0x230, mode, mux) /* U2: ECAP0_IN_APWM_OUT U2_AF28 */
+#define P9_28B(mode, mux) J721E_IOPAD(0xB0, mode, mux) /* AF28: PRG0_PRU0_GPO0 U2_AF28 */
+#define P9_29A(mode, mux) J721E_IOPAD(0x23C, mode, mux) /* V5: TIMER_IO1 V5_AB25 */
+#define P9_29B(mode, mux) J721E_IOPAD(0xD8, mode, mux) /* AB25: PRG0_PRU0_GPO10 V5_AB25 */
+#define P9_30A(mode, mux) J721E_IOPAD(0x238, mode, mux) /* V6: TIMER_IO0 V6_AE28 */
+#define P9_30B(mode, mux) J721E_IOPAD(0xB4, mode, mux) /* AE28: PRG0_PRU0_GPO1 V6_AE28 */
+#define P9_31A(mode, mux) J721E_IOPAD(0x234, mode, mux) /* U3: EXT_REFCLK1 U3_AB26 */
+#define P9_31B(mode, mux) J721E_IOPAD(0xD4, mode, mux) /* AB26: PRG0_PRU0_GPO9 U3_AB26 */
+#define P9_33A(mode, mux) J721E_WKUP_IOPAD(0x140, mode, mux) /* K24: MCU_ADC0_AIN4 K24_AC28 */
+#define P9_33B(mode, mux) J721E_IOPAD(0xCC, mode, mux) /* AC28: PRG0_PRU0_GPO7 K24_AC28 */
+#define P9_35A(mode, mux) J721E_WKUP_IOPAD(0x148, mode, mux) /* K29: MCU_ADC0_AIN6 K29_AH27 */
+#define P9_35B(mode, mux) J721E_IOPAD(0xE0, mode, mux) /* AH27: PRG0_PRU0_GPO12 K29_AH27 */
+#define P9_36A(mode, mux) J721E_WKUP_IOPAD(0x144, mode, mux) /* K27: MCU_ADC0_AIN5 K27_AH29 */
+#define P9_36B(mode, mux) J721E_IOPAD(0xE4, mode, mux) /* AH29: PRG0_PRU0_GPO13 K27_AH29 */
+#define P9_37A(mode, mux) J721E_WKUP_IOPAD(0x138, mode, mux) /* K28: MCU_ADC0_AIN2 K28_AG28 */
+#define P9_37B(mode, mux) J721E_IOPAD(0xE8, mode, mux) /* AG28: PRG0_PRU0_GPO14 K28_AG28 */
+#define P9_38A(mode, mux) J721E_WKUP_IOPAD(0x13C, mode, mux) /* L28: MCU_ADC0_AIN3 L28_AG27 */
+#define P9_38B(mode, mux) J721E_IOPAD(0xEC, mode, mux) /* AG27: PRG0_PRU0_GPO15 L28_AG27 */
+#define P9_39A(mode, mux) J721E_WKUP_IOPAD(0x130, mode, mux) /* K25: MCU_ADC0_AIN0 K25_AJ28 */
+#define P9_39B(mode, mux) J721E_IOPAD(0xDC, mode, mux) /* AJ28: PRG0_PRU0_GPO11 K25_AJ28 */
+#define P9_40A(mode, mux) J721E_WKUP_IOPAD(0x134, mode, mux) /* K26: MCU_ADC0_AIN1 K26_AA26 */
+#define P9_40B(mode, mux) J721E_IOPAD(0x148, mode, mux) /* AA26: PRG0_PRU1_GPO18 K26_AA26 */
+#define P9_41(mode, mux) J721E_IOPAD(0x204, mode, mux) /* AD5: UART1_RTSn AD5_EQEP0_I */
+#define P9_42A(mode, mux) J721E_IOPAD(0x1F0, mode, mux) /* AC2: UART0_CTSn AC2_AJ21 */
+#define P9_42B(mode, mux) J721E_IOPAD(0x4C, mode, mux) /* AJ21: PRG1_PRU0_GPO17 AC2_AJ21 */
+
+#endif
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
index 5ec4137231e30..7d57063b8a651 100644
--- a/include/dt-bindings/clock/dra7.h
+++ b/include/dt-bindings/clock/dra7.h
@@ -84,6 +84,10 @@
#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+/* iva clocks */
+#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+
/* dss clocks */
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h
index 41775272fd275..90e0d4b00127d 100644
--- a/include/dt-bindings/clock/omap5.h
+++ b/include/dt-bindings/clock/omap5.h
@@ -32,6 +32,8 @@
/* l3main2 clocks */
#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_L3_MAIN_2_GPMC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
/* ipu clocks */
#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
index f48245ff87e5f..6257180424132 100644
--- a/include/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -64,8 +64,8 @@
#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
-#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0)
-#define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux)
+#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_PADCONF(pa, dir, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux))
/*
* Macros to allow using the offset from the padconf physical address
--
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