diff --git a/patch.sh b/patch.sh
index bf8225063ec8026e90c7a9720172f1c13398ca0d..d1cdf9698cc15c233537ad90cbcb2eb204f705fb 100644
--- a/patch.sh
+++ b/patch.sh
@@ -70,6 +70,17 @@ usb () {
${git} "${DIR}/patches/usb/0003-usb-musb-musb_cppi41-Handle-ISOCH-differently-and-no.patch"
}
+reset () {
+ echo "dir: reset"
+ ${git} "${DIR}/patches/reset/0001-drivers-reset-TI-SoC-reset-controller-support.patch"
+ ${git} "${DIR}/patches/reset/0002-ARM-TI-Describe-the-ti-reset-DT-entries.patch"
+ ${git} "${DIR}/patches/reset/0003-ARM-dts-am33xx-Add-prcm_resets-node.patch"
+ ${git} "${DIR}/patches/reset/0004-ARM-dts-am4372-Add-prcm_resets-node.patch"
+ ${git} "${DIR}/patches/reset/0005-ARM-dts-dra7-Add-prm_resets-node.patch"
+ ${git} "${DIR}/patches/reset/0006-ARM-dts-omap5-Add-prm_resets-node.patch"
+ ${git} "${DIR}/patches/reset/0007-SGX-reset-function-needed.patch"
+}
+
sgx () {
echo "dir: sgx"
${git} "${DIR}/patches/sgx/0001-reset-Add-driver-for-gpio-controlled-reset-pins.patch"
@@ -115,6 +126,7 @@ rt () {
dts
fixes
#usb
+reset
#sgx
dts_bone
diff --git a/patches/defconfig b/patches/defconfig
index 631772431126152fb403f8cca7e060071c32ddb8..8217b37ef1d57a46e2afcea46c568ecf005843d4 100644
--- a/patches/defconfig
+++ b/patches/defconfig
@@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
-# Linux/arm 3.15.0-rc5 Kernel Configuration
+# Linux/arm 3.15.0 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_ARM_HAS_SG_CHAIN=y
@@ -4623,6 +4623,7 @@ CONFIG_PWM_TWL_LED=y
CONFIG_IRQCHIP=y
# CONFIG_IPACK_BUS is not set
CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_TI=y
# CONFIG_FMC is not set
#
diff --git a/patches/reset/0001-drivers-reset-TI-SoC-reset-controller-support.patch b/patches/reset/0001-drivers-reset-TI-SoC-reset-controller-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..dd1b09d7e3099d8975960a17d4f2de97f313903c
--- /dev/null
+++ b/patches/reset/0001-drivers-reset-TI-SoC-reset-controller-support.patch
@@ -0,0 +1,416 @@
+From e1aba45800304e7f26227705f447d6e3e4c51897 Mon Sep 17 00:00:00 2001
+From: Dan Murphy <dmurphy@ti.com>
+Date: Mon, 5 May 2014 15:09:22 -0500
+Subject: [PATCH 1/6] drivers: reset: TI: SoC reset controller support.
+
+The TI SoC reset controller support utilizes the
+reset controller framework to give device drivers or
+function drivers a common set of APIs to call to reset
+a module.
+
+The reset-ti is a common interface to the reset framework.
+ The register data is retrieved during initialization
+ of the reset driver through the reset-ti-data
+file. The array of data is associated with the compatible from the
+respective DT entry.
+
+Once the data is available then this is derefenced within the common
+interface.
+
+The device driver has the ability to assert, deassert or perform a
+complete reset.
+
+This code was derived from previous work by Rajendra Nayak and Afzal Mohammed.
+The code was changed to adopt to the reset core and abstract away the SoC information.
+
+Signed-off-by: Dan Murphy <dmurphy@ti.com>
+---
+ drivers/reset/Kconfig | 1 +
+ drivers/reset/Makefile | 1 +
+ drivers/reset/ti/Kconfig | 8 ++
+ drivers/reset/ti/Makefile | 1 +
+ drivers/reset/ti/reset-ti-data.h | 56 ++++++++
+ drivers/reset/ti/reset-ti.c | 267 +++++++++++++++++++++++++++++++++++++++
+ 6 files changed, 334 insertions(+)
+ create mode 100644 drivers/reset/ti/Kconfig
+ create mode 100644 drivers/reset/ti/Makefile
+ create mode 100644 drivers/reset/ti/reset-ti-data.h
+ create mode 100644 drivers/reset/ti/reset-ti.c
+
+diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
+index 0615f50..a58d789 100644
+--- a/drivers/reset/Kconfig
++++ b/drivers/reset/Kconfig
+@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
+ If unsure, say no.
+
+ source "drivers/reset/sti/Kconfig"
++source "drivers/reset/ti/Kconfig"
+diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
+index 4f60caf..1c8c444 100644
+--- a/drivers/reset/Makefile
++++ b/drivers/reset/Makefile
+@@ -1,3 +1,4 @@
+ obj-$(CONFIG_RESET_CONTROLLER) += core.o
+ obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
+ obj-$(CONFIG_ARCH_STI) += sti/
++obj-$(CONFIG_RESET_TI) += ti/
+diff --git a/drivers/reset/ti/Kconfig b/drivers/reset/ti/Kconfig
+new file mode 100644
+index 0000000..dcdce90
+--- /dev/null
++++ b/drivers/reset/ti/Kconfig
+@@ -0,0 +1,8 @@
++config RESET_TI
++ depends on RESET_CONTROLLER
++ bool "TI reset controller"
++ help
++ Reset controller support for TI SoC's
++
++ Reset controller found in TI's AM series of SoC's like
++ AM335x and AM43x and OMAP SoC's like OMAP5 and DRA7
+diff --git a/drivers/reset/ti/Makefile b/drivers/reset/ti/Makefile
+new file mode 100644
+index 0000000..55ab3f5
+--- /dev/null
++++ b/drivers/reset/ti/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_RESET_TI) += reset-ti.o
+diff --git a/drivers/reset/ti/reset-ti-data.h b/drivers/reset/ti/reset-ti-data.h
+new file mode 100644
+index 0000000..4d2a6d5
+--- /dev/null
++++ b/drivers/reset/ti/reset-ti-data.h
+@@ -0,0 +1,56 @@
++/*
++ * PRCM reset driver for TI SoC's
++ *
++ * Copyright 2014 Texas Instruments Inc.
++ *
++ * Author: Dan Murphy <dmurphy@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef _RESET_TI_DATA_H_
++#define _RESET_TI_DATA_H_
++
++#include <linux/kernel.h>
++#include <linux/reset-controller.h>
++
++/**
++ * struct ti_reset_reg_data - Structure of the reset register information
++ * for a particular SoC.
++ * @rstctrl_offs: This is the reset control offset value from
++ * from the parent reset node.
++ * @rstst_offs: This is the reset status offset value from
++ * from the parent reset node.
++ * @rstctrl_bit: This is the reset control bit for the module.
++ * @rstst_bit: This is the reset status bit for the module.
++ *
++ * This structure describes the reset register control and status offsets.
++ * The bits are also defined for the same.
++ */
++struct ti_reset_reg_data {
++ void __iomem *reg_base;
++ u32 rstctrl_offs;
++ u32 rstst_offs;
++ u32 rstctrl_bit;
++ u32 rstst_bit;
++};
++
++/**
++ * struct ti_reset_data - Structure that contains the reset register data
++ * as well as the total number of resets for a particular SoC.
++ * @reg_data: Pointer to the register data structure.
++ * @nr_resets: Total number of resets for the SoC in the reset array.
++ *
++ * This structure contains a pointer to the register data and the modules
++ * register base. The number of resets and reset controller device data is
++ * stored within this structure.
++ *
++ */
++struct ti_reset_data {
++ struct ti_reset_reg_data *reg_data;
++ struct reset_controller_dev rcdev;
++};
++
++#endif
+diff --git a/drivers/reset/ti/reset-ti.c b/drivers/reset/ti/reset-ti.c
+new file mode 100644
+index 0000000..349f4fb
+--- /dev/null
++++ b/drivers/reset/ti/reset-ti.c
+@@ -0,0 +1,267 @@
++/*
++ * PRCM reset driver for TI SoC's
++ *
++ * Copyright 2014 Texas Instruments Inc.
++ *
++ * Author: Dan Murphy <dmurphy@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#include "reset-ti-data.h"
++
++#define DRIVER_NAME "prcm_reset_ti"
++
++static struct ti_reset_data *ti_data;
++
++static int ti_reset_get_of_data(struct ti_reset_reg_data *reset_data,
++ unsigned long id)
++{
++ struct device_node *dev_node;
++ struct device_node *parent;
++ struct device_node *prcm_parent;
++ struct device_node *reset_parent;
++ int ret = -EINVAL;
++
++ dev_node = of_find_node_by_phandle((phandle) id);
++ if (!dev_node) {
++ pr_err("%s: Cannot find phandle node\n", __func__);
++ return ret;
++ }
++
++ /* node parent */
++ parent = of_get_parent(dev_node);
++ if (!parent) {
++ pr_err("%s: Cannot find parent reset node\n", __func__);
++ return ret;
++ }
++ /* prcm reset parent */
++ reset_parent = of_get_next_parent(parent);
++ if (!reset_parent) {
++ pr_err("%s: Cannot find parent reset node\n", __func__);
++ return ret;
++ }
++ /* PRCM Parent */
++ reset_parent = of_get_parent(reset_parent);
++ if (!prcm_parent) {
++ pr_err("%s: Cannot find parent reset node\n", __func__);
++ return ret;
++ }
++
++ reset_data->reg_base = of_iomap(reset_parent, 0);
++ if (!reset_data->reg_base) {
++ pr_err("%s: Cannot map reset parent.\n", __func__);
++ return ret;
++ }
++
++ ret = of_property_read_u32_index(parent, "reg", 0,
++ &reset_data->rstctrl_offs);
++ if (ret)
++ return ret;
++
++ ret = of_property_read_u32_index(parent, "reg", 1,
++ &reset_data->rstst_offs);
++ if (ret)
++ return ret;
++
++ ret = of_property_read_u32(dev_node, "control-bit",
++ &reset_data->rstctrl_bit);
++ if (ret < 0)
++ pr_err("%s: No entry in %s for rstst_offs\n", __func__,
++ dev_node->name);
++
++ ret = of_property_read_u32(dev_node, "status-bit",
++ &reset_data->rstst_bit);
++ if (ret < 0)
++ pr_err("%s: No entry in %s for rstst_offs\n", __func__,
++ dev_node->name);
++
++ return 0;
++}
++
++static void ti_reset_wait_on_reset(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ struct ti_reset_reg_data *temp_reg_data;
++ void __iomem *status_reg;
++ u32 bit_mask = 0;
++ u32 val = 0;
++
++ temp_reg_data = kzalloc(sizeof(struct ti_reset_reg_data), GFP_KERNEL);
++ ti_reset_get_of_data(temp_reg_data, id);
++
++ /* Clear the reset status bit to reflect the current status */
++ status_reg = temp_reg_data->reg_base + temp_reg_data->rstst_offs;
++ bit_mask = temp_reg_data->rstst_bit;
++ do {
++ val = readl(status_reg);
++ if (!(val & (1 << bit_mask)))
++ break;
++ } while (1);
++}
++
++static int ti_reset_assert(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ struct ti_reset_reg_data *temp_reg_data;
++ void __iomem *reg;
++ void __iomem *status_reg;
++ u32 status_bit = 0;
++ u32 bit_mask = 0;
++ u32 val = 0;
++
++ temp_reg_data = kzalloc(sizeof(struct ti_reset_reg_data), GFP_KERNEL);
++ ti_reset_get_of_data(temp_reg_data, id);
++
++ /* Clear the reset status bit to reflect the current status */
++ status_reg = temp_reg_data->reg_base + temp_reg_data->rstst_offs;
++ status_bit = temp_reg_data->rstst_bit;
++ writel(1 << status_bit, status_reg);
++
++ reg = temp_reg_data->reg_base + temp_reg_data->rstctrl_offs;
++ bit_mask = temp_reg_data->rstctrl_bit;
++ val = readl(reg);
++ if (!(val & bit_mask)) {
++ val |= bit_mask;
++ writel(val, reg);
++ }
++
++ kfree(temp_reg_data);
++
++ return 0;
++}
++
++static int ti_reset_deassert(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++
++ struct ti_reset_reg_data *temp_reg_data;
++ void __iomem *reg;
++ void __iomem *status_reg;
++ u32 status_bit = 0;
++ u32 bit_mask = 0;
++ u32 val = 0;
++
++ temp_reg_data = kzalloc(sizeof(struct ti_reset_reg_data), GFP_KERNEL);
++ ti_reset_get_of_data(temp_reg_data, id);
++
++ /* Clear the reset status bit to reflect the current status */
++ status_reg = temp_reg_data->reg_base + temp_reg_data->rstst_offs;
++ status_bit = temp_reg_data->rstst_bit;
++ writel(1 << status_bit, status_reg);
++
++ reg = temp_reg_data->reg_base + temp_reg_data->rstctrl_offs;
++ bit_mask = temp_reg_data->rstctrl_bit;
++ val = readl(reg);
++ if (val & bit_mask) {
++ val &= ~bit_mask;
++ writel(val, reg);
++ }
++
++ return 0;
++}
++
++static int ti_reset_reset(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ ti_reset_assert(rcdev, id);
++ ti_reset_deassert(rcdev, id);
++ ti_reset_wait_on_reset(rcdev, id);
++
++ return 0;
++}
++
++static int ti_reset_xlate(struct reset_controller_dev *rcdev,
++ const struct of_phandle_args *reset_spec)
++{
++ struct device_node *dev_node;
++
++ if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
++ return -EINVAL;
++
++ /* Verify that the phandle exists */
++ dev_node = of_find_node_by_phandle((phandle) reset_spec->args[0]);
++ if (!dev_node) {
++ pr_err("%s: Cannot find phandle node\n", __func__);
++ return -EINVAL;
++ }
++
++ return reset_spec->args[0];
++}
++
++static struct reset_control_ops ti_reset_ops = {
++ .reset = ti_reset_reset,
++ .assert = ti_reset_assert,
++ .deassert = ti_reset_deassert,
++};
++
++static int ti_reset_probe(struct platform_device *pdev)
++{
++ struct device_node *resets;
++
++ resets = of_find_node_by_name(NULL, "resets");
++ if (!resets) {
++ pr_err("%s: missing 'resets' child node.\n", __func__);
++ return -EINVAL;
++ }
++
++ ti_data = kzalloc(sizeof(*ti_data), GFP_KERNEL);
++ if (!ti_data)
++ return -ENOMEM;
++
++ ti_data->rcdev.owner = THIS_MODULE;
++ ti_data->rcdev.of_node = resets;
++ ti_data->rcdev.ops = &ti_reset_ops;
++
++ ti_data->rcdev.of_reset_n_cells = 1;
++ ti_data->rcdev.of_xlate = &ti_reset_xlate;
++
++ reset_controller_register(&ti_data->rcdev);
++
++ return 0;
++}
++
++static int ti_reset_remove(struct platform_device *pdev)
++{
++ reset_controller_unregister(&ti_data->rcdev);
++
++ return 0;
++}
++
++static const struct of_device_id ti_reset_of_match[] = {
++ { .compatible = "ti,omap5-prm" },
++ { .compatible = "ti,omap4-prm" },
++ { .compatible = "ti,omap5-prm" },
++ { .compatible = "ti,dra7-prm" },
++ { .compatible = "ti,am4-prcm" },
++ { .compatible = "ti,am3-prcm" },
++ {},
++};
++
++static struct platform_driver ti_reset_driver = {
++ .probe = ti_reset_probe,
++ .remove = ti_reset_remove,
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(ti_reset_of_match),
++ },
++};
++module_platform_driver(ti_reset_driver);
++
++MODULE_DESCRIPTION("PRCM reset driver for TI SoCs");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:" DRIVER_NAME);
+--
+2.0.0
+
diff --git a/patches/reset/0002-ARM-TI-Describe-the-ti-reset-DT-entries.patch b/patches/reset/0002-ARM-TI-Describe-the-ti-reset-DT-entries.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f62084be9a0eb368e2819ecded45fd0bc18f1563
--- /dev/null
+++ b/patches/reset/0002-ARM-TI-Describe-the-ti-reset-DT-entries.patch
@@ -0,0 +1,125 @@
+From f4c977f7386f0711b72cae023c4f21bd103d2037 Mon Sep 17 00:00:00 2001
+From: Dan Murphy <dmurphy@ti.com>
+Date: Mon, 5 May 2014 15:09:23 -0500
+Subject: [PATCH 2/6] ARM: TI: Describe the ti reset DT entries
+
+Describe the TI reset DT entries for TI SoC's.
+
+Signed-off-by: Dan Murphy <dmurphy@ti.com>
+---
+ .../devicetree/bindings/reset/ti,reset.txt | 103 +++++++++++++++++++++
+ 1 file changed, 103 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/reset/ti,reset.txt
+
+diff --git a/Documentation/devicetree/bindings/reset/ti,reset.txt b/Documentation/devicetree/bindings/reset/ti,reset.txt
+new file mode 100644
+index 0000000..9d5c29c
+--- /dev/null
++++ b/Documentation/devicetree/bindings/reset/ti,reset.txt
+@@ -0,0 +1,103 @@
++Texas Instruments Reset Controller
++======================================
++Please also refer to reset.txt in this directory for common reset
++controller binding usage.
++
++Specifying the reset entries for the IP module
++==============================================
++Parent module:
++This is the module node that contains the reset registers and bits.
++
++example:
++ prcm_resets: resets {
++ compatible = "ti,dra7-resets";
++ #reset-cells = <1>;
++ };
++
++Required parent properties:
++- compatible : Should be one of,
++ "ti,omap4-prm" for OMAP4 PRM instances
++ "ti,omap5-prm" for OMAP5 PRM instances
++ "ti,dra7-prm" for DRA7xx PRM instances
++ "ti,am4-prcm" for AM43xx PRCM instances
++ "ti,am3-prcm" for AM33xx PRCM instances
++
++Required child reset property:
++- compatible : Should be
++ "resets" for All TI SoCs
++
++example:
++ prm: prm@4ae06000 {
++ compatible = "ti,omap5-prm";
++ reg = <0x4ae06000 0x3000>;
++
++ prm_resets: resets {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ #reset-cells = <1>;
++ };
++ };
++
++
++Reset node declaration
++==============================================
++The reset node is declared in a parent child relationship. The main parent
++is the PRCM module which contains the base address. The first child within
++the reset parent declares the target modules reset name. This is followed by
++the control and status offsets.
++
++Within the first reset child node is a secondary child node which declares the
++reset signal of interest. Under this node the control and status bits
++are declared. These bits declare the bit mask for the target reset.
++
++
++Required properties:
++reg - This is the register offset from the PRCM parent.
++ This must be declared as:
++
++ reg = <control register offset>,
++ <status register offset>;
++
++control-bit - This is the bit within the register which controls the reset
++ of the target module. This is declared as a bit mask for the register.
++status-bit - This is the bit within the register which contains the status of
++ the reset of the target module.
++ This is declared as a bit mask for the register.
++
++example:
++&prm_resets {
++ dsp_rstctrl {
++ reg = <0x1c00>,
++ <0x1c04>;
++
++ dsp_reset: dsp_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++};
++
++
++
++Client Node Declaration
++==============================================
++This is the consumer of the parent node to declare what resets this
++particular module is interested in.
++
++example:
++ src: src@55082000 {
++ resets = <&reset_src phandle>;
++ reset-names = "<reset_name>";
++ };
++
++Required Properties:
++reset_src - This is the parent DT entry for the reset controller
++phandle - This is the phandle of the specific reset to be used by the clien
++ driver.
++reset-names - This is the reset name of module that the device driver
++ needs to be able to reset. This value must correspond to a value within
++ the reset controller array.
++
++example:
++resets = <&prm_resets &dsp_mmu_reset>;
++reset-names = "dsp_mmu_reset";
+--
+2.0.0
+
diff --git a/patches/reset/0003-ARM-dts-am33xx-Add-prcm_resets-node.patch b/patches/reset/0003-ARM-dts-am33xx-Add-prcm_resets-node.patch
new file mode 100644
index 0000000000000000000000000000000000000000..61614bf06df53c5054fd16919ed668c2966705bb
--- /dev/null
+++ b/patches/reset/0003-ARM-dts-am33xx-Add-prcm_resets-node.patch
@@ -0,0 +1,91 @@
+From 94ba5be0d1a7271bbdfc12616a5680fa3780f40e Mon Sep 17 00:00:00 2001
+From: Dan Murphy <dmurphy@ti.com>
+Date: Mon, 5 May 2014 15:09:24 -0500
+Subject: [PATCH 3/6] ARM: dts: am33xx: Add prcm_resets node
+
+Add the prcm_resets node to the prcm parent node.
+
+Add the am33xx_resets file to define the
+am33xx reset lines that are handled by this reset
+framework.
+
+Signed-off-by: Dan Murphy <dmurphy@ti.com>
+---
+ arch/arm/boot/dts/am33xx-resets.dtsi | 42 ++++++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/am33xx.dtsi | 7 ++++++
+ 2 files changed, 49 insertions(+)
+ create mode 100644 arch/arm/boot/dts/am33xx-resets.dtsi
+
+diff --git a/arch/arm/boot/dts/am33xx-resets.dtsi b/arch/arm/boot/dts/am33xx-resets.dtsi
+new file mode 100644
+index 0000000..9260626
+--- /dev/null
++++ b/arch/arm/boot/dts/am33xx-resets.dtsi
+@@ -0,0 +1,42 @@
++/*
++ * Device Tree Source for AM33XX reset data
++ *
++ * Copyright (C) 2014 Texas Instruments, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++&prcm_resets {
++ gfx_rstctrl {
++ reg = <0x1104>,
++ <0x1114>;
++
++ gfx_reset: gfx_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++ per_rstctrl {
++ reg = <0xD00>,
++ <0xD0C>;
++
++ iva_reset: iva_reset {
++ control-bit = <0x04>;
++ status-bit = <0x10>;
++ };
++ };
++
++ device_rstctrl {
++ reg = <0xf00>,
++ <0xf08>;
++
++ device_reset: device_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++};
+diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
+index 7ad75b4..7f73147 100644
+--- a/arch/arm/boot/dts/am33xx.dtsi
++++ b/arch/arm/boot/dts/am33xx.dtsi
+@@ -117,6 +117,12 @@
+
+ prcm_clockdomains: clockdomains {
+ };
++
++ prcm_resets: resets {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ #reset-cells = <1>;
++ };
+ };
+
+ scrm: scrm@44e10000 {
+@@ -833,3 +839,4 @@
+ };
+
+ /include/ "am33xx-clocks.dtsi"
++/include/ "am33xx-resets.dtsi"
+--
+2.0.0
+
diff --git a/patches/reset/0004-ARM-dts-am4372-Add-prcm_resets-node.patch b/patches/reset/0004-ARM-dts-am4372-Add-prcm_resets-node.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8eaa3e88f262db62e12e897656dc4f00381186b6
--- /dev/null
+++ b/patches/reset/0004-ARM-dts-am4372-Add-prcm_resets-node.patch
@@ -0,0 +1,101 @@
+From df85d4a5a48471933706c0bda518cd165c93b7bd Mon Sep 17 00:00:00 2001
+From: Dan Murphy <dmurphy@ti.com>
+Date: Mon, 5 May 2014 15:09:25 -0500
+Subject: [PATCH 4/6] ARM: dts: am4372: Add prcm_resets node
+
+Add the prcm_resets node to the prcm parent node.
+
+Add the am34xx_resets file to define the
+am34xx reset lines that are handled by this reset
+framework.
+
+Signed-off-by: Dan Murphy <dmurphy@ti.com>
+---
+ arch/arm/boot/dts/am4372.dtsi | 7 +++++
+ arch/arm/boot/dts/am43xx-resets.dtsi | 52 ++++++++++++++++++++++++++++++++++++
+ 2 files changed, 59 insertions(+)
+ create mode 100644 arch/arm/boot/dts/am43xx-resets.dtsi
+
+diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
+index d1f8707..e1ba7ed 100644
+--- a/arch/arm/boot/dts/am4372.dtsi
++++ b/arch/arm/boot/dts/am4372.dtsi
+@@ -84,6 +84,12 @@
+
+ prcm_clockdomains: clockdomains {
+ };
++
++ prcm_resets: resets {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ #reset-cells = <1>;
++ };
+ };
+
+ scrm: scrm@44e10000 {
+@@ -739,3 +745,4 @@
+ };
+
+ /include/ "am43xx-clocks.dtsi"
++/include/ "am43xx-resets.dtsi"
+diff --git a/arch/arm/boot/dts/am43xx-resets.dtsi b/arch/arm/boot/dts/am43xx-resets.dtsi
+new file mode 100644
+index 0000000..ef338ba
+--- /dev/null
++++ b/arch/arm/boot/dts/am43xx-resets.dtsi
+@@ -0,0 +1,52 @@
++/*
++ * Device Tree Source for AM43XX reset data
++ *
++ * Copyright (C) 2014 Texas Instruments, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++&prcm_resets {
++ icss_rstctrl {
++ reg = <0x810>,
++ <0x814>;
++
++ icss_reset: icss_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++ gfx_rstctrl {
++ reg = <0x410>,
++ <0x414>;
++
++ gfx_reset: gfx_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++ per_rstctrl {
++ reg = <0x2010>,
++ <0x2014>;
++
++ iva_reset: iva_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++ device_rstctrl {
++ reg = <0x4000>,
++ <0x4004>;
++
++ device_reset: device_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++};
+--
+2.0.0
+
diff --git a/patches/reset/0005-ARM-dts-dra7-Add-prm_resets-node.patch b/patches/reset/0005-ARM-dts-dra7-Add-prm_resets-node.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e68e8fb1f5b457fefb24f99800c0938f2059ba36
--- /dev/null
+++ b/patches/reset/0005-ARM-dts-dra7-Add-prm_resets-node.patch
@@ -0,0 +1,131 @@
+From 19fb779fff4b2363617bc7650b62b06f01692201 Mon Sep 17 00:00:00 2001
+From: Dan Murphy <dmurphy@ti.com>
+Date: Mon, 5 May 2014 15:09:26 -0500
+Subject: [PATCH 5/6] ARM: dts: dra7: Add prm_resets node
+
+Add the prcm_resets node to the prm parent node.
+
+Add the draxx_resets file to define the
+dra7xx reset lines that are handled by this reset
+framework.
+
+Signed-off-by: Dan Murphy <dmurphy@ti.com>
+---
+ arch/arm/boot/dts/dra7.dtsi | 7 +++
+ arch/arm/boot/dts/dra7xx-resets.dtsi | 82 ++++++++++++++++++++++++++++++++++++
+ 2 files changed, 89 insertions(+)
+ create mode 100644 arch/arm/boot/dts/dra7xx-resets.dtsi
+
+diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
+index 149b550..c008996 100644
+--- a/arch/arm/boot/dts/dra7.dtsi
++++ b/arch/arm/boot/dts/dra7.dtsi
+@@ -120,6 +120,12 @@
+
+ prm_clockdomains: clockdomains {
+ };
++
++ prm_resets: resets {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ #reset-cells = <1>;
++ };
+ };
+
+ cm_core_aon: cm_core_aon@4a005000 {
+@@ -793,3 +799,4 @@
+ };
+
+ /include/ "dra7xx-clocks.dtsi"
++/include/ "dra7xx-resets.dtsi"
+diff --git a/arch/arm/boot/dts/dra7xx-resets.dtsi b/arch/arm/boot/dts/dra7xx-resets.dtsi
+new file mode 100644
+index 0000000..4c4966d
+--- /dev/null
++++ b/arch/arm/boot/dts/dra7xx-resets.dtsi
+@@ -0,0 +1,82 @@
++/*
++ * Device Tree Source for DRA7XX reset data
++ *
++ * Copyright (C) 2014 Texas Instruments, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++&prm_resets {
++ dsp_rstctrl {
++ reg = <0x410>,
++ <0x414>;
++
++ dsp_reset: dsp_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++
++ dsp_mmu_reset: dsp_mmu_reset {
++ control-bit = <0x02>;
++ status-bit = <0x02>;
++ };
++ };
++
++ ipu_rstctrl {
++ reg = <0x510>,
++ <0x514>;
++
++ ipu_cpu0_reset: ipu_cpu0_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++
++ ipu_cpu1_reset: ipu_cpu1_reset {
++ control-bit = <0x02>;
++ status-bit = <0x02>;
++ };
++
++ ipu_mmu_reset: ipu_mmu_reset {
++ control-bit = <0x04>;
++ status-bit = <0x04>;
++ };
++ };
++
++ iva_rstctrl {
++ reg = <0xf10>,
++ <0xf14>;
++
++ iva_reset: iva_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++ pcie_rstctrl {
++ reg = <0x1310>,
++ <0x1314>;
++
++ pcie1_reset: pcie1_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++
++ pcie2_reset: pcie2_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++ device_rstctrl {
++ reg = <0x1D00>,
++ <0x1D04>;
++
++ device_reset: device_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++};
+--
+2.0.0
+
diff --git a/patches/reset/0006-ARM-dts-omap5-Add-prm_resets-node.patch b/patches/reset/0006-ARM-dts-omap5-Add-prm_resets-node.patch
new file mode 100644
index 0000000000000000000000000000000000000000..087d1635ced539018bc62e32aa07f00078bd4c8e
--- /dev/null
+++ b/patches/reset/0006-ARM-dts-omap5-Add-prm_resets-node.patch
@@ -0,0 +1,115 @@
+From 11f4c821248dd0cbcfc8f0e71c6bcf78f2dcb795 Mon Sep 17 00:00:00 2001
+From: Dan Murphy <dmurphy@ti.com>
+Date: Mon, 5 May 2014 15:09:27 -0500
+Subject: [PATCH 6/6] ARM: dts: omap5: Add prm_resets node
+
+Add the prm_resets node to the prm parent node.
+
+Add the omap54xx_resets file to define the
+omap5 reset lines that are handled by this reset
+framework.
+
+Signed-off-by: Dan Murphy <dmurphy@ti.com>
+---
+ arch/arm/boot/dts/omap5.dtsi | 7 ++++
+ arch/arm/boot/dts/omap54xx-resets.dtsi | 66 ++++++++++++++++++++++++++++++++++
+ 2 files changed, 73 insertions(+)
+ create mode 100644 arch/arm/boot/dts/omap54xx-resets.dtsi
+
+diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
+index 36b4312..d750052 100644
+--- a/arch/arm/boot/dts/omap5.dtsi
++++ b/arch/arm/boot/dts/omap5.dtsi
+@@ -134,6 +134,12 @@
+
+ prm_clockdomains: clockdomains {
+ };
++
++ prm_resets: resets {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ #reset-cells = <1>;
++ };
+ };
+
+ cm_core_aon: cm_core_aon@4a004000 {
+@@ -880,3 +886,4 @@
+ };
+
+ /include/ "omap54xx-clocks.dtsi"
++/include/ "omap54xx-resets.dtsi"
+diff --git a/arch/arm/boot/dts/omap54xx-resets.dtsi b/arch/arm/boot/dts/omap54xx-resets.dtsi
+new file mode 100644
+index 0000000..cba6f52
+--- /dev/null
++++ b/arch/arm/boot/dts/omap54xx-resets.dtsi
+@@ -0,0 +1,66 @@
++/*
++ * Device Tree Source for OMAP5 reset data
++ *
++ * Copyright (C) 2014 Texas Instruments, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++&prm_resets {
++ dsp_rstctrl {
++ reg = <0x1c00>,
++ <0x1c04>;
++
++ dsp_reset: dsp_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++
++ dsp_mmu_reset: dsp_mmu_reset {
++ control-bit = <0x02>;
++ status-bit = <0x02>;
++ };
++ };
++
++ ipu_rstctrl {
++ reg = <0x910>,
++ <0x914>;
++
++ ipu_cpu0_reset: ipu_cpu0_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++
++ ipu_cpu1_reset: ipu_cpu1_reset {
++ control-bit = <0x02>;
++ status-bit = <0x02>;
++ };
++
++ ipu_mmu_reset: ipu_mmu_reset {
++ control-bit = <0x04>;
++ status-bit = <0x04>;
++ };
++ };
++
++ iva_rstctrl {
++ reg = <0x1210>,
++ <0x1214>;
++
++ iva_reset: iva_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++
++ device_rstctrl {
++ reg = <0x1c00>,
++ <0x1c04>;
++
++ device_reset: device_reset {
++ control-bit = <0x01>;
++ status-bit = <0x01>;
++ };
++ };
++};
+--
+2.0.0
+
diff --git a/patches/reset/0007-SGX-reset-function-needed.patch b/patches/reset/0007-SGX-reset-function-needed.patch
new file mode 100644
index 0000000000000000000000000000000000000000..62211e326f087d3b9030ae27db8599e41ac7f5f1
--- /dev/null
+++ b/patches/reset/0007-SGX-reset-function-needed.patch
@@ -0,0 +1,84 @@
+From 3259d02fa3413099f5507c7ba60b07e9165477c8 Mon Sep 17 00:00:00 2001
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Thu, 12 Jun 2014 21:56:32 -0500
+Subject: [PATCH 7/7] SGX: reset function needed
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ drivers/reset/core.c | 32 ++++++++++++++++++++++++++++++++
+ include/linux/reset-controller.h | 2 ++
+ include/linux/reset.h | 2 ++
+ 3 files changed, 36 insertions(+)
+
+diff --git a/drivers/reset/core.c b/drivers/reset/core.c
+index baeaf82..55ce8b5 100644
+--- a/drivers/reset/core.c
++++ b/drivers/reset/core.c
+@@ -190,6 +190,38 @@ struct reset_control *of_reset_control_get(struct device_node *node,
+ EXPORT_SYMBOL_GPL(of_reset_control_get);
+
+ /**
++ * reset_control_is_reset - check reset status
++ * @rstc: reset controller
++ *
++ * Returns a boolean or negative error code
++ *
++ */
++int reset_control_is_reset(struct reset_control *rstc)
++{
++ if (rstc->rcdev->ops->is_reset)
++ return rstc->rcdev->ops->is_reset(rstc->rcdev, rstc->id);
++
++ return -ENOSYS;
++}
++EXPORT_SYMBOL_GPL(reset_control_is_reset);
++
++/**
++ * reset_control_clear_reset - clear the reset
++ * @rstc: reset controller
++ *
++ * Returns zero on success or negative error code
++ *
++ */
++int reset_control_clear_reset(struct reset_control *rstc)
++{
++ if (rstc->rcdev->ops->clear_reset)
++ return rstc->rcdev->ops->clear_reset(rstc->rcdev, rstc->id);
++
++ return -ENOSYS;
++}
++EXPORT_SYMBOL_GPL(reset_control_clear_reset);
++
++/**
+ * reset_control_get - Lookup and obtain a reference to a reset controller.
+ * @dev: device to be reset by the controller
+ * @id: reset line name
+diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
+index 41a4695..df03108 100644
+--- a/include/linux/reset-controller.h
++++ b/include/linux/reset-controller.h
+@@ -17,6 +17,8 @@ struct reset_control_ops {
+ int (*reset)(struct reset_controller_dev *rcdev, unsigned long id);
+ int (*assert)(struct reset_controller_dev *rcdev, unsigned long id);
+ int (*deassert)(struct reset_controller_dev *rcdev, unsigned long id);
++ int (*is_reset)(struct reset_controller_dev *rcdev, unsigned long id);
++ int (*clear_reset)(struct reset_controller_dev *rcdev, unsigned long i);
+ };
+
+ struct module;
+diff --git a/include/linux/reset.h b/include/linux/reset.h
+index c0eda50..57ebbe3 100644
+--- a/include/linux/reset.h
++++ b/include/linux/reset.h
+@@ -9,6 +9,8 @@ struct reset_control;
+ int reset_control_reset(struct reset_control *rstc);
+ int reset_control_assert(struct reset_control *rstc);
+ int reset_control_deassert(struct reset_control *rstc);
++int reset_control_is_reset(struct reset_control *rstc);
++int reset_control_clear_reset(struct reset_control *rstc);
+
+ struct reset_control *reset_control_get(struct device *dev, const char *id);
+ void reset_control_put(struct reset_control *rstc);
+--
+2.0.0
+
diff --git a/version.sh b/version.sh
index 7c8d8264fd7735b304bcebd33d07d4e67e5a1a8c..e40522f0c0f26805a1b1487984fbfdf639c33cd8 100644
--- a/version.sh
+++ b/version.sh
@@ -29,7 +29,7 @@ toolchain="gcc_linaro_gnueabihf_4_8"
#Kernel/Build
KERNEL_REL=3.15
KERNEL_TAG=${KERNEL_REL}
-BUILD=bone1
+BUILD=bone1.1
#v3.X-rcX + upto SHA
#KERNEL_SHA=""