diff --git a/build_kernel.sh b/build_kernel.sh
index 7923c51fc7852b6bd58425d5807174306543c076..417ce6e765e110c79b98aea8f4266c195ee8b306 100755
--- a/build_kernel.sh
+++ b/build_kernel.sh
@@ -224,7 +224,7 @@ if [ "${NO_DEVTMPS}" ] ; then
echo ""
else
echo ""
- echo "Building for Debian Squeeze/Sid & Ubuntu 10.04/10.10/11.04"
+ echo "Building for Debian Squeeze/Wheezy/Sid & Ubuntu 10.04/10.10/11.04"
echo ""
fi
diff --git a/patch.sh b/patch.sh
index c9d526994e645de7675fc1d337265ddcaa832993..6765316e440b2b308bcdfacf3474a0327db676f1 100644
--- a/patch.sh
+++ b/patch.sh
@@ -34,6 +34,267 @@ patch -s -p1 < "${DIR}/patches/trivial/0001-arm-fix-oops-in-sched_clock_poll.pat
}
+function for_next {
+echo "for_next from tmlind's tree.."
+
+patch -s -p1 < "${DIR}/patches/for_next/0001-omap-Start-using-CONFIG_SOC_OMAP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0002-arm-omap-i2c-fix-compile-warning.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0003-arm-omap1-fix-compile-warning.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0004-arm-omap1-fix-compile-warnings.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0005-arm-omap1-fix-a-bunch-of-section-mismatches.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0006-arm-omap2-irq-fix-compile-warning.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0007-arm-plat-omap-dma-make-omap_dma_in_1510_mode-static.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0008-arm-mach-omap1-board-h2-make-h2_nand_platdata-static.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0009-arm-mach-omap1-board-innovator-make-innovator_mmc_in.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0010-arm-mach-omap1-board-htcherald-make-htcpld_chips-and.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0011-arm-mach-omap1-board-h3-make-nand_platdata-static.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0012-ARM-OMAP-Allow-platforms-to-hook-reset-cleanly.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0013-arm-mach-omap1-board-voiceblue-add-missing-include.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0014-ARM-omap1-nokia770-mark-some-functions-__init.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0015-ARM-omap-move-omap_get_config-et-al.-to-.init.text.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0016-ARM-omap-move-omap_board_config_kernel-to-.init.data.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0017-wip-fix-section-mismatches-in-omap1_defconfig.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0018-omap-McBSP-Remove-unused-audio-macros-in-mcbsp.h.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0019-ARM-OMAP2-use-early-init-hook.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0020-omap2-Make-omap_hwmod_late_init-into-core_initcall.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0021-omap2-Fix-omap_serial_early_init-to-work-with-init_e.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0022-omap-hwmod-Populate-_mpu_rt_va-later-on-in-omap_hwmo.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0023-TI816X-Update-common-omap-platform-files.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0024-TI816X-Update-common-OMAP-machine-specific-sources.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0025-TI816X-Create-board-support-and-enable-build-for-TI8.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0026-TI816X-Add-low-level-debug-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0027-TI816X-Update-to-use-init_early.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0028-arm-omap2-clksel-fix-compile-warningOrganization-Tex.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0029-OMAP4-hwmod-data-Add-hwspinlock.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0030-usb-musb-AM35x-moving-internal-phy-functions-out-of-.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0031-arm-omap4-usb-explicitly-configure-MUSB-pads.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0032-arm-omap4-4430sdp-drop-ehci-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0033-OMAP2430-hwmod-data-Add-USBOTG.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0034-OMAP3xxx-hwmod-data-Add-USBOTG.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0035-AM35xx-hwmod-data-Add-USBOTG.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0036-OMAP2-musb-hwmod-adaptation-for-musb-registration.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0037-OMAP4-hwmod-data-Add-McSPI.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0038-OMAP4-hwmod-data-Add-timer.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0039-OMAP4-hwmod-data-Add-DSS-DISPC-DSI1-2-RFBI-HDMI-and-.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0040-OMAP4-hwmod-data-Add-mailbox.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0041-OMAP4-hwmod-data-Add-DMIC.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0042-OMAP4-hwmod-data-Add-McBSP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0043-OMAP4-hwmod-data-Add-AESS-McPDM-bandgap-counter_32k-.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0044-OMAP4-hwmod-data-Add-USBOTG.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0045-drivers-hwspinlock-add-framework.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0046-drivers-hwspinlock-add-OMAP-implementation.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0047-omap-add-hwspinlock-device.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0048-OMAP2420-hwmod-data-Add-McSPI.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0049-OMAP2430-hwmod-data-Add-McSPI.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0050-OMAP3-hwmod-data-Add-McSPI.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0051-OMAP-devices-Modify-McSPI-device-to-adapt-to-hwmod-f.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0052-OMAP-runtime-McSPI-driver-runtime-conversion.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0053-omap2plus-omap4-Set-NR_CPU-to-2-instead-of-default-4.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0054-omap4-Remove-FIXME-omap44xx_sram_init-not-implemente.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0055-OMAP4-keypad-Add-the-board-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0056-omap3evm-add-support-for-the-WL12xx-WLAN-module-to-t.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0057-OMAP3EVM-Reset-the-smsc911x-ethernet-controller-in-b.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0058-omap3evm-Change-TWL-related-gpio-API-s-to-gpio-_cans.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0059-OMAP3EVM-Add-vio-regulator-supply-required-for-ads78.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0060-AM-DM37x-DSS-mux-configuration-for-Rev-B-processor-c.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0061-OMAP3EVM-Made-backlight-GPIO-default-state-to-off.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0062-OMAP3EVM-Set-TSC-wakeup-option-in-pad-config.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0063-omap3630-nand-fix-device-size-to-work-in-polled-mode.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0064-omap3-nand-configurable-transfer-type-per-board.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0065-omap-gpmc-enable-irq-mode-in-gpmc.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0066-omap3-nand-prefetch-in-irq-mode-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0067-omap3-nand-configurable-fifo-threshold-to-gain-the-t.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0068-omap3-nand-ecc-layout-select-from-board-file.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0069-omap3-nand-making-ecc-layout-as-compatible-with-romc.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0070-omap3sdp-Fix-regulator-mapping-for-ads7846-TS-contro.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0071-OMAP-OneNAND-fix-104MHz-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0072-OMAP-OneNAND-determine-frequency-in-one-place.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0073-OMAP-OneNAND-let-boards-determine-OneNAND-frequency.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0074-mtd-OneNAND-OMAP2-increase-multiblock-erase-verify-t.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0075-omap-IOMMU-add-missing-function-declaration.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0076-omap3-fix-minor-typos.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0077-omap3-flash-use-pr_err-instead-of-printk.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0078-omap-Add-chip-id-recognition-for-OMAP4-ES2.1-and-ES2.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0079-OMAP4-hwmod-data-Add-rev-and-dev_attr-fields-in-McSP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0080-omap3sdp-clean-regulator-supply-mapping-in-board-fil.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0081-OMAP4-Fix-EINVAL-for-vana-vcxio-vdac.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0082-OMAP2-add-regulator-for-MMC1.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0083-omap-panda-wlan-board-muxing.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0084-omap-select-REGULATOR_FIXED_VOLTAGE-by-default-for-p.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0085-omap-panda-add-fixed-regulator-device-for-wlan.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0086-omap-panda-add-mmc5-wl1271-device-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0087-OMAP-hsmmc-Enable-MMC4-and-MMC5-on-OMAP4-platforms.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0088-OMAP4-hwmod-data-Prevent-timer1-to-be-reset-and-idle.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0089-OMAP2420-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0090-OMAP2430-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0091-OMAP3-hwmod-data-add-DSS-DISPC-RFBI-DSI-VENC.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0092-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0093-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0094-OMAP2-3-DSS2-board-files-replace-platform_device_reg.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0095-omap-iommu-Gracefully-fail-iommu_enable-if-no-arch_i.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0096-omap-iommu-print-module-name-on-error-messages.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0097-OMAP2-hwmod-data-add-mailbox-data.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0098-OMAP3-hwmod-data-add-mailbox-data.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0099-OMAP-mailbox-build-device-using-omap_device-omap_hwm.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0100-OMAP-mailbox-use-runtime-pm-for-clk-and-sysc-handlin.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0101-OMAP-hwmod-allow-hwmod-to-provide-address-space-acce.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0102-OMAP-McBSP-Convert-McBSP-to-platform-device-model.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0103-OMAP2420-hwmod-data-Add-McBSP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0104-OMAP2430-hwmod-data-Add-McBSP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0105-OMAP3-hwmod-data-Add-McBSP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0106-OMAP4-hwmod-Naming-of-address-space.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0107-OMAP3-hwmod-add-dev_attr-for-McBSP-sidetone.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0108-OMAP2-McBSP-hwmod-adaptation-for-McBSP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0109-OMAP-McBSP-use-omap_device-APIs-to-modify-SYSCONFIG.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0110-OMAP-McBSP-Add-pm-runtime-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0111-OMAP-McBSP-APIs-to-pass-DMA-params-from-McBSP-driver.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0112-ASoC-McBSP-get-hw-params-from-McBSP-driver.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0113-OMAP-hwmod-Removal-of-macros-for-data-that-is-obtain.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0114-OMAP2-IOMMU-don-t-print-fault-warning-on-specific-la.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0115-omap-IOMMU-add-support-to-callback-during-fault-hand.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0116-omap-Fix-compile-if-MTD_NAND_OMAP2-is-not-selected.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0117-omap-rx51-Add-SI4713-FM-transmitter.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0118-OMAP3-Touchbook-fix-board-initialization.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0119-omap2-Minimize-board-specific-init_early-calls.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0120-OMAP-powerdomain-remove-unused-func-declaration.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0121-OMAP-clockdomain-Infrastructure-to-put-arch-specific.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0122-OMAP-clockdomain-Arch-specific-funcs-to-handle-deps.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0123-OMAP-clockdomain-Arch-specific-funcs-for-sleep-wakeu.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0124-OMAP-clockdomain-Arch-specific-funcs-for-hwsup-contr.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0125-OMAP-clockdomain-Arch-specific-funcs-for-clkdm_clk_e.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0126-OMAP4-clockdomain-Add-clkdm-static-dependency-srcs.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0127-OMAP4-CM-Add-CM-accesor-api-for-bitwise-control.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0128-OMAP4-clockdomain-Add-wkup-sleep-dependency-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0129-OMAP4-clockdomain-Remove-pr_errs-stating-unsupported.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0130-omap-clock-Check-for-enable-disable-ops-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0131-omap3-dpll-Populate-clkops-for-dpll1_ck.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0132-OMAP-clock-Add-allow_idle-deny_idle-support-in-clkop.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0133-OMAP3-4-DPLL-Add-allow_idle-deny_idle-support-for-al.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0134-OMAP2-clock-autoidle-as-many-clocks-as-possible-if-C.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0135-OMAP4-DPLL-Add-dpll-api-to-control-GATE_CTRL.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0136-omap4-dpll-Enable-auto-gate-control-for-all-MX-postd.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0137-OMAP2-clock-disable-autoidle-on-all-clocks-during-cl.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0138-OMAP2420-hwmod-data-add-dmtimer.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0139-OMAP2430-hwmod-data-add-dmtimer.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0140-OMAP3-hwmod-data-add-dmtimer.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0141-OMAP2-hwmod-allow-multiple-calls-to-omap_hwmod_init.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0142-OMAP2-hwmod-rename-some-init-functions.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0143-OMAP2-hwmod-find-MPU-initiator-hwmod-during-in-_regi.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0144-OMAP2-hwmod-ignore-attempts-to-re-setup-a-hwmod.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0145-OMAP2-hwmod-add-ability-to-setup-individual-hwmods.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0146-OMAP2-clockevent-set-up-GPTIMER-clockevent-hwmod-rig.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0147-OMAP2-sdrc-fix-compile-break-on-OMAP4-only-config-on.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0148-omap-omap3evm-add-support-for-the-WL12xx-WLAN-module.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0149-omap-mmc-split-out-init-for-2420.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0150-OMAP2430-hwmod-data-Add-HSMMC.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0151-OMAP3-hwmod-data-Add-HSMMC.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0152-OMAP4-hwmod-data-enable-HSMMC.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0153-OMAP-hwmod-data-Add-dev_attr-and-use-in-the-host-dri.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0154-OMAP-hsmmc-Move-mux-configuration-to-hsmmc.c.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0155-OMAP-adapt-hsmmc-to-hwmod-framework.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0156-OMAP-hsmmc-Rename-the-device-and-driver.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0157-omap4-clockdomain-Fix-the-CPUx-domain-name.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0158-omap4-powerdomain-Use-intended-PWRSTS_-flags-instead.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0159-OMAP2-omap_device-clock-Do-not-expect-an-entry-in-cl.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0160-MMC-omap_hsmmc-enable-interface-clock-before-calling.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0161-arm-omap-fix-section-mismatch-warning.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0162-ldp-Fix-regulator-mapping-for-ads7846-TS-controller.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0163-omap-panda-Add-TI-ST-driver-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0164-omap-rx51-Add-support-for-vibra.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0165-omap-Remove-unnecessary-twl4030_codec_audio-settings.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0166-mfd-twl4030_codec-Remove-unused-and-duplicate-audio_.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0167-Revert-OMAP4-hwmod-data-Prevent-timer1-to-be-reset-a.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0168-OMAP2-3-WKUP-powerdomain-mark-as-being-always-on.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0169-OMAP2-powerdomain-fix-bank-power-state-bitfields.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0170-OMAP2-powerdomain-add-pwrdm_can_ever_lose_context.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0171-OMAP2-clock-add-DPLL-autoidle-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0172-OMAP2xxx-clock-add-clockfw-autoidle-support-for-APLL.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0173-OMAP2-clock-comment-that-osc_ck-osc_sys_ck-should-us.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0174-OMAP2-clock-add-interface-clock-type-code-with-autoi.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0175-OMAP2420-clock-add-sdrc_ick.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0176-OMAP2420-clock-use-autoidle-clkops-for-all-autoidle-.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0177-OMAP2430-3xxx-clock-add-modem-clock-autoidle-support.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0178-OMAP2430-clock-use-autoidle-clkops-for-all-autoidle-.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0179-OMAP3-clock-use-autoidle-clkops-for-all-autoidle-con.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0180-OMAP2-3-PM-remove-manual-CM_AUTOIDLE-bit-setting-in-.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0181-OMAP-smartreflex-move-plat-smartreflex.h-to-mach-oma.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0182-OMAP-voltage-move-plat-voltage.h-to-mach-omap2-volta.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0183-OMAP2xxx-clock-fix-parents-for-L3-derived-clocks.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0184-OMAP2xxx-clock-fix-low-frequency-oscillator-clock-ra.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0185-OMAP2xxx-clock-fix-interface-clocks-and-clockdomains.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0186-OMAP-clock-bail-out-early-if-arch_clock-functions-no.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0187-OMAP2-clock-remove-the-DPLL-rate-tolerance-code.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0188-OMAP2xxx-clock-remove-dsp_irate_ick.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0189-omap2-3-clockdomains-fix-compile-time-warnings.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0190-OMAP2xxx-clock-fix-clockdomains-on-gpt7_ick-2430-mmc.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0191-OMAP2xxx-clock-data-clean-up-some-comments.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0192-OMAP1-McBSP-fix-build-break-for-non-multi-OMAP1-conf.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0193-audio-AM3517-Adding-i2c-info-for-AIC23-codec.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0194-OMAP3-hwmod_data-Add-address-space-and-irq-in-L3-hwm.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0195-OMAP3-devices-Initialise-the-l3-device-with-the-hwmo.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0196-OMAP3-l3-Introduce-l3-interconnect-error-handling-dr.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0197-OMAP4-hwmod_data-Add-address-space-and-irq-in-L3-hwm.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0198-OMAP4-Initialise-the-l3-device-with-the-hwmod-data.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0199-OMAP4-l3-Introduce-l3-interconnect-error-handling-dr.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0200-OMAP2-3-VENC-hwmod-add-OCPIF_SWSUP_IDLE-flag-to-inte.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0201-MAINTAINERS-update-Kevin-s-email-for-OMAP-PM-section.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0202-OMAP3630-PM-don-t-warn-the-user-with-a-trace-in-case.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0203-OMAP3-4-OPP-make-omapx_opp_init-non-static.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0204-OMAP3-beagle-xm-enable-up-to-800MHz-OPP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0205-OMAP-PM-SmartReflex-fix-potential-NULL-dereference.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0206-OMAP2-remove-unused-UART-base-addresses-from-omap_gl.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0207-OMAP2-3-PM-remove-unnecessary-wakeup-sleep-dependenc.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0208-omap3-pm-Use-exported-set_cr-instead-of-a-custom-one.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0209-omap3-cpuidle-Add-description-field-to-each-C-state.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0210-OMAP3-PM-Set-clear-T2-bit-for-Smartreflex-on-TWL.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0211-OMAP3-PM-Initialize-IVA-only-if-available.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0212-ARM-omap4-Provide-do_wfi-for-Thumb-2.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0213-ARM-omap4-Convert-END-to-ENDPROC-for-correct-linkage.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0214-ARM-omap3-Remove-hand-encoded-SMC-instructions.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0215-ARM-omap3-Thumb-2-compatibility-for-sram34xx.S.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0216-ARM-omap3-Thumb-2-compatibility-for-sleep34xx.S.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0217-OMAP2-smartreflex-remove-SR-debug-directory-in-omap_.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0218-OMAP-clock-fix-compile-warning.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0219-MAINTAINERS-add-entry-for-OMAP-powerdomain-clockdoma.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0220-OMAP3-hwmod-data-Fix-incorrect-SmartReflex-L4-CORE-i.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0221-OMAP3-hwmod-data-Remove-masters-port-links-for-inter.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0222-OMAP2-hwmod-fix-incorrect-computation-of-autoidle_ma.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0223-omap-hwmod-add-syss-reset-done-flags-to-omap2-omap3-.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0224-OMAP2-hwmod-Fix-what-_init_clock-returns.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0225-OMAP2-hwmod-fix-a-documentation-bug-with-HWMOD_NO_OC.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0226-OMAP2-hwmod-use-status-bit-info-for-reset-line.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0227-OMAP2-hwmod-allow-board-files-to-prevent-devices-fro.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0228-OMAP2-hwmod-add-API-to-handle-autoidle-mode.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0229-OMAP2-clockdomain-add-flag-that-will-block-autodeps-.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0230-omap2-3-dmtimer-Enable-autoidle.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0231-omap-Fix-H4-init_irq-to-not-call-h4_init_flash.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0232-OMAP3-PM-Use-ARMv7-supported-instructions-instead-of.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0233-OMAP3-PM-Fix-the-MMU-on-sequence-in-the-asm-code.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0234-OMAP3-PM-Allow-the-cache-clean-when-L1-is-lost.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0235-OMAP3-PM-Remove-un-necessary-cp15-registers-form-low.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0236-OMAP3-PM-Clear-the-SCTLR-C-bit-in-asm-code-to-preven.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0237-OMAP2-voltage-reorganize-split-code-from-data.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0238-Watchdog-omap_wdt-add-fine-grain-runtime-pm.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0239-OMAP3-wdtimer-Fix-CORE-idle-transition.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0240-OMAP3-OPP-Replace-voltage-values-with-Macros.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0241-OMAP4-Enable-800-MHz-and-1-GHz-MPU-OPP.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0242-OMAP4-Update-Voltage-Rail-Values-for-MPU-IVA-and-COR.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0243-OMAP4-Add-IVA-OPP-enteries.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0244-perf-add-OMAP-support-for-the-new-power-events.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0245-omap2-Add-separate-list-for-dynamic-pads-to-mux.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0246-omap2-mux-Remove-the-use-of-IDLE-flag.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0247-omap2-mux-Add-macro-for-configuring-static-with-omap.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0248-omap4-board-4430sdp-Initialise-the-serial-pads.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0249-omap3-board-3430sdp-Initialise-the-serial-pads.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0250-omap4-board-omap4panda-Initialise-the-serial-pads.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0251-omap2-mux-Fix-compile-when-CONFIG_OMAP_MUX-is-not-se.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0252-omap4-mux-Remove-duplicate-mux-modes.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0253-omap-iovmm-disallow-mapping-NULL-address-when-IOVMF_.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0254-omap-iovmm-don-t-check-da-to-set-IOVMF_DA_FIXED-flag.patch"
+patch -s -p1 < "${DIR}/patches/for_next/0001-merge-changes-missed-in-rebase.patch"
+
+}
+
function sakoman {
echo "sakoman's patches"
@@ -56,7 +317,6 @@ patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0011-ARM-OMAP-Make-beagle-u-boot-p
patch -s -p1 < "${DIR}/patches/sakoman/2.6.37/0012-MFD-enable-madc-clock.patch"
patch -s -p1 < "${DIR}/patches/sakoman/2.6.38/0013-MFD-add-twl4030-madc-driver.patch"
-
patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0014-ARM-OMAP-Add-twl4030-madc-support-to-Overo.patch"
patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0015-ARM-OMAP-Add-twl4030-madc-support-to-Beagle.patch"
patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0016-OMAP-DSS2-Add-support-for-Samsung-LTE430WQ-F0C-panel.patch"
@@ -65,7 +325,9 @@ patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0016-OMAP-DSS2-Add-support-for-Sam
#patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0017-OMAP-DSS2-Add-support-for-LG-Philips-LB035Q02-panel.patch"
patch -s -p1 < "${DIR}/patches/sakoman/2.6.38/0017-OMAP-DSS2-Add-support-for-LG-Philips-LB035Q02-panel.patch"
-patch -s -p1 < "${DIR}/patches/sakoman/2.6.38/0018-OMAP-DSS2-Add-DSS2-support-for-Overo.patch"
+#fixme pull in dss2 tree..
+#patch -s -p1 < "${DIR}/patches/sakoman/2.6.38/0018-OMAP-DSS2-Add-DSS2-support-for-Overo.patch"
+
patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0019-OMAP-DSS2-add-bootarg-for-selecting-svideo-or-compos.patch"
patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0020-ARM-OMAP2-mmc-twl4030-move-clock-input-selection-pri.patch"
patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0021-RTC-add-support-for-backup-battery-recharge.patch"
@@ -84,10 +346,6 @@ patch -s -p1 < "${DIR}/patches/sakoman/2.6.38/0030-Revert-Input-ads7846-add-regu
patch -s -p1 < "${DIR}/patches/sakoman/2.6.35/0031-Revert-omap2_mcspi-Flush-posted-writes.patch"
}
-function dss2 {
-echo "dss2 patches"
-}
-
function musb {
echo "musb patches"
patch -s -p1 < "${DIR}/patches/musb/0001-default-to-fifo-mode-5-for-old-musb-beagles.patch"
@@ -136,7 +394,9 @@ patch -s -p1 < "${DIR}/patches/arago-project/0001-omap3-Increase-limit-on-bootar
#2.6.37-git12
#patch -s -p1 < "${DIR}/patches/beagle/0001-omap-beagle-use-GPIO2-on-the-xM-A3-to-turn-DVI-on.patch"
-patch -s -p1 < "${DIR}/patches/beagle/0001-xM-audio-fix-from-Ashok.patch"
+#disabled in for_next merge
+#patch -s -p1 < "${DIR}/patches/beagle/0001-xM-audio-fix-from-Ashok.patch"
+
patch -s -p1 < "${DIR}/patches/beagle/0001-omap-mmc-Adjust-dto-to-eliminate-timeout-errors.patch"
patch -s -p1 < "${DIR}/patches/beagle/0001-beagleboard-hack-in-support-from-xM-rev-C-from-Koen.patch"
}
@@ -212,13 +472,9 @@ echo "omap4 related patches"
#panda display from: http://dev.omapzoom.org/?p=anand/linux-omap-usb.git;a=shortlog;h=refs/heads/display-patches-for-v2.6.38-rc4
patch -s -p1 < "${DIR}/patches/panda/0001-OMAP2-3-DSS2-remove-forced-clk-disable-from-omap_dss.patch"
-patch -s -p1 < "${DIR}/patches/panda/0002-OMAP2420-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch"
-patch -s -p1 < "${DIR}/patches/panda/0003-OMAP2430-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch"
-patch -s -p1 < "${DIR}/patches/panda/0004-OMAP3-hwmod-data-add-DSS-DISPC-RFBI-DSI-VENC.patch"
patch -s -p1 < "${DIR}/patches/panda/0005-OMAP2-3-DSS2-Change-driver-name-to-omap_display.patch"
patch -s -p1 < "${DIR}/patches/panda/0006-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch"
patch -s -p1 < "${DIR}/patches/panda/0007-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch"
-patch -s -p1 < "${DIR}/patches/panda/0008-OMAP2-3-DSS2-board-files-replace-platform_device_reg.patch"
patch -s -p1 < "${DIR}/patches/panda/0009-OMAP2-3-DSS2-Build-omap_device-for-each-DSS-HWIP.patch"
patch -s -p1 < "${DIR}/patches/panda/0010-OMAP2-3-DSS2-DSS-create-platform_driver-move-init-ex.patch"
patch -s -p1 < "${DIR}/patches/panda/0011-OMAP2-3-DSS2-Move-clocks-from-core-driver-to-dss-dri.patch"
@@ -238,7 +494,6 @@ patch -s -p1 < "${DIR}/patches/panda/0020-OMAP2PLUS-DSS2-Generalize-naming-of-PR
patch -s -p1 < "${DIR}/patches/panda/0021-OMAP2PLUS-DSS2-Generalize-external-clock-names-in-st.patch"
patch -s -p1 < "${DIR}/patches/panda/0022-OMAP4-DSS2-clocks-Add-ick-as-dummy-clock.patch"
patch -s -p1 < "${DIR}/patches/panda/0023-OMAP2PLUS-DSS2-Add-OMAP4-Kconfig-support.patch"
-patch -s -p1 < "${DIR}/patches/panda/0024-OMAP4-hwmod-data-add-DSS-DISPC-DSI1-2-RFBI-HDMI-VENC.patch"
patch -s -p1 < "${DIR}/patches/panda/0025-OMAP4-DSS2-Add-hwmod-device-names-for-OMAP4.patch"
patch -s -p1 < "${DIR}/patches/panda/0026-OMAP-DSS2-Common-IRQ-handler-for-all-OMAPs.patch"
patch -s -p1 < "${DIR}/patches/panda/0027-OMAP-DSS2-Add-dss_feature-for-variable-DPLL-fclk.patch"
@@ -315,18 +570,6 @@ patch -s -p1 < "${DIR}/patches/dspbridge/0037-staging-tidspbridge-set12-remove-h
function dvfs {
echo "dvfs"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0001-MAINTAINERS-update-Kevin-s-email-for-OMAP-PM-section.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0002-OMAP3630-PM-don-t-warn-the-user-with-a-trace-in-case.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0003-OMAP3-4-OPP-make-omapx_opp_init-non-static.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0004-OMAP3-beagle-xm-enable-up-to-800MHz-OPP.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0005-OMAP-PM-SmartReflex-fix-potential-NULL-dereference.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0006-OMAP2-remove-unused-UART-base-addresses-from-omap_gl.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0007-OMAP2-3-PM-remove-unnecessary-wakeup-sleep-dependenc.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0008-omap3-pm-Use-exported-set_cr-instead-of-a-custom-one.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0009-omap3-cpuidle-Add-description-field-to-each-C-state.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/for-2.6.39/0010-OMAP3-PM-Set-clear-T2-bit-for-Smartreflex-on-TWL.patch"
-
-
#from:http://gitorious.org/linux-omap-nm-sr/linux-omap-sr/commits/sr-dvfs-1.5
patch -s -p1 < "${DIR}/patches/dvfs/0002-OMAP3-CPUIdle-prevent-CORE-from-going-off-if-doing-s.patch"
patch -s -p1 < "${DIR}/patches/dvfs/0003-OMAP-CPUfreq-ensure-driver-initializes-after-cpufreq.patch"
@@ -336,7 +579,6 @@ patch -s -p1 < "${DIR}/patches/dvfs/0006-OMAP-PM-CPUFREQ-Fix-conditional-compila
patch -s -p1 < "${DIR}/patches/dvfs/0007-cpufreq-fixup-after-new-OPP-layer-merged.patch"
patch -s -p1 < "${DIR}/patches/dvfs/0008-OMAP3-PM-CPUFreq-driver-for-OMAP3.patch"
patch -s -p1 < "${DIR}/patches/dvfs/0009-cpufreq-fixup-after-new-OPP-layer-merged.patch"
-patch -s -p1 < "${DIR}/patches/dvfs/0015-perf-add-OMAP-support-for-the-new-power-events.patch"
patch -s -p1 < "${DIR}/patches/dvfs/0017-OMAP-Introduce-accessory-APIs-for-DVFS.patch"
patch -s -p1 < "${DIR}/patches/dvfs/0018-OMAP-Introduce-device-specific-set-rate-and-get-rate.patch"
patch -s -p1 < "${DIR}/patches/dvfs/0019-OMAP-Implement-Basic-DVFS.patch"
@@ -382,11 +624,11 @@ patch -s -p1 < "${DIR}/patches/dvfs/0001-omap3-Add-basic-support-for-720MHz-part
}
-bugs_trivial
+#bugs_trivial
+for_next
sakoman
beagle
touchbook
-dss2
musb
micrel
zippy
@@ -395,7 +637,7 @@ igepv2
omap4
devkit8000
dspbridge
-dvfs
+#dvfs
echo "patch.sh ran successful"
diff --git a/patches/defconfig b/patches/defconfig
index a8dbb56b4856a06e621aaa54411e26501de89a57..614bee2aca4ee0d1bb447913a2b0fe5416c69e5c 100644
--- a/patches/defconfig
+++ b/patches/defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux/arm 2.6.38-rc8 Kernel Configuration
-# Tue Mar 8 18:40:21 2011
+# Sat Mar 12 18:54:49 2011
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -299,8 +299,6 @@ CONFIG_ARCH_OMAP2PLUS=y
#
CONFIG_OMAP_SMARTREFLEX=y
CONFIG_OMAP_SMARTREFLEX_CLASS3=y
-CONFIG_OMAP_SMARTREFLEX_CLASS1P5=y
-CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY=86400000
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_OMAP_MUX=y
# CONFIG_OMAP_MUX_DEBUG is not set
@@ -322,7 +320,8 @@ CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
# CONFIG_ARCH_OMAP2 is not set
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y
-CONFIG_ARCH_OMAP3430=y
+CONFIG_SOC_OMAP3430=y
+CONFIG_SOC_OMAPTI816X=y
CONFIG_OMAP_PACKAGE_CBB=y
CONFIG_OMAP_PACKAGE_CUS=y
CONFIG_OMAP_PACKAGE_CBP=y
@@ -354,6 +353,7 @@ CONFIG_MACH_IGEP0020=y
CONFIG_MACH_IGEP0030=y
CONFIG_MACH_SBC3530=y
CONFIG_MACH_OMAP_3630SDP=y
+CONFIG_MACH_TI8168EVM=y
CONFIG_MACH_OMAP_4430SDP=y
CONFIG_MACH_OMAP4_PANDA=y
CONFIG_OMAP3_EMU=y
@@ -1257,8 +1257,6 @@ CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_GPIO is not set
CONFIG_MTD_NAND_OMAP2=y
-CONFIG_MTD_NAND_OMAP_PREFETCH=y
-CONFIG_MTD_NAND_OMAP_PREFETCH_DMA=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_DISKONCHIP=m
# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
@@ -3237,6 +3235,7 @@ CONFIG_MACH_OMAP3_WESTBRIDGE_AST_PNAND_HAL=y
# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
CONFIG_OMAP3_SGX=y
CONFIG_CLKDEV_LOOKUP=y
+# CONFIG_HWSPINLOCK is not set
#
# File systems
diff --git a/patches/dvfs/0001-omap3-Add-basic-support-for-720MHz-part.patch b/patches/dvfs/0001-omap3-Add-basic-support-for-720MHz-part.patch
index b192ee29914e5353da97a0257fe1982d09383275..1de3646e1316e84c16441608f2df503f81e4252c 100644
--- a/patches/dvfs/0001-omap3-Add-basic-support-for-720MHz-part.patch
+++ b/patches/dvfs/0001-omap3-Add-basic-support-for-720MHz-part.patch
@@ -38,18 +38,18 @@ Signed-off-by: Sanjeev Premi <premi@ti.com>
Reviewed-by: G, Manjunath Kondaiah <manjugk@ti.com>
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/control.h | 6 +++
- arch/arm/mach-omap2/id.c | 5 ++
- arch/arm/mach-omap2/opp3xxx_data.c | 63 ++++++++++++++++++++++++++++-
- arch/arm/plat-omap/include/plat/cpu.h | 2 +
- arch/arm/plat-omap/include/plat/voltage.h | 1 +
+ arch/arm/mach-omap2/control.h | 6 +++
+ arch/arm/mach-omap2/id.c | 5 +++
+ arch/arm/mach-omap2/opp3xxx_data.c | 63 ++++++++++++++++++++++++++++++++-
+ arch/arm/mach-omap2/voltage.h | 1 +
+ arch/arm/plat-omap/include/plat/cpu.h | 2 +
5 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
-index f0629ae..c338466 100644
+index c2804c1..b52bf34 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
-@@ -365,6 +365,12 @@
+@@ -371,6 +371,12 @@
#define FEAT_NEON 0
#define FEAT_NEON_NONE 1
@@ -63,12 +63,12 @@ index f0629ae..c338466 100644
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_OMAP2PLUS
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
-index 5f9086c..8c4500f 100644
+index 3168b17..b361209 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
-@@ -191,6 +191,10 @@ static void __init omap3_check_features(void)
- if (!cpu_is_omap3505() && !cpu_is_omap3517())
- omap3_features |= OMAP3_HAS_IO_WAKEUP;
+@@ -193,6 +193,10 @@ static void __init omap3_check_features(void)
+
+ omap3_features |= OMAP3_HAS_SDRC;
+ status = (OMAP3_SKUID_MASK & read_tap_reg(OMAP3_PRODID));
+ if (status & OMAP3_SKUID_720MHZ)
@@ -77,7 +77,7 @@ index 5f9086c..8c4500f 100644
/*
* TODO: Get additional info (where applicable)
* e.g. Size of L2 cache.
-@@ -445,6 +449,7 @@ static void __init omap3_cpuinfo(void)
+@@ -477,6 +481,7 @@ static void __init omap3_cpuinfo(void)
OMAP3_SHOW_FEATURE(neon);
OMAP3_SHOW_FEATURE(isp);
OMAP3_SHOW_FEATURE(192mhz_clk);
@@ -97,7 +97,7 @@ index e3ea9ba..4a70607 100644
#include <plat/cpu.h>
+#include <plat/omap_device.h>
- #include <plat/voltage.h>
+ #include "voltage.h"
#include "omap_opp_data.h"
@@ -35,6 +37,8 @@ static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
@@ -192,37 +192,37 @@ index e3ea9ba..4a70607 100644
return r;
}
device_initcall(omap3_opp_init);
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index c8f69e4..fe22f32 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -33,6 +33,7 @@
+ #define OMAP3430_VDD_MPU_OPP3_UV 1200000
+ #define OMAP3430_VDD_MPU_OPP4_UV 1270000
+ #define OMAP3430_VDD_MPU_OPP5_UV 1350000
++#define OMAP3430_VDD_MPU_OPP6_UV 1350000
+
+ #define OMAP3430_VDD_CORE_OPP1_UV 975000
+ #define OMAP3430_VDD_CORE_OPP2_UV 1050000
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
-index 7cfaad1..f98151c 100644
+index 5c49dd1..ab98f38 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
-@@ -511,6 +511,7 @@ extern u32 omap3_features;
- #define OMAP3_HAS_ISP BIT(4)
+@@ -534,6 +534,7 @@ extern u32 omap3_features;
#define OMAP3_HAS_192MHZ_CLK BIT(5)
#define OMAP3_HAS_IO_WAKEUP BIT(6)
-+#define OMAP3_HAS_720MHZ BIT(7)
+ #define OMAP3_HAS_SDRC BIT(7)
++#define OMAP3_HAS_720MHZ BIT(8)
#define OMAP3_HAS_FEATURE(feat,flag) \
static inline unsigned int omap3_has_ ##feat(void) \
-@@ -525,5 +526,6 @@ OMAP3_HAS_FEATURE(neon, NEON)
- OMAP3_HAS_FEATURE(isp, ISP)
+@@ -549,5 +550,6 @@ OMAP3_HAS_FEATURE(isp, ISP)
OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+ OMAP3_HAS_FEATURE(sdrc, SDRC)
+OMAP3_HAS_FEATURE(720mhz, 720MHZ)
#endif
-diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
-index 80544a7..2711ba1 100644
---- a/arch/arm/plat-omap/include/plat/voltage.h
-+++ b/arch/arm/plat-omap/include/plat/voltage.h
-@@ -33,6 +33,7 @@
- #define OMAP3430_VDD_MPU_OPP3_UV 1200000
- #define OMAP3430_VDD_MPU_OPP4_UV 1270000
- #define OMAP3430_VDD_MPU_OPP5_UV 1350000
-+#define OMAP3430_VDD_MPU_OPP6_UV 1350000
-
- #define OMAP3430_VDD_CORE_OPP1_UV 975000
- #define OMAP3430_VDD_CORE_OPP2_UV 1050000
--
1.7.1
diff --git a/patches/dvfs/0005-OMAP3-PM-CPUFreq-driver-for-OMAP3.patch b/patches/dvfs/0005-OMAP3-PM-CPUFreq-driver-for-OMAP3.patch
index 5bc970b79a0b240d475514f90d54cbc8a5ca019b..1580c34fe9db6c93933f9d5f2fe374c2c71d41eb 100644
--- a/patches/dvfs/0005-OMAP3-PM-CPUFreq-driver-for-OMAP3.patch
+++ b/patches/dvfs/0005-OMAP3-PM-CPUFreq-driver-for-OMAP3.patch
@@ -114,6 +114,7 @@ Cc: Thara Gopinath <thara@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm/mach-omap2/clock.h | 14 +++++++++++++-
arch/arm/mach-omap2/clock34xx.c | 2 ++
@@ -121,10 +122,10 @@ Signed-off-by: Nishanth Menon <nm@ti.com>
3 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
-index 896584e..29b5cf0 100644
+index 70f8b07..569693d 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
-@@ -137,7 +137,9 @@ extern const struct clksel_rate gpt_32k_rates[];
+@@ -144,7 +144,9 @@ extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
@@ -135,7 +136,7 @@ index 896584e..29b5cf0 100644
extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
#else
-@@ -145,6 +147,16 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+@@ -152,6 +154,16 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
#define omap2_clk_exit_cpufreq_table 0
#endif
@@ -149,11 +150,11 @@ index 896584e..29b5cf0 100644
+
+#endif /* CONFIG_CPU_FREQ */
+
- extern const struct clkops clkops_omap3_noncore_dpll_ops;
-
- #endif
+ extern const struct clkops clkops_omap2_iclk_dflt_wait;
+ extern const struct clkops clkops_omap2_iclk_dflt;
+ extern const struct clkops clkops_omap2_iclk_idle_only;
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
-index 287abc4..85d3877 100644
+index 1fc96b9..119e135 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -20,6 +20,8 @@
@@ -166,7 +167,7 @@ index 287abc4..85d3877 100644
#include <plat/clock.h>
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
-index bfa063b..7753e86 100644
+index 1b36664..f0f9430 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -8,6 +8,10 @@
@@ -242,7 +243,7 @@ index bfa063b..7753e86 100644
return ret;
}
-@@ -114,7 +135,14 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy)
+@@ -114,7 +135,14 @@ static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
policy->cur = policy->min = policy->max = omap_getspeed(0);
diff --git a/patches/dvfs/0017-OMAP-Introduce-accessory-APIs-for-DVFS.patch b/patches/dvfs/0017-OMAP-Introduce-accessory-APIs-for-DVFS.patch
index 8494334ca211965ebd0555eb517d1625a6d3c965..e52147db28c0c7ddd75a5101992fbe1338932730 100644
--- a/patches/dvfs/0017-OMAP-Introduce-accessory-APIs-for-DVFS.patch
+++ b/patches/dvfs/0017-OMAP-Introduce-accessory-APIs-for-DVFS.patch
@@ -37,6 +37,7 @@ rework.
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Cc: Thara Gopinath <thara@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm/mach-omap2/Makefile | 2 +-
arch/arm/mach-omap2/dvfs.c | 456 ++++++++++++++++++++++++++++++++
@@ -47,21 +48,21 @@ Cc: Thara Gopinath <thara@ti.com>
create mode 100644 arch/arm/plat-omap/include/plat/dvfs.h
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
-index 1c0c2b0..625087e 100644
+index 989ae13..ac91025 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -61,7 +61,7 @@ ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
- obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o voltage.o
- obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \
+ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o
+ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \
- cpuidle34xx.o pm_bus.o
+ cpuidle34xx.o pm_bus.o dvfs.o
- obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o
+ obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
diff --git a/arch/arm/mach-omap2/dvfs.c b/arch/arm/mach-omap2/dvfs.c
new file mode 100644
-index 0000000..8832e4a
+index 0000000..9fc4041
--- /dev/null
+++ b/arch/arm/mach-omap2/dvfs.c
@@ -0,0 +1,456 @@
@@ -84,7 +85,7 @@ index 0000000..8832e4a
+#include <linux/slab.h>
+#include <linux/opp.h>
+#include <plat/common.h>
-+#include <plat/voltage.h>
++#include "voltage.h"
+#include <plat/omap_device.h>
+
+/**
@@ -523,7 +524,7 @@ index 0000000..8832e4a
+core_initcall(omap_dvfs_init);
diff --git a/arch/arm/plat-omap/include/plat/dvfs.h b/arch/arm/plat-omap/include/plat/dvfs.h
new file mode 100644
-index 0000000..1302990
+index 0000000..cb810f2
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dvfs.h
@@ -0,0 +1,27 @@
@@ -542,7 +543,7 @@ index 0000000..1302990
+
+#ifndef __ARCH_ARM_MACH_OMAP2_DVFS_H
+#define __ARCH_ARM_MACH_OMAP2_DVFS_H
-+#include <plat/voltage.h>
++#include "voltage.h"
+
+#ifdef CONFIG_PM
+int omap_dvfs_register_device(struct voltagedomain *voltdm, struct device *dev);
@@ -555,21 +556,21 @@ index 0000000..1302990
+#endif
+#endif
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
-index 57adb27..a84e849 100644
+index 9bbda9a..50131ac 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
-@@ -86,6 +86,7 @@
+@@ -87,6 +87,7 @@
#include <plat/omap_device.h>
#include <plat/omap_hwmod.h>
+#include <plat/dvfs.h>
+ #include <plat/clock.h>
/* These parameters are passed to _omap_device_{de,}activate() */
- #define USE_WAKEUP_LAT 0
-@@ -481,6 +482,14 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+@@ -497,6 +498,14 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
for (i = 0; i < oh_cnt; i++) {
hwmods[i]->od = od;
- _add_optional_clock_alias(od, hwmods[i]);
+ _add_optional_clock_clkdev(od, hwmods[i]);
+ if (!is_early_device && hwmods[i]->vdd_name) {
+ struct omap_hwmod *oh = hwmods[i];
+ struct voltagedomain *voltdm;
diff --git a/patches/dvfs/0020-OMAP-Introduce-dependent-voltage-domain-support.patch b/patches/dvfs/0020-OMAP-Introduce-dependent-voltage-domain-support.patch
index 2a798c4a5864a3d3ce7801f590f479d2d8d0e488..280158a07f9b9082eec9916ff77bcdc265a38651 100644
--- a/patches/dvfs/0020-OMAP-Introduce-dependent-voltage-domain-support.patch
+++ b/patches/dvfs/0020-OMAP-Introduce-dependent-voltage-domain-support.patch
@@ -20,10 +20,11 @@ Based on original patch from Thara.
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Cc: Thara Gopinath <thara@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/dvfs.c | 87 +++++++++++++++++
- arch/arm/mach-omap2/voltage.c | 117 -----------------------
- arch/arm/plat-omap/include/plat/voltage.h | 148 +++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/dvfs.c | 87 ++++++++++++++++++++++++
+ arch/arm/mach-omap2/voltage.c | 117 --------------------------------
+ arch/arm/mach-omap2/voltage.h | 148 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 235 insertions(+), 117 deletions(-)
diff --git a/arch/arm/mach-omap2/dvfs.c b/arch/arm/mach-omap2/dvfs.c
@@ -160,10 +161,10 @@ index cefc2be..c9d3894 100644
}
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
-index 12be525..cd61e6d 100644
+index 3c9bcdc..6488573 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
-@@ -39,123 +39,6 @@
+@@ -40,123 +40,6 @@
#define VP_TRANXDONE_TIMEOUT 300
#define VOLTAGE_DIR_SIZE 16
@@ -287,10 +288,10 @@ index 12be525..cd61e6d 100644
static struct omap_vdd_info *vdd_info;
/*
* Number of scalable voltage domains.
-diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 5bd204e..e0b7f22 100644
---- a/arch/arm/plat-omap/include/plat/voltage.h
-+++ b/arch/arm/plat-omap/include/plat/voltage.h
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
@@ -113,6 +113,154 @@ struct omap_volt_pmic_info {
u8 (*uv_to_vsel) (unsigned long uV);
};
diff --git a/patches/dvfs/0021-OMAP-Introduce-device-scale-implementation.patch b/patches/dvfs/0021-OMAP-Introduce-device-scale-implementation.patch
index f6a04bdd8d37eeee91894bf6aa0bf1c50b62156c..38240460e5a13f70c307240c045300a7f4118a81 100644
--- a/patches/dvfs/0021-OMAP-Introduce-device-scale-implementation.patch
+++ b/patches/dvfs/0021-OMAP-Introduce-device-scale-implementation.patch
@@ -21,9 +21,9 @@ index c9d3894..05a9ce3 100644
+++ b/arch/arm/mach-omap2/dvfs.c
@@ -19,6 +19,7 @@
#include <plat/common.h>
- #include <plat/voltage.h>
+ #include "voltage.h"
#include <plat/omap_device.h>
-+#include <plat/smartreflex.h>
++#include "smartreflex.h"
/**
* struct omap_dev_user_list - Structure maitain userlist per device
diff --git a/patches/dvfs/0025-OMAP3-Introduce-voltage-domain-info-in-the-hwmod-str.patch b/patches/dvfs/0025-OMAP3-Introduce-voltage-domain-info-in-the-hwmod-str.patch
index 7d9db8f9b78805583c14cfea7f0d0d02c122e24e..730ea335103ce53e116c1d9ec5256724fc1aaf10 100644
--- a/patches/dvfs/0025-OMAP3-Introduce-voltage-domain-info-in-the-hwmod-str.patch
+++ b/patches/dvfs/0025-OMAP3-Introduce-voltage-domain-info-in-the-hwmod-str.patch
@@ -8,23 +8,24 @@ device hwmod structures so as to enable OMAP3 DVFS
support.
Signed-off-by: Thara Gopinath <thara@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
-index 8d81813..c57f34d 100644
+index d949be4..8c4f76d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
-@@ -94,6 +94,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
+@@ -150,6 +150,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
static struct omap_hwmod omap3xxx_l3_main_hwmod = {
.name = "l3_main",
.class = &l3_hwmod_class,
+ .vdd_name = "core",
+ .mpu_irqs = omap3xxx_l3_main_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
.masters = omap3xxx_l3_main_masters,
- .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
- .slaves = omap3xxx_l3_main_slaves,
-@@ -384,6 +385,7 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
+@@ -570,6 +571,7 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
.name = "mpu",
.class = &mpu_hwmod_class,
.main_clk = "arm_fck",
@@ -32,7 +33,7 @@ index 8d81813..c57f34d 100644
.masters = omap3xxx_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
-@@ -412,6 +414,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
+@@ -598,6 +600,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
static struct omap_hwmod omap3xxx_iva_hwmod = {
.name = "iva",
.class = &iva_hwmod_class,
diff --git a/patches/dvfs/0027-OMAP2PLUS-Replace-voltage-values-with-Macros.patch b/patches/dvfs/0027-OMAP2PLUS-Replace-voltage-values-with-Macros.patch
index 8553de237fd52817bd423dc87eec453fdf376457..abc2ba2b1e01a1b2037ad268f4b862e96c2f5557 100644
--- a/patches/dvfs/0027-OMAP2PLUS-Replace-voltage-values-with-Macros.patch
+++ b/patches/dvfs/0027-OMAP2PLUS-Replace-voltage-values-with-Macros.patch
@@ -23,7 +23,7 @@ index fd3a1af..e3ea9ba 100644
#include <linux/module.h>
#include <plat/cpu.h>
-+#include <plat/voltage.h>
++#include "voltage.h"
#include "omap_opp_data.h"
#include "pm.h"
@@ -121,7 +121,7 @@ index f0e9939..705fe9a 100644
#include <linux/module.h>
#include <plat/cpu.h>
-+#include <plat/voltage.h>
++#include "voltage.h"
#include "omap_opp_data.h"
#include "pm.h"
diff --git a/patches/dvfs/0037-omap3-voltage-use-volt_data-pointer-instead-values.patch b/patches/dvfs/0037-omap3-voltage-use-volt_data-pointer-instead-values.patch
index a97c3c99ce3efc938e4f29007a83329009467770..32def3d17e62d5b651cd45da7c57a063dc0123e5 100644
--- a/patches/dvfs/0037-omap3-voltage-use-volt_data-pointer-instead-values.patch
+++ b/patches/dvfs/0037-omap3-voltage-use-volt_data-pointer-instead-values.patch
@@ -8,12 +8,13 @@ classes being active. Depending on the class used, the actual voltage
selected might be a variant.
Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/dvfs.c | 9 +++-
- arch/arm/mach-omap2/pm.c | 3 +-
- arch/arm/mach-omap2/smartreflex-class3.c | 3 +-
- arch/arm/mach-omap2/voltage.c | 68 +++++++++++++++-------------
- arch/arm/plat-omap/include/plat/voltage.h | 17 ++++++--
+ arch/arm/mach-omap2/dvfs.c | 9 +++-
+ arch/arm/mach-omap2/pm.c | 3 +-
+ arch/arm/mach-omap2/smartreflex-class3.c | 3 +-
+ arch/arm/mach-omap2/voltage.c | 68 ++++++++++++++++--------------
+ arch/arm/mach-omap2/voltage.h | 17 ++++++--
5 files changed, 59 insertions(+), 41 deletions(-)
diff --git a/arch/arm/mach-omap2/dvfs.c b/arch/arm/mach-omap2/dvfs.c
@@ -51,7 +52,7 @@ index 526e0af..ac32593 100644
/* Enable Smartreflex module */
if (is_sr_disabled)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
-index 1b94ad4..bd9454b 100644
+index ea3ebb8..9a64afa 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -280,7 +280,8 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
@@ -65,7 +66,7 @@ index 1b94ad4..bd9454b 100644
exit:
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
-index 60e7055..2195668 100644
+index f438cf4..2ee48af 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -15,7 +15,8 @@
@@ -79,10 +80,10 @@ index 60e7055..2195668 100644
if (!volt) {
pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
-index 1db3349..1543b10 100644
+index 2794433..ada1628 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
-@@ -277,13 +277,15 @@ static int vp_volt_debug_get(void *data, u64 *val)
+@@ -278,13 +278,15 @@ static int vp_volt_debug_get(void *data, u64 *val)
static int nom_volt_debug_get(void *data, u64 *val)
{
struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
@@ -99,7 +100,7 @@ index 1db3349..1543b10 100644
return 0;
}
-@@ -298,7 +300,8 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
+@@ -299,7 +301,8 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
unsigned long uvdc;
char vsel;
@@ -109,7 +110,7 @@ index 1db3349..1543b10 100644
if (!uvdc) {
pr_warning("%s: unable to find current voltage for vdd_%s\n",
__func__, vdd->voltdm.name);
-@@ -421,12 +424,18 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
+@@ -422,12 +425,18 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
/* Voltage scale and accessory APIs */
static int _pre_volt_scale(struct omap_vdd_info *vdd,
@@ -130,7 +131,7 @@ index 1db3349..1543b10 100644
/* Check if suffiecient pmic info is available for this vdd */
if (!vdd->pmic_info) {
pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
-@@ -450,12 +459,8 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
+@@ -451,12 +460,8 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
vp_mod = vdd->vp_reg.prm_mod;
vc_mod = vdd->vc_reg.prm_mod;
@@ -145,7 +146,7 @@ index 1db3349..1543b10 100644
*current_vsel = vdd->read_reg(vp_mod, vdd->vp_offs.voltage);
/* Setting the ON voltage to the new target voltage */
-@@ -465,22 +470,21 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
+@@ -466,22 +471,21 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
vdd->write_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg);
/* Setting vp errorgain based on the voltage */
@@ -178,7 +179,7 @@ index 1db3349..1543b10 100644
{
u32 smps_steps = 0, smps_delay = 0;
-@@ -495,7 +499,7 @@ static void _post_volt_scale(struct omap_vdd_info *vdd,
+@@ -496,7 +500,7 @@ static void _post_volt_scale(struct omap_vdd_info *vdd,
/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
@@ -187,7 +188,7 @@ index 1db3349..1543b10 100644
{
u32 loop_cnt = 0, retries_cnt = 0;
u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
-@@ -548,7 +552,7 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+@@ -549,7 +553,7 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
/* VP force update method of voltage scaling */
static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
@@ -196,7 +197,7 @@ index 1db3349..1543b10 100644
{
u32 vpconfig;
u16 mod, ocp_mod;
-@@ -1039,16 +1043,15 @@ static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
+@@ -1040,16 +1044,15 @@ static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
* omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage
* @voltdm: pointer to the VDD for which current voltage info is needed
*
@@ -216,7 +217,7 @@ index 1db3349..1543b10 100644
}
vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
-@@ -1190,18 +1193,19 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+@@ -1191,18 +1194,19 @@ void omap_vp_disable(struct voltagedomain *voltdm)
* omap_voltage_scale_vdd() - API to scale voltage of a particular
* voltage domain.
* @voltdm: pointer to the VDD which is to be scaled.
@@ -240,7 +241,7 @@ index 1db3349..1543b10 100644
return -EINVAL;
}
-@@ -1227,7 +1231,7 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+@@ -1228,7 +1232,7 @@ int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
*/
void omap_voltage_reset(struct voltagedomain *voltdm)
{
@@ -249,10 +250,10 @@ index 1db3349..1543b10 100644
if (!voltdm || IS_ERR(voltdm)) {
pr_warning("%s: VDD specified does not exist!\n", __func__);
-diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index e0b7f22..80544a7 100644
---- a/arch/arm/plat-omap/include/plat/voltage.h
-+++ b/arch/arm/plat-omap/include/plat/voltage.h
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
@@ -251,27 +251,27 @@ struct omap_vdd_info {
struct omap_vdd_dep_info *dep_vdd_info;
int nr_dep_vdd;
diff --git a/patches/dvfs/0040-omap3-sr-introduce-class-init-deinit-and-priv-data.patch b/patches/dvfs/0040-omap3-sr-introduce-class-init-deinit-and-priv-data.patch
index 810d79ae6b4b2e8bdd1f0077689f026b48508513..9aed4b9e84cb88de55957e3426e781d6bd28183a 100644
--- a/patches/dvfs/0040-omap3-sr-introduce-class-init-deinit-and-priv-data.patch
+++ b/patches/dvfs/0040-omap3-sr-introduce-class-init-deinit-and-priv-data.patch
@@ -9,13 +9,14 @@ reflex operation. They also may need private data to be used
for operations of thier own, provide the same.
Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/smartreflex.c | 14 ++++++++++++++
- arch/arm/plat-omap/include/plat/smartreflex.h | 7 +++++++
+ arch/arm/mach-omap2/smartreflex.c | 14 ++++++++++++++
+ arch/arm/mach-omap2/smartreflex.h | 7 +++++++
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index 6f0c7d0..fb675c0 100644
+index 7096300..25c0cdd 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -220,6 +220,13 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
@@ -46,11 +47,11 @@ index 6f0c7d0..fb675c0 100644
sr->autocomp_active = false;
}
}
-diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
-index 6568c88..8b6ecd9 100644
---- a/arch/arm/plat-omap/include/plat/smartreflex.h
-+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
-@@ -167,6 +167,8 @@ struct omap_sr_pmic_data {
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 5f35b9e..1679cbc 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -168,6 +168,8 @@ struct omap_sr_pmic_data {
*
* @enable: API to enable a particular class smaartreflex.
* @disable: API to disable a particular class smartreflex.
@@ -59,7 +60,7 @@ index 6568c88..8b6ecd9 100644
* @configure: API to configure a particular class smartreflex.
* @notify: API to notify the class driver about an event in SR.
* Not needed for class3.
-@@ -174,14 +176,19 @@ struct omap_sr_pmic_data {
+@@ -175,14 +177,19 @@ struct omap_sr_pmic_data {
* @class_type: specify which smartreflex class.
* Can be used by the SR driver to take any class
* based decisions.
diff --git a/patches/dvfs/0046-omap3-sr-introduce-notifiers-flags.patch b/patches/dvfs/0046-omap3-sr-introduce-notifiers-flags.patch
index 3eb83179747b9569a29e67b504f4b9e911950905..b3867522d32e295fd724edb5a4b36e44466f0fef 100644
--- a/patches/dvfs/0046-omap3-sr-introduce-notifiers-flags.patch
+++ b/patches/dvfs/0046-omap3-sr-introduce-notifiers-flags.patch
@@ -12,13 +12,14 @@ As part of this change, we will now call the notifier iff we get
a match with the notifier flags that the class driver requested.
Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/smartreflex.c | 73 ++++++++++++++++++++++++-
- arch/arm/plat-omap/include/plat/smartreflex.h | 6 ++
+ arch/arm/mach-omap2/smartreflex.c | 73 +++++++++++++++++++++++++++++++++++--
+ arch/arm/mach-omap2/smartreflex.h | 6 +++
2 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index 210293a..37de7e8 100644
+index bf2d5bf..c38c0cc 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -123,27 +123,94 @@ static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
@@ -119,11 +120,11 @@ index 210293a..37de7e8 100644
return IRQ_HANDLED;
}
-diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
-index 8b6ecd9..ff07d1e 100644
---- a/arch/arm/plat-omap/include/plat/smartreflex.h
-+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
-@@ -141,6 +141,12 @@
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 1679cbc..0e6dedb 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -142,6 +142,12 @@
#define OMAP3430_SR_ERRWEIGHT 0x04
#define OMAP3430_SR_ERRMAXLIMIT 0x02
diff --git a/patches/dvfs/0047-omap3-sr-introduce-notifier_control.patch b/patches/dvfs/0047-omap3-sr-introduce-notifier_control.patch
index 66805be4b33a1fd95517f953e5edf4df41e70722..62eff6be3b37536fbec354782c95829f0f440828 100644
--- a/patches/dvfs/0047-omap3-sr-introduce-notifier_control.patch
+++ b/patches/dvfs/0047-omap3-sr-introduce-notifier_control.patch
@@ -8,8 +8,8 @@ should be triggered and when not. Introduce an api for the same.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
- arch/arm/mach-omap2/smartreflex.c | 57 +++++++++++++++++++++++++
- arch/arm/plat-omap/include/plat/smartreflex.h | 8 ++++
+ arch/arm/mach-omap2/smartreflex.c | 57 +++++++++++++++++++++++++
+ arch/arm/mach-omap2/smartreflex.h | 8 ++++
2 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
@@ -80,10 +80,10 @@ index 37de7e8..8b3c266 100644
* sr_register_class() - API to register a smartreflex class parameters.
* @class_data: The structure containing various sr class specific data.
*
-diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index ff07d1e..d420f44 100644
---- a/arch/arm/plat-omap/include/plat/smartreflex.h
-+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
@@ -242,6 +242,7 @@ void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
/* Smartreflex driver hooks to be called from Smartreflex class driver */
int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
diff --git a/patches/dvfs/0050-omap3-sr-make-enable-patch-use-volt_data-pointer.patch b/patches/dvfs/0050-omap3-sr-make-enable-patch-use-volt_data-pointer.patch
index a93c43c8228e42e601b380d427d52cab87b157b6..e6e50341ae66ac1d0dbd6da65b042fa9a2944ffe 100644
--- a/patches/dvfs/0050-omap3-sr-make-enable-patch-use-volt_data-pointer.patch
+++ b/patches/dvfs/0050-omap3-sr-make-enable-patch-use-volt_data-pointer.patch
@@ -12,7 +12,7 @@ Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm/mach-omap2/dvfs.c | 6 ++++--
arch/arm/mach-omap2/smartreflex-class3.c | 13 +++----------
arch/arm/mach-omap2/smartreflex.c | 25 ++++++++++++-------------
- arch/arm/plat-omap/include/plat/smartreflex.h | 8 +++++---
+ arch/arm/mach-omap2/smartreflex.h | 8 +++++---
4 files changed, 24 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-omap2/dvfs.c b/arch/arm/mach-omap2/dvfs.c
@@ -45,7 +45,7 @@ index 2195668..7ac88da 100644
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -13,19 +13,12 @@
- #include <plat/smartreflex.h>
+ #include "smartreflex.h"
-static int sr_class3_enable(struct voltagedomain *voltdm)
+static int sr_class3_enable(struct voltagedomain *voltdm,
@@ -151,10 +151,10 @@ index d12b9d1..ddd78ce 100644
}
/**
-diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index d420f44..07f35b2 100644
---- a/arch/arm/plat-omap/include/plat/smartreflex.h
-+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
@@ -185,7 +185,8 @@ struct omap_sr_pmic_data {
* @class_priv_data: Class specific private data (optional)
*/
diff --git a/patches/dvfs/0051-omap3-voltage-add-transdone-apis.patch b/patches/dvfs/0051-omap3-voltage-add-transdone-apis.patch
index 9a885103581f68d053901ad986e1f3836bb5ac96..4363fac9e22fe17db2b2c64faf281f078bdac82d 100644
--- a/patches/dvfs/0051-omap3-voltage-add-transdone-apis.patch
+++ b/patches/dvfs/0051-omap3-voltage-add-transdone-apis.patch
@@ -12,16 +12,17 @@ to know fine grained if the voltage is actually send to PMIC
needs to depend on this status.
Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/voltage.c | 64 ++++++++++++++++++++++-------
- arch/arm/plat-omap/include/plat/voltage.h | 2 +
+ arch/arm/mach-omap2/voltage.c | 64 +++++++++++++++++++++++++++++++---------
+ arch/arm/mach-omap2/voltage.h | 2 +
2 files changed, 51 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
-index 639f645..15eed85 100644
+index b291227..02d7072 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
-@@ -555,8 +555,8 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+@@ -556,8 +556,8 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
struct omap_volt_data *target_volt)
{
u32 vpconfig;
@@ -32,7 +33,7 @@ index 639f645..15eed85 100644
int ret, timeout = 0;
ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel);
-@@ -564,18 +564,13 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+@@ -565,18 +565,13 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
return ret;
mod = vdd->vp_reg.prm_mod;
@@ -53,7 +54,7 @@ index 639f645..15eed85 100644
break;
udelay(1);
}
-@@ -607,7 +602,7 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+@@ -608,7 +603,7 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
* Depends on SMPSWAITTIMEMIN/MAX and voltage change
*/
timeout = 0;
@@ -62,7 +63,7 @@ index 639f645..15eed85 100644
vdd->vp_reg.tranxdone_status),
VP_TRANXDONE_TIMEOUT, timeout);
if (timeout >= VP_TRANXDONE_TIMEOUT)
-@@ -623,11 +618,9 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+@@ -624,11 +619,9 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
*/
timeout = 0;
while (timeout++ < VP_TRANXDONE_TIMEOUT) {
@@ -77,7 +78,7 @@ index 639f645..15eed85 100644
udelay(1);
}
-@@ -1190,6 +1183,47 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+@@ -1191,6 +1184,47 @@ void omap_vp_disable(struct voltagedomain *voltdm)
}
/**
@@ -125,10 +126,10 @@ index 639f645..15eed85 100644
* omap_voltage_scale_vdd() - API to scale voltage of a particular
* voltage domain.
* @voltdm: pointer to the VDD which is to be scaled.
-diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 80544a7..6f310f2 100644
---- a/arch/arm/plat-omap/include/plat/voltage.h
-+++ b/arch/arm/plat-omap/include/plat/voltage.h
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
@@ -272,6 +272,8 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
unsigned long volt);
diff --git a/patches/dvfs/0052-omap3-dvfs-introduce-api-to-protect-sr-ops.patch b/patches/dvfs/0052-omap3-dvfs-introduce-api-to-protect-sr-ops.patch
index 361b4ec06383e142b652dd3fb21b4ed067bba505..f56c916aeecdd2a968425d8e1906985be609f652 100644
--- a/patches/dvfs/0052-omap3-dvfs-introduce-api-to-protect-sr-ops.patch
+++ b/patches/dvfs/0052-omap3-dvfs-introduce-api-to-protect-sr-ops.patch
@@ -10,6 +10,7 @@ dvfs operations untill we are done with enabling/disabling
SR
Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm/mach-omap2/dvfs.c | 50 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/smartreflex.c | 12 +++++++
@@ -78,18 +79,18 @@ index a00ab95..302d654 100644
*
* Initalizes omap dvfs layer. It basically allocates memory for
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index ddd78ce..6ffc1a0 100644
+index 99cbfba..87fff94 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
-@@ -27,6 +27,7 @@
+@@ -26,6 +26,7 @@
+ #include <linux/pm_runtime.h>
#include <plat/common.h>
- #include <plat/smartreflex.h>
+#include <plat/dvfs.h>
#include "pm.h"
-
-@@ -940,6 +941,7 @@ static int omap_sr_autocomp_show(void *data, u64 *val)
+ #include "smartreflex.h"
+@@ -941,6 +942,7 @@ static int omap_sr_autocomp_show(void *data, u64 *val)
static int omap_sr_autocomp_store(void *data, u64 val)
{
struct omap_sr *sr_info = (struct omap_sr *) data;
@@ -97,7 +98,7 @@ index ddd78ce..6ffc1a0 100644
if (!sr_info) {
pr_warning("%s: omap_sr struct not found\n", __func__);
-@@ -954,10 +956,20 @@ static int omap_sr_autocomp_store(void *data, u64 val)
+@@ -955,10 +957,20 @@ static int omap_sr_autocomp_store(void *data, u64 val)
/* control enable/disable only if there is a delta in value */
if (sr_info->autocomp_active ^ val) {
diff --git a/patches/dvfs/0053-omap3630-sr-add-support-for-class-1.5.patch b/patches/dvfs/0053-omap3630-sr-add-support-for-class-1.5.patch
index 75f37b8cf2c08869e4bff89467de7a10dcd83a87..0900d551ba394dd57412d6cf8ce11f41f2167248 100644
--- a/patches/dvfs/0053-omap3630-sr-add-support-for-class-1.5.patch
+++ b/patches/dvfs/0053-omap3630-sr-add-support-for-class-1.5.patch
@@ -102,21 +102,22 @@ Cc: Peter 'p2' De Schrijver <Peter.De-Schrijver@nokia.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/Makefile | 1 +
- arch/arm/mach-omap2/dvfs.c | 2 +-
- arch/arm/mach-omap2/smartreflex-class1p5.c | 562 +++++++++++++++++++++++++
- arch/arm/mach-omap2/smartreflex-class3.c | 4 +-
- arch/arm/mach-omap2/smartreflex.c | 34 ++-
- arch/arm/mach-omap2/voltage.c | 61 +++
- arch/arm/plat-omap/Kconfig | 19 +
- arch/arm/plat-omap/include/plat/smartreflex.h | 13 +-
- arch/arm/plat-omap/include/plat/voltage.h | 23 +-
- 9 files changed, 710 insertions(+), 9 deletions(-)
+ arch/arm/mach-omap2/Makefile | 1 +
+ arch/arm/mach-omap2/dvfs.c | 2 +-
+ arch/arm/mach-omap2/smartreflex-class1p5.c | 562 ++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/smartreflex-class3.c | 4 +-
+ arch/arm/mach-omap2/smartreflex.c | 34 ++-
+ arch/arm/mach-omap2/smartreflex.h | 13 +-
+ arch/arm/mach-omap2/voltage.c | 61 +++
+ arch/arm/mach-omap2/voltage.h | 23 ++
+ arch/arm/plat-omap/Kconfig | 19 +
+ 9 files changed, 711 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/mach-omap2/smartreflex-class1p5.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
-index 625087e..61b9daf 100644
+index b550381..5613318 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o
@@ -175,8 +176,8 @@ index 0000000..6bddce0
+#include <linux/workqueue.h>
+#include <linux/opp.h>
+
-+#include <plat/smartreflex.h>
-+#include <plat/voltage.h>
++#include "smartreflex.h"
++#include "voltage.h"
+#include <plat/dvfs.h>
+
+#define MAX_VDDS 3
@@ -709,7 +710,7 @@ index 0000000..6bddce0
+}
+late_initcall(sr_class1p5_init);
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
-index 7ac88da..5f7a33e 100644
+index 1d3eb11..0136afb 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -21,7 +21,9 @@ static int sr_class3_enable(struct voltagedomain *voltdm,
@@ -724,7 +725,7 @@ index 7ac88da..5f7a33e 100644
omap_vp_disable(voltdm);
sr_disable(voltdm);
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index 6ffc1a0..09f65a0 100644
+index 87fff94..be161a0 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -318,7 +318,9 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
@@ -738,7 +739,7 @@ index 6ffc1a0..09f65a0 100644
if (sr_class->class_deinit &&
sr_class->class_deinit(sr->voltdm,
sr_class->class_priv_data)) {
-@@ -474,6 +476,28 @@ static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
+@@ -475,6 +477,28 @@ static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
/* Public Functions */
/**
@@ -767,7 +768,7 @@ index 6ffc1a0..09f65a0 100644
* sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
* error generator module.
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
-@@ -842,6 +866,7 @@ void omap_sr_enable(struct voltagedomain *voltdm,
+@@ -843,6 +867,7 @@ void omap_sr_enable(struct voltagedomain *voltdm,
* omap_sr_disable() - API to disable SR without resetting the voltage
* processor voltage
* @voltdm: VDD pointer to which the SR module to be configured belongs to.
@@ -775,7 +776,7 @@ index 6ffc1a0..09f65a0 100644
*
* This API is to be called from the kernel in order to disable
* a particular smartreflex module. This API will in turn call
-@@ -849,7 +874,8 @@ void omap_sr_enable(struct voltagedomain *voltdm,
+@@ -850,7 +875,8 @@ void omap_sr_enable(struct voltagedomain *voltdm,
* the smartreflex class disable not to reset the VP voltage after
* disabling smartreflex.
*/
@@ -785,7 +786,7 @@ index 6ffc1a0..09f65a0 100644
{
struct omap_sr *sr = _sr_lookup(voltdm);
-@@ -868,7 +894,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
+@@ -869,7 +895,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
return;
}
@@ -794,7 +795,7 @@ index 6ffc1a0..09f65a0 100644
}
/**
-@@ -901,7 +927,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
+@@ -902,7 +928,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
return;
}
@@ -803,11 +804,62 @@ index 6ffc1a0..09f65a0 100644
}
/**
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 78d409a..eb3c87f 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -168,6 +168,7 @@ struct omap_sr_pmic_data {
+ #define SR_CLASS1 0x1
+ #define SR_CLASS2 0x2
+ #define SR_CLASS3 0x3
++#define SR_CLASS1P5 0x4
+
+ /**
+ * struct omap_sr_class_data - Smartreflex class driver info
+@@ -188,7 +189,9 @@ struct omap_sr_pmic_data {
+ struct omap_sr_class_data {
+ int (*enable)(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data);
+- int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
++ int (*disable)(struct voltagedomain *voltdm,
++ struct omap_volt_data *volt_data,
++ int is_volt_reset);
+ int (*class_init)(struct voltagedomain *voltdm, void *class_priv_data);
+ int (*class_deinit)(struct voltagedomain *voltdm,
+ void *class_priv_data);
+@@ -236,7 +239,8 @@ struct omap_sr_data {
+ /* Smartreflex module enable/disable interface */
+ void omap_sr_enable(struct voltagedomain *voltdm,
+ struct omap_volt_data *volt_data);
+-void omap_sr_disable(struct voltagedomain *voltdm);
++void omap_sr_disable(struct voltagedomain *voltdm,
++ struct omap_volt_data *volt_data);
+ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+
+ /* API to register the pmic specific data with the smartreflex driver. */
+@@ -251,6 +255,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm);
+
+ /* API to register the smartreflex class driver with the smartreflex driver */
+ int sr_register_class(struct omap_sr_class_data *class_data);
++bool is_sr_enabled(struct voltagedomain *voltdm);
+ #else
+ static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+ static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+@@ -265,5 +270,9 @@ static inline void omap_sr_disable_reset_volt(
+ struct voltagedomain *voltdm) {}
+ static inline void omap_sr_register_pmic(
+ struct omap_sr_pmic_data *pmic_data) {}
++static bool is_sr_enabled(struct voltagedomain *voltdm)
++{
++ return false;
++}
+ #endif
+ #endif
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
-index 15eed85..5675a13 100644
+index 02d7072..8533c4a 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
-@@ -290,9 +290,45 @@ static int nom_volt_debug_get(void *data, u64 *val)
+@@ -291,9 +291,45 @@ static int nom_volt_debug_get(void *data, u64 *val)
return 0;
}
@@ -853,7 +905,7 @@ index 15eed85..5675a13 100644
static void vp_latch_vsel(struct omap_vdd_info *vdd)
{
u32 vpconfig;
-@@ -420,6 +456,12 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
+@@ -421,6 +457,12 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
(void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
vdd->debug_dir, (void *) vdd,
&nom_volt_debug_fops);
@@ -866,7 +918,7 @@ index 15eed85..5675a13 100644
}
/* Voltage scale and accessory APIs */
-@@ -1052,6 +1094,25 @@ struct omap_volt_data *omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+@@ -1053,6 +1095,25 @@ struct omap_volt_data *omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
return vdd->curr_volt;
}
@@ -892,91 +944,10 @@ index 15eed85..5675a13 100644
/**
* omap_vp_get_curr_volt() - API to get the current vp voltage.
* @voltdm: pointer to the VDD.
-diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
-index b6333ae..121756a 100644
---- a/arch/arm/plat-omap/Kconfig
-+++ b/arch/arm/plat-omap/Kconfig
-@@ -67,6 +67,25 @@ config OMAP_SMARTREFLEX_CLASS3
- Class 3 implementation of Smartreflex employs continuous hardware
- voltage calibration.
-
-+config OMAP_SMARTREFLEX_CLASS1P5
-+ bool "Class 1.5 mode of Smartreflex Implementation"
-+ depends on OMAP_SMARTREFLEX && TWL4030_CORE
-+ help
-+ Say Y to enable Class 1.5 implementation of Smartreflex
-+
-+ Class 1.5 implementation of Smartreflex employs software controlled
-+ hardware voltage calibration.
-+
-+config OMAP_SR_CLASS1P5_RECALIBRATION_DELAY
-+ int "Class 1.5 mode recalibration recalibration delay(ms)"
-+ depends on OMAP_SMARTREFLEX_CLASS1P5
-+ default 86400000
-+ help
-+ Setup the recalibration delay in milliseconds. Use 0 for never doing
-+ a recalibration. Defaults to recommended recalibration every 24hrs.
-+ If you do not understand this, use the default.
-+
-+
- config OMAP_RESET_CLOCKS
- bool "Reset unused clocks during boot"
- depends on ARCH_OMAP
-diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
-index 07f35b2..192cb06 100644
---- a/arch/arm/plat-omap/include/plat/smartreflex.h
-+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
-@@ -167,6 +167,7 @@ struct omap_sr_pmic_data {
- #define SR_CLASS1 0x1
- #define SR_CLASS2 0x2
- #define SR_CLASS3 0x3
-+#define SR_CLASS1P5 0x4
-
- /**
- * struct omap_sr_class_data - Smartreflex class driver info
-@@ -187,7 +188,9 @@ struct omap_sr_pmic_data {
- struct omap_sr_class_data {
- int (*enable)(struct voltagedomain *voltdm,
- struct omap_volt_data *volt_data);
-- int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
-+ int (*disable)(struct voltagedomain *voltdm,
-+ struct omap_volt_data *volt_data,
-+ int is_volt_reset);
- int (*class_init)(struct voltagedomain *voltdm, void *class_priv_data);
- int (*class_deinit)(struct voltagedomain *voltdm,
- void *class_priv_data);
-@@ -235,7 +238,8 @@ struct omap_sr_data {
- /* Smartreflex module enable/disable interface */
- void omap_sr_enable(struct voltagedomain *voltdm,
- struct omap_volt_data *volt_data);
--void omap_sr_disable(struct voltagedomain *voltdm);
-+void omap_sr_disable(struct voltagedomain *voltdm,
-+ struct omap_volt_data *volt_data);
- void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
-
- /* API to register the pmic specific data with the smartreflex driver. */
-@@ -250,6 +254,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm);
-
- /* API to register the smartreflex class driver with the smartreflex driver */
- int sr_register_class(struct omap_sr_class_data *class_data);
-+bool is_sr_enabled(struct voltagedomain *voltdm);
- #else
- static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
- static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
-@@ -264,5 +269,9 @@ static inline void omap_sr_disable_reset_volt(
- struct voltagedomain *voltdm) {}
- static inline void omap_sr_register_pmic(
- struct omap_sr_pmic_data *pmic_data) {}
-+static bool is_sr_enabled(struct voltagedomain *voltdm)
-+{
-+ return false;
-+}
- #endif
- #endif
-diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
-index 6f310f2..3553b89 100644
---- a/arch/arm/plat-omap/include/plat/voltage.h
-+++ b/arch/arm/plat-omap/include/plat/voltage.h
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 6f310f2..c8f69e4 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
@@ -58,6 +58,8 @@
#define OMAP4430_VDD_CORE_OPP50_UV 930000
#define OMAP4430_VDD_CORE_OPP100_UV 1100000
@@ -1003,16 +974,15 @@ index 6f310f2..3553b89 100644
#ifdef CONFIG_PM
int omap_voltage_register_pmic(struct voltagedomain *voltdm,
struct omap_volt_pmic_info *pmic_info);
-@@ -308,7 +313,23 @@ static inline unsigned long omap_get_operation_voltage(
+@@ -308,7 +313,25 @@ static inline unsigned long omap_get_operation_voltage(
{
if (IS_ERR_OR_NULL(vdata))
return 0;
-- return vdata->volt_nominal;
+ return (vdata->volt_calibrated) ? vdata->volt_calibrated :
+ (vdata->volt_dynamic_nominal) ? vdata->volt_dynamic_nominal :
+ vdata->volt_nominal;
- }
-
++}
++
+/* what is my dynamic nominal? */
+static inline unsigned long omap_get_dyn_nominal(struct omap_volt_data *vdata)
+{
@@ -1025,9 +995,41 @@ index 6f310f2..3553b89 100644
+ return vdata->volt_nominal;
+ return v;
+ }
-+ return vdata->volt_nominal;
-+}
+ return vdata->volt_nominal;
+ }
+
#endif
++
+diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
+index b6333ae..121756a 100644
+--- a/arch/arm/plat-omap/Kconfig
++++ b/arch/arm/plat-omap/Kconfig
+@@ -67,6 +67,25 @@ config OMAP_SMARTREFLEX_CLASS3
+ Class 3 implementation of Smartreflex employs continuous hardware
+ voltage calibration.
+
++config OMAP_SMARTREFLEX_CLASS1P5
++ bool "Class 1.5 mode of Smartreflex Implementation"
++ depends on OMAP_SMARTREFLEX && TWL4030_CORE
++ help
++ Say Y to enable Class 1.5 implementation of Smartreflex
++
++ Class 1.5 implementation of Smartreflex employs software controlled
++ hardware voltage calibration.
++
++config OMAP_SR_CLASS1P5_RECALIBRATION_DELAY
++ int "Class 1.5 mode recalibration recalibration delay(ms)"
++ depends on OMAP_SMARTREFLEX_CLASS1P5
++ default 86400000
++ help
++ Setup the recalibration delay in milliseconds. Use 0 for never doing
++ a recalibration. Defaults to recommended recalibration every 24hrs.
++ If you do not understand this, use the default.
++
++
+ config OMAP_RESET_CLOCKS
+ bool "Reset unused clocks during boot"
+ depends on ARCH_OMAP
--
1.7.1
diff --git a/patches/dvfs/0054-omap3430-sr-class3-restrict-cpu-to-run-on.patch b/patches/dvfs/0054-omap3430-sr-class3-restrict-cpu-to-run-on.patch
index 3323fcdc297e5d7d770399eb9d11e54398490de4..54203885cfc7bd4ce4bc2311bd94855604444ac8 100644
--- a/patches/dvfs/0054-omap3430-sr-class3-restrict-cpu-to-run-on.patch
+++ b/patches/dvfs/0054-omap3430-sr-class3-restrict-cpu-to-run-on.patch
@@ -7,12 +7,13 @@ Use SmartReflex AVS Class3 initialization only for OMAP343x family of
processors.
Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm/mach-omap2/smartreflex-class3.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
-index 5f7a33e..f99e517 100644
+index 0136afb..6fbed0c 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -11,6 +11,7 @@
@@ -20,7 +21,7 @@ index 5f7a33e..f99e517 100644
*/
+#include <plat/cpu.h>
- #include <plat/smartreflex.h>
+ #include "smartreflex.h"
static int sr_class3_enable(struct voltagedomain *voltdm,
@@ -49,6 +50,10 @@ static struct omap_sr_class_data class3_data = {
diff --git a/patches/dvfs/for-2.6.39/0007-OMAP2-3-PM-remove-unnecessary-wakeup-sleep-dependenc.patch b/patches/dvfs/for-2.6.39/0007-OMAP2-3-PM-remove-unnecessary-wakeup-sleep-dependenc.patch
deleted file mode 100644
index 4b27a0bdcfdcd0d6c2bc87c0e5152b1749fcef3b..0000000000000000000000000000000000000000
--- a/patches/dvfs/for-2.6.39/0007-OMAP2-3-PM-remove-unnecessary-wakeup-sleep-dependenc.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From d0bc69bf5875fd8ff8cfc31e3005ab8f8b7b18c0 Mon Sep 17 00:00:00 2001
-From: Paul Walmsley <paul@pwsan.com>
-Date: Thu, 27 Jan 2011 02:52:55 -0700
-Subject: [PATCH 07/10] OMAP2/3: PM: remove unnecessary wakeup/sleep dependency clear
-
-The OMAP2 and OMAP3 PM code clears clockdomain wakeup and sleep
-dependencies. This is unnecessary after commit
-6f7f63cc9adf3192e6fcac4e8bed5cc10fd924aa ("OMAP clockdomain:
-initialize clockdomain registers when the clockdomain layer starts")
-which clears these dependencies during clockdomain init.
-
-Signed-off-by: Paul Walmsley <paul@pwsan.com>
-Signed-off-by: Kevin Hilman <khilman@ti.com>
----
- arch/arm/mach-omap2/pm24xx.c | 8 +-------
- arch/arm/mach-omap2/pm34xx.c | 15 ---------------
- 2 files changed, 1 insertions(+), 22 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
-index 97feb3a..10f8747 100644
---- a/arch/arm/mach-omap2/pm24xx.c
-+++ b/arch/arm/mach-omap2/pm24xx.c
-@@ -363,9 +363,6 @@ static const struct platform_suspend_ops __initdata omap_pm_ops;
- /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
- static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
- {
-- clkdm_clear_all_wkdeps(clkdm);
-- clkdm_clear_all_sleepdeps(clkdm);
--
- if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
- omap2_clkdm_allow_idle(clkdm);
- else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-@@ -411,10 +408,7 @@ static void __init prcm_setup_regs(void)
- pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
- omap2_clkdm_sleep(gfx_clkdm);
-
-- /*
-- * Clear clockdomain wakeup dependencies and enable
-- * hardware-supervised idle for all clkdms
-- */
-+ /* Enable hardware-supervised idle for all clkdms */
- clkdm_for_each(clkdms_setup, NULL);
- clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
-
-diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
-index 6ade4ea..b9427c7 100644
---- a/arch/arm/mach-omap2/pm34xx.c
-+++ b/arch/arm/mach-omap2/pm34xx.c
-@@ -695,21 +695,6 @@ static void __init prcm_setup_regs(void)
- u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
- OMAP3630_GRPSEL_UART4_MASK : 0;
-
--
-- /* XXX Reset all wkdeps. This should be done when initializing
-- * powerdomains */
-- omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
-- omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
-- omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
-- omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
-- omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
-- omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
-- if (omap_rev() > OMAP3430_REV_ES1_0) {
-- omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
-- omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
-- } else
-- omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
--
- /*
- * Enable interface clock autoidle for all modules.
- * Note that in the long run this should be done by clockfw
---
-1.7.1
-
diff --git a/patches/for_next/0001-merge-changes-missed-in-rebase.patch b/patches/for_next/0001-merge-changes-missed-in-rebase.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e11f1d8e22ab365804fa903377ed7804cc3b6acd
--- /dev/null
+++ b/patches/for_next/0001-merge-changes-missed-in-rebase.patch
@@ -0,0 +1,230 @@
+From b4f5adde25a2e491f71c7915a85451a540e58474 Mon Sep 17 00:00:00 2001
+From: Robert Nelson <robertcnelson@gmail.com>
+Date: Sat, 12 Mar 2011 19:58:07 -0600
+Subject: [PATCH] merge changes missed in rebase
+
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 9 +--
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 4 +
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 ++
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 +
+ arch/arm/mach-omap2/pm34xx.c | 102 +-------------------------
+ arch/arm/mach-omap2/timer-gp.c | 1 +
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
+ 7 files changed, 19 insertions(+), 108 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 5f33ed4..b391804 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -533,13 +533,8 @@ static struct regulator_init_data sdp3430_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &sdp3430_vdda_dac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
++ .consumer_supplies = sdp3430_vdda_dac_supplies,
+ };
+
+ static struct regulator_init_data sdp3430_vpll2 = {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 5afe27d..0fdf2ca 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -2723,6 +2723,10 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ &omap2430_mcspi1_hwmod,
+ &omap2430_mcspi2_hwmod,
+ &omap2430_mcspi3_hwmod,
++
++ /* usbotg class*/
++ &omap2430_usbhsotg_hwmod,
++
+ NULL,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 1d05660..c819c30 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -22,6 +22,8 @@
+ #include <plat/l4_3xxx.h>
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
++#include <plat/mmc.h>
++#include <plat/mcbsp.h>
+ #include <plat/mcspi.h>
+ #include <plat/dmtimer.h>
+
+@@ -3638,6 +3640,13 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ &omap34xx_mcspi2,
+ &omap34xx_mcspi3,
+ &omap34xx_mcspi4,
++
++ /* usbotg class */
++ &omap3xxx_usbhsotg_hwmod,
++
++ /* usbotg for am35x */
++ &am35xx_usbhsotg_hwmod,
++
+ NULL,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index eaef28f..3e88dd3 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -25,6 +25,7 @@
+ #include <plat/gpio.h>
+ #include <plat/dma.h>
+ #include <plat/mcspi.h>
++#include <plat/mcbsp.h>
+ #include <plat/mmc.h>
+
+ #include "omap_hwmod_common_data.h"
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index bab0343..0c5e3a4 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
++++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -695,107 +695,7 @@ static void __init prcm_setup_regs(void)
+ u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
+ OMAP3630_GRPSEL_UART4_MASK : 0;
+
+- /*
+- * Enable interface clock autoidle for all modules.
+- * Note that in the long run this should be done by clockfw
+- */
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_MODEM_MASK |
+- OMAP3430ES2_AUTO_MMC3_MASK |
+- OMAP3430ES2_AUTO_ICR_MASK |
+- OMAP3430_AUTO_AES2_MASK |
+- OMAP3430_AUTO_SHA12_MASK |
+- OMAP3430_AUTO_DES2_MASK |
+- OMAP3430_AUTO_MMC2_MASK |
+- OMAP3430_AUTO_MMC1_MASK |
+- OMAP3430_AUTO_MSPRO_MASK |
+- OMAP3430_AUTO_HDQ_MASK |
+- OMAP3430_AUTO_MCSPI4_MASK |
+- OMAP3430_AUTO_MCSPI3_MASK |
+- OMAP3430_AUTO_MCSPI2_MASK |
+- OMAP3430_AUTO_MCSPI1_MASK |
+- OMAP3430_AUTO_I2C3_MASK |
+- OMAP3430_AUTO_I2C2_MASK |
+- OMAP3430_AUTO_I2C1_MASK |
+- OMAP3430_AUTO_UART2_MASK |
+- OMAP3430_AUTO_UART1_MASK |
+- OMAP3430_AUTO_GPT11_MASK |
+- OMAP3430_AUTO_GPT10_MASK |
+- OMAP3430_AUTO_MCBSP5_MASK |
+- OMAP3430_AUTO_MCBSP1_MASK |
+- OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
+- OMAP3430_AUTO_MAILBOXES_MASK |
+- OMAP3430_AUTO_OMAPCTRL_MASK |
+- OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
+- OMAP3430_AUTO_HSOTGUSB_MASK |
+- OMAP3430_AUTO_SAD2D_MASK |
+- OMAP3430_AUTO_SSI_MASK,
+- CORE_MOD, CM_AUTOIDLE1);
+-
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_PKA_MASK |
+- OMAP3430_AUTO_AES1_MASK |
+- OMAP3430_AUTO_RNG_MASK |
+- OMAP3430_AUTO_SHA11_MASK |
+- OMAP3430_AUTO_DES1_MASK,
+- CORE_MOD, CM_AUTOIDLE2);
+-
+- if (omap_rev() > OMAP3430_REV_ES1_0) {
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_MAD2D_MASK |
+- OMAP3430ES2_AUTO_USBTLL_MASK,
+- CORE_MOD, CM_AUTOIDLE3);
+- }
+-
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_WDT2_MASK |
+- OMAP3430_AUTO_WDT1_MASK |
+- OMAP3430_AUTO_GPIO1_MASK |
+- OMAP3430_AUTO_32KSYNC_MASK |
+- OMAP3430_AUTO_GPT12_MASK |
+- OMAP3430_AUTO_GPT1_MASK,
+- WKUP_MOD, CM_AUTOIDLE);
+-
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_DSS_MASK,
+- OMAP3430_DSS_MOD,
+- CM_AUTOIDLE);
+-
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_CAM_MASK,
+- OMAP3430_CAM_MOD,
+- CM_AUTOIDLE);
+-
+- omap2_cm_write_mod_reg(
+- omap3630_auto_uart4_mask |
+- OMAP3430_AUTO_GPIO6_MASK |
+- OMAP3430_AUTO_GPIO5_MASK |
+- OMAP3430_AUTO_GPIO4_MASK |
+- OMAP3430_AUTO_GPIO3_MASK |
+- OMAP3430_AUTO_GPIO2_MASK |
+- OMAP3430_AUTO_WDT3_MASK |
+- OMAP3430_AUTO_UART3_MASK |
+- OMAP3430_AUTO_GPT9_MASK |
+- OMAP3430_AUTO_GPT8_MASK |
+- OMAP3430_AUTO_GPT7_MASK |
+- OMAP3430_AUTO_GPT6_MASK |
+- OMAP3430_AUTO_GPT5_MASK |
+- OMAP3430_AUTO_GPT4_MASK |
+- OMAP3430_AUTO_GPT3_MASK |
+- OMAP3430_AUTO_GPT2_MASK |
+- OMAP3430_AUTO_MCBSP4_MASK |
+- OMAP3430_AUTO_MCBSP3_MASK |
+- OMAP3430_AUTO_MCBSP2_MASK,
+- OMAP3430_PER_MOD,
+- CM_AUTOIDLE);
+-
+- if (omap_rev() > OMAP3430_REV_ES1_0) {
+- omap2_cm_write_mod_reg(
+- OMAP3430ES2_AUTO_USBHOST_MASK,
+- OMAP3430ES2_USBHOST_MOD,
+- CM_AUTOIDLE);
+- }
+-
++ /* XXX This should be handled by hwmod code or SCM init code */
+ omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
+
+ /*
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+index 1887dd0..3b9cf85 100644
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ b/arch/arm/mach-omap2/timer-gp.c
+@@ -39,6 +39,7 @@
+ #include <asm/mach/time.h>
+ #include <plat/dmtimer.h>
+ #include <asm/localtimer.h>
++#include <asm/sched_clock.h>
+ #include <plat/common.h>
+ #include <plat/omap_hwmod.h>
+
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index aef7081..1adea9c 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -380,6 +380,7 @@ struct omap_hwmod_omap4_prcm {
+ * XXX Should be HWMOD_SETUP_NO_RESET
+ * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
+ * controller, etc. XXX probably belongs outside the main hwmod file
++ * XXX Should be HWMOD_SETUP_NO_IDLE
+ * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ * when module is enabled, rather than the default, which is to
+ * enable autoidle
+--
+1.7.1
+
diff --git a/patches/for_next/0001-omap-Start-using-CONFIG_SOC_OMAP.patch b/patches/for_next/0001-omap-Start-using-CONFIG_SOC_OMAP.patch
new file mode 100644
index 0000000000000000000000000000000000000000..52303e67381f11ab086618244e4a25f7f2508796
--- /dev/null
+++ b/patches/for_next/0001-omap-Start-using-CONFIG_SOC_OMAP.patch
@@ -0,0 +1,717 @@
+From 53d8f08065ccf0f2b7e520997ca3168b0e02e05e Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Thu, 27 Jan 2011 16:39:40 -0800
+Subject: [PATCH 001/254] omap: Start using CONFIG_SOC_OMAP
+
+We want to have just CONFIG_ARCH_OMAP2, 3 and 4. The rest
+are nowadays just subcategories of these.
+
+Search and replace the following:
+
+ARCH_OMAP2420 SOC_OMAP2420
+ARCH_OMAP2430 SOC_OMAP2430
+ARCH_OMAP3430 SOC_OMAP3430
+
+No functional changes.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Thomas Weber <weber@corscience.de>
+Acked-by: Sourav Poddar <sourav.poddar@ti.com>
+---
+ arch/arm/mach-omap2/Kconfig | 16 ++++++++--------
+ arch/arm/mach-omap2/Makefile | 20 ++++++++++----------
+ arch/arm/mach-omap2/clock2xxx.h | 4 ++--
+ arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 16 ++++++++--------
+ arch/arm/mach-omap2/common.c | 4 ++--
+ arch/arm/mach-omap2/devices.c | 6 +++---
+ arch/arm/mach-omap2/io.c | 8 ++++----
+ arch/arm/mach-omap2/mailbox.c | 2 +-
+ arch/arm/mach-omap2/mcbsp.c | 4 ++--
+ arch/arm/mach-omap2/opp2xxx.h | 2 +-
+ arch/arm/mach-omap2/powerdomains2xxx_data.c | 6 +++---
+ arch/arm/plat-omap/counter_32k.c | 4 ++--
+ arch/arm/plat-omap/include/plat/cpu.h | 10 +++++-----
+ arch/arm/plat-omap/include/plat/io.h | 4 ++--
+ arch/arm/plat-omap/include/plat/multi.h | 4 ++--
+ arch/arm/plat-omap/sram.c | 4 ++--
+ drivers/mmc/host/Kconfig | 2 +-
+ drivers/spi/omap2_mcspi.c | 4 ++--
+ drivers/usb/musb/musb_core.c | 2 +-
+ drivers/usb/musb/musb_core.h | 6 +++---
+ drivers/usb/musb/musbhsdma.h | 2 +-
+ drivers/w1/masters/Kconfig | 2 +-
+ sound/soc/omap/omap-mcbsp.c | 6 +++---
+ sound/soc/omap/omap-mcbsp.h | 4 ++--
+ 24 files changed, 71 insertions(+), 71 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
+index 1a2cf62..ae7f47d 100644
+--- a/arch/arm/mach-omap2/Kconfig
++++ b/arch/arm/mach-omap2/Kconfig
+@@ -53,20 +53,20 @@ config ARCH_OMAP4
+ comment "OMAP Core Type"
+ depends on ARCH_OMAP2
+
+-config ARCH_OMAP2420
++config SOC_OMAP2420
+ bool "OMAP2420 support"
+ depends on ARCH_OMAP2
+ default y
+ select OMAP_DM_TIMER
+ select ARCH_OMAP_OTG
+
+-config ARCH_OMAP2430
++config SOC_OMAP2430
+ bool "OMAP2430 support"
+ depends on ARCH_OMAP2
+ default y
+ select ARCH_OMAP_OTG
+
+-config ARCH_OMAP3430
++config SOC_OMAP3430
+ bool "OMAP3430 support"
+ depends on ARCH_OMAP3
+ default y
+@@ -106,25 +106,25 @@ config MACH_OMAP_GENERIC
+
+ config MACH_OMAP2_TUSB6010
+ bool
+- depends on ARCH_OMAP2 && ARCH_OMAP2420
++ depends on ARCH_OMAP2 && SOC_OMAP2420
+ default y if MACH_NOKIA_N8X0
+
+ config MACH_OMAP_H4
+ bool "OMAP 2420 H4 board"
+- depends on ARCH_OMAP2420
++ depends on SOC_OMAP2420
+ default y
+ select OMAP_PACKAGE_ZAF
+ select OMAP_DEBUG_DEVICES
+
+ config MACH_OMAP_APOLLON
+ bool "OMAP 2420 Apollon board"
+- depends on ARCH_OMAP2420
++ depends on SOC_OMAP2420
+ default y
+ select OMAP_PACKAGE_ZAC
+
+ config MACH_OMAP_2430SDP
+ bool "OMAP 2430 SDP board"
+- depends on ARCH_OMAP2430
++ depends on SOC_OMAP2430
+ default y
+ select OMAP_PACKAGE_ZAC
+
+@@ -219,7 +219,7 @@ config MACH_NOKIA_N810_WIMAX
+
+ config MACH_NOKIA_N8X0
+ bool "Nokia N800/N810"
+- depends on ARCH_OMAP2420
++ depends on SOC_OMAP2420
+ default y
+ select OMAP_PACKAGE_ZAC
+ select MACH_NOKIA_N800
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 1c0c2b0..9eeabaf 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -31,8 +31,8 @@ AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
+ AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec)
+
+ # Functions loaded to SRAM
+-obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
+-obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
++obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
++obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
+ obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
+
+ AFLAGS_sram242x.o :=-Wa,-march=armv6
+@@ -40,8 +40,8 @@ AFLAGS_sram243x.o :=-Wa,-march=armv6
+ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
+
+ # Pin multiplexing
+-obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o
+-obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o
++obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
++obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
+ obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
+ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
+
+@@ -113,8 +113,8 @@ obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
+ clkt2xxx_dpllcore.o \
+ clkt2xxx_virt_prcm_set.o \
+ clkt2xxx_apll.o clkt2xxx_osc.o
+-obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o
+-obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o
++obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
++obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
+ clock34xx.o clkt34xx_dpll3m2.o \
+ clock3517.o clock36xx.o \
+@@ -123,12 +123,12 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
+ dpll3xxx.o
+
+ # OMAP2 clock rate set data (old "OPP" data)
+-obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
+-obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
++obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
++obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
+
+ # hwmod data
+-obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o
+-obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o
++obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
++obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
+
+diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
+index 6a658b8..cc5c8d4 100644
+--- a/arch/arm/mach-omap2/clock2xxx.h
++++ b/arch/arm/mach-omap2/clock2xxx.h
+@@ -20,13 +20,13 @@ u32 omap2xxx_get_apll_clkin(void);
+ u32 omap2xxx_get_sysclkdiv(void);
+ void omap2xxx_clk_prepare_for_reboot(void);
+
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ int omap2420_clk_init(void);
+ #else
+ #define omap2420_clk_init() 0
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ int omap2430_clk_init(void);
+ #else
+ #define omap2430_clk_init() 0
+diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+index e4a7133..e6f0d18 100644
+--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
++++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+@@ -171,7 +171,7 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
+
+ /* 2430-specific possible wakeup dependencies */
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+
+ /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
+ static struct clkdm_dep mdm_2430_wkdeps[] = {
+@@ -194,7 +194,7 @@ static struct clkdm_dep mdm_2430_wkdeps[] = {
+ { NULL },
+ };
+
+-#endif /* CONFIG_ARCH_OMAP2430 */
++#endif /* CONFIG_SOC_OMAP2430 */
+
+
+ /* OMAP3-specific possible dependencies */
+@@ -450,7 +450,7 @@ static struct clockdomain cm_clkdm = {
+ * 2420-only clockdomains
+ */
+
+-#if defined(CONFIG_ARCH_OMAP2420)
++#if defined(CONFIG_SOC_OMAP2420)
+
+ static struct clockdomain mpu_2420_clkdm = {
+ .name = "mpu_clkdm",
+@@ -514,14 +514,14 @@ static struct clockdomain dss_2420_clkdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
+-#endif /* CONFIG_ARCH_OMAP2420 */
++#endif /* CONFIG_SOC_OMAP2420 */
+
+
+ /*
+ * 2430-only clockdomains
+ */
+
+-#if defined(CONFIG_ARCH_OMAP2430)
++#if defined(CONFIG_SOC_OMAP2430)
+
+ static struct clockdomain mpu_2430_clkdm = {
+ .name = "mpu_clkdm",
+@@ -600,7 +600,7 @@ static struct clockdomain dss_2430_clkdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+-#endif /* CONFIG_ARCH_OMAP2430 */
++#endif /* CONFIG_SOC_OMAP2430 */
+
+
+ /*
+@@ -811,7 +811,7 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
+ &cm_clkdm,
+ &prm_clkdm,
+
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ &mpu_2420_clkdm,
+ &iva1_2420_clkdm,
+ &dsp_2420_clkdm,
+@@ -821,7 +821,7 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
+ &dss_2420_clkdm,
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ &mpu_2430_clkdm,
+ &mdm_clkdm,
+ &dsp_2430_clkdm,
+diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
+index 778929f..d5eaee3 100644
+--- a/arch/arm/mach-omap2/common.c
++++ b/arch/arm/mach-omap2/common.c
+@@ -40,7 +40,7 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
+
+ #endif
+
+-#if defined(CONFIG_ARCH_OMAP2420)
++#if defined(CONFIG_SOC_OMAP2420)
+
+ static struct omap_globals omap242x_globals = {
+ .class = OMAP242X_CLASS,
+@@ -61,7 +61,7 @@ void __init omap2_set_globals_242x(void)
+ }
+ #endif
+
+-#if defined(CONFIG_ARCH_OMAP2430)
++#if defined(CONFIG_SOC_OMAP2430)
+
+ static struct omap_globals omap243x_globals = {
+ .class = OMAP243X_CLASS,
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index 2c9c912..e0f0ef9 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -333,7 +333,7 @@ static struct platform_device omap2_mcspi2 = {
+ },
+ };
+
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+ defined(CONFIG_ARCH_OMAP4)
+ static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
+ .num_cs = 2,
+@@ -400,7 +400,7 @@ static inline void omap4_mcspi_fixup(void)
+ }
+ #endif
+
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+ defined(CONFIG_ARCH_OMAP4)
+ static inline void omap2_mcspi3_init(void)
+ {
+@@ -895,7 +895,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ /*-------------------------------------------------------------------------*/
+
+ #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
+ #define OMAP_HDQ_BASE 0x480B2000
+ #endif
+ static struct resource omap_hdq_resources[] = {
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index c203204..11decd8 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -66,7 +66,7 @@ static struct map_desc omap24xx_io_desc[] __initdata = {
+ },
+ };
+
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ static struct map_desc omap242x_io_desc[] __initdata = {
+ {
+ .virtual = DSP_MEM_2420_VIRT,
+@@ -90,7 +90,7 @@ static struct map_desc omap242x_io_desc[] __initdata = {
+
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ static struct map_desc omap243x_io_desc[] __initdata = {
+ {
+ .virtual = L4_WK_243X_VIRT,
+@@ -241,7 +241,7 @@ static void __init _omap2_map_common_io(void)
+ omap_sram_init();
+ }
+
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ void __init omap242x_map_common_io(void)
+ {
+ iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
+@@ -250,7 +250,7 @@ void __init omap242x_map_common_io(void)
+ }
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ void __init omap243x_map_common_io(void)
+ {
+ iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
+diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
+index 24b8850..20b8777 100644
+--- a/arch/arm/mach-omap2/mailbox.c
++++ b/arch/arm/mach-omap2/mailbox.c
+@@ -312,7 +312,7 @@ struct omap_mbox mbox_dsp_info = {
+ struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
+ #endif
+
+-#if defined(CONFIG_ARCH_OMAP2420)
++#if defined(CONFIG_SOC_OMAP2420)
+ /* IVA */
+ static struct omap_mbox2_priv omap2_mbox_iva_priv = {
+ .tx_fifo = {
+diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
+index f9c9df5..0526b75 100644
+--- a/arch/arm/mach-omap2/mcbsp.c
++++ b/arch/arm/mach-omap2/mcbsp.c
+@@ -104,7 +104,7 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
+
+ /* Platform data */
+
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
+ {
+ .phys_base = OMAP24XX_MCBSP1_BASE,
+@@ -129,7 +129,7 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
+ #define OMAP2420_MCBSP_REG_NUM 0
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
+ {
+ .phys_base = OMAP24XX_MCBSP1_BASE,
+diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
+index 38b7305..8affc66 100644
+--- a/arch/arm/mach-omap2/opp2xxx.h
++++ b/arch/arm/mach-omap2/opp2xxx.h
+@@ -418,7 +418,7 @@ struct prcm_config {
+
+ extern const struct prcm_config omap2420_rate_table[];
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ extern const struct prcm_config omap2430_rate_table[];
+ #else
+ #define omap2430_rate_table NULL
+diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
+index 9b1a335..78739e1 100644
+--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
++++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
+@@ -78,7 +78,7 @@ static struct powerdomain core_24xx_pwrdm = {
+ * 2430-specific powerdomains
+ */
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+
+ /* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
+
+@@ -97,7 +97,7 @@ static struct powerdomain mdm_pwrdm = {
+ },
+ };
+
+-#endif /* CONFIG_ARCH_OMAP2430 */
++#endif /* CONFIG_SOC_OMAP2430 */
+
+ /* As powerdomains are added or removed above, this list must also be changed */
+ static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
+@@ -111,7 +111,7 @@ static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
+ &core_24xx_pwrdm,
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ &mdm_pwrdm,
+ #endif
+ NULL
+diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
+index 862dda9..f7fed60 100644
+--- a/arch/arm/plat-omap/counter_32k.c
++++ b/arch/arm/plat-omap/counter_32k.c
+@@ -54,7 +54,7 @@ static cycle_t notrace omap16xx_32k_read(struct clocksource *cs)
+ #define omap16xx_32k_read NULL
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
+ {
+ return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
+@@ -63,7 +63,7 @@ static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
+ #define omap2420_32k_read NULL
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ static cycle_t notrace omap2430_32k_read(struct clocksource *cs)
+ {
+ return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
+diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
+index 3fd8b40..73d91ee 100644
+--- a/arch/arm/plat-omap/include/plat/cpu.h
++++ b/arch/arm/plat-omap/include/plat/cpu.h
+@@ -170,11 +170,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
+ # undef cpu_is_omap24xx
+ # define cpu_is_omap24xx() is_omap24xx()
+ # endif
+-# if defined (CONFIG_ARCH_OMAP2420)
++# if defined (CONFIG_SOC_OMAP2420)
+ # undef cpu_is_omap242x
+ # define cpu_is_omap242x() is_omap242x()
+ # endif
+-# if defined (CONFIG_ARCH_OMAP2430)
++# if defined (CONFIG_SOC_OMAP2430)
+ # undef cpu_is_omap243x
+ # define cpu_is_omap243x() is_omap243x()
+ # endif
+@@ -189,11 +189,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
+ # undef cpu_is_omap24xx
+ # define cpu_is_omap24xx() 1
+ # endif
+-# if defined(CONFIG_ARCH_OMAP2420)
++# if defined(CONFIG_SOC_OMAP2420)
+ # undef cpu_is_omap242x
+ # define cpu_is_omap242x() 1
+ # endif
+-# if defined(CONFIG_ARCH_OMAP2430)
++# if defined(CONFIG_SOC_OMAP2430)
+ # undef cpu_is_omap243x
+ # define cpu_is_omap243x() 1
+ # endif
+@@ -201,7 +201,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
+ # undef cpu_is_omap34xx
+ # define cpu_is_omap34xx() 1
+ # endif
+-# if defined(CONFIG_ARCH_OMAP3430)
++# if defined(CONFIG_SOC_OMAP3430)
+ # undef cpu_is_omap343x
+ # define cpu_is_omap343x() 1
+ # endif
+diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
+index ef4106c..478c5d9 100644
+--- a/arch/arm/plat-omap/include/plat/io.h
++++ b/arch/arm/plat-omap/include/plat/io.h
+@@ -259,7 +259,7 @@ struct omap_sdrc_params;
+ extern void omap1_map_common_io(void);
+ extern void omap1_init_common_hw(void);
+
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ extern void omap242x_map_common_io(void);
+ #else
+ static inline void omap242x_map_common_io(void)
+@@ -267,7 +267,7 @@ static inline void omap242x_map_common_io(void)
+ }
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ extern void omap243x_map_common_io(void);
+ #else
+ static inline void omap243x_map_common_io(void)
+diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
+index ffd909f..999ffba 100644
+--- a/arch/arm/plat-omap/include/plat/multi.h
++++ b/arch/arm/plat-omap/include/plat/multi.h
+@@ -66,7 +66,7 @@
+ # error "OMAP1 and OMAP2PLUS can't be selected at the same time"
+ # endif
+ #endif
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ # ifdef OMAP_NAME
+ # undef MULTI_OMAP2
+ # define MULTI_OMAP2
+@@ -74,7 +74,7 @@
+ # define OMAP_NAME omap2420
+ # endif
+ #endif
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ # ifdef OMAP_NAME
+ # undef MULTI_OMAP2
+ # define MULTI_OMAP2
+diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
+index e26e504..aedcb3b 100644
+--- a/arch/arm/plat-omap/sram.c
++++ b/arch/arm/plat-omap/sram.c
+@@ -312,7 +312,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
+ }
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2420
++#ifdef CONFIG_SOC_OMAP2420
+ static int __init omap242x_sram_init(void)
+ {
+ _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
+@@ -333,7 +333,7 @@ static inline int omap242x_sram_init(void)
+ }
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP2430
++#ifdef CONFIG_SOC_OMAP2430
+ static int __init omap243x_sram_init(void)
+ {
+ _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
+diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
+index afe8c6f..54f9132 100644
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -225,7 +225,7 @@ config MMC_OMAP
+
+ config MMC_OMAP_HS
+ tristate "TI OMAP High Speed Multimedia Card Interface support"
+- depends on ARCH_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4
++ depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4
+ help
+ This selects the TI OMAP High Speed Multimedia card Interface.
+ If you have an OMAP2430 or OMAP3 board or OMAP4 board with a
+diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
+index abb1ffb..f076cc5 100644
+--- a/drivers/spi/omap2_mcspi.c
++++ b/drivers/spi/omap2_mcspi.c
+@@ -1111,7 +1111,7 @@ static u8 __initdata spi2_txdma_id[] = {
+ OMAP24XX_DMA_SPI2_TX1,
+ };
+
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
+ || defined(CONFIG_ARCH_OMAP4)
+ static u8 __initdata spi3_rxdma_id[] = {
+ OMAP24XX_DMA_SPI3_RX0,
+@@ -1154,7 +1154,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ txdma_id = spi2_txdma_id;
+ num_chipselect = 2;
+ break;
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
+ || defined(CONFIG_ARCH_OMAP4)
+ case 3:
+ rxdma_id = spi3_rxdma_id;
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index c292d5c..e550f35 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -1530,7 +1530,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
+
+ /*-------------------------------------------------------------------------*/
+
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
+ defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \
+ defined(CONFIG_ARCH_U5500)
+
+diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
+index e6400be..3fb617e 100644
+--- a/drivers/usb/musb/musb_core.h
++++ b/drivers/usb/musb/musb_core.h
+@@ -212,8 +212,8 @@ enum musb_g_ep0_state {
+ * directly with the "flat" model, or after setting up an index register.
+ */
+
+-#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_ARCH_OMAP2430) \
+- || defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_BLACKFIN) \
++#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \
++ || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \
+ || defined(CONFIG_ARCH_OMAP4)
+ /* REVISIT indexed access seemed to
+ * misbehave (on DaVinci) for at least peripheral IN ...
+@@ -358,7 +358,7 @@ struct musb_csr_regs {
+
+ struct musb_context_registers {
+
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+ defined(CONFIG_ARCH_OMAP4)
+ u32 otg_sysconfig, otg_forcestandby;
+ #endif
+diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
+index 21056c9..320fd4a 100644
+--- a/drivers/usb/musb/musbhsdma.h
++++ b/drivers/usb/musb/musbhsdma.h
+@@ -31,7 +31,7 @@
+ *
+ */
+
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
+ #include "omap2430.h"
+ #endif
+
+diff --git a/drivers/w1/masters/Kconfig b/drivers/w1/masters/Kconfig
+index 80b3b12..7c608c5 100644
+--- a/drivers/w1/masters/Kconfig
++++ b/drivers/w1/masters/Kconfig
+@@ -60,7 +60,7 @@ config W1_MASTER_GPIO
+
+ config HDQ_MASTER_OMAP
+ tristate "OMAP HDQ driver"
+- depends on ARCH_OMAP2430 || ARCH_OMAP3
++ depends on SOC_OMAP2430 || ARCH_OMAP3
+ help
+ Say Y here if you want support for the 1-wire or HDQ Interface
+ on an OMAP processor.
+diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
+index d203f4d..ede6afd 100644
+--- a/sound/soc/omap/omap-mcbsp.c
++++ b/sound/soc/omap/omap-mcbsp.c
+@@ -92,7 +92,7 @@ static const unsigned long omap1_mcbsp_port[][2] = {};
+ static const int omap24xx_dma_reqs[][2] = {
+ { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
+ { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
++#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+ { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
+ { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
+ { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
+@@ -113,7 +113,7 @@ static const int omap44xx_dma_reqs[][2] = {
+ static const int omap44xx_dma_reqs[][2] = {};
+ #endif
+
+-#if defined(CONFIG_ARCH_OMAP2420)
++#if defined(CONFIG_SOC_OMAP2420)
+ static const unsigned long omap2420_mcbsp_port[][2] = {
+ { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
+ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
+@@ -124,7 +124,7 @@ static const unsigned long omap2420_mcbsp_port[][2] = {
+ static const unsigned long omap2420_mcbsp_port[][2] = {};
+ #endif
+
+-#if defined(CONFIG_ARCH_OMAP2430)
++#if defined(CONFIG_SOC_OMAP2430)
+ static const unsigned long omap2430_mcbsp_port[][2] = {
+ { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
+ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
+diff --git a/sound/soc/omap/omap-mcbsp.h b/sound/soc/omap/omap-mcbsp.h
+index 110c106..37dc721 100644
+--- a/sound/soc/omap/omap-mcbsp.h
++++ b/sound/soc/omap/omap-mcbsp.h
+@@ -43,7 +43,7 @@ enum omap_mcbsp_div {
+ OMAP_MCBSP_CLKGDV, /* Sample rate generator divider */
+ };
+
+-#if defined(CONFIG_ARCH_OMAP2420)
++#if defined(CONFIG_SOC_OMAP2420)
+ #define NUM_LINKS 2
+ #endif
+ #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
+@@ -54,7 +54,7 @@ enum omap_mcbsp_div {
+ #undef NUM_LINKS
+ #define NUM_LINKS 4
+ #endif
+-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
++#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_OMAP2430)
+ #undef NUM_LINKS
+ #define NUM_LINKS 5
+ #endif
+--
+1.7.1
+
diff --git a/patches/for_next/0002-arm-omap-i2c-fix-compile-warning.patch b/patches/for_next/0002-arm-omap-i2c-fix-compile-warning.patch
new file mode 100644
index 0000000000000000000000000000000000000000..35005ccb29aaeef59bd4eaf94d998d16252491f2
--- /dev/null
+++ b/patches/for_next/0002-arm-omap-i2c-fix-compile-warning.patch
@@ -0,0 +1,40 @@
+From 3f6fc0447e76c8e94f9e8a8f05a68c281f841ae1 Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Thu, 27 Jan 2011 16:39:41 -0800
+Subject: [PATCH 002/254] arm: omap: i2c: fix compile warning
+
+Fix the following compile warning:
+arch/arm/plat-omap/i2c.c:120:13: warning:
+'omap_pm_set_max_mpu_wakeup_lat_compat' defined but not used
+arch/arm/plat-omap/i2c.c:125:38: warning: 'omap_i2c_latency'
+defined but not used
+
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/i2c.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
+index a4f8003..3341ca4 100644
+--- a/arch/arm/plat-omap/i2c.c
++++ b/arch/arm/plat-omap/i2c.c
+@@ -112,6 +112,7 @@ static inline int omap1_i2c_add_bus(int bus_id)
+ }
+
+
++#ifdef CONFIG_ARCH_OMAP2PLUS
+ /*
+ * XXX This function is a temporary compatibility wrapper - only
+ * needed until the I2C driver can be converted to call
+@@ -130,7 +131,6 @@ static struct omap_device_pm_latency omap_i2c_latency[] = {
+ },
+ };
+
+-#ifdef CONFIG_ARCH_OMAP2PLUS
+ static inline int omap2_i2c_add_bus(int bus_id)
+ {
+ int l;
+--
+1.7.1
+
diff --git a/patches/for_next/0003-arm-omap1-fix-compile-warning.patch b/patches/for_next/0003-arm-omap1-fix-compile-warning.patch
new file mode 100644
index 0000000000000000000000000000000000000000..151063b95d948f39c71174c4bd1daaa1dcb80fff
--- /dev/null
+++ b/patches/for_next/0003-arm-omap1-fix-compile-warning.patch
@@ -0,0 +1,42 @@
+From e2109d9b9ac200cc28e5b4fa899817387c2bc5ea Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Thu, 27 Jan 2011 16:39:41 -0800
+Subject: [PATCH 003/254] arm: omap1: fix compile warning
+
+Fix the following compile warning:
+arch/arm/mach-omap1/board-palmte.c:233:13: warning:
+'palmte_headphones_detect' defined but not used
+
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-palmte.c | 13 -------------
+ 1 files changed, 0 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
+index fb51ce6..c9d38f4 100644
+--- a/arch/arm/mach-omap1/board-palmte.c
++++ b/arch/arm/mach-omap1/board-palmte.c
+@@ -230,19 +230,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
+ },
+ };
+
+-static void palmte_headphones_detect(void *data, int state)
+-{
+- if (state) {
+- /* Headphones connected, disable speaker */
+- gpio_set_value(PALMTE_SPEAKER_GPIO, 0);
+- printk(KERN_INFO "PM: speaker off\n");
+- } else {
+- /* Headphones unplugged, re-enable speaker */
+- gpio_set_value(PALMTE_SPEAKER_GPIO, 1);
+- printk(KERN_INFO "PM: speaker on\n");
+- }
+-}
+-
+ static void __init palmte_misc_gpio_setup(void)
+ {
+ /* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */
+--
+1.7.1
+
diff --git a/patches/for_next/0004-arm-omap1-fix-compile-warnings.patch b/patches/for_next/0004-arm-omap1-fix-compile-warnings.patch
new file mode 100644
index 0000000000000000000000000000000000000000..1b0821fc5fffa673904aad6d005821867c930348
--- /dev/null
+++ b/patches/for_next/0004-arm-omap1-fix-compile-warnings.patch
@@ -0,0 +1,147 @@
+From 393597fdd1b01e6bed46beeaa1fc6e0f7b1c01c6 Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Thu, 27 Jan 2011 16:39:41 -0800
+Subject: [PATCH 004/254] arm: omap1: fix compile warnings
+
+Fix the following compile warnings:
+arch/arm/mach-omap1/board-innovator.c:165:3: warning: initialization
+makes integer from pointer without a cast
+arch/arm/mach-omap1/board-perseus2.c:305:3: warning: initialization
+makes integer from pointer without a cast
+arch/arm/mach-omap1/board-fsample.c:338:3: warning: initialization makes
+integer from pointer without a cast
+
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/fpga.h | 92 ++++++++++++++++----------------
+ 1 files changed, 46 insertions(+), 46 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
+index ae39bcb..bd3c632 100644
+--- a/arch/arm/plat-omap/include/plat/fpga.h
++++ b/arch/arm/plat-omap/include/plat/fpga.h
+@@ -30,18 +30,18 @@ extern void omap1510_fpga_init_irq(void);
+ * ---------------------------------------------------------------------------
+ */
+ /* maps in the FPGA registers and the ETHR registers */
+-#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
++#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
+ #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
+ #define H2P2_DBG_FPGA_START 0x04000000 /* PA */
+
+ #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
+-#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
+-#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
+-#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
+-#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
+-#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
+-#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
+-#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
++#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
++#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
++#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
++#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
++#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
++#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
++#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
+
+ /* NOTE: most boards don't have a static mapping for the FPGA ... */
+ struct h2p2_dbg_fpga {
+@@ -81,55 +81,55 @@ struct h2p2_dbg_fpga {
+ * OMAP-1510 FPGA
+ * ---------------------------------------------------------------------------
+ */
+-#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
++#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
+ #define OMAP1510_FPGA_SIZE SZ_4K
+ #define OMAP1510_FPGA_START 0x08000000 /* PA */
+
+ /* Revision */
+-#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
+-#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
++#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
++#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
+
+-#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
+-#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
+-#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
+-#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
++#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
++#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)
++#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)
++#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
+
+ /* Interrupt status */
+-#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
+-#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
++#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
++#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
+
+ /* Interrupt mask */
+-#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
+-#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
++#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
++#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
+
+ /* Reset registers */
+-#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
+-#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
+-
+-#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
+-#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
+-#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
+-#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
+-#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
+-#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
+-#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
+-#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
+-#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
+-#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
+-
+-#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
+-
+-#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
+-#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
+-#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
+-#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
+-#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
+-#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
+-#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
+-#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
+-#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
+-#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
+-#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
++#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa)
++#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb)
++
++#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc)
++#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe)
++#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf)
++#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14)
++#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15)
++#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16)
++#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18)
++#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100)
++#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101)
++#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102)
++
++#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204)
++
++#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205)
++#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206)
++#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207)
++#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208)
++#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209)
++#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a)
++#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b)
++#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c)
++#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d)
++#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e)
++#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210)
+
+ #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
+
+--
+1.7.1
+
diff --git a/patches/for_next/0005-arm-omap1-fix-a-bunch-of-section-mismatches.patch b/patches/for_next/0005-arm-omap1-fix-a-bunch-of-section-mismatches.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b6b0e03270efeba7e7c6991ad0dcecbaedbcc081
--- /dev/null
+++ b/patches/for_next/0005-arm-omap1-fix-a-bunch-of-section-mismatches.patch
@@ -0,0 +1,151 @@
+From d46a169c37a4659f18011c045d3153870a69b0c5 Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Thu, 27 Jan 2011 16:39:42 -0800
+Subject: [PATCH 005/254] arm: omap1: fix a bunch of section mismatches
+
+Fix the following section mismatches:
+WARNING: arch/arm/mach-omap1/built-in.o(.data+0x491c): Section mismatch
+in reference from the variable fsample_config to the (unknown reference)
+.init.data:(unknown)
+The variable fsample_config references
+the (unknown reference) __initdata (unknown)
+If the reference is valid then annotate the
+variable with __init* or __refdata (see linux/init.h) or name the
+variable:
+*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
+
+WARNING: arch/arm/mach-omap1/built-in.o(.data+0x8f0c): Section mismatch
+in reference from the variable ams_delta_config to the (unknown
+reference) .init.data:(unknown)
+The variable ams_delta_config references
+the (unknown reference) __initdata (unknown)
+If the reference is valid then annotate the
+variable with __init* or __refdata (see linux/init.h) or name the
+variable:
+*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
+
+WARNING: arch/arm/mach-omap1/built-in.o(.data+0x93ac): Section mismatch
+in reference from the variable ams_delta_camera_device to the (unknown
+reference) .init.data:(unknown)
+The variable ams_delta_camera_device references
+the (unknown reference) __initdata (unknown)
+If the reference is valid then annotate the
+variable with __init* or __refdata (see linux/init.h) or name the
+variable:
+*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
+
+WARNING: vmlinux.o(.data+0x5e94): Section mismatch in reference from the
+variable fsample_config to the (unknown reference) .init.data:(unknown)
+The variable fsample_config references
+the (unknown reference) __initdata (unknown)
+If the reference is valid then annotate the
+variable with __init* or __refdata (see linux/init.h) or name the
+variable:
+*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
+
+WARNING: vmlinux.o(.data+0xa484): Section mismatch in reference from the
+variable ams_delta_config to the (unknown reference)
+.init.data:(unknown)
+The variable ams_delta_config references
+the (unknown reference) __initdata (unknown)
+If the reference is valid then annotate the
+variable with __init* or __refdata (see linux/init.h) or name the
+variable:
+*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
+
+WARNING: vmlinux.o(.data+0xa924): Section mismatch in reference from the
+variable ams_delta_camera_device to the (unknown reference)
+.init.data:(unknown)
+The variable ams_delta_camera_device references
+the (unknown reference) __initdata (unknown)
+If the reference is valid then annotate the
+variable with __init* or __refdata (see linux/init.h) or name the
+variable:
+*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
+
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-ams-delta.c | 14 +++++++-------
+ arch/arm/mach-omap1/board-fsample.c | 2 +-
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
+index 22cc8c8..2f446a2 100644
+--- a/arch/arm/mach-omap1/board-ams-delta.c
++++ b/arch/arm/mach-omap1/board-ams-delta.c
+@@ -165,7 +165,7 @@ static struct map_desc ams_delta_io_desc[] __initdata = {
+ }
+ };
+
+-static struct omap_lcd_config ams_delta_lcd_config __initdata = {
++static struct omap_lcd_config ams_delta_lcd_config = {
+ .ctrl_name = "internal",
+ };
+
+@@ -208,14 +208,14 @@ static const struct matrix_keymap_data ams_delta_keymap_data = {
+ .keymap_size = ARRAY_SIZE(ams_delta_keymap),
+ };
+
+-static struct omap_kp_platform_data ams_delta_kp_data = {
++static struct omap_kp_platform_data ams_delta_kp_data __initdata = {
+ .rows = 8,
+ .cols = 8,
+ .keymap_data = &ams_delta_keymap_data,
+ .delay = 9,
+ };
+
+-static struct platform_device ams_delta_kp_device = {
++static struct platform_device ams_delta_kp_device __initdata = {
+ .name = "omap-keypad",
+ .id = -1,
+ .dev = {
+@@ -225,12 +225,12 @@ static struct platform_device ams_delta_kp_device = {
+ .resource = ams_delta_kp_resources,
+ };
+
+-static struct platform_device ams_delta_lcd_device = {
++static struct platform_device ams_delta_lcd_device __initdata = {
+ .name = "lcd_ams_delta",
+ .id = -1,
+ };
+
+-static struct platform_device ams_delta_led_device = {
++static struct platform_device ams_delta_led_device __initdata = {
+ .name = "ams-delta-led",
+ .id = -1
+ };
+@@ -259,7 +259,7 @@ static int ams_delta_camera_power(struct device *dev, int power)
+ #define ams_delta_camera_power NULL
+ #endif
+
+-static struct soc_camera_link __initdata ams_delta_iclink = {
++static struct soc_camera_link ams_delta_iclink __initdata = {
+ .bus_id = 0, /* OMAP1 SoC camera bus */
+ .i2c_adapter_id = 1,
+ .board_info = &ams_delta_camera_board_info[0],
+@@ -267,7 +267,7 @@ static struct soc_camera_link __initdata ams_delta_iclink = {
+ .power = ams_delta_camera_power,
+ };
+
+-static struct platform_device ams_delta_camera_device = {
++static struct platform_device ams_delta_camera_device __initdata = {
+ .name = "soc-camera-pdrv",
+ .id = 0,
+ .dev = {
+diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
+index 0efb9db..27fb1be 100644
+--- a/arch/arm/mach-omap1/board-fsample.c
++++ b/arch/arm/mach-omap1/board-fsample.c
+@@ -287,7 +287,7 @@ static struct platform_device *devices[] __initdata = {
+ &lcd_device,
+ };
+
+-static struct omap_lcd_config fsample_lcd_config __initdata = {
++static struct omap_lcd_config fsample_lcd_config = {
+ .ctrl_name = "internal",
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0006-arm-omap2-irq-fix-compile-warning.patch b/patches/for_next/0006-arm-omap2-irq-fix-compile-warning.patch
new file mode 100644
index 0000000000000000000000000000000000000000..03f362f8911155634ff13d9f9604e33b8f74d16d
--- /dev/null
+++ b/patches/for_next/0006-arm-omap2-irq-fix-compile-warning.patch
@@ -0,0 +1,40 @@
+From a8911a7b395fae16c9dc73803157324b8f1e739a Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Thu, 27 Jan 2011 16:39:43 -0800
+Subject: [PATCH 006/254] arm: omap2: irq: fix compile warning:
+
+Fix the following compile warning:
+arch/arm/mach-omap2/irq.c:64:31: warning: 'intc_context' defined but not
+used
+
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/irq.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
+index 23049c4..d151aac 100644
+--- a/arch/arm/mach-omap2/irq.c
++++ b/arch/arm/mach-omap2/irq.c
+@@ -61,8 +61,6 @@ struct omap3_intc_regs {
+ u32 mir[INTCPS_NR_MIR_REGS];
+ };
+
+-static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
+-
+ /* INTC bank register get/set */
+
+ static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
+@@ -229,6 +227,8 @@ void __init omap_init_irq(void)
+ }
+
+ #ifdef CONFIG_ARCH_OMAP3
++static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
++
+ void omap_intc_save_context(void)
+ {
+ int ind = 0, i = 0;
+--
+1.7.1
+
diff --git a/patches/for_next/0007-arm-plat-omap-dma-make-omap_dma_in_1510_mode-static.patch b/patches/for_next/0007-arm-plat-omap-dma-make-omap_dma_in_1510_mode-static.patch
new file mode 100644
index 0000000000000000000000000000000000000000..97604d69dcee9deb056f296e49e24641c76f3594
--- /dev/null
+++ b/patches/for_next/0007-arm-plat-omap-dma-make-omap_dma_in_1510_mode-static.patch
@@ -0,0 +1,31 @@
+From 49502a22a6c424fdd977736599c5c57e53c60891 Mon Sep 17 00:00:00 2001
+From: Aaro Koskinen <aaro.koskinen@iki.fi>
+Date: Thu, 27 Jan 2011 16:39:43 -0800
+Subject: [PATCH 007/254] arm: plat-omap: dma: make omap_dma_in_1510_mode() static
+
+Eliminates the following sparse warning:
+
+ arch/arm/plat-omap/dma.c:137:5: warning: symbol 'omap_dma_in_1510_mode' was not declared. Should it be static?
+
+Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/dma.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
+index 8536308..2ec3b5d 100644
+--- a/arch/arm/plat-omap/dma.c
++++ b/arch/arm/plat-omap/dma.c
+@@ -134,7 +134,7 @@ static inline void omap_enable_channel_irq(int lch);
+
+ #ifdef CONFIG_ARCH_OMAP15XX
+ /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
+-int omap_dma_in_1510_mode(void)
++static int omap_dma_in_1510_mode(void)
+ {
+ return enable_1510_mode;
+ }
+--
+1.7.1
+
diff --git a/patches/for_next/0008-arm-mach-omap1-board-h2-make-h2_nand_platdata-static.patch b/patches/for_next/0008-arm-mach-omap1-board-h2-make-h2_nand_platdata-static.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2299e7d97bfc8f04fa94eb0330e44f33dc7aea00
--- /dev/null
+++ b/patches/for_next/0008-arm-mach-omap1-board-h2-make-h2_nand_platdata-static.patch
@@ -0,0 +1,31 @@
+From 34a035edd067a06d58969eddaf84bd4699b17843 Mon Sep 17 00:00:00 2001
+From: Aaro Koskinen <aaro.koskinen@iki.fi>
+Date: Thu, 27 Jan 2011 16:39:43 -0800
+Subject: [PATCH 008/254] arm: mach-omap1: board-h2: make h2_nand_platdata static
+
+Eliminates the following sparse warning:
+
+ arch/arm/mach-omap1/board-h2.c:205:27: warning: symbol 'h2_nand_platdata' was not declared. Should it be static?
+
+Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-h2.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
+index 28b84aa..ba3bd09 100644
+--- a/arch/arm/mach-omap1/board-h2.c
++++ b/arch/arm/mach-omap1/board-h2.c
+@@ -202,7 +202,7 @@ static int h2_nand_dev_ready(struct mtd_info *mtd)
+
+ static const char *h2_part_probes[] = { "cmdlinepart", NULL };
+
+-struct platform_nand_data h2_nand_platdata = {
++static struct platform_nand_data h2_nand_platdata = {
+ .chip = {
+ .nr_chips = 1,
+ .chip_offset = 0,
+--
+1.7.1
+
diff --git a/patches/for_next/0009-arm-mach-omap1-board-innovator-make-innovator_mmc_in.patch b/patches/for_next/0009-arm-mach-omap1-board-innovator-make-innovator_mmc_in.patch
new file mode 100644
index 0000000000000000000000000000000000000000..eab9cf8e2b668743005c4eec08d9018acfc4fc86
--- /dev/null
+++ b/patches/for_next/0009-arm-mach-omap1-board-innovator-make-innovator_mmc_in.patch
@@ -0,0 +1,31 @@
+From 6c33dc17b5b01f7743bc41a4a044042389d0bf71 Mon Sep 17 00:00:00 2001
+From: Aaro Koskinen <aaro.koskinen@iki.fi>
+Date: Thu, 27 Jan 2011 16:39:44 -0800
+Subject: [PATCH 009/254] arm: mach-omap1: board-innovator: make innovator_mmc_init() static
+
+Eliminates the following sparse warning:
+
+ arch/arm/mach-omap1/board-innovator.c:368:13: warning: symbol 'innovator_mmc_init' was not declared. Should it be static?
+
+Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-innovator.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
+index a36e674..2d9b8cb 100644
+--- a/arch/arm/mach-omap1/board-innovator.c
++++ b/arch/arm/mach-omap1/board-innovator.c
+@@ -365,7 +365,7 @@ static struct omap_mmc_platform_data mmc1_data = {
+
+ static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC];
+
+-void __init innovator_mmc_init(void)
++static void __init innovator_mmc_init(void)
+ {
+ mmc_data[0] = &mmc1_data;
+ omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC);
+--
+1.7.1
+
diff --git a/patches/for_next/0010-arm-mach-omap1-board-htcherald-make-htcpld_chips-and.patch b/patches/for_next/0010-arm-mach-omap1-board-htcherald-make-htcpld_chips-and.patch
new file mode 100644
index 0000000000000000000000000000000000000000..45185ee1ee33c3b7ef1ca1ca457d4c0db5cc4b6b
--- /dev/null
+++ b/patches/for_next/0010-arm-mach-omap1-board-htcherald-make-htcpld_chips-and.patch
@@ -0,0 +1,41 @@
+From 56af414647a3704fd81f27edb88b25828210fdf2 Mon Sep 17 00:00:00 2001
+From: Aaro Koskinen <aaro.koskinen@iki.fi>
+Date: Thu, 27 Jan 2011 16:39:44 -0800
+Subject: [PATCH 010/254] arm: mach-omap1: board-htcherald: make htcpld_chips and htcpld_pfdata static
+
+Eliminates the following sparse warnings:
+
+ arch/arm/mach-omap1/board-htcherald.c:334:34: warning: symbol 'htcpld_chips' was not declared. Should it be static?
+ arch/arm/mach-omap1/board-htcherald.c:369:34: warning: symbol 'htcpld_pfdata' was not declared. Should it be static?
+
+Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-htcherald.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
+index f2c5c58..ba05a51 100644
+--- a/arch/arm/mach-omap1/board-htcherald.c
++++ b/arch/arm/mach-omap1/board-htcherald.c
+@@ -331,7 +331,7 @@ static struct resource htcpld_resources[] = {
+ },
+ };
+
+-struct htcpld_chip_platform_data htcpld_chips[] = {
++static struct htcpld_chip_platform_data htcpld_chips[] = {
+ [0] = {
+ .addr = 0x03,
+ .reset = 0x04,
+@@ -366,7 +366,7 @@ struct htcpld_chip_platform_data htcpld_chips[] = {
+ },
+ };
+
+-struct htcpld_core_platform_data htcpld_pfdata = {
++static struct htcpld_core_platform_data htcpld_pfdata = {
+ .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI,
+ .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO,
+ .i2c_adapter_id = 1,
+--
+1.7.1
+
diff --git a/patches/for_next/0011-arm-mach-omap1-board-h3-make-nand_platdata-static.patch b/patches/for_next/0011-arm-mach-omap1-board-h3-make-nand_platdata-static.patch
new file mode 100644
index 0000000000000000000000000000000000000000..79900fc787ea133903a848bd3978511a92dac334
--- /dev/null
+++ b/patches/for_next/0011-arm-mach-omap1-board-h3-make-nand_platdata-static.patch
@@ -0,0 +1,31 @@
+From f0ad0d07908b85ffc714647ba5d64d03b77759ec Mon Sep 17 00:00:00 2001
+From: Aaro Koskinen <aaro.koskinen@iki.fi>
+Date: Thu, 27 Jan 2011 16:39:44 -0800
+Subject: [PATCH 011/254] arm: mach-omap1: board-h3: make nand_platdata static
+
+Eliminates the following sparse warning:
+
+ arch/arm/mach-omap1/board-h3.c:207:27: warning: symbol 'nand_platdata' was not declared. Should it be static?
+
+Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-h3.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
+index dbc8b8d..ac48677 100644
+--- a/arch/arm/mach-omap1/board-h3.c
++++ b/arch/arm/mach-omap1/board-h3.c
+@@ -204,7 +204,7 @@ static int nand_dev_ready(struct mtd_info *mtd)
+
+ static const char *part_probes[] = { "cmdlinepart", NULL };
+
+-struct platform_nand_data nand_platdata = {
++static struct platform_nand_data nand_platdata = {
+ .chip = {
+ .nr_chips = 1,
+ .chip_offset = 0,
+--
+1.7.1
+
diff --git a/patches/for_next/0012-ARM-OMAP-Allow-platforms-to-hook-reset-cleanly.patch b/patches/for_next/0012-ARM-OMAP-Allow-platforms-to-hook-reset-cleanly.patch
new file mode 100644
index 0000000000000000000000000000000000000000..743c8a7bf931423aa7743a206a5997c1a0ddd77d
--- /dev/null
+++ b/patches/for_next/0012-ARM-OMAP-Allow-platforms-to-hook-reset-cleanly.patch
@@ -0,0 +1,303 @@
+From d8dc122867e4bc760c9b17ae97eaed994bee5790 Mon Sep 17 00:00:00 2001
+From: Russell King - ARM Linux <linux@arm.linux.org.uk>
+Date: Thu, 27 Jan 2011 16:39:45 -0800
+Subject: [PATCH 012/254] ARM: OMAP: Allow platforms to hook reset cleanly
+
+This adds a clean method to allow platforms to hook into the reset
+code if they require to.
+
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/Makefile | 2 +-
+ arch/arm/mach-omap1/board-voiceblue.c | 106 +++++++++++++++++-------------
+ arch/arm/mach-omap1/reset.c | 25 +++++++
+ arch/arm/mach-omap2/prcm.c | 5 +-
+ arch/arm/plat-omap/include/plat/prcm.h | 1 -
+ arch/arm/plat-omap/include/plat/system.h | 38 +----------
+ 6 files changed, 91 insertions(+), 86 deletions(-)
+ create mode 100644 arch/arm/mach-omap1/reset.c
+
+diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
+index ba6009f..af98117 100644
+--- a/arch/arm/mach-omap1/Makefile
++++ b/arch/arm/mach-omap1/Makefile
+@@ -4,7 +4,7 @@
+
+ # Common support
+ obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
+-obj-y += clock.o clock_data.o opp_data.o
++obj-y += clock.o clock_data.o opp_data.o reset.o
+
+ obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+
+diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
+index 815a69c..6712817 100644
+--- a/arch/arm/mach-omap1/board-voiceblue.c
++++ b/arch/arm/mach-omap1/board-voiceblue.c
+@@ -26,6 +26,7 @@
+ #include <linux/smc91x.h>
+
+ #include <mach/hardware.h>
++#include <mach/system.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+@@ -163,52 +164,6 @@ static void __init voiceblue_init_irq(void)
+ omap_init_irq();
+ }
+
+-static void __init voiceblue_init(void)
+-{
+- /* mux pins for uarts */
+- omap_cfg_reg(UART1_TX);
+- omap_cfg_reg(UART1_RTS);
+- omap_cfg_reg(UART2_TX);
+- omap_cfg_reg(UART2_RTS);
+- omap_cfg_reg(UART3_TX);
+- omap_cfg_reg(UART3_RX);
+-
+- /* Watchdog */
+- gpio_request(0, "Watchdog");
+- /* smc91x reset */
+- gpio_request(7, "SMC91x reset");
+- gpio_direction_output(7, 1);
+- udelay(2); /* wait at least 100ns */
+- gpio_set_value(7, 0);
+- mdelay(50); /* 50ms until PHY ready */
+- /* smc91x interrupt pin */
+- gpio_request(8, "SMC91x irq");
+- /* 16C554 reset*/
+- gpio_request(6, "16C554 reset");
+- gpio_direction_output(6, 0);
+- /* 16C554 interrupt pins */
+- gpio_request(12, "16C554 irq");
+- gpio_request(13, "16C554 irq");
+- gpio_request(14, "16C554 irq");
+- gpio_request(15, "16C554 irq");
+- set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
+- set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
+- set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
+- set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
+-
+- platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
+- omap_board_config = voiceblue_config;
+- omap_board_config_size = ARRAY_SIZE(voiceblue_config);
+- omap_serial_init();
+- omap1_usb_init(&voiceblue_usb_config);
+- omap_register_i2c_bus(1, 100, NULL, 0);
+-
+- /* There is a good chance board is going up, so enable power LED
+- * (it is connected through invertor) */
+- omap_writeb(0x00, OMAP_LPG1_LCR);
+- omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
+-}
+-
+ static void __init voiceblue_map_io(void)
+ {
+ omap1_map_common_io();
+@@ -275,8 +230,17 @@ void voiceblue_wdt_ping(void)
+ gpio_set_value(0, wdt_gpio_state);
+ }
+
+-void voiceblue_reset(void)
++static void voiceblue_reset(char mode, const char *cmd)
+ {
++ /*
++ * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
++ * "Global Software Reset Affects Traffic Controller Frequency".
++ */
++ if (cpu_is_omap5912()) {
++ omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
++ omap_writew(0x8, ARM_RSTCT1);
++ }
++
+ set_bit(MACHINE_REBOOT, &machine_state);
+ voiceblue_wdt_enable();
+ while (1) ;
+@@ -286,6 +250,54 @@ EXPORT_SYMBOL(voiceblue_wdt_enable);
+ EXPORT_SYMBOL(voiceblue_wdt_disable);
+ EXPORT_SYMBOL(voiceblue_wdt_ping);
+
++static void __init voiceblue_init(void)
++{
++ /* mux pins for uarts */
++ omap_cfg_reg(UART1_TX);
++ omap_cfg_reg(UART1_RTS);
++ omap_cfg_reg(UART2_TX);
++ omap_cfg_reg(UART2_RTS);
++ omap_cfg_reg(UART3_TX);
++ omap_cfg_reg(UART3_RX);
++
++ /* Watchdog */
++ gpio_request(0, "Watchdog");
++ /* smc91x reset */
++ gpio_request(7, "SMC91x reset");
++ gpio_direction_output(7, 1);
++ udelay(2); /* wait at least 100ns */
++ gpio_set_value(7, 0);
++ mdelay(50); /* 50ms until PHY ready */
++ /* smc91x interrupt pin */
++ gpio_request(8, "SMC91x irq");
++ /* 16C554 reset*/
++ gpio_request(6, "16C554 reset");
++ gpio_direction_output(6, 0);
++ /* 16C554 interrupt pins */
++ gpio_request(12, "16C554 irq");
++ gpio_request(13, "16C554 irq");
++ gpio_request(14, "16C554 irq");
++ gpio_request(15, "16C554 irq");
++ set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
++ set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
++ set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
++ set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
++
++ platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
++ omap_board_config = voiceblue_config;
++ omap_board_config_size = ARRAY_SIZE(voiceblue_config);
++ omap_serial_init();
++ omap1_usb_init(&voiceblue_usb_config);
++ omap_register_i2c_bus(1, 100, NULL, 0);
++
++ /* There is a good chance board is going up, so enable power LED
++ * (it is connected through invertor) */
++ omap_writeb(0x00, OMAP_LPG1_LCR);
++ omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
++
++ arch_reset = voiceblue_reset;
++}
++
+ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
+ /* Maintainer: Ladislav Michl <michl@2n.cz> */
+ .boot_params = 0x10000100,
+diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
+new file mode 100644
+index 0000000..ad951ee
+--- /dev/null
++++ b/arch/arm/mach-omap1/reset.c
+@@ -0,0 +1,25 @@
++/*
++ * OMAP1 reset support
++ */
++#include <linux/kernel.h>
++#include <linux/io.h>
++
++#include <mach/hardware.h>
++#include <mach/system.h>
++#include <plat/prcm.h>
++
++void omap1_arch_reset(char mode, const char *cmd)
++{
++ /*
++ * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
++ * "Global Software Reset Affects Traffic Controller Frequency".
++ */
++ if (cpu_is_omap5912()) {
++ omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
++ omap_writew(0x8, ARM_RSTCT1);
++ }
++
++ omap_writew(1, ARM_RSTCT1);
++}
++
++void (*arch_reset)(char, const char *) = omap1_arch_reset;
+diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
+index 679bcd2..6be1438 100644
+--- a/arch/arm/mach-omap2/prcm.c
++++ b/arch/arm/mach-omap2/prcm.c
+@@ -24,6 +24,7 @@
+ #include <linux/io.h>
+ #include <linux/delay.h>
+
++#include <mach/system.h>
+ #include <plat/common.h>
+ #include <plat/prcm.h>
+ #include <plat/irqs.h>
+@@ -57,7 +58,7 @@ u32 omap_prcm_get_reset_sources(void)
+ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
+
+ /* Resets clock rates and reboots the system. Only called from system.h */
+-void omap_prcm_arch_reset(char mode, const char *cmd)
++static void omap_prcm_arch_reset(char mode, const char *cmd)
+ {
+ s16 prcm_offs = 0;
+
+@@ -108,6 +109,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
+ omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
+ }
+
++void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
++
+ /**
+ * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
+ * @reg: physical address of module IDLEST register
+diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
+index 2fdf8c8..267f43b 100644
+--- a/arch/arm/plat-omap/include/plat/prcm.h
++++ b/arch/arm/plat-omap/include/plat/prcm.h
+@@ -28,7 +28,6 @@
+ #define __ASM_ARM_ARCH_OMAP_PRCM_H
+
+ u32 omap_prcm_get_reset_sources(void);
+-void omap_prcm_arch_reset(char mode, const char *cmd);
+ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
+ const char *name);
+
+diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
+index d0a119f..c5fa9e9 100644
+--- a/arch/arm/plat-omap/include/plat/system.h
++++ b/arch/arm/plat-omap/include/plat/system.h
+@@ -4,48 +4,14 @@
+ */
+ #ifndef __ASM_ARCH_SYSTEM_H
+ #define __ASM_ARCH_SYSTEM_H
+-#include <linux/clk.h>
+
+-#include <asm/mach-types.h>
+-#include <mach/hardware.h>
+-
+-#include <plat/prcm.h>
+-
+-#ifndef CONFIG_MACH_VOICEBLUE
+-#define voiceblue_reset() do {} while (0)
+-#else
+-extern void voiceblue_reset(void);
+-#endif
++#include <asm/proc-fns.h>
+
+ static inline void arch_idle(void)
+ {
+ cpu_do_idle();
+ }
+
+-static inline void omap1_arch_reset(char mode, const char *cmd)
+-{
+- /*
+- * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
+- * "Global Software Reset Affects Traffic Controller Frequency".
+- */
+- if (cpu_is_omap5912()) {
+- omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
+- DPLL_CTL);
+- omap_writew(0x8, ARM_RSTCT1);
+- }
+-
+- if (machine_is_voiceblue())
+- voiceblue_reset();
+- else
+- omap_writew(1, ARM_RSTCT1);
+-}
+-
+-static inline void arch_reset(char mode, const char *cmd)
+-{
+- if (!cpu_class_is_omap2())
+- omap1_arch_reset(mode, cmd);
+- else
+- omap_prcm_arch_reset(mode, cmd);
+-}
++extern void (*arch_reset)(char, const char *);
+
+ #endif
+--
+1.7.1
+
diff --git a/patches/for_next/0013-arm-mach-omap1-board-voiceblue-add-missing-include.patch b/patches/for_next/0013-arm-mach-omap1-board-voiceblue-add-missing-include.patch
new file mode 100644
index 0000000000000000000000000000000000000000..56311eeb3376d3058396c32645b059e19fb19319
--- /dev/null
+++ b/patches/for_next/0013-arm-mach-omap1-board-voiceblue-add-missing-include.patch
@@ -0,0 +1,33 @@
+From 33b57178e4f2f3356bf50bcfc1e2fc1e958dd64c Mon Sep 17 00:00:00 2001
+From: Aaro Koskinen <aaro.koskinen@iki.fi>
+Date: Thu, 27 Jan 2011 16:39:45 -0800
+Subject: [PATCH 013/254] arm: mach-omap1: board-voiceblue: add missing include
+
+Eliminates the following sparse warnings:
+
+ arch/arm/mach-omap1/board-voiceblue.c:253:6: warning: symbol 'voiceblue_wdt_enable' was not declared. Should it be static?
+ arch/arm/mach-omap1/board-voiceblue.c:261:6: warning: symbol 'voiceblue_wdt_disable' was not declared. Should it be static?
+ arch/arm/mach-omap1/board-voiceblue.c:269:6: warning: symbol 'voiceblue_wdt_ping' was not declared. Should it be static?
+ arch/arm/mach-omap1/board-voiceblue.c:278:6: warning: symbol 'voiceblue_reset' was not declared. Should it be static?
+
+Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-voiceblue.c | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
+index 6712817..bdc0ac8 100644
+--- a/arch/arm/mach-omap1/board-voiceblue.c
++++ b/arch/arm/mach-omap1/board-voiceblue.c
+@@ -31,6 +31,7 @@
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+
++#include <plat/board-voiceblue.h>
+ #include <plat/common.h>
+ #include <mach/gpio.h>
+ #include <plat/flash.h>
+--
+1.7.1
+
diff --git a/patches/for_next/0014-ARM-omap1-nokia770-mark-some-functions-__init.patch b/patches/for_next/0014-ARM-omap1-nokia770-mark-some-functions-__init.patch
new file mode 100644
index 0000000000000000000000000000000000000000..59c72196b647320586df01425aa8de090d2a6bac
--- /dev/null
+++ b/patches/for_next/0014-ARM-omap1-nokia770-mark-some-functions-__init.patch
@@ -0,0 +1,50 @@
+From 6a80aec5d5ec32289a3a726cfa0c6a2d628fcfba Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 9 Feb 2011 21:40:07 +0100
+Subject: [PATCH 014/254] ARM: omap1/nokia770: mark some functions __init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These are only called from omap_nokia770_init which is in .init.text, too.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-nokia770.c | 6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
+index d21f09d..cfd0849 100644
+--- a/arch/arm/mach-omap1/board-nokia770.c
++++ b/arch/arm/mach-omap1/board-nokia770.c
+@@ -115,7 +115,7 @@ static struct mipid_platform_data nokia770_mipid_platform_data = {
+ .shutdown = mipid_shutdown,
+ };
+
+-static void mipid_dev_init(void)
++static void __init mipid_dev_init(void)
+ {
+ const struct omap_lcd_config *conf;
+
+@@ -126,7 +126,7 @@ static void mipid_dev_init(void)
+ }
+ }
+
+-static void ads7846_dev_init(void)
++static void __init ads7846_dev_init(void)
+ {
+ if (gpio_request(ADS7846_PENDOWN_GPIO, "ADS7846 pendown") < 0)
+ printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
+@@ -170,7 +170,7 @@ static struct hwa742_platform_data nokia770_hwa742_platform_data = {
+ .te_connected = 1,
+ };
+
+-static void hwa742_dev_init(void)
++static void __init hwa742_dev_init(void)
+ {
+ clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
+ omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);
+--
+1.7.1
+
diff --git a/patches/for_next/0015-ARM-omap-move-omap_get_config-et-al.-to-.init.text.patch b/patches/for_next/0015-ARM-omap-move-omap_get_config-et-al.-to-.init.text.patch
new file mode 100644
index 0000000000000000000000000000000000000000..dbb9c24e5c261ac546c6f6f381a1238bb7e37321
--- /dev/null
+++ b/patches/for_next/0015-ARM-omap-move-omap_get_config-et-al.-to-.init.text.patch
@@ -0,0 +1,67 @@
+From ba22bbc3ced4249f18e0c133a40a2e0957acebe3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 9 Feb 2011 21:40:08 +0100
+Subject: [PATCH 015/254] ARM: omap: move omap_get_config et al. to .init.text
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+All callers of these functions live in .init.text, so these can go there,
+too. There they must not be exported anymore, this is no problem though,
+as all callers are always built-in.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/common.c | 6 ++----
+ arch/arm/plat-omap/include/plat/board.h | 4 ++--
+ 2 files changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
+index f047318..30c698e 100644
+--- a/arch/arm/plat-omap/common.c
++++ b/arch/arm/plat-omap/common.c
+@@ -49,17 +49,15 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
+ return kinfo->data;
+ }
+
+-const void *__omap_get_config(u16 tag, size_t len, int nr)
++const void *__init __omap_get_config(u16 tag, size_t len, int nr)
+ {
+ return get_config(tag, len, nr, NULL);
+ }
+-EXPORT_SYMBOL(__omap_get_config);
+
+-const void *omap_get_var_config(u16 tag, size_t *len)
++const void *__init omap_get_var_config(u16 tag, size_t *len)
+ {
+ return get_config(tag, NO_LENGTH_CHECK, 0, len);
+ }
+-EXPORT_SYMBOL(omap_get_var_config);
+
+ void __init omap_reserve(void)
+ {
+diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
+index 3cf4fa2..97126df 100644
+--- a/arch/arm/plat-omap/include/plat/board.h
++++ b/arch/arm/plat-omap/include/plat/board.h
+@@ -151,14 +151,14 @@ struct omap_board_config_kernel {
+ const void *data;
+ };
+
+-extern const void *__omap_get_config(u16 tag, size_t len, int nr);
++extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
+
+ #define omap_get_config(tag, type) \
+ ((const type *) __omap_get_config((tag), sizeof(type), 0))
+ #define omap_get_nr_config(tag, type, nr) \
+ ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
+
+-extern const void *omap_get_var_config(u16 tag, size_t *len);
++extern const void *__init omap_get_var_config(u16 tag, size_t *len);
+
+ extern struct omap_board_config_kernel *omap_board_config;
+ extern int omap_board_config_size;
+--
+1.7.1
+
diff --git a/patches/for_next/0016-ARM-omap-move-omap_board_config_kernel-to-.init.data.patch b/patches/for_next/0016-ARM-omap-move-omap_board_config_kernel-to-.init.data.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9fb38e2932f1cf35294f89575c844f6888f9ca15
--- /dev/null
+++ b/patches/for_next/0016-ARM-omap-move-omap_board_config_kernel-to-.init.data.patch
@@ -0,0 +1,37 @@
+From bda99544c81416fa7abdfaf1c62488c03846b78c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 9 Feb 2011 21:40:09 +0100
+Subject: [PATCH 016/254] ARM: omap: move omap_board_config_kernel to .init.data
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This variable is only assigned in __init functions and never used later.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/common.c | 5 +++--
+ 1 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
+index 30c698e..d9f10a3 100644
+--- a/arch/arm/plat-omap/common.c
++++ b/arch/arm/plat-omap/common.c
+@@ -24,10 +24,11 @@
+
+ #define NO_LENGTH_CHECK 0xffffffff
+
+-struct omap_board_config_kernel *omap_board_config;
++struct omap_board_config_kernel *omap_board_config __initdata;
+ int omap_board_config_size;
+
+-static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
++static const void *__init get_config(u16 tag, size_t len,
++ int skip, size_t *len_out)
+ {
+ struct omap_board_config_kernel *kinfo = NULL;
+ int i;
+--
+1.7.1
+
diff --git a/patches/for_next/0017-wip-fix-section-mismatches-in-omap1_defconfig.patch b/patches/for_next/0017-wip-fix-section-mismatches-in-omap1_defconfig.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e3b9be5b9741f1ecb05453915b835308302ed52c
--- /dev/null
+++ b/patches/for_next/0017-wip-fix-section-mismatches-in-omap1_defconfig.patch
@@ -0,0 +1,71 @@
+From 95bd7c7e2102d7d3cd8abb089c2c64a74219fee1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Wed, 9 Feb 2011 21:40:10 +0100
+Subject: [PATCH 017/254] wip: fix section mismatches in omap1_defconfig
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+after these changes omap1_defconfig and omap2plus_defconfig don't have any
+section mismatches any more, making it plausible that the patches earlier
+in this series are OK.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/board-ams-delta.c | 4 ++--
+ arch/arm/mach-omap1/board-fsample.c | 2 +-
+ drivers/usb/otg/isp1301_omap.c | 2 +-
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
+index 2f446a2..de88c92 100644
+--- a/arch/arm/mach-omap1/board-ams-delta.c
++++ b/arch/arm/mach-omap1/board-ams-delta.c
+@@ -175,7 +175,7 @@ static struct omap_usb_config ams_delta_usb_config __initdata = {
+ .pins[0] = 2,
+ };
+
+-static struct omap_board_config_kernel ams_delta_config[] = {
++static struct omap_board_config_kernel ams_delta_config[] __initdata = {
+ { OMAP_TAG_LCD, &ams_delta_lcd_config },
+ };
+
+@@ -259,7 +259,7 @@ static int ams_delta_camera_power(struct device *dev, int power)
+ #define ams_delta_camera_power NULL
+ #endif
+
+-static struct soc_camera_link ams_delta_iclink __initdata = {
++static struct soc_camera_link ams_delta_iclink = {
+ .bus_id = 0, /* OMAP1 SoC camera bus */
+ .i2c_adapter_id = 1,
+ .board_info = &ams_delta_camera_board_info[0],
+diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
+index 27fb1be..87f173d 100644
+--- a/arch/arm/mach-omap1/board-fsample.c
++++ b/arch/arm/mach-omap1/board-fsample.c
+@@ -291,7 +291,7 @@ static struct omap_lcd_config fsample_lcd_config = {
+ .ctrl_name = "internal",
+ };
+
+-static struct omap_board_config_kernel fsample_config[] = {
++static struct omap_board_config_kernel fsample_config[] __initdata = {
+ { OMAP_TAG_LCD, &fsample_lcd_config },
+ };
+
+diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
+index e00fa1b..8c6fdef 100644
+--- a/drivers/usb/otg/isp1301_omap.c
++++ b/drivers/usb/otg/isp1301_omap.c
+@@ -1510,7 +1510,7 @@ isp1301_start_hnp(struct otg_transceiver *dev)
+
+ /*-------------------------------------------------------------------------*/
+
+-static int __init
++static int __devinit
+ isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+ {
+ int status;
+--
+1.7.1
+
diff --git a/patches/for_next/0018-omap-McBSP-Remove-unused-audio-macros-in-mcbsp.h.patch b/patches/for_next/0018-omap-McBSP-Remove-unused-audio-macros-in-mcbsp.h.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5890c265b3bab21ed68979b0be3c6ef6a7ac7d94
--- /dev/null
+++ b/patches/for_next/0018-omap-McBSP-Remove-unused-audio-macros-in-mcbsp.h.patch
@@ -0,0 +1,54 @@
+From 6bddaabddbe485669304850b3ae25e24ae987a58 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Fri, 4 Feb 2011 09:15:09 +0000
+Subject: [PATCH 018/254] omap: McBSP: Remove unused audio macros in mcbsp.h
+
+Some macros defined in mcbsp.h related to audio, which are never being used
+is removed.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Reviewed-by: Charulatha V <charu@ti.com>
+Cc: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: G, Manjunath Kondaiah <manjugk@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/mcbsp.h | 14 --------------
+ 1 files changed, 0 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index b87d83c..6ecf105 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -106,13 +106,6 @@ static struct platform_device omap_mcbsp##port_nr = { \
+ #define OMAP_MCBSP_REG_XCCR 0x00
+ #define OMAP_MCBSP_REG_RCCR 0x00
+
+-#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
+-#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
+-
+-#define AUDIO_MCBSP OMAP_MCBSP1
+-#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
+-#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
+-
+ #else
+
+ #define OMAP_MCBSP_REG_DRR2 0x00
+@@ -168,13 +161,6 @@ static struct platform_device omap_mcbsp##port_nr = { \
+ #define OMAP_ST_REG_SFIRCR 0x28
+ #define OMAP_ST_REG_SSELCR 0x2C
+
+-#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
+-#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
+-
+-#define AUDIO_MCBSP OMAP_MCBSP2
+-#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
+-#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
+-
+ #endif
+
+ /************************** McBSP SPCR1 bit definitions ***********************/
+--
+1.7.1
+
diff --git a/patches/for_next/0019-ARM-OMAP2-use-early-init-hook.patch b/patches/for_next/0019-ARM-OMAP2-use-early-init-hook.patch
new file mode 100644
index 0000000000000000000000000000000000000000..fbf89a3f3271835f8051a54ca11fa1040b02f0ce
--- /dev/null
+++ b/patches/for_next/0019-ARM-OMAP2-use-early-init-hook.patch
@@ -0,0 +1,952 @@
+From 34ccdd6b3a0f5d131ae2acbe83f5688436f553a4 Mon Sep 17 00:00:00 2001
+From: Russell King - ARM Linux <linux@arm.linux.org.uk>
+Date: Mon, 14 Feb 2011 15:40:20 -0800
+Subject: [PATCH 019/254] ARM: OMAP2: use early init hook
+
+Move non-mapping and non-irq initialization code out of .map_io and
+.init_irq respectively into the new init_early hook.
+
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-2430sdp.c | 8 ++++----
+ arch/arm/mach-omap2/board-3430sdp.c | 8 ++++----
+ arch/arm/mach-omap2/board-3630sdp.c | 8 ++++----
+ arch/arm/mach-omap2/board-4430sdp.c | 8 ++++----
+ arch/arm/mach-omap2/board-am3517crane.c | 8 ++++----
+ arch/arm/mach-omap2/board-am3517evm.c | 8 ++++----
+ arch/arm/mach-omap2/board-apollon.c | 8 ++++----
+ arch/arm/mach-omap2/board-cm-t35.c | 8 ++++----
+ arch/arm/mach-omap2/board-cm-t3517.c | 8 ++++----
+ arch/arm/mach-omap2/board-devkit8000.c | 9 +++++++--
+ arch/arm/mach-omap2/board-generic.c | 8 ++++----
+ arch/arm/mach-omap2/board-h4.c | 9 +++++++--
+ arch/arm/mach-omap2/board-igep0020.c | 8 ++++----
+ arch/arm/mach-omap2/board-igep0030.c | 6 +++---
+ arch/arm/mach-omap2/board-ldp.c | 8 ++++----
+ arch/arm/mach-omap2/board-n8x0.c | 18 ++++++++++--------
+ arch/arm/mach-omap2/board-omap3beagle.c | 9 +++++++--
+ arch/arm/mach-omap2/board-omap3evm.c | 8 ++++----
+ arch/arm/mach-omap2/board-omap3logic.c | 9 +++++----
+ arch/arm/mach-omap2/board-omap3pandora.c | 8 ++++----
+ arch/arm/mach-omap2/board-omap3stalker.c | 7 ++++++-
+ arch/arm/mach-omap2/board-omap3touchbook.c | 9 +++++++--
+ arch/arm/mach-omap2/board-omap4panda.c | 6 +++---
+ arch/arm/mach-omap2/board-overo.c | 8 ++++----
+ arch/arm/mach-omap2/board-rm680.c | 8 ++++----
+ arch/arm/mach-omap2/board-rx51.c | 8 ++++----
+ arch/arm/mach-omap2/board-zoom.c | 14 +++++++-------
+ 27 files changed, 130 insertions(+), 102 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
+index e066177..ec74c0f 100644
+--- a/arch/arm/mach-omap2/board-2430sdp.c
++++ b/arch/arm/mach-omap2/board-2430sdp.c
+@@ -139,13 +139,12 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
+ {OMAP_TAG_LCD, &sdp2430_lcd_config},
+ };
+
+-static void __init omap_2430sdp_init_irq(void)
++static void __init omap_2430sdp_init_early(void)
+ {
+ omap_board_config = sdp2430_config;
+ omap_board_config_size = ARRAY_SIZE(sdp2430_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
+@@ -253,9 +252,10 @@ static void __init omap_2430sdp_map_io(void)
+ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
+ /* Maintainer: Syed Khasim - Texas Instruments Inc */
+ .boot_params = 0x80000100,
+- .map_io = omap_2430sdp_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_2430sdp_init_irq,
++ .map_io = omap_2430sdp_map_io,
++ .init_early = omap_2430sdp_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap_2430sdp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index d4e41ef..3108588 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -327,14 +327,13 @@ static struct platform_device *sdp3430_devices[] __initdata = {
+ static struct omap_board_config_kernel sdp3430_config[] __initdata = {
+ };
+
+-static void __init omap_3430sdp_init_irq(void)
++static void __init omap_3430sdp_init_early(void)
+ {
+ omap_board_config = sdp3430_config;
+ omap_board_config_size = ARRAY_SIZE(sdp3430_config);
+ omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
+- omap_init_irq();
+ }
+
+ static int sdp3430_batt_table[] = {
+@@ -822,9 +821,10 @@ static void __init omap_3430sdp_init(void)
+ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
+ /* Maintainer: Syed Khasim - Texas Instruments Inc */
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_3430sdp_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = omap_3430sdp_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap_3430sdp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
+index 6264564..1653875 100644
+--- a/arch/arm/mach-omap2/board-3630sdp.c
++++ b/arch/arm/mach-omap2/board-3630sdp.c
+@@ -69,14 +69,13 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+ static struct omap_board_config_kernel sdp_config[] __initdata = {
+ };
+
+-static void __init omap_sdp_init_irq(void)
++static void __init omap_sdp_init_early(void)
+ {
+ omap_board_config = sdp_config;
+ omap_board_config_size = ARRAY_SIZE(sdp_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
+ h8mbx00u0mer0em_sdrc_params);
+- omap_init_irq();
+ }
+
+ #ifdef CONFIG_OMAP_MUX
+@@ -216,9 +215,10 @@ static void __init omap_sdp_init(void)
+
+ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_sdp_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = omap_sdp_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap_sdp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index 07d1b20..12d99e5 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -239,7 +239,7 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
+ { OMAP_TAG_LCD, &sdp4430_lcd_config },
+ };
+
+-static void __init omap_4430sdp_init_irq(void)
++static void __init omap_4430sdp_init_early(void)
+ {
+ omap_board_config = sdp4430_config;
+ omap_board_config_size = ARRAY_SIZE(sdp4430_config);
+@@ -248,7 +248,6 @@ static void __init omap_4430sdp_init_irq(void)
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(1);
+ #endif
+- gic_init_irq();
+ }
+
+ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+@@ -605,9 +604,10 @@ static void __init omap_4430sdp_map_io(void)
+ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
+ /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
+ .boot_params = 0x80000100,
+- .map_io = omap_4430sdp_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_4430sdp_init_irq,
++ .map_io = omap_4430sdp_map_io,
++ .init_early = omap_4430sdp_init_early,
++ .init_irq = gic_init_irq,
+ .init_machine = omap_4430sdp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
+index 71acb5a..ae3a83d 100644
+--- a/arch/arm/mach-omap2/board-am3517crane.c
++++ b/arch/arm/mach-omap2/board-am3517crane.c
+@@ -49,14 +49,13 @@ static struct omap_board_mux board_mux[] __initdata = {
+ #define board_mux NULL
+ #endif
+
+-static void __init am3517_crane_init_irq(void)
++static void __init am3517_crane_init_early(void)
+ {
+ omap_board_config = am3517_crane_config;
+ omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
+
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
+@@ -108,9 +107,10 @@ static void __init am3517_crane_init(void)
+
+ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = am3517_crane_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = am3517_crane_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = am3517_crane_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
+index 10d60b7..d0d0f55 100644
+--- a/arch/arm/mach-omap2/board-am3517evm.c
++++ b/arch/arm/mach-omap2/board-am3517evm.c
+@@ -396,13 +396,12 @@ static struct platform_device *am3517_evm_devices[] __initdata = {
+ &am3517_evm_dss_device,
+ };
+
+-static void __init am3517_evm_init_irq(void)
++static void __init am3517_evm_init_early(void)
+ {
+ omap_board_config = am3517_evm_config;
+ omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ static struct omap_musb_board_data musb_board_data = {
+@@ -521,9 +520,10 @@ static void __init am3517_evm_init(void)
+
+ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = am3517_evm_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = am3517_evm_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = am3517_evm_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
+index 9f55b68..4ef4aad 100644
+--- a/arch/arm/mach-omap2/board-apollon.c
++++ b/arch/arm/mach-omap2/board-apollon.c
+@@ -274,13 +274,12 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
+ { OMAP_TAG_LCD, &apollon_lcd_config },
+ };
+
+-static void __init omap_apollon_init_irq(void)
++static void __init omap_apollon_init_early(void)
+ {
+ omap_board_config = apollon_config;
+ omap_board_config_size = ARRAY_SIZE(apollon_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ static void __init apollon_led_init(void)
+@@ -355,9 +354,10 @@ static void __init omap_apollon_map_io(void)
+ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
+ /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
+ .boot_params = 0x80000100,
+- .map_io = omap_apollon_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_apollon_init_irq,
++ .map_io = omap_apollon_map_io,
++ .init_early = omap_apollon_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap_apollon_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index dac1416..9e4de92 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -683,7 +683,7 @@ static void __init cm_t35_init_i2c(void)
+ static struct omap_board_config_kernel cm_t35_config[] __initdata = {
+ };
+
+-static void __init cm_t35_init_irq(void)
++static void __init cm_t35_init_early(void)
+ {
+ omap_board_config = cm_t35_config;
+ omap_board_config_size = ARRAY_SIZE(cm_t35_config);
+@@ -691,7 +691,6 @@ static void __init cm_t35_init_irq(void)
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
+- omap_init_irq();
+ }
+
+ static struct omap_board_mux board_mux[] __initdata = {
+@@ -815,9 +814,10 @@ static void __init cm_t35_init(void)
+
+ MACHINE_START(CM_T35, "Compulab CM-T35")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = cm_t35_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = cm_t35_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = cm_t35_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
+index 8f9a64d..38bef6d 100644
+--- a/arch/arm/mach-omap2/board-cm-t3517.c
++++ b/arch/arm/mach-omap2/board-cm-t3517.c
+@@ -254,14 +254,13 @@ static inline void cm_t3517_init_nand(void) {}
+ static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
+ };
+
+-static void __init cm_t3517_init_irq(void)
++static void __init cm_t3517_init_early(void)
+ {
+ omap_board_config = cm_t3517_config;
+ omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
+
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ static struct omap_board_mux board_mux[] __initdata = {
+@@ -303,9 +302,10 @@ static void __init cm_t3517_init(void)
+
+ MACHINE_START(CM_T3517, "Compulab CM-T3517")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = cm_t3517_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = cm_t3517_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = cm_t3517_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index 9a2a31e..af74288 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -456,11 +456,15 @@ static struct platform_device keys_gpio = {
+ };
+
+
+-static void __init devkit8000_init_irq(void)
++static void __init devkit8000_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
++}
++
++static void __init devkit8000_init_irq(void)
++{
+ omap_init_irq();
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+@@ -813,8 +817,9 @@ static void __init devkit8000_init(void)
+
+ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
++ .map_io = omap3_map_io,
++ .init_early = devkit8000_init_early,
+ .init_irq = devkit8000_init_irq,
+ .init_machine = devkit8000_init,
+ .timer = &omap_timer,
+diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
+index 0e3d81e..682da92 100644
+--- a/arch/arm/mach-omap2/board-generic.c
++++ b/arch/arm/mach-omap2/board-generic.c
+@@ -33,13 +33,12 @@
+ static struct omap_board_config_kernel generic_config[] = {
+ };
+
+-static void __init omap_generic_init_irq(void)
++static void __init omap_generic_init_early(void)
+ {
+ omap_board_config = generic_config;
+ omap_board_config_size = ARRAY_SIZE(generic_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ static void __init omap_generic_init(void)
+@@ -68,9 +67,10 @@ static void __init omap_generic_map_io(void)
+ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
+ /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
+ .boot_params = 0x80000100,
+- .map_io = omap_generic_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_generic_init_irq,
++ .map_io = omap_generic_map_io,
++ .init_early = omap_generic_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap_generic_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
+index 25cc9da..f6a3872 100644
+--- a/arch/arm/mach-omap2/board-h4.c
++++ b/arch/arm/mach-omap2/board-h4.c
+@@ -290,12 +290,16 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
+ { OMAP_TAG_LCD, &h4_lcd_config },
+ };
+
+-static void __init omap_h4_init_irq(void)
++static void __init omap_h4_init_early(void)
+ {
+ omap_board_config = h4_config;
+ omap_board_config_size = ARRAY_SIZE(h4_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
++}
++
++static void __init omap_h4_init_irq(void)
++{
+ omap_init_irq();
+ h4_init_flash();
+ }
+@@ -378,8 +382,9 @@ static void __init omap_h4_map_io(void)
+ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
+ /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
+ .boot_params = 0x80000100,
+- .map_io = omap_h4_map_io,
+ .reserve = omap_reserve,
++ .map_io = omap_h4_map_io,
++ .init_early = omap_h4_init_early,
+ .init_irq = omap_h4_init_irq,
+ .init_machine = omap_h4_init,
+ .timer = &omap_timer,
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index 3be85a1..dd0b1ac 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -525,12 +525,11 @@ static struct platform_device *igep2_devices[] __initdata = {
+ &igep2_vwlan_device,
+ };
+
+-static void __init igep2_init_irq(void)
++static void __init igep2_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(m65kxxxxam_sdrc_params,
+ m65kxxxxam_sdrc_params);
+- omap_init_irq();
+ }
+
+ static struct twl4030_codec_audio_data igep2_audio_data = {
+@@ -716,9 +715,10 @@ static void __init igep2_init(void)
+
+ MACHINE_START(IGEP0020, "IGEP v2 board")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = igep2_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = igep2_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = igep2_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
+index 4dc62a9..d75028e 100644
+--- a/arch/arm/mach-omap2/board-igep0030.c
++++ b/arch/arm/mach-omap2/board-igep0030.c
+@@ -331,12 +331,11 @@ static struct platform_device *igep3_devices[] __initdata = {
+ &igep3_vwlan_device,
+ };
+
+-static void __init igep3_init_irq(void)
++static void __init igep3_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(m65kxxxxam_sdrc_params,
+ m65kxxxxam_sdrc_params);
+- omap_init_irq();
+ }
+
+ static struct twl4030_platform_data igep3_twl4030_pdata = {
+@@ -452,7 +451,8 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
+ .boot_params = 0x80000100,
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+- .init_irq = igep3_init_irq,
++ .init_early = igep3_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = igep3_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index e5dc748..d8eb2cb 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -288,13 +288,12 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
+ { OMAP_TAG_LCD, &ldp_lcd_config },
+ };
+
+-static void __init omap_ldp_init_irq(void)
++static void __init omap_ldp_init_early(void)
+ {
+ omap_board_config = ldp_config;
+ omap_board_config_size = ARRAY_SIZE(ldp_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ static struct twl4030_usb_data ldp_usb_data = {
+@@ -443,9 +442,10 @@ static void __init omap_ldp_init(void)
+
+ MACHINE_START(OMAP_LDP, "OMAP LDP board")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_ldp_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = omap_ldp_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap_ldp_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
+index f396756..b36cbd2 100644
+--- a/arch/arm/mach-omap2/board-n8x0.c
++++ b/arch/arm/mach-omap2/board-n8x0.c
+@@ -628,11 +628,10 @@ static void __init n8x0_map_io(void)
+ omap242x_map_common_io();
+ }
+
+-static void __init n8x0_init_irq(void)
++static void __init n8x0_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ #ifdef CONFIG_OMAP_MUX
+@@ -703,27 +702,30 @@ static void __init n8x0_init_machine(void)
+
+ MACHINE_START(NOKIA_N800, "Nokia N800")
+ .boot_params = 0x80000100,
+- .map_io = n8x0_map_io,
+ .reserve = omap_reserve,
+- .init_irq = n8x0_init_irq,
++ .map_io = n8x0_map_io,
++ .init_early = n8x0_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = n8x0_init_machine,
+ .timer = &omap_timer,
+ MACHINE_END
+
+ MACHINE_START(NOKIA_N810, "Nokia N810")
+ .boot_params = 0x80000100,
+- .map_io = n8x0_map_io,
+ .reserve = omap_reserve,
+- .init_irq = n8x0_init_irq,
++ .map_io = n8x0_map_io,
++ .init_early = n8x0_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = n8x0_init_machine,
+ .timer = &omap_timer,
+ MACHINE_END
+
+ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
+ .boot_params = 0x80000100,
+- .map_io = n8x0_map_io,
+ .reserve = omap_reserve,
+- .init_irq = n8x0_init_irq,
++ .map_io = n8x0_map_io,
++ .init_early = n8x0_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = n8x0_init_machine,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index 46d814a..19bcd00 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -536,11 +536,15 @@ static struct platform_device keys_gpio = {
+ },
+ };
+
+-static void __init omap3_beagle_init_irq(void)
++static void __init omap3_beagle_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
++}
++
++static void __init omap3_beagle_init_irq(void)
++{
+ omap_init_irq();
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+@@ -638,8 +642,9 @@ static void __init omap3_beagle_init(void)
+ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
+ /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
++ .map_io = omap3_map_io,
++ .init_early = omap3_beagle_init_early,
+ .init_irq = omap3_beagle_init_irq,
+ .init_machine = omap3_beagle_init,
+ .timer = &omap_timer,
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 323c380..c2a0fca 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -625,13 +625,12 @@ static struct spi_board_info omap3evm_spi_board_info[] = {
+ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+ };
+
+-static void __init omap3_evm_init_irq(void)
++static void __init omap3_evm_init_early(void)
+ {
+ omap_board_config = omap3_evm_config;
+ omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
+- omap_init_irq();
+ }
+
+ static struct platform_device *omap3_evm_devices[] __initdata = {
+@@ -720,9 +719,10 @@ static void __init omap3_evm_init(void)
+ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
+ /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap3_evm_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = omap3_evm_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap3_evm_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
+index 15e4b08..b726943 100644
+--- a/arch/arm/mach-omap2/board-omap3logic.c
++++ b/arch/arm/mach-omap2/board-omap3logic.c
+@@ -195,11 +195,10 @@ static inline void __init board_smsc911x_init(void)
+ gpmc_smsc911x_init(&board_smsc911x_data);
+ }
+
+-static void __init omap3logic_init_irq(void)
++static void __init omap3logic_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- omap_init_irq();
+ }
+
+ #ifdef CONFIG_OMAP_MUX
+@@ -225,7 +224,8 @@ static void __init omap3logic_init(void)
+ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
+ .boot_params = 0x80000100,
+ .map_io = omap3_map_io,
+- .init_irq = omap3logic_init_irq,
++ .init_early = omap3logic_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap3logic_init,
+ .timer = &omap_timer,
+ MACHINE_END
+@@ -233,7 +233,8 @@ MACHINE_END
+ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
+ .boot_params = 0x80000100,
+ .map_io = omap3_map_io,
+- .init_irq = omap3logic_init_irq,
++ .init_early = omap3logic_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap3logic_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
+index 0b34bed..b91f74c 100644
+--- a/arch/arm/mach-omap2/board-omap3pandora.c
++++ b/arch/arm/mach-omap2/board-omap3pandora.c
+@@ -634,12 +634,11 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
+ }
+ };
+
+-static void __init omap3pandora_init_irq(void)
++static void __init omap3pandora_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
+- omap_init_irq();
+ }
+
+ static void __init pandora_wl1251_init(void)
+@@ -727,9 +726,10 @@ static void __init omap3pandora_init(void)
+
+ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap3pandora_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = omap3pandora_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap3pandora_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index 2a2dad4..5d1ccef 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -591,12 +591,16 @@ static struct spi_board_info omap3stalker_spi_board_info[] = {
+ static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
+ };
+
+-static void __init omap3_stalker_init_irq(void)
++static void __init omap3_stalker_init_early(void)
+ {
+ omap_board_config = omap3_stalker_config;
+ omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
++}
++
++static void __init omap3_stalker_init_irq(void)
++{
+ omap_init_irq();
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+@@ -666,6 +670,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
+ /* Maintainer: Jason Lam -lzg@ema-tech.com */
+ .boot_params = 0x80000100,
+ .map_io = omap3_map_io,
++ .init_early = omap3_stalker_init_early,
+ .init_irq = omap3_stalker_init_irq,
+ .init_machine = omap3_stalker_init,
+ .timer = &omap_timer,
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index db1f74f..6a60f79 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -415,7 +415,7 @@ static struct omap_board_mux board_mux[] __initdata = {
+ };
+ #endif
+
+-static void __init omap3_touchbook_init_irq(void)
++static void __init omap3_touchbook_init_early(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ omap_board_config = omap3_touchbook_config;
+@@ -423,6 +423,10 @@ static void __init omap3_touchbook_init_irq(void)
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
++}
++
++static void __init omap3_touchbook_init_irq(void)
++{
+ omap_init_irq();
+ #ifdef CONFIG_OMAP_32K_TIMER
+ omap2_gp_clockevent_set_gptimer(12);
+@@ -538,8 +542,9 @@ static void __init omap3_touchbook_init(void)
+ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
+ /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
++ .map_io = omap3_map_io,
++ .init_early = omap3_touchbook_init_early,
+ .init_irq = omap3_touchbook_init_irq,
+ .init_machine = omap3_touchbook_init,
+ .timer = &omap_timer,
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index e944025..fca5b9e 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -76,11 +76,10 @@ static struct platform_device *panda_devices[] __initdata = {
+ &leds_gpio,
+ };
+
+-static void __init omap4_panda_init_irq(void)
++static void __init omap4_panda_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+- gic_init_irq();
+ }
+
+ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+@@ -424,7 +423,8 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
+ .boot_params = 0x80000100,
+ .reserve = omap_reserve,
+ .map_io = omap4_panda_map_io,
+- .init_irq = omap4_panda_init_irq,
++ .init_early = omap4_panda_init_early,
++ .init_irq = gic_init_irq,
+ .init_machine = omap4_panda_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index cb26e5d..a33ec0e 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -409,14 +409,13 @@ static struct omap_board_config_kernel overo_config[] __initdata = {
+ { OMAP_TAG_LCD, &overo_lcd_config },
+ };
+
+-static void __init overo_init_irq(void)
++static void __init overo_init_early(void)
+ {
+ omap_board_config = overo_config;
+ omap_board_config_size = ARRAY_SIZE(overo_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
+- omap_init_irq();
+ }
+
+ static struct platform_device *overo_devices[] __initdata = {
+@@ -501,9 +500,10 @@ static void __init overo_init(void)
+
+ MACHINE_START(OVERO, "Gumstix Overo")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = overo_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = overo_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = overo_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
+index 39a71bb..bdebcb7 100644
+--- a/arch/arm/mach-omap2/board-rm680.c
++++ b/arch/arm/mach-omap2/board-rm680.c
+@@ -138,14 +138,13 @@ static void __init rm680_peripherals_init(void)
+ omap2_hsmmc_init(mmc);
+ }
+
+-static void __init rm680_init_irq(void)
++static void __init rm680_init_early(void)
+ {
+ struct omap_sdrc_params *sdrc_params;
+
+ omap2_init_common_infrastructure();
+ sdrc_params = nokia_get_sdram_timings();
+ omap2_init_common_devices(sdrc_params, sdrc_params);
+- omap_init_irq();
+ }
+
+ #ifdef CONFIG_OMAP_MUX
+@@ -176,9 +175,10 @@ static void __init rm680_map_io(void)
+
+ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
+ .boot_params = 0x80000100,
+- .map_io = rm680_map_io,
+ .reserve = omap_reserve,
+- .init_irq = rm680_init_irq,
++ .map_io = rm680_map_io,
++ .init_early = rm680_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = rm680_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
+index f53fc55..3cf72fe 100644
+--- a/arch/arm/mach-omap2/board-rx51.c
++++ b/arch/arm/mach-omap2/board-rx51.c
+@@ -98,7 +98,7 @@ static struct omap_board_config_kernel rx51_config[] = {
+ { OMAP_TAG_LCD, &rx51_lcd_config },
+ };
+
+-static void __init rx51_init_irq(void)
++static void __init rx51_init_early(void)
+ {
+ struct omap_sdrc_params *sdrc_params;
+
+@@ -108,7 +108,6 @@ static void __init rx51_init_irq(void)
+ omap2_init_common_infrastructure();
+ sdrc_params = nokia_get_sdram_timings();
+ omap2_init_common_devices(sdrc_params, sdrc_params);
+- omap_init_irq();
+ }
+
+ extern void __init rx51_peripherals_init(void);
+@@ -149,9 +148,10 @@ static void __init rx51_map_io(void)
+ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
+ /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
+ .boot_params = 0x80000100,
+- .map_io = rx51_map_io,
+ .reserve = omap_reserve,
+- .init_irq = rx51_init_irq,
++ .map_io = rx51_map_io,
++ .init_early = rx51_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = rx51_init,
+ .timer = &omap_timer,
+ MACHINE_END
+diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
+index e26754c..85d4170 100644
+--- a/arch/arm/mach-omap2/board-zoom.c
++++ b/arch/arm/mach-omap2/board-zoom.c
+@@ -33,7 +33,7 @@
+
+ #define ZOOM3_EHCI_RESET_GPIO 64
+
+-static void __init omap_zoom_init_irq(void)
++static void __init omap_zoom_init_early(void)
+ {
+ omap2_init_common_infrastructure();
+ if (machine_is_omap_zoom2())
+@@ -42,8 +42,6 @@ static void __init omap_zoom_init_irq(void)
+ else if (machine_is_omap_zoom3())
+ omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
+ h8mbx00u0mer0em_sdrc_params);
+-
+- omap_init_irq();
+ }
+
+ #ifdef CONFIG_OMAP_MUX
+@@ -135,18 +133,20 @@ static void __init omap_zoom_init(void)
+
+ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_zoom_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = omap_zoom_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap_zoom_init,
+ .timer = &omap_timer,
+ MACHINE_END
+
+ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
+ .boot_params = 0x80000100,
+- .map_io = omap3_map_io,
+ .reserve = omap_reserve,
+- .init_irq = omap_zoom_init_irq,
++ .map_io = omap3_map_io,
++ .init_early = omap_zoom_init_early,
++ .init_irq = omap_init_irq,
+ .init_machine = omap_zoom_init,
+ .timer = &omap_timer,
+ MACHINE_END
+--
+1.7.1
+
diff --git a/patches/for_next/0020-omap2-Make-omap_hwmod_late_init-into-core_initcall.patch b/patches/for_next/0020-omap2-Make-omap_hwmod_late_init-into-core_initcall.patch
new file mode 100644
index 0000000000000000000000000000000000000000..bbdad770fd77f079e8f84f74ab4b0dbe7533ebd1
--- /dev/null
+++ b/patches/for_next/0020-omap2-Make-omap_hwmod_late_init-into-core_initcall.patch
@@ -0,0 +1,63 @@
+From 279a1282af89b1e65de1d17e8f9ec34406ee2bc7 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Mon, 14 Feb 2011 15:40:20 -0800
+Subject: [PATCH 020/254] omap2+: Make omap_hwmod_late_init into core_initcall
+
+Otherwise things will fail with early_init changes.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/io.c | 2 --
+ arch/arm/mach-omap2/omap_hwmod.c | 3 ++-
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 -
+ 3 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index 11decd8..bbfb0c8 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -400,8 +400,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+ {
+ omap_serial_early_init();
+
+- omap_hwmod_late_init();
+-
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+ omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
+ _omap2_init_reprogram_sdrc();
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index e282e35..eacdfd3 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1628,7 +1628,7 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs)
+ * to struct clk pointers for each registered omap_hwmod. Also calls
+ * _setup() on each hwmod. Returns 0.
+ */
+-int omap_hwmod_late_init(void)
++static int __init omap_hwmod_late_init(void)
+ {
+ int r;
+
+@@ -1644,6 +1644,7 @@ int omap_hwmod_late_init(void)
+
+ return 0;
+ }
++core_initcall(omap_hwmod_late_init);
+
+ /**
+ * omap_hwmod_enable - enable an omap_hwmod
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 1eee85a..fedd829 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -539,7 +539,6 @@ int omap_hwmod_init(struct omap_hwmod **ohs);
+ struct omap_hwmod *omap_hwmod_lookup(const char *name);
+ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+ void *data);
+-int omap_hwmod_late_init(void);
+
+ int omap_hwmod_enable(struct omap_hwmod *oh);
+ int _omap_hwmod_enable(struct omap_hwmod *oh);
+--
+1.7.1
+
diff --git a/patches/for_next/0021-omap2-Fix-omap_serial_early_init-to-work-with-init_e.patch b/patches/for_next/0021-omap2-Fix-omap_serial_early_init-to-work-with-init_e.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2600b65a188357e0d87ff8c364733256b16d8644
--- /dev/null
+++ b/patches/for_next/0021-omap2-Fix-omap_serial_early_init-to-work-with-init_e.patch
@@ -0,0 +1,79 @@
+From 8912503d45f93c1665aae88a8a1920fc981ca156 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Mon, 14 Feb 2011 15:40:20 -0800
+Subject: [PATCH 021/254] omap2+: Fix omap_serial_early_init to work with init_early hook
+
+The new init_early hook happens at the end of setup_arch,
+which is too early for kzalloc. However, there's no need
+to call omap_serial_early_init that early, so fix this
+by setting it up as a core_initcall.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Tested-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/io.c | 2 --
+ arch/arm/mach-omap2/serial.c | 7 +++++--
+ arch/arm/plat-omap/include/plat/serial.h | 1 -
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index bbfb0c8..684e20a 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -398,8 +398,6 @@ void __init omap2_init_common_infrastructure(void)
+ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+ struct omap_sdrc_params *sdrc_cs1)
+ {
+- omap_serial_early_init();
+-
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+ omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
+ _omap2_init_reprogram_sdrc();
+diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
+index 32e91a9..74e25cd 100644
+--- a/arch/arm/mach-omap2/serial.c
++++ b/arch/arm/mach-omap2/serial.c
+@@ -655,7 +655,7 @@ static void serial_out_override(struct uart_port *up, int offset, int value)
+ }
+ #endif
+
+-void __init omap_serial_early_init(void)
++static int __init omap_serial_early_init(void)
+ {
+ int i = 0;
+
+@@ -672,7 +672,7 @@ void __init omap_serial_early_init(void)
+
+ uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
+ if (WARN_ON(!uart))
+- return;
++ return -ENODEV;
+
+ uart->oh = oh;
+ uart->num = i++;
+@@ -691,7 +691,10 @@ void __init omap_serial_early_init(void)
+ */
+ uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+ } while (1);
++
++ return 0;
+ }
++core_initcall(omap_serial_early_init);
+
+ /**
+ * omap_serial_init_port() - initialize single serial port
+diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
+index cec5d56..a1a118d 100644
+--- a/arch/arm/plat-omap/include/plat/serial.h
++++ b/arch/arm/plat-omap/include/plat/serial.h
+@@ -96,7 +96,6 @@
+
+ struct omap_board_data;
+
+-extern void __init omap_serial_early_init(void);
+ extern void omap_serial_init(void);
+ extern void omap_serial_init_port(struct omap_board_data *bdata);
+ extern int omap_uart_can_sleep(void);
+--
+1.7.1
+
diff --git a/patches/for_next/0022-omap-hwmod-Populate-_mpu_rt_va-later-on-in-omap_hwmo.patch b/patches/for_next/0022-omap-hwmod-Populate-_mpu_rt_va-later-on-in-omap_hwmo.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7e41846f50b0effc7380a842fd2fae2a10baca59
--- /dev/null
+++ b/patches/for_next/0022-omap-hwmod-Populate-_mpu_rt_va-later-on-in-omap_hwmo.patch
@@ -0,0 +1,71 @@
+From b31023f929176983e9d0046165009c827533946a Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Mon, 14 Feb 2011 15:40:21 -0800
+Subject: [PATCH 022/254] omap: hwmod: Populate _mpu_rt_va later on in omap_hwmod_late_init
+
+Otherwise ioremap can fail with early_init patch unless we have
+a static mapping for everything.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 28 ++++++++++++++++++++++++----
+ 1 files changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index eacdfd3..9e89a58 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1467,12 +1467,10 @@ static int __init _register(struct omap_hwmod *oh)
+ return -EEXIST;
+
+ ms_id = _find_mpu_port_index(oh);
+- if (!IS_ERR_VALUE(ms_id)) {
++ if (!IS_ERR_VALUE(ms_id))
+ oh->_mpu_port_index = ms_id;
+- oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+- } else {
++ else
+ oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+- }
+
+ list_add_tail(&oh->node, &omap_hwmod_list);
+
+@@ -1621,6 +1619,26 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs)
+ return 0;
+ }
+
++/*
++ * _populate_mpu_rt_base - populate the virtual address for a hwmod
++ *
++ * Must be called only from omap_hwmod_late_init so ioremap works properly.
++ * Assumes the caller takes care of locking if needed.
++ *
++ */
++static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
++{
++ if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
++ return 0;
++
++ oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
++ if (!oh->_mpu_rt_va)
++ pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
++ __func__, oh->name);
++
++ return 0;
++}
++
+ /**
+ * omap_hwmod_late_init - do some post-clock framework initialization
+ *
+@@ -1632,6 +1650,8 @@ static int __init omap_hwmod_late_init(void)
+ {
+ int r;
+
++ r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
++
+ /* XXX check return value */
+ r = omap_hwmod_for_each(_init_clocks, NULL);
+ WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");
+--
+1.7.1
+
diff --git a/patches/for_next/0023-TI816X-Update-common-omap-platform-files.patch b/patches/for_next/0023-TI816X-Update-common-omap-platform-files.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b083ca4bb69fd483a9916a177e274f5e8887538c
--- /dev/null
+++ b/patches/for_next/0023-TI816X-Update-common-omap-platform-files.patch
@@ -0,0 +1,164 @@
+From dcfaf0187bb5c69127aaa9228d3a44b4d474e2d2 Mon Sep 17 00:00:00 2001
+From: Hemant Pedanekar <hemantp@ti.com>
+Date: Wed, 16 Feb 2011 08:31:39 -0800
+Subject: [PATCH 023/254] TI816X: Update common omap platform files
+
+This patch updates the common platform files with TI816X support.
+
+The approach taken in this patch is to add TI816X as part of OMAP3 variant where
+the cpu class is considered as OMAP34XX and the type is TI816X. This means, both
+cpu_is_omap34xx() and cpu_is_ti816x() checks return success on TI816X.
+
+A kernel config option CONFIG_SOC_OMAPTI816X is added under OMAP3 to include
+support for TI816X build.
+
+Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/Kconfig | 5 +++++
+ arch/arm/plat-omap/include/plat/clkdev_omap.h | 1 +
+ arch/arm/plat-omap/include/plat/clock.h | 1 +
+ arch/arm/plat-omap/include/plat/common.h | 1 +
+ arch/arm/plat-omap/include/plat/cpu.h | 18 ++++++++++++++++++
+ 5 files changed, 26 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
+index ae7f47d..6a4cfc2 100644
+--- a/arch/arm/mach-omap2/Kconfig
++++ b/arch/arm/mach-omap2/Kconfig
+@@ -72,6 +72,11 @@ config SOC_OMAP3430
+ default y
+ select ARCH_OMAP_OTG
+
++config SOC_OMAPTI816X
++ bool "TI816X support"
++ depends on ARCH_OMAP3
++ default y
++
+ config OMAP_PACKAGE_ZAF
+ bool
+
+diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
+index 256ab3f..f1899a3 100644
+--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
++++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
+@@ -38,6 +38,7 @@ struct omap_clk {
+ #define CK_3517 (1 << 9)
+ #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
+ #define CK_443X (1 << 11)
++#define CK_TI816X (1 << 12)
+
+
+ #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
+diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
+index 8eb0ada..d43e623 100644
+--- a/arch/arm/plat-omap/include/plat/clock.h
++++ b/arch/arm/plat-omap/include/plat/clock.h
+@@ -53,6 +53,7 @@ struct clkops {
+ #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
+ #define RATE_IN_36XX (1 << 4)
+ #define RATE_IN_4430 (1 << 5)
++#define RATE_IN_TI816X (1 << 6)
+
+ #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
+ #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
+diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
+index 29b2afb..1dd97e7 100644
+--- a/arch/arm/plat-omap/include/plat/common.h
++++ b/arch/arm/plat-omap/include/plat/common.h
+@@ -66,6 +66,7 @@ void omap2_set_globals_242x(void);
+ void omap2_set_globals_243x(void);
+ void omap2_set_globals_3xxx(void);
+ void omap2_set_globals_443x(void);
++void omap2_set_globals_ti816x(void);
+
+ /* These get called from omap2_set_globals_xxxx(), do not call these */
+ void omap2_set_globals_tap(struct omap_globals *);
+diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
+index 73d91ee..be99438 100644
+--- a/arch/arm/plat-omap/include/plat/cpu.h
++++ b/arch/arm/plat-omap/include/plat/cpu.h
+@@ -105,6 +105,12 @@ static inline int is_omap ##subclass (void) \
+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
+ }
+
++#define IS_TI_SUBCLASS(subclass, id) \
++static inline int is_ti ##subclass (void) \
++{ \
++ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
++}
++
+ IS_OMAP_CLASS(7xx, 0x07)
+ IS_OMAP_CLASS(15xx, 0x15)
+ IS_OMAP_CLASS(16xx, 0x16)
+@@ -118,6 +124,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
+ IS_OMAP_SUBCLASS(363x, 0x363)
+ IS_OMAP_SUBCLASS(443x, 0x443)
+
++IS_TI_SUBCLASS(816x, 0x816)
++
+ #define cpu_is_omap7xx() 0
+ #define cpu_is_omap15xx() 0
+ #define cpu_is_omap16xx() 0
+@@ -126,6 +134,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
+ #define cpu_is_omap243x() 0
+ #define cpu_is_omap34xx() 0
+ #define cpu_is_omap343x() 0
++#define cpu_is_ti816x() 0
+ #define cpu_is_omap44xx() 0
+ #define cpu_is_omap443x() 0
+
+@@ -330,6 +339,7 @@ IS_OMAP_TYPE(3517, 0x3517)
+ # undef cpu_is_omap3530
+ # undef cpu_is_omap3505
+ # undef cpu_is_omap3517
++# undef cpu_is_ti816x
+ # define cpu_is_omap3430() is_omap3430()
+ # define cpu_is_omap3503() (cpu_is_omap3430() && \
+ (!omap3_has_iva()) && \
+@@ -345,6 +355,7 @@ IS_OMAP_TYPE(3517, 0x3517)
+ # define cpu_is_omap3517() is_omap3517()
+ # undef cpu_is_omap3630
+ # define cpu_is_omap3630() is_omap363x()
++# define cpu_is_ti816x() is_ti816x()
+ #endif
+
+ # if defined(CONFIG_ARCH_OMAP4)
+@@ -389,6 +400,10 @@ IS_OMAP_TYPE(3517, 0x3517)
+ #define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
+ #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+
++#define TI816X_CLASS 0x81600034
++#define TI8168_REV_ES1_0 TI816X_CLASS
++#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
++
+ #define OMAP443X_CLASS 0x44300044
+ #define OMAP4430_REV_ES1_0 OMAP443X_CLASS
+ #define OMAP4430_REV_ES2_0 0x44301044
+@@ -419,6 +434,7 @@ IS_OMAP_TYPE(3517, 0x3517)
+ #define CHIP_IS_OMAP3630ES1_1 (1 << 9)
+ #define CHIP_IS_OMAP3630ES1_2 (1 << 10)
+ #define CHIP_IS_OMAP4430ES2 (1 << 11)
++#define CHIP_IS_TI816X (1 << 14)
+
+ #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+
+@@ -455,6 +471,7 @@ extern u32 omap3_features;
+ #define OMAP3_HAS_ISP BIT(4)
+ #define OMAP3_HAS_192MHZ_CLK BIT(5)
+ #define OMAP3_HAS_IO_WAKEUP BIT(6)
++#define OMAP3_HAS_SDRC BIT(7)
+
+ #define OMAP3_HAS_FEATURE(feat,flag) \
+ static inline unsigned int omap3_has_ ##feat(void) \
+@@ -469,5 +486,6 @@ OMAP3_HAS_FEATURE(neon, NEON)
+ OMAP3_HAS_FEATURE(isp, ISP)
+ OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
+ OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
++OMAP3_HAS_FEATURE(sdrc, SDRC)
+
+ #endif
+--
+1.7.1
+
diff --git a/patches/for_next/0024-TI816X-Update-common-OMAP-machine-specific-sources.patch b/patches/for_next/0024-TI816X-Update-common-OMAP-machine-specific-sources.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e4361f9369c2f1f7ce81fe993cf6225bb2c9d36b
--- /dev/null
+++ b/patches/for_next/0024-TI816X-Update-common-OMAP-machine-specific-sources.patch
@@ -0,0 +1,405 @@
+From d11cb50d07b3df9c00b28b07f7301dca693a4d5e Mon Sep 17 00:00:00 2001
+From: Hemant Pedanekar <hemantp@ti.com>
+Date: Wed, 16 Feb 2011 08:31:39 -0800
+Subject: [PATCH 024/254] TI816X: Update common OMAP machine specific sources
+
+This patch updates the common machine specific source files with support for
+TI816X.
+
+Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/clock3xxx_data.c | 5 +++-
+ arch/arm/mach-omap2/common.c | 21 +++++++++++++++
+ arch/arm/mach-omap2/control.h | 6 ++++
+ arch/arm/mach-omap2/id.c | 33 ++++++++++++++++++++++-
+ arch/arm/mach-omap2/include/mach/entry-macro.S | 13 +++++++++
+ arch/arm/mach-omap2/io.c | 22 +++++++++++++++-
+ arch/arm/mach-omap2/irq.c | 5 +++-
+ arch/arm/mach-omap2/serial.c | 8 +++---
+ arch/arm/plat-omap/include/plat/hardware.h | 1 +
+ arch/arm/plat-omap/include/plat/io.h | 8 ++++++
+ arch/arm/plat-omap/include/plat/ti816x.h | 27 +++++++++++++++++++
+ arch/arm/plat-omap/io.c | 5 +++-
+ 12 files changed, 144 insertions(+), 10 deletions(-)
+ create mode 100644 arch/arm/plat-omap/include/plat/ti816x.h
+
+diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
+index 403a4a1..f14d986 100644
+--- a/arch/arm/mach-omap2/clock3xxx_data.c
++++ b/arch/arm/mach-omap2/clock3xxx_data.c
+@@ -3471,6 +3471,9 @@ int __init omap3xxx_clk_init(void)
+ } else if (cpu_is_omap3630()) {
+ cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
+ cpu_clkflg = CK_36XX;
++ } else if (cpu_is_ti816x()) {
++ cpu_mask = RATE_IN_TI816X;
++ cpu_clkflg = CK_TI816X;
+ } else if (cpu_is_omap34xx()) {
+ if (omap_rev() == OMAP3430_REV_ES1_0) {
+ cpu_mask = RATE_IN_3430ES1;
+@@ -3550,7 +3553,7 @@ int __init omap3xxx_clk_init(void)
+ /*
+ * Lock DPLL5 and put it in autoidle.
+ */
+- if (omap_rev() >= OMAP3430_REV_ES2_0)
++ if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+ omap3_clk_lock_dpll5();
+
+ /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
+diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
+index d5eaee3..48de451 100644
+--- a/arch/arm/mach-omap2/common.c
++++ b/arch/arm/mach-omap2/common.c
+@@ -108,6 +108,27 @@ void __init omap3_map_io(void)
+ omap2_set_globals_3xxx();
+ omap34xx_map_common_io();
+ }
++
++/*
++ * Adjust TAP register base such that omap3_check_revision accesses the correct
++ * TI816X register for checking device ID (it adds 0x204 to tap base while
++ * TI816X DEVICE ID register is at offset 0x600 from control base).
++ */
++#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \
++ TI816X_CONTROL_DEVICE_ID - 0x204)
++
++static struct omap_globals ti816x_globals = {
++ .class = OMAP343X_CLASS,
++ .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
++ .ctrl = TI816X_CTRL_BASE,
++ .prm = TI816X_PRCM_BASE,
++ .cm = TI816X_PRCM_BASE,
++};
++
++void __init omap2_set_globals_ti816x(void)
++{
++ __omap2_set_globals(&ti816x_globals);
++}
+ #endif
+
+ #if defined(CONFIG_ARCH_OMAP4)
+diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
+index f0629ae..c2804c1 100644
+--- a/arch/arm/mach-omap2/control.h
++++ b/arch/arm/mach-omap2/control.h
+@@ -52,6 +52,9 @@
+ #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
+ #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
+
++/* TI816X spefic control submodules */
++#define TI816X_CONTROL_DEVCONF 0x600
++
+ /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
+
+ #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
+@@ -241,6 +244,9 @@
+ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
+ #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
+
++/* TI816X CONTROL_DEVCONF register offsets */
++#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000)
++
+ /*
+ * REVISIT: This list of registers is not comprehensive - there are more
+ * that should be added.
+diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
+index 5f9086c..5c25f1b 100644
+--- a/arch/arm/mach-omap2/id.c
++++ b/arch/arm/mach-omap2/id.c
+@@ -191,12 +191,19 @@ static void __init omap3_check_features(void)
+ if (!cpu_is_omap3505() && !cpu_is_omap3517())
+ omap3_features |= OMAP3_HAS_IO_WAKEUP;
+
++ omap3_features |= OMAP3_HAS_SDRC;
++
+ /*
+ * TODO: Get additional info (where applicable)
+ * e.g. Size of L2 cache.
+ */
+ }
+
++static void __init ti816x_check_features(void)
++{
++ omap3_features = OMAP3_HAS_NEON;
++}
++
+ static void __init omap3_check_revision(void)
+ {
+ u32 cpuid, idcode;
+@@ -287,6 +294,20 @@ static void __init omap3_check_revision(void)
+ omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+ }
+ break;
++ case 0xb81e:
++ omap_chip.oc = CHIP_IS_TI816X;
++
++ switch (rev) {
++ case 0:
++ omap_revision = TI8168_REV_ES1_0;
++ break;
++ case 1:
++ omap_revision = TI8168_REV_ES1_1;
++ break;
++ default:
++ omap_revision = TI8168_REV_ES1_1;
++ }
++ break;
+ default:
+ /* Unknown default to latest silicon rev as default*/
+ omap_revision = OMAP3630_REV_ES1_2;
+@@ -372,6 +393,8 @@ static void __init omap3_cpuinfo(void)
+ /* Already set in omap3_check_revision() */
+ strcpy(cpu_name, "AM3505");
+ }
++ } else if (cpu_is_ti816x()) {
++ strcpy(cpu_name, "TI816X");
+ } else if (omap3_has_iva() && omap3_has_sgx()) {
+ /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
+ strcpy(cpu_name, "OMAP3430/3530");
+@@ -386,7 +409,7 @@ static void __init omap3_cpuinfo(void)
+ strcpy(cpu_name, "OMAP3503");
+ }
+
+- if (cpu_is_omap3630()) {
++ if (cpu_is_omap3630() || cpu_is_ti816x()) {
+ switch (rev) {
+ case OMAP_REVBITS_00:
+ strcpy(cpu_rev, "1.0");
+@@ -462,7 +485,13 @@ void __init omap2_check_revision(void)
+ omap24xx_check_revision();
+ } else if (cpu_is_omap34xx()) {
+ omap3_check_revision();
+- omap3_check_features();
++
++ /* TI816X doesn't have feature register */
++ if (!cpu_is_ti816x())
++ omap3_check_features();
++ else
++ ti816x_check_features();
++
+ omap3_cpuinfo();
+ return;
+ } else if (cpu_is_omap44xx()) {
+diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
+index 81985a6..a48690b 100644
+--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
++++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
+@@ -61,6 +61,14 @@
+ bne 9998f
+ ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+ cmp \irqnr, #0x0
++ bne 9998f
++
++ /*
++ * ti816x has additional IRQ pending register. Checking this
++ * register on omap2 & omap3 has no effect (read as 0).
++ */
++ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
++ cmp \irqnr, #0x0
+ 9998:
+ ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
+ and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
+@@ -133,6 +141,11 @@
+ bne 9999f
+ ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
+ cmp \irqnr, #0x0
++#ifdef CONFIG_SOC_OMAPTI816X
++ bne 9999f
++ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
++ cmp \irqnr, #0x0
++#endif
+ 9999:
+ ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
+ and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index 684e20a..b8b49e4 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -175,6 +175,18 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
+ #endif
+ };
+ #endif
++
++#ifdef CONFIG_SOC_OMAPTI816X
++static struct map_desc omapti816x_io_desc[] __initdata = {
++ {
++ .virtual = L4_34XX_VIRT,
++ .pfn = __phys_to_pfn(L4_34XX_PHYS),
++ .length = L4_34XX_SIZE,
++ .type = MT_DEVICE
++ },
++};
++#endif
++
+ #ifdef CONFIG_ARCH_OMAP4
+ static struct map_desc omap44xx_io_desc[] __initdata = {
+ {
+@@ -267,6 +279,14 @@ void __init omap34xx_map_common_io(void)
+ }
+ #endif
+
++#ifdef CONFIG_SOC_OMAPTI816X
++void __init omapti816x_map_common_io(void)
++{
++ iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
++ _omap2_map_common_io();
++}
++#endif
++
+ #ifdef CONFIG_ARCH_OMAP4
+ void __init omap44xx_map_common_io(void)
+ {
+@@ -398,7 +418,7 @@ void __init omap2_init_common_infrastructure(void)
+ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+ struct omap_sdrc_params *sdrc_cs1)
+ {
+- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
++ if (cpu_is_omap24xx() || omap3_has_sdrc()) {
+ omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
+ _omap2_init_reprogram_sdrc();
+ }
+diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
+index d151aac..bc524b9 100644
+--- a/arch/arm/mach-omap2/irq.c
++++ b/arch/arm/mach-omap2/irq.c
+@@ -108,7 +108,7 @@ static void omap_mask_irq(struct irq_data *d)
+ unsigned int irq = d->irq;
+ int offset = irq & (~(IRQ_BITS_PER_REG - 1));
+
+- if (cpu_is_omap34xx()) {
++ if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+ int spurious = 0;
+
+ /*
+@@ -203,6 +203,9 @@ void __init omap_init_irq(void)
+
+ BUG_ON(!base);
+
++ if (cpu_is_ti816x())
++ bank->nr_irqs = 128;
++
+ /* Static mapping, never released */
+ bank->base_reg = ioremap(base, SZ_4K);
+ if (!bank->base_reg) {
+diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
+index 74e25cd..47eef48 100644
+--- a/arch/arm/mach-omap2/serial.c
++++ b/arch/arm/mach-omap2/serial.c
+@@ -486,7 +486,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
+ mod_timer(&uart->timer, jiffies + uart->timeout);
+ omap_uart_smart_idle_enable(uart, 0);
+
+- if (cpu_is_omap34xx()) {
++ if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
+ u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
+ u32 wk_mask = 0;
+ u32 padconf = 0;
+@@ -762,13 +762,13 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
+ p->private_data = uart;
+
+ /*
+- * omap44xx: Never read empty UART fifo
++ * omap44xx, ti816x: Never read empty UART fifo
+ * omap3xxx: Never read empty UART fifo on UARTs
+ * with IP rev >=0x52
+ */
+ uart->regshift = p->regshift;
+ uart->membase = p->membase;
+- if (cpu_is_omap44xx())
++ if (cpu_is_omap44xx() || cpu_is_ti816x())
+ uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
+ else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
+ >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
+@@ -850,7 +850,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
+ }
+
+ /* Enable the MDR1 errata for OMAP3 */
+- if (cpu_is_omap34xx())
++ if (cpu_is_omap34xx() && !cpu_is_ti816x())
+ uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
+ }
+
+diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
+index d5b26ad..e87efe1 100644
+--- a/arch/arm/plat-omap/include/plat/hardware.h
++++ b/arch/arm/plat-omap/include/plat/hardware.h
+@@ -286,5 +286,6 @@
+ #include <plat/omap24xx.h>
+ #include <plat/omap34xx.h>
+ #include <plat/omap44xx.h>
++#include <plat/ti816x.h>
+
+ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */
+diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
+index 478c5d9..d72ec85 100644
+--- a/arch/arm/plat-omap/include/plat/io.h
++++ b/arch/arm/plat-omap/include/plat/io.h
+@@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void)
+ }
+ #endif
+
++#ifdef CONFIG_SOC_OMAPTI816X
++extern void omapti816x_map_common_io(void);
++#else
++static inline void omapti816x_map_common_io(void)
++{
++}
++#endif
++
+ #ifdef CONFIG_ARCH_OMAP4
+ extern void omap44xx_map_common_io(void);
+ #else
+diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h
+new file mode 100644
+index 0000000..50510f5
+--- /dev/null
++++ b/arch/arm/plat-omap/include/plat/ti816x.h
+@@ -0,0 +1,27 @@
++/*
++ * This file contains the address data for various TI816X modules.
++ *
++ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __ASM_ARCH_TI816X_H
++#define __ASM_ARCH_TI816X_H
++
++#define L4_SLOW_TI816X_BASE 0x48000000
++
++#define TI816X_SCM_BASE 0x48140000
++#define TI816X_CTRL_BASE TI816X_SCM_BASE
++#define TI816X_PRCM_BASE 0x48180000
++
++#define TI816X_ARM_INTC_BASE 0x48200000
++
++#endif /* __ASM_ARCH_TI816X_H */
+diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
+index f1295fa..f1ecfa9 100644
+--- a/arch/arm/plat-omap/io.c
++++ b/arch/arm/plat-omap/io.c
+@@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
+ }
+ #endif
+ #ifdef CONFIG_ARCH_OMAP3
+- if (cpu_is_omap34xx()) {
++ if (cpu_is_ti816x()) {
++ if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
++ return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
++ } else if (cpu_is_omap34xx()) {
+ if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
+ return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
+ if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+--
+1.7.1
+
diff --git a/patches/for_next/0025-TI816X-Create-board-support-and-enable-build-for-TI8.patch b/patches/for_next/0025-TI816X-Create-board-support-and-enable-build-for-TI8.patch
new file mode 100644
index 0000000000000000000000000000000000000000..351a1845c4f51b7a32d02f07f2bed4e44e835a8e
--- /dev/null
+++ b/patches/for_next/0025-TI816X-Create-board-support-and-enable-build-for-TI8.patch
@@ -0,0 +1,111 @@
+From 535fe5694508e8acbf31ef950f79b27a066594d3 Mon Sep 17 00:00:00 2001
+From: Hemant Pedanekar <hemantp@ti.com>
+Date: Tue, 15 Feb 2011 23:06:08 +0530
+Subject: [PATCH 025/254] TI816X: Create board support and enable build for TI816X EVM
+
+This patch adds minimal support and build configuration for TI816X EVM.
+
+Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/Kconfig | 5 +++
+ arch/arm/mach-omap2/Makefile | 1 +
+ arch/arm/mach-omap2/board-ti8168evm.c | 57 +++++++++++++++++++++++++++++++++
+ 3 files changed, 63 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/board-ti8168evm.c
+
+diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
+index 6a4cfc2..9b4e78f 100644
+--- a/arch/arm/mach-omap2/Kconfig
++++ b/arch/arm/mach-omap2/Kconfig
+@@ -299,6 +299,11 @@ config MACH_OMAP_3630SDP
+ default y
+ select OMAP_PACKAGE_CBP
+
++config MACH_TI8168EVM
++ bool "TI8168 Evaluation Module"
++ depends on SOC_OMAPTI816X
++ default y
++
+ config MACH_OMAP_4430SDP
+ bool "OMAP 4430 SDP board"
+ default y
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 9eeabaf..a9e3974 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -224,6 +224,7 @@ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
+
+ obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \
+ hsmmc.o
++obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
+ # Platform specific device init code
+ usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o
+ obj-y += $(usbfs-m) $(usbfs-y)
+diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
+new file mode 100644
+index 0000000..6282cc4
+--- /dev/null
++++ b/arch/arm/mach-omap2/board-ti8168evm.c
+@@ -0,0 +1,57 @@
++/*
++ * Code for TI8168 EVM.
++ *
++ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++
++#include <mach/hardware.h>
++#include <asm/mach-types.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++
++#include <plat/irqs.h>
++#include <plat/board.h>
++#include <plat/common.h>
++
++static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
++};
++
++static void __init ti8168_evm_init_irq(void)
++{
++ omap_board_config = ti8168_evm_config;
++ omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
++ omap2_init_common_infrastructure();
++ omap2_init_common_devices(NULL, NULL);
++ omap_init_irq();
++}
++
++static void __init ti8168_evm_init(void)
++{
++ omap_serial_init();
++}
++
++static void __init ti8168_evm_map_io(void)
++{
++ omap2_set_globals_ti816x();
++ omapti816x_map_common_io();
++}
++
++MACHINE_START(TI8168EVM, "ti8168evm")
++ /* Maintainer: Texas Instruments */
++ .boot_params = 0x80000100,
++ .map_io = ti8168_evm_map_io,
++ .init_irq = ti8168_evm_init_irq,
++ .timer = &omap_timer,
++ .init_machine = ti8168_evm_init,
++MACHINE_END
+--
+1.7.1
+
diff --git a/patches/for_next/0026-TI816X-Add-low-level-debug-support.patch b/patches/for_next/0026-TI816X-Add-low-level-debug-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7c276d61ec4b4a39e155c7730673c80a5e20c337
--- /dev/null
+++ b/patches/for_next/0026-TI816X-Add-low-level-debug-support.patch
@@ -0,0 +1,101 @@
+From dba00f6da58e7272bc9964accbbb7a5f5881ffe4 Mon Sep 17 00:00:00 2001
+From: Hemant Pedanekar <hemantp@ti.com>
+Date: Tue, 15 Feb 2011 23:06:17 +0530
+Subject: [PATCH 026/254] TI816X: Add low level debug support
+
+This patch adds support for low level debugging on TI816X boards. Currently the
+support for UART3 console on TI816X EVM is added.
+
+Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/include/mach/debug-macro.S | 12 ++++++++++++
+ arch/arm/plat-omap/include/plat/serial.h | 8 ++++++++
+ arch/arm/plat-omap/include/plat/uncompress.h | 7 +++++++
+ 3 files changed, 27 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
+index 6a4d413..e1b0f17 100644
+--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
++++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
+@@ -69,6 +69,12 @@ omap_uart_lsr: .word 0
+ beq 34f @ configure OMAP3UART4
+ cmp \rp, #OMAP4UART4 @ only on 44xx
+ beq 44f @ configure OMAP4UART4
++ cmp \rp, #TI816XUART1 @ ti816x UART offsets different
++ beq 81f @ configure UART1
++ cmp \rp, #TI816XUART2 @ ti816x UART offsets different
++ beq 82f @ configure UART2
++ cmp \rp, #TI816XUART3 @ ti816x UART offsets different
++ beq 83f @ configure UART3
+ cmp \rp, #ZOOM_UART @ only on zoom2/3
+ beq 95f @ configure ZOOM_UART
+
+@@ -91,6 +97,12 @@ omap_uart_lsr: .word 0
+ b 98f
+ 44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
+ b 98f
++81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE)
++ b 98f
++82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE)
++ b 98f
++83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
++ b 98f
+ 95: ldr \rp, =ZOOM_UART_BASE
+ mrc p15, 0, \rv, c1, c0
+ tst \rv, #1 @ MMU enabled?
+diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
+index a1a118d..8061695 100644
+--- a/arch/arm/plat-omap/include/plat/serial.h
++++ b/arch/arm/plat-omap/include/plat/serial.h
+@@ -51,6 +51,11 @@
+ #define OMAP4_UART3_BASE 0x48020000
+ #define OMAP4_UART4_BASE 0x4806e000
+
++/* TI816X serial ports */
++#define TI816X_UART1_BASE 0x48020000
++#define TI816X_UART2_BASE 0x48022000
++#define TI816X_UART3_BASE 0x48024000
++
+ /* External port on Zoom2/3 */
+ #define ZOOM_UART_BASE 0x10000000
+ #define ZOOM_UART_VIRT 0xfa400000
+@@ -81,6 +86,9 @@
+ #define OMAP4UART2 OMAP2UART2
+ #define OMAP4UART3 43
+ #define OMAP4UART4 44
++#define TI816XUART1 81
++#define TI816XUART2 82
++#define TI816XUART3 83
+ #define ZOOM_UART 95 /* Only on zoom2/3 */
+
+ /* This is only used by 8250.c for omap1510 */
+diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
+index ad98b85..30b891c 100644
+--- a/arch/arm/plat-omap/include/plat/uncompress.h
++++ b/arch/arm/plat-omap/include/plat/uncompress.h
+@@ -93,6 +93,10 @@ static inline void flush(void)
+ #define DEBUG_LL_ZOOM(mach) \
+ _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
+
++#define DEBUG_LL_TI816X(p, mach) \
++ _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \
++ TI816XUART##p)
++
+ static inline void __arch_decomp_setup(unsigned long arch_id)
+ {
+ int port = 0;
+@@ -166,6 +170,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
+ DEBUG_LL_ZOOM(omap_zoom2);
+ DEBUG_LL_ZOOM(omap_zoom3);
+
++ /* TI8168 base boards using UART3 */
++ DEBUG_LL_TI816X(3, ti8168evm);
++
+ } while (0);
+ }
+
+--
+1.7.1
+
diff --git a/patches/for_next/0027-TI816X-Update-to-use-init_early.patch b/patches/for_next/0027-TI816X-Update-to-use-init_early.patch
new file mode 100644
index 0000000000000000000000000000000000000000..ee0873a080cdc8b06b1b0c30ac5fb3923489a127
--- /dev/null
+++ b/patches/for_next/0027-TI816X-Update-to-use-init_early.patch
@@ -0,0 +1,45 @@
+From 2d0431646aaacd07a607c16bc543fb110f21d0bc Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Wed, 16 Feb 2011 08:45:46 -0800
+Subject: [PATCH 027/254] TI816X: Update to use init_early
+
+Update to use init_early
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-ti8168evm.c | 7 ++++++-
+ 1 files changed, 6 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
+index 6282cc4..f2b0971 100644
+--- a/arch/arm/mach-omap2/board-ti8168evm.c
++++ b/arch/arm/mach-omap2/board-ti8168evm.c
+@@ -27,12 +27,16 @@
+ static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+ };
+
+-static void __init ti8168_evm_init_irq(void)
++static void __init ti8168_init_early(void)
+ {
+ omap_board_config = ti8168_evm_config;
+ omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
++}
++
++static void __init ti8168_evm_init_irq(void)
++{
+ omap_init_irq();
+ }
+
+@@ -51,6 +55,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
+ /* Maintainer: Texas Instruments */
+ .boot_params = 0x80000100,
+ .map_io = ti8168_evm_map_io,
++ .init_early = ti8168_init_early,
+ .init_irq = ti8168_evm_init_irq,
+ .timer = &omap_timer,
+ .init_machine = ti8168_evm_init,
+--
+1.7.1
+
diff --git a/patches/for_next/0028-arm-omap2-clksel-fix-compile-warningOrganization-Tex.patch b/patches/for_next/0028-arm-omap2-clksel-fix-compile-warningOrganization-Tex.patch
new file mode 100644
index 0000000000000000000000000000000000000000..442f8332fb85f8b3372b2c1e52dd3c72dbf55855
--- /dev/null
+++ b/patches/for_next/0028-arm-omap2-clksel-fix-compile-warningOrganization-Tex.patch
@@ -0,0 +1,33 @@
+From 41e2a921d455d74dfeabab4cffc6a814b4f247be Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Sun, 16 Jan 2011 13:22:03 +0200
+Subject: [PATCH 028/254] arm: omap2: clksel: fix compile warningOrganization: Texas Instruments\n
+
+Fix the following compile warning:
+arch/arm/mach-omap2/clkt_clksel.c: In function '_get_div_and_fieldval':
+arch/arm/mach-omap2/clkt_clksel.c:100:35: warning: 'max_clkr' may be
+used uninitialized in this function
+
+Acked-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/clkt_clksel.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
+index a781cd6..e25364d 100644
+--- a/arch/arm/mach-omap2/clkt_clksel.c
++++ b/arch/arm/mach-omap2/clkt_clksel.c
+@@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
+ u32 *field_val)
+ {
+ const struct clksel *clks;
+- const struct clksel_rate *clkr, *max_clkr;
++ const struct clksel_rate *clkr, *max_clkr = NULL;
+ u8 max_div = 0;
+
+ clks = _get_clksel_by_parent(clk, src_clk);
+--
+1.7.1
+
diff --git a/patches/for_next/0029-OMAP4-hwmod-data-Add-hwspinlock.patch b/patches/for_next/0029-OMAP4-hwmod-data-Add-hwspinlock.patch
new file mode 100644
index 0000000000000000000000000000000000000000..184366fbd210dbad2490d33d396db17ebee3cbf8
--- /dev/null
+++ b/patches/for_next/0029-OMAP4-hwmod-data-Add-hwspinlock.patch
@@ -0,0 +1,110 @@
+From a12886b3b1d8dbd5fb903a3b69c3e4e218ddb532 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Wed, 2 Feb 2011 12:04:36 +0000
+Subject: [PATCH 029/254] OMAP4: hwmod data: Add hwspinlock
+
+Add hwspinlock hwmod data for OMAP4 chip
+
+Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
+Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
+Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+[b-cousson@ti.com: Move the data to keep the original
+order and add missing SIDLE_SMART_WKUP flag]
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 65 +++++++++++++++++++++++++++-
+ 1 files changed, 64 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index c2806bd..46da576 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -555,7 +555,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * sl2if
+ * slimbus1
+ * slimbus2
+- * spinlock
+ * timer1
+ * timer10
+ * timer11
+@@ -1639,6 +1638,67 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+ };
+
+ /*
++ * 'spinlock' class
++ * spinlock provides hardware assistance for synchronizing the processes
++ * running on multiple processors
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
++ .name = "spinlock",
++ .sysc = &omap44xx_spinlock_sysc,
++};
++
++/* spinlock */
++static struct omap_hwmod omap44xx_spinlock_hwmod;
++static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
++ {
++ .pa_start = 0x4a0f6000,
++ .pa_end = 0x4a0f6fff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_cfg -> spinlock */
++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
++ .master = &omap44xx_l4_cfg_hwmod,
++ .slave = &omap44xx_spinlock_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_spinlock_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* spinlock slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
++ &omap44xx_l4_cfg__spinlock,
++};
++
++static struct omap_hwmod omap44xx_spinlock_hwmod = {
++ .name = "spinlock",
++ .class = &omap44xx_spinlock_hwmod_class,
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_spinlock_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+@@ -2058,6 +2118,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ &omap44xx_smartreflex_iva_hwmod,
+ &omap44xx_smartreflex_mpu_hwmod,
+
++ /* spinlock class */
++ &omap44xx_spinlock_hwmod,
++
+ /* uart class */
+ &omap44xx_uart1_hwmod,
+ &omap44xx_uart2_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0030-usb-musb-AM35x-moving-internal-phy-functions-out-of-.patch b/patches/for_next/0030-usb-musb-AM35x-moving-internal-phy-functions-out-of-.patch
new file mode 100644
index 0000000000000000000000000000000000000000..92fa0b4c2e90bf836c3fa90f0061861b1aaed53e
--- /dev/null
+++ b/patches/for_next/0030-usb-musb-AM35x-moving-internal-phy-functions-out-of-.patch
@@ -0,0 +1,296 @@
+From a66b7f42d9a669688d38fd1a5186a79612caaca1 Mon Sep 17 00:00:00 2001
+From: Hema HK <hemahk@ti.com>
+Date: Wed, 16 Feb 2011 17:34:40 +0530
+Subject: [PATCH 030/254] usb: musb: AM35x: moving internal phy functions out of usb_musb.c file
+
+Moved all the board specific internal PHY functions out of usb_musb.c file
+as this file is shared between the OMAP2+ and AM35xx platforms.
+There exists a file which has the functions specific to internal PHY
+used for OMAP4 platform. Moved all phy specific functions to this file
+and passing these functions through board data in the board file.
+
+Signed-off-by: Hema HK <hemahk@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 3 +-
+ arch/arm/mach-omap2/board-am3517evm.c | 4 +
+ arch/arm/mach-omap2/omap_phy_internal.c | 93 +++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/usb-musb.c | 97 -------------------------------
+ arch/arm/plat-omap/include/plat/usb.h | 4 +
+ 5 files changed, 103 insertions(+), 98 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index a9e3974..4919e09 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -218,7 +218,8 @@ obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \
+ hsmmc.o \
+ omap_phy_internal.o
+
+-obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
++obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \
++ omap_phy_internal.o \
+
+ obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
+
+diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
+index d0d0f55..8532d6e 100644
+--- a/arch/arm/mach-omap2/board-am3517evm.c
++++ b/arch/arm/mach-omap2/board-am3517evm.c
+@@ -408,6 +408,10 @@ static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 500,
++ .set_phy_power = am35x_musb_phy_power,
++ .clear_irq = am35x_musb_clear_irq,
++ .set_mode = am35x_musb_set_mode,
++ .reset = am35x_musb_reset,
+ };
+
+ static __init void am3517_evm_musb_init(void)
+diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
+index 745252c..f172ec0 100644
+--- a/arch/arm/mach-omap2/omap_phy_internal.c
++++ b/arch/arm/mach-omap2/omap_phy_internal.c
+@@ -29,6 +29,7 @@
+ #include <linux/usb.h>
+
+ #include <plat/usb.h>
++#include "control.h"
+
+ /* OMAP control module register for UTMI PHY */
+ #define CONTROL_DEV_CONF 0x300
+@@ -147,3 +148,95 @@ int omap4430_phy_exit(struct device *dev)
+
+ return 0;
+ }
++
++void am35x_musb_reset(void)
++{
++ u32 regval;
++
++ /* Reset the musb interface */
++ regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
++
++ regval |= AM35XX_USBOTGSS_SW_RST;
++ omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
++
++ regval &= ~AM35XX_USBOTGSS_SW_RST;
++ omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
++
++ regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
++}
++
++void am35x_musb_phy_power(u8 on)
++{
++ unsigned long timeout = jiffies + msecs_to_jiffies(100);
++ u32 devconf2;
++
++ if (on) {
++ /*
++ * Start the on-chip PHY and its PLL.
++ */
++ devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
++
++ devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
++ devconf2 |= CONF2_PHY_PLLON;
++
++ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
++
++ pr_info(KERN_INFO "Waiting for PHY clock good...\n");
++ while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
++ & CONF2_PHYCLKGD)) {
++ cpu_relax();
++
++ if (time_after(jiffies, timeout)) {
++ pr_err(KERN_ERR "musb PHY clock good timed out\n");
++ break;
++ }
++ }
++ } else {
++ /*
++ * Power down the on-chip PHY.
++ */
++ devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
++
++ devconf2 &= ~CONF2_PHY_PLLON;
++ devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
++ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
++ }
++}
++
++void am35x_musb_clear_irq(void)
++{
++ u32 regval;
++
++ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
++ regval |= AM35XX_USBOTGSS_INT_CLR;
++ omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
++ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
++}
++
++void am35x_musb_set_mode(u8 musb_mode)
++{
++ u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
++
++ devconf2 &= ~CONF2_OTGMODE;
++ switch (musb_mode) {
++#ifdef CONFIG_USB_MUSB_HDRC_HCD
++ case MUSB_HOST: /* Force VBUS valid, ID = 0 */
++ devconf2 |= CONF2_FORCE_HOST;
++ break;
++#endif
++#ifdef CONFIG_USB_GADGET_MUSB_HDRC
++ case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
++ devconf2 |= CONF2_FORCE_DEVICE;
++ break;
++#endif
++#ifdef CONFIG_USB_MUSB_OTG
++ case MUSB_OTG: /* Don't override the VBUS/ID comparators */
++ devconf2 |= CONF2_NO_OVERRIDE;
++ break;
++#endif
++ default:
++ pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
++ }
++
++ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
++}
+diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
+index 5298949..9107883 100644
+--- a/arch/arm/mach-omap2/usb-musb.c
++++ b/arch/arm/mach-omap2/usb-musb.c
+@@ -30,102 +30,9 @@
+ #include <mach/irqs.h>
+ #include <mach/am35xx.h>
+ #include <plat/usb.h>
+-#include "control.h"
+
+ #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
+
+-static void am35x_musb_reset(void)
+-{
+- u32 regval;
+-
+- /* Reset the musb interface */
+- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+-
+- regval |= AM35XX_USBOTGSS_SW_RST;
+- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+-
+- regval &= ~AM35XX_USBOTGSS_SW_RST;
+- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+-
+- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+-}
+-
+-static void am35x_musb_phy_power(u8 on)
+-{
+- unsigned long timeout = jiffies + msecs_to_jiffies(100);
+- u32 devconf2;
+-
+- if (on) {
+- /*
+- * Start the on-chip PHY and its PLL.
+- */
+- devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+-
+- devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
+- devconf2 |= CONF2_PHY_PLLON;
+-
+- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+-
+- pr_info(KERN_INFO "Waiting for PHY clock good...\n");
+- while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
+- & CONF2_PHYCLKGD)) {
+- cpu_relax();
+-
+- if (time_after(jiffies, timeout)) {
+- pr_err(KERN_ERR "musb PHY clock good timed out\n");
+- break;
+- }
+- }
+- } else {
+- /*
+- * Power down the on-chip PHY.
+- */
+- devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+-
+- devconf2 &= ~CONF2_PHY_PLLON;
+- devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
+- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+- }
+-}
+-
+-static void am35x_musb_clear_irq(void)
+-{
+- u32 regval;
+-
+- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+- regval |= AM35XX_USBOTGSS_INT_CLR;
+- omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+-}
+-
+-static void am35x_musb_set_mode(u8 musb_mode)
+-{
+- u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+-
+- devconf2 &= ~CONF2_OTGMODE;
+- switch (musb_mode) {
+-#ifdef CONFIG_USB_MUSB_HDRC_HCD
+- case MUSB_HOST: /* Force VBUS valid, ID = 0 */
+- devconf2 |= CONF2_FORCE_HOST;
+- break;
+-#endif
+-#ifdef CONFIG_USB_GADGET_MUSB_HDRC
+- case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
+- devconf2 |= CONF2_FORCE_DEVICE;
+- break;
+-#endif
+-#ifdef CONFIG_USB_MUSB_OTG
+- case MUSB_OTG: /* Don't override the VBUS/ID comparators */
+- devconf2 |= CONF2_NO_OVERRIDE;
+- break;
+-#endif
+- default:
+- pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
+- }
+-
+- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+-}
+-
+ static struct resource musb_resources[] = {
+ [0] = { /* start and end set dynamically */
+ .flags = IORESOURCE_MEM,
+@@ -189,10 +96,6 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
+ musb_device.name = "musb-am35x";
+ musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE;
+ musb_resources[1].start = INT_35XX_USBOTG_IRQ;
+- board_data->set_phy_power = am35x_musb_phy_power;
+- board_data->clear_irq = am35x_musb_clear_irq;
+- board_data->set_mode = am35x_musb_set_mode;
+- board_data->reset = am35x_musb_reset;
+ } else if (cpu_is_omap34xx()) {
+ musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
+ } else if (cpu_is_omap44xx()) {
+diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
+index 450a332..0771927 100644
+--- a/arch/arm/plat-omap/include/plat/usb.h
++++ b/arch/arm/plat-omap/include/plat/usb.h
+@@ -91,6 +91,10 @@ extern int omap4430_phy_exit(struct device *dev);
+
+ #endif
+
++extern void am35x_musb_reset(void);
++extern void am35x_musb_phy_power(u8 on);
++extern void am35x_musb_clear_irq(void);
++extern void am35x_musb_set_mode(u8 musb_mode);
+
+ /*
+ * FIXME correct answer depends on hmc_mode,
+--
+1.7.1
+
diff --git a/patches/for_next/0031-arm-omap4-usb-explicitly-configure-MUSB-pads.patch b/patches/for_next/0031-arm-omap4-usb-explicitly-configure-MUSB-pads.patch
new file mode 100644
index 0000000000000000000000000000000000000000..592949dbd5d60d84d9e87a917bad337289357cd0
--- /dev/null
+++ b/patches/for_next/0031-arm-omap4-usb-explicitly-configure-MUSB-pads.patch
@@ -0,0 +1,85 @@
+From 8ace0283bc31cec3b631789cee54720b109b7fa5 Mon Sep 17 00:00:00 2001
+From: Anand Gadiyar <gadiyar@ti.com>
+Date: Wed, 16 Feb 2011 15:42:15 +0530
+Subject: [PATCH 031/254] arm: omap4: usb: explicitly configure MUSB pads
+
+Use the mux framework APIs to explicitly configure
+the MUSB pads. The MUSB controller in OMAP4 can use
+either the old ULPI interface, or the new internal PHY.
+Configure the pads accordingly.
+
+Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+---
+ arch/arm/mach-omap2/usb-musb.c | 40 ++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 40 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
+index 9107883..9788b49 100644
+--- a/arch/arm/mach-omap2/usb-musb.c
++++ b/arch/arm/mach-omap2/usb-musb.c
+@@ -30,6 +30,7 @@
+ #include <mach/irqs.h>
+ #include <mach/am35xx.h>
+ #include <plat/usb.h>
++#include "mux.h"
+
+ #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
+
+@@ -88,6 +89,43 @@ static struct platform_device musb_device = {
+ .resource = musb_resources,
+ };
+
++static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
++{
++ switch (board_data->interface_type) {
++ case MUSB_INTERFACE_UTMI:
++ omap_mux_init_signal("usba0_otg_dp", OMAP_PIN_INPUT);
++ omap_mux_init_signal("usba0_otg_dm", OMAP_PIN_INPUT);
++ break;
++ case MUSB_INTERFACE_ULPI:
++ omap_mux_init_signal("usba0_ulpiphy_clk",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_stp",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dir",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_nxt",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dat0",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dat1",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dat2",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dat3",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dat4",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dat5",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dat6",
++ OMAP_PIN_INPUT_PULLDOWN);
++ omap_mux_init_signal("usba0_ulpiphy_dat7",
++ OMAP_PIN_INPUT_PULLDOWN);
++ break;
++ default:
++ break;
++ }
++}
+ void __init usb_musb_init(struct omap_musb_board_data *board_data)
+ {
+ if (cpu_is_omap243x()) {
+@@ -102,6 +140,8 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
+ musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
+ musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
+ musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
++
++ usb_musb_mux_init(board_data);
+ }
+ musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
+
+--
+1.7.1
+
diff --git a/patches/for_next/0032-arm-omap4-4430sdp-drop-ehci-support.patch b/patches/for_next/0032-arm-omap4-4430sdp-drop-ehci-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7621f6450de214eebeae4ef2774989a968d73b94
--- /dev/null
+++ b/patches/for_next/0032-arm-omap4-4430sdp-drop-ehci-support.patch
@@ -0,0 +1,80 @@
+From 3b44dbbc7773d2aa47f74d9c6a4c29104d87c937 Mon Sep 17 00:00:00 2001
+From: Anand Gadiyar <gadiyar@ti.com>
+Date: Wed, 16 Feb 2011 16:47:19 +0530
+Subject: [PATCH 032/254] arm: omap4: 4430sdp: drop ehci support
+
+Most revisions of the OMAP4 Blaze/SDP platform do not have
+the EHCI signals routed by default. The pads are routed
+for the alternate HSI functionality instead, and explicit
+board modifications are needed to route the signals to
+the USB PHY on the board.
+
+Also, turning on the PHY connected to the EHCI port causes
+a board reboot during bootup due to an unintended short
+on the rails - this affects many initial revisions of the
+board, and needs a minor board mod to fix (or as a
+workaround, one should not attempt to power on the
+USB PHY).
+
+Given that these boards need explicit board mods to even
+get EHCI working (separate from the accidental short above),
+we should not attempt to enable EHCI by default.
+
+So drop the EHCI support from the board files for the
+Blaze/SDP platforms.
+
+Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
+Cc: Keshava Munegowda <keshava_mgowda@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+---
+ arch/arm/mach-omap2/board-4430sdp.c | 19 -------------------
+ 1 files changed, 0 insertions(+), 19 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index 12d99e5..bf82684 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -44,7 +44,6 @@
+ #define ETH_KS8851_IRQ 34
+ #define ETH_KS8851_POWER_ON 48
+ #define ETH_KS8851_QUART 138
+-#define OMAP4SDP_MDM_PWR_EN_GPIO 157
+ #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
+ #define OMAP4_SFH7741_ENABLE_GPIO 188
+
+@@ -250,16 +249,6 @@ static void __init omap_4430sdp_init_early(void)
+ #endif
+ }
+
+-static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+- .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+- .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+- .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+- .phy_reset = false,
+- .reset_gpio_port[0] = -EINVAL,
+- .reset_gpio_port[1] = -EINVAL,
+- .reset_gpio_port[2] = -EINVAL,
+-};
+-
+ static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_UTMI,
+ .mode = MUSB_OTG,
+@@ -575,14 +564,6 @@ static void __init omap_4430sdp_init(void)
+ omap_serial_init();
+ omap4_twl6030_hsmmc_init(mmc);
+
+- /* Power on the ULPI PHY */
+- status = gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3");
+- if (status)
+- pr_err("%s: Could not get USBB1 PHY GPIO\n", __func__);
+- else
+- gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1);
+-
+- usb_ehci_init(&ehci_pdata);
+ usb_musb_init(&musb_board_data);
+
+ status = omap_ethernet_init();
+--
+1.7.1
+
diff --git a/patches/for_next/0033-OMAP2430-hwmod-data-Add-USBOTG.patch b/patches/for_next/0033-OMAP2430-hwmod-data-Add-USBOTG.patch
new file mode 100644
index 0000000000000000000000000000000000000000..dfba1ff05e8f81ea116af27aaf3662b98b57f6fb
--- /dev/null
+++ b/patches/for_next/0033-OMAP2430-hwmod-data-Add-USBOTG.patch
@@ -0,0 +1,158 @@
+From ccb02d8791f90552e6da5479081e4beef39a700b Mon Sep 17 00:00:00 2001
+From: Hema HK <hemahk@ti.com>
+Date: Thu, 17 Feb 2011 12:07:17 +0530
+Subject: [PATCH 033/254] OMAP2430: hwmod data: Add USBOTG
+
+OMAP2430 hwmod data structures are populated with base address, L3 and L4
+interface clocks, IRQs and sysconfig register details.
+
+As per OMAP USBOTG specification, need to configure the USBOTG
+to smart idle/standby or no idle/standby during data transfer and
+force idle/standby when not in use to support retention and off-mode.
+By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags, framework
+will take care of configuring to no idle/standby when module is enabled
+and force idle/standby when suspended.
+
+Signed-off-by: Hema HK <hemahk@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Kevin Hilman <khilman@deeprootsystems.com>
+Cc: Cousson, Benoit <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 98 ++++++++++++++++++++++++++++
+ 1 files changed, 98 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 8ecfbcd..76bbf8a 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -89,6 +89,16 @@ static struct omap_hwmod omap2430_uart3_hwmod;
+ static struct omap_hwmod omap2430_i2c1_hwmod;
+ static struct omap_hwmod omap2430_i2c2_hwmod;
+
++static struct omap_hwmod omap2430_usbhsotg_hwmod;
++
++/* l3_core -> usbhsotg interface */
++static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
++ .master = &omap2430_usbhsotg_hwmod,
++ .slave = &omap2430_l3_main_hwmod,
++ .clk = "core_l3_ck",
++ .user = OCP_USER_MPU,
++};
++
+ /* I2C IP block address space length (in bytes) */
+ #define OMAP2_I2C_AS_LEN 128
+
+@@ -189,6 +199,35 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
++/*
++* usbhsotg interface data
++*/
++static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
++ {
++ .pa_start = OMAP243X_HS_BASE,
++ .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core ->usbhsotg interface */
++static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_usbhsotg_hwmod,
++ .clk = "usb_l4_ick",
++ .addr = omap2430_usbhsotg_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
++ &omap2430_usbhsotg__l3,
++};
++
++static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
++ &omap2430_l4_core__usbhsotg,
++};
++
+ /* Slave interfaces on the L4_CORE interconnect */
+ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
+ &omap2430_l3_main__l4_core,
+@@ -919,6 +958,62 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
++/*
++ * usbhsotg
++ */
++static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
++ .rev_offs = 0x0400,
++ .sysc_offs = 0x0404,
++ .syss_offs = 0x0408,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class usbotg_class = {
++ .name = "usbotg",
++ .sysc = &omap2430_usbhsotg_sysc,
++};
++
++/* usb_otg_hs */
++static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
++
++ { .name = "mc", .irq = 92 },
++ { .name = "dma", .irq = 93 },
++};
++
++static struct omap_hwmod omap2430_usbhsotg_hwmod = {
++ .name = "usb_otg_hs",
++ .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
++ .main_clk = "usbhs_ick",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP2430_EN_USBHS_MASK,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
++ },
++ },
++ .masters = omap2430_usbhsotg_masters,
++ .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
++ .slaves = omap2430_usbhsotg_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
++ .class = &usbotg_class,
++ /*
++ * Erratum ID: i479 idle_req / idle_ack mechanism potentially
++ * broken when autoidle is enabled
++ * workaround is to disable the autoidle bit at module level.
++ */
++ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
++ | HWMOD_SWSUP_MSTANDBY,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
+ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ &omap2430_l3_main_hwmod,
+ &omap2430_l4_core_hwmod,
+@@ -941,6 +1036,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+
+ /* dma_system class*/
+ &omap2430_dma_system_hwmod,
++
++ /* usbotg class*/
++ &omap2430_usbhsotg_hwmod,
+ NULL,
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0034-OMAP3xxx-hwmod-data-Add-USBOTG.patch b/patches/for_next/0034-OMAP3xxx-hwmod-data-Add-USBOTG.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8c5c29b653b72e8cdb33269fd254afb87f79bfad
--- /dev/null
+++ b/patches/for_next/0034-OMAP3xxx-hwmod-data-Add-USBOTG.patch
@@ -0,0 +1,162 @@
+From 2890b5f2c8c61aae4599fee3a86e025d6461b2fd Mon Sep 17 00:00:00 2001
+From: Hema HK <hemahk@ti.com>
+Date: Thu, 17 Feb 2011 12:07:18 +0530
+Subject: [PATCH 034/254] OMAP3xxx: hwmod data: Add USBOTG
+
+OMAP3 hwmod data structures are populated for USBOTG with base address,
+L3 and L4 interface clocks, IRQs and sysconfig register details.
+This is applicable for OMAP3430 amd OMAP3630.
+
+As per OMAP USBOTG specification, need to configure the USBOTG
+to smart idle/standby or no idle/standby during data transfer and
+force idle/standby when not in use to support retention and offmode.
+By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags, framework
+will take care of configuring to no idle/standby when module is enabled
+and force idle/standby when idled.
+
+Signed-off-by: Hema HK <hemahk@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Kevin Hilman <khilman@deeprootsystems.com>
+Cc: Cousson, Benoit <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 101 ++++++++++++++++++++++++++++
+ 1 files changed, 101 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 8d81813..cce09fd 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -107,6 +107,15 @@ static struct omap_hwmod omap3xxx_uart1_hwmod;
+ static struct omap_hwmod omap3xxx_uart2_hwmod;
+ static struct omap_hwmod omap3xxx_uart3_hwmod;
+ static struct omap_hwmod omap3xxx_uart4_hwmod;
++static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
++
++/* l3_core -> usbhsotg interface */
++static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
++ .master = &omap3xxx_usbhsotg_hwmod,
++ .slave = &omap3xxx_l3_main_hwmod,
++ .clk = "core_l3_ick",
++ .user = OCP_USER_MPU,
++};
+
+ /* L4_CORE -> L4_WKUP interface */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
+@@ -301,6 +310,36 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
+ .user = OCP_USER_MPU,
+ };
+
++/*
++* usbhsotg interface data
++*/
++
++static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
++ {
++ .pa_start = OMAP34XX_HSUSB_OTG_BASE,
++ .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> usbhsotg */
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_usbhsotg_hwmod,
++ .clk = "l4_ick",
++ .addr = omap3xxx_usbhsotg_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
++ &omap3xxx_usbhsotg__l3,
++};
++
++static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
++ &omap3xxx_l4_core__usbhsotg,
++};
++
+ /* Slave interfaces on the L4_CORE interconnect */
+ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
+ &omap3xxx_l3_main__l4_core,
+@@ -1356,6 +1395,64 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ };
+
++/*
++ * usbhsotg
++ */
++static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
++ .rev_offs = 0x0400,
++ .sysc_offs = 0x0404,
++ .syss_offs = 0x0408,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class usbotg_class = {
++ .name = "usbotg",
++ .sysc = &omap3xxx_usbhsotg_sysc,
++};
++
++/* usb_otg_hs */
++static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
++
++ { .name = "mc", .irq = 92 },
++ { .name = "dma", .irq = 93 },
++};
++
++static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
++ .name = "usb_otg_hs",
++ .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
++ .main_clk = "hsotgusb_ick",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
++ .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
++ },
++ },
++ .masters = omap3xxx_usbhsotg_masters,
++ .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
++ .slaves = omap3xxx_usbhsotg_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
++ .class = &usbotg_class,
++
++ /*
++ * Erratum ID: i479 idle_req / idle_ack mechanism potentially
++ * broken when autoidle is enabled
++ * workaround is to disable the autoidle bit at module level.
++ */
++ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
++ | HWMOD_SWSUP_MSTANDBY,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
+ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ &omap3xxx_l3_main_hwmod,
+ &omap3xxx_l4_core_hwmod,
+@@ -1387,6 +1484,10 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+
+ /* dma_system class*/
+ &omap3xxx_dma_system_hwmod,
++
++ /* usbotg class */
++ &omap3xxx_usbhsotg_hwmod,
++
+ NULL,
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0035-AM35xx-hwmod-data-Add-USBOTG.patch b/patches/for_next/0035-AM35xx-hwmod-data-Add-USBOTG.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f546aea153d9766dcf4adfd7b3f84e70a4fd594f
--- /dev/null
+++ b/patches/for_next/0035-AM35xx-hwmod-data-Add-USBOTG.patch
@@ -0,0 +1,132 @@
+From 246d642906fbfbb8469eb0835f088d9d0b04f075 Mon Sep 17 00:00:00 2001
+From: Hema HK <hemahk@ti.com>
+Date: Thu, 17 Feb 2011 12:07:19 +0530
+Subject: [PATCH 035/254] AM35xx: hwmod data: Add USBOTG
+
+AM35xx hwmod data structures are populated for USBOTG with base address,
+L3 and L4 interface clocks and IRQ.
+
+Signed-off-by: Hema HK <hemahk@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Kevin Hilman <khilman@deeprootsystems.com>
+Cc: Cousson, Benoit <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 65 ++++++++++++++++++++++++++++
+ 1 files changed, 65 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index cce09fd..b4cd8dd 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -28,6 +28,7 @@
+ #include "prm-regbits-34xx.h"
+ #include "cm-regbits-34xx.h"
+ #include "wd_timer.h"
++#include <mach/am35xx.h>
+
+ /*
+ * OMAP3xxx hardware module integration data
+@@ -55,6 +56,8 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod;
+ static struct omap_hwmod omap3xxx_gpio6_hwmod;
+ static struct omap_hwmod omap34xx_sr1_hwmod;
+ static struct omap_hwmod omap34xx_sr2_hwmod;
++static struct omap_hwmod am35xx_usbhsotg_hwmod;
++
+
+ static struct omap_hwmod omap3xxx_dma_system_hwmod;
+
+@@ -117,6 +120,13 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
+ .user = OCP_USER_MPU,
+ };
+
++/* l3_core -> am35xx_usbhsotg interface */
++static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
++ .master = &am35xx_usbhsotg_hwmod,
++ .slave = &omap3xxx_l3_main_hwmod,
++ .clk = "core_l3_ick",
++ .user = OCP_USER_MPU,
++};
+ /* L4_CORE -> L4_WKUP interface */
+ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
+ .master = &omap3xxx_l4_core_hwmod,
+@@ -340,6 +350,31 @@ static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
+ &omap3xxx_l4_core__usbhsotg,
+ };
+
++static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
++ {
++ .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
++ .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> usbhsotg */
++static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &am35xx_usbhsotg_hwmod,
++ .clk = "l4_ick",
++ .addr = am35xx_usbhsotg_addrs,
++ .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
++ &am35xx_usbhsotg__l3,
++};
++
++static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
++ &am35xx_l4_core__usbhsotg,
++};
+ /* Slave interfaces on the L4_CORE interconnect */
+ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
+ &omap3xxx_l3_main__l4_core,
+@@ -1452,6 +1487,33 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
+ | HWMOD_SWSUP_MSTANDBY,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ };
++/* usb_otg_hs */
++static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
++
++ { .name = "mc", .irq = 71 },
++};
++
++static struct omap_hwmod_class am35xx_usbotg_class = {
++ .name = "am35xx_usbotg",
++ .sysc = NULL,
++};
++
++static struct omap_hwmod am35xx_usbhsotg_hwmod = {
++ .name = "am35x_otg_hs",
++ .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
++ .main_clk = NULL,
++ .prcm = {
++ .omap2 = {
++ },
++ },
++ .masters = am35xx_usbhsotg_masters,
++ .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
++ .slaves = am35xx_usbhsotg_slaves,
++ .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
++ .class = &am35xx_usbotg_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
++};
+
+ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ &omap3xxx_l3_main_hwmod,
+@@ -1488,6 +1550,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ /* usbotg class */
+ &omap3xxx_usbhsotg_hwmod,
+
++ /* usbotg for am35x */
++ &am35xx_usbhsotg_hwmod,
++
+ NULL,
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0036-OMAP2-musb-hwmod-adaptation-for-musb-registration.patch b/patches/for_next/0036-OMAP2-musb-hwmod-adaptation-for-musb-registration.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d4a1e6fc4bbb3e98c56b0ffd6c798fe0278d485d
--- /dev/null
+++ b/patches/for_next/0036-OMAP2-musb-hwmod-adaptation-for-musb-registration.patch
@@ -0,0 +1,149 @@
+From e4b7071ae4238d74e55565371e79e22b791e5e31 Mon Sep 17 00:00:00 2001
+From: Hema HK <hemahk@ti.com>
+Date: Thu, 17 Feb 2011 12:07:21 +0530
+Subject: [PATCH 036/254] OMAP2+: musb: hwmod adaptation for musb registration
+
+Using omap_device_build API instead of platform_device_register for
+OMAP2430,OMAP3xxx, OMAP4430 and AM35x musb device registration.
+The device specific resources defined in centralized
+database will be used.
+
+Signed-off-by: Hema HK <hemahk@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Kevin Hilman <khilman@deeprootsystems.com>
+Cc: Cousson, Benoit <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+---
+ arch/arm/mach-omap2/usb-musb.c | 84 +++++++++++++++++++++-------------------
+ 1 files changed, 44 insertions(+), 40 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
+index 9788b49..a9d4d14 100644
+--- a/arch/arm/mach-omap2/usb-musb.c
++++ b/arch/arm/mach-omap2/usb-musb.c
+@@ -30,26 +30,11 @@
+ #include <mach/irqs.h>
+ #include <mach/am35xx.h>
+ #include <plat/usb.h>
++#include <plat/omap_device.h>
+ #include "mux.h"
+
+ #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
+
+-static struct resource musb_resources[] = {
+- [0] = { /* start and end set dynamically */
+- .flags = IORESOURCE_MEM,
+- },
+- [1] = { /* general IRQ */
+- .start = INT_243X_HS_USB_MC,
+- .flags = IORESOURCE_IRQ,
+- .name = "mc",
+- },
+- [2] = { /* DMA IRQ */
+- .start = INT_243X_HS_USB_DMA,
+- .flags = IORESOURCE_IRQ,
+- .name = "dma",
+- },
+-};
+-
+ static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+@@ -77,16 +62,12 @@ static struct musb_hdrc_platform_data musb_plat = {
+
+ static u64 musb_dmamask = DMA_BIT_MASK(32);
+
+-static struct platform_device musb_device = {
+- .name = "musb-omap2430",
+- .id = -1,
+- .dev = {
+- .dma_mask = &musb_dmamask,
+- .coherent_dma_mask = DMA_BIT_MASK(32),
+- .platform_data = &musb_plat,
++static struct omap_device_pm_latency omap_musb_latency[] = {
++ {
++ .deactivate_func = omap_device_idle_hwmods,
++ .activate_func = omap_device_enable_hwmods,
++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+- .num_resources = ARRAY_SIZE(musb_resources),
+- .resource = musb_resources,
+ };
+
+ static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
+@@ -126,24 +107,20 @@ static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
+ break;
+ }
+ }
++
+ void __init usb_musb_init(struct omap_musb_board_data *board_data)
+ {
+- if (cpu_is_omap243x()) {
+- musb_resources[0].start = OMAP243X_HS_BASE;
+- } else if (cpu_is_omap3517() || cpu_is_omap3505()) {
+- musb_device.name = "musb-am35x";
+- musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE;
+- musb_resources[1].start = INT_35XX_USBOTG_IRQ;
+- } else if (cpu_is_omap34xx()) {
+- musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
+- } else if (cpu_is_omap44xx()) {
+- musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
+- musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
+- musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
++ struct omap_hwmod *oh;
++ struct omap_device *od;
++ struct platform_device *pdev;
++ struct device *dev;
++ int bus_id = -1;
++ const char *oh_name, *name;
+
++ if (cpu_is_omap3517() || cpu_is_omap3505()) {
++ } else if (cpu_is_omap44xx()) {
+ usb_musb_mux_init(board_data);
+ }
+- musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
+
+ /*
+ * REVISIT: This line can be removed once all the platforms using
+@@ -155,8 +132,35 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
+ musb_plat.mode = board_data->mode;
+ musb_plat.extvbus = board_data->extvbus;
+
+- if (platform_device_register(&musb_device) < 0)
+- printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
++ if (cpu_is_omap3517() || cpu_is_omap3505()) {
++ oh_name = "am35x_otg_hs";
++ name = "musb-am35x";
++ } else {
++ oh_name = "usb_otg_hs";
++ name = "musb-omap2430";
++ }
++
++ oh = omap_hwmod_lookup(oh_name);
++ if (!oh) {
++ pr_err("Could not look up %s\n", oh_name);
++ return;
++ }
++
++ od = omap_device_build(name, bus_id, oh, &musb_plat,
++ sizeof(musb_plat), omap_musb_latency,
++ ARRAY_SIZE(omap_musb_latency), false);
++ if (IS_ERR(od)) {
++ pr_err("Could not build omap_device for %s %s\n",
++ name, oh_name);
++ return;
++ }
++
++ pdev = &od->pdev;
++ dev = &pdev->dev;
++ get_device(dev);
++ dev->dma_mask = &musb_dmamask;
++ dev->coherent_dma_mask = musb_dmamask;
++ put_device(dev);
+ }
+
+ #else
+--
+1.7.1
+
diff --git a/patches/for_next/0037-OMAP4-hwmod-data-Add-McSPI.patch b/patches/for_next/0037-OMAP4-hwmod-data-Add-McSPI.patch
new file mode 100644
index 0000000000000000000000000000000000000000..4fe9c4a3f05bc26addafdde3123f0c5e50633b7d
--- /dev/null
+++ b/patches/for_next/0037-OMAP4-hwmod-data-Add-McSPI.patch
@@ -0,0 +1,293 @@
+From 80fd2f324329bf4939b153529a2bd06e5db24268 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Wed, 2 Feb 2011 17:52:13 +0530
+Subject: [PATCH 037/254] OMAP4: hwmod data: Add McSPI
+
+Update omap4 hwmod file with McSPI info.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 249 +++++++++++++++++++++++++++-
+ 1 files changed, 245 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 46da576..8199eb2 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -534,10 +534,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * mcbsp3
+ * mcbsp4
+ * mcpdm
+- * mcspi1
+- * mcspi2
+- * mcspi3
+- * mcspi4
+ * mmc1
+ * mmc2
+ * mmc3
+@@ -1434,6 +1430,245 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
+ };
+
+ /*
++ * 'mcspi' class
++ * multichannel serial port interface (mcspi) / master/slave synchronous serial
++ * bus
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP),
++ .sysc_fields = &omap_hwmod_sysc_type2,
++};
++
++static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
++ .name = "mcspi",
++ .sysc = &omap44xx_mcspi_sysc,
++};
++
++/* mcspi1 */
++static struct omap_hwmod omap44xx_mcspi1_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
++ { .irq = 65 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
++ { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
++ { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
++ { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
++ {
++ .pa_start = 0x48098000,
++ .pa_end = 0x480981ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcspi1 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mcspi1_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mcspi1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcspi1 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
++ &omap44xx_l4_per__mcspi1,
++};
++
++static struct omap_hwmod omap44xx_mcspi1_hwmod = {
++ .name = "mcspi1",
++ .class = &omap44xx_mcspi_hwmod_class,
++ .mpu_irqs = omap44xx_mcspi1_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
++ .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
++ .main_clk = "mcspi1_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcspi1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mcspi2 */
++static struct omap_hwmod omap44xx_mcspi2_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
++ { .irq = 66 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
++ { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
++ {
++ .pa_start = 0x4809a000,
++ .pa_end = 0x4809a1ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcspi2 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mcspi2_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mcspi2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcspi2 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
++ &omap44xx_l4_per__mcspi2,
++};
++
++static struct omap_hwmod omap44xx_mcspi2_hwmod = {
++ .name = "mcspi2",
++ .class = &omap44xx_mcspi_hwmod_class,
++ .mpu_irqs = omap44xx_mcspi2_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
++ .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
++ .main_clk = "mcspi2_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcspi2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mcspi3 */
++static struct omap_hwmod omap44xx_mcspi3_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
++ { .irq = 91 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
++ { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
++ {
++ .pa_start = 0x480b8000,
++ .pa_end = 0x480b81ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcspi3 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mcspi3_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mcspi3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcspi3 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
++ &omap44xx_l4_per__mcspi3,
++};
++
++static struct omap_hwmod omap44xx_mcspi3_hwmod = {
++ .name = "mcspi3",
++ .class = &omap44xx_mcspi_hwmod_class,
++ .mpu_irqs = omap44xx_mcspi3_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
++ .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
++ .main_clk = "mcspi3_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcspi3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mcspi4 */
++static struct omap_hwmod omap44xx_mcspi4_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
++ { .irq = 48 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
++ {
++ .pa_start = 0x480ba000,
++ .pa_end = 0x480ba1ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcspi4 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mcspi4_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mcspi4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcspi4 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
++ &omap44xx_l4_per__mcspi4,
++};
++
++static struct omap_hwmod omap44xx_mcspi4_hwmod = {
++ .name = "mcspi4",
++ .class = &omap44xx_mcspi_hwmod_class,
++ .mpu_irqs = omap44xx_mcspi4_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
++ .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
++ .main_clk = "mcspi4_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcspi4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+@@ -2110,6 +2345,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ &omap44xx_iva_seq0_hwmod,
+ &omap44xx_iva_seq1_hwmod,
+
++ /* mcspi class */
++ &omap44xx_mcspi1_hwmod,
++ &omap44xx_mcspi2_hwmod,
++ &omap44xx_mcspi3_hwmod,
++ &omap44xx_mcspi4_hwmod,
++
+ /* mpu class */
+ &omap44xx_mpu_hwmod,
+
+--
+1.7.1
+
diff --git a/patches/for_next/0038-OMAP4-hwmod-data-Add-timer.patch b/patches/for_next/0038-OMAP4-hwmod-data-Add-timer.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2ef9382fb7dd1d72c94d1044988abda236e9ed8d
--- /dev/null
+++ b/patches/for_next/0038-OMAP4-hwmod-data-Add-timer.patch
@@ -0,0 +1,693 @@
+From ac5111e7634f2419a328ed418fb8909ae90040a0 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 11 Feb 2011 11:17:14 +0000
+Subject: [PATCH 038/254] OMAP4: hwmod data: Add timer
+
+Add the data for the 11 timers IPs.
+OMAP4 contains two differents IP variants for the timers:
+- 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11)
+- 3 x 1ms timer (1, 2 & 10)
+
+The regular timers registers programming model was changed due to the
+adaptation to the new IP interface. Unfortunately the 1ms version
+still use the previous programming model. The driver will have
+to take care of theses differences.
+
+Please note that the capability and the partitioning is also
+different depending of the instance.
+- timer 1 is inside the wakeup domain
+- timers 5, 6, 7 & 8 are inside in the ABE (audio backend)
+- timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain
+
+The timer was previously named gptimerX or dmtimerX, it is
+now simply named timerX.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+[b-cousson@ti.com: Fix alignement in class attribute,
+re-order flags and update the changelog]
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 633 +++++++++++++++++++++++++++-
+ 1 files changed, 622 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 8199eb2..37b3024 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -551,17 +551,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * sl2if
+ * slimbus1
+ * slimbus2
+- * timer1
+- * timer10
+- * timer11
+- * timer2
+- * timer3
+- * timer4
+- * timer5
+- * timer6
+- * timer7
+- * timer8
+- * timer9
+ * usb_host_fs
+ * usb_host_hs
+ * usb_otg_hs
+@@ -1934,6 +1923,615 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
+ };
+
+ /*
++ * 'timer' class
++ * general purpose timer module with accurate 1ms tick
++ * This class contains several variants: ['timer_1ms', 'timer']
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
++ SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
++ SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
++ .name = "timer",
++ .sysc = &omap44xx_timer_1ms_sysc,
++};
++
++static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP),
++ .sysc_fields = &omap_hwmod_sysc_type2,
++};
++
++static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
++ .name = "timer",
++ .sysc = &omap44xx_timer_sysc,
++};
++
++/* timer1 */
++static struct omap_hwmod omap44xx_timer1_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
++ { .irq = 37 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
++ {
++ .pa_start = 0x4a318000,
++ .pa_end = 0x4a31807f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_wkup -> timer1 */
++static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
++ .master = &omap44xx_l4_wkup_hwmod,
++ .slave = &omap44xx_timer1_hwmod,
++ .clk = "l4_wkup_clk_mux_ck",
++ .addr = omap44xx_timer1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer1 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
++ &omap44xx_l4_wkup__timer1,
++};
++
++static struct omap_hwmod omap44xx_timer1_hwmod = {
++ .name = "timer1",
++ .class = &omap44xx_timer_1ms_hwmod_class,
++ .mpu_irqs = omap44xx_timer1_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
++ .main_clk = "timer1_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer2 */
++static struct omap_hwmod omap44xx_timer2_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
++ { .irq = 38 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
++ {
++ .pa_start = 0x48032000,
++ .pa_end = 0x4803207f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer2 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_timer2_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_timer2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer2 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
++ &omap44xx_l4_per__timer2,
++};
++
++static struct omap_hwmod omap44xx_timer2_hwmod = {
++ .name = "timer2",
++ .class = &omap44xx_timer_1ms_hwmod_class,
++ .mpu_irqs = omap44xx_timer2_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
++ .main_clk = "timer2_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer3 */
++static struct omap_hwmod omap44xx_timer3_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
++ { .irq = 39 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
++ {
++ .pa_start = 0x48034000,
++ .pa_end = 0x4803407f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer3 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_timer3_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_timer3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer3 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
++ &omap44xx_l4_per__timer3,
++};
++
++static struct omap_hwmod omap44xx_timer3_hwmod = {
++ .name = "timer3",
++ .class = &omap44xx_timer_hwmod_class,
++ .mpu_irqs = omap44xx_timer3_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
++ .main_clk = "timer3_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer4 */
++static struct omap_hwmod omap44xx_timer4_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
++ { .irq = 40 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
++ {
++ .pa_start = 0x48036000,
++ .pa_end = 0x4803607f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer4 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_timer4_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_timer4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer4 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
++ &omap44xx_l4_per__timer4,
++};
++
++static struct omap_hwmod omap44xx_timer4_hwmod = {
++ .name = "timer4",
++ .class = &omap44xx_timer_hwmod_class,
++ .mpu_irqs = omap44xx_timer4_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
++ .main_clk = "timer4_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer5 */
++static struct omap_hwmod omap44xx_timer5_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
++ { .irq = 41 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
++ {
++ .pa_start = 0x40138000,
++ .pa_end = 0x4013807f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> timer5 */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_timer5_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_timer5_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
++ {
++ .pa_start = 0x49038000,
++ .pa_end = 0x4903807f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> timer5 (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_timer5_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_timer5_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* timer5 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
++ &omap44xx_l4_abe__timer5,
++ &omap44xx_l4_abe__timer5_dma,
++};
++
++static struct omap_hwmod omap44xx_timer5_hwmod = {
++ .name = "timer5",
++ .class = &omap44xx_timer_hwmod_class,
++ .mpu_irqs = omap44xx_timer5_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
++ .main_clk = "timer5_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer5_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer6 */
++static struct omap_hwmod omap44xx_timer6_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
++ { .irq = 42 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
++ {
++ .pa_start = 0x4013a000,
++ .pa_end = 0x4013a07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> timer6 */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_timer6_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_timer6_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
++ {
++ .pa_start = 0x4903a000,
++ .pa_end = 0x4903a07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> timer6 (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_timer6_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_timer6_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* timer6 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
++ &omap44xx_l4_abe__timer6,
++ &omap44xx_l4_abe__timer6_dma,
++};
++
++static struct omap_hwmod omap44xx_timer6_hwmod = {
++ .name = "timer6",
++ .class = &omap44xx_timer_hwmod_class,
++ .mpu_irqs = omap44xx_timer6_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
++ .main_clk = "timer6_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer6_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer7 */
++static struct omap_hwmod omap44xx_timer7_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
++ { .irq = 43 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
++ {
++ .pa_start = 0x4013c000,
++ .pa_end = 0x4013c07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> timer7 */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_timer7_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_timer7_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
++ {
++ .pa_start = 0x4903c000,
++ .pa_end = 0x4903c07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> timer7 (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_timer7_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_timer7_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* timer7 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
++ &omap44xx_l4_abe__timer7,
++ &omap44xx_l4_abe__timer7_dma,
++};
++
++static struct omap_hwmod omap44xx_timer7_hwmod = {
++ .name = "timer7",
++ .class = &omap44xx_timer_hwmod_class,
++ .mpu_irqs = omap44xx_timer7_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
++ .main_clk = "timer7_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer7_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer8 */
++static struct omap_hwmod omap44xx_timer8_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
++ { .irq = 44 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
++ {
++ .pa_start = 0x4013e000,
++ .pa_end = 0x4013e07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> timer8 */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_timer8_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_timer8_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
++ {
++ .pa_start = 0x4903e000,
++ .pa_end = 0x4903e07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> timer8 (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_timer8_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_timer8_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* timer8 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
++ &omap44xx_l4_abe__timer8,
++ &omap44xx_l4_abe__timer8_dma,
++};
++
++static struct omap_hwmod omap44xx_timer8_hwmod = {
++ .name = "timer8",
++ .class = &omap44xx_timer_hwmod_class,
++ .mpu_irqs = omap44xx_timer8_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
++ .main_clk = "timer8_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer8_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer9 */
++static struct omap_hwmod omap44xx_timer9_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
++ { .irq = 45 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
++ {
++ .pa_start = 0x4803e000,
++ .pa_end = 0x4803e07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer9 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_timer9_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_timer9_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer9 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
++ &omap44xx_l4_per__timer9,
++};
++
++static struct omap_hwmod omap44xx_timer9_hwmod = {
++ .name = "timer9",
++ .class = &omap44xx_timer_hwmod_class,
++ .mpu_irqs = omap44xx_timer9_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
++ .main_clk = "timer9_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer9_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer10 */
++static struct omap_hwmod omap44xx_timer10_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
++ { .irq = 46 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
++ {
++ .pa_start = 0x48086000,
++ .pa_end = 0x4808607f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer10 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_timer10_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_timer10_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer10 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
++ &omap44xx_l4_per__timer10,
++};
++
++static struct omap_hwmod omap44xx_timer10_hwmod = {
++ .name = "timer10",
++ .class = &omap44xx_timer_1ms_hwmod_class,
++ .mpu_irqs = omap44xx_timer10_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
++ .main_clk = "timer10_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer10_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* timer11 */
++static struct omap_hwmod omap44xx_timer11_hwmod;
++static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
++ { .irq = 47 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
++ {
++ .pa_start = 0x48088000,
++ .pa_end = 0x4808807f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer11 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_timer11_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_timer11_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer11 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
++ &omap44xx_l4_per__timer11,
++};
++
++static struct omap_hwmod omap44xx_timer11_hwmod = {
++ .name = "timer11",
++ .class = &omap44xx_timer_hwmod_class,
++ .mpu_irqs = omap44xx_timer11_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
++ .main_clk = "timer11_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_timer11_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+@@ -2362,6 +2960,19 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ /* spinlock class */
+ &omap44xx_spinlock_hwmod,
+
++ /* timer class */
++ &omap44xx_timer1_hwmod,
++ &omap44xx_timer2_hwmod,
++ &omap44xx_timer3_hwmod,
++ &omap44xx_timer4_hwmod,
++ &omap44xx_timer5_hwmod,
++ &omap44xx_timer6_hwmod,
++ &omap44xx_timer7_hwmod,
++ &omap44xx_timer8_hwmod,
++ &omap44xx_timer9_hwmod,
++ &omap44xx_timer10_hwmod,
++ &omap44xx_timer11_hwmod,
++
+ /* uart class */
+ &omap44xx_uart1_hwmod,
+ &omap44xx_uart2_hwmod,
+--
+1.7.1
+
diff --git a/patches/panda/0024-OMAP4-hwmod-data-add-DSS-DISPC-DSI1-2-RFBI-HDMI-VENC.patch b/patches/for_next/0039-OMAP4-hwmod-data-Add-DSS-DISPC-DSI1-2-RFBI-HDMI-and-.patch
similarity index 88%
rename from patches/panda/0024-OMAP4-hwmod-data-add-DSS-DISPC-DSI1-2-RFBI-HDMI-VENC.patch
rename to patches/for_next/0039-OMAP4-hwmod-data-Add-DSS-DISPC-DSI1-2-RFBI-HDMI-and-.patch
index 5a777cf0cab929bacfeb89e00c619d206e3128ab..02b31d95491a50b68f05cfc0cdd23092aa80d9b9 100644
--- a/patches/panda/0024-OMAP4-hwmod-data-add-DSS-DISPC-DSI1-2-RFBI-HDMI-VENC.patch
+++ b/patches/for_next/0039-OMAP4-hwmod-data-Add-DSS-DISPC-DSI1-2-RFBI-HDMI-and-.patch
@@ -1,7 +1,7 @@
-From 19863f9c25eced95a191424c737dd2ee367b734b Mon Sep 17 00:00:00 2001
+From cda87c7aba6280aa05c108127202d9b4bd0121d3 Mon Sep 17 00:00:00 2001
From: Benoit Cousson <b-cousson@ti.com>
Date: Thu, 27 Jan 2011 11:17:03 +0000
-Subject: [PATCH 24/35] OMAP4: hwmod data: add DSS DISPC DSI1,2 RFBI HDMI VENC
+Subject: [PATCH 039/254] OMAP4: hwmod data: Add DSS, DISPC, DSI1&2, RFBI, HDMI and VENC
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods.
In OMAP4 there are severals IPs that can be reached by differents
@@ -21,56 +21,163 @@ Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
+[b-cousson@ti.com: Re-organize structures to match file
+convention and remove irq entry from dss_hwmod]
---
- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 603 ++++++++++++++++++++++++++++
- 1 files changed, 603 insertions(+), 0 deletions(-)
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 612 +++++++++++++++++++++++++++-
+ 1 files changed, 604 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-index c2806bd..0bd579e 100644
+index 37b3024..aafe60d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
-@@ -43,6 +43,13 @@
+@@ -1,7 +1,7 @@
+ /*
+ * Hardware modules present on the OMAP44xx chips
+ *
+- * Copyright (C) 2009-2010 Texas Instruments, Inc.
++ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+@@ -43,6 +43,7 @@
static struct omap_hwmod omap44xx_dma_system_hwmod;
static struct omap_hwmod omap44xx_dmm_hwmod;
static struct omap_hwmod omap44xx_dsp_hwmod;
-+static struct omap_hwmod omap44xx_dss_core_hwmod;
-+static struct omap_hwmod omap44xx_dss_dispc_hwmod;
-+static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
-+static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
-+static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
-+static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
-+static struct omap_hwmod omap44xx_dss_venc_hwmod;
++static struct omap_hwmod omap44xx_dss_hwmod;
static struct omap_hwmod omap44xx_emif_fw_hwmod;
static struct omap_hwmod omap44xx_iva_hwmod;
static struct omap_hwmod omap44xx_l3_instr_hwmod;
-@@ -237,12 +244,21 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+@@ -213,6 +214,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* dss -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
-+ .master = &omap44xx_dss_core_hwmod,
++ .master = &omap44xx_dss_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+ /* l3_main_2 -> l3_main_1 */
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
+ .master = &omap44xx_l3_main_2_hwmod,
+@@ -240,6 +249,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
/* l3_main_1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
&omap44xx_dsp__l3_main_1,
++ &omap44xx_dss__l3_main_1,
&omap44xx_l3_main_2__l3_main_1,
&omap44xx_l4_cfg__l3_main_1,
&omap44xx_mpu__l3_main_1,
-+ &omap44xx_dss__l3_main_1,
- };
-
- static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
-@@ -746,6 +762,584 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -507,13 +517,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * ctrl_module_wkup
+ * debugss
+ * dmic
+- * dss
+- * dss_dispc
+- * dss_dsi1
+- * dss_dsi2
+- * dss_hdmi
+- * dss_rfbi
+- * dss_venc
+ * efuse_ctrl_cust
+ * efuse_ctrl_std
+ * elm
+@@ -731,6 +734,590 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
};
-+/* ==== DSS related classes ==== */
-+ /*
+ /*
++ * 'dss' class
++ * display sub-system
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
++ .rev_offs = 0x0000,
++ .syss_offs = 0x0014,
++ .sysc_flags = SYSS_HAS_RESET_STATUS,
++};
++
++static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
++ .name = "dss",
++ .sysc = &omap44xx_dss_sysc,
++};
++
++/* dss */
++/* dss master ports */
++static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
++ &omap44xx_dss__l3_main_1,
++};
++
++static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
++ {
++ .pa_start = 0x58000000,
++ .pa_end = 0x5800007f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l3_main_2 -> dss */
++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
++ .master = &omap44xx_l3_main_2_hwmod,
++ .slave = &omap44xx_dss_hwmod,
++ .clk = "l3_div_ck",
++ .addr = omap44xx_dss_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
++ {
++ .pa_start = 0x48040000,
++ .pa_end = 0x4804007f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> dss */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_dss_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_dss_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
++ .user = OCP_USER_MPU,
++};
++
++/* dss slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
++ &omap44xx_l3_main_2__dss,
++ &omap44xx_l4_per__dss,
++};
++
++static struct omap_hwmod_opt_clk dss_opt_clks[] = {
++ { .role = "sys_clk", .clk = "dss_sys_clk" },
++ { .role = "tv_clk", .clk = "dss_tv_clk" },
++ { .role = "dss_clk", .clk = "dss_dss_clk" },
++ { .role = "video_clk", .clk = "dss_48mhz_clk" },
++};
++
++static struct omap_hwmod omap44xx_dss_hwmod = {
++ .name = "dss_core",
++ .class = &omap44xx_dss_hwmod_class,
++ .main_clk = "dss_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
++ },
++ },
++ .opt_clks = dss_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
++ .slaves = omap44xx_dss_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
++ .masters = omap44xx_dss_masters,
++ .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'dispc' class
+ * display controller
+ */
@@ -89,11 +196,12 @@ index c2806bd..0bd579e 100644
+};
+
+static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
-+ .name = "dispc",
-+ .sysc = &omap44xx_dispc_sysc,
++ .name = "dispc",
++ .sysc = &omap44xx_dispc_sysc,
+};
+
+/* dss_dispc */
++static struct omap_hwmod omap44xx_dss_dispc_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
+ { .irq = 25 + OMAP44XX_IRQ_GIC_START },
+};
@@ -102,24 +210,6 @@ index c2806bd..0bd579e 100644
+ { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
+};
+
-+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
-+ {
-+ .pa_start = 0x48041000,
-+ .pa_end = 0x48041fff,
-+ .flags = ADDR_TYPE_RT
-+ },
-+};
-+
-+/* l4_per -> dss_dispc */
-+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
-+ .master = &omap44xx_l4_per_hwmod,
-+ .slave = &omap44xx_dss_dispc_hwmod,
-+ .clk = "l4_div_ck",
-+ .addr = omap44xx_dss_dispc_addrs,
-+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
-+ .user = OCP_USER_MPU,
-+};
-+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+ {
+ .pa_start = 0x58001000,
@@ -138,6 +228,24 @@ index c2806bd..0bd579e 100644
+ .user = OCP_USER_SDMA,
+};
+
++static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
++ {
++ .pa_start = 0x48041000,
++ .pa_end = 0x48041fff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> dss_dispc */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_dss_dispc_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_dss_dispc_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
++ .user = OCP_USER_MPU,
++};
++
+/* dss_dispc slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
+ &omap44xx_l3_main_2__dss_dispc,
@@ -166,6 +274,7 @@ index c2806bd..0bd579e 100644
+ * 'dsi' class
+ * display serial interface controller
+ */
++
+static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
@@ -178,11 +287,12 @@ index c2806bd..0bd579e 100644
+};
+
+static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
-+ .name = "dsi",
-+ .sysc = &omap44xx_dsi_sysc,
++ .name = "dsi",
++ .sysc = &omap44xx_dsi_sysc,
+};
+
+/* dss_dsi1 */
++static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
+ { .irq = 53 + OMAP44XX_IRQ_GIC_START },
+};
@@ -191,28 +301,10 @@ index c2806bd..0bd579e 100644
+ { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
+};
+
-+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
-+ {
-+ .pa_start = 0x48044000,
-+ .pa_end = 0x480440ff,
-+ .flags = ADDR_TYPE_RT
-+ },
-+};
-+
-+/* l4_per -> dss_dsi1 */
-+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
-+ .master = &omap44xx_l4_per_hwmod,
-+ .slave = &omap44xx_dss_dsi1_hwmod,
-+ .clk = "l4_div_ck",
-+ .addr = omap44xx_dss_dsi1_addrs,
-+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
-+ .user = OCP_USER_MPU,
-+};
-+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+ {
+ .pa_start = 0x58004000,
-+ .pa_end = 0x580040ff,
++ .pa_end = 0x580041ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
@@ -227,6 +319,24 @@ index c2806bd..0bd579e 100644
+ .user = OCP_USER_SDMA,
+};
+
++static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
++ {
++ .pa_start = 0x48044000,
++ .pa_end = 0x480441ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> dss_dsi1 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_dss_dsi1_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_dss_dsi1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
++ .user = OCP_USER_MPU,
++};
++
+/* dss_dsi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
+ &omap44xx_l3_main_2__dss_dsi1,
@@ -252,6 +362,7 @@ index c2806bd..0bd579e 100644
+};
+
+/* dss_dsi2 */
++static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
+ { .irq = 84 + OMAP44XX_IRQ_GIC_START },
+};
@@ -260,28 +371,10 @@ index c2806bd..0bd579e 100644
+ { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
+};
+
-+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
-+ {
-+ .pa_start = 0x48045000,
-+ .pa_end = 0x480450ff,
-+ .flags = ADDR_TYPE_RT
-+ },
-+};
-+
-+/* l4_per -> dss_dsi2 */
-+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
-+ .master = &omap44xx_l4_per_hwmod,
-+ .slave = &omap44xx_dss_dsi2_hwmod,
-+ .clk = "l4_div_ck",
-+ .addr = omap44xx_dss_dsi2_addrs,
-+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
-+ .user = OCP_USER_MPU,
-+};
-+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+ {
+ .pa_start = 0x58005000,
-+ .pa_end = 0x580050ff,
++ .pa_end = 0x580051ff,
+ .flags = ADDR_TYPE_RT
+ },
+};
@@ -296,6 +389,24 @@ index c2806bd..0bd579e 100644
+ .user = OCP_USER_SDMA,
+};
+
++static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
++ {
++ .pa_start = 0x48045000,
++ .pa_end = 0x480451ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> dss_dsi2 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_dss_dsi2_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_dss_dsi2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
++ .user = OCP_USER_MPU,
++};
++
+/* dss_dsi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
+ &omap44xx_l3_main_2__dss_dsi2,
@@ -321,118 +432,53 @@ index c2806bd..0bd579e 100644
+};
+
+/*
-+ * 'dss' class
-+ * display sub-system
++ * 'hdmi' class
++ * hdmi controller
+ */
-+static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
-+ .rev_offs = 0x0000,
-+ .syss_offs = 0x0014,
-+ .sysc_flags = SYSS_HAS_RESET_STATUS,
-+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+};
-+
-+static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
-+ .name = "dss",
-+ .sysc = &omap44xx_dss_sysc,
-+};
+
-+/* dss */
-+/* dss master ports */
-+static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
-+ &omap44xx_dss__l3_main_1,
++static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP),
++ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
-+static struct omap_hwmod_irq_info omap44xx_dss_irqs[] = {
-+ { .irq = 25 + OMAP44XX_IRQ_GIC_START },
++static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
++ .name = "hdmi",
++ .sysc = &omap44xx_hdmi_sysc,
+};
+
-+static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
-+ {
-+ .pa_start = 0x48040000,
-+ .pa_end = 0x4804007f,
-+ .flags = ADDR_TYPE_RT
-+ },
++/* dss_hdmi */
++static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
++static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
++ { .irq = 101 + OMAP44XX_IRQ_GIC_START },
+};
+
-+/* l4_per -> dss */
-+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
-+ .master = &omap44xx_l4_per_hwmod,
-+ .slave = &omap44xx_dss_core_hwmod,
-+ .clk = "l4_div_ck",
-+ .addr = omap44xx_dss_addrs,
-+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
-+ .user = OCP_USER_MPU,
++static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
++ { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
+};
+
-+static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
++static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+ {
-+ .pa_start = 0x58000000,
-+ .pa_end = 0x5800007f,
++ .pa_start = 0x58006000,
++ .pa_end = 0x58006fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
-+/* l3_main_2 -> dss */
-+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
++/* l3_main_2 -> dss_hdmi */
++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+ .master = &omap44xx_l3_main_2_hwmod,
-+ .slave = &omap44xx_dss_core_hwmod,
++ .slave = &omap44xx_dss_hdmi_hwmod,
+ .clk = "l3_div_ck",
-+ .addr = omap44xx_dss_dma_addrs,
-+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
++ .addr = omap44xx_dss_hdmi_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
+ .user = OCP_USER_SDMA,
+};
+
-+/* dss slave ports */
-+static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
-+ &omap44xx_l3_main_2__dss,
-+ &omap44xx_l4_per__dss,
-+};
-+
-+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-+ { .role = "sys_clk", .clk = "dss_sys_clk" },
-+ { .role = "tv_clk", .clk = "dss_tv_clk" },
-+ { .role = "dss_clk", .clk = "dss_dss_clk" },
-+ { .role = "video_clk", .clk = "dss_48mhz_clk" },
-+};
-+
-+static struct omap_hwmod omap44xx_dss_core_hwmod = {
-+ .name = "dss_core",
-+ .class = &omap44xx_dss_hwmod_class,
-+ .mpu_irqs = omap44xx_dss_irqs,
-+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_irqs),
-+ .main_clk = "dss_fck",
-+ .prcm = {
-+ .omap4 = {
-+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
-+ },
-+ },
-+ .opt_clks = dss_opt_clks,
-+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-+ .slaves = omap44xx_dss_slaves,
-+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
-+ .masters = omap44xx_dss_masters,
-+ .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
-+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-+};
-+
-+/*
-+ * 'hdmi' class
-+ * hdmi controller
-+ */
-+
-+static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
-+ .name = "hdmi",
-+};
-+
-+/* dss_hdmi */
-+static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
-+ { .irq = 101 + OMAP44XX_IRQ_GIC_START },
-+};
-+
-+static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
-+ { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
-+};
-+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
+ {
+ .pa_start = 0x48046000,
@@ -451,24 +497,6 @@ index c2806bd..0bd579e 100644
+ .user = OCP_USER_MPU,
+};
+
-+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
-+ {
-+ .pa_start = 0x58006000,
-+ .pa_end = 0x58006fff,
-+ .flags = ADDR_TYPE_RT
-+ },
-+};
-+
-+/* l3_main_2 -> dss_hdmi */
-+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
-+ .master = &omap44xx_l3_main_2_hwmod,
-+ .slave = &omap44xx_dss_hdmi_hwmod,
-+ .clk = "l3_div_ck",
-+ .addr = omap44xx_dss_hdmi_dma_addrs,
-+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
-+ .user = OCP_USER_SDMA,
-+};
-+
+/* dss_hdmi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
+ &omap44xx_l3_main_2__dss_hdmi,
@@ -493,7 +521,7 @@ index c2806bd..0bd579e 100644
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
-+ /*
++/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
@@ -509,33 +537,16 @@ index c2806bd..0bd579e 100644
+};
+
+static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
-+ .name = "rfbi",
-+ .sysc = &omap44xx_rfbi_sysc,
++ .name = "rfbi",
++ .sysc = &omap44xx_rfbi_sysc,
+};
+
+/* dss_rfbi */
++static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
+static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
+ { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
+};
+
-+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
-+ {
-+ .pa_start = 0x48042000,
-+ .pa_end = 0x480420ff,
-+ .flags = ADDR_TYPE_RT
-+ },
-+};
-+
-+/* l4_per -> dss_rfbi */
-+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
-+ .master = &omap44xx_l4_per_hwmod,
-+ .slave = &omap44xx_dss_rfbi_hwmod,
-+ .clk = "l4_div_ck",
-+ .addr = omap44xx_dss_rfbi_addrs,
-+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
-+ .user = OCP_USER_MPU,
-+};
-+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+ {
+ .pa_start = 0x58002000,
@@ -554,6 +565,24 @@ index c2806bd..0bd579e 100644
+ .user = OCP_USER_SDMA,
+};
+
++static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
++ {
++ .pa_start = 0x48042000,
++ .pa_end = 0x480420ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> dss_rfbi */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_dss_rfbi_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_dss_rfbi_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
++ .user = OCP_USER_MPU,
++};
++
+/* dss_rfbi slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
+ &omap44xx_l3_main_2__dss_rfbi,
@@ -581,34 +610,12 @@ index c2806bd..0bd579e 100644
+ * video encoder
+ */
+
-+static struct omap_hwmod_class_sysconfig omap44xx_venc_sysc = {
-+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-+};
-+
+static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
-+ .name = "venc",
-+ .sysc = &omap44xx_venc_sysc,
++ .name = "venc",
+};
+
+/* dss_venc */
-+static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
-+ {
-+ .pa_start = 0x48043000,
-+ .pa_end = 0x480430ff,
-+ .flags = ADDR_TYPE_RT
-+ },
-+};
-+
-+/* l4_per -> dss_venc */
-+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
-+ .master = &omap44xx_l4_per_hwmod,
-+ .slave = &omap44xx_dss_venc_hwmod,
-+ .clk = "l4_div_ck",
-+ .addr = omap44xx_dss_venc_addrs,
-+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
-+ .user = OCP_USER_MPU,
-+};
-+
++static struct omap_hwmod omap44xx_dss_venc_hwmod;
+static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+ {
+ .pa_start = 0x58003000,
@@ -627,6 +634,24 @@ index c2806bd..0bd579e 100644
+ .user = OCP_USER_SDMA,
+};
+
++static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
++ {
++ .pa_start = 0x48043000,
++ .pa_end = 0x480430ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> dss_venc */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_dss_venc_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_dss_venc_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
++ .user = OCP_USER_MPU,
++};
++
+/* dss_venc slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
+ &omap44xx_l3_main_2__dss_venc,
@@ -636,6 +661,7 @@ index c2806bd..0bd579e 100644
+static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+ .name = "dss_venc",
+ .class = &omap44xx_venc_hwmod_class,
++ .main_clk = "dss_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
@@ -646,16 +672,16 @@ index c2806bd..0bd579e 100644
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
-+
- /*
++/*
* 'gpio' class
* general purpose io module
-@@ -2031,6 +2625,15 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ */
+@@ -2924,6 +3511,15 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
&omap44xx_dsp_hwmod,
&omap44xx_dsp_c0_hwmod,
+ /* dss class */
-+ &omap44xx_dss_core_hwmod,
++ &omap44xx_dss_hwmod,
+ &omap44xx_dss_dispc_hwmod,
+ &omap44xx_dss_dsi1_hwmod,
+ &omap44xx_dss_dsi2_hwmod,
diff --git a/patches/for_next/0040-OMAP4-hwmod-data-Add-mailbox.patch b/patches/for_next/0040-OMAP4-hwmod-data-Add-mailbox.patch
new file mode 100644
index 0000000000000000000000000000000000000000..0397af948220503ab8229b384e2d79a2cdbd5307
--- /dev/null
+++ b/patches/for_next/0040-OMAP4-hwmod-data-Add-mailbox.patch
@@ -0,0 +1,111 @@
+From a9c5e031e37bec9df78b710220c16e1e17c7e812 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Wed, 2 Feb 2011 19:27:21 +0000
+Subject: [PATCH 040/254] OMAP4: hwmod data: Add mailbox
+
+Mailbox hwmod data for omap4.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
+[b-cousson@ti.com: Re-order the structures
+and remove the irq line name]
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 68 +++++++++++++++++++++++++++-
+ 1 files changed, 67 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index aafe60d..efdf266 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -530,7 +530,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * ipu
+ * iss
+ * kbd
+- * mailbox
+ * mcasp
+ * mcbsp1
+ * mcbsp2
+@@ -2006,6 +2005,70 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
+ };
+
+ /*
++ * 'mailbox' class
++ * mailbox module allowing communication between the on-chip processors using a
++ * queued mailbox-interrupt mechanism.
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type2,
++};
++
++static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
++ .name = "mailbox",
++ .sysc = &omap44xx_mailbox_sysc,
++};
++
++/* mailbox */
++static struct omap_hwmod omap44xx_mailbox_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
++ { .irq = 26 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
++ {
++ .pa_start = 0x4a0f4000,
++ .pa_end = 0x4a0f41ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_cfg -> mailbox */
++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
++ .master = &omap44xx_l4_cfg_hwmod,
++ .slave = &omap44xx_mailbox_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mailbox_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mailbox slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
++ &omap44xx_l4_cfg__mailbox,
++};
++
++static struct omap_hwmod omap44xx_mailbox_hwmod = {
++ .name = "mailbox",
++ .class = &omap44xx_mailbox_hwmod_class,
++ .mpu_irqs = omap44xx_mailbox_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mailbox_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+@@ -3539,6 +3602,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ &omap44xx_iva_seq0_hwmod,
+ &omap44xx_iva_seq1_hwmod,
+
++ /* mailbox class */
++ &omap44xx_mailbox_hwmod,
++
+ /* mcspi class */
+ &omap44xx_mcspi1_hwmod,
+ &omap44xx_mcspi2_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0041-OMAP4-hwmod-data-Add-DMIC.patch b/patches/for_next/0041-OMAP4-hwmod-data-Add-DMIC.patch
new file mode 100644
index 0000000000000000000000000000000000000000..0ffe5c6925e916994caf8714f264bbd0e156d33d
--- /dev/null
+++ b/patches/for_next/0041-OMAP4-hwmod-data-Add-DMIC.patch
@@ -0,0 +1,141 @@
+From 31d18eb079e2a9870bc34518e6ef1a1e0b312d2b Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Tue, 25 Jan 2011 22:01:00 +0000
+Subject: [PATCH 041/254] OMAP4: hwmod data: Add DMIC
+
+Add HWMOD entries for the OMAP DMIC. The HWMOD entires define the system
+resource requirements for the driver such as DMA addresses, channels,
+and IRQ's. Placing this information in the HWMOD database allows for
+more generic drivers to be written and having the specific implementation
+details defined in HWMOD.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: David Lambert <dlambert@ti.com>
+[b-cousson@ti.com: Change the wrong hwmod name,
+add missing flag and re-order structures]
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 94 +++++++++++++++++++++++++++-
+ 1 files changed, 93 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index efdf266..1488438 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -516,7 +516,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * ctrl_module_pad_wkup
+ * ctrl_module_wkup
+ * debugss
+- * dmic
+ * efuse_ctrl_cust
+ * efuse_ctrl_std
+ * elm
+@@ -648,6 +647,96 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
+ };
+
+ /*
++ * 'dmic' class
++ * digital microphone controller
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP),
++ .sysc_fields = &omap_hwmod_sysc_type2,
++};
++
++static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
++ .name = "dmic",
++ .sysc = &omap44xx_dmic_sysc,
++};
++
++/* dmic */
++static struct omap_hwmod omap44xx_dmic_hwmod;
++static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
++ { .irq = 114 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
++ { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
++ {
++ .pa_start = 0x4012e000,
++ .pa_end = 0x4012e07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> dmic */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_dmic_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_dmic_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
++ {
++ .pa_start = 0x4902e000,
++ .pa_end = 0x4902e07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> dmic (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_dmic_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_dmic_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* dmic slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
++ &omap44xx_l4_abe__dmic,
++ &omap44xx_l4_abe__dmic_dma,
++};
++
++static struct omap_hwmod omap44xx_dmic_hwmod = {
++ .name = "dmic",
++ .class = &omap44xx_dmic_hwmod_class,
++ .mpu_irqs = omap44xx_dmic_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
++ .sdma_reqs = omap44xx_dmic_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
++ .main_clk = "dmic_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_dmic_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'dsp' class
+ * dsp sub-system
+ */
+@@ -3570,6 +3659,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ /* dma class */
+ &omap44xx_dma_system_hwmod,
+
++ /* dmic class */
++ &omap44xx_dmic_hwmod,
++
+ /* dsp class */
+ &omap44xx_dsp_hwmod,
+ &omap44xx_dsp_c0_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0042-OMAP4-hwmod-data-Add-McBSP.patch b/patches/for_next/0042-OMAP4-hwmod-data-Add-McBSP.patch
new file mode 100644
index 0000000000000000000000000000000000000000..13be1bae4e7922035f4085641964b2dcd5b353f1
--- /dev/null
+++ b/patches/for_next/0042-OMAP4-hwmod-data-Add-McBSP.patch
@@ -0,0 +1,338 @@
+From 5a2ffbdecda003d377df24dbcc83be935d04ec2e Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Mon, 31 Jan 2011 14:50:30 +0000
+Subject: [PATCH 042/254] OMAP4: hwmod data: Add McBSP
+
+Add mcbsp data including a revision member in hwmod_class in
+order to provide mcbsp revision information in different omap.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Charulatha V <charu@ti.com>
+[b-cousson@ti.com: Remove the mcbsp4 memory name, re-order
+properly the structures]
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 293 +++++++++++++++++++++++++++-
+ 1 files changed, 289 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 1488438..f108614 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -530,10 +530,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * iss
+ * kbd
+ * mcasp
+- * mcbsp1
+- * mcbsp2
+- * mcbsp3
+- * mcbsp4
+ * mcpdm
+ * mmc1
+ * mmc2
+@@ -2158,6 +2154,289 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
+ };
+
+ /*
++ * 'mcbsp' class
++ * multi channel buffered serial port controller
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
++ .sysc_offs = 0x008c,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
++ .name = "mcbsp",
++ .sysc = &omap44xx_mcbsp_sysc,
++};
++
++/* mcbsp1 */
++static struct omap_hwmod omap44xx_mcbsp1_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
++ { .irq = 17 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
++ {
++ .pa_start = 0x40122000,
++ .pa_end = 0x401220ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> mcbsp1 */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_mcbsp1_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_mcbsp1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
++ {
++ .pa_start = 0x49022000,
++ .pa_end = 0x490220ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> mcbsp1 (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_mcbsp1_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_mcbsp1_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* mcbsp1 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
++ &omap44xx_l4_abe__mcbsp1,
++ &omap44xx_l4_abe__mcbsp1_dma,
++};
++
++static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
++ .name = "mcbsp1",
++ .class = &omap44xx_mcbsp_hwmod_class,
++ .mpu_irqs = omap44xx_mcbsp1_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
++ .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
++ .main_clk = "mcbsp1_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcbsp1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mcbsp2 */
++static struct omap_hwmod omap44xx_mcbsp2_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
++ { .irq = 22 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
++ {
++ .pa_start = 0x40124000,
++ .pa_end = 0x401240ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> mcbsp2 */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_mcbsp2_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_mcbsp2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
++ {
++ .pa_start = 0x49024000,
++ .pa_end = 0x490240ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> mcbsp2 (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_mcbsp2_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_mcbsp2_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* mcbsp2 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
++ &omap44xx_l4_abe__mcbsp2,
++ &omap44xx_l4_abe__mcbsp2_dma,
++};
++
++static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
++ .name = "mcbsp2",
++ .class = &omap44xx_mcbsp_hwmod_class,
++ .mpu_irqs = omap44xx_mcbsp2_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
++ .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
++ .main_clk = "mcbsp2_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcbsp2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mcbsp3 */
++static struct omap_hwmod omap44xx_mcbsp3_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
++ { .irq = 23 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
++ {
++ .pa_start = 0x40126000,
++ .pa_end = 0x401260ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> mcbsp3 */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_mcbsp3_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_mcbsp3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
++ {
++ .pa_start = 0x49026000,
++ .pa_end = 0x490260ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> mcbsp3 (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_mcbsp3_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_mcbsp3_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* mcbsp3 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
++ &omap44xx_l4_abe__mcbsp3,
++ &omap44xx_l4_abe__mcbsp3_dma,
++};
++
++static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
++ .name = "mcbsp3",
++ .class = &omap44xx_mcbsp_hwmod_class,
++ .mpu_irqs = omap44xx_mcbsp3_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
++ .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
++ .main_clk = "mcbsp3_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcbsp3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mcbsp4 */
++static struct omap_hwmod omap44xx_mcbsp4_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
++ { .irq = 16 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
++ {
++ .pa_start = 0x48096000,
++ .pa_end = 0x480960ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcbsp4 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mcbsp4_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mcbsp4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp4 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
++ &omap44xx_l4_per__mcbsp4,
++};
++
++static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
++ .name = "mcbsp4",
++ .class = &omap44xx_mcbsp_hwmod_class,
++ .mpu_irqs = omap44xx_mcbsp4_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
++ .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
++ .main_clk = "mcbsp4_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcbsp4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+@@ -3697,6 +3976,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ /* mailbox class */
+ &omap44xx_mailbox_hwmod,
+
++ /* mcbsp class */
++ &omap44xx_mcbsp1_hwmod,
++ &omap44xx_mcbsp2_hwmod,
++ &omap44xx_mcbsp3_hwmod,
++ &omap44xx_mcbsp4_hwmod,
++
+ /* mcspi class */
+ &omap44xx_mcspi1_hwmod,
+ &omap44xx_mcspi2_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0043-OMAP4-hwmod-data-Add-AESS-McPDM-bandgap-counter_32k-.patch b/patches/for_next/0043-OMAP4-hwmod-data-Add-AESS-McPDM-bandgap-counter_32k-.patch
new file mode 100644
index 0000000000000000000000000000000000000000..326e1c143e408abd93b8b616a31684f78d35dd19
--- /dev/null
+++ b/patches/for_next/0043-OMAP4-hwmod-data-Add-AESS-McPDM-bandgap-counter_32k-.patch
@@ -0,0 +1,1193 @@
+From 75836dfbc76fc9546b2243d505781f7c361851e2 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Tue, 15 Feb 2011 22:39:48 +0100
+Subject: [PATCH 043/254] OMAP4: hwmod data: Add AESS, McPDM, bandgap, counter_32k, MMC, KBD, ISS & IPU
+
+Add more hwmod structures but keep them commented out for the moment
+until the driver adaptation to hwmod / omap_device is done.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1009 +++++++++++++++++++++++++++-
+ 1 files changed, 993 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index f108614..989bc96 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -40,11 +40,15 @@
+ #define OMAP44XX_DMA_REQ_START 1
+
+ /* Backward references (IPs with Bus Master capability) */
++static struct omap_hwmod omap44xx_aess_hwmod;
+ static struct omap_hwmod omap44xx_dma_system_hwmod;
+ static struct omap_hwmod omap44xx_dmm_hwmod;
+ static struct omap_hwmod omap44xx_dsp_hwmod;
+ static struct omap_hwmod omap44xx_dss_hwmod;
+ static struct omap_hwmod omap44xx_emif_fw_hwmod;
++static struct omap_hwmod omap44xx_hsi_hwmod;
++static struct omap_hwmod omap44xx_ipu_hwmod;
++static struct omap_hwmod omap44xx_iss_hwmod;
+ static struct omap_hwmod omap44xx_iva_hwmod;
+ static struct omap_hwmod omap44xx_l3_instr_hwmod;
+ static struct omap_hwmod omap44xx_l3_main_1_hwmod;
+@@ -54,6 +58,8 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod;
+ static struct omap_hwmod omap44xx_l4_cfg_hwmod;
+ static struct omap_hwmod omap44xx_l4_per_hwmod;
+ static struct omap_hwmod omap44xx_l4_wkup_hwmod;
++static struct omap_hwmod omap44xx_mmc1_hwmod;
++static struct omap_hwmod omap44xx_mmc2_hwmod;
+ static struct omap_hwmod omap44xx_mpu_hwmod;
+ static struct omap_hwmod omap44xx_mpu_private_hwmod;
+
+@@ -238,6 +244,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
++/* mmc1 -> l3_main_1 */
++static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
++ .master = &omap44xx_mmc1_hwmod,
++ .slave = &omap44xx_l3_main_1_hwmod,
++ .clk = "l3_div_ck",
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mmc2 -> l3_main_1 */
++static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
++ .master = &omap44xx_mmc2_hwmod,
++ .slave = &omap44xx_l3_main_1_hwmod,
++ .clk = "l3_div_ck",
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
+ /* mpu -> l3_main_1 */
+ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+ .master = &omap44xx_mpu_hwmod,
+@@ -252,6 +274,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+ &omap44xx_dss__l3_main_1,
+ &omap44xx_l3_main_2__l3_main_1,
+ &omap44xx_l4_cfg__l3_main_1,
++ &omap44xx_mmc1__l3_main_1,
++ &omap44xx_mmc2__l3_main_1,
+ &omap44xx_mpu__l3_main_1,
+ };
+
+@@ -272,6 +296,30 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
++/* hsi -> l3_main_2 */
++static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
++ .master = &omap44xx_hsi_hwmod,
++ .slave = &omap44xx_l3_main_2_hwmod,
++ .clk = "l3_div_ck",
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* ipu -> l3_main_2 */
++static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
++ .master = &omap44xx_ipu_hwmod,
++ .slave = &omap44xx_l3_main_2_hwmod,
++ .clk = "l3_div_ck",
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* iss -> l3_main_2 */
++static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
++ .master = &omap44xx_iss_hwmod,
++ .slave = &omap44xx_l3_main_2_hwmod,
++ .clk = "l3_div_ck",
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
+ /* iva -> l3_main_2 */
+ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
+ .master = &omap44xx_iva_hwmod,
+@@ -299,6 +347,9 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
+ /* l3_main_2 slave ports */
+ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+ &omap44xx_dma_system__l3_main_2,
++ &omap44xx_hsi__l3_main_2,
++ &omap44xx_ipu__l3_main_2,
++ &omap44xx_iss__l3_main_2,
+ &omap44xx_iva__l3_main_2,
+ &omap44xx_l3_main_1__l3_main_2,
+ &omap44xx_l4_cfg__l3_main_2,
+@@ -361,6 +412,14 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
+ };
+
+ /* l4_abe interface data */
++/* aess -> l4_abe */
++static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
++ .master = &omap44xx_aess_hwmod,
++ .slave = &omap44xx_l4_abe_hwmod,
++ .clk = "ocp_abe_iclk",
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
+ /* dsp -> l4_abe */
+ static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
+ .master = &omap44xx_dsp_hwmod,
+@@ -387,6 +446,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
+
+ /* l4_abe slave ports */
+ static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
++ &omap44xx_aess__l4_abe,
+ &omap44xx_dsp__l4_abe,
+ &omap44xx_l3_main_1__l4_abe,
+ &omap44xx_mpu__l4_abe,
+@@ -504,13 +564,10 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * - They still need to be validated with the driver
+ * properly adapted to omap_hwmod / omap_device
+ *
+- * aess
+- * bandgap
+ * c2c
+ * c2c_target_fw
+ * cm_core
+ * cm_core_aon
+- * counter_32k
+ * ctrl_module_core
+ * ctrl_module_pad_core
+ * ctrl_module_pad_wkup
+@@ -526,22 +583,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * gpu
+ * hdq1w
+ * hsi
+- * ipu
+- * iss
+- * kbd
+- * mcasp
+- * mcpdm
+- * mmc1
+- * mmc2
+- * mmc3
+- * mmc4
+- * mmc5
+- * mpu_c0
+- * mpu_c1
+ * ocmc_ram
+ * ocp2scp_usb_phy
+ * ocp_wp_noc
+- * prcm
+ * prcm_mpu
+ * prm
+ * scrm
+@@ -557,6 +601,194 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ */
+
+ /*
++ * 'aess' class
++ * audio engine sub system
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type2,
++};
++
++static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
++ .name = "aess",
++ .sysc = &omap44xx_aess_sysc,
++};
++
++/* aess */
++static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
++ { .irq = 99 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
++ { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
++ { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
++ { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
++ { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
++ { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
++ { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
++ { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
++ { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
++};
++
++/* aess master ports */
++static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
++ &omap44xx_aess__l4_abe,
++};
++
++static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
++ {
++ .pa_start = 0x401f1000,
++ .pa_end = 0x401f13ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> aess */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_aess_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_aess_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
++ {
++ .pa_start = 0x490f1000,
++ .pa_end = 0x490f13ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> aess (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_aess_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_aess_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* aess slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
++ &omap44xx_l4_abe__aess,
++ &omap44xx_l4_abe__aess_dma,
++};
++
++static struct omap_hwmod omap44xx_aess_hwmod = {
++ .name = "aess",
++ .class = &omap44xx_aess_hwmod_class,
++ .mpu_irqs = omap44xx_aess_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
++ .sdma_reqs = omap44xx_aess_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
++ .main_clk = "aess_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_aess_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
++ .masters = omap44xx_aess_masters,
++ .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
++ * 'bandgap' class
++ * bangap reference for ldo regulators
++ */
++
++static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
++ .name = "bandgap",
++};
++
++/* bandgap */
++static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
++ { .role = "fclk", .clk = "bandgap_fclk" },
++};
++
++static struct omap_hwmod omap44xx_bandgap_hwmod = {
++ .name = "bandgap",
++ .class = &omap44xx_bandgap_hwmod_class,
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
++ },
++ },
++ .opt_clks = bandgap_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
++ * 'counter' class
++ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0004,
++ .sysc_flags = SYSC_HAS_SIDLEMODE,
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
++ .name = "counter",
++ .sysc = &omap44xx_counter_sysc,
++};
++
++/* counter_32k */
++static struct omap_hwmod omap44xx_counter_32k_hwmod;
++static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
++ {
++ .pa_start = 0x4a304000,
++ .pa_end = 0x4a30401f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_wkup -> counter_32k */
++static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
++ .master = &omap44xx_l4_wkup_hwmod,
++ .slave = &omap44xx_counter_32k_hwmod,
++ .clk = "l4_wkup_clk_mux_ck",
++ .addr = omap44xx_counter_32k_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* counter_32k slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
++ &omap44xx_l4_wkup__counter_32k,
++};
++
++static struct omap_hwmod omap44xx_counter_32k_hwmod = {
++ .name = "counter_32k",
++ .class = &omap44xx_counter_hwmod_class,
++ .flags = HWMOD_SWSUP_SIDLE,
++ .main_clk = "sys_32k_ck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_counter_32k_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+@@ -1748,6 +1980,83 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
+ };
+
+ /*
++ * 'hsi' class
++ * mipi high-speed synchronous serial interface (multichannel and full-duplex
++ * serial if)
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
++ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
++ MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
++ .name = "hsi",
++ .sysc = &omap44xx_hsi_sysc,
++};
++
++/* hsi */
++static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
++ { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
++ { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
++ { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
++};
++
++/* hsi master ports */
++static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
++ &omap44xx_hsi__l3_main_2,
++};
++
++static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
++ {
++ .pa_start = 0x4a058000,
++ .pa_end = 0x4a05bfff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_cfg -> hsi */
++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
++ .master = &omap44xx_l4_cfg_hwmod,
++ .slave = &omap44xx_hsi_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_hsi_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* hsi slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
++ &omap44xx_l4_cfg__hsi,
++};
++
++static struct omap_hwmod omap44xx_hsi_hwmod = {
++ .name = "hsi",
++ .class = &omap44xx_hsi_hwmod_class,
++ .mpu_irqs = omap44xx_hsi_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
++ .main_clk = "hsi_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_hsi_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
++ .masters = omap44xx_hsi_masters,
++ .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+@@ -1981,6 +2290,188 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
+ };
+
+ /*
++ * 'ipu' class
++ * imaging processor unit
++ */
++
++static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
++ .name = "ipu",
++};
++
++/* ipu */
++static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
++ { .irq = 100 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
++ { .name = "cpu0", .rst_shift = 0 },
++};
++
++static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
++ { .name = "cpu1", .rst_shift = 1 },
++};
++
++static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
++ { .name = "mmu_cache", .rst_shift = 2 },
++};
++
++/* ipu master ports */
++static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
++ &omap44xx_ipu__l3_main_2,
++};
++
++/* l3_main_2 -> ipu */
++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
++ .master = &omap44xx_l3_main_2_hwmod,
++ .slave = &omap44xx_ipu_hwmod,
++ .clk = "l3_div_ck",
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* ipu slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
++ &omap44xx_l3_main_2__ipu,
++};
++
++/* Pseudo hwmod for reset control purpose only */
++static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
++ .name = "ipu_c0",
++ .class = &omap44xx_ipu_hwmod_class,
++ .flags = HWMOD_INIT_NO_RESET,
++ .rst_lines = omap44xx_ipu_c0_resets,
++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
++ .prcm = {
++ .omap4 = {
++ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
++ },
++ },
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* Pseudo hwmod for reset control purpose only */
++static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
++ .name = "ipu_c1",
++ .class = &omap44xx_ipu_hwmod_class,
++ .flags = HWMOD_INIT_NO_RESET,
++ .rst_lines = omap44xx_ipu_c1_resets,
++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
++ .prcm = {
++ .omap4 = {
++ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
++ },
++ },
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++static struct omap_hwmod omap44xx_ipu_hwmod = {
++ .name = "ipu",
++ .class = &omap44xx_ipu_hwmod_class,
++ .mpu_irqs = omap44xx_ipu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
++ .rst_lines = omap44xx_ipu_resets,
++ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
++ .main_clk = "ipu_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
++ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
++ },
++ },
++ .slaves = omap44xx_ipu_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
++ .masters = omap44xx_ipu_masters,
++ .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
++ * 'iss' class
++ * external images sensor pixel data processor
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
++ MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type2,
++};
++
++static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
++ .name = "iss",
++ .sysc = &omap44xx_iss_sysc,
++};
++
++/* iss */
++static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
++ { .irq = 24 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
++ { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
++ { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
++ { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
++ { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
++};
++
++/* iss master ports */
++static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
++ &omap44xx_iss__l3_main_2,
++};
++
++static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
++ {
++ .pa_start = 0x52000000,
++ .pa_end = 0x520000ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l3_main_2 -> iss */
++static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
++ .master = &omap44xx_l3_main_2_hwmod,
++ .slave = &omap44xx_iss_hwmod,
++ .clk = "l3_div_ck",
++ .addr = omap44xx_iss_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* iss slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
++ &omap44xx_l3_main_2__iss,
++};
++
++static struct omap_hwmod_opt_clk iss_opt_clks[] = {
++ { .role = "ctrlclk", .clk = "iss_ctrlclk" },
++};
++
++static struct omap_hwmod omap44xx_iss_hwmod = {
++ .name = "iss",
++ .class = &omap44xx_iss_hwmod_class,
++ .mpu_irqs = omap44xx_iss_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
++ .sdma_reqs = omap44xx_iss_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
++ .main_clk = "iss_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
++ },
++ },
++ .opt_clks = iss_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
++ .slaves = omap44xx_iss_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
++ .masters = omap44xx_iss_masters,
++ .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'iva' class
+ * multi-standard video encoder/decoder hardware accelerator
+ */
+@@ -2090,6 +2581,73 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
+ };
+
+ /*
++ * 'kbd' class
++ * keyboard controller
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
++ SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
++ SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
++ .name = "kbd",
++ .sysc = &omap44xx_kbd_sysc,
++};
++
++/* kbd */
++static struct omap_hwmod omap44xx_kbd_hwmod;
++static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
++ { .irq = 120 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
++ {
++ .pa_start = 0x4a31c000,
++ .pa_end = 0x4a31c07f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_wkup -> kbd */
++static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
++ .master = &omap44xx_l4_wkup_hwmod,
++ .slave = &omap44xx_kbd_hwmod,
++ .clk = "l4_wkup_clk_mux_ck",
++ .addr = omap44xx_kbd_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* kbd slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
++ &omap44xx_l4_wkup__kbd,
++};
++
++static struct omap_hwmod omap44xx_kbd_hwmod = {
++ .name = "kbd",
++ .class = &omap44xx_kbd_hwmod_class,
++ .mpu_irqs = omap44xx_kbd_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
++ .main_clk = "kbd_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_kbd_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+@@ -2437,6 +2995,98 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
+ };
+
+ /*
++ * 'mcpdm' class
++ * multi channel pdm controller (proprietary interface with phoenix power
++ * ic)
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP),
++ .sysc_fields = &omap_hwmod_sysc_type2,
++};
++
++static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
++ .name = "mcpdm",
++ .sysc = &omap44xx_mcpdm_sysc,
++};
++
++/* mcpdm */
++static struct omap_hwmod omap44xx_mcpdm_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
++ { .irq = 112 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
++ { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
++ { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
++ {
++ .pa_start = 0x40132000,
++ .pa_end = 0x4013207f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> mcpdm */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_mcpdm_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_mcpdm_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
++ .user = OCP_USER_MPU,
++};
++
++static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
++ {
++ .pa_start = 0x49032000,
++ .pa_end = 0x4903207f,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_abe -> mcpdm (dma) */
++static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
++ .master = &omap44xx_l4_abe_hwmod,
++ .slave = &omap44xx_mcpdm_hwmod,
++ .clk = "ocp_abe_iclk",
++ .addr = omap44xx_mcpdm_dma_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
++ .user = OCP_USER_SDMA,
++};
++
++/* mcpdm slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
++ &omap44xx_l4_abe__mcpdm,
++ &omap44xx_l4_abe__mcpdm_dma,
++};
++
++static struct omap_hwmod omap44xx_mcpdm_hwmod = {
++ .name = "mcpdm",
++ .class = &omap44xx_mcpdm_hwmod_class,
++ .mpu_irqs = omap44xx_mcpdm_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
++ .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
++ .main_clk = "mcpdm_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mcpdm_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+@@ -2676,6 +3326,300 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ };
+
+ /*
++ * 'mmc' class
++ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
++ SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
++ MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type2,
++};
++
++static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
++ .name = "mmc",
++ .sysc = &omap44xx_mmc_sysc,
++};
++
++/* mmc1 */
++static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
++ { .irq = 83 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
++};
++
++/* mmc1 master ports */
++static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
++ &omap44xx_mmc1__l3_main_1,
++};
++
++static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
++ {
++ .pa_start = 0x4809c000,
++ .pa_end = 0x4809c3ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mmc1 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mmc1_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mmc1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mmc1 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
++ &omap44xx_l4_per__mmc1,
++};
++
++static struct omap_hwmod omap44xx_mmc1_hwmod = {
++ .name = "mmc1",
++ .class = &omap44xx_mmc_hwmod_class,
++ .mpu_irqs = omap44xx_mmc1_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
++ .sdma_reqs = omap44xx_mmc1_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
++ .main_clk = "mmc1_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mmc1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
++ .masters = omap44xx_mmc1_masters,
++ .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mmc2 */
++static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
++ { .irq = 86 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
++};
++
++/* mmc2 master ports */
++static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
++ &omap44xx_mmc2__l3_main_1,
++};
++
++static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
++ {
++ .pa_start = 0x480b4000,
++ .pa_end = 0x480b43ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mmc2 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mmc2_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mmc2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mmc2 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
++ &omap44xx_l4_per__mmc2,
++};
++
++static struct omap_hwmod omap44xx_mmc2_hwmod = {
++ .name = "mmc2",
++ .class = &omap44xx_mmc_hwmod_class,
++ .mpu_irqs = omap44xx_mmc2_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
++ .sdma_reqs = omap44xx_mmc2_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
++ .main_clk = "mmc2_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mmc2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
++ .masters = omap44xx_mmc2_masters,
++ .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mmc3 */
++static struct omap_hwmod omap44xx_mmc3_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
++ { .irq = 94 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
++ {
++ .pa_start = 0x480ad000,
++ .pa_end = 0x480ad3ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mmc3 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mmc3_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mmc3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mmc3 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
++ &omap44xx_l4_per__mmc3,
++};
++
++static struct omap_hwmod omap44xx_mmc3_hwmod = {
++ .name = "mmc3",
++ .class = &omap44xx_mmc_hwmod_class,
++ .mpu_irqs = omap44xx_mmc3_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
++ .sdma_reqs = omap44xx_mmc3_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
++ .main_clk = "mmc3_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mmc3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mmc4 */
++static struct omap_hwmod omap44xx_mmc4_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
++ { .irq = 96 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
++ {
++ .pa_start = 0x480d1000,
++ .pa_end = 0x480d13ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mmc4 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mmc4_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mmc4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mmc4 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
++ &omap44xx_l4_per__mmc4,
++};
++
++static struct omap_hwmod omap44xx_mmc4_hwmod = {
++ .name = "mmc4",
++ .class = &omap44xx_mmc_hwmod_class,
++ .mpu_irqs = omap44xx_mmc4_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
++ .sdma_reqs = omap44xx_mmc4_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
++ .main_clk = "mmc4_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mmc4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/* mmc5 */
++static struct omap_hwmod omap44xx_mmc5_hwmod;
++static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
++ { .irq = 59 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
++ { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
++ {
++ .pa_start = 0x480d5000,
++ .pa_end = 0x480d53ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mmc5 */
++static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
++ .master = &omap44xx_l4_per_hwmod,
++ .slave = &omap44xx_mmc5_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_mmc5_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mmc5 slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
++ &omap44xx_l4_per__mmc5,
++};
++
++static struct omap_hwmod omap44xx_mmc5_hwmod = {
++ .name = "mmc5",
++ .class = &omap44xx_mmc_hwmod_class,
++ .mpu_irqs = omap44xx_mmc5_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
++ .sdma_reqs = omap44xx_mmc5_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
++ .main_clk = "mmc5_fck",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
++ },
++ },
++ .slaves = omap44xx_mmc5_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+@@ -3935,6 +4879,15 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ /* mpu_bus class */
+ &omap44xx_mpu_private_hwmod,
+
++ /* aess class */
++/* &omap44xx_aess_hwmod, */
++
++ /* bandgap class */
++ &omap44xx_bandgap_hwmod,
++
++ /* counter class */
++/* &omap44xx_counter_32k_hwmod, */
++
+ /* dma class */
+ &omap44xx_dma_system_hwmod,
+
+@@ -3962,17 +4915,31 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ &omap44xx_gpio5_hwmod,
+ &omap44xx_gpio6_hwmod,
+
++ /* hsi class */
++/* &omap44xx_hsi_hwmod, */
++
+ /* i2c class */
+ &omap44xx_i2c1_hwmod,
+ &omap44xx_i2c2_hwmod,
+ &omap44xx_i2c3_hwmod,
+ &omap44xx_i2c4_hwmod,
+
++ /* ipu class */
++ &omap44xx_ipu_hwmod,
++ &omap44xx_ipu_c0_hwmod,
++ &omap44xx_ipu_c1_hwmod,
++
++ /* iss class */
++/* &omap44xx_iss_hwmod, */
++
+ /* iva class */
+ &omap44xx_iva_hwmod,
+ &omap44xx_iva_seq0_hwmod,
+ &omap44xx_iva_seq1_hwmod,
+
++ /* kbd class */
++/* &omap44xx_kbd_hwmod, */
++
+ /* mailbox class */
+ &omap44xx_mailbox_hwmod,
+
+@@ -3982,12 +4949,22 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ &omap44xx_mcbsp3_hwmod,
+ &omap44xx_mcbsp4_hwmod,
+
++ /* mcpdm class */
++/* &omap44xx_mcpdm_hwmod, */
++
+ /* mcspi class */
+ &omap44xx_mcspi1_hwmod,
+ &omap44xx_mcspi2_hwmod,
+ &omap44xx_mcspi3_hwmod,
+ &omap44xx_mcspi4_hwmod,
+
++ /* mmc class */
++/* &omap44xx_mmc1_hwmod, */
++/* &omap44xx_mmc2_hwmod, */
++/* &omap44xx_mmc3_hwmod, */
++/* &omap44xx_mmc4_hwmod, */
++/* &omap44xx_mmc5_hwmod, */
++
+ /* mpu class */
+ &omap44xx_mpu_hwmod,
+
+--
+1.7.1
+
diff --git a/patches/for_next/0044-OMAP4-hwmod-data-Add-USBOTG.patch b/patches/for_next/0044-OMAP4-hwmod-data-Add-USBOTG.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b04f16746cfa081b0fb9aa85072641afb659b78c
--- /dev/null
+++ b/patches/for_next/0044-OMAP4-hwmod-data-Add-USBOTG.patch
@@ -0,0 +1,171 @@
+From f3676254e16c8f6f1bb1f4eb218fd959809c6b48 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Thu, 17 Feb 2011 12:41:05 +0000
+Subject: [PATCH 044/254] OMAP4: hwmod data: Add USBOTG
+
+OMAP4 hwmod data structures are populated with base address, L3 and L4
+interface clocks, IRQs and sysconfig register details.
+
+As per OMAP USBOTG specification, need to configure the USBOTG
+to smart idle/standby or no idle/standby during data transfer and
+force idle/standby when not in use to support retention and offmode.
+By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags,framework
+will take care of configuring to no idle/standby when module is enabled
+and force idle/standby when idled.
+
+Signed-off-by: Cousson, Benoit <b-cousson@ti.com>
+Signed-off-by: Hema HK <hemahk@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Kevin Hilman <khilman@deeprootsystems.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+[b-cousson@ti.com: Fix position, opt_clk, and author]
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 96 +++++++++++++++++++++++++++-
+ 1 files changed, 95 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 989bc96..84e795c 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -62,6 +62,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod;
+ static struct omap_hwmod omap44xx_mmc2_hwmod;
+ static struct omap_hwmod omap44xx_mpu_hwmod;
+ static struct omap_hwmod omap44xx_mpu_private_hwmod;
++static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
+
+ /*
+ * Interconnects omap_hwmod structures
+@@ -344,6 +345,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
++/* usb_otg_hs -> l3_main_2 */
++static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
++ .master = &omap44xx_usb_otg_hs_hwmod,
++ .slave = &omap44xx_l3_main_2_hwmod,
++ .clk = "l3_div_ck",
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
+ /* l3_main_2 slave ports */
+ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+ &omap44xx_dma_system__l3_main_2,
+@@ -353,6 +362,7 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+ &omap44xx_iva__l3_main_2,
+ &omap44xx_l3_main_1__l3_main_2,
+ &omap44xx_l4_cfg__l3_main_2,
++ &omap44xx_usb_otg_hs__l3_main_2,
+ };
+
+ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+@@ -594,7 +604,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+ * slimbus2
+ * usb_host_fs
+ * usb_host_hs
+- * usb_otg_hs
+ * usb_phy_cm
+ * usb_tll_hs
+ * usim
+@@ -4725,6 +4734,88 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
+ };
+
+ /*
++ * 'usb_otg_hs' class
++ * high-speed on-the-go universal serial bus (usb_otg_hs) controller
++ */
++
++static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
++ .rev_offs = 0x0400,
++ .sysc_offs = 0x0404,
++ .syss_offs = 0x0408,
++ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
++ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
++ MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
++ .name = "usb_otg_hs",
++ .sysc = &omap44xx_usb_otg_hs_sysc,
++};
++
++/* usb_otg_hs */
++static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
++ { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
++ { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
++};
++
++/* usb_otg_hs master ports */
++static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
++ &omap44xx_usb_otg_hs__l3_main_2,
++};
++
++static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
++ {
++ .pa_start = 0x4a0ab000,
++ .pa_end = 0x4a0ab003,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_cfg -> usb_otg_hs */
++static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
++ .master = &omap44xx_l4_cfg_hwmod,
++ .slave = &omap44xx_usb_otg_hs_hwmod,
++ .clk = "l4_div_ck",
++ .addr = omap44xx_usb_otg_hs_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* usb_otg_hs slave ports */
++static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
++ &omap44xx_l4_cfg__usb_otg_hs,
++};
++
++static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
++ { .role = "xclk", .clk = "usb_otg_hs_xclk" },
++};
++
++static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
++ .name = "usb_otg_hs",
++ .class = &omap44xx_usb_otg_hs_hwmod_class,
++ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
++ .mpu_irqs = omap44xx_usb_otg_hs_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
++ .main_clk = "usb_otg_hs_ick",
++ .prcm = {
++ .omap4 = {
++ .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
++ },
++ },
++ .opt_clks = usb_otg_hs_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
++ .slaves = omap44xx_usb_otg_hs_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
++ .masters = omap44xx_usb_otg_hs_masters,
++ .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
++};
++
++/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+@@ -4995,6 +5086,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ &omap44xx_uart3_hwmod,
+ &omap44xx_uart4_hwmod,
+
++ /* usb_otg_hs class */
++ &omap44xx_usb_otg_hs_hwmod,
++
+ /* wd_timer class */
+ &omap44xx_wd_timer2_hwmod,
+ &omap44xx_wd_timer3_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0045-drivers-hwspinlock-add-framework.patch b/patches/for_next/0045-drivers-hwspinlock-add-framework.patch
new file mode 100644
index 0000000000000000000000000000000000000000..73cba203fd83e1b6f2ed9338444b2e62bda70c83
--- /dev/null
+++ b/patches/for_next/0045-drivers-hwspinlock-add-framework.patch
@@ -0,0 +1,1310 @@
+From 877cd32ff0c6b9f0a0f638a98595329a503c71be Mon Sep 17 00:00:00 2001
+From: Ohad Ben-Cohen <ohad@wizery.com>
+Date: Thu, 17 Feb 2011 09:52:03 -0800
+Subject: [PATCH 045/254] drivers: hwspinlock: add framework
+
+Add a platform-independent hwspinlock framework.
+
+Hardware spinlock devices are needed, e.g., in order to access data
+that is shared between remote processors, that otherwise have no
+alternative mechanism to accomplish synchronization and mutual exclusion
+operations.
+
+Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
+Cc: Hari Kanigeri <h-kanigeri2@ti.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Grant Likely <grant.likely@secretlab.ca>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Russell King <linux@arm.linux.org.uk>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ Documentation/hwspinlock.txt | 293 ++++++++++++++++
+ drivers/Kconfig | 2 +
+ drivers/Makefile | 2 +
+ drivers/hwspinlock/Kconfig | 13 +
+ drivers/hwspinlock/Makefile | 5 +
+ drivers/hwspinlock/hwspinlock_core.c | 548 ++++++++++++++++++++++++++++++
+ drivers/hwspinlock/hwspinlock_internal.h | 61 ++++
+ include/linux/hwspinlock.h | 292 ++++++++++++++++
+ 8 files changed, 1216 insertions(+), 0 deletions(-)
+ create mode 100644 Documentation/hwspinlock.txt
+ create mode 100644 drivers/hwspinlock/Kconfig
+ create mode 100644 drivers/hwspinlock/Makefile
+ create mode 100644 drivers/hwspinlock/hwspinlock_core.c
+ create mode 100644 drivers/hwspinlock/hwspinlock_internal.h
+ create mode 100644 include/linux/hwspinlock.h
+
+diff --git a/Documentation/hwspinlock.txt b/Documentation/hwspinlock.txt
+new file mode 100644
+index 0000000..7dcd1a4
+--- /dev/null
++++ b/Documentation/hwspinlock.txt
+@@ -0,0 +1,293 @@
++Hardware Spinlock Framework
++
++1. Introduction
++
++Hardware spinlock modules provide hardware assistance for synchronization
++and mutual exclusion between heterogeneous processors and those not operating
++under a single, shared operating system.
++
++For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP,
++each of which is running a different Operating System (the master, A9,
++is usually running Linux and the slave processors, the M3 and the DSP,
++are running some flavor of RTOS).
++
++A generic hwspinlock framework allows platform-independent drivers to use
++the hwspinlock device in order to access data structures that are shared
++between remote processors, that otherwise have no alternative mechanism
++to accomplish synchronization and mutual exclusion operations.
++
++This is necessary, for example, for Inter-processor communications:
++on OMAP4, cpu-intensive multimedia tasks are offloaded by the host to the
++remote M3 and/or C64x+ slave processors (by an IPC subsystem called Syslink).
++
++To achieve fast message-based communications, a minimal kernel support
++is needed to deliver messages arriving from a remote processor to the
++appropriate user process.
++
++This communication is based on simple data structures that is shared between
++the remote processors, and access to it is synchronized using the hwspinlock
++module (remote processor directly places new messages in this shared data
++structure).
++
++A common hwspinlock interface makes it possible to have generic, platform-
++independent, drivers.
++
++2. User API
++
++ struct hwspinlock *hwspin_lock_request(void);
++ - dynamically assign an hwspinlock and return its address, or NULL
++ in case an unused hwspinlock isn't available. Users of this
++ API will usually want to communicate the lock's id to the remote core
++ before it can be used to achieve synchronization.
++ Can be called from an atomic context (this function will not sleep) but
++ not from within interrupt context.
++
++ struct hwspinlock *hwspin_lock_request_specific(unsigned int id);
++ - assign a specific hwspinlock id and return its address, or NULL
++ if that hwspinlock is already in use. Usually board code will
++ be calling this function in order to reserve specific hwspinlock
++ ids for predefined purposes.
++ Can be called from an atomic context (this function will not sleep) but
++ not from within interrupt context.
++
++ int hwspin_lock_free(struct hwspinlock *hwlock);
++ - free a previously-assigned hwspinlock; returns 0 on success, or an
++ appropriate error code on failure (e.g. -EINVAL if the hwspinlock
++ is already free).
++ Can be called from an atomic context (this function will not sleep) but
++ not from within interrupt context.
++
++ int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int timeout);
++ - lock a previously-assigned hwspinlock with a timeout limit (specified in
++ msecs). If the hwspinlock is already taken, the function will busy loop
++ waiting for it to be released, but give up when the timeout elapses.
++ Upon a successful return from this function, preemption is disabled so
++ the caller must not sleep, and is advised to release the hwspinlock as
++ soon as possible, in order to minimize remote cores polling on the
++ hardware interconnect.
++ Returns 0 when successful and an appropriate error code otherwise (most
++ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
++ The function will never sleep.
++
++ int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int timeout);
++ - lock a previously-assigned hwspinlock with a timeout limit (specified in
++ msecs). If the hwspinlock is already taken, the function will busy loop
++ waiting for it to be released, but give up when the timeout elapses.
++ Upon a successful return from this function, preemption and the local
++ interrupts are disabled, so the caller must not sleep, and is advised to
++ release the hwspinlock as soon as possible.
++ Returns 0 when successful and an appropriate error code otherwise (most
++ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
++ The function will never sleep.
++
++ int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock, unsigned int to,
++ unsigned long *flags);
++ - lock a previously-assigned hwspinlock with a timeout limit (specified in
++ msecs). If the hwspinlock is already taken, the function will busy loop
++ waiting for it to be released, but give up when the timeout elapses.
++ Upon a successful return from this function, preemption is disabled,
++ local interrupts are disabled and their previous state is saved at the
++ given flags placeholder. The caller must not sleep, and is advised to
++ release the hwspinlock as soon as possible.
++ Returns 0 when successful and an appropriate error code otherwise (most
++ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs).
++ The function will never sleep.
++
++ int hwspin_trylock(struct hwspinlock *hwlock);
++ - attempt to lock a previously-assigned hwspinlock, but immediately fail if
++ it is already taken.
++ Upon a successful return from this function, preemption is disabled so
++ caller must not sleep, and is advised to release the hwspinlock as soon as
++ possible, in order to minimize remote cores polling on the hardware
++ interconnect.
++ Returns 0 on success and an appropriate error code otherwise (most
++ notably -EBUSY if the hwspinlock was already taken).
++ The function will never sleep.
++
++ int hwspin_trylock_irq(struct hwspinlock *hwlock);
++ - attempt to lock a previously-assigned hwspinlock, but immediately fail if
++ it is already taken.
++ Upon a successful return from this function, preemption and the local
++ interrupts are disabled so caller must not sleep, and is advised to
++ release the hwspinlock as soon as possible.
++ Returns 0 on success and an appropriate error code otherwise (most
++ notably -EBUSY if the hwspinlock was already taken).
++ The function will never sleep.
++
++ int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags);
++ - attempt to lock a previously-assigned hwspinlock, but immediately fail if
++ it is already taken.
++ Upon a successful return from this function, preemption is disabled,
++ the local interrupts are disabled and their previous state is saved
++ at the given flags placeholder. The caller must not sleep, and is advised
++ to release the hwspinlock as soon as possible.
++ Returns 0 on success and an appropriate error code otherwise (most
++ notably -EBUSY if the hwspinlock was already taken).
++ The function will never sleep.
++
++ void hwspin_unlock(struct hwspinlock *hwlock);
++ - unlock a previously-locked hwspinlock. Always succeed, and can be called
++ from any context (the function never sleeps). Note: code should _never_
++ unlock an hwspinlock which is already unlocked (there is no protection
++ against this).
++
++ void hwspin_unlock_irq(struct hwspinlock *hwlock);
++ - unlock a previously-locked hwspinlock and enable local interrupts.
++ The caller should _never_ unlock an hwspinlock which is already unlocked.
++ Doing so is considered a bug (there is no protection against this).
++ Upon a successful return from this function, preemption and local
++ interrupts are enabled. This function will never sleep.
++
++ void
++ hwspin_unlock_irqrestore(struct hwspinlock *hwlock, unsigned long *flags);
++ - unlock a previously-locked hwspinlock.
++ The caller should _never_ unlock an hwspinlock which is already unlocked.
++ Doing so is considered a bug (there is no protection against this).
++ Upon a successful return from this function, preemption is reenabled,
++ and the state of the local interrupts is restored to the state saved at
++ the given flags. This function will never sleep.
++
++ int hwspin_lock_get_id(struct hwspinlock *hwlock);
++ - retrieve id number of a given hwspinlock. This is needed when an
++ hwspinlock is dynamically assigned: before it can be used to achieve
++ mutual exclusion with a remote cpu, the id number should be communicated
++ to the remote task with which we want to synchronize.
++ Returns the hwspinlock id number, or -EINVAL if hwlock is null.
++
++3. Typical usage
++
++#include <linux/hwspinlock.h>
++#include <linux/err.h>
++
++int hwspinlock_example1(void)
++{
++ struct hwspinlock *hwlock;
++ int ret;
++
++ /* dynamically assign a hwspinlock */
++ hwlock = hwspin_lock_request();
++ if (!hwlock)
++ ...
++
++ id = hwspin_lock_get_id(hwlock);
++ /* probably need to communicate id to a remote processor now */
++
++ /* take the lock, spin for 1 sec if it's already taken */
++ ret = hwspin_lock_timeout(hwlock, 1000);
++ if (ret)
++ ...
++
++ /*
++ * we took the lock, do our thing now, but do NOT sleep
++ */
++
++ /* release the lock */
++ hwspin_unlock(hwlock);
++
++ /* free the lock */
++ ret = hwspin_lock_free(hwlock);
++ if (ret)
++ ...
++
++ return ret;
++}
++
++int hwspinlock_example2(void)
++{
++ struct hwspinlock *hwlock;
++ int ret;
++
++ /*
++ * assign a specific hwspinlock id - this should be called early
++ * by board init code.
++ */
++ hwlock = hwspin_lock_request_specific(PREDEFINED_LOCK_ID);
++ if (!hwlock)
++ ...
++
++ /* try to take it, but don't spin on it */
++ ret = hwspin_trylock(hwlock);
++ if (!ret) {
++ pr_info("lock is already taken\n");
++ return -EBUSY;
++ }
++
++ /*
++ * we took the lock, do our thing now, but do NOT sleep
++ */
++
++ /* release the lock */
++ hwspin_unlock(hwlock);
++
++ /* free the lock */
++ ret = hwspin_lock_free(hwlock);
++ if (ret)
++ ...
++
++ return ret;
++}
++
++
++4. API for implementors
++
++ int hwspin_lock_register(struct hwspinlock *hwlock);
++ - to be called from the underlying platform-specific implementation, in
++ order to register a new hwspinlock instance. Can be called from an atomic
++ context (this function will not sleep) but not from within interrupt
++ context. Returns 0 on success, or appropriate error code on failure.
++
++ struct hwspinlock *hwspin_lock_unregister(unsigned int id);
++ - to be called from the underlying vendor-specific implementation, in order
++ to unregister an existing (and unused) hwspinlock instance.
++ Can be called from an atomic context (will not sleep) but not from
++ within interrupt context.
++ Returns the address of hwspinlock on success, or NULL on error (e.g.
++ if the hwspinlock is sill in use).
++
++5. struct hwspinlock
++
++This struct represents an hwspinlock instance. It is registered by the
++underlying hwspinlock implementation using the hwspin_lock_register() API.
++
++/**
++ * struct hwspinlock - vendor-specific hwspinlock implementation
++ *
++ * @dev: underlying device, will be used with runtime PM api
++ * @ops: vendor-specific hwspinlock handlers
++ * @id: a global, unique, system-wide, index of the lock.
++ * @lock: initialized and used by hwspinlock core
++ * @owner: underlying implementation module, used to maintain module ref count
++ */
++struct hwspinlock {
++ struct device *dev;
++ const struct hwspinlock_ops *ops;
++ int id;
++ spinlock_t lock;
++ struct module *owner;
++};
++
++The underlying implementation is responsible to assign the dev, ops, id and
++owner members. The lock member, OTOH, is initialized and used by the hwspinlock
++core.
++
++6. Implementation callbacks
++
++There are three possible callbacks defined in 'struct hwspinlock_ops':
++
++struct hwspinlock_ops {
++ int (*trylock)(struct hwspinlock *lock);
++ void (*unlock)(struct hwspinlock *lock);
++ void (*relax)(struct hwspinlock *lock);
++};
++
++The first two callbacks are mandatory:
++
++The ->trylock() callback should make a single attempt to take the lock, and
++return 0 on failure and 1 on success. This callback may _not_ sleep.
++
++The ->unlock() callback releases the lock. It always succeed, and it, too,
++may _not_ sleep.
++
++The ->relax() callback is optional. It is called by hwspinlock core while
++spinning on a lock, and can be used by the underlying implementation to force
++a delay between two successive invocations of ->trylock(). It may _not_ sleep.
+diff --git a/drivers/Kconfig b/drivers/Kconfig
+index 9bfb71f..177c7d1 100644
+--- a/drivers/Kconfig
++++ b/drivers/Kconfig
+@@ -117,4 +117,6 @@ source "drivers/staging/Kconfig"
+ source "drivers/platform/Kconfig"
+
+ source "drivers/clk/Kconfig"
++
++source "drivers/hwspinlock/Kconfig"
+ endmenu
+diff --git a/drivers/Makefile b/drivers/Makefile
+index b423bb1..3f135b6 100644
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -117,3 +117,5 @@ obj-y += platform/
+ obj-y += ieee802154/
+ #common clk code
+ obj-y += clk/
++
++obj-$(CONFIG_HWSPINLOCK) += hwspinlock/
+diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
+new file mode 100644
+index 0000000..9dd8db4
+--- /dev/null
++++ b/drivers/hwspinlock/Kconfig
+@@ -0,0 +1,13 @@
++#
++# Generic HWSPINLOCK framework
++#
++
++config HWSPINLOCK
++ tristate "Generic Hardware Spinlock framework"
++ help
++ Say y here to support the generic hardware spinlock framework.
++ You only need to enable this if you have hardware spinlock module
++ on your system (usually only relevant if your system has remote slave
++ coprocessors).
++
++ If unsure, say N.
+diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile
+new file mode 100644
+index 0000000..b9d2b9f
+--- /dev/null
++++ b/drivers/hwspinlock/Makefile
+@@ -0,0 +1,5 @@
++#
++# Generic Hardware Spinlock framework
++#
++
++obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o
+diff --git a/drivers/hwspinlock/hwspinlock_core.c b/drivers/hwspinlock/hwspinlock_core.c
+new file mode 100644
+index 0000000..43a6271
+--- /dev/null
++++ b/drivers/hwspinlock/hwspinlock_core.c
+@@ -0,0 +1,548 @@
++/*
++ * Hardware spinlock framework
++ *
++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Contact: Ohad Ben-Cohen <ohad@wizery.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#define pr_fmt(fmt) "%s: " fmt, __func__
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++#include <linux/err.h>
++#include <linux/jiffies.h>
++#include <linux/radix-tree.h>
++#include <linux/hwspinlock.h>
++#include <linux/pm_runtime.h>
++
++#include "hwspinlock_internal.h"
++
++/* radix tree tags */
++#define HWSPINLOCK_UNUSED (0) /* tags an hwspinlock as unused */
++
++/*
++ * A radix tree is used to maintain the available hwspinlock instances.
++ * The tree associates hwspinlock pointers with their integer key id,
++ * and provides easy-to-use API which makes the hwspinlock core code simple
++ * and easy to read.
++ *
++ * Radix trees are quick on lookups, and reasonably efficient in terms of
++ * storage, especially with high density usages such as this framework
++ * requires (a continuous range of integer keys, beginning with zero, is
++ * used as the ID's of the hwspinlock instances).
++ *
++ * The radix tree API supports tagging items in the tree, which this
++ * framework uses to mark unused hwspinlock instances (see the
++ * HWSPINLOCK_UNUSED tag above). As a result, the process of querying the
++ * tree, looking for an unused hwspinlock instance, is now reduced to a
++ * single radix tree API call.
++ */
++static RADIX_TREE(hwspinlock_tree, GFP_KERNEL);
++
++/*
++ * Synchronization of access to the tree is achieved using this spinlock,
++ * as the radix-tree API requires that users provide all synchronisation.
++ */
++static DEFINE_SPINLOCK(hwspinlock_tree_lock);
++
++/**
++ * __hwspin_trylock() - attempt to lock a specific hwspinlock
++ * @hwlock: an hwspinlock which we want to trylock
++ * @mode: controls whether local interrupts are disabled or not
++ * @flags: a pointer where the caller's interrupt state will be saved at (if
++ * requested)
++ *
++ * This function attempts to lock an hwspinlock, and will immediately
++ * fail if the hwspinlock is already taken.
++ *
++ * Upon a successful return from this function, preemption (and possibly
++ * interrupts) is disabled, so the caller must not sleep, and is advised to
++ * release the hwspinlock as soon as possible. This is required in order to
++ * minimize remote cores polling on the hardware interconnect.
++ *
++ * The user decides whether local interrupts are disabled or not, and if yes,
++ * whether he wants their previous state to be saved. It is up to the user
++ * to choose the appropriate @mode of operation, exactly the same way users
++ * should decide between spin_trylock, spin_trylock_irq and
++ * spin_trylock_irqsave.
++ *
++ * Returns 0 if we successfully locked the hwspinlock or -EBUSY if
++ * the hwspinlock was already taken.
++ * This function will never sleep.
++ */
++int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags)
++{
++ int ret;
++
++ BUG_ON(!hwlock);
++ BUG_ON(!flags && mode == HWLOCK_IRQSTATE);
++
++ /*
++ * This spin_lock{_irq, _irqsave} serves three purposes:
++ *
++ * 1. Disable preemption, in order to minimize the period of time
++ * in which the hwspinlock is taken. This is important in order
++ * to minimize the possible polling on the hardware interconnect
++ * by a remote user of this lock.
++ * 2. Make the hwspinlock SMP-safe (so we can take it from
++ * additional contexts on the local host).
++ * 3. Ensure that in_atomic/might_sleep checks catch potential
++ * problems with hwspinlock usage (e.g. scheduler checks like
++ * 'scheduling while atomic' etc.)
++ */
++ if (mode == HWLOCK_IRQSTATE)
++ ret = spin_trylock_irqsave(&hwlock->lock, *flags);
++ else if (mode == HWLOCK_IRQ)
++ ret = spin_trylock_irq(&hwlock->lock);
++ else
++ ret = spin_trylock(&hwlock->lock);
++
++ /* is lock already taken by another context on the local cpu ? */
++ if (!ret)
++ return -EBUSY;
++
++ /* try to take the hwspinlock device */
++ ret = hwlock->ops->trylock(hwlock);
++
++ /* if hwlock is already taken, undo spin_trylock_* and exit */
++ if (!ret) {
++ if (mode == HWLOCK_IRQSTATE)
++ spin_unlock_irqrestore(&hwlock->lock, *flags);
++ else if (mode == HWLOCK_IRQ)
++ spin_unlock_irq(&hwlock->lock);
++ else
++ spin_unlock(&hwlock->lock);
++
++ return -EBUSY;
++ }
++
++ /*
++ * We can be sure the other core's memory operations
++ * are observable to us only _after_ we successfully take
++ * the hwspinlock, and we must make sure that subsequent memory
++ * operations (both reads and writes) will not be reordered before
++ * we actually took the hwspinlock.
++ *
++ * Note: the implicit memory barrier of the spinlock above is too
++ * early, so we need this additional explicit memory barrier.
++ */
++ mb();
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(__hwspin_trylock);
++
++/**
++ * __hwspin_lock_timeout() - lock an hwspinlock with timeout limit
++ * @hwlock: the hwspinlock to be locked
++ * @timeout: timeout value in msecs
++ * @mode: mode which controls whether local interrupts are disabled or not
++ * @flags: a pointer to where the caller's interrupt state will be saved at (if
++ * requested)
++ *
++ * This function locks the given @hwlock. If the @hwlock
++ * is already taken, the function will busy loop waiting for it to
++ * be released, but give up after @timeout msecs have elapsed.
++ *
++ * Upon a successful return from this function, preemption is disabled
++ * (and possibly local interrupts, too), so the caller must not sleep,
++ * and is advised to release the hwspinlock as soon as possible.
++ * This is required in order to minimize remote cores polling on the
++ * hardware interconnect.
++ *
++ * The user decides whether local interrupts are disabled or not, and if yes,
++ * whether he wants their previous state to be saved. It is up to the user
++ * to choose the appropriate @mode of operation, exactly the same way users
++ * should decide between spin_lock, spin_lock_irq and spin_lock_irqsave.
++ *
++ * Returns 0 when the @hwlock was successfully taken, and an appropriate
++ * error code otherwise (most notably -ETIMEDOUT if the @hwlock is still
++ * busy after @timeout msecs). The function will never sleep.
++ */
++int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to,
++ int mode, unsigned long *flags)
++{
++ int ret;
++ unsigned long expire;
++
++ expire = msecs_to_jiffies(to) + jiffies;
++
++ for (;;) {
++ /* Try to take the hwspinlock */
++ ret = __hwspin_trylock(hwlock, mode, flags);
++ if (ret != -EBUSY)
++ break;
++
++ /*
++ * The lock is already taken, let's check if the user wants
++ * us to try again
++ */
++ if (time_is_before_eq_jiffies(expire))
++ return -ETIMEDOUT;
++
++ /*
++ * Allow platform-specific relax handlers to prevent
++ * hogging the interconnect (no sleeping, though)
++ */
++ if (hwlock->ops->relax)
++ hwlock->ops->relax(hwlock);
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(__hwspin_lock_timeout);
++
++/**
++ * __hwspin_unlock() - unlock a specific hwspinlock
++ * @hwlock: a previously-acquired hwspinlock which we want to unlock
++ * @mode: controls whether local interrupts needs to be restored or not
++ * @flags: previous caller's interrupt state to restore (if requested)
++ *
++ * This function will unlock a specific hwspinlock, enable preemption and
++ * (possibly) enable interrupts or restore their previous state.
++ * @hwlock must be already locked before calling this function: it is a bug
++ * to call unlock on a @hwlock that is already unlocked.
++ *
++ * The user decides whether local interrupts should be enabled or not, and
++ * if yes, whether he wants their previous state to be restored. It is up
++ * to the user to choose the appropriate @mode of operation, exactly the
++ * same way users decide between spin_unlock, spin_unlock_irq and
++ * spin_unlock_irqrestore.
++ *
++ * The function will never sleep.
++ */
++void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags)
++{
++ BUG_ON(!hwlock);
++ BUG_ON(!flags && mode == HWLOCK_IRQSTATE);
++
++ /*
++ * We must make sure that memory operations (both reads and writes),
++ * done before unlocking the hwspinlock, will not be reordered
++ * after the lock is released.
++ *
++ * That's the purpose of this explicit memory barrier.
++ *
++ * Note: the memory barrier induced by the spin_unlock below is too
++ * late; the other core is going to access memory soon after it will
++ * take the hwspinlock, and by then we want to be sure our memory
++ * operations are already observable.
++ */
++ mb();
++
++ hwlock->ops->unlock(hwlock);
++
++ /* Undo the spin_trylock{_irq, _irqsave} called while locking */
++ if (mode == HWLOCK_IRQSTATE)
++ spin_unlock_irqrestore(&hwlock->lock, *flags);
++ else if (mode == HWLOCK_IRQ)
++ spin_unlock_irq(&hwlock->lock);
++ else
++ spin_unlock(&hwlock->lock);
++}
++EXPORT_SYMBOL_GPL(__hwspin_unlock);
++
++/**
++ * hwspin_lock_register() - register a new hw spinlock
++ * @hwlock: hwspinlock to register.
++ *
++ * This function should be called from the underlying platform-specific
++ * implementation, to register a new hwspinlock instance.
++ *
++ * Can be called from an atomic context (will not sleep) but not from
++ * within interrupt context.
++ *
++ * Returns 0 on success, or an appropriate error code on failure
++ */
++int hwspin_lock_register(struct hwspinlock *hwlock)
++{
++ struct hwspinlock *tmp;
++ int ret;
++
++ if (!hwlock || !hwlock->ops ||
++ !hwlock->ops->trylock || !hwlock->ops->unlock) {
++ pr_err("invalid parameters\n");
++ return -EINVAL;
++ }
++
++ spin_lock_init(&hwlock->lock);
++
++ spin_lock(&hwspinlock_tree_lock);
++
++ ret = radix_tree_insert(&hwspinlock_tree, hwlock->id, hwlock);
++ if (ret)
++ goto out;
++
++ /* mark this hwspinlock as available */
++ tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock->id,
++ HWSPINLOCK_UNUSED);
++
++ /* self-sanity check which should never fail */
++ WARN_ON(tmp != hwlock);
++
++out:
++ spin_unlock(&hwspinlock_tree_lock);
++ return ret;
++}
++EXPORT_SYMBOL_GPL(hwspin_lock_register);
++
++/**
++ * hwspin_lock_unregister() - unregister an hw spinlock
++ * @id: index of the specific hwspinlock to unregister
++ *
++ * This function should be called from the underlying platform-specific
++ * implementation, to unregister an existing (and unused) hwspinlock.
++ *
++ * Can be called from an atomic context (will not sleep) but not from
++ * within interrupt context.
++ *
++ * Returns the address of hwspinlock @id on success, or NULL on failure
++ */
++struct hwspinlock *hwspin_lock_unregister(unsigned int id)
++{
++ struct hwspinlock *hwlock = NULL;
++ int ret;
++
++ spin_lock(&hwspinlock_tree_lock);
++
++ /* make sure the hwspinlock is not in use (tag is set) */
++ ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED);
++ if (ret == 0) {
++ pr_err("hwspinlock %d still in use (or not present)\n", id);
++ goto out;
++ }
++
++ hwlock = radix_tree_delete(&hwspinlock_tree, id);
++ if (!hwlock) {
++ pr_err("failed to delete hwspinlock %d\n", id);
++ goto out;
++ }
++
++out:
++ spin_unlock(&hwspinlock_tree_lock);
++ return hwlock;
++}
++EXPORT_SYMBOL_GPL(hwspin_lock_unregister);
++
++/**
++ * __hwspin_lock_request() - tag an hwspinlock as used and power it up
++ *
++ * This is an internal function that prepares an hwspinlock instance
++ * before it is given to the user. The function assumes that
++ * hwspinlock_tree_lock is taken.
++ *
++ * Returns 0 or positive to indicate success, and a negative value to
++ * indicate an error (with the appropriate error code)
++ */
++static int __hwspin_lock_request(struct hwspinlock *hwlock)
++{
++ struct hwspinlock *tmp;
++ int ret;
++
++ /* prevent underlying implementation from being removed */
++ if (!try_module_get(hwlock->owner)) {
++ dev_err(hwlock->dev, "%s: can't get owner\n", __func__);
++ return -EINVAL;
++ }
++
++ /* notify PM core that power is now needed */
++ ret = pm_runtime_get_sync(hwlock->dev);
++ if (ret < 0) {
++ dev_err(hwlock->dev, "%s: can't power on device\n", __func__);
++ return ret;
++ }
++
++ /* mark hwspinlock as used, should not fail */
++ tmp = radix_tree_tag_clear(&hwspinlock_tree, hwlock->id,
++ HWSPINLOCK_UNUSED);
++
++ /* self-sanity check that should never fail */
++ WARN_ON(tmp != hwlock);
++
++ return ret;
++}
++
++/**
++ * hwspin_lock_get_id() - retrieve id number of a given hwspinlock
++ * @hwlock: a valid hwspinlock instance
++ *
++ * Returns the id number of a given @hwlock, or -EINVAL if @hwlock is invalid.
++ */
++int hwspin_lock_get_id(struct hwspinlock *hwlock)
++{
++ if (!hwlock) {
++ pr_err("invalid hwlock\n");
++ return -EINVAL;
++ }
++
++ return hwlock->id;
++}
++EXPORT_SYMBOL_GPL(hwspin_lock_get_id);
++
++/**
++ * hwspin_lock_request() - request an hwspinlock
++ *
++ * This function should be called by users of the hwspinlock device,
++ * in order to dynamically assign them an unused hwspinlock.
++ * Usually the user of this lock will then have to communicate the lock's id
++ * to the remote core before it can be used for synchronization (to get the
++ * id of a given hwlock, use hwspin_lock_get_id()).
++ *
++ * Can be called from an atomic context (will not sleep) but not from
++ * within interrupt context (simply because there is no use case for
++ * that yet).
++ *
++ * Returns the address of the assigned hwspinlock, or NULL on error
++ */
++struct hwspinlock *hwspin_lock_request(void)
++{
++ struct hwspinlock *hwlock;
++ int ret;
++
++ spin_lock(&hwspinlock_tree_lock);
++
++ /* look for an unused lock */
++ ret = radix_tree_gang_lookup_tag(&hwspinlock_tree, (void **)&hwlock,
++ 0, 1, HWSPINLOCK_UNUSED);
++ if (ret == 0) {
++ pr_warn("a free hwspinlock is not available\n");
++ hwlock = NULL;
++ goto out;
++ }
++
++ /* sanity check that should never fail */
++ WARN_ON(ret > 1);
++
++ /* mark as used and power up */
++ ret = __hwspin_lock_request(hwlock);
++ if (ret < 0)
++ hwlock = NULL;
++
++out:
++ spin_unlock(&hwspinlock_tree_lock);
++ return hwlock;
++}
++EXPORT_SYMBOL_GPL(hwspin_lock_request);
++
++/**
++ * hwspin_lock_request_specific() - request for a specific hwspinlock
++ * @id: index of the specific hwspinlock that is requested
++ *
++ * This function should be called by users of the hwspinlock module,
++ * in order to assign them a specific hwspinlock.
++ * Usually early board code will be calling this function in order to
++ * reserve specific hwspinlock ids for predefined purposes.
++ *
++ * Can be called from an atomic context (will not sleep) but not from
++ * within interrupt context (simply because there is no use case for
++ * that yet).
++ *
++ * Returns the address of the assigned hwspinlock, or NULL on error
++ */
++struct hwspinlock *hwspin_lock_request_specific(unsigned int id)
++{
++ struct hwspinlock *hwlock;
++ int ret;
++
++ spin_lock(&hwspinlock_tree_lock);
++
++ /* make sure this hwspinlock exists */
++ hwlock = radix_tree_lookup(&hwspinlock_tree, id);
++ if (!hwlock) {
++ pr_warn("hwspinlock %u does not exist\n", id);
++ goto out;
++ }
++
++ /* sanity check (this shouldn't happen) */
++ WARN_ON(hwlock->id != id);
++
++ /* make sure this hwspinlock is unused */
++ ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED);
++ if (ret == 0) {
++ pr_warn("hwspinlock %u is already in use\n", id);
++ hwlock = NULL;
++ goto out;
++ }
++
++ /* mark as used and power up */
++ ret = __hwspin_lock_request(hwlock);
++ if (ret < 0)
++ hwlock = NULL;
++
++out:
++ spin_unlock(&hwspinlock_tree_lock);
++ return hwlock;
++}
++EXPORT_SYMBOL_GPL(hwspin_lock_request_specific);
++
++/**
++ * hwspin_lock_free() - free a specific hwspinlock
++ * @hwlock: the specific hwspinlock to free
++ *
++ * This function mark @hwlock as free again.
++ * Should only be called with an @hwlock that was retrieved from
++ * an earlier call to omap_hwspin_lock_request{_specific}.
++ *
++ * Can be called from an atomic context (will not sleep) but not from
++ * within interrupt context (simply because there is no use case for
++ * that yet).
++ *
++ * Returns 0 on success, or an appropriate error code on failure
++ */
++int hwspin_lock_free(struct hwspinlock *hwlock)
++{
++ struct hwspinlock *tmp;
++ int ret;
++
++ if (!hwlock) {
++ pr_err("invalid hwlock\n");
++ return -EINVAL;
++ }
++
++ spin_lock(&hwspinlock_tree_lock);
++
++ /* make sure the hwspinlock is used */
++ ret = radix_tree_tag_get(&hwspinlock_tree, hwlock->id,
++ HWSPINLOCK_UNUSED);
++ if (ret == 1) {
++ dev_err(hwlock->dev, "%s: hwlock is already free\n", __func__);
++ dump_stack();
++ ret = -EINVAL;
++ goto out;
++ }
++
++ /* notify the underlying device that power is not needed */
++ ret = pm_runtime_put(hwlock->dev);
++ if (ret < 0)
++ goto out;
++
++ /* mark this hwspinlock as available */
++ tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock->id,
++ HWSPINLOCK_UNUSED);
++
++ /* sanity check (this shouldn't happen) */
++ WARN_ON(tmp != hwlock);
++
++ module_put(hwlock->owner);
++
++out:
++ spin_unlock(&hwspinlock_tree_lock);
++ return ret;
++}
++EXPORT_SYMBOL_GPL(hwspin_lock_free);
++
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("Hardware spinlock interface");
++MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");
+diff --git a/drivers/hwspinlock/hwspinlock_internal.h b/drivers/hwspinlock/hwspinlock_internal.h
+new file mode 100644
+index 0000000..69935e6
+--- /dev/null
++++ b/drivers/hwspinlock/hwspinlock_internal.h
+@@ -0,0 +1,61 @@
++/*
++ * Hardware spinlocks internal header
++ *
++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Contact: Ohad Ben-Cohen <ohad@wizery.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __HWSPINLOCK_HWSPINLOCK_H
++#define __HWSPINLOCK_HWSPINLOCK_H
++
++#include <linux/spinlock.h>
++#include <linux/device.h>
++
++/**
++ * struct hwspinlock_ops - platform-specific hwspinlock handlers
++ *
++ * @trylock: make a single attempt to take the lock. returns 0 on
++ * failure and true on success. may _not_ sleep.
++ * @unlock: release the lock. always succeed. may _not_ sleep.
++ * @relax: optional, platform-specific relax handler, called by hwspinlock
++ * core while spinning on a lock, between two successive
++ * invocations of @trylock. may _not_ sleep.
++ */
++struct hwspinlock_ops {
++ int (*trylock)(struct hwspinlock *lock);
++ void (*unlock)(struct hwspinlock *lock);
++ void (*relax)(struct hwspinlock *lock);
++};
++
++/**
++ * struct hwspinlock - this struct represents a single hwspinlock instance
++ *
++ * @dev: underlying device, will be used to invoke runtime PM api
++ * @ops: platform-specific hwspinlock handlers
++ * @id: a global, unique, system-wide, index of the lock.
++ * @lock: initialized and used by hwspinlock core
++ * @owner: underlying implementation module, used to maintain module ref count
++ *
++ * Note: currently simplicity was opted for, but later we can squeeze some
++ * memory bytes by grouping the dev, ops and owner members in a single
++ * per-platform struct, and have all hwspinlocks point at it.
++ */
++struct hwspinlock {
++ struct device *dev;
++ const struct hwspinlock_ops *ops;
++ int id;
++ spinlock_t lock;
++ struct module *owner;
++};
++
++#endif /* __HWSPINLOCK_HWSPINLOCK_H */
+diff --git a/include/linux/hwspinlock.h b/include/linux/hwspinlock.h
+new file mode 100644
+index 0000000..8390efc
+--- /dev/null
++++ b/include/linux/hwspinlock.h
+@@ -0,0 +1,292 @@
++/*
++ * Hardware spinlock public header
++ *
++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Contact: Ohad Ben-Cohen <ohad@wizery.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef __LINUX_HWSPINLOCK_H
++#define __LINUX_HWSPINLOCK_H
++
++#include <linux/err.h>
++#include <linux/sched.h>
++
++/* hwspinlock mode argument */
++#define HWLOCK_IRQSTATE 0x01 /* Disable interrupts, save state */
++#define HWLOCK_IRQ 0x02 /* Disable interrupts, don't save state */
++
++struct hwspinlock;
++
++#if defined(CONFIG_HWSPINLOCK) || defined(CONFIG_HWSPINLOCK_MODULE)
++
++int hwspin_lock_register(struct hwspinlock *lock);
++struct hwspinlock *hwspin_lock_unregister(unsigned int id);
++struct hwspinlock *hwspin_lock_request(void);
++struct hwspinlock *hwspin_lock_request_specific(unsigned int id);
++int hwspin_lock_free(struct hwspinlock *hwlock);
++int hwspin_lock_get_id(struct hwspinlock *hwlock);
++int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int,
++ unsigned long *);
++int __hwspin_trylock(struct hwspinlock *, int, unsigned long *);
++void __hwspin_unlock(struct hwspinlock *, int, unsigned long *);
++
++#else /* !CONFIG_HWSPINLOCK */
++
++/*
++ * We don't want these functions to fail if CONFIG_HWSPINLOCK is not
++ * enabled. We prefer to silently succeed in this case, and let the
++ * code path get compiled away. This way, if CONFIG_HWSPINLOCK is not
++ * required on a given setup, users will still work.
++ *
++ * The only exception is hwspin_lock_register/hwspin_lock_unregister, with which
++ * we _do_ want users to fail (no point in registering hwspinlock instances if
++ * the framework is not available).
++ *
++ * Note: ERR_PTR(-ENODEV) will still be considered a success for NULL-checking
++ * users. Others, which care, can still check this with IS_ERR.
++ */
++static inline struct hwspinlock *hwspin_lock_request(void)
++{
++ return ERR_PTR(-ENODEV);
++}
++
++static inline struct hwspinlock *hwspin_lock_request_specific(unsigned int id)
++{
++ return ERR_PTR(-ENODEV);
++}
++
++static inline int hwspin_lock_free(struct hwspinlock *hwlock)
++{
++ return 0;
++}
++
++static inline
++int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to,
++ int mode, unsigned long *flags)
++{
++ return 0;
++}
++
++static inline
++int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags)
++{
++ return 0;
++}
++
++static inline
++void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags)
++{
++ return 0;
++}
++
++static inline int hwspin_lock_get_id(struct hwspinlock *hwlock)
++{
++ return 0;
++}
++
++static inline int hwspin_lock_register(struct hwspinlock *hwlock)
++{
++ return -ENODEV;
++}
++
++static inline struct hwspinlock *hwspin_lock_unregister(unsigned int id)
++{
++ return NULL;
++}
++
++#endif /* !CONFIG_HWSPINLOCK */
++
++/**
++ * hwspin_trylock_irqsave() - try to lock an hwspinlock, disable interrupts
++ * @hwlock: an hwspinlock which we want to trylock
++ * @flags: a pointer to where the caller's interrupt state will be saved at
++ *
++ * This function attempts to lock the underlying hwspinlock, and will
++ * immediately fail if the hwspinlock is already locked.
++ *
++ * Upon a successful return from this function, preemption and local
++ * interrupts are disabled (previous interrupts state is saved at @flags),
++ * so the caller must not sleep, and is advised to release the hwspinlock
++ * as soon as possible.
++ *
++ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if
++ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid.
++ */
++static inline
++int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags)
++{
++ return __hwspin_trylock(hwlock, HWLOCK_IRQSTATE, flags);
++}
++
++/**
++ * hwspin_trylock_irq() - try to lock an hwspinlock, disable interrupts
++ * @hwlock: an hwspinlock which we want to trylock
++ *
++ * This function attempts to lock the underlying hwspinlock, and will
++ * immediately fail if the hwspinlock is already locked.
++ *
++ * Upon a successful return from this function, preemption and local
++ * interrupts are disabled, so the caller must not sleep, and is advised
++ * to release the hwspinlock as soon as possible.
++ *
++ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if
++ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid.
++ */
++static inline int hwspin_trylock_irq(struct hwspinlock *hwlock)
++{
++ return __hwspin_trylock(hwlock, HWLOCK_IRQ, NULL);
++}
++
++/**
++ * hwspin_trylock() - attempt to lock a specific hwspinlock
++ * @hwlock: an hwspinlock which we want to trylock
++ *
++ * This function attempts to lock an hwspinlock, and will immediately fail
++ * if the hwspinlock is already taken.
++ *
++ * Upon a successful return from this function, preemption is disabled,
++ * so the caller must not sleep, and is advised to release the hwspinlock
++ * as soon as possible. This is required in order to minimize remote cores
++ * polling on the hardware interconnect.
++ *
++ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if
++ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid.
++ */
++static inline int hwspin_trylock(struct hwspinlock *hwlock)
++{
++ return __hwspin_trylock(hwlock, 0, NULL);
++}
++
++/**
++ * hwspin_lock_timeout_irqsave() - lock hwspinlock, with timeout, disable irqs
++ * @hwlock: the hwspinlock to be locked
++ * @to: timeout value in msecs
++ * @flags: a pointer to where the caller's interrupt state will be saved at
++ *
++ * This function locks the underlying @hwlock. If the @hwlock
++ * is already taken, the function will busy loop waiting for it to
++ * be released, but give up when @timeout msecs have elapsed.
++ *
++ * Upon a successful return from this function, preemption and local interrupts
++ * are disabled (plus previous interrupt state is saved), so the caller must
++ * not sleep, and is advised to release the hwspinlock as soon as possible.
++ *
++ * Returns 0 when the @hwlock was successfully taken, and an appropriate
++ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still
++ * busy after @timeout msecs). The function will never sleep.
++ */
++static inline int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock,
++ unsigned int to, unsigned long *flags)
++{
++ return __hwspin_lock_timeout(hwlock, to, HWLOCK_IRQSTATE, flags);
++}
++
++/**
++ * hwspin_lock_timeout_irq() - lock hwspinlock, with timeout, disable irqs
++ * @hwlock: the hwspinlock to be locked
++ * @to: timeout value in msecs
++ *
++ * This function locks the underlying @hwlock. If the @hwlock
++ * is already taken, the function will busy loop waiting for it to
++ * be released, but give up when @timeout msecs have elapsed.
++ *
++ * Upon a successful return from this function, preemption and local interrupts
++ * are disabled so the caller must not sleep, and is advised to release the
++ * hwspinlock as soon as possible.
++ *
++ * Returns 0 when the @hwlock was successfully taken, and an appropriate
++ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still
++ * busy after @timeout msecs). The function will never sleep.
++ */
++static inline
++int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int to)
++{
++ return __hwspin_lock_timeout(hwlock, to, HWLOCK_IRQ, NULL);
++}
++
++/**
++ * hwspin_lock_timeout() - lock an hwspinlock with timeout limit
++ * @hwlock: the hwspinlock to be locked
++ * @to: timeout value in msecs
++ *
++ * This function locks the underlying @hwlock. If the @hwlock
++ * is already taken, the function will busy loop waiting for it to
++ * be released, but give up when @timeout msecs have elapsed.
++ *
++ * Upon a successful return from this function, preemption is disabled
++ * so the caller must not sleep, and is advised to release the hwspinlock
++ * as soon as possible.
++ * This is required in order to minimize remote cores polling on the
++ * hardware interconnect.
++ *
++ * Returns 0 when the @hwlock was successfully taken, and an appropriate
++ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still
++ * busy after @timeout msecs). The function will never sleep.
++ */
++static inline
++int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to)
++{
++ return __hwspin_lock_timeout(hwlock, to, 0, NULL);
++}
++
++/**
++ * hwspin_unlock_irqrestore() - unlock hwspinlock, restore irq state
++ * @hwlock: a previously-acquired hwspinlock which we want to unlock
++ * @flags: previous caller's interrupt state to restore
++ *
++ * This function will unlock a specific hwspinlock, enable preemption and
++ * restore the previous state of the local interrupts. It should be used
++ * to undo, e.g., hwspin_trylock_irqsave().
++ *
++ * @hwlock must be already locked before calling this function: it is a bug
++ * to call unlock on a @hwlock that is already unlocked.
++ */
++static inline void hwspin_unlock_irqrestore(struct hwspinlock *hwlock,
++ unsigned long *flags)
++{
++ __hwspin_unlock(hwlock, HWLOCK_IRQSTATE, flags);
++}
++
++/**
++ * hwspin_unlock_irq() - unlock hwspinlock, enable interrupts
++ * @hwlock: a previously-acquired hwspinlock which we want to unlock
++ *
++ * This function will unlock a specific hwspinlock, enable preemption and
++ * enable local interrupts. Should be used to undo hwspin_lock_irq().
++ *
++ * @hwlock must be already locked (e.g. by hwspin_trylock_irq()) before
++ * calling this function: it is a bug to call unlock on a @hwlock that is
++ * already unlocked.
++ */
++static inline void hwspin_unlock_irq(struct hwspinlock *hwlock)
++{
++ __hwspin_unlock(hwlock, HWLOCK_IRQ, NULL);
++}
++
++/**
++ * hwspin_unlock() - unlock hwspinlock
++ * @hwlock: a previously-acquired hwspinlock which we want to unlock
++ *
++ * This function will unlock a specific hwspinlock and enable preemption
++ * back.
++ *
++ * @hwlock must be already locked (e.g. by hwspin_trylock()) before calling
++ * this function: it is a bug to call unlock on a @hwlock that is already
++ * unlocked.
++ */
++static inline void hwspin_unlock(struct hwspinlock *hwlock)
++{
++ __hwspin_unlock(hwlock, 0, NULL);
++}
++
++#endif /* __LINUX_HWSPINLOCK_H */
+--
+1.7.1
+
diff --git a/patches/for_next/0046-drivers-hwspinlock-add-OMAP-implementation.patch b/patches/for_next/0046-drivers-hwspinlock-add-OMAP-implementation.patch
new file mode 100644
index 0000000000000000000000000000000000000000..dc37e6f6f2b64627386509eb5e83d4a4898a9ac1
--- /dev/null
+++ b/patches/for_next/0046-drivers-hwspinlock-add-OMAP-implementation.patch
@@ -0,0 +1,296 @@
+From 16c9c830f6dbc67550a73ffb34820aec89b1d2f4 Mon Sep 17 00:00:00 2001
+From: Simon Que <sque@ti.com>
+Date: Thu, 17 Feb 2011 09:52:03 -0800
+Subject: [PATCH 046/254] drivers: hwspinlock: add OMAP implementation
+
+Add hwspinlock support for the OMAP4 Hardware Spinlock device.
+
+The Hardware Spinlock device on OMAP4 provides hardware assistance
+for synchronization between the multiple processors in the system
+(dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP).
+
+[ohad@wizery.com: adapt to hwspinlock framework, tidy up]
+Signed-off-by: Simon Que <sque@ti.com>
+Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
+Signed-off-by: Krishnamoorthy, Balaji T <balajitk@ti.com>
+Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Grant Likely <grant.likely@secretlab.ca>
+Cc: Arnd Bergmann <arnd@arndb.de>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Russell King <linux@arm.linux.org.uk>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ drivers/hwspinlock/Kconfig | 9 ++
+ drivers/hwspinlock/Makefile | 1 +
+ drivers/hwspinlock/omap_hwspinlock.c | 231 ++++++++++++++++++++++++++++++++++
+ 3 files changed, 241 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/hwspinlock/omap_hwspinlock.c
+
+diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
+index 9dd8db4..eb4af28 100644
+--- a/drivers/hwspinlock/Kconfig
++++ b/drivers/hwspinlock/Kconfig
+@@ -11,3 +11,12 @@ config HWSPINLOCK
+ coprocessors).
+
+ If unsure, say N.
++
++config HWSPINLOCK_OMAP
++ tristate "OMAP Hardware Spinlock device"
++ depends on HWSPINLOCK && ARCH_OMAP4
++ help
++ Say y here to support the OMAP Hardware Spinlock device (firstly
++ introduced in OMAP4).
++
++ If unsure, say N.
+diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile
+index b9d2b9f..5729a3f 100644
+--- a/drivers/hwspinlock/Makefile
++++ b/drivers/hwspinlock/Makefile
+@@ -3,3 +3,4 @@
+ #
+
+ obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o
++obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o
+diff --git a/drivers/hwspinlock/omap_hwspinlock.c b/drivers/hwspinlock/omap_hwspinlock.c
+new file mode 100644
+index 0000000..a8f0273
+--- /dev/null
++++ b/drivers/hwspinlock/omap_hwspinlock.c
+@@ -0,0 +1,231 @@
++/*
++ * OMAP hardware spinlock driver
++ *
++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Contact: Simon Que <sque@ti.com>
++ * Hari Kanigeri <h-kanigeri2@ti.com>
++ * Ohad Ben-Cohen <ohad@wizery.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/pm_runtime.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/hwspinlock.h>
++#include <linux/platform_device.h>
++
++#include "hwspinlock_internal.h"
++
++/* Spinlock register offsets */
++#define SYSSTATUS_OFFSET 0x0014
++#define LOCK_BASE_OFFSET 0x0800
++
++#define SPINLOCK_NUMLOCKS_BIT_OFFSET (24)
++
++/* Possible values of SPINLOCK_LOCK_REG */
++#define SPINLOCK_NOTTAKEN (0) /* free */
++#define SPINLOCK_TAKEN (1) /* locked */
++
++#define to_omap_hwspinlock(lock) \
++ container_of(lock, struct omap_hwspinlock, lock)
++
++struct omap_hwspinlock {
++ struct hwspinlock lock;
++ void __iomem *addr;
++};
++
++struct omap_hwspinlock_state {
++ int num_locks; /* Total number of locks in system */
++ void __iomem *io_base; /* Mapped base address */
++};
++
++static int omap_hwspinlock_trylock(struct hwspinlock *lock)
++{
++ struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock);
++
++ /* attempt to acquire the lock by reading its value */
++ return (SPINLOCK_NOTTAKEN == readl(omap_lock->addr));
++}
++
++static void omap_hwspinlock_unlock(struct hwspinlock *lock)
++{
++ struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock);
++
++ /* release the lock by writing 0 to it */
++ writel(SPINLOCK_NOTTAKEN, omap_lock->addr);
++}
++
++/*
++ * relax the OMAP interconnect while spinning on it.
++ *
++ * The specs recommended that the retry delay time will be
++ * just over half of the time that a requester would be
++ * expected to hold the lock.
++ *
++ * The number below is taken from an hardware specs example,
++ * obviously it is somewhat arbitrary.
++ */
++static void omap_hwspinlock_relax(struct hwspinlock *lock)
++{
++ ndelay(50);
++}
++
++static const struct hwspinlock_ops omap_hwspinlock_ops = {
++ .trylock = omap_hwspinlock_trylock,
++ .unlock = omap_hwspinlock_unlock,
++ .relax = omap_hwspinlock_relax,
++};
++
++static int __devinit omap_hwspinlock_probe(struct platform_device *pdev)
++{
++ struct omap_hwspinlock *omap_lock;
++ struct omap_hwspinlock_state *state;
++ struct hwspinlock *lock;
++ struct resource *res;
++ void __iomem *io_base;
++ int i, ret;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENODEV;
++
++ state = kzalloc(sizeof(*state), GFP_KERNEL);
++ if (!state)
++ return -ENOMEM;
++
++ io_base = ioremap(res->start, resource_size(res));
++ if (!io_base) {
++ ret = -ENOMEM;
++ goto free_state;
++ }
++
++ /* Determine number of locks */
++ i = readl(io_base + SYSSTATUS_OFFSET);
++ i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET;
++
++ /* one of the four lsb's must be set, and nothing else */
++ if (hweight_long(i & 0xf) != 1 || i > 8) {
++ ret = -EINVAL;
++ goto iounmap_base;
++ }
++
++ state->num_locks = i * 32;
++ state->io_base = io_base;
++
++ platform_set_drvdata(pdev, state);
++
++ /*
++ * runtime PM will make sure the clock of this module is
++ * enabled iff at least one lock is requested
++ */
++ pm_runtime_enable(&pdev->dev);
++
++ for (i = 0; i < state->num_locks; i++) {
++ omap_lock = kzalloc(sizeof(*omap_lock), GFP_KERNEL);
++ if (!omap_lock) {
++ ret = -ENOMEM;
++ goto free_locks;
++ }
++
++ omap_lock->lock.dev = &pdev->dev;
++ omap_lock->lock.owner = THIS_MODULE;
++ omap_lock->lock.id = i;
++ omap_lock->lock.ops = &omap_hwspinlock_ops;
++ omap_lock->addr = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
++
++ ret = hwspin_lock_register(&omap_lock->lock);
++ if (ret) {
++ kfree(omap_lock);
++ goto free_locks;
++ }
++ }
++
++ return 0;
++
++free_locks:
++ while (--i >= 0) {
++ lock = hwspin_lock_unregister(i);
++ /* this should't happen, but let's give our best effort */
++ if (!lock) {
++ dev_err(&pdev->dev, "%s: cleanups failed\n", __func__);
++ continue;
++ }
++ omap_lock = to_omap_hwspinlock(lock);
++ kfree(omap_lock);
++ }
++ pm_runtime_disable(&pdev->dev);
++iounmap_base:
++ iounmap(io_base);
++free_state:
++ kfree(state);
++ return ret;
++}
++
++static int omap_hwspinlock_remove(struct platform_device *pdev)
++{
++ struct omap_hwspinlock_state *state = platform_get_drvdata(pdev);
++ struct hwspinlock *lock;
++ struct omap_hwspinlock *omap_lock;
++ int i;
++
++ for (i = 0; i < state->num_locks; i++) {
++ lock = hwspin_lock_unregister(i);
++ /* this shouldn't happen at this point. if it does, at least
++ * don't continue with the remove */
++ if (!lock) {
++ dev_err(&pdev->dev, "%s: failed on %d\n", __func__, i);
++ return -EBUSY;
++ }
++
++ omap_lock = to_omap_hwspinlock(lock);
++ kfree(omap_lock);
++ }
++
++ pm_runtime_disable(&pdev->dev);
++ iounmap(state->io_base);
++ kfree(state);
++
++ return 0;
++}
++
++static struct platform_driver omap_hwspinlock_driver = {
++ .probe = omap_hwspinlock_probe,
++ .remove = omap_hwspinlock_remove,
++ .driver = {
++ .name = "omap_hwspinlock",
++ },
++};
++
++static int __init omap_hwspinlock_init(void)
++{
++ return platform_driver_register(&omap_hwspinlock_driver);
++}
++/* board init code might need to reserve hwspinlocks for predefined purposes */
++postcore_initcall(omap_hwspinlock_init);
++
++static void __exit omap_hwspinlock_exit(void)
++{
++ platform_driver_unregister(&omap_hwspinlock_driver);
++}
++module_exit(omap_hwspinlock_exit);
++
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("Hardware spinlock driver for OMAP");
++MODULE_AUTHOR("Simon Que <sque@ti.com>");
++MODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>");
++MODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>");
+--
+1.7.1
+
diff --git a/patches/for_next/0047-omap-add-hwspinlock-device.patch b/patches/for_next/0047-omap-add-hwspinlock-device.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a3a6b93c987cd64defb35385af61850d047d7840
--- /dev/null
+++ b/patches/for_next/0047-omap-add-hwspinlock-device.patch
@@ -0,0 +1,105 @@
+From d95ed280cd867daf03af25dc7c6d8706699cb78e Mon Sep 17 00:00:00 2001
+From: Simon Que <sque@ti.com>
+Date: Thu, 17 Feb 2011 09:52:03 -0800
+Subject: [PATCH 047/254] omap: add hwspinlock device
+
+Build and register an hwspinlock platform device.
+
+Although only OMAP4 supports the hardware spinlock module (for now),
+it is still safe to run this initcall on all omaps, because hwmod lookup
+will simply fail on hwspinlock-less platforms.
+
+Signed-off-by: Simon Que <sque@ti.com>
+Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
+Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/Makefile | 1 +
+ arch/arm/mach-omap2/hwspinlock.c | 63 ++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 64 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/hwspinlock.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 4919e09..ee72a97 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -244,3 +244,4 @@ obj-y += $(smc91x-m) $(smc91x-y)
+
+ smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
+ obj-y += $(smsc911x-m) $(smsc911x-y)
++obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
+diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
+new file mode 100644
+index 0000000..06d4a80
+--- /dev/null
++++ b/arch/arm/mach-omap2/hwspinlock.c
+@@ -0,0 +1,63 @@
++/*
++ * OMAP hardware spinlock device initialization
++ *
++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Contact: Simon Que <sque@ti.com>
++ * Hari Kanigeri <h-kanigeri2@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/err.h>
++
++#include <plat/omap_hwmod.h>
++#include <plat/omap_device.h>
++
++struct omap_device_pm_latency omap_spinlock_latency[] = {
++ {
++ .deactivate_func = omap_device_idle_hwmods,
++ .activate_func = omap_device_enable_hwmods,
++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
++ }
++};
++
++int __init hwspinlocks_init(void)
++{
++ int retval = 0;
++ struct omap_hwmod *oh;
++ struct omap_device *od;
++ const char *oh_name = "spinlock";
++ const char *dev_name = "omap_hwspinlock";
++
++ /*
++ * Hwmod lookup will fail in case our platform doesn't support the
++ * hardware spinlock module, so it is safe to run this initcall
++ * on all omaps
++ */
++ oh = omap_hwmod_lookup(oh_name);
++ if (oh == NULL)
++ return -EINVAL;
++
++ od = omap_device_build(dev_name, 0, oh, NULL, 0,
++ omap_spinlock_latency,
++ ARRAY_SIZE(omap_spinlock_latency), false);
++ if (IS_ERR(od)) {
++ pr_err("Can't build omap_device for %s:%s\n", dev_name,
++ oh_name);
++ retval = PTR_ERR(od);
++ }
++
++ return retval;
++}
++/* early board code might need to reserve specific hwspinlock instances */
++postcore_initcall(hwspinlocks_init);
+--
+1.7.1
+
diff --git a/patches/for_next/0048-OMAP2420-hwmod-data-Add-McSPI.patch b/patches/for_next/0048-OMAP2420-hwmod-data-Add-McSPI.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b5e7995def1317b2cf2b6c34bb967b482e1797f0
--- /dev/null
+++ b/patches/for_next/0048-OMAP2420-hwmod-data-Add-McSPI.patch
@@ -0,0 +1,242 @@
+From 6f86dcca177be2091406baa20232fad6fca9e890 Mon Sep 17 00:00:00 2001
+From: Charulatha V <charu@ti.com>
+Date: Thu, 17 Feb 2011 09:53:09 -0800
+Subject: [PATCH 048/254] OMAP2420: hwmod data: Add McSPI
+
+Update the omap2420 hwmod data with the McSPI info.
+Add a device attribute structure which will be used
+for passing number of chipselects from hwmod data.
+Add revision macros to be passed from rev field from
+hwmod.
+
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 156 ++++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/mcspi.h | 8 ++
+ 2 files changed, 164 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index b85c630..7fffd34 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -18,6 +18,7 @@
+ #include <plat/serial.h>
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
++#include <plat/mcspi.h>
+
+ #include "omap_hwmod_common_data.h"
+
+@@ -44,6 +45,8 @@ static struct omap_hwmod omap2420_gpio2_hwmod;
+ static struct omap_hwmod omap2420_gpio3_hwmod;
+ static struct omap_hwmod omap2420_gpio4_hwmod;
+ static struct omap_hwmod omap2420_dma_system_hwmod;
++static struct omap_hwmod omap2420_mcspi1_hwmod;
++static struct omap_hwmod omap2420_mcspi2_hwmod;
+
+ /* L3 -> L4_CORE interface */
+ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
+@@ -88,6 +91,42 @@ static struct omap_hwmod omap2420_uart3_hwmod;
+ static struct omap_hwmod omap2420_i2c1_hwmod;
+ static struct omap_hwmod omap2420_i2c2_hwmod;
+
++/* l4 core -> mcspi1 interface */
++static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
++ {
++ .pa_start = 0x48098000,
++ .pa_end = 0x480980ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_mcspi1_hwmod,
++ .clk = "mcspi1_ick",
++ .addr = omap2420_mcspi1_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* l4 core -> mcspi2 interface */
++static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
++ {
++ .pa_start = 0x4809a000,
++ .pa_end = 0x4809a0ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_mcspi2_hwmod,
++ .clk = "mcspi2_ick",
++ .addr = omap2420_mcspi2_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
+ /* L4_CORE -> L4_WKUP interface */
+ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
+ .master = &omap2420_l4_core_hwmod,
+@@ -864,6 +903,119 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
++/*
++ * 'mcspi' class
++ * multichannel serial port interface (mcspi) / master/slave synchronous serial
++ * bus
++ */
++
++static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap2420_mcspi_class = {
++ .name = "mcspi",
++ .sysc = &omap2420_mcspi_sysc,
++ .rev = OMAP2_MCSPI_REV,
++};
++
++/* mcspi1 */
++static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
++ { .irq = 65 },
++};
++
++static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
++ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
++ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
++ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
++ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
++ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
++ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
++ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
++};
++
++static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
++ &omap2420_l4_core__mcspi1,
++};
++
++static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
++ .num_chipselect = 4,
++};
++
++static struct omap_hwmod omap2420_mcspi1_hwmod = {
++ .name = "mcspi1_hwmod",
++ .mpu_irqs = omap2420_mcspi1_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
++ .sdma_reqs = omap2420_mcspi1_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
++ .main_clk = "mcspi1_fck",
++ .prcm = {
++ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
++ },
++ },
++ .slaves = omap2420_mcspi1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
++ .class = &omap2420_mcspi_class,
++ .dev_attr = &omap_mcspi1_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
++};
++
++/* mcspi2 */
++static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
++ { .irq = 66 },
++};
++
++static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
++ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
++ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
++ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
++};
++
++static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
++ &omap2420_l4_core__mcspi2,
++};
++
++static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
++ .num_chipselect = 2,
++};
++
++static struct omap_hwmod omap2420_mcspi2_hwmod = {
++ .name = "mcspi2_hwmod",
++ .mpu_irqs = omap2420_mcspi2_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
++ .sdma_reqs = omap2420_mcspi2_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
++ .main_clk = "mcspi2_fck",
++ .prcm = {
++ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
++ },
++ },
++ .slaves = omap2420_mcspi2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
++ .class = &omap2420_mcspi_class,
++ .dev_attr = &omap_mcspi2_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
++};
++
+ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+ &omap2420_l3_main_hwmod,
+ &omap2420_l4_core_hwmod,
+@@ -885,6 +1037,10 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+
+ /* dma_system class*/
+ &omap2420_dma_system_hwmod,
++
++ /* mcspi class */
++ &omap2420_mcspi1_hwmod,
++ &omap2420_mcspi2_hwmod,
+ NULL,
+ };
+
+diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
+index 1254e49..560e266 100644
+--- a/arch/arm/plat-omap/include/plat/mcspi.h
++++ b/arch/arm/plat-omap/include/plat/mcspi.h
+@@ -1,10 +1,18 @@
+ #ifndef _OMAP2_MCSPI_H
+ #define _OMAP2_MCSPI_H
+
++#define OMAP2_MCSPI_REV 0
++#define OMAP3_MCSPI_REV 1
++#define OMAP4_MCSPI_REV 2
++
+ struct omap2_mcspi_platform_config {
+ unsigned short num_cs;
+ };
+
++struct omap2_mcspi_dev_attr {
++ unsigned short num_chipselect;
++};
++
+ struct omap2_mcspi_device_config {
+ unsigned turbo_mode:1;
+
+--
+1.7.1
+
diff --git a/patches/for_next/0049-OMAP2430-hwmod-data-Add-McSPI.patch b/patches/for_next/0049-OMAP2430-hwmod-data-Add-McSPI.patch
new file mode 100644
index 0000000000000000000000000000000000000000..92b9c8581a02a63a8a554515ce217dc0c924e23f
--- /dev/null
+++ b/patches/for_next/0049-OMAP2430-hwmod-data-Add-McSPI.patch
@@ -0,0 +1,313 @@
+From 9a7295af18cd2c39d6947329b8b3d77d553f5638 Mon Sep 17 00:00:00 2001
+From: Charulatha V <charu@ti.com>
+Date: Thu, 17 Feb 2011 09:53:10 -0800
+Subject: [PATCH 049/254] OMAP2430: hwmod data: Add McSPI
+
+Update the 2430 hwmod data file with McSPI info.
+
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 240 +++++++++++++++++++++++-----
+ 1 files changed, 200 insertions(+), 40 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 76bbf8a..414b397 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -18,6 +18,7 @@
+ #include <plat/serial.h>
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
++#include <plat/mcspi.h>
+
+ #include "omap_hwmod_common_data.h"
+
+@@ -45,6 +46,9 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
+ static struct omap_hwmod omap2430_gpio4_hwmod;
+ static struct omap_hwmod omap2430_gpio5_hwmod;
+ static struct omap_hwmod omap2430_dma_system_hwmod;
++static struct omap_hwmod omap2430_mcspi1_hwmod;
++static struct omap_hwmod omap2430_mcspi2_hwmod;
++static struct omap_hwmod omap2430_mcspi3_hwmod;
+
+ /* L3 -> L4_CORE interface */
+ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
+@@ -262,6 +266,60 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
+ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
+ };
+
++/* l4 core -> mcspi1 interface */
++static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
++ {
++ .pa_start = 0x48098000,
++ .pa_end = 0x480980ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mcspi1_hwmod,
++ .clk = "mcspi1_ick",
++ .addr = omap2430_mcspi1_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* l4 core -> mcspi2 interface */
++static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
++ {
++ .pa_start = 0x4809a000,
++ .pa_end = 0x4809a0ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mcspi2_hwmod,
++ .clk = "mcspi2_ick",
++ .addr = omap2430_mcspi2_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* l4 core -> mcspi3 interface */
++static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
++ {
++ .pa_start = 0x480b8000,
++ .pa_end = 0x480b80ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mcspi3_hwmod,
++ .clk = "mcspi3_ick",
++ .addr = omap2430_mcspi3_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
+ /* L4 WKUP */
+ static struct omap_hwmod omap2430_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+@@ -959,59 +1017,159 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
+ };
+
+ /*
+- * usbhsotg
++ * 'mcspi' class
++ * multichannel serial port interface (mcspi) / master/slave synchronous serial
++ * bus
+ */
+-static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
+- .rev_offs = 0x0400,
+- .sysc_offs = 0x0404,
+- .syss_offs = 0x0408,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
++
++static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+
+-static struct omap_hwmod_class usbotg_class = {
+- .name = "usbotg",
+- .sysc = &omap2430_usbhsotg_sysc,
++static struct omap_hwmod_class omap2430_mcspi_class = {
++ .name = "mcspi",
++ .sysc = &omap2430_mcspi_sysc,
++ .rev = OMAP2_MCSPI_REV,
+ };
+
+-/* usb_otg_hs */
+-static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
++/* mcspi1 */
++static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
++ { .irq = 65 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
++ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
++ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
++ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
++ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
++ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
++ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
++ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
++};
++
++static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
++ &omap2430_l4_core__mcspi1,
++};
+
+- { .name = "mc", .irq = 92 },
+- { .name = "dma", .irq = 93 },
++static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
++ .num_chipselect = 4,
+ };
+
+-static struct omap_hwmod omap2430_usbhsotg_hwmod = {
+- .name = "usb_otg_hs",
+- .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
+- .main_clk = "usbhs_ick",
++static struct omap_hwmod omap2430_mcspi1_hwmod = {
++ .name = "mcspi1_hwmod",
++ .mpu_irqs = omap2430_mcspi1_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
++ .sdma_reqs = omap2430_mcspi1_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
++ .main_clk = "mcspi1_fck",
+ .prcm = {
+ .omap2 = {
++ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+- .module_bit = OMAP2430_EN_USBHS_MASK,
++ .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
++ },
++ },
++ .slaves = omap2430_mcspi1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
++ .class = &omap2430_mcspi_class,
++ .dev_attr = &omap_mcspi1_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
++/* mcspi2 */
++static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
++ { .irq = 66 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
++ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
++ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
++ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
++};
++
++static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
++ &omap2430_l4_core__mcspi2,
++};
++
++static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
++ .num_chipselect = 2,
++};
++
++static struct omap_hwmod omap2430_mcspi2_hwmod = {
++ .name = "mcspi2_hwmod",
++ .mpu_irqs = omap2430_mcspi2_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
++ .sdma_reqs = omap2430_mcspi2_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
++ .main_clk = "mcspi2_fck",
++ .prcm = {
++ .omap2 = {
+ .module_offs = CORE_MOD,
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+ .idlest_reg_id = 1,
+- .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
++ .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+ },
+ },
+- .masters = omap2430_usbhsotg_masters,
+- .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
+- .slaves = omap2430_usbhsotg_slaves,
+- .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
+- .class = &usbotg_class,
+- /*
+- * Erratum ID: i479 idle_req / idle_ack mechanism potentially
+- * broken when autoidle is enabled
+- * workaround is to disable the autoidle bit at module level.
+- */
+- .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+- | HWMOD_SWSUP_MSTANDBY,
+- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++ .slaves = omap2430_mcspi2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
++ .class = &omap2430_mcspi_class,
++ .dev_attr = &omap_mcspi2_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
++/* mcspi3 */
++static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
++ { .irq = 91 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
++ { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
++ { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
++ { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
++};
++
++static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
++ &omap2430_l4_core__mcspi3,
++};
++
++static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
++ .num_chipselect = 2,
++};
++
++static struct omap_hwmod omap2430_mcspi3_hwmod = {
++ .name = "mcspi3_hwmod",
++ .mpu_irqs = omap2430_mcspi3_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
++ .sdma_reqs = omap2430_mcspi3_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
++ .main_clk = "mcspi3_fck",
++ .prcm = {
++ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 2,
++ .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
++ .idlest_reg_id = 2,
++ .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
++ },
++ },
++ .slaves = omap2430_mcspi3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
++ .class = &omap2430_mcspi_class,
++ .dev_attr = &omap_mcspi3_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
+ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+@@ -1037,8 +1195,10 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ /* dma_system class*/
+ &omap2430_dma_system_hwmod,
+
+- /* usbotg class*/
+- &omap2430_usbhsotg_hwmod,
++ /* mcspi class */
++ &omap2430_mcspi1_hwmod,
++ &omap2430_mcspi2_hwmod,
++ &omap2430_mcspi3_hwmod,
+ NULL,
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0050-OMAP3-hwmod-data-Add-McSPI.patch b/patches/for_next/0050-OMAP3-hwmod-data-Add-McSPI.patch
new file mode 100644
index 0000000000000000000000000000000000000000..decaf4cb0f2e41ceea59c5918cd791c4570861d6
--- /dev/null
+++ b/patches/for_next/0050-OMAP3-hwmod-data-Add-McSPI.patch
@@ -0,0 +1,393 @@
+From 263c52daff2fc474391851d7ffdc75d47b70171f Mon Sep 17 00:00:00 2001
+From: Charulatha V <charu@ti.com>
+Date: Thu, 17 Feb 2011 09:53:10 -0800
+Subject: [PATCH 050/254] OMAP3: hwmod data: Add McSPI
+
+Update omap3 hwmod data file with McSPI info.
+
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 317 ++++++++++++++++++++++------
+ 1 files changed, 252 insertions(+), 65 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index b4cd8dd..0252cd5 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -22,6 +22,7 @@
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
+ #include <plat/smartreflex.h>
++#include <plat/mcspi.h>
+
+ #include "omap_hwmod_common_data.h"
+
+@@ -56,7 +57,10 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod;
+ static struct omap_hwmod omap3xxx_gpio6_hwmod;
+ static struct omap_hwmod omap34xx_sr1_hwmod;
+ static struct omap_hwmod omap34xx_sr2_hwmod;
+-static struct omap_hwmod am35xx_usbhsotg_hwmod;
++static struct omap_hwmod omap34xx_mcspi1;
++static struct omap_hwmod omap34xx_mcspi2;
++static struct omap_hwmod omap34xx_mcspi3;
++static struct omap_hwmod omap34xx_mcspi4;
+
+
+ static struct omap_hwmod omap3xxx_dma_system_hwmod;
+@@ -1430,89 +1434,273 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ };
+
++/* l4 core -> mcspi1 interface */
++static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
++ {
++ .pa_start = 0x48098000,
++ .pa_end = 0x480980ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap34xx_mcspi1,
++ .clk = "mcspi1_ick",
++ .addr = omap34xx_mcspi1_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* l4 core -> mcspi2 interface */
++static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
++ {
++ .pa_start = 0x4809a000,
++ .pa_end = 0x4809a0ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap34xx_mcspi2,
++ .clk = "mcspi2_ick",
++ .addr = omap34xx_mcspi2_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* l4 core -> mcspi3 interface */
++static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
++ {
++ .pa_start = 0x480b8000,
++ .pa_end = 0x480b80ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap34xx_mcspi3,
++ .clk = "mcspi3_ick",
++ .addr = omap34xx_mcspi3_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* l4 core -> mcspi4 interface */
++static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
++ {
++ .pa_start = 0x480ba000,
++ .pa_end = 0x480ba0ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap34xx_mcspi4,
++ .clk = "mcspi4_ick",
++ .addr = omap34xx_mcspi4_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
+ /*
+- * usbhsotg
++ * 'mcspi' class
++ * multichannel serial port interface (mcspi) / master/slave synchronous serial
++ * bus
+ */
+-static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
+- .rev_offs = 0x0400,
+- .sysc_offs = 0x0404,
+- .syss_offs = 0x0408,
+- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
+- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
+- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+- .sysc_fields = &omap_hwmod_sysc_type1,
++
++static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap34xx_mcspi_class = {
++ .name = "mcspi",
++ .sysc = &omap34xx_mcspi_sysc,
++ .rev = OMAP3_MCSPI_REV,
++};
++
++/* mcspi1 */
++static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
++ { .name = "irq", .irq = 65 },
++};
++
++static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 35 },
++ { .name = "rx0", .dma_req = 36 },
++ { .name = "tx1", .dma_req = 37 },
++ { .name = "rx1", .dma_req = 38 },
++ { .name = "tx2", .dma_req = 39 },
++ { .name = "rx2", .dma_req = 40 },
++ { .name = "tx3", .dma_req = 41 },
++ { .name = "rx3", .dma_req = 42 },
+ };
+
+-static struct omap_hwmod_class usbotg_class = {
+- .name = "usbotg",
+- .sysc = &omap3xxx_usbhsotg_sysc,
++static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
++ &omap34xx_l4_core__mcspi1,
+ };
+
+-/* usb_otg_hs */
+-static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
++static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
++ .num_chipselect = 4,
++};
+
+- { .name = "mc", .irq = 92 },
+- { .name = "dma", .irq = 93 },
++static struct omap_hwmod omap34xx_mcspi1 = {
++ .name = "mcspi1",
++ .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
++ .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
++ .main_clk = "mcspi1_fck",
++ .prcm = {
++ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
++ },
++ },
++ .slaves = omap34xx_mcspi1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
++ .class = &omap34xx_mcspi_class,
++ .dev_attr = &omap_mcspi1_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+
+-static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
+- .name = "usb_otg_hs",
+- .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
+- .main_clk = "hsotgusb_ick",
++/* mcspi2 */
++static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
++ { .name = "irq", .irq = 66 },
++};
++
++static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 43 },
++ { .name = "rx0", .dma_req = 44 },
++ { .name = "tx1", .dma_req = 45 },
++ { .name = "rx1", .dma_req = 46 },
++};
++
++static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
++ &omap34xx_l4_core__mcspi2,
++};
++
++static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
++ .num_chipselect = 2,
++};
++
++static struct omap_hwmod omap34xx_mcspi2 = {
++ .name = "mcspi2",
++ .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
++ .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
++ .main_clk = "mcspi2_fck",
+ .prcm = {
+ .omap2 = {
++ .module_offs = CORE_MOD,
+ .prcm_reg_id = 1,
+- .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
++ .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
++ },
++ },
++ .slaves = omap34xx_mcspi2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
++ .class = &omap34xx_mcspi_class,
++ .dev_attr = &omap_mcspi2_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++/* mcspi3 */
++static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
++ { .name = "irq", .irq = 91 }, /* 91 */
++};
++
++static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 15 },
++ { .name = "rx0", .dma_req = 16 },
++ { .name = "tx1", .dma_req = 23 },
++ { .name = "rx1", .dma_req = 24 },
++};
++
++static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
++ &omap34xx_l4_core__mcspi3,
++};
++
++static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
++ .num_chipselect = 2,
++};
++
++static struct omap_hwmod omap34xx_mcspi3 = {
++ .name = "mcspi3",
++ .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
++ .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
++ .main_clk = "mcspi3_fck",
++ .prcm = {
++ .omap2 = {
+ .module_offs = CORE_MOD,
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
+ .idlest_reg_id = 1,
+- .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
+- .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
++ .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
+ },
+ },
+- .masters = omap3xxx_usbhsotg_masters,
+- .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
+- .slaves = omap3xxx_usbhsotg_slaves,
+- .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
+- .class = &usbotg_class,
+-
+- /*
+- * Erratum ID: i479 idle_req / idle_ack mechanism potentially
+- * broken when autoidle is enabled
+- * workaround is to disable the autoidle bit at module level.
+- */
+- .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
+- | HWMOD_SWSUP_MSTANDBY,
+- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++ .slaves = omap34xx_mcspi3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
++ .class = &omap34xx_mcspi_class,
++ .dev_attr = &omap_mcspi3_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+-/* usb_otg_hs */
+-static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
+
+- { .name = "mc", .irq = 71 },
++/* SPI4 */
++static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
++ { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
+ };
+
+-static struct omap_hwmod_class am35xx_usbotg_class = {
+- .name = "am35xx_usbotg",
+- .sysc = NULL,
++static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
++ { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
++ { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
+ };
+
+-static struct omap_hwmod am35xx_usbhsotg_hwmod = {
+- .name = "am35x_otg_hs",
+- .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
+- .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
+- .main_clk = NULL,
+- .prcm = {
++static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
++ &omap34xx_l4_core__mcspi4,
++};
++
++static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
++ .num_chipselect = 1,
++};
++
++static struct omap_hwmod omap34xx_mcspi4 = {
++ .name = "mcspi4",
++ .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
++ .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
++ .main_clk = "mcspi4_fck",
++ .prcm = {
+ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
+ },
+ },
+- .masters = am35xx_usbhsotg_masters,
+- .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
+- .slaves = am35xx_usbhsotg_slaves,
+- .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
+- .class = &am35xx_usbotg_class,
+- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
++ .slaves = omap34xx_mcspi4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
++ .class = &omap34xx_mcspi_class,
++ .dev_attr = &omap_mcspi4_dev_attr,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+
+ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+@@ -1547,12 +1735,11 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ /* dma_system class*/
+ &omap3xxx_dma_system_hwmod,
+
+- /* usbotg class */
+- &omap3xxx_usbhsotg_hwmod,
+-
+- /* usbotg for am35x */
+- &am35xx_usbhsotg_hwmod,
+-
++ /* mcspi class */
++ &omap34xx_mcspi1,
++ &omap34xx_mcspi2,
++ &omap34xx_mcspi3,
++ &omap34xx_mcspi4,
+ NULL,
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0051-OMAP-devices-Modify-McSPI-device-to-adapt-to-hwmod-f.patch b/patches/for_next/0051-OMAP-devices-Modify-McSPI-device-to-adapt-to-hwmod-f.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5afd546621fa4c8e7af99c55a21ac929d6895331
--- /dev/null
+++ b/patches/for_next/0051-OMAP-devices-Modify-McSPI-device-to-adapt-to-hwmod-f.patch
@@ -0,0 +1,424 @@
+From c2686f8c194ccd088668af9837c96d29bebf25a5 Mon Sep 17 00:00:00 2001
+From: Charulatha V <charu@ti.com>
+Date: Wed, 2 Feb 2011 17:52:14 +0530
+Subject: [PATCH 051/254] OMAP: devices: Modify McSPI device to adapt to hwmod framework
+
+Cleans up all base address definitions for omap_mcspi
+and adapts the device registration and driver to hwmod framework.
+Changes involves:
+1) Removing all base address macro defines.
+2) Using omap-device layer to register device and utilizing data from
+ hwmod data file for base address, dma channel number, Irq_number,
+ device attribute(number of chipselect).
+3) Appending base address with pdata reg_offset for omap4 boards.
+ For omap4 all regs used in driver deviate with reg_offset_macros
+ defined with an value of 0x100. So pass this offset through pdata
+ and append the same to base address retrieved from hwmod data file
+ and we are not mapping *_HL_* regs which are not used in driver.
+
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Reviewed-by: Partha Basak <p-basak2@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/devices.c | 187 +++++++------------------------
+ arch/arm/plat-omap/include/plat/mcspi.h | 3 +
+ drivers/spi/omap2_mcspi.c | 112 +++++--------------
+ 3 files changed, 72 insertions(+), 230 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index e0f0ef9..71f099b 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -15,6 +15,7 @@
+ #include <linux/io.h>
+ #include <linux/clk.h>
+ #include <linux/err.h>
++#include <linux/slab.h>
+
+ #include <mach/hardware.h>
+ #include <mach/irqs.h>
+@@ -279,163 +280,55 @@ static inline void omap_init_audio(void) {}
+
+ #include <plat/mcspi.h>
+
+-#define OMAP2_MCSPI1_BASE 0x48098000
+-#define OMAP2_MCSPI2_BASE 0x4809a000
+-#define OMAP2_MCSPI3_BASE 0x480b8000
+-#define OMAP2_MCSPI4_BASE 0x480ba000
+-
+-#define OMAP4_MCSPI1_BASE 0x48098100
+-#define OMAP4_MCSPI2_BASE 0x4809a100
+-#define OMAP4_MCSPI3_BASE 0x480b8100
+-#define OMAP4_MCSPI4_BASE 0x480ba100
+-
+-static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
+- .num_cs = 4,
+-};
+-
+-static struct resource omap2_mcspi1_resources[] = {
+- {
+- .start = OMAP2_MCSPI1_BASE,
+- .end = OMAP2_MCSPI1_BASE + 0xff,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct platform_device omap2_mcspi1 = {
+- .name = "omap2_mcspi",
+- .id = 1,
+- .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
+- .resource = omap2_mcspi1_resources,
+- .dev = {
+- .platform_data = &omap2_mcspi1_config,
+- },
+-};
+-
+-static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
+- .num_cs = 2,
+-};
+-
+-static struct resource omap2_mcspi2_resources[] = {
+- {
+- .start = OMAP2_MCSPI2_BASE,
+- .end = OMAP2_MCSPI2_BASE + 0xff,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct platform_device omap2_mcspi2 = {
+- .name = "omap2_mcspi",
+- .id = 2,
+- .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
+- .resource = omap2_mcspi2_resources,
+- .dev = {
+- .platform_data = &omap2_mcspi2_config,
+- },
+-};
+-
+-#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+- defined(CONFIG_ARCH_OMAP4)
+-static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
+- .num_cs = 2,
+-};
+-
+-static struct resource omap2_mcspi3_resources[] = {
+- {
+- .start = OMAP2_MCSPI3_BASE,
+- .end = OMAP2_MCSPI3_BASE + 0xff,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct platform_device omap2_mcspi3 = {
+- .name = "omap2_mcspi",
+- .id = 3,
+- .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
+- .resource = omap2_mcspi3_resources,
+- .dev = {
+- .platform_data = &omap2_mcspi3_config,
+- },
+-};
+-#endif
+-
+-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+-static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
+- .num_cs = 1,
+-};
+-
+-static struct resource omap2_mcspi4_resources[] = {
+- {
+- .start = OMAP2_MCSPI4_BASE,
+- .end = OMAP2_MCSPI4_BASE + 0xff,
+- .flags = IORESOURCE_MEM,
+- },
+-};
+-
+-static struct platform_device omap2_mcspi4 = {
+- .name = "omap2_mcspi",
+- .id = 4,
+- .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
+- .resource = omap2_mcspi4_resources,
+- .dev = {
+- .platform_data = &omap2_mcspi4_config,
++struct omap_device_pm_latency omap_mcspi_latency[] = {
++ [0] = {
++ .deactivate_func = omap_device_idle_hwmods,
++ .activate_func = omap_device_enable_hwmods,
++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+ };
+-#endif
+
+-#ifdef CONFIG_ARCH_OMAP4
+-static inline void omap4_mcspi_fixup(void)
++static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
+ {
+- omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
+- omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
+- omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
+- omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
+- omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
+- omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
+- omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
+- omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
+-}
+-#else
+-static inline void omap4_mcspi_fixup(void)
+-{
+-}
+-#endif
++ struct omap_device *od;
++ char *name = "omap2_mcspi";
++ struct omap2_mcspi_platform_config *pdata;
++ static int spi_num;
++ struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
++
++ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
++ if (!pdata) {
++ pr_err("Memory allocation for McSPI device failed\n");
++ return -ENOMEM;
++ }
+
+-#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
+- defined(CONFIG_ARCH_OMAP4)
+-static inline void omap2_mcspi3_init(void)
+-{
+- platform_device_register(&omap2_mcspi3);
+-}
+-#else
+-static inline void omap2_mcspi3_init(void)
+-{
+-}
+-#endif
++ pdata->num_cs = mcspi_attrib->num_chipselect;
++ switch (oh->class->rev) {
++ case OMAP2_MCSPI_REV:
++ case OMAP3_MCSPI_REV:
++ pdata->regs_offset = 0;
++ break;
++ case OMAP4_MCSPI_REV:
++ pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
++ break;
++ default:
++ pr_err("Invalid McSPI Revision value\n");
++ return -EINVAL;
++ }
+
+-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+-static inline void omap2_mcspi4_init(void)
+-{
+- platform_device_register(&omap2_mcspi4);
+-}
+-#else
+-static inline void omap2_mcspi4_init(void)
+-{
++ spi_num++;
++ od = omap_device_build(name, spi_num, oh, pdata,
++ sizeof(*pdata), omap_mcspi_latency,
++ ARRAY_SIZE(omap_mcspi_latency), 0);
++ WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
++ name, oh->name);
++ kfree(pdata);
++ return 0;
+ }
+-#endif
+
+ static void omap_init_mcspi(void)
+ {
+- if (cpu_is_omap44xx())
+- omap4_mcspi_fixup();
+-
+- platform_device_register(&omap2_mcspi1);
+- platform_device_register(&omap2_mcspi2);
+-
+- if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
+- omap2_mcspi3_init();
+-
+- if (cpu_is_omap343x() || cpu_is_omap44xx())
+- omap2_mcspi4_init();
++ omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
+ }
+
+ #else
+diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
+index 560e266..3d51b18 100644
+--- a/arch/arm/plat-omap/include/plat/mcspi.h
++++ b/arch/arm/plat-omap/include/plat/mcspi.h
+@@ -5,8 +5,11 @@
+ #define OMAP3_MCSPI_REV 1
+ #define OMAP4_MCSPI_REV 2
+
++#define OMAP4_MCSPI_REG_OFFSET 0x100
++
+ struct omap2_mcspi_platform_config {
+ unsigned short num_cs;
++ unsigned int regs_offset;
+ };
+
+ struct omap2_mcspi_dev_attr {
+diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
+index f076cc5..f785132 100644
+--- a/drivers/spi/omap2_mcspi.c
++++ b/drivers/spi/omap2_mcspi.c
+@@ -3,7 +3,7 @@
+ *
+ * Copyright (C) 2005, 2006 Nokia Corporation
+ * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
+- * Juha Yrjölä <juha.yrjola@nokia.com>
++ * Juha Yrj�l� <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+@@ -1087,91 +1087,14 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
+ return 0;
+ }
+
+-static u8 __initdata spi1_rxdma_id [] = {
+- OMAP24XX_DMA_SPI1_RX0,
+- OMAP24XX_DMA_SPI1_RX1,
+- OMAP24XX_DMA_SPI1_RX2,
+- OMAP24XX_DMA_SPI1_RX3,
+-};
+-
+-static u8 __initdata spi1_txdma_id [] = {
+- OMAP24XX_DMA_SPI1_TX0,
+- OMAP24XX_DMA_SPI1_TX1,
+- OMAP24XX_DMA_SPI1_TX2,
+- OMAP24XX_DMA_SPI1_TX3,
+-};
+-
+-static u8 __initdata spi2_rxdma_id[] = {
+- OMAP24XX_DMA_SPI2_RX0,
+- OMAP24XX_DMA_SPI2_RX1,
+-};
+-
+-static u8 __initdata spi2_txdma_id[] = {
+- OMAP24XX_DMA_SPI2_TX0,
+- OMAP24XX_DMA_SPI2_TX1,
+-};
+-
+-#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
+- || defined(CONFIG_ARCH_OMAP4)
+-static u8 __initdata spi3_rxdma_id[] = {
+- OMAP24XX_DMA_SPI3_RX0,
+- OMAP24XX_DMA_SPI3_RX1,
+-};
+-
+-static u8 __initdata spi3_txdma_id[] = {
+- OMAP24XX_DMA_SPI3_TX0,
+- OMAP24XX_DMA_SPI3_TX1,
+-};
+-#endif
+-
+-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+-static u8 __initdata spi4_rxdma_id[] = {
+- OMAP34XX_DMA_SPI4_RX0,
+-};
+-
+-static u8 __initdata spi4_txdma_id[] = {
+- OMAP34XX_DMA_SPI4_TX0,
+-};
+-#endif
+
+ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ {
+ struct spi_master *master;
++ struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
+ struct omap2_mcspi *mcspi;
+ struct resource *r;
+ int status = 0, i;
+- const u8 *rxdma_id, *txdma_id;
+- unsigned num_chipselect;
+-
+- switch (pdev->id) {
+- case 1:
+- rxdma_id = spi1_rxdma_id;
+- txdma_id = spi1_txdma_id;
+- num_chipselect = 4;
+- break;
+- case 2:
+- rxdma_id = spi2_rxdma_id;
+- txdma_id = spi2_txdma_id;
+- num_chipselect = 2;
+- break;
+-#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
+- || defined(CONFIG_ARCH_OMAP4)
+- case 3:
+- rxdma_id = spi3_rxdma_id;
+- txdma_id = spi3_txdma_id;
+- num_chipselect = 2;
+- break;
+-#endif
+-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+- case 4:
+- rxdma_id = spi4_rxdma_id;
+- txdma_id = spi4_txdma_id;
+- num_chipselect = 1;
+- break;
+-#endif
+- default:
+- return -EINVAL;
+- }
+
+ master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
+ if (master == NULL) {
+@@ -1188,7 +1111,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ master->setup = omap2_mcspi_setup;
+ master->transfer = omap2_mcspi_transfer;
+ master->cleanup = omap2_mcspi_cleanup;
+- master->num_chipselect = num_chipselect;
++ master->num_chipselect = pdata->num_cs;
+
+ dev_set_drvdata(&pdev->dev, master);
+
+@@ -1206,6 +1129,8 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ goto err1;
+ }
+
++ r->start += pdata->regs_offset;
++ r->end += pdata->regs_offset;
+ mcspi->phys = r->start;
+ mcspi->base = ioremap(r->start, r->end - r->start + 1);
+ if (!mcspi->base) {
+@@ -1240,11 +1165,32 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ if (mcspi->dma_channels == NULL)
+ goto err3;
+
+- for (i = 0; i < num_chipselect; i++) {
++ for (i = 0; i < master->num_chipselect; i++) {
++ char dma_ch_name[14];
++ struct resource *dma_res;
++
++ sprintf(dma_ch_name, "rx%d", i);
++ dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
++ dma_ch_name);
++ if (!dma_res) {
++ dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
++ status = -ENODEV;
++ break;
++ }
++
+ mcspi->dma_channels[i].dma_rx_channel = -1;
+- mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
++ mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
++ sprintf(dma_ch_name, "tx%d", i);
++ dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
++ dma_ch_name);
++ if (!dma_res) {
++ dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
++ status = -ENODEV;
++ break;
++ }
++
+ mcspi->dma_channels[i].dma_tx_channel = -1;
+- mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
++ mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
+ }
+
+ if (omap2_mcspi_reset(mcspi) < 0)
+--
+1.7.1
+
diff --git a/patches/for_next/0052-OMAP-runtime-McSPI-driver-runtime-conversion.patch b/patches/for_next/0052-OMAP-runtime-McSPI-driver-runtime-conversion.patch
new file mode 100644
index 0000000000000000000000000000000000000000..41a6bf03452d559a7c958c4e084a3481138279b0
--- /dev/null
+++ b/patches/for_next/0052-OMAP-runtime-McSPI-driver-runtime-conversion.patch
@@ -0,0 +1,302 @@
+From 1f417fb6fe0c867c4367b991103fbe93f83a760d Mon Sep 17 00:00:00 2001
+From: Govindraj.R <govindraj.raja@ti.com>
+Date: Wed, 2 Feb 2011 17:52:15 +0530
+Subject: [PATCH 052/254] OMAP: runtime: McSPI driver runtime conversion
+
+McSPI runtime conversion.
+Changes involves:
+1) remove clock framework apis to use runtime framework apis.
+2) context restore from runtime resume which is a callback for get_sync.
+3) Remove SYSCONFIG(sysc) register handling
+ (a) Remove context save and restore of sysc reg and remove soft reset
+ done from sysc reg as this will be done with hwmod framework.
+ (b) Also cleanup sysc reg bit macros.
+4) Rename the omap2_mcspi_reset function to omap2_mcspi_master_setup
+ function as with hwmod changes soft reset will be done in
+ hwmod framework itself and use the return value from clock
+ enable function to return for failure scenarios.
+
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+Reviewed-by: Partha Basak <p-basak2@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ drivers/spi/omap2_mcspi.c | 116 ++++++++++++++++----------------------------
+ 1 files changed, 42 insertions(+), 74 deletions(-)
+
+diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
+index f785132..36501ad 100644
+--- a/drivers/spi/omap2_mcspi.c
++++ b/drivers/spi/omap2_mcspi.c
+@@ -33,6 +33,7 @@
+ #include <linux/clk.h>
+ #include <linux/io.h>
+ #include <linux/slab.h>
++#include <linux/pm_runtime.h>
+
+ #include <linux/spi/spi.h>
+
+@@ -46,7 +47,6 @@
+ #define OMAP2_MCSPI_MAX_CTRL 4
+
+ #define OMAP2_MCSPI_REVISION 0x00
+-#define OMAP2_MCSPI_SYSCONFIG 0x10
+ #define OMAP2_MCSPI_SYSSTATUS 0x14
+ #define OMAP2_MCSPI_IRQSTATUS 0x18
+ #define OMAP2_MCSPI_IRQENABLE 0x1c
+@@ -63,13 +63,6 @@
+
+ /* per-register bitmasks: */
+
+-#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
+-#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
+-#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
+-#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
+-
+-#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
+-
+ #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
+ #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
+ #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
+@@ -122,13 +115,12 @@ struct omap2_mcspi {
+ spinlock_t lock;
+ struct list_head msg_queue;
+ struct spi_master *master;
+- struct clk *ick;
+- struct clk *fck;
+ /* Virtual base address of the controller */
+ void __iomem *base;
+ unsigned long phys;
+ /* SPI1 has 4 channels, while SPI2 has 2 */
+ struct omap2_mcspi_dma *dma_channels;
++ struct device *dev;
+ };
+
+ struct omap2_mcspi_cs {
+@@ -144,7 +136,6 @@ struct omap2_mcspi_cs {
+ * corresponding registers are modified.
+ */
+ struct omap2_mcspi_regs {
+- u32 sysconfig;
+ u32 modulctrl;
+ u32 wakeupenable;
+ struct list_head cs;
+@@ -268,9 +259,6 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
+ mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
+ omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
+
+- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
+- omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
+-
+ mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
+ omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
+
+@@ -280,20 +268,12 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
+ }
+ static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
+ {
+- clk_disable(mcspi->ick);
+- clk_disable(mcspi->fck);
++ pm_runtime_put_sync(mcspi->dev);
+ }
+
+ static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
+ {
+- if (clk_enable(mcspi->ick))
+- return -ENODEV;
+- if (clk_enable(mcspi->fck))
+- return -ENODEV;
+-
+- omap2_mcspi_restore_ctx(mcspi);
+-
+- return 0;
++ return pm_runtime_get_sync(mcspi->dev);
+ }
+
+ static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
+@@ -819,8 +799,9 @@ static int omap2_mcspi_setup(struct spi_device *spi)
+ return ret;
+ }
+
+- if (omap2_mcspi_enable_clocks(mcspi))
+- return -ENODEV;
++ ret = omap2_mcspi_enable_clocks(mcspi);
++ if (ret < 0)
++ return ret;
+
+ ret = omap2_mcspi_setup_transfer(spi, NULL);
+ omap2_mcspi_disable_clocks(mcspi);
+@@ -863,10 +844,11 @@ static void omap2_mcspi_work(struct work_struct *work)
+ struct omap2_mcspi *mcspi;
+
+ mcspi = container_of(work, struct omap2_mcspi, work);
+- spin_lock_irq(&mcspi->lock);
+
+- if (omap2_mcspi_enable_clocks(mcspi))
+- goto out;
++ if (omap2_mcspi_enable_clocks(mcspi) < 0)
++ return;
++
++ spin_lock_irq(&mcspi->lock);
+
+ /* We only enable one channel at a time -- the one whose message is
+ * at the head of the queue -- although this controller would gladly
+@@ -979,10 +961,9 @@ static void omap2_mcspi_work(struct work_struct *work)
+ spin_lock_irq(&mcspi->lock);
+ }
+
+- omap2_mcspi_disable_clocks(mcspi);
+-
+-out:
+ spin_unlock_irq(&mcspi->lock);
++
++ omap2_mcspi_disable_clocks(mcspi);
+ }
+
+ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
+@@ -1058,25 +1039,15 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
+ return 0;
+ }
+
+-static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
++static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
+ {
+ struct spi_master *master = mcspi->master;
+ u32 tmp;
++ int ret = 0;
+
+- if (omap2_mcspi_enable_clocks(mcspi))
+- return -1;
+-
+- mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
+- OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
+- do {
+- tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
+- } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
+-
+- tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
+- OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
+- OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
+- mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
+- omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
++ ret = omap2_mcspi_enable_clocks(mcspi);
++ if (ret < 0)
++ return ret;
+
+ tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
+ mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
+@@ -1087,6 +1058,18 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
+ return 0;
+ }
+
++static int omap_mcspi_runtime_resume(struct device *dev)
++{
++ struct omap2_mcspi *mcspi;
++ struct spi_master *master;
++
++ master = dev_get_drvdata(dev);
++ mcspi = spi_master_get_devdata(master);
++ omap2_mcspi_restore_ctx(mcspi);
++
++ return 0;
++}
++
+
+ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ {
+@@ -1136,34 +1119,22 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ if (!mcspi->base) {
+ dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
+ status = -ENOMEM;
+- goto err1aa;
++ goto err2;
+ }
+
++ mcspi->dev = &pdev->dev;
+ INIT_WORK(&mcspi->work, omap2_mcspi_work);
+
+ spin_lock_init(&mcspi->lock);
+ INIT_LIST_HEAD(&mcspi->msg_queue);
+ INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
+
+- mcspi->ick = clk_get(&pdev->dev, "ick");
+- if (IS_ERR(mcspi->ick)) {
+- dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
+- status = PTR_ERR(mcspi->ick);
+- goto err1a;
+- }
+- mcspi->fck = clk_get(&pdev->dev, "fck");
+- if (IS_ERR(mcspi->fck)) {
+- dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
+- status = PTR_ERR(mcspi->fck);
+- goto err2;
+- }
+-
+ mcspi->dma_channels = kcalloc(master->num_chipselect,
+ sizeof(struct omap2_mcspi_dma),
+ GFP_KERNEL);
+
+ if (mcspi->dma_channels == NULL)
+- goto err3;
++ goto err2;
+
+ for (i = 0; i < master->num_chipselect; i++) {
+ char dma_ch_name[14];
+@@ -1193,8 +1164,10 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
+ }
+
+- if (omap2_mcspi_reset(mcspi) < 0)
+- goto err4;
++ pm_runtime_enable(&pdev->dev);
++
++ if (status || omap2_mcspi_master_setup(mcspi) < 0)
++ goto err3;
+
+ status = spi_register_master(master);
+ if (status < 0)
+@@ -1203,17 +1176,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
+ return status;
+
+ err4:
+- kfree(mcspi->dma_channels);
++ spi_master_put(master);
+ err3:
+- clk_put(mcspi->fck);
++ kfree(mcspi->dma_channels);
+ err2:
+- clk_put(mcspi->ick);
+-err1a:
+- iounmap(mcspi->base);
+-err1aa:
+ release_mem_region(r->start, (r->end - r->start) + 1);
++ iounmap(mcspi->base);
+ err1:
+- spi_master_put(master);
+ return status;
+ }
+
+@@ -1229,9 +1198,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
+ mcspi = spi_master_get_devdata(master);
+ dma_channels = mcspi->dma_channels;
+
+- clk_put(mcspi->fck);
+- clk_put(mcspi->ick);
+-
++ omap2_mcspi_disable_clocks(mcspi);
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(r->start, (r->end - r->start) + 1);
+
+@@ -1282,6 +1249,7 @@ static int omap2_mcspi_resume(struct device *dev)
+
+ static const struct dev_pm_ops omap2_mcspi_pm_ops = {
+ .resume = omap2_mcspi_resume,
++ .runtime_resume = omap_mcspi_runtime_resume,
+ };
+
+ static struct platform_driver omap2_mcspi_driver = {
+--
+1.7.1
+
diff --git a/patches/for_next/0053-omap2plus-omap4-Set-NR_CPU-to-2-instead-of-default-4.patch b/patches/for_next/0053-omap2plus-omap4-Set-NR_CPU-to-2-instead-of-default-4.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8ba6af30d5ed28fdfcd5563ae90f0572f8b87170
--- /dev/null
+++ b/patches/for_next/0053-omap2plus-omap4-Set-NR_CPU-to-2-instead-of-default-4.patch
@@ -0,0 +1,29 @@
+From 1a4f46c7d391adadd5dc4c400e6aa74f85bae705 Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Thu, 17 Feb 2011 09:55:03 -0800
+Subject: [PATCH 053/254] omap2plus: omap4: Set NR_CPU to 2 instead of default 4
+
+The omap2plus_defconfig picks default NR_CPU value as 4 which isn't
+correct for OMAP4430. Available CPUs are ony 2, so fix the same.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/configs/omap2plus_defconfig | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
+index ae890ca..019fb7c 100644
+--- a/arch/arm/configs/omap2plus_defconfig
++++ b/arch/arm/configs/omap2plus_defconfig
+@@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y
+ CONFIG_NO_HZ=y
+ CONFIG_HIGH_RES_TIMERS=y
+ CONFIG_SMP=y
++CONFIG_NR_CPUS=2
+ # CONFIG_LOCAL_TIMERS is not set
+ CONFIG_AEABI=y
+ CONFIG_LEDS=y
+--
+1.7.1
+
diff --git a/patches/for_next/0054-omap4-Remove-FIXME-omap44xx_sram_init-not-implemente.patch b/patches/for_next/0054-omap4-Remove-FIXME-omap44xx_sram_init-not-implemente.patch
new file mode 100644
index 0000000000000000000000000000000000000000..aef8418423ad3ec60d8bca56775654606118ac49
--- /dev/null
+++ b/patches/for_next/0054-omap4-Remove-FIXME-omap44xx_sram_init-not-implemente.patch
@@ -0,0 +1,57 @@
+From 86277d11a62476bf0daf52c70eab4fbbfcef7418 Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Thu, 17 Feb 2011 09:55:03 -0800
+Subject: [PATCH 054/254] omap4: Remove 'FIXME: omap44xx_sram_init not implemented'
+
+The omap44xx_sram_init() implements functionality to push some
+code on SRAM whenever the code can't be executed from external
+memory. The low power and DVFS code can be executed from
+external DDR itself thanks to OMAP4 memory controller hardware
+support. So on OMAP4, sram_push kind of functionality isn't needed.
+
+Hence remove the FIXME warning added for implementing sram push
+feature on OMAP4.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/sram.c | 16 ----------------
+ 1 files changed, 0 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
+index aedcb3b..9d80064 100644
+--- a/arch/arm/plat-omap/sram.c
++++ b/arch/arm/plat-omap/sram.c
+@@ -405,20 +405,6 @@ static inline int omap34xx_sram_init(void)
+ }
+ #endif
+
+-#ifdef CONFIG_ARCH_OMAP4
+-static int __init omap44xx_sram_init(void)
+-{
+- printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
+-
+- return -ENODEV;
+-}
+-#else
+-static inline int omap44xx_sram_init(void)
+-{
+- return 0;
+-}
+-#endif
+-
+ int __init omap_sram_init(void)
+ {
+ omap_detect_sram();
+@@ -432,8 +418,6 @@ int __init omap_sram_init(void)
+ omap243x_sram_init();
+ else if (cpu_is_omap34xx())
+ omap34xx_sram_init();
+- else if (cpu_is_omap44xx())
+- omap44xx_sram_init();
+
+ return 0;
+ }
+--
+1.7.1
+
diff --git a/patches/for_next/0055-OMAP4-keypad-Add-the-board-support.patch b/patches/for_next/0055-OMAP4-keypad-Add-the-board-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d351665cd558eb235d25952179da57cd8fec8d88
--- /dev/null
+++ b/patches/for_next/0055-OMAP4-keypad-Add-the-board-support.patch
@@ -0,0 +1,193 @@
+From a4b244a0d8aa82c15671fd441694a4239d9370ad Mon Sep 17 00:00:00 2001
+From: Syed Rafiuddin <rafiuddin.syed@ti.com>
+Date: Mon, 27 Dec 2010 05:51:45 +0000
+Subject: [PATCH 055/254] OMAP4: keypad: Add the board support
+
+-Add the platform changes for the keypad driver
+-Register keyboard device with hwmod framework.
+
+Signed-off-by: Syed Rafiuddin <rafiuddin.syed@ti.com>
+Signed-off-by: Abraham Arce <x0066660@ti.com>
+Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-4430sdp.c | 89 +++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/devices.c | 41 ++++++++++++++++
+ 2 files changed, 130 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index bf82684..7f58d89 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -35,6 +35,7 @@
+ #include <plat/common.h>
+ #include <plat/usb.h>
+ #include <plat/mmc.h>
++#include <plat/omap4-keypad.h>
+
+ #include "mux.h"
+ #include "hsmmc.h"
+@@ -47,6 +48,90 @@
+ #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
+ #define OMAP4_SFH7741_ENABLE_GPIO 188
+
++static const int sdp4430_keymap[] = {
++ KEY(0, 0, KEY_E),
++ KEY(0, 1, KEY_R),
++ KEY(0, 2, KEY_T),
++ KEY(0, 3, KEY_HOME),
++ KEY(0, 4, KEY_F5),
++ KEY(0, 5, KEY_UNKNOWN),
++ KEY(0, 6, KEY_I),
++ KEY(0, 7, KEY_LEFTSHIFT),
++
++ KEY(1, 0, KEY_D),
++ KEY(1, 1, KEY_F),
++ KEY(1, 2, KEY_G),
++ KEY(1, 3, KEY_SEND),
++ KEY(1, 4, KEY_F6),
++ KEY(1, 5, KEY_UNKNOWN),
++ KEY(1, 6, KEY_K),
++ KEY(1, 7, KEY_ENTER),
++
++ KEY(2, 0, KEY_X),
++ KEY(2, 1, KEY_C),
++ KEY(2, 2, KEY_V),
++ KEY(2, 3, KEY_END),
++ KEY(2, 4, KEY_F7),
++ KEY(2, 5, KEY_UNKNOWN),
++ KEY(2, 6, KEY_DOT),
++ KEY(2, 7, KEY_CAPSLOCK),
++
++ KEY(3, 0, KEY_Z),
++ KEY(3, 1, KEY_KPPLUS),
++ KEY(3, 2, KEY_B),
++ KEY(3, 3, KEY_F1),
++ KEY(3, 4, KEY_F8),
++ KEY(3, 5, KEY_UNKNOWN),
++ KEY(3, 6, KEY_O),
++ KEY(3, 7, KEY_SPACE),
++
++ KEY(4, 0, KEY_W),
++ KEY(4, 1, KEY_Y),
++ KEY(4, 2, KEY_U),
++ KEY(4, 3, KEY_F2),
++ KEY(4, 4, KEY_VOLUMEUP),
++ KEY(4, 5, KEY_UNKNOWN),
++ KEY(4, 6, KEY_L),
++ KEY(4, 7, KEY_LEFT),
++
++ KEY(5, 0, KEY_S),
++ KEY(5, 1, KEY_H),
++ KEY(5, 2, KEY_J),
++ KEY(5, 3, KEY_F3),
++ KEY(5, 4, KEY_F9),
++ KEY(5, 5, KEY_VOLUMEDOWN),
++ KEY(5, 6, KEY_M),
++ KEY(5, 7, KEY_RIGHT),
++
++ KEY(6, 0, KEY_Q),
++ KEY(6, 1, KEY_A),
++ KEY(6, 2, KEY_N),
++ KEY(6, 3, KEY_BACK),
++ KEY(6, 4, KEY_BACKSPACE),
++ KEY(6, 5, KEY_UNKNOWN),
++ KEY(6, 6, KEY_P),
++ KEY(6, 7, KEY_UP),
++
++ KEY(7, 0, KEY_PROG1),
++ KEY(7, 1, KEY_PROG2),
++ KEY(7, 2, KEY_PROG3),
++ KEY(7, 3, KEY_PROG4),
++ KEY(7, 4, KEY_F4),
++ KEY(7, 5, KEY_UNKNOWN),
++ KEY(7, 6, KEY_OK),
++ KEY(7, 7, KEY_DOWN),
++};
++
++static struct matrix_keymap_data sdp4430_keymap_data = {
++ .keymap = sdp4430_keymap,
++ .keymap_size = ARRAY_SIZE(sdp4430_keymap),
++};
++
++static struct omap4_keypad_platform_data sdp4430_keypad_data = {
++ .keymap_data = &sdp4430_keymap_data,
++ .rows = 8,
++ .cols = 8,
++};
+ static struct gpio_led sdp4430_gpio_leds[] = {
+ {
+ .name = "omap4:green:debug0",
+@@ -574,6 +659,10 @@ static void __init omap_4430sdp_init(void)
+ spi_register_board_info(sdp4430_spi_board_info,
+ ARRAY_SIZE(sdp4430_spi_board_info));
+ }
++
++ status = omap4_keyboard_init(&sdp4430_keypad_data);
++ if (status)
++ pr_err("Keypad initialization failed: %d\n", status);
+ }
+
+ static void __init omap_4430sdp_map_io(void)
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index 71f099b..9ee876f 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -31,6 +31,7 @@
+ #include <plat/dma.h>
+ #include <plat/omap_hwmod.h>
+ #include <plat/omap_device.h>
++#include <plat/omap4-keypad.h>
+
+ #include "mux.h"
+ #include "control.h"
+@@ -142,6 +143,46 @@ static inline void omap_init_camera(void)
+ }
+ #endif
+
++struct omap_device_pm_latency omap_keyboard_latency[] = {
++ {
++ .deactivate_func = omap_device_idle_hwmods,
++ .activate_func = omap_device_enable_hwmods,
++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
++ },
++};
++
++int __init omap4_keyboard_init(struct omap4_keypad_platform_data
++ *sdp4430_keypad_data)
++{
++ struct omap_device *od;
++ struct omap_hwmod *oh;
++ struct omap4_keypad_platform_data *keypad_data;
++ unsigned int id = -1;
++ char *oh_name = "kbd";
++ char *name = "omap4-keypad";
++
++ oh = omap_hwmod_lookup(oh_name);
++ if (!oh) {
++ pr_err("Could not look up %s\n", oh_name);
++ return -ENODEV;
++ }
++
++ keypad_data = sdp4430_keypad_data;
++
++ od = omap_device_build(name, id, oh, keypad_data,
++ sizeof(struct omap4_keypad_platform_data),
++ omap_keyboard_latency,
++ ARRAY_SIZE(omap_keyboard_latency), 0);
++
++ if (IS_ERR(od)) {
++ WARN(1, "Cant build omap_device for %s:%s.\n",
++ name, oh->name);
++ return PTR_ERR(od);
++ }
++
++ return 0;
++}
++
+ #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+
+ #define MBOX_REG_SIZE 0x120
+--
+1.7.1
+
diff --git a/patches/for_next/0056-omap3evm-add-support-for-the-WL12xx-WLAN-module-to-t.patch b/patches/for_next/0056-omap3evm-add-support-for-the-WL12xx-WLAN-module-to-t.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2ffb49a8f8847e7e01a25fd70b34366301cb44aa
--- /dev/null
+++ b/patches/for_next/0056-omap3evm-add-support-for-the-WL12xx-WLAN-module-to-t.patch
@@ -0,0 +1,134 @@
+From 2583e92fa439164a00fa28ebb894f78c2754a04e Mon Sep 17 00:00:00 2001
+From: Eyal Reizer <eyalr@ti.com>
+Date: Thu, 27 Jan 2011 09:49:49 +0000
+Subject: [PATCH 056/254] omap3evm: add support for the WL12xx WLAN module to the AM/DM3xx Evaluation Module
+
+Adds platform initialization for working with the WLAN module attached to the evaluation module.
+The patch includes MMC2 initialization, SDIO and control pins muxing and platform device registration
+
+Signed-off-by: Eyal Reizer <eyalr@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 78 ++++++++++++++++++++++++++++++++++
+ 1 files changed, 78 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index c2a0fca..ac50bf9 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -30,6 +30,8 @@
+ #include <linux/usb/otg.h>
+ #include <linux/smsc911x.h>
+
++#include <linux/wl12xx.h>
++#include <linux/regulator/fixed.h>
+ #include <linux/regulator/machine.h>
+ #include <linux/mmc/host.h>
+
+@@ -381,6 +383,16 @@ static struct omap2_hsmmc_info mmc[] = {
+ .gpio_cd = -EINVAL,
+ .gpio_wp = 63,
+ },
++#ifdef CONFIG_WL12XX_PLATFORM_DATA
++ {
++ .name = "wl1271",
++ .mmc = 2,
++ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
++ .gpio_wp = -EINVAL,
++ .gpio_cd = -EINVAL,
++ .nonremovable = true,
++ },
++#endif
+ {} /* Terminator */
+ };
+
+@@ -538,6 +550,50 @@ static struct regulator_init_data omap3_evm_vpll2 = {
+ .consumer_supplies = &omap3_evm_vpll2_supply,
+ };
+
++#ifdef CONFIG_WL12XX_PLATFORM_DATA
++
++#define OMAP3EVM_WLAN_PMENA_GPIO (150)
++#define OMAP3EVM_WLAN_IRQ_GPIO (149)
++
++static struct regulator_consumer_supply omap3evm_vmmc2_supply = {
++ .supply = "vmmc",
++ .dev_name = "mmci-omap-hs.1",
++};
++
++/* VMMC2 for driving the WL12xx module */
++static struct regulator_init_data omap3evm_vmmc2 = {
++ .constraints = {
++ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = 1,
++ .consumer_supplies = &omap3evm_vmmc2_supply,
++};
++
++static struct fixed_voltage_config omap3evm_vwlan = {
++ .supply_name = "vwl1271",
++ .microvolts = 1800000, /* 1.80V */
++ .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
++ .startup_delay = 70000, /* 70ms */
++ .enable_high = 1,
++ .enabled_at_boot = 0,
++ .init_data = &omap3evm_vmmc2,
++};
++
++static struct platform_device omap3evm_vwlan_device = {
++ .name = "reg-fixed-voltage",
++ .id = 1,
++ .dev = {
++ .platform_data = &omap3evm_vwlan,
++ },
++};
++
++struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
++ .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
++ /* ref clock is 38.4 MHz */
++ .board_ref_clock = 2,
++};
++#endif
++
+ static struct twl4030_platform_data omap3evm_twldata = {
+ .irq_base = TWL4030_IRQ_BASE,
+ .irq_end = TWL4030_IRQ_END,
+@@ -657,6 +713,21 @@ static struct omap_board_mux board_mux[] __initdata = {
+ OMAP_PIN_OFF_WAKEUPENABLE),
+ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
++#ifdef CONFIG_WL12XX_PLATFORM_DATA
++ /* WLAN IRQ - GPIO 149 */
++ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
++
++ /* WLAN POWER ENABLE - GPIO 150 */
++ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
++
++ /* MMC2 SDIO pin muxes for WL12xx */
++ OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++#endif
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
+ #endif
+@@ -714,6 +785,13 @@ static void __init omap3_evm_init(void)
+ ads7846_dev_init();
+ omap3evm_init_smsc911x();
+ omap3_evm_display_init();
++
++#ifdef CONFIG_WL12XX_PLATFORM_DATA
++ /* WL12xx WLAN Init */
++ if (wl12xx_set_platform_data(&omap3evm_wlan_data))
++ pr_err("error setting wl12xx data\n");
++ platform_device_register(&omap3evm_vwlan_device);
++#endif
+ }
+
+ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
+--
+1.7.1
+
diff --git a/patches/for_next/0057-OMAP3EVM-Reset-the-smsc911x-ethernet-controller-in-b.patch b/patches/for_next/0057-OMAP3EVM-Reset-the-smsc911x-ethernet-controller-in-b.patch
new file mode 100644
index 0000000000000000000000000000000000000000..4a475f013b86dbb0673bed9381f6234ff0ab0ad0
--- /dev/null
+++ b/patches/for_next/0057-OMAP3EVM-Reset-the-smsc911x-ethernet-controller-in-b.patch
@@ -0,0 +1,101 @@
+From e74f0a55bf1978917b995da6f321638cde4df3b2 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Mon, 24 Jan 2011 19:25:55 +0000
+Subject: [PATCH 057/254] OMAP3EVM: Reset the smsc911x ethernet controller in board_init
+
+With addition of hwmod support to gpio, the ethernet controller
+goes undetected for OMAP35xEVM. So explicitly assert the reset signal to
+ethernet controller smsc911x -
+
+ - GPIO7 (>=RevG version of EVM's)
+ - GPIO64 (<=RevD version of EVM's)
+
+Tested this patch on RevG version of EVM with ES3.1 Si.
+
+This patch is based on intial version from Charulatha V, reference
+to original discussion -
+http://www.mail-archive.com/linux-omap@vger.kernel.org/msg35784.html
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 39 +++++++++++++++++++++++++++++++++-
+ 1 files changed, 38 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index ac50bf9..b9f954e 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -60,6 +60,13 @@
+ #define OMAP3EVM_ETHR_ID_REV 0x50
+ #define OMAP3EVM_ETHR_GPIO_IRQ 176
+ #define OMAP3EVM_SMSC911X_CS 5
++/*
++ * Eth Reset signal
++ * 64 = Generation 1 (<=RevD)
++ * 7 = Generation 2 (>=RevE)
++ */
++#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
++#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
+
+ static u8 omap3_evm_version;
+
+@@ -126,10 +133,15 @@ static struct platform_device omap3evm_smsc911x_device = {
+
+ static inline void __init omap3evm_init_smsc911x(void)
+ {
+- int eth_cs;
++ int eth_cs, eth_rst;
+ struct clk *l3ck;
+ unsigned int rate;
+
++ if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
++ eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST;
++ else
++ eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST;
++
+ eth_cs = OMAP3EVM_SMSC911X_CS;
+
+ l3ck = clk_get(NULL, "l3_ck");
+@@ -138,6 +150,27 @@ static inline void __init omap3evm_init_smsc911x(void)
+ else
+ rate = clk_get_rate(l3ck);
+
++ /* Configure ethernet controller reset gpio */
++ if (cpu_is_omap3430()) {
++ if (gpio_request(eth_rst, "SMSC911x gpio") < 0) {
++ pr_err(KERN_ERR "Failed to request %d for smsc911x\n",
++ eth_rst);
++ return;
++ }
++
++ if (gpio_direction_output(eth_rst, 1) < 0) {
++ pr_err(KERN_ERR "Failed to set direction of %d for" \
++ " smsc911x\n", eth_rst);
++ return;
++ }
++ /* reset pulse to ethernet controller*/
++ usleep_range(150, 220);
++ gpio_set_value(eth_rst, 0);
++ usleep_range(150, 220);
++ gpio_set_value(eth_rst, 1);
++ usleep_range(1, 2);
++ }
++
+ if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) {
+ printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
+ OMAP3EVM_ETHR_GPIO_IRQ);
+@@ -713,6 +746,10 @@ static struct omap_board_mux board_mux[] __initdata = {
+ OMAP_PIN_OFF_WAKEUPENABLE),
+ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
++ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
++ OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
++ OMAP_PIN_OFF_NONE),
+ #ifdef CONFIG_WL12XX_PLATFORM_DATA
+ /* WLAN IRQ - GPIO 149 */
+ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+--
+1.7.1
+
diff --git a/patches/for_next/0058-omap3evm-Change-TWL-related-gpio-API-s-to-gpio-_cans.patch b/patches/for_next/0058-omap3evm-Change-TWL-related-gpio-API-s-to-gpio-_cans.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5ea9d1c68aa4006f48703004cfa5aa5ed6ec4675
--- /dev/null
+++ b/patches/for_next/0058-omap3evm-Change-TWL-related-gpio-API-s-to-gpio-_cans.patch
@@ -0,0 +1,66 @@
+From a50988d127892dc826ecb74aeac56eff438b14a0 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Tue, 25 Jan 2011 17:37:37 +0000
+Subject: [PATCH 058/254] omap3evm: Change TWL related gpio API's to gpio*_cansleep
+
+Since TWL GPIO's can go into sleep, and using normal
+gpio_get/set_value() API will lead to kernel dump (WARN_ON()).
+So replacing standard gpio_get/set_value() to
+gpio_get/set_value_cansleep().
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+Reviewed-by: Charulatha V <charu@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 12 ++++++------
+ 1 files changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index b9f954e..80c9f8a 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -270,9 +270,9 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
+ gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
+
+ if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
++ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+ else
+- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
++ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+
+ lcd_enabled = 1;
+ return 0;
+@@ -283,9 +283,9 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
+ gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
+
+ if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
++ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+ else
+- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
++ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+
+ lcd_enabled = 0;
+ }
+@@ -324,7 +324,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
+ return -EINVAL;
+ }
+
+- gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
++ gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
+
+ dvi_enabled = 1;
+ return 0;
+@@ -332,7 +332,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
+
+ static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
+ {
+- gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
++ gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
+
+ dvi_enabled = 0;
+ }
+--
+1.7.1
+
diff --git a/patches/for_next/0059-OMAP3EVM-Add-vio-regulator-supply-required-for-ads78.patch b/patches/for_next/0059-OMAP3EVM-Add-vio-regulator-supply-required-for-ads78.patch
new file mode 100644
index 0000000000000000000000000000000000000000..95de3996f970d3efa6c2772fd52f02b939959da4
--- /dev/null
+++ b/patches/for_next/0059-OMAP3EVM-Add-vio-regulator-supply-required-for-ads78.patch
@@ -0,0 +1,57 @@
+From de2133c7b0ee95a343aaff02e59705b4fe7fcd38 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Tue, 25 Jan 2011 17:37:38 +0000
+Subject: [PATCH 059/254] OMAP3EVM: Add vio regulator supply required for ads7846 TSC driver
+
+Add vio regulator supply, needed for ads7846 touchscreen controller
+driver.
+
+Tested on OMAP3 (ES3.1 Si) RevG version of EVM.
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 20 ++++++++++++++++++++
+ 1 files changed, 20 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 80c9f8a..bbdf3ad 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -583,6 +583,25 @@ static struct regulator_init_data omap3_evm_vpll2 = {
+ .consumer_supplies = &omap3_evm_vpll2_supply,
+ };
+
++/* ads7846 on SPI */
++static struct regulator_consumer_supply omap3evm_vio_supply =
++ REGULATOR_SUPPLY("vcc", "spi1.0");
++
++/* VIO for ads7846 */
++static struct regulator_init_data omap3evm_vio = {
++ .constraints = {
++ .min_uV = 1800000,
++ .max_uV = 1800000,
++ .apply_uV = true,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = 1,
++ .consumer_supplies = &omap3evm_vio_supply,
++};
++
+ #ifdef CONFIG_WL12XX_PLATFORM_DATA
+
+ #define OMAP3EVM_WLAN_PMENA_GPIO (150)
+@@ -639,6 +658,7 @@ static struct twl4030_platform_data omap3evm_twldata = {
+ .codec = &omap3evm_codec_data,
+ .vdac = &omap3_evm_vdac,
+ .vpll2 = &omap3_evm_vpll2,
++ .vio = &omap3evm_vio,
+ };
+
+ static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
+--
+1.7.1
+
diff --git a/patches/for_next/0060-AM-DM37x-DSS-mux-configuration-for-Rev-B-processor-c.patch b/patches/for_next/0060-AM-DM37x-DSS-mux-configuration-for-Rev-B-processor-c.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8c979ea7ddd6aeb0fb943f09291fb297c0ece65a
--- /dev/null
+++ b/patches/for_next/0060-AM-DM37x-DSS-mux-configuration-for-Rev-B-processor-c.patch
@@ -0,0 +1,81 @@
+From ae2a5224c6e1500d2b8b8db672397a5ee1943bb3 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Tue, 25 Jan 2011 17:37:39 +0000
+Subject: [PATCH 060/254] AM/DM37x: DSS mux configuration for >Rev-B processor cards
+
+To support higher resolution (e.g 720P@60), on OMAP36x (AM/DM37x)
+DSS data bus has been muxed with sys_boot pins.
+
+DSS[18-23] => DSS[0-5]
+sys_boot[0,1 3-5] => DSS[18-23]
+
+EVM revision >=RevB adopt this mux changes, which is going to ship outside.
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 34 ++++++++++++++++++++++++++++++++--
+ 1 files changed, 32 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index bbdf3ad..36dac55 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -760,7 +760,7 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
+ };
+
+ #ifdef CONFIG_OMAP_MUX
+-static struct omap_board_mux board_mux[] __initdata = {
++static struct omap_board_mux omap35x_board_mux[] __initdata = {
+ OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+ OMAP_PIN_OFF_WAKEUPENABLE),
+@@ -787,6 +787,32 @@ static struct omap_board_mux board_mux[] __initdata = {
+ #endif
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
++
++static struct omap_board_mux omap36x_board_mux[] __initdata = {
++ OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
++ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
++ OMAP_PIN_OFF_WAKEUPENABLE),
++ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
++ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
++ /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
++ OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++ OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++
++ { .reg_offset = OMAP_MUX_TERMINATOR },
++};
++#else
++#define omap35x_board_mux NULL
++#define omap36x_board_mux NULL
+ #endif
+
+ static struct omap_musb_board_data musb_board_data = {
+@@ -798,7 +824,11 @@ static struct omap_musb_board_data musb_board_data = {
+ static void __init omap3_evm_init(void)
+ {
+ omap3_evm_get_revision();
+- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
++
++ if (cpu_is_omap3630())
++ omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
++ else
++ omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
+
+ omap3_evm_i2c_init();
+
+--
+1.7.1
+
diff --git a/patches/for_next/0061-OMAP3EVM-Made-backlight-GPIO-default-state-to-off.patch b/patches/for_next/0061-OMAP3EVM-Made-backlight-GPIO-default-state-to-off.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3505f5aed44c94709a8ee306adc6d1bc160bbf4b
--- /dev/null
+++ b/patches/for_next/0061-OMAP3EVM-Made-backlight-GPIO-default-state-to-off.patch
@@ -0,0 +1,48 @@
+From 3becd628e4531e2bc40ba6d67b9d1bc9b8986218 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Tue, 25 Jan 2011 17:37:40 +0000
+Subject: [PATCH 061/254] OMAP3EVM: Made backlight GPIO default state to off
+
+If you choose default output to DVI, the LCD backlight used to
+stay on, since panel->disable function never gets called.
+
+So, during init put backlight GPIO to off state and the driver
+code will decide which output to enable.
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 10 ++++++++--
+ 1 files changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 36dac55..4f2574c 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -456,6 +456,8 @@ static struct platform_device leds_gpio = {
+ static int omap3evm_twl_gpio_setup(struct device *dev,
+ unsigned gpio, unsigned ngpio)
+ {
++ int r;
++
+ /* gpio + 0 is "mmc0_cd" (input/IRQ) */
+ omap_mux_init_gpio(63, OMAP_PIN_INPUT);
+ mmc[0].gpio_cd = gpio + 0;
+@@ -471,8 +473,12 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
+ */
+
+ /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
+- gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
+- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
++ r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
++ if (!r)
++ r = gpio_direction_output(gpio + TWL4030_GPIO_MAX,
++ (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0);
++ if (r)
++ printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
+
+ /* gpio + 7 == DVI Enable */
+ gpio_request(gpio + 7, "EN_DVI");
+--
+1.7.1
+
diff --git a/patches/for_next/0062-OMAP3EVM-Set-TSC-wakeup-option-in-pad-config.patch b/patches/for_next/0062-OMAP3EVM-Set-TSC-wakeup-option-in-pad-config.patch
new file mode 100644
index 0000000000000000000000000000000000000000..02275aacf205852382f3732627e1acf00c0683b8
--- /dev/null
+++ b/patches/for_next/0062-OMAP3EVM-Set-TSC-wakeup-option-in-pad-config.patch
@@ -0,0 +1,41 @@
+From 5acb1744a49387571258cd91e8760079547ffbee Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Tue, 25 Jan 2011 17:37:41 +0000
+Subject: [PATCH 062/254] OMAP3EVM: Set TSC wakeup option in pad config
+
+Set OMAP_PIN_OFF_WAKEUPENABLE to enable the wake-up
+functionality from touchscreen controller.
+
+Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 6 ++++--
+ 1 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 4f2574c..d4a1157 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -771,7 +771,8 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = {
+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+ OMAP_PIN_OFF_WAKEUPENABLE),
+ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+- OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
++ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
++ OMAP_PIN_OFF_WAKEUPENABLE),
+ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+ OMAP_PIN_OFF_NONE),
+ OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+@@ -799,7 +800,8 @@ static struct omap_board_mux omap36x_board_mux[] __initdata = {
+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+ OMAP_PIN_OFF_WAKEUPENABLE),
+ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+- OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
++ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
++ OMAP_PIN_OFF_WAKEUPENABLE),
+ /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
+ OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+ OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+--
+1.7.1
+
diff --git a/patches/for_next/0063-omap3630-nand-fix-device-size-to-work-in-polled-mode.patch b/patches/for_next/0063-omap3630-nand-fix-device-size-to-work-in-polled-mode.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2d241989038e1b1a99e4fefc0412e8ea5684bc59
--- /dev/null
+++ b/patches/for_next/0063-omap3630-nand-fix-device-size-to-work-in-polled-mode.patch
@@ -0,0 +1,182 @@
+From 60752791ef565e4a0ede07331bb06a05ba493647 Mon Sep 17 00:00:00 2001
+From: Sukumar Ghorai <s-ghorai@ti.com>
+Date: Fri, 28 Jan 2011 15:42:03 +0530
+Subject: [PATCH 063/254] omap3630: nand: fix device size to work in polled mode
+
+zoom3 and 3630-sdp having the x16 nand device.
+This patch configure gpmc as x16 and select the currect function in driver
+for polled mode (without prefetch enable) transfer.
+
+Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 2 +-
+ arch/arm/mach-omap2/board-3630sdp.c | 3 ++-
+ arch/arm/mach-omap2/board-flash.c | 10 ++++++----
+ arch/arm/mach-omap2/board-flash.h | 4 ++--
+ arch/arm/mach-omap2/board-ldp.c | 2 +-
+ arch/arm/mach-omap2/board-zoom.c | 5 +++--
+ arch/arm/mach-omap2/gpmc-nand.c | 7 +++++--
+ drivers/mtd/nand/omap2.c | 2 +-
+ 8 files changed, 21 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 3108588..4a37c70 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -812,7 +812,7 @@ static void __init omap_3430sdp_init(void)
+ omap_serial_init();
+ usb_musb_init(&musb_board_data);
+ board_smc91x_init();
+- board_flash_init(sdp_flash_partitions, chip_sel_3430);
++ board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
+ sdp3430_display_init();
+ enable_board_wakeup_source();
+ usb_ehci_init(&ehci_pdata);
+diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
+index 1653875..8d1c435 100644
+--- a/arch/arm/mach-omap2/board-3630sdp.c
++++ b/arch/arm/mach-omap2/board-3630sdp.c
+@@ -11,6 +11,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/input.h>
+ #include <linux/gpio.h>
++#include <linux/mtd/nand.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -208,7 +209,7 @@ static void __init omap_sdp_init(void)
+ zoom_peripherals_init();
+ zoom_display_init();
+ board_smc91x_init();
+- board_flash_init(sdp_flash_partitions, chip_sel_sdp);
++ board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
+ enable_board_wakeup_source();
+ usb_ehci_init(&ehci_pdata);
+ }
+diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
+index fd38c05..f6b7253 100644
+--- a/arch/arm/mach-omap2/board-flash.c
++++ b/arch/arm/mach-omap2/board-flash.c
+@@ -139,11 +139,13 @@ static struct omap_nand_platform_data board_nand_data = {
+ };
+
+ void
+-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
++__init board_nand_init(struct mtd_partition *nand_parts,
++ u8 nr_parts, u8 cs, int nand_type)
+ {
+ board_nand_data.cs = cs;
+ board_nand_data.parts = nand_parts;
+- board_nand_data.nr_parts = nr_parts;
++ board_nand_data.nr_parts = nr_parts;
++ board_nand_data.devsize = nand_type;
+
+ gpmc_nand_init(&board_nand_data);
+ }
+@@ -194,7 +196,7 @@ unmap:
+ * @return - void.
+ */
+ void board_flash_init(struct flash_partitions partition_info[],
+- char chip_sel_board[][GPMC_CS_NUM])
++ char chip_sel_board[][GPMC_CS_NUM], int nand_type)
+ {
+ u8 cs = 0;
+ u8 norcs = GPMC_CS_NUM + 1;
+@@ -250,5 +252,5 @@ void board_flash_init(struct flash_partitions partition_info[],
+ "in GPMC\n");
+ else
+ board_nand_init(partition_info[2].parts,
+- partition_info[2].nr_parts, nandcs);
++ partition_info[2].nr_parts, nandcs, nand_type);
+ }
+diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
+index 69befe0..c240a3f 100644
+--- a/arch/arm/mach-omap2/board-flash.h
++++ b/arch/arm/mach-omap2/board-flash.h
+@@ -25,6 +25,6 @@ struct flash_partitions {
+ };
+
+ extern void board_flash_init(struct flash_partitions [],
+- char chip_sel[][GPMC_CS_NUM]);
++ char chip_sel[][GPMC_CS_NUM], int nand_type);
+ extern void board_nand_init(struct mtd_partition *nand_parts,
+- u8 nr_parts, u8 cs);
++ u8 nr_parts, u8 cs, int nand_type);
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index d8eb2cb..a3fae56 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -433,7 +433,7 @@ static void __init omap_ldp_init(void)
+ omap_serial_init();
+ usb_musb_init(&musb_board_data);
+ board_nand_init(ldp_nand_partitions,
+- ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS);
++ ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
+
+ omap2_hsmmc_init(mmc);
+ /* link regulators to MMC adapters */
+diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
+index 85d4170..7e3f159 100644
+--- a/arch/arm/mach-omap2/board-zoom.c
++++ b/arch/arm/mach-omap2/board-zoom.c
+@@ -16,6 +16,7 @@
+ #include <linux/input.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c/twl.h>
++#include <linux/mtd/nand.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+@@ -124,8 +125,8 @@ static void __init omap_zoom_init(void)
+ usb_ehci_init(&ehci_pdata);
+ }
+
+- board_nand_init(zoom_nand_partitions,
+- ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
++ board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
++ ZOOM_NAND_CS, NAND_BUSWIDTH_16);
+ zoom_debugboard_init();
+ zoom_peripherals_init();
+ zoom_display_init();
+diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
+index 2bb29c1..c1791d0 100644
+--- a/arch/arm/mach-omap2/gpmc-nand.c
++++ b/arch/arm/mach-omap2/gpmc-nand.c
+@@ -12,6 +12,7 @@
+ #include <linux/kernel.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
++#include <linux/mtd/nand.h>
+
+ #include <asm/mach/flash.h>
+
+@@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void)
+ t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
+
+ /* Configure GPMC */
+- gpmc_cs_configure(gpmc_nand_data->cs,
+- GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize);
++ if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
++ gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
++ else
++ gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
+ gpmc_cs_configure(gpmc_nand_data->cs,
+ GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
+ err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
+diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
+index 15682ec..7c04cd6 100644
+--- a/drivers/mtd/nand/omap2.c
++++ b/drivers/mtd/nand/omap2.c
+@@ -804,7 +804,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ info->mtd.name = dev_name(&pdev->dev);
+ info->mtd.owner = THIS_MODULE;
+
+- info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0;
++ info->nand.options = pdata->devsize;
+ info->nand.options |= NAND_SKIP_BBTSCAN;
+
+ /* NAND write protect off */
+--
+1.7.1
+
diff --git a/patches/for_next/0064-omap3-nand-configurable-transfer-type-per-board.patch b/patches/for_next/0064-omap3-nand-configurable-transfer-type-per-board.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5f618cf3486d299678bc2a56050d81a701b1a4b5
--- /dev/null
+++ b/patches/for_next/0064-omap3-nand-configurable-transfer-type-per-board.patch
@@ -0,0 +1,233 @@
+From 09576a01f41502f2454ce2ad56d5bcfeaead2aa4 Mon Sep 17 00:00:00 2001
+From: Sukumar Ghorai <s-ghorai@ti.com>
+Date: Fri, 28 Jan 2011 15:42:04 +0530
+Subject: [PATCH 064/254] omap3: nand: configurable transfer type per board
+
+nand transfer type (sDMA, Polled, prefetch) can be select from board file,
+enabling all transfer type in driver, by default.
+
+this helps in multi-omap build and to select different transfer type for
+different board.
+
+Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/nand.h | 7 +++
+ drivers/mtd/nand/Kconfig | 17 ------
+ drivers/mtd/nand/omap2.c | 94 ++++++++++++--------------------
+ 3 files changed, 41 insertions(+), 77 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
+index 6562cd0..78c0bdb 100644
+--- a/arch/arm/plat-omap/include/plat/nand.h
++++ b/arch/arm/plat-omap/include/plat/nand.h
+@@ -10,6 +10,12 @@
+
+ #include <linux/mtd/partitions.h>
+
++enum nand_io {
++ NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
++ NAND_OMAP_POLLED, /* polled mode, without prefetch */
++ NAND_OMAP_PREFETCH_DMA /* prefetch enabled sDMA mode */
++};
++
+ struct omap_nand_platform_data {
+ unsigned int options;
+ int cs;
+@@ -20,6 +26,7 @@ struct omap_nand_platform_data {
+ int (*nand_setup)(void);
+ int (*dev_ready)(struct omap_nand_platform_data *);
+ int dma_channel;
++ enum nand_io xfer_type;
+ unsigned long phys_base;
+ int devsize;
+ };
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index c895922..178e200 100644
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -106,23 +106,6 @@ config MTD_NAND_OMAP2
+ help
+ Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms.
+
+-config MTD_NAND_OMAP_PREFETCH
+- bool "GPMC prefetch support for NAND Flash device"
+- depends on MTD_NAND_OMAP2
+- default y
+- help
+- The NAND device can be accessed for Read/Write using GPMC PREFETCH engine
+- to improve the performance.
+-
+-config MTD_NAND_OMAP_PREFETCH_DMA
+- depends on MTD_NAND_OMAP_PREFETCH
+- bool "DMA mode"
+- default n
+- help
+- The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode
+- or in DMA interrupt mode.
+- Say y for DMA mode or MPU mode will be used
+-
+ config MTD_NAND_IDS
+ tristate
+
+diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
+index 7c04cd6..60bac8e 100644
+--- a/drivers/mtd/nand/omap2.c
++++ b/drivers/mtd/nand/omap2.c
+@@ -96,27 +96,6 @@
+ static const char *part_probes[] = { "cmdlinepart", NULL };
+ #endif
+
+-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
+-static int use_prefetch = 1;
+-
+-/* "modprobe ... use_prefetch=0" etc */
+-module_param(use_prefetch, bool, 0);
+-MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH");
+-
+-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
+-static int use_dma = 1;
+-
+-/* "modprobe ... use_dma=0" etc */
+-module_param(use_dma, bool, 0);
+-MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
+-#else
+-static const int use_dma;
+-#endif
+-#else
+-const int use_prefetch;
+-static const int use_dma;
+-#endif
+-
+ struct omap_nand_info {
+ struct nand_hw_control controller;
+ struct omap_nand_platform_data *pdata;
+@@ -324,7 +303,6 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
+ }
+ }
+
+-#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
+ /*
+ * omap_nand_dma_cb: callback on the completion of dma transfer
+ * @lch: logical channel
+@@ -426,14 +404,6 @@ out_copy:
+ : omap_write_buf8(mtd, (u_char *) addr, len);
+ return 0;
+ }
+-#else
+-static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {}
+-static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
+- unsigned int len, int is_write)
+-{
+- return 0;
+-}
+-#endif
+
+ /**
+ * omap_read_buf_dma_pref - read data from NAND controller into buffer
+@@ -842,28 +812,13 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ info->nand.chip_delay = 50;
+ }
+
+- if (use_prefetch) {
+-
++ switch (pdata->xfer_type) {
++ case NAND_OMAP_PREFETCH_POLLED:
+ info->nand.read_buf = omap_read_buf_pref;
+ info->nand.write_buf = omap_write_buf_pref;
+- if (use_dma) {
+- err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
+- omap_nand_dma_cb, &info->comp, &info->dma_ch);
+- if (err < 0) {
+- info->dma_ch = -1;
+- printk(KERN_WARNING "DMA request failed."
+- " Non-dma data transfer mode\n");
+- } else {
+- omap_set_dma_dest_burst_mode(info->dma_ch,
+- OMAP_DMA_DATA_BURST_16);
+- omap_set_dma_src_burst_mode(info->dma_ch,
+- OMAP_DMA_DATA_BURST_16);
+-
+- info->nand.read_buf = omap_read_buf_dma_pref;
+- info->nand.write_buf = omap_write_buf_dma_pref;
+- }
+- }
+- } else {
++ break;
++
++ case NAND_OMAP_POLLED:
+ if (info->nand.options & NAND_BUSWIDTH_16) {
+ info->nand.read_buf = omap_read_buf16;
+ info->nand.write_buf = omap_write_buf16;
+@@ -871,7 +826,33 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ info->nand.read_buf = omap_read_buf8;
+ info->nand.write_buf = omap_write_buf8;
+ }
++ break;
++
++ case NAND_OMAP_PREFETCH_DMA:
++ err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
++ omap_nand_dma_cb, &info->comp, &info->dma_ch);
++ if (err < 0) {
++ info->dma_ch = -1;
++ dev_err(&pdev->dev, "DMA request failed!\n");
++ goto out_release_mem_region;
++ } else {
++ omap_set_dma_dest_burst_mode(info->dma_ch,
++ OMAP_DMA_DATA_BURST_16);
++ omap_set_dma_src_burst_mode(info->dma_ch,
++ OMAP_DMA_DATA_BURST_16);
++
++ info->nand.read_buf = omap_read_buf_dma_pref;
++ info->nand.write_buf = omap_write_buf_dma_pref;
++ }
++ break;
++
++ default:
++ dev_err(&pdev->dev,
++ "xfer_type(%d) not supported!\n", pdata->xfer_type);
++ err = -EINVAL;
++ goto out_release_mem_region;
+ }
++
+ info->nand.verify_buf = omap_verify_buf;
+
+ #ifdef CONFIG_MTD_NAND_OMAP_HWECC
+@@ -897,6 +878,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ }
+ }
+
++
+ #ifdef CONFIG_MTD_PARTITIONS
+ err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
+ if (err > 0)
+@@ -926,7 +908,7 @@ static int omap_nand_remove(struct platform_device *pdev)
+ mtd);
+
+ platform_set_drvdata(pdev, NULL);
+- if (use_dma)
++ if (info->dma_ch != -1)
+ omap_free_dma(info->dma_ch);
+
+ /* Release NAND device, its internal structures and partitions */
+@@ -947,16 +929,8 @@ static struct platform_driver omap_nand_driver = {
+
+ static int __init omap_nand_init(void)
+ {
+- printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
++ pr_info("%s driver initializing\n", DRIVER_NAME);
+
+- /* This check is required if driver is being
+- * loaded run time as a module
+- */
+- if ((1 == use_dma) && (0 == use_prefetch)) {
+- printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 "
+- "without use_prefetch'. Prefetch will not be"
+- " used in either mode (mpu or dma)\n");
+- }
+ return platform_driver_register(&omap_nand_driver);
+ }
+
+--
+1.7.1
+
diff --git a/patches/for_next/0065-omap-gpmc-enable-irq-mode-in-gpmc.patch b/patches/for_next/0065-omap-gpmc-enable-irq-mode-in-gpmc.patch
new file mode 100644
index 0000000000000000000000000000000000000000..54037b50e60723197d67225c9aeef7b42a470cb7
--- /dev/null
+++ b/patches/for_next/0065-omap-gpmc-enable-irq-mode-in-gpmc.patch
@@ -0,0 +1,196 @@
+From fddfc9892b1e9f2b9f06f77e77a8bb8d0766f8d1 Mon Sep 17 00:00:00 2001
+From: Sukumar Ghorai <s-ghorai@ti.com>
+Date: Fri, 28 Jan 2011 15:42:05 +0530
+Subject: [PATCH 065/254] omap: gpmc: enable irq mode in gpmc
+
+add support the irq mode in GPMC.
+gpmc_init() function move after omap_init_irq() as it has dependecy on irq.
+
+Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/gpmc.c | 45 +++++++++++++++++++++++++++++--
+ arch/arm/mach-omap2/io.c | 2 -
+ arch/arm/plat-omap/include/plat/gpmc.h | 5 +++-
+ arch/arm/plat-omap/include/plat/irqs.h | 9 +++++-
+ 4 files changed, 54 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
+index 1b7b3e7..382dea8 100644
+--- a/arch/arm/mach-omap2/gpmc.c
++++ b/arch/arm/mach-omap2/gpmc.c
+@@ -14,6 +14,7 @@
+ */
+ #undef DEBUG
+
++#include <linux/irq.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/err.h>
+@@ -22,6 +23,7 @@
+ #include <linux/spinlock.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
++#include <linux/interrupt.h>
+
+ #include <asm/mach-types.h>
+ #include <plat/gpmc.h>
+@@ -100,6 +102,8 @@ static void __iomem *gpmc_base;
+
+ static struct clk *gpmc_l3_clk;
+
++static irqreturn_t gpmc_handle_irq(int irq, void *dev);
++
+ static void gpmc_write_reg(int idx, u32 val)
+ {
+ __raw_writel(val, gpmc_base + idx);
+@@ -497,6 +501,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
+ u32 regval = 0;
+
+ switch (cmd) {
++ case GPMC_ENABLE_IRQ:
++ gpmc_write_reg(GPMC_IRQENABLE, wval);
++ break;
++
+ case GPMC_SET_IRQ_STATUS:
+ gpmc_write_reg(GPMC_IRQSTATUS, wval);
+ break;
+@@ -678,9 +686,10 @@ static void __init gpmc_mem_init(void)
+ }
+ }
+
+-void __init gpmc_init(void)
++static int __init gpmc_init(void)
+ {
+- u32 l;
++ u32 l, irq;
++ int cs, ret = -EINVAL;
+ char *ck = NULL;
+
+ if (cpu_is_omap24xx()) {
+@@ -698,7 +707,7 @@ void __init gpmc_init(void)
+ }
+
+ if (WARN_ON(!ck))
+- return;
++ return ret;
+
+ gpmc_l3_clk = clk_get(NULL, ck);
+ if (IS_ERR(gpmc_l3_clk)) {
+@@ -723,6 +732,36 @@ void __init gpmc_init(void)
+ l |= (0x02 << 3) | (1 << 0);
+ gpmc_write_reg(GPMC_SYSCONFIG, l);
+ gpmc_mem_init();
++
++ /* initalize the irq_chained */
++ irq = OMAP_GPMC_IRQ_BASE;
++ for (cs = 0; cs < GPMC_CS_NUM; cs++) {
++ set_irq_handler(irq, handle_simple_irq);
++ set_irq_flags(irq, IRQF_VALID);
++ irq++;
++ }
++
++ ret = request_irq(INT_34XX_GPMC_IRQ,
++ gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
++ if (ret)
++ pr_err("gpmc: irq-%d could not claim: err %d\n",
++ INT_34XX_GPMC_IRQ, ret);
++ return ret;
++}
++postcore_initcall(gpmc_init);
++
++static irqreturn_t gpmc_handle_irq(int irq, void *dev)
++{
++ u8 cs;
++
++ if (irq != INT_34XX_GPMC_IRQ)
++ return IRQ_HANDLED;
++ /* check cs to invoke the irq */
++ cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
++ if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
++ generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
++
++ return IRQ_HANDLED;
+ }
+
+ #ifdef CONFIG_ARCH_OMAP3
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index b8b49e4..657f3c8 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -30,7 +30,6 @@
+
+ #include <plat/sram.h>
+ #include <plat/sdrc.h>
+-#include <plat/gpmc.h>
+ #include <plat/serial.h>
+
+ #include "clock2xxx.h"
+@@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+ omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
+ _omap2_init_reprogram_sdrc();
+ }
+- gpmc_init();
+
+ omap_irq_base_init();
+ }
+diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
+index 85ded59..9c060da 100644
+--- a/arch/arm/plat-omap/include/plat/gpmc.h
++++ b/arch/arm/plat-omap/include/plat/gpmc.h
+@@ -41,6 +41,8 @@
+ #define GPMC_NAND_ADDRESS 0x0000000b
+ #define GPMC_NAND_DATA 0x0000000c
+
++#define GPMC_ENABLE_IRQ 0x0000000d
++
+ /* ECC commands */
+ #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
+ #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
+@@ -78,6 +80,8 @@
+ #define WR_RD_PIN_MONITORING 0x00600000
+ #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
+ #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
++#define GPMC_IRQ_FIFOEVENTENABLE 0x01
++#define GPMC_IRQ_COUNT_EVENT 0x02
+
+ /*
+ * Note that all values in this struct are in nanoseconds except sync_clk
+@@ -135,7 +139,6 @@ extern int gpmc_prefetch_enable(int cs, int dma_mode,
+ extern int gpmc_prefetch_reset(int cs);
+ extern void omap3_gpmc_save_context(void);
+ extern void omap3_gpmc_restore_context(void);
+-extern void gpmc_init(void);
+ extern int gpmc_read_status(int cmd);
+ extern int gpmc_cs_configure(int cs, int cmd, int wval);
+ extern int gpmc_nand_read(int cs, int cmd);
+diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
+index 2910de9..1b91168 100644
+--- a/arch/arm/plat-omap/include/plat/irqs.h
++++ b/arch/arm/plat-omap/include/plat/irqs.h
+@@ -318,6 +318,7 @@
+ #define INT_34XX_PRCM_MPU_IRQ 11
+ #define INT_34XX_MCBSP1_IRQ 16
+ #define INT_34XX_MCBSP2_IRQ 17
++#define INT_34XX_GPMC_IRQ 20
+ #define INT_34XX_MCBSP3_IRQ 22
+ #define INT_34XX_MCBSP4_IRQ 23
+ #define INT_34XX_CAM_IRQ 24
+@@ -411,7 +412,13 @@
+ #define TWL_IRQ_END TWL6030_IRQ_END
+ #endif
+
+-#define NR_IRQS TWL_IRQ_END
++/* GPMC related */
++#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
++#define OMAP_GPMC_NR_IRQS 7
++#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
++
++
++#define NR_IRQS OMAP_GPMC_IRQ_END
+
+ #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
+
+--
+1.7.1
+
diff --git a/patches/for_next/0066-omap3-nand-prefetch-in-irq-mode-support.patch b/patches/for_next/0066-omap3-nand-prefetch-in-irq-mode-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..c1ac7553283571dd33b974d52f74e63f8c7d2b48
--- /dev/null
+++ b/patches/for_next/0066-omap3-nand-prefetch-in-irq-mode-support.patch
@@ -0,0 +1,347 @@
+From 39f62835e94858611816c28ba681c8ce92d61e24 Mon Sep 17 00:00:00 2001
+From: Sukumar Ghorai <s-ghorai@ti.com>
+Date: Fri, 28 Jan 2011 15:42:06 +0530
+Subject: [PATCH 066/254] omap3: nand: prefetch in irq mode support
+
+This patch enable prefetch-irq mode for nand transfer(read, write)
+
+Signed-off-by: Vimal Singh <vimalsingh@ti.com>
+Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-flash.c | 2 +
+ arch/arm/plat-omap/include/plat/nand.h | 4 +-
+ drivers/mtd/nand/omap2.c | 198 ++++++++++++++++++++++++++++++--
+ 3 files changed, 194 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
+index f6b7253..1964509 100644
+--- a/arch/arm/mach-omap2/board-flash.c
++++ b/arch/arm/mach-omap2/board-flash.c
+@@ -16,6 +16,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/mtd/physmap.h>
+ #include <linux/io.h>
++#include <plat/irqs.h>
+
+ #include <plat/gpmc.h>
+ #include <plat/nand.h>
+@@ -147,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
+ board_nand_data.nr_parts = nr_parts;
+ board_nand_data.devsize = nand_type;
+
++ board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
+ gpmc_nand_init(&board_nand_data);
+ }
+ #else
+diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
+index 78c0bdb..ae5e053 100644
+--- a/arch/arm/plat-omap/include/plat/nand.h
++++ b/arch/arm/plat-omap/include/plat/nand.h
+@@ -13,7 +13,8 @@
+ enum nand_io {
+ NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */
+ NAND_OMAP_POLLED, /* polled mode, without prefetch */
+- NAND_OMAP_PREFETCH_DMA /* prefetch enabled sDMA mode */
++ NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */
++ NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */
+ };
+
+ struct omap_nand_platform_data {
+@@ -26,6 +27,7 @@ struct omap_nand_platform_data {
+ int (*nand_setup)(void);
+ int (*dev_ready)(struct omap_nand_platform_data *);
+ int dma_channel;
++ int gpmc_irq;
+ enum nand_io xfer_type;
+ unsigned long phys_base;
+ int devsize;
+diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
+index 60bac8e..fbe8414 100644
+--- a/drivers/mtd/nand/omap2.c
++++ b/drivers/mtd/nand/omap2.c
+@@ -11,6 +11,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/delay.h>
++#include <linux/interrupt.h>
+ #include <linux/jiffies.h>
+ #include <linux/sched.h>
+ #include <linux/mtd/mtd.h>
+@@ -24,6 +25,7 @@
+ #include <plat/nand.h>
+
+ #define DRIVER_NAME "omap2-nand"
++#define OMAP_NAND_TIMEOUT_MS 5000
+
+ #define NAND_Ecc_P1e (1 << 0)
+ #define NAND_Ecc_P2e (1 << 1)
+@@ -108,6 +110,13 @@ struct omap_nand_info {
+ unsigned long phys_base;
+ struct completion comp;
+ int dma_ch;
++ int gpmc_irq;
++ enum {
++ OMAP_NAND_IO_READ = 0, /* read */
++ OMAP_NAND_IO_WRITE, /* write */
++ } iomode;
++ u_char *buf;
++ int buf_len;
+ };
+
+ /**
+@@ -267,9 +276,10 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
+ {
+ struct omap_nand_info *info = container_of(mtd,
+ struct omap_nand_info, mtd);
+- uint32_t pref_count = 0, w_count = 0;
++ uint32_t w_count = 0;
+ int i = 0, ret = 0;
+ u16 *p;
++ unsigned long tim, limit;
+
+ /* take care of subpage writes */
+ if (len % 2 != 0) {
+@@ -295,9 +305,12 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
+ iowrite16(*p++, info->nand.IO_ADDR_W);
+ }
+ /* wait for data to flushed-out before reset the prefetch */
+- do {
+- pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT);
+- } while (pref_count);
++ tim = 0;
++ limit = (loops_per_jiffy *
++ msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
++ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
++ cpu_relax();
++
+ /* disable and stop the PFPW engine */
+ gpmc_prefetch_reset(info->gpmc_cs);
+ }
+@@ -326,11 +339,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
+ {
+ struct omap_nand_info *info = container_of(mtd,
+ struct omap_nand_info, mtd);
+- uint32_t prefetch_status = 0;
+ enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
+ DMA_FROM_DEVICE;
+ dma_addr_t dma_addr;
+ int ret;
++ unsigned long tim, limit;
+
+ /* The fifo depth is 64 bytes. We have a sync at each frame and frame
+ * length is 64 bytes.
+@@ -376,7 +389,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
+ /* configure and start prefetch transfer */
+ ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
+ if (ret)
+- /* PFPW engine is busy, use cpu copy methode */
++ /* PFPW engine is busy, use cpu copy method */
+ goto out_copy;
+
+ init_completion(&info->comp);
+@@ -385,10 +398,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
+
+ /* setup and start DMA using dma_addr */
+ wait_for_completion(&info->comp);
++ tim = 0;
++ limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
++ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
++ cpu_relax();
+
+- do {
+- prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT);
+- } while (prefetch_status);
+ /* disable and stop the PFPW engine */
+ gpmc_prefetch_reset(info->gpmc_cs);
+
+@@ -436,6 +450,155 @@ static void omap_write_buf_dma_pref(struct mtd_info *mtd,
+ omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
+ }
+
++/*
++ * omap_nand_irq - GMPC irq handler
++ * @this_irq: gpmc irq number
++ * @dev: omap_nand_info structure pointer is passed here
++ */
++static irqreturn_t omap_nand_irq(int this_irq, void *dev)
++{
++ struct omap_nand_info *info = (struct omap_nand_info *) dev;
++ u32 bytes;
++ u32 irq_stat;
++
++ irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
++ bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
++ bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
++ if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
++ if (irq_stat & 0x2)
++ goto done;
++
++ if (info->buf_len && (info->buf_len < bytes))
++ bytes = info->buf_len;
++ else if (!info->buf_len)
++ bytes = 0;
++ iowrite32_rep(info->nand.IO_ADDR_W,
++ (u32 *)info->buf, bytes >> 2);
++ info->buf = info->buf + bytes;
++ info->buf_len -= bytes;
++
++ } else {
++ ioread32_rep(info->nand.IO_ADDR_R,
++ (u32 *)info->buf, bytes >> 2);
++ info->buf = info->buf + bytes;
++
++ if (irq_stat & 0x2)
++ goto done;
++ }
++ gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
++
++ return IRQ_HANDLED;
++
++done:
++ complete(&info->comp);
++ /* disable irq */
++ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
++
++ /* clear status */
++ gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * omap_read_buf_irq_pref - read data from NAND controller into buffer
++ * @mtd: MTD device structure
++ * @buf: buffer to store date
++ * @len: number of bytes to read
++ */
++static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
++{
++ struct omap_nand_info *info = container_of(mtd,
++ struct omap_nand_info, mtd);
++ int ret = 0;
++
++ if (len <= mtd->oobsize) {
++ omap_read_buf_pref(mtd, buf, len);
++ return;
++ }
++
++ info->iomode = OMAP_NAND_IO_READ;
++ info->buf = buf;
++ init_completion(&info->comp);
++
++ /* configure and start prefetch transfer */
++ ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
++ if (ret)
++ /* PFPW engine is busy, use cpu copy method */
++ goto out_copy;
++
++ info->buf_len = len;
++ /* enable irq */
++ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
++ (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
++
++ /* waiting for read to complete */
++ wait_for_completion(&info->comp);
++
++ /* disable and stop the PFPW engine */
++ gpmc_prefetch_reset(info->gpmc_cs);
++ return;
++
++out_copy:
++ if (info->nand.options & NAND_BUSWIDTH_16)
++ omap_read_buf16(mtd, buf, len);
++ else
++ omap_read_buf8(mtd, buf, len);
++}
++
++/*
++ * omap_write_buf_irq_pref - write buffer to NAND controller
++ * @mtd: MTD device structure
++ * @buf: data buffer
++ * @len: number of bytes to write
++ */
++static void omap_write_buf_irq_pref(struct mtd_info *mtd,
++ const u_char *buf, int len)
++{
++ struct omap_nand_info *info = container_of(mtd,
++ struct omap_nand_info, mtd);
++ int ret = 0;
++ unsigned long tim, limit;
++
++ if (len <= mtd->oobsize) {
++ omap_write_buf_pref(mtd, buf, len);
++ return;
++ }
++
++ info->iomode = OMAP_NAND_IO_WRITE;
++ info->buf = (u_char *) buf;
++ init_completion(&info->comp);
++
++ /* configure and start prefetch transfer */
++ ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
++ if (ret)
++ /* PFPW engine is busy, use cpu copy method */
++ goto out_copy;
++
++ info->buf_len = len;
++ /* enable irq */
++ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
++ (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
++
++ /* waiting for write to complete */
++ wait_for_completion(&info->comp);
++ /* wait for data to flushed-out before reset the prefetch */
++ tim = 0;
++ limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
++ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
++ cpu_relax();
++
++ /* disable and stop the PFPW engine */
++ gpmc_prefetch_reset(info->gpmc_cs);
++ return;
++
++out_copy:
++ if (info->nand.options & NAND_BUSWIDTH_16)
++ omap_write_buf16(mtd, buf, len);
++ else
++ omap_write_buf8(mtd, buf, len);
++}
++
+ /**
+ * omap_verify_buf - Verify chip data against buffer
+ * @mtd: MTD device structure
+@@ -846,6 +1009,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ }
+ break;
+
++ case NAND_OMAP_PREFETCH_IRQ:
++ err = request_irq(pdata->gpmc_irq,
++ omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
++ if (err) {
++ dev_err(&pdev->dev, "requesting irq(%d) error:%d",
++ pdata->gpmc_irq, err);
++ goto out_release_mem_region;
++ } else {
++ info->gpmc_irq = pdata->gpmc_irq;
++ info->nand.read_buf = omap_read_buf_irq_pref;
++ info->nand.write_buf = omap_write_buf_irq_pref;
++ }
++ break;
++
+ default:
+ dev_err(&pdev->dev,
+ "xfer_type(%d) not supported!\n", pdata->xfer_type);
+@@ -911,6 +1088,9 @@ static int omap_nand_remove(struct platform_device *pdev)
+ if (info->dma_ch != -1)
+ omap_free_dma(info->dma_ch);
+
++ if (info->gpmc_irq)
++ free_irq(info->gpmc_irq, info);
++
+ /* Release NAND device, its internal structures and partitions */
+ nand_release(&info->mtd);
+ iounmap(info->nand.IO_ADDR_R);
+--
+1.7.1
+
diff --git a/patches/for_next/0067-omap3-nand-configurable-fifo-threshold-to-gain-the-t.patch b/patches/for_next/0067-omap3-nand-configurable-fifo-threshold-to-gain-the-t.patch
new file mode 100644
index 0000000000000000000000000000000000000000..79daff317df4a890794394573e6b0b9537e066b8
--- /dev/null
+++ b/patches/for_next/0067-omap3-nand-configurable-fifo-threshold-to-gain-the-t.patch
@@ -0,0 +1,154 @@
+From 0bd9a1135bdbba7c09e70d27a50c7a961f7e4bb9 Mon Sep 17 00:00:00 2001
+From: Sukumar Ghorai <s-ghorai@ti.com>
+Date: Fri, 28 Jan 2011 15:42:07 +0530
+Subject: [PATCH 067/254] omap3: nand: configurable fifo threshold to gain the throughput
+
+Configure the FIFO THREASHOLD value different for read and write to keep busy
+both filling and to drain out of FIFO at reading and writing.
+
+Signed-off-by: Vimal Singh <vimalsingh@ti.com>
+Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/gpmc.c | 11 +++++++----
+ arch/arm/plat-omap/include/plat/gpmc.h | 5 ++++-
+ drivers/mtd/nand/omap2.c | 22 ++++++++++++++--------
+ 3 files changed, 25 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
+index 382dea8..6741743 100644
+--- a/arch/arm/mach-omap2/gpmc.c
++++ b/arch/arm/mach-omap2/gpmc.c
+@@ -60,7 +60,6 @@
+ #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
+ #define GPMC_SECTION_SHIFT 28 /* 128 MB */
+
+-#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
+ #define CS_NUM_SHIFT 24
+ #define ENABLE_PREFETCH (0x1 << 7)
+ #define DMA_MPU_MODE 2
+@@ -606,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
+ /**
+ * gpmc_prefetch_enable - configures and starts prefetch transfer
+ * @cs: cs (chip select) number
++ * @fifo_th: fifo threshold to be used for read/ write
+ * @dma_mode: dma mode enable (1) or disable (0)
+ * @u32_count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ */
+-int gpmc_prefetch_enable(int cs, int dma_mode,
++int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
+ unsigned int u32_count, int is_write)
+ {
+
+- if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
++ if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
++ pr_err("gpmc: fifo threshold is not supported\n");
++ return -1;
++ } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
+ /* Set the amount of bytes to be prefetched */
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
+
+@@ -622,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
+ * enable the engine. Set which cs is has requested for.
+ */
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
+- PREFETCH_FIFOTHRESHOLD |
++ PREFETCH_FIFOTHRESHOLD(fifo_th) |
+ ENABLE_PREFETCH |
+ (dma_mode << DMA_MPU_MODE) |
+ (0x1 & is_write)));
+diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
+index 9c060da..a243463 100644
+--- a/arch/arm/plat-omap/include/plat/gpmc.h
++++ b/arch/arm/plat-omap/include/plat/gpmc.h
+@@ -83,6 +83,9 @@
+ #define GPMC_IRQ_FIFOEVENTENABLE 0x01
+ #define GPMC_IRQ_COUNT_EVENT 0x02
+
++#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
++#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
++
+ /*
+ * Note that all values in this struct are in nanoseconds except sync_clk
+ * (which is in picoseconds), while the register values are in gpmc_fck cycles.
+@@ -134,7 +137,7 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
+ extern void gpmc_cs_free(int cs);
+ extern int gpmc_cs_set_reserved(int cs, int reserved);
+ extern int gpmc_cs_reserved(int cs);
+-extern int gpmc_prefetch_enable(int cs, int dma_mode,
++extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
+ unsigned int u32_count, int is_write);
+ extern int gpmc_prefetch_reset(int cs);
+ extern void omap3_gpmc_save_context(void);
+diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
+index fbe8414..f1648fd 100644
+--- a/drivers/mtd/nand/omap2.c
++++ b/drivers/mtd/nand/omap2.c
+@@ -244,7 +244,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
+ }
+
+ /* configure and start prefetch transfer */
+- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
++ ret = gpmc_prefetch_enable(info->gpmc_cs,
++ PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
+ if (ret) {
+ /* PFPW engine is busy, use cpu copy method */
+ if (info->nand.options & NAND_BUSWIDTH_16)
+@@ -289,7 +290,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
+ }
+
+ /* configure and start prefetch transfer */
+- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
++ ret = gpmc_prefetch_enable(info->gpmc_cs,
++ PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
+ if (ret) {
+ /* PFPW engine is busy, use cpu copy method */
+ if (info->nand.options & NAND_BUSWIDTH_16)
+@@ -345,8 +347,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
+ int ret;
+ unsigned long tim, limit;
+
+- /* The fifo depth is 64 bytes. We have a sync at each frame and frame
+- * length is 64 bytes.
++ /* The fifo depth is 64 bytes max.
++ * But configure the FIFO-threahold to 32 to get a sync at each frame
++ * and frame length is 32 bytes.
+ */
+ int buf_len = len >> 6;
+
+@@ -387,7 +390,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
+ OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
+ }
+ /* configure and start prefetch transfer */
+- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
++ ret = gpmc_prefetch_enable(info->gpmc_cs,
++ PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
+ if (ret)
+ /* PFPW engine is busy, use cpu copy method */
+ goto out_copy;
+@@ -522,7 +526,8 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
+ init_completion(&info->comp);
+
+ /* configure and start prefetch transfer */
+- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
++ ret = gpmc_prefetch_enable(info->gpmc_cs,
++ PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
+ if (ret)
+ /* PFPW engine is busy, use cpu copy method */
+ goto out_copy;
+@@ -569,8 +574,9 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
+ info->buf = (u_char *) buf;
+ init_completion(&info->comp);
+
+- /* configure and start prefetch transfer */
+- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
++ /* configure and start prefetch transfer : size=24 */
++ ret = gpmc_prefetch_enable(info->gpmc_cs,
++ (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
+ if (ret)
+ /* PFPW engine is busy, use cpu copy method */
+ goto out_copy;
+--
+1.7.1
+
diff --git a/patches/for_next/0068-omap3-nand-ecc-layout-select-from-board-file.patch b/patches/for_next/0068-omap3-nand-ecc-layout-select-from-board-file.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7de4346d31e3765fe09e68142be7d9ebb27ec0e2
--- /dev/null
+++ b/patches/for_next/0068-omap3-nand-ecc-layout-select-from-board-file.patch
@@ -0,0 +1,121 @@
+From 2fc831d401d179b6617e7a970e3f75d3acdb4a57 Mon Sep 17 00:00:00 2001
+From: Sukumar Ghorai <s-ghorai@ti.com>
+Date: Fri, 28 Jan 2011 15:42:08 +0530
+Subject: [PATCH 068/254] omap3: nand: ecc layout select from board file
+
+This patch makes it possible to select sw or hw (different layout options)
+ecc scheme supported by omap nand driver.
+
+Signed-off-by: Vimal Singh <vimalsingh@ti.com>
+Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-flash.c | 1 +
+ arch/arm/plat-omap/include/plat/gpmc.h | 6 ++++++
+ arch/arm/plat-omap/include/plat/nand.h | 2 ++
+ drivers/mtd/nand/omap2.c | 26 +++++++++++---------------
+ 4 files changed, 20 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
+index 1964509..a768198 100644
+--- a/arch/arm/mach-omap2/board-flash.c
++++ b/arch/arm/mach-omap2/board-flash.c
+@@ -148,6 +148,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
+ board_nand_data.nr_parts = nr_parts;
+ board_nand_data.devsize = nand_type;
+
++ board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
+ board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
+ gpmc_nand_init(&board_nand_data);
+ }
+diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
+index a243463..773351b 100644
+--- a/arch/arm/plat-omap/include/plat/gpmc.h
++++ b/arch/arm/plat-omap/include/plat/gpmc.h
+@@ -86,6 +86,12 @@
+ #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
+ #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
+
++enum omap_ecc {
++ /* 1-bit ecc: stored at end of spare area */
++ OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
++ OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
++};
++
+ /*
+ * Note that all values in this struct are in nanoseconds except sync_clk
+ * (which is in picoseconds), while the register values are in gpmc_fck cycles.
+diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
+index ae5e053..d86d1ec 100644
+--- a/arch/arm/plat-omap/include/plat/nand.h
++++ b/arch/arm/plat-omap/include/plat/nand.h
+@@ -8,6 +8,7 @@
+ * published by the Free Software Foundation.
+ */
+
++#include <plat/gpmc.h>
+ #include <linux/mtd/partitions.h>
+
+ enum nand_io {
+@@ -31,6 +32,7 @@ struct omap_nand_platform_data {
+ enum nand_io xfer_type;
+ unsigned long phys_base;
+ int devsize;
++ enum omap_ecc ecc_opt;
+ };
+
+ /* minimum size for IO mapping */
+diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
+index f1648fd..6d4a42e 100644
+--- a/drivers/mtd/nand/omap2.c
++++ b/drivers/mtd/nand/omap2.c
+@@ -626,8 +626,6 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+ return 0;
+ }
+
+-#ifdef CONFIG_MTD_NAND_OMAP_HWECC
+-
+ /**
+ * gen_true_ecc - This function will generate true ECC value
+ * @ecc_buf: buffer to store ecc code
+@@ -847,8 +845,6 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
+ gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
+ }
+
+-#endif
+-
+ /**
+ * omap_wait - wait until the command is done
+ * @mtd: MTD device structure
+@@ -1038,17 +1034,17 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+
+ info->nand.verify_buf = omap_verify_buf;
+
+-#ifdef CONFIG_MTD_NAND_OMAP_HWECC
+- info->nand.ecc.bytes = 3;
+- info->nand.ecc.size = 512;
+- info->nand.ecc.calculate = omap_calculate_ecc;
+- info->nand.ecc.hwctl = omap_enable_hwecc;
+- info->nand.ecc.correct = omap_correct_data;
+- info->nand.ecc.mode = NAND_ECC_HW;
+-
+-#else
+- info->nand.ecc.mode = NAND_ECC_SOFT;
+-#endif
++ /* selsect the ecc type */
++ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
++ info->nand.ecc.mode = NAND_ECC_SOFT;
++ else if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) {
++ info->nand.ecc.bytes = 3;
++ info->nand.ecc.size = 512;
++ info->nand.ecc.calculate = omap_calculate_ecc;
++ info->nand.ecc.hwctl = omap_enable_hwecc;
++ info->nand.ecc.correct = omap_correct_data;
++ info->nand.ecc.mode = NAND_ECC_HW;
++ }
+
+ /* DIP switches on some boards change between 8 and 16 bit
+ * bus widths for flash. Try the other width if the first try fails.
+--
+1.7.1
+
diff --git a/patches/for_next/0069-omap3-nand-making-ecc-layout-as-compatible-with-romc.patch b/patches/for_next/0069-omap3-nand-making-ecc-layout-as-compatible-with-romc.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3da67f0ce7920b985cd806a8b56d025483a9d578
--- /dev/null
+++ b/patches/for_next/0069-omap3-nand-making-ecc-layout-as-compatible-with-romc.patch
@@ -0,0 +1,108 @@
+From 7824c8996fa3b26a9d14f2c3bdfb049b874a1f50 Mon Sep 17 00:00:00 2001
+From: Sukumar Ghorai <s-ghorai@ti.com>
+Date: Fri, 28 Jan 2011 15:42:09 +0530
+Subject: [PATCH 069/254] omap3: nand: making ecc layout as compatible with romcode ecc
+
+This patch overrides nand ecc layout and bad block descriptor (for 8-bit
+device) to support hw ecc in romcode layout. So as to have in sync with ecc
+layout throughout; i.e. x-loader, u-boot and kernel.
+
+This enables to flash x-loader, u-boot, kernel, FS images from kernel itself
+and compatiable with other tools.
+
+This patch does not enables this feature by default and need to pass from
+board file to enable for any board.
+
+Signed-off-by: Vimal Singh <vimalsingh@ti.com>
+Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/gpmc.h | 2 +
+ drivers/mtd/nand/omap2.c | 37 +++++++++++++++++++++++++++++++-
+ 2 files changed, 38 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
+index 773351b..12b3161 100644
+--- a/arch/arm/plat-omap/include/plat/gpmc.h
++++ b/arch/arm/plat-omap/include/plat/gpmc.h
+@@ -90,6 +90,8 @@ enum omap_ecc {
+ /* 1-bit ecc: stored at end of spare area */
+ OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
+ OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
++ /* 1-bit ecc: stored at begining of spare area as romcode */
++ OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
+ };
+
+ /*
+diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
+index 6d4a42e..4e33972 100644
+--- a/drivers/mtd/nand/omap2.c
++++ b/drivers/mtd/nand/omap2.c
+@@ -98,6 +98,20 @@
+ static const char *part_probes[] = { "cmdlinepart", NULL };
+ #endif
+
++/* oob info generated runtime depending on ecc algorithm and layout selected */
++static struct nand_ecclayout omap_oobinfo;
++/* Define some generic bad / good block scan pattern which are used
++ * while scanning a device for factory marked good / bad blocks
++ */
++static uint8_t scan_ff_pattern[] = { 0xff };
++static struct nand_bbt_descr bb_descrip_flashbased = {
++ .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
++ .offs = 0,
++ .len = 1,
++ .pattern = scan_ff_pattern,
++};
++
++
+ struct omap_nand_info {
+ struct nand_hw_control controller;
+ struct omap_nand_platform_data *pdata;
+@@ -914,6 +928,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ struct omap_nand_info *info;
+ struct omap_nand_platform_data *pdata;
+ int err;
++ int i, offset;
+
+ pdata = pdev->dev.platform_data;
+ if (pdata == NULL) {
+@@ -1037,7 +1052,8 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ /* selsect the ecc type */
+ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
+ info->nand.ecc.mode = NAND_ECC_SOFT;
+- else if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) {
++ else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
++ (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
+ info->nand.ecc.bytes = 3;
+ info->nand.ecc.size = 512;
+ info->nand.ecc.calculate = omap_calculate_ecc;
+@@ -1057,6 +1073,25 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ }
+ }
+
++ /* rom code layout */
++ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
++
++ if (info->nand.options & NAND_BUSWIDTH_16)
++ offset = 2;
++ else {
++ offset = 1;
++ info->nand.badblock_pattern = &bb_descrip_flashbased;
++ }
++ omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
++ for (i = 0; i < omap_oobinfo.eccbytes; i++)
++ omap_oobinfo.eccpos[i] = i+offset;
++
++ omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
++ omap_oobinfo.oobfree->length = info->mtd.oobsize -
++ (offset + omap_oobinfo.eccbytes);
++
++ info->nand.ecc.layout = &omap_oobinfo;
++ }
+
+ #ifdef CONFIG_MTD_PARTITIONS
+ err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
+--
+1.7.1
+
diff --git a/patches/for_next/0070-omap3sdp-Fix-regulator-mapping-for-ads7846-TS-contro.patch b/patches/for_next/0070-omap3sdp-Fix-regulator-mapping-for-ads7846-TS-contro.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e9c8e695fff6af8ae294ed8bee2e3c7035a20a2b
--- /dev/null
+++ b/patches/for_next/0070-omap3sdp-Fix-regulator-mapping-for-ads7846-TS-contro.patch
@@ -0,0 +1,47 @@
+From b0a86ce7993b1b0159bb6f6fc63c1a2bcf5095db Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Thu, 3 Feb 2011 12:45:21 +0000
+Subject: [PATCH 070/254] omap3sdp: Fix regulator mapping for ads7846 TS controller
+
+On the OMAP3430SDP board, the ads7846 touchscreen controller
+is powered by VAUX3 regulator (supplying 2.8v).
+Fix this mapping in the board file, and hence prevent
+the ads7846 driver init to fail with the below error..
+
+ads7846 spi1.0: unable to get regulator: -19
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 4a37c70..3e905da 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -426,6 +426,11 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = {
+ .irq_line = 1,
+ };
+
++/* ads7846 on SPI */
++static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
++ REGULATOR_SUPPLY("vcc", "spi1.0"),
++};
++
+ /*
+ * Apply all the fixed voltages since most versions of U-Boot
+ * don't bother with that initialization.
+@@ -468,6 +473,8 @@ static struct regulator_init_data sdp3430_vaux3 = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
++ .consumer_supplies = sdp3430_vaux3_supplies,
+ };
+
+ /* VAUX4 for OMAP VDD_CSI2 (camera) */
+--
+1.7.1
+
diff --git a/patches/for_next/0071-OMAP-OneNAND-fix-104MHz-support.patch b/patches/for_next/0071-OMAP-OneNAND-fix-104MHz-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3a264166d5b8098593cdffc0a2781a89dc25f3b9
--- /dev/null
+++ b/patches/for_next/0071-OMAP-OneNAND-fix-104MHz-support.patch
@@ -0,0 +1,115 @@
+From ee2cebd52681f5dca926c8a74fa76909f7727c2d Mon Sep 17 00:00:00 2001
+From: Adrian Hunter <adrian.hunter@nokia.com>
+Date: Mon, 7 Feb 2011 10:46:58 +0200
+Subject: [PATCH 071/254] OMAP: OneNAND: fix 104MHz support
+
+104MHz needs a latency of 8 clock cycles and the VHF
+flag must be set. Also t_rdyo is specified as
+"not applicable" so pick a lower value, and force at
+least 1 clk between AVD High to OE Low.
+
+Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/gpmc-onenand.c | 23 +++++++++++++++++------
+ include/linux/mtd/onenand_regs.h | 1 +
+ 2 files changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
+index 3a7d25f..3a4307b 100644
+--- a/arch/arm/mach-omap2/gpmc-onenand.c
++++ b/arch/arm/mach-omap2/gpmc-onenand.c
+@@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
+ }
+
+ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
+- int sync_read, int sync_write, int hf)
++ int sync_read, int sync_write, int hf, int vhf)
+ {
+ u32 reg;
+
+@@ -114,6 +114,10 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
+ reg |= ONENAND_SYS_CFG1_HF;
+ else
+ reg &= ~ONENAND_SYS_CFG1_HF;
++ if (vhf)
++ reg |= ONENAND_SYS_CFG1_VHF;
++ else
++ reg &= ~ONENAND_SYS_CFG1_VHF;
+ writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+ }
+
+@@ -130,7 +134,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ const int t_wph = 30;
+ int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
+ int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+- int first_time = 0, hf = 0, sync_read = 0, sync_write = 0;
++ int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
+ int err, ticks_cez;
+ int cs = cfg->cs;
+ u32 reg;
+@@ -180,7 +184,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ t_avdh = 2;
+ t_ach = 3;
+ t_aavdh = 6;
+- t_rdyo = 9;
++ t_rdyo = 6;
+ break;
+ case 83:
+ min_gpmc_clk_period = 12000; /* 83 MHz */
+@@ -217,7 +221,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ gpmc_clk_ns = gpmc_ticks_to_ns(div);
+ if (gpmc_clk_ns < 15) /* >66Mhz */
+ hf = 1;
+- if (hf)
++ if (gpmc_clk_ns < 12) /* >83Mhz */
++ vhf = 1;
++ if (vhf)
++ latency = 8;
++ else if (hf)
+ latency = 6;
+ else if (gpmc_clk_ns >= 25) /* 40 MHz*/
+ latency = 3;
+@@ -226,7 +234,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+
+ if (first_time)
+ set_onenand_cfg(onenand_base, latency,
+- sync_read, sync_write, hf);
++ sync_read, sync_write, hf, vhf);
+
+ if (div == 1) {
+ reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
+@@ -264,6 +272,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ /* Read */
+ t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
+ t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
++ /* Force at least 1 clk between AVD High to OE Low */
++ if (t.oe_on <= t.adv_rd_off)
++ t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
+ t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
+ t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
+ t.cs_rd_off = t.oe_off;
+@@ -317,7 +328,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ if (err)
+ return err;
+
+- set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
++ set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+
+ return 0;
+ }
+diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
+index cd6f3b4..d60130f 100644
+--- a/include/linux/mtd/onenand_regs.h
++++ b/include/linux/mtd/onenand_regs.h
+@@ -168,6 +168,7 @@
+ #define ONENAND_SYS_CFG1_INT (1 << 6)
+ #define ONENAND_SYS_CFG1_IOBE (1 << 5)
+ #define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
++#define ONENAND_SYS_CFG1_VHF (1 << 3)
+ #define ONENAND_SYS_CFG1_HF (1 << 2)
+ #define ONENAND_SYS_CFG1_SYNC_WRITE (1 << 1)
+
+--
+1.7.1
+
diff --git a/patches/for_next/0072-OMAP-OneNAND-determine-frequency-in-one-place.patch b/patches/for_next/0072-OMAP-OneNAND-determine-frequency-in-one-place.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b510dfeee65bc6f9d408fd1a96221d2e2b7029c4
--- /dev/null
+++ b/patches/for_next/0072-OMAP-OneNAND-determine-frequency-in-one-place.patch
@@ -0,0 +1,143 @@
+From 852f858f1bb5d440dd2bb060aad4d478547664cf Mon Sep 17 00:00:00 2001
+From: Adrian Hunter <adrian.hunter@nokia.com>
+Date: Mon, 7 Feb 2011 10:46:59 +0200
+Subject: [PATCH 072/254] OMAP: OneNAND: determine frequency in one place
+
+OneNAND frequency is determined when calculating
+GPMC timings. Return that value instead of determining it
+again in the OMAP OneNAND driver.
+
+Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/gpmc-onenand.c | 10 ++++++----
+ arch/arm/plat-omap/include/plat/onenand.h | 2 +-
+ drivers/mtd/onenand/omap2.c | 28 +++++-----------------------
+ 3 files changed, 12 insertions(+), 28 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
+index 3a4307b..46786a6 100644
+--- a/arch/arm/mach-omap2/gpmc-onenand.c
++++ b/arch/arm/mach-omap2/gpmc-onenand.c
+@@ -123,7 +123,7 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
+
+ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ void __iomem *onenand_base,
+- int freq)
++ int *freq_ptr)
+ {
+ struct gpmc_timings t;
+ const int t_cer = 15;
+@@ -136,7 +136,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+ int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
+ int err, ticks_cez;
+- int cs = cfg->cs;
++ int cs = cfg->cs, freq = *freq_ptr;
+ u32 reg;
+
+ if (cfg->flags & ONENAND_SYNC_READ) {
+@@ -330,16 +330,18 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+
+ set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+
++ *freq_ptr = freq;
++
+ return 0;
+ }
+
+-static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
++static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
+ {
+ struct device *dev = &gpmc_onenand_device.dev;
+
+ /* Set sync timings in GPMC */
+ if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
+- freq) < 0) {
++ freq_ptr) < 0) {
+ dev_err(dev, "Unable to set synchronous mode\n");
+ return -EINVAL;
+ }
+diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
+index affe87e..86118dc 100644
+--- a/arch/arm/plat-omap/include/plat/onenand.h
++++ b/arch/arm/plat-omap/include/plat/onenand.h
+@@ -20,7 +20,7 @@ struct omap_onenand_platform_data {
+ int gpio_irq;
+ struct mtd_partition *parts;
+ int nr_parts;
+- int (*onenand_setup)(void __iomem *, int freq);
++ int (*onenand_setup)(void __iomem *, int *freq_ptr);
+ int dma_channel;
+ u8 flags;
+ u8 regulator_can_sleep;
+diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
+index ac31f46..3e1bb95 100644
+--- a/drivers/mtd/onenand/omap2.c
++++ b/drivers/mtd/onenand/omap2.c
+@@ -63,7 +63,7 @@ struct omap2_onenand {
+ struct completion dma_done;
+ int dma_channel;
+ int freq;
+- int (*setup)(void __iomem *base, int freq);
++ int (*setup)(void __iomem *base, int *freq_ptr);
+ struct regulator *regulator;
+ };
+
+@@ -581,7 +581,7 @@ static int __adjust_timing(struct device *dev, void *data)
+
+ /* DMA is not in use so this is all that is needed */
+ /* Revisit for OMAP3! */
+- ret = c->setup(c->onenand.base, c->freq);
++ ret = c->setup(c->onenand.base, &c->freq);
+
+ return ret;
+ }
+@@ -673,7 +673,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
+ }
+
+ if (pdata->onenand_setup != NULL) {
+- r = pdata->onenand_setup(c->onenand.base, c->freq);
++ r = pdata->onenand_setup(c->onenand.base, &c->freq);
+ if (r < 0) {
+ dev_err(&pdev->dev, "Onenand platform setup failed: "
+ "%d\n", r);
+@@ -718,8 +718,8 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
+ }
+
+ dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
+- "base %p\n", c->gpmc_cs, c->phys_base,
+- c->onenand.base);
++ "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
++ c->onenand.base, c->freq);
+
+ c->pdev = pdev;
+ c->mtd.name = dev_name(&pdev->dev);
+@@ -754,24 +754,6 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
+ if ((r = onenand_scan(&c->mtd, 1)) < 0)
+ goto err_release_regulator;
+
+- switch ((c->onenand.version_id >> 4) & 0xf) {
+- case 0:
+- c->freq = 40;
+- break;
+- case 1:
+- c->freq = 54;
+- break;
+- case 2:
+- c->freq = 66;
+- break;
+- case 3:
+- c->freq = 83;
+- break;
+- case 4:
+- c->freq = 104;
+- break;
+- }
+-
+ #ifdef CONFIG_MTD_PARTITIONS
+ r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0);
+ if (r > 0)
+--
+1.7.1
+
diff --git a/patches/for_next/0073-OMAP-OneNAND-let-boards-determine-OneNAND-frequency.patch b/patches/for_next/0073-OMAP-OneNAND-let-boards-determine-OneNAND-frequency.patch
new file mode 100644
index 0000000000000000000000000000000000000000..fe08fa248cbc25e5e855b6f9f2a9cb6991729d2c
--- /dev/null
+++ b/patches/for_next/0073-OMAP-OneNAND-let-boards-determine-OneNAND-frequency.patch
@@ -0,0 +1,156 @@
+From a5fead8e7ef1e1d25895198db43b9c6ce59e4386 Mon Sep 17 00:00:00 2001
+From: Adrian Hunter <adrian.hunter@nokia.com>
+Date: Mon, 7 Feb 2011 10:47:00 +0200
+Subject: [PATCH 073/254] OMAP: OneNAND: let boards determine OneNAND frequency
+
+OneNAND version ID may not give the highest frequency
+supported and some OneNAND's have setup times that are
+clock dependent. Let the board provide that information.
+
+Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/gpmc-onenand.c | 80 +++++++++++++++++++++--------
+ arch/arm/plat-omap/include/plat/onenand.h | 8 +++
+ 2 files changed, 67 insertions(+), 21 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
+index 46786a6..d776ded 100644
+--- a/arch/arm/mach-omap2/gpmc-onenand.c
++++ b/arch/arm/mach-omap2/gpmc-onenand.c
+@@ -121,6 +121,47 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
+ writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+ }
+
++static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
++ void __iomem *onenand_base, bool *clk_dep)
++{
++ u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
++ int freq = 0;
++
++ if (cfg->get_freq) {
++ struct onenand_freq_info fi;
++
++ fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
++ fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
++ fi.ver_id = ver;
++ freq = cfg->get_freq(&fi, clk_dep);
++ if (freq)
++ return freq;
++ }
++
++ switch ((ver >> 4) & 0xf) {
++ case 0:
++ freq = 40;
++ break;
++ case 1:
++ freq = 54;
++ break;
++ case 2:
++ freq = 66;
++ break;
++ case 3:
++ freq = 83;
++ break;
++ case 4:
++ freq = 104;
++ break;
++ default:
++ freq = 54;
++ break;
++ }
++
++ return freq;
++}
++
+ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ void __iomem *onenand_base,
+ int *freq_ptr)
+@@ -138,6 +179,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ int err, ticks_cez;
+ int cs = cfg->cs, freq = *freq_ptr;
+ u32 reg;
++ bool clk_dep = false;
+
+ if (cfg->flags & ONENAND_SYNC_READ) {
+ sync_read = 1;
+@@ -152,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ err = omap2_onenand_set_async_mode(cs, onenand_base);
+ if (err)
+ return err;
+- reg = readw(onenand_base + ONENAND_REG_VERSION_ID);
+- switch ((reg >> 4) & 0xf) {
+- case 0:
+- freq = 40;
+- break;
+- case 1:
+- freq = 54;
+- break;
+- case 2:
+- freq = 66;
+- break;
+- case 3:
+- freq = 83;
+- break;
+- case 4:
+- freq = 104;
+- break;
+- default:
+- freq = 54;
+- break;
+- }
++ freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
+ first_time = 1;
+ }
+
+@@ -232,6 +254,22 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
+ else
+ latency = 4;
+
++ if (clk_dep) {
++ if (gpmc_clk_ns < 12) { /* >83Mhz */
++ t_ces = 3;
++ t_avds = 4;
++ } else if (gpmc_clk_ns < 15) { /* >66Mhz */
++ t_ces = 5;
++ t_avds = 4;
++ } else if (gpmc_clk_ns < 25) { /* >40Mhz */
++ t_ces = 6;
++ t_avds = 5;
++ } else {
++ t_ces = 7;
++ t_avds = 7;
++ }
++ }
++
+ if (first_time)
+ set_onenand_cfg(onenand_base, latency,
+ sync_read, sync_write, hf, vhf);
+diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
+index 86118dc..cbe897c 100644
+--- a/arch/arm/plat-omap/include/plat/onenand.h
++++ b/arch/arm/plat-omap/include/plat/onenand.h
+@@ -15,12 +15,20 @@
+ #define ONENAND_SYNC_READ (1 << 0)
+ #define ONENAND_SYNC_READWRITE (1 << 1)
+
++struct onenand_freq_info {
++ u16 maf_id;
++ u16 dev_id;
++ u16 ver_id;
++};
++
+ struct omap_onenand_platform_data {
+ int cs;
+ int gpio_irq;
+ struct mtd_partition *parts;
+ int nr_parts;
+ int (*onenand_setup)(void __iomem *, int *freq_ptr);
++ int (*get_freq)(const struct onenand_freq_info *freq_info,
++ bool *clk_dep);
+ int dma_channel;
+ u8 flags;
+ u8 regulator_can_sleep;
+--
+1.7.1
+
diff --git a/patches/for_next/0074-mtd-OneNAND-OMAP2-increase-multiblock-erase-verify-t.patch b/patches/for_next/0074-mtd-OneNAND-OMAP2-increase-multiblock-erase-verify-t.patch
new file mode 100644
index 0000000000000000000000000000000000000000..deed82b8eed2f1899d8c3a0c3b7b8e18c9428e97
--- /dev/null
+++ b/patches/for_next/0074-mtd-OneNAND-OMAP2-increase-multiblock-erase-verify-t.patch
@@ -0,0 +1,43 @@
+From cf13f58b7290fa97210027302dd6c6ba349ad165 Mon Sep 17 00:00:00 2001
+From: Roman Tereshonkov <roman.tereshonkov@nokia.com>
+Date: Mon, 7 Feb 2011 10:47:01 +0200
+Subject: [PATCH 074/254] mtd: OneNAND: OMAP2: increase multiblock erase verify timeout
+
+The current multiblock erase verify read timeout 100us is the maximum
+for none-error case. If errors happen during multibock erase then
+the specification recommends to run multiblock erase verify command
+with maximum timeout 10ms (see specs. for KFM4G16Q2A and KFN8G16Q2A).
+
+For the most common non-error case we wait 100us in udelay polling
+loop. In case of timeout the interrupt mode is used to wait for the
+command end.
+
+Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com>
+Acked-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ drivers/mtd/onenand/omap2.c | 8 +++-----
+ 1 files changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
+index 3e1bb95..ec26399 100644
+--- a/drivers/mtd/onenand/omap2.c
++++ b/drivers/mtd/onenand/omap2.c
+@@ -148,11 +148,9 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
+ wait_err("controller error", state, ctrl, intr);
+ return -EIO;
+ }
+- if ((intr & intr_flags) != intr_flags) {
+- wait_err("timeout", state, ctrl, intr);
+- return -EIO;
+- }
+- return 0;
++ if ((intr & intr_flags) == intr_flags)
++ return 0;
++ /* Continue in wait for interrupt branch */
+ }
+
+ if (state != FL_READING) {
+--
+1.7.1
+
diff --git a/patches/for_next/0075-omap-IOMMU-add-missing-function-declaration.patch b/patches/for_next/0075-omap-IOMMU-add-missing-function-declaration.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b0e9544b7c71b1ed95dad063f4b18f01239a7539
--- /dev/null
+++ b/patches/for_next/0075-omap-IOMMU-add-missing-function-declaration.patch
@@ -0,0 +1,32 @@
+From 809e677a02ce4ef53f5bfd8c24db68eeefc752b6 Mon Sep 17 00:00:00 2001
+From: David Cohen <dacohen@gmail.com>
+Date: Tue, 15 Feb 2011 11:31:13 +0000
+Subject: [PATCH 075/254] omap: IOMMU: add missing function declaration
+
+Declaration of exported function 'iopgtable_lookup_entry' is missing from
+header file. Currently we have a sparse warning as it's not being used
+externally. Adding its declaration to avoid such warning and allow its usage
+in future.
+
+Signed-off-by: David Cohen <dacohen@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/iommu.h | 2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
+index 69230d6..19cbb5e 100644
+--- a/arch/arm/plat-omap/include/plat/iommu.h
++++ b/arch/arm/plat-omap/include/plat/iommu.h
+@@ -154,6 +154,8 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
+ extern void flush_iotlb_all(struct iommu *obj);
+
+ extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
++extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
++ u32 **ppte);
+ extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
+
+ extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
+--
+1.7.1
+
diff --git a/patches/for_next/0076-omap3-fix-minor-typos.patch b/patches/for_next/0076-omap3-fix-minor-typos.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f5ce60669fa252500596b23bca0d72c6aa1619f4
--- /dev/null
+++ b/patches/for_next/0076-omap3-fix-minor-typos.patch
@@ -0,0 +1,37 @@
+From 9a3679ec38cba23ab5774d52ffca739188ec9c51 Mon Sep 17 00:00:00 2001
+From: Sanjeev Premi <premi@ti.com>
+Date: Tue, 15 Feb 2011 10:57:31 +0000
+Subject: [PATCH 076/254] omap3: fix minor typos
+
+This patch fixes typos that were remaining after
+the file and functions were renamed.
+
+Signed-off-by: Sanjeev Premi <premi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-flash.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
+index a768198..32e353f 100644
+--- a/arch/arm/mach-omap2/board-flash.c
++++ b/arch/arm/mach-omap2/board-flash.c
+@@ -1,5 +1,5 @@
+ /*
+- * board-sdp-flash.c
++ * board-flash.c
+ * Modified from mach-omap2/board-3430sdp-flash.c
+ *
+ * Copyright (C) 2009 Nokia Corporation
+@@ -194,7 +194,7 @@ unmap:
+ }
+
+ /**
+- * sdp3430_flash_init - Identify devices connected to GPMC and register.
++ * board_flash_init - Identify devices connected to GPMC and register.
+ *
+ * @return - void.
+ */
+--
+1.7.1
+
diff --git a/patches/for_next/0077-omap3-flash-use-pr_err-instead-of-printk.patch b/patches/for_next/0077-omap3-flash-use-pr_err-instead-of-printk.patch
new file mode 100644
index 0000000000000000000000000000000000000000..381f0d9c928986b48c600ee17ee7c74957f392cb
--- /dev/null
+++ b/patches/for_next/0077-omap3-flash-use-pr_err-instead-of-printk.patch
@@ -0,0 +1,71 @@
+From 137e1c6a6fc4027b696fb076af972a4c890e5476 Mon Sep 17 00:00:00 2001
+From: Sanjeev Premi <premi@ti.com>
+Date: Tue, 15 Feb 2011 10:57:32 +0000
+Subject: [PATCH 077/254] omap3: flash: use pr_err instead of printk
+
+Change all occurences of printf() to pr_err().
+Includes minor formatting changes as result of
+this change.
+
+Signed-off-by: Sanjeev Premi <premi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-flash.c | 15 ++++++---------
+ 1 files changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
+index 32e353f..c32c068 100644
+--- a/arch/arm/mach-omap2/board-flash.c
++++ b/arch/arm/mach-omap2/board-flash.c
+@@ -74,11 +74,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
+ + FLASH_SIZE_SDPV1 - 1;
+ }
+ if (err < 0) {
+- printk(KERN_ERR "NOR: Can't request GPMC CS\n");
++ pr_err("NOR: Can't request GPMC CS\n");
+ return;
+ }
+ if (platform_device_register(&board_nor_device) < 0)
+- printk(KERN_ERR "Unable to register NOR device\n");
++ pr_err("Unable to register NOR device\n");
+ }
+
+ #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+@@ -213,7 +213,7 @@ void board_flash_init(struct flash_partitions partition_info[],
+ */
+ idx = get_gpmc0_type();
+ if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
+- printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
++ pr_err("%s: Invalid chip select: %d\n", __func__, cs);
+ return;
+ }
+ config_sel = (unsigned char *)(chip_sel_board[idx]);
+@@ -237,22 +237,19 @@ void board_flash_init(struct flash_partitions partition_info[],
+ }
+
+ if (norcs > GPMC_CS_NUM)
+- printk(KERN_INFO "NOR: Unable to find configuration "
+- "in GPMC\n");
++ pr_err("NOR: Unable to find configuration in GPMC\n");
+ else
+ board_nor_init(partition_info[0].parts,
+ partition_info[0].nr_parts, norcs);
+
+ if (onenandcs > GPMC_CS_NUM)
+- printk(KERN_INFO "OneNAND: Unable to find configuration "
+- "in GPMC\n");
++ pr_err("OneNAND: Unable to find configuration in GPMC\n");
+ else
+ board_onenand_init(partition_info[1].parts,
+ partition_info[1].nr_parts, onenandcs);
+
+ if (nandcs > GPMC_CS_NUM)
+- printk(KERN_INFO "NAND: Unable to find configuration "
+- "in GPMC\n");
++ pr_err("NAND: Unable to find configuration in GPMC\n");
+ else
+ board_nand_init(partition_info[2].parts,
+ partition_info[2].nr_parts, nandcs, nand_type);
+--
+1.7.1
+
diff --git a/patches/for_next/0078-omap-Add-chip-id-recognition-for-OMAP4-ES2.1-and-ES2.patch b/patches/for_next/0078-omap-Add-chip-id-recognition-for-OMAP4-ES2.1-and-ES2.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8c5fe6840fb753800281bc360341d7b92705276b
--- /dev/null
+++ b/patches/for_next/0078-omap-Add-chip-id-recognition-for-OMAP4-ES2.1-and-ES2.patch
@@ -0,0 +1,141 @@
+From 5ff21a5fbdbf4b79dec0d194fe532ffc2cc8af6f Mon Sep 17 00:00:00 2001
+From: Nishant Kamat <nskamat@ti.com>
+Date: Thu, 17 Feb 2011 09:55:03 -0800
+Subject: [PATCH 078/254] omap: Add chip id recognition for OMAP4 ES2.1 and ES2.2
+
+Allow OMAP4 ES2.1 and ES2.2 revisions to be recognized in the
+omap4_check_revision() function.
+
+Mainly, ES2.1 has fixes that allow LPDDR to be used at 100% OPP (400MHz).
+ES2.2 additionally has a couple of power management fixes (to reduce
+leakage), an I2C1 SDA line state fix, and a floating point write
+corruption fix (cortex erratum).
+
+Even though the current mainline support doesn't need to distinguish
+between ES2.X versions, it's still useful to know the correct silicon
+rev when issues are reported. Moreover, these id checks can be used by
+power management code that selects suitable OPPs considering the
+memory speed limitation on ES2.0.
+
+For details about the silicon errata on OMAP4430, refer
+http://focus.ti.com/pdfs/wtbu/SWPZ009A_OMAP4430_Errata_Public_vA.pdf
+
+Signed-off-by: Nishant Kamat <nskamat@ti.com>
+Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/id.c | 31 ++++++++++++++++++++-----------
+ arch/arm/plat-omap/include/plat/cpu.h | 16 +++++++++++-----
+ 2 files changed, 31 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
+index 5c25f1b..3168b17 100644
+--- a/arch/arm/mach-omap2/id.c
++++ b/arch/arm/mach-omap2/id.c
+@@ -6,7 +6,7 @@
+ * Copyright (C) 2005 Nokia Corporation
+ * Written by Tony Lindgren <tony@atomide.com>
+ *
+- * Copyright (C) 2009 Texas Instruments
++ * Copyright (C) 2009-11 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -328,7 +328,7 @@ static void __init omap4_check_revision(void)
+ */
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+- rev = (idcode >> 28) & 0xff;
++ rev = (idcode >> 28) & 0xf;
+
+ /*
+ * Few initial ES2.0 samples IDCODE is same as ES1.0
+@@ -347,22 +347,31 @@ static void __init omap4_check_revision(void)
+ omap_chip.oc |= CHIP_IS_OMAP4430ES1;
+ break;
+ case 1:
++ default:
+ omap_revision = OMAP4430_REV_ES2_0;
+ omap_chip.oc |= CHIP_IS_OMAP4430ES2;
++ }
++ break;
++ case 0xb95c:
++ switch (rev) {
++ case 3:
++ omap_revision = OMAP4430_REV_ES2_1;
++ omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
+ break;
++ case 4:
+ default:
+- omap_revision = OMAP4430_REV_ES2_0;
+- omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+- }
+- break;
++ omap_revision = OMAP4430_REV_ES2_2;
++ omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
++ }
++ break;
+ default:
+- /* Unknown default to latest silicon rev as default*/
+- omap_revision = OMAP4430_REV_ES2_0;
+- omap_chip.oc |= CHIP_IS_OMAP4430ES2;
++ /* Unknown default to latest silicon rev as default */
++ omap_revision = OMAP4430_REV_ES2_2;
++ omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
+ }
+
+- pr_info("OMAP%04x ES%d.0\n",
+- omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
++ pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
++ ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+ }
+
+ #define OMAP3_SHOW_FEATURE(feat) \
+diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
+index be99438..8198bb6 100644
+--- a/arch/arm/plat-omap/include/plat/cpu.h
++++ b/arch/arm/plat-omap/include/plat/cpu.h
+@@ -5,7 +5,7 @@
+ *
+ * Copyright (C) 2004, 2008 Nokia Corporation
+ *
+- * Copyright (C) 2009 Texas Instruments.
++ * Copyright (C) 2009-11 Texas Instruments.
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+@@ -405,8 +405,10 @@ IS_OMAP_TYPE(3517, 0x3517)
+ #define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+
+ #define OMAP443X_CLASS 0x44300044
+-#define OMAP4430_REV_ES1_0 OMAP443X_CLASS
+-#define OMAP4430_REV_ES2_0 0x44301044
++#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
++#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
++#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
++#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
+
+ /*
+ * omap_chip bits
+@@ -434,12 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517)
+ #define CHIP_IS_OMAP3630ES1_1 (1 << 9)
+ #define CHIP_IS_OMAP3630ES1_2 (1 << 10)
+ #define CHIP_IS_OMAP4430ES2 (1 << 11)
++#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
++#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
+ #define CHIP_IS_TI816X (1 << 14)
+
+ #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+
+-#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
+- CHIP_IS_OMAP4430ES2)
++#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
++ CHIP_IS_OMAP4430ES2 | \
++ CHIP_IS_OMAP4430ES2_1 | \
++ CHIP_IS_OMAP4430ES2_2)
+
+ /*
+ * "GE" here represents "greater than or equal to" in terms of ES
+--
+1.7.1
+
diff --git a/patches/for_next/0079-OMAP4-hwmod-data-Add-rev-and-dev_attr-fields-in-McSP.patch b/patches/for_next/0079-OMAP4-hwmod-data-Add-rev-and-dev_attr-fields-in-McSP.patch
new file mode 100644
index 0000000000000000000000000000000000000000..002c9644e46fcb678045a9eb641c089d407c5951
--- /dev/null
+++ b/patches/for_next/0079-OMAP4-hwmod-data-Add-rev-and-dev_attr-fields-in-McSP.patch
@@ -0,0 +1,120 @@
+From 5b24f51d9a11ec146c3888d991e10dc69c26d27f Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 18 Feb 2011 14:01:06 +0100
+Subject: [PATCH 079/254] OMAP4: hwmod data: Add rev and dev_attr fields in McSPI
+
+- Add a rev attribute to identify various McSPI IP version.
+- Add a dev_attr structure to provide the number of chipselect
+ supported by the instance.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Govindraj.R <govindraj.raja@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 26 ++++++++++++++++++++++++++
+ 1 files changed, 26 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 84e795c..182aa79 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -24,6 +24,7 @@
+ #include <plat/cpu.h>
+ #include <plat/gpio.h>
+ #include <plat/dma.h>
++#include <plat/mcspi.h>
+
+ #include "omap_hwmod_common_data.h"
+
+@@ -3114,6 +3115,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &omap44xx_mcspi_sysc,
++ .rev = OMAP4_MCSPI_REV,
+ };
+
+ /* mcspi1 */
+@@ -3156,6 +3158,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+ &omap44xx_l4_per__mcspi1,
+ };
+
++/* mcspi1 dev_attr */
++static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
++ .num_chipselect = 4,
++};
++
+ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .class = &omap44xx_mcspi_hwmod_class,
+@@ -3169,6 +3176,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+ },
+ },
++ .dev_attr = &mcspi1_dev_attr,
+ .slaves = omap44xx_mcspi1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -3210,6 +3218,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+ &omap44xx_l4_per__mcspi2,
+ };
+
++/* mcspi2 dev_attr */
++static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
++ .num_chipselect = 2,
++};
++
+ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .class = &omap44xx_mcspi_hwmod_class,
+@@ -3223,6 +3236,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+ },
+ },
++ .dev_attr = &mcspi2_dev_attr,
+ .slaves = omap44xx_mcspi2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -3264,6 +3278,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+ &omap44xx_l4_per__mcspi3,
+ };
+
++/* mcspi3 dev_attr */
++static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
++ .num_chipselect = 2,
++};
++
+ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .class = &omap44xx_mcspi_hwmod_class,
+@@ -3277,6 +3296,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+ },
+ },
++ .dev_attr = &mcspi3_dev_attr,
+ .slaves = omap44xx_mcspi3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -3316,6 +3336,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+ &omap44xx_l4_per__mcspi4,
+ };
+
++/* mcspi4 dev_attr */
++static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
++ .num_chipselect = 1,
++};
++
+ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .name = "mcspi4",
+ .class = &omap44xx_mcspi_hwmod_class,
+@@ -3329,6 +3354,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+ },
+ },
++ .dev_attr = &mcspi4_dev_attr,
+ .slaves = omap44xx_mcspi4_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+--
+1.7.1
+
diff --git a/patches/for_next/0080-omap3sdp-clean-regulator-supply-mapping-in-board-fil.patch b/patches/for_next/0080-omap3sdp-clean-regulator-supply-mapping-in-board-fil.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5cc9d483464a8d97112b73c388c470ecc1ececf7
--- /dev/null
+++ b/patches/for_next/0080-omap3sdp-clean-regulator-supply-mapping-in-board-fil.patch
@@ -0,0 +1,160 @@
+From c9f02e415acc4eec48f69f7a7c15639aa065caae Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Thu, 3 Feb 2011 12:45:22 +0000
+Subject: [PATCH 080/254] omap3sdp: clean regulator supply mapping in board file
+
+clean the regulator supply mapping data in the 3430sdp
+board file (which is spread all over) by moving all
+of them together.
+Also use the REGULATOR_SUPPLY macro and remove instances
+of mapping dev pointers at run time.
+Additonally define all regulator_consumer_supply as
+array's and use ARRAY_SIZE macro to define
+num_consumer_supplies.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 71 +++++++++++++++-------------------
+ 1 files changed, 31 insertions(+), 40 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 3e905da..76a260f 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -315,11 +315,6 @@ static struct platform_device sdp3430_dss_device = {
+ },
+ };
+
+-static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
+- .supply = "vdda_dac",
+- .dev = &sdp3430_dss_device.dev,
+-};
+-
+ static struct platform_device *sdp3430_devices[] __initdata = {
+ &sdp3430_dss_device,
+ };
+@@ -369,18 +364,6 @@ static struct omap2_hsmmc_info mmc[] = {
+ {} /* Terminator */
+ };
+
+-static struct regulator_consumer_supply sdp3430_vmmc1_supply = {
+- .supply = "vmmc",
+-};
+-
+-static struct regulator_consumer_supply sdp3430_vsim_supply = {
+- .supply = "vmmc_aux",
+-};
+-
+-static struct regulator_consumer_supply sdp3430_vmmc2_supply = {
+- .supply = "vmmc",
+-};
+-
+ static int sdp3430_twl_gpio_setup(struct device *dev,
+ unsigned gpio, unsigned ngpio)
+ {
+@@ -391,13 +374,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
+ mmc[1].gpio_cd = gpio + 1;
+ omap2_hsmmc_init(mmc);
+
+- /* link regulators to MMC adapters ... we "know" the
+- * regulators will be set up only *after* we return.
+- */
+- sdp3430_vmmc1_supply.dev = mmc[0].dev;
+- sdp3430_vsim_supply.dev = mmc[0].dev;
+- sdp3430_vmmc2_supply.dev = mmc[1].dev;
+-
+ /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
+ gpio_request(gpio + 7, "sub_lcd_en_bkl");
+ gpio_direction_output(gpio + 7, 0);
+@@ -426,11 +402,34 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = {
+ .irq_line = 1,
+ };
+
++/* regulator consumer mappings */
++
+ /* ads7846 on SPI */
+ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
+ REGULATOR_SUPPLY("vcc", "spi1.0"),
+ };
+
++static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
++ REGULATOR_SUPPLY("vdda_dac", "omapdss"),
++};
++
++/* VPLL2 for digital video outputs */
++static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
++};
++
++static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
++ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"),
++};
++
++static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
++ REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.0"),
++};
++
++static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
++ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
++};
++
+ /*
+ * Apply all the fixed voltages since most versions of U-Boot
+ * don't bother with that initialization.
+@@ -501,8 +500,8 @@ static struct regulator_init_data sdp3430_vmmc1 = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &sdp3430_vmmc1_supply,
++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
++ .consumer_supplies = sdp3430_vmmc1_supplies,
+ };
+
+ /* VMMC2 for MMC2 card */
+@@ -516,8 +515,8 @@ static struct regulator_init_data sdp3430_vmmc2 = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &sdp3430_vmmc2_supply,
++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
++ .consumer_supplies = sdp3430_vmmc2_supplies,
+ };
+
+ /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
+@@ -531,8 +530,8 @@ static struct regulator_init_data sdp3430_vsim = {
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &sdp3430_vsim_supply,
++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
++ .consumer_supplies = sdp3430_vsim_supplies,
+ };
+
+ /* VDAC for DSS driving S-Video */
+@@ -546,16 +545,8 @@ static struct regulator_init_data sdp3430_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = 1,
+- .consumer_supplies = &sdp3430_vdda_dac_supply,
+-};
+-
+-/* VPLL2 for digital video outputs */
+-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
+- {
+- .supply = "vdds_dsi",
+- .dev = &sdp3430_dss_device.dev,
+- }
++ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
++ .consumer_supplies = sdp3430_vdda_dac_supplies,
+ };
+
+ static struct regulator_init_data sdp3430_vpll2 = {
+--
+1.7.1
+
diff --git a/patches/for_next/0081-OMAP4-Fix-EINVAL-for-vana-vcxio-vdac.patch b/patches/for_next/0081-OMAP4-Fix-EINVAL-for-vana-vcxio-vdac.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2a1091904c09a797714dc8ccc765f2982222e96c
--- /dev/null
+++ b/patches/for_next/0081-OMAP4-Fix-EINVAL-for-vana-vcxio-vdac.patch
@@ -0,0 +1,87 @@
+From 47571ae5cc6933f3c5b43aecfc01b99394f1ea28 Mon Sep 17 00:00:00 2001
+From: Balaji T K <balajitk@ti.com>
+Date: Mon, 7 Feb 2011 20:59:59 +0530
+Subject: [PATCH 081/254] OMAP4: Fix -EINVAL for vana, vcxio, vdac
+
+Fixed regulators in twl6030 do not have set_voltage hook.
+Regulator core returns -22 if set_voltage is NULL and apply_uV is set
+while applying the constraint to set voltage resulting in failure during probe
+of these regulators.
+Do not set apply_uV for fixed regulators which don't have set_voltage.
+
+machine_constraints_voltage: VANA: failed to apply 2100000uV constraint
+twl_reg twl_reg.43: can't register VANA, -22
+twl_reg: probe of twl_reg.43 failed with error -22
+machine_constraints_voltage: VCXIO: failed to apply 1800000uV constraint
+twl_reg twl_reg.44: can't register VCXIO, -22
+twl_reg: probe of twl_reg.44 failed with error -22
+machine_constraints_voltage: VDAC: failed to apply 1800000uV constraint
+twl_reg twl_reg.45: can't register VDAC, -22
+twl_reg: probe of twl_reg.45 failed with error -22
+
+Signed-off-by: Balaji T K <balajitk@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-4430sdp.c | 3 ---
+ arch/arm/mach-omap2/board-omap4panda.c | 3 ---
+ 2 files changed, 0 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index 7f58d89..1a943be 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -507,7 +507,6 @@ static struct regulator_init_data sdp4430_vana = {
+ .constraints = {
+ .min_uV = 2100000,
+ .max_uV = 2100000,
+- .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+@@ -519,7 +518,6 @@ static struct regulator_init_data sdp4430_vcxio = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+- .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+@@ -531,7 +529,6 @@ static struct regulator_init_data sdp4430_vdac = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+- .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index fca5b9e..220d3b8 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -304,7 +304,6 @@ static struct regulator_init_data omap4_panda_vana = {
+ .constraints = {
+ .min_uV = 2100000,
+ .max_uV = 2100000,
+- .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+@@ -316,7 +315,6 @@ static struct regulator_init_data omap4_panda_vcxio = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+- .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+@@ -328,7 +326,6 @@ static struct regulator_init_data omap4_panda_vdac = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+- .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+--
+1.7.1
+
diff --git a/patches/for_next/0082-OMAP2-add-regulator-for-MMC1.patch b/patches/for_next/0082-OMAP2-add-regulator-for-MMC1.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b4db41243e997e72becf47f4dd636a03fc22ce80
--- /dev/null
+++ b/patches/for_next/0082-OMAP2-add-regulator-for-MMC1.patch
@@ -0,0 +1,61 @@
+From aeccddb22f6995ea522d6096e71d04549dc71fb5 Mon Sep 17 00:00:00 2001
+From: Balaji T K <balajitk@ti.com>
+Date: Mon, 7 Feb 2011 16:08:47 +0000
+Subject: [PATCH 082/254] OMAP2: add regulator for MMC1
+
+Signed-off-by: Balaji T K <balajitk@ti.com>
+Tested-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-2430sdp.c | 21 +++++++++++++++++++++
+ 1 files changed, 21 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
+index ec74c0f..cc42d47 100644
+--- a/arch/arm/mach-omap2/board-2430sdp.c
++++ b/arch/arm/mach-omap2/board-2430sdp.c
+@@ -22,6 +22,7 @@
+ #include <linux/mmc/host.h>
+ #include <linux/delay.h>
+ #include <linux/i2c/twl.h>
++#include <linux/regulator/machine.h>
+ #include <linux/err.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
+@@ -147,6 +148,25 @@ static void __init omap_2430sdp_init_early(void)
+ omap2_init_common_devices(NULL, NULL);
+ }
+
++static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
++ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"),
++};
++
++/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
++static struct regulator_init_data sdp2430_vmmc1 = {
++ .constraints = {
++ .min_uV = 1850000,
++ .max_uV = 3150000,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
++ | REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies),
++ .consumer_supplies = &sdp2430_vmmc1_supplies[0],
++};
++
+ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
+ .gpio_base = OMAP_MAX_GPIO_LINES,
+ .irq_base = TWL4030_GPIO_IRQ_BASE,
+@@ -159,6 +179,7 @@ static struct twl4030_platform_data sdp2430_twldata = {
+
+ /* platform_data for children goes here */
+ .gpio = &sdp2430_gpio_data,
++ .vmmc1 = &sdp2430_vmmc1,
+ };
+
+ static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
+--
+1.7.1
+
diff --git a/patches/for_next/0083-omap-panda-wlan-board-muxing.patch b/patches/for_next/0083-omap-panda-wlan-board-muxing.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b981db33e47c7a5f46964575d7e6da2a8617d150
--- /dev/null
+++ b/patches/for_next/0083-omap-panda-wlan-board-muxing.patch
@@ -0,0 +1,43 @@
+From add3e6e31aadfec3711c165c9e3b3a550f424a56 Mon Sep 17 00:00:00 2001
+From: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Date: Tue, 15 Feb 2011 03:40:32 -0500
+Subject: [PATCH 083/254] omap: panda: wlan board muxing
+
+Add board muxing to support the wlan wl1271 chip that is
+hardwired to mmc5 (fifth mmc controller) on the PANDA.
+
+Based on the wlan board muxing for zoom3 by Ohad Ben-Cohen
+<ohadb@ti.com>
+Signed-off-by: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap4panda.c | 13 +++++++++++++
+ 1 files changed, 13 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index 220d3b8..9f4f86e 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -387,6 +387,19 @@ static int __init omap4_panda_i2c_init(void)
+
+ #ifdef CONFIG_OMAP_MUX
+ static struct omap_board_mux board_mux[] __initdata = {
++ /* WLAN IRQ - GPIO 53 */
++ OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
++ /* WLAN POWER ENABLE - GPIO 43 */
++ OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
++ /* WLAN SDIO: MMC5 CMD */
++ OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ /* WLAN SDIO: MMC5 CLK */
++ OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ /* WLAN SDIO: MMC5 DAT[0-3] */
++ OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
+ #else
+--
+1.7.1
+
diff --git a/patches/for_next/0084-omap-select-REGULATOR_FIXED_VOLTAGE-by-default-for-p.patch b/patches/for_next/0084-omap-select-REGULATOR_FIXED_VOLTAGE-by-default-for-p.patch
new file mode 100644
index 0000000000000000000000000000000000000000..dbe9fd0d2bc551013267a3afb8025d9426e27311
--- /dev/null
+++ b/patches/for_next/0084-omap-select-REGULATOR_FIXED_VOLTAGE-by-default-for-p.patch
@@ -0,0 +1,36 @@
+From b3d3cf431b57096c73839bfd52c2b1430368fe4e Mon Sep 17 00:00:00 2001
+From: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Date: Tue, 15 Feb 2011 03:40:33 -0500
+Subject: [PATCH 084/254] omap: select REGULATOR_FIXED_VOLTAGE by default for panda and sdp4430
+
+Power to the wl12xx wlan device is controlled by a fixed regulator.
+Boards that have the wl12xx should select REGULATOR_FIXED_VOLTAGE.
+Signed-off-by: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/Kconfig | 2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
+index 9b4e78f..b9d8a7b 100644
+--- a/arch/arm/mach-omap2/Kconfig
++++ b/arch/arm/mach-omap2/Kconfig
+@@ -310,6 +310,7 @@ config MACH_OMAP_4430SDP
+ depends on ARCH_OMAP4
+ select OMAP_PACKAGE_CBL
+ select OMAP_PACKAGE_CBS
++ select REGULATOR_FIXED_VOLTAGE
+
+ config MACH_OMAP4_PANDA
+ bool "OMAP4 Panda Board"
+@@ -317,6 +318,7 @@ config MACH_OMAP4_PANDA
+ depends on ARCH_OMAP4
+ select OMAP_PACKAGE_CBL
+ select OMAP_PACKAGE_CBS
++ select REGULATOR_FIXED_VOLTAGE
+
+ config OMAP3_EMU
+ bool "OMAP3 debugging peripherals"
+--
+1.7.1
+
diff --git a/patches/for_next/0085-omap-panda-add-fixed-regulator-device-for-wlan.patch b/patches/for_next/0085-omap-panda-add-fixed-regulator-device-for-wlan.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e86b47b5a2ea33ed8dbc6063e3b8a906901592cd
--- /dev/null
+++ b/patches/for_next/0085-omap-panda-add-fixed-regulator-device-for-wlan.patch
@@ -0,0 +1,84 @@
+From ff69da69e48128d9b1979f11db9e6fddcf3b8d36 Mon Sep 17 00:00:00 2001
+From: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Date: Tue, 15 Feb 2011 03:40:34 -0500
+Subject: [PATCH 085/254] omap: panda: add fixed regulator device for wlan
+
+Add a fixed regulator vmmc device to enable power control
+of the wl1271 wlan device.
+
+Based on the patch for zoom by Ohad Ben-Cohen <ohad@wizery.com>
+Signed-off-by: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap4panda.c | 34 ++++++++++++++++++++++++++++++++
+ 1 files changed, 34 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index 9f4f86e..d56bef1 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -26,6 +26,7 @@
+ #include <linux/usb/otg.h>
+ #include <linux/i2c/twl.h>
+ #include <linux/regulator/machine.h>
++#include <linux/regulator/fixed.h>
+
+ #include <mach/hardware.h>
+ #include <mach/omap4-common.h>
+@@ -45,6 +46,7 @@
+
+ #define GPIO_HUB_POWER 1
+ #define GPIO_HUB_NRESET 62
++#define GPIO_WIFI_PMENA 43
+
+ static struct gpio_led gpio_leds[] = {
+ {
+@@ -171,6 +173,37 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
+ },
+ };
+
++static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
++ .supply = "vmmc",
++ .dev_name = "mmci-omap-hs.4",
++};
++
++static struct regulator_init_data panda_vmmc5 = {
++ .constraints = {
++ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = 1,
++ .consumer_supplies = &omap4_panda_vmmc5_supply,
++};
++
++static struct fixed_voltage_config panda_vwlan = {
++ .supply_name = "vwl1271",
++ .microvolts = 1800000, /* 1.8V */
++ .gpio = GPIO_WIFI_PMENA,
++ .startup_delay = 70000, /* 70msec */
++ .enable_high = 1,
++ .enabled_at_boot = 0,
++ .init_data = &panda_vmmc5,
++};
++
++static struct platform_device omap_vwlan_device = {
++ .name = "reg-fixed-voltage",
++ .id = 1,
++ .dev = {
++ .platform_data = &panda_vwlan,
++ },
++};
++
+ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+ {
+ int ret = 0;
+@@ -416,6 +449,7 @@ static void __init omap4_panda_init(void)
+
+ omap4_panda_i2c_init();
+ platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
++ platform_device_register(&omap_vwlan_device);
+ omap_serial_init();
+ omap4_twl6030_hsmmc_init(mmc);
+ omap4_ehci_init();
+--
+1.7.1
+
diff --git a/patches/for_next/0086-omap-panda-add-mmc5-wl1271-device-support.patch b/patches/for_next/0086-omap-panda-add-mmc5-wl1271-device-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b56037c1b16692aabc0b0c17214d1826511ae449
--- /dev/null
+++ b/patches/for_next/0086-omap-panda-add-mmc5-wl1271-device-support.patch
@@ -0,0 +1,80 @@
+From c92d7d9a9b3265c422c8c449785343e979c89f10 Mon Sep 17 00:00:00 2001
+From: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Date: Tue, 15 Feb 2011 03:40:35 -0500
+Subject: [PATCH 086/254] omap: panda: add mmc5/wl1271 device support
+
+Add MMC5 support on PANDA, which has the wl1271 device hardwired to.
+
+The wl1271 is a 4-wire, 1.8V, embedded SDIO WLAN device with an
+external IRQ line, and power-controlled by a GPIO-based fixed regulator.
+
+Based on the patch for mmc3/wl1271 device support for zoom by Ohad
+Ben-Cohen <ohad@wizery.com>
+Signed-off-by: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap4panda.c | 20 ++++++++++++++++++++
+ 1 files changed, 20 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index d56bef1..3dd241b 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -27,6 +27,7 @@
+ #include <linux/i2c/twl.h>
+ #include <linux/regulator/machine.h>
+ #include <linux/regulator/fixed.h>
++#include <linux/wl12xx.h>
+
+ #include <mach/hardware.h>
+ #include <mach/omap4-common.h>
+@@ -47,6 +48,7 @@
+ #define GPIO_HUB_POWER 1
+ #define GPIO_HUB_NRESET 62
+ #define GPIO_WIFI_PMENA 43
++#define GPIO_WIFI_IRQ 53
+
+ static struct gpio_led gpio_leds[] = {
+ {
+@@ -163,6 +165,15 @@ static struct omap2_hsmmc_info mmc[] = {
+ .gpio_wp = -EINVAL,
+ .gpio_cd = -EINVAL,
+ },
++ {
++ .name = "wl1271",
++ .mmc = 5,
++ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
++ .gpio_wp = -EINVAL,
++ .gpio_cd = -EINVAL,
++ .ocr_mask = MMC_VDD_165_195,
++ .nonremovable = true,
++ },
+ {} /* Terminator */
+ };
+
+@@ -204,6 +215,12 @@ static struct platform_device omap_vwlan_device = {
+ },
+ };
+
++struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
++ .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
++ /* PANDA ref clock is 38.4 MHz */
++ .board_ref_clock = 2,
++};
++
+ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+ {
+ int ret = 0;
+@@ -447,6 +464,9 @@ static void __init omap4_panda_init(void)
+ package = OMAP_PACKAGE_CBL;
+ omap4_mux_init(board_mux, package);
+
++ if (wl12xx_set_platform_data(&omap_panda_wlan_data))
++ pr_err("error setting wl12xx data\n");
++
+ omap4_panda_i2c_init();
+ platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
+ platform_device_register(&omap_vwlan_device);
+--
+1.7.1
+
diff --git a/patches/for_next/0087-OMAP-hsmmc-Enable-MMC4-and-MMC5-on-OMAP4-platforms.patch b/patches/for_next/0087-OMAP-hsmmc-Enable-MMC4-and-MMC5-on-OMAP4-platforms.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a1d8843a77ad0697c66b7f1e3797f98e321145e1
--- /dev/null
+++ b/patches/for_next/0087-OMAP-hsmmc-Enable-MMC4-and-MMC5-on-OMAP4-platforms.patch
@@ -0,0 +1,100 @@
+From 10d3c4e7aa281a9d26cca13b931c0dfc8ef7033e Mon Sep 17 00:00:00 2001
+From: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Date: Tue, 15 Feb 2011 03:40:36 -0500
+Subject: [PATCH 087/254] OMAP: hsmmc: Enable MMC4 and MMC5 on OMAP4 platforms
+
+OMAP4 supports up to 5 MMC controllers, but only 3 of these were
+initialized. MMC5 is used by wl12xx chip. So initialize MMC4 and MMC5.
+
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Signed-off-by: Panduranga Mallireddy <panduranga_mallireddy@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/hsmmc.c | 5 +++++
+ drivers/mmc/host/omap_hsmmc.c | 24 ++++++++++++++++++++----
+ 2 files changed, 25 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
+index 34272e4..5496bc7 100644
+--- a/arch/arm/mach-omap2/hsmmc.c
++++ b/arch/arm/mach-omap2/hsmmc.c
+@@ -350,6 +350,11 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+ mmc->slots[0].after_set_reg = NULL;
+ }
+ break;
++ case 4:
++ case 5:
++ mmc->slots[0].before_set_reg = NULL;
++ mmc->slots[0].after_set_reg = NULL;
++ break;
+ default:
+ pr_err("MMC%d configuration not supported!\n", c->mmc);
+ kfree(mmc);
+diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
+index 078fdf1..8c42573 100644
+--- a/drivers/mmc/host/omap_hsmmc.c
++++ b/drivers/mmc/host/omap_hsmmc.c
+@@ -260,7 +260,7 @@ static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
+ return ret;
+ }
+
+-static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
++static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
+ int vdd)
+ {
+ struct omap_hsmmc_host *host =
+@@ -316,6 +316,12 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
+ return ret;
+ }
+
++static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
++ int vdd)
++{
++ return 0;
++}
++
+ static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
+ int vdd, int cardsleep)
+ {
+@@ -326,7 +332,7 @@ static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
+ return regulator_set_mode(host->vcc, mode);
+ }
+
+-static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
++static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
+ int vdd, int cardsleep)
+ {
+ struct omap_hsmmc_host *host =
+@@ -365,6 +371,12 @@ static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
+ return regulator_enable(host->vcc_aux);
+ }
+
++static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
++ int vdd, int cardsleep)
++{
++ return 0;
++}
++
+ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
+ {
+ struct regulator *reg;
+@@ -379,10 +391,14 @@ static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
+ break;
+ case OMAP_MMC2_DEVID:
+ case OMAP_MMC3_DEVID:
++ case OMAP_MMC5_DEVID:
+ /* Off-chip level shifting, or none */
+- mmc_slot(host).set_power = omap_hsmmc_23_set_power;
+- mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
++ mmc_slot(host).set_power = omap_hsmmc_235_set_power;
++ mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
+ break;
++ case OMAP_MMC4_DEVID:
++ mmc_slot(host).set_power = omap_hsmmc_4_set_power;
++ mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
+ default:
+ pr_err("MMC%d configuration not supported!\n", host->id);
+ return -EINVAL;
+--
+1.7.1
+
diff --git a/patches/for_next/0088-OMAP4-hwmod-data-Prevent-timer1-to-be-reset-and-idle.patch b/patches/for_next/0088-OMAP4-hwmod-data-Prevent-timer1-to-be-reset-and-idle.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d201e7cbfca9c1669fc9001f83503ca78b15861c
--- /dev/null
+++ b/patches/for_next/0088-OMAP4-hwmod-data-Prevent-timer1-to-be-reset-and-idle.patch
@@ -0,0 +1,33 @@
+From a6bea99ad46bbe8dec66502ecfaaa7002a7e3e50 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Tue, 22 Feb 2011 10:36:27 +0100
+Subject: [PATCH 088/254] OMAP4: hwmod data: Prevent timer1 to be reset and idle during init
+
+Since the timer1 is now started before the hwmod_init, we cannot
+reset it and idle it anymore.
+
+Add the appropriate flags to prevent the hwmod framework to do that.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@deeprootsystems.com>
+Acked-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 182aa79..79a8601 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -3989,6 +3989,7 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+ static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &omap44xx_timer_1ms_hwmod_class,
++ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_timer1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
+ .main_clk = "timer1_fck",
+--
+1.7.1
+
diff --git a/patches/panda/0002-OMAP2420-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch b/patches/for_next/0089-OMAP2420-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
similarity index 94%
rename from patches/panda/0002-OMAP2420-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
rename to patches/for_next/0089-OMAP2420-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
index 0fe48005a6c853b41ac5793e9a2b8a23083636eb..44b81c5aa4bdfb0a778e54c993730817dc9278b2 100644
--- a/patches/panda/0002-OMAP2420-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
+++ b/patches/for_next/0089-OMAP2420-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
@@ -1,7 +1,7 @@
-From 5af6a65e8b5e42c9d1dd4f4df4a2f7d253134ba7 Mon Sep 17 00:00:00 2001
+From 9d6fdcb402dcb1098572ea1daee45491c23ba9c3 Mon Sep 17 00:00:00 2001
From: Senthilvadivu Guruswamy <svadivu@ti.com>
-Date: Mon, 24 Jan 2011 06:21:49 +0000
-Subject: [PATCH 02/35] OMAP2420: hwmod data: add DSS DISPC RFBI VENC
+Date: Tue, 22 Feb 2011 09:50:36 +0200
+Subject: [PATCH 089/254] OMAP2420: hwmod data: add DSS DISPC RFBI VENC
Hwmod needs database of all IPs in a system. This patch generates the hwmod
database for OMAP2420 Display Sub System,. Since DSS is also considered as an
@@ -12,29 +12,29 @@ Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 311 +++++++++++++++++++++++++++-
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 310 ++++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/l3_2xxx.h | 20 ++
arch/arm/plat-omap/include/plat/l4_2xxx.h | 24 +++
- 3 files changed, 354 insertions(+), 1 deletions(-)
+ 3 files changed, 354 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-omap/include/plat/l3_2xxx.h
create mode 100644 arch/arm/plat-omap/include/plat/l4_2xxx.h
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
-index b85c630..21014de 100644
+index 7fffd34..f323c6b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
-@@ -18,7 +18,8 @@
- #include <plat/serial.h>
+@@ -19,6 +19,8 @@
#include <plat/i2c.h>
#include <plat/gpio.h>
--
+ #include <plat/mcspi.h>
+#include <plat/l3_2xxx.h>
+#include <plat/l4_2xxx.h>
+
#include "omap_hwmod_common_data.h"
- #include "cm-regbits-24xx.h"
-@@ -38,6 +39,10 @@ static struct omap_hwmod omap2420_mpu_hwmod;
+@@ -39,6 +41,10 @@ static struct omap_hwmod omap2420_mpu_hwmod;
static struct omap_hwmod omap2420_iva_hwmod;
static struct omap_hwmod omap2420_l3_main_hwmod;
static struct omap_hwmod omap2420_l4_core_hwmod;
@@ -45,7 +45,7 @@ index b85c630..21014de 100644
static struct omap_hwmod omap2420_wd_timer2_hwmod;
static struct omap_hwmod omap2420_gpio1_hwmod;
static struct omap_hwmod omap2420_gpio2_hwmod;
-@@ -64,6 +69,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
+@@ -67,6 +73,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
&omap2420_mpu__l3_main,
};
@@ -65,7 +65,7 @@ index b85c630..21014de 100644
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
&omap2420_l3_main__l4_core,
-@@ -470,6 +488,291 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
+@@ -509,6 +528,291 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
@@ -357,7 +357,7 @@ index b85c630..21014de 100644
/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
.rev_offs = 0x00,
-@@ -874,6 +1177,12 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+@@ -1026,6 +1330,12 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
&omap2420_uart1_hwmod,
&omap2420_uart2_hwmod,
&omap2420_uart3_hwmod,
diff --git a/patches/panda/0003-OMAP2430-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch b/patches/for_next/0090-OMAP2430-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
similarity index 94%
rename from patches/panda/0003-OMAP2430-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
rename to patches/for_next/0090-OMAP2430-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
index df278c09332ee4922cfc80ab650fdd63e3e5e16a..5f8eb00f0fb9381d8ad3af2cfc9a677f93a60ef9 100644
--- a/patches/panda/0003-OMAP2430-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
+++ b/patches/for_next/0090-OMAP2430-hwmod-data-add-DSS-DISPC-RFBI-VENC.patch
@@ -1,7 +1,7 @@
-From 7b1e2c0b9fa7ec9df0b1e01184cd50835c01a18f Mon Sep 17 00:00:00 2001
+From c64b44b5898e913d4ba3dcfbf468db4677709fb0 Mon Sep 17 00:00:00 2001
From: Senthilvadivu Guruswamy <svadivu@ti.com>
-Date: Mon, 24 Jan 2011 06:21:50 +0000
-Subject: [PATCH 03/35] OMAP2430: hwmod data: add DSS DISPC RFBI VENC
+Date: Tue, 22 Feb 2011 09:51:15 +0200
+Subject: [PATCH 090/254] OMAP2430: hwmod data: add DSS DISPC RFBI VENC
Hwmod needs database of all IPs in a system. This patch generates the hwmod
database for OMAP2430 Display Sub System. Since DSS is also considered as an
@@ -12,23 +12,24 @@ Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 284 ++++++++++++++++++++++++++++
1 files changed, 284 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
-index 8ecfbcd..1ef3f3f 100644
+index 414b397..36d59ef 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
-@@ -18,6 +18,7 @@
- #include <plat/serial.h>
+@@ -19,6 +19,7 @@
#include <plat/i2c.h>
#include <plat/gpio.h>
+ #include <plat/mcspi.h>
+#include <plat/l3_2xxx.h>
#include "omap_hwmod_common_data.h"
-@@ -38,6 +39,10 @@ static struct omap_hwmod omap2430_mpu_hwmod;
+@@ -39,6 +40,10 @@ static struct omap_hwmod omap2430_mpu_hwmod;
static struct omap_hwmod omap2430_iva_hwmod;
static struct omap_hwmod omap2430_l3_main_hwmod;
static struct omap_hwmod omap2430_l4_core_hwmod;
@@ -39,7 +40,7 @@ index 8ecfbcd..1ef3f3f 100644
static struct omap_hwmod omap2430_wd_timer2_hwmod;
static struct omap_hwmod omap2430_gpio1_hwmod;
static struct omap_hwmod omap2430_gpio2_hwmod;
-@@ -65,6 +70,19 @@ static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
+@@ -69,6 +74,19 @@ static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
&omap2430_mpu__l3_main,
};
@@ -59,7 +60,7 @@ index 8ecfbcd..1ef3f3f 100644
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
&omap2430_l3_main__l4_core,
-@@ -469,6 +487,266 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
+@@ -566,6 +584,266 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
@@ -326,7 +327,7 @@ index 8ecfbcd..1ef3f3f 100644
/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
.rev_offs = 0x00,
-@@ -929,6 +1207,12 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+@@ -1182,6 +1460,12 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
&omap2430_uart1_hwmod,
&omap2430_uart2_hwmod,
&omap2430_uart3_hwmod,
diff --git a/patches/panda/0004-OMAP3-hwmod-data-add-DSS-DISPC-RFBI-DSI-VENC.patch b/patches/for_next/0091-OMAP3-hwmod-data-add-DSS-DISPC-RFBI-DSI-VENC.patch
similarity index 97%
rename from patches/panda/0004-OMAP3-hwmod-data-add-DSS-DISPC-RFBI-DSI-VENC.patch
rename to patches/for_next/0091-OMAP3-hwmod-data-add-DSS-DISPC-RFBI-DSI-VENC.patch
index 9986a5e7df4c34b0b58ac379ea7d27990cbe2987..a53d4f57c9833bb8170fd0ce8393c8824f294858 100644
--- a/patches/panda/0004-OMAP3-hwmod-data-add-DSS-DISPC-RFBI-DSI-VENC.patch
+++ b/patches/for_next/0091-OMAP3-hwmod-data-add-DSS-DISPC-RFBI-DSI-VENC.patch
@@ -1,7 +1,7 @@
-From f6f4f5176ae19ce0695150f3ecbd1964f4c1aa0f Mon Sep 17 00:00:00 2001
+From 12cb8d3ca807d494eb27e8515df5b1006673e375 Mon Sep 17 00:00:00 2001
From: Senthilvadivu Guruswamy <svadivu@ti.com>
Date: Mon, 24 Jan 2011 06:21:51 +0000
-Subject: [PATCH 04/35] OMAP3: hwmod data: add DSS DISPC RFBI DSI VENC
+Subject: [PATCH 091/254] OMAP3: hwmod data: add DSS DISPC RFBI DSI VENC
Hwmod needs database of all IPs in a system. This patch generates the hwmod
database for Display Sub System applicable for OMAP3430 and
@@ -18,6 +18,7 @@ Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 433 ++++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/l3_3xxx.h | 20 ++
@@ -26,7 +27,7 @@ Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
create mode 100644 arch/arm/plat-omap/include/plat/l3_3xxx.h
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
-index 8d81813..713165d 100644
+index 0252cd5..a88767d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -18,6 +18,7 @@
@@ -37,7 +38,7 @@ index 8d81813..713165d 100644
#include <plat/l4_3xxx.h>
#include <plat/i2c.h>
#include <plat/gpio.h>
-@@ -44,6 +45,12 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
+@@ -46,6 +47,12 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
static struct omap_hwmod omap3xxx_l4_core_hwmod;
static struct omap_hwmod omap3xxx_l4_per_hwmod;
static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
@@ -50,7 +51,7 @@ index 8d81813..713165d 100644
static struct omap_hwmod omap3xxx_i2c1_hwmod;
static struct omap_hwmod omap3xxx_i2c2_hwmod;
static struct omap_hwmod omap3xxx_i2c3_hwmod;
-@@ -84,6 +91,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
+@@ -91,6 +98,19 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
&omap3xxx_mpu__l3_main,
};
@@ -70,7 +71,7 @@ index 8d81813..713165d 100644
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
&omap3xxx_l3_main__l4_core,
-@@ -664,6 +684,410 @@ static struct omap_hwmod_class i2c_class = {
+@@ -742,6 +762,410 @@ static struct omap_hwmod_class i2c_class = {
.sysc = &i2c_sysc,
};
@@ -481,7 +482,7 @@ index 8d81813..713165d 100644
/* I2C1 */
static struct omap_i2c_dev_attr i2c1_dev_attr = {
-@@ -1368,6 +1792,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+@@ -1715,6 +2139,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_uart2_hwmod,
&omap3xxx_uart3_hwmod,
&omap3xxx_uart4_hwmod,
diff --git a/patches/for_next/0092-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch b/patches/for_next/0092-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch
new file mode 100644
index 0000000000000000000000000000000000000000..379a357fe6698b60121574d56d6ac238430c8265
--- /dev/null
+++ b/patches/for_next/0092-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch
@@ -0,0 +1,142 @@
+From 038119e451ee1c177d23b0967129fa01d8822e00 Mon Sep 17 00:00:00 2001
+From: Senthilvadivu Guruswamy <svadivu@ti.com>
+Date: Mon, 24 Jan 2011 06:21:53 +0000
+Subject: [PATCH 092/254] OMAP2, 3: DSS2: Use Regulator init with driver name
+
+Use driver name in regulator inits needed for display instead of using device
+structure name.
+
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Tested-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
+Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 12 ++++++++++--
+ arch/arm/mach-omap2/board-cm-t35.c | 12 ++++--------
+ arch/arm/mach-omap2/board-igep0020.c | 6 ++----
+ arch/arm/mach-omap2/board-omap3evm.c | 6 ++----
+ arch/arm/mach-omap2/board-omap3stalker.c | 12 ++++--------
+ 5 files changed, 22 insertions(+), 26 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 76a260f..979c05d 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -315,6 +315,9 @@ static struct platform_device sdp3430_dss_device = {
+ },
+ };
+
++static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
++ REGULATOR_SUPPLY("vdda_dac", "omapdss");
++
+ static struct platform_device *sdp3430_devices[] __initdata = {
+ &sdp3430_dss_device,
+ };
+@@ -545,8 +548,13 @@ static struct regulator_init_data sdp3430_vdac = {
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+- .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
+- .consumer_supplies = sdp3430_vdda_dac_supplies,
++ .num_consumer_supplies = 1,
++ .consumer_supplies = &sdp3430_vdda_dac_supply,
++};
++
++/* VPLL2 for digital video outputs */
++static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
++ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+ };
+
+ static struct regulator_init_data sdp3430_vpll2 = {
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index 9e4de92..d650b7f 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -495,15 +495,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
+ .supply = "vmmc_aux",
+ };
+
+-static struct regulator_consumer_supply cm_t35_vdac_supply = {
+- .supply = "vdda_dac",
+- .dev = &cm_t35_dss_device.dev,
+-};
++static struct regulator_consumer_supply cm_t35_vdac_supply =
++ REGULATOR_SUPPLY("vdda_dac", "omapdss");
+
+-static struct regulator_consumer_supply cm_t35_vdvi_supply = {
+- .supply = "vdvi",
+- .dev = &cm_t35_dss_device.dev,
+-};
++static struct regulator_consumer_supply cm_t35_vdvi_supply =
++ REGULATOR_SUPPLY("vdvi", "omapdss");
+
+ /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+ static struct regulator_init_data cm_t35_vmmc1 = {
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index dd0b1ac..c235fa2 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -493,10 +493,8 @@ static struct platform_device igep2_dss_device = {
+ },
+ };
+
+-static struct regulator_consumer_supply igep2_vpll2_supply = {
+- .supply = "vdds_dsi",
+- .dev = &igep2_dss_device.dev,
+-};
++static struct regulator_consumer_supply igep2_vpll2_supply =
++ REGULATOR_SUPPLY("vdds_dsi", "omapdss");
+
+ static struct regulator_init_data igep2_vpll2 = {
+ .constraints = {
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index d4a1157..f5bf87f 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -551,10 +551,8 @@ static struct twl4030_codec_data omap3evm_codec_data = {
+ .audio = &omap3evm_audio_data,
+ };
+
+-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = {
+- .supply = "vdda_dac",
+- .dev = &omap3_evm_dss_device.dev,
+-};
++static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
++ REGULATOR_SUPPLY("vdda_dac", "omapdss");
+
+ /* VDAC for DSS driving S-Video */
+ static struct regulator_init_data omap3_evm_vdac = {
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index 5d1ccef..9c63c37 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -448,10 +448,8 @@ static struct twl4030_codec_data omap3stalker_codec_data = {
+ .audio = &omap3stalker_audio_data,
+ };
+
+-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = {
+- .supply = "vdda_dac",
+- .dev = &omap3_stalker_dss_device.dev,
+-};
++static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
++ REGULATOR_SUPPLY("vdda_dac", "omapdss");
+
+ /* VDAC for DSS driving S-Video */
+ static struct regulator_init_data omap3_stalker_vdac = {
+@@ -469,10 +467,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
+ };
+
+ /* VPLL2 for digital video outputs */
+-static struct regulator_consumer_supply omap3_stalker_vpll2_supply = {
+- .supply = "vdds_dsi",
+- .dev = &omap3_stalker_lcd_device.dev,
+-};
++static struct regulator_consumer_supply omap3_stalker_vpll2_supply =
++ REGULATOR_SUPPLY("vdds_dsi", "omapdss");
+
+ static struct regulator_init_data omap3_stalker_vpll2 = {
+ .constraints = {
+--
+1.7.1
+
diff --git a/patches/for_next/0093-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch b/patches/for_next/0093-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a499d6791b274a94458ca25aabfb076cd55c2b69
--- /dev/null
+++ b/patches/for_next/0093-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch
@@ -0,0 +1,115 @@
+From 01c5a8193d9a9377a1654542f001f7fac0ff3b70 Mon Sep 17 00:00:00 2001
+From: Sumit Semwal <sumit.semwal@ti.com>
+Date: Mon, 24 Jan 2011 06:21:54 +0000
+Subject: [PATCH 093/254] OMAP2, 3: DSS2: Create new file display.c for central dss driver registration.
+
+A new file display.c is introduced for display driver init, which adds a function
+omap_display_init to do the DSS driver registration. This is the first step in moving
+away registration of DSS from board files into a common place.
+
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+Tested-by: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
+Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 3 ++
+ arch/arm/mach-omap2/display.c | 45 +++++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/display.h | 11 +++++++
+ 3 files changed, 59 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/display.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index ee72a97..1c3635d 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -245,3 +245,6 @@ obj-y += $(smc91x-m) $(smc91x-y)
+ smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
+ obj-y += $(smsc911x-m) $(smsc911x-y)
+ obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
++
++disp-$(CONFIG_OMAP2_DSS) := display.o
++obj-y += $(disp-m) $(disp-y)
+diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
+new file mode 100644
+index 0000000..b18db84
+--- /dev/null
++++ b/arch/arm/mach-omap2/display.c
+@@ -0,0 +1,45 @@
++/*
++ * OMAP2plus display device setup / initialization.
++ *
++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
++ * Senthilvadivu Guruswamy
++ * Sumit Semwal
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++
++#include <plat/display.h>
++
++static struct platform_device omap_display_device = {
++ .name = "omapdss",
++ .id = -1,
++ .dev = {
++ .platform_data = NULL,
++ },
++};
++
++int __init omap_display_init(struct omap_dss_board_info *board_data)
++{
++ int r = 0;
++ omap_display_device.dev.platform_data = board_data;
++
++ r = platform_device_register(&omap_display_device);
++ if (r < 0)
++ printk(KERN_ERR "Unable to register OMAP-Display device\n");
++
++ return r;
++}
+diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
+index 537f4e4..0f140ec 100644
+--- a/arch/arm/plat-omap/include/plat/display.h
++++ b/arch/arm/plat-omap/include/plat/display.h
+@@ -23,6 +23,7 @@
+ #include <linux/list.h>
+ #include <linux/kobject.h>
+ #include <linux/device.h>
++#include <linux/platform_device.h>
+ #include <asm/atomic.h>
+
+ #define DISPC_IRQ_FRAMEDONE (1 << 0)
+@@ -226,6 +227,16 @@ struct omap_dss_board_info {
+ struct omap_dss_device *default_device;
+ };
+
++#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
++/* Init with the board info */
++extern int omap_display_init(struct omap_dss_board_info *board_data);
++#else
++static inline int omap_display_init(struct omap_dss_board_info *board_data)
++{
++ return 0;
++}
++#endif
++
+ struct omap_video_timings {
+ /* Unit: pixels */
+ u16 x_res;
+--
+1.7.1
+
diff --git a/patches/panda/0008-OMAP2-3-DSS2-board-files-replace-platform_device_reg.patch b/patches/for_next/0094-OMAP2-3-DSS2-board-files-replace-platform_device_reg.patch
similarity index 85%
rename from patches/panda/0008-OMAP2-3-DSS2-board-files-replace-platform_device_reg.patch
rename to patches/for_next/0094-OMAP2-3-DSS2-board-files-replace-platform_device_reg.patch
index 25c36a7da41ecdcfb87688e3b678b57f2d159743..e0136ef6a2a478f96d3ee2013dc8f68eee7ef49c 100644
--- a/patches/panda/0008-OMAP2-3-DSS2-board-files-replace-platform_device_reg.patch
+++ b/patches/for_next/0094-OMAP2-3-DSS2-board-files-replace-platform_device_reg.patch
@@ -1,7 +1,7 @@
-From 410f97f52e5895a74c5e9b75a2f44354d2b7f1cf Mon Sep 17 00:00:00 2001
+From 19c2faaa8b15387e3641d73626db472bd4b7cd0e Mon Sep 17 00:00:00 2001
From: Senthilvadivu Guruswamy <svadivu@ti.com>
-Date: Mon, 24 Jan 2011 06:21:55 +0000
-Subject: [PATCH 08/35] OMAP2, 3: DSS2: board files: replace platform_device_register with omap_display_init()
+Date: Tue, 22 Feb 2011 11:24:50 +0200
+Subject: [PATCH 094/254] OMAP2, 3: DSS2: board files: replace platform_device_register with omap_display_init()
This patch updated board files to replace platform_device_register or
platform_add_devices of DSS with omap_display_init(). This moves away
@@ -11,6 +11,7 @@ Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
---
arch/arm/mach-omap2/board-3430sdp.c | 14 +-------------
arch/arm/mach-omap2/board-am3517evm.c | 16 +---------------
@@ -26,7 +27,7 @@ Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
11 files changed, 11 insertions(+), 123 deletions(-)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
-index d99902c..d00f356 100644
+index 979c05d..8465e80 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -307,21 +307,9 @@ static struct omap_dss_board_info sdp3430_dss_data = {
@@ -34,7 +35,7 @@ index d99902c..d00f356 100644
};
-static struct platform_device sdp3430_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &sdp3430_dss_data,
@@ -42,7 +43,7 @@ index d99902c..d00f356 100644
-};
-
static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omap_display");
+ REGULATOR_SUPPLY("vdda_dac", "omapdss");
-static struct platform_device *sdp3430_devices[] __initdata = {
- &sdp3430_dss_device,
@@ -51,7 +52,7 @@ index d99902c..d00f356 100644
static struct omap_board_config_kernel sdp3430_config[] __initdata = {
};
-@@ -796,7 +784,7 @@ static void __init omap_3430sdp_init(void)
+@@ -806,7 +794,7 @@ static void __init omap_3430sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3430_i2c_init();
@@ -61,7 +62,7 @@ index d99902c..d00f356 100644
ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
else
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
-index 6bb5f53..548f524 100644
+index 8532d6e..634fe65 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -378,24 +378,12 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
@@ -69,7 +70,7 @@ index 6bb5f53..548f524 100644
};
-static struct platform_device am3517_evm_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &am3517_evm_dss_data,
@@ -86,10 +87,10 @@ index 6bb5f53..548f524 100644
- &am3517_evm_dss_device,
-};
-
- static void __init am3517_evm_init_irq(void)
+ static void __init am3517_evm_init_early(void)
{
omap_board_config = am3517_evm_config;
-@@ -495,9 +483,7 @@ static void __init am3517_evm_init(void)
+@@ -498,9 +486,7 @@ static void __init am3517_evm_init(void)
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
am3517_evm_i2c_init();
@@ -101,7 +102,7 @@ index 6bb5f53..548f524 100644
/* Configure GPIO for EHCI port */
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
-index 22322d1..1c36ec8 100644
+index d650b7f..7311824 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -401,14 +401,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
@@ -109,7 +110,7 @@ index 22322d1..1c36ec8 100644
};
-static struct platform_device cm_t35_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &cm_t35_dss_data,
@@ -129,7 +130,7 @@ index 22322d1..1c36ec8 100644
pr_err("CM-T35: failed to register DSS device\n");
goto err_dev_reg;
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
-index e8cde27..84ff6b0 100644
+index af74288..54abdd0 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -195,14 +195,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
@@ -137,7 +138,7 @@ index e8cde27..84ff6b0 100644
};
-static struct platform_device devkit8000_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &devkit8000_dss_data,
@@ -145,9 +146,9 @@ index e8cde27..84ff6b0 100644
-};
-
static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omap_display");
+ REGULATOR_SUPPLY("vdda_dac", "omapdss");
-@@ -575,7 +567,6 @@ static void __init omap_dm9000_init(void)
+@@ -579,7 +571,6 @@ static void __init omap_dm9000_init(void)
}
static struct platform_device *devkit8000_devices[] __initdata = {
@@ -155,7 +156,7 @@ index e8cde27..84ff6b0 100644
&leds_gpio,
&keys_gpio,
&omap_dm9000_dev,
-@@ -797,6 +788,7 @@ static void __init devkit8000_init(void)
+@@ -801,6 +792,7 @@ static void __init devkit8000_init(void)
platform_add_devices(devkit8000_devices,
ARRAY_SIZE(devkit8000_devices));
@@ -164,7 +165,7 @@ index e8cde27..84ff6b0 100644
ARRAY_SIZE(devkit8000_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
-index 238c69e..d79dcd5 100644
+index c235fa2..54e6318 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -485,14 +485,6 @@ static struct omap_dss_board_info igep2_dss_data = {
@@ -172,7 +173,7 @@ index 238c69e..d79dcd5 100644
};
-static struct platform_device igep2_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &igep2_dss_data,
@@ -180,7 +181,7 @@ index 238c69e..d79dcd5 100644
-};
-
static struct regulator_consumer_supply igep2_vpll2_supply =
- REGULATOR_SUPPLY("vdds_dsi", "omap_display");
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss");
@@ -519,7 +511,6 @@ static void __init igep2_display_init(void)
}
@@ -190,7 +191,7 @@ index 238c69e..d79dcd5 100644
&igep2_vwlan_device,
};
-@@ -695,6 +686,7 @@ static void __init igep2_init(void)
+@@ -694,6 +685,7 @@ static void __init igep2_init(void)
/* Register I2C busses and drivers */
igep2_i2c_init();
platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
@@ -199,7 +200,7 @@ index 238c69e..d79dcd5 100644
usb_musb_init(&musb_board_data);
usb_ehci_init(&ehci_pdata);
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index fd6b4b8..c0a5066 100644
+index 19bcd00..a1faea3 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -228,14 +228,6 @@ static struct omap_dss_board_info beagle_dss_data = {
@@ -207,7 +208,7 @@ index fd6b4b8..c0a5066 100644
};
-static struct platform_device beagle_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &beagle_dss_data,
@@ -215,9 +216,9 @@ index fd6b4b8..c0a5066 100644
-};
-
static struct regulator_consumer_supply beagle_vdac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omap_display");
+ REGULATOR_SUPPLY("vdda_dac", "omapdss");
-@@ -550,7 +542,6 @@ static void __init omap3_beagle_init_irq(void)
+@@ -554,7 +546,6 @@ static void __init omap3_beagle_init_irq(void)
static struct platform_device *omap3_beagle_devices[] __initdata = {
&leds_gpio,
&keys_gpio,
@@ -225,7 +226,7 @@ index fd6b4b8..c0a5066 100644
};
static void __init omap3beagle_flash_init(void)
-@@ -617,6 +608,7 @@ static void __init omap3_beagle_init(void)
+@@ -621,6 +612,7 @@ static void __init omap3_beagle_init(void)
omap3_beagle_i2c_init();
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
@@ -234,15 +235,15 @@ index fd6b4b8..c0a5066 100644
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
-index 32ac816..5f156fe 100644
+index f5bf87f..5364147 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
-@@ -328,14 +328,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
+@@ -363,14 +363,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
.default_device = &omap3_evm_lcd_device,
};
-static struct platform_device omap3_evm_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &omap3_evm_dss_data,
@@ -252,8 +253,8 @@ index 32ac816..5f156fe 100644
static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
.supply = "vmmc",
};
-@@ -632,10 +624,6 @@ static void __init omap3_evm_init_irq(void)
- omap_init_irq();
+@@ -746,10 +738,6 @@ static void __init omap3_evm_init_early(void)
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
}
-static struct platform_device *omap3_evm_devices[] __initdata = {
@@ -263,7 +264,7 @@ index 32ac816..5f156fe 100644
static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
-@@ -673,7 +661,7 @@ static void __init omap3_evm_init(void)
+@@ -838,7 +826,7 @@ static void __init omap3_evm_init(void)
omap3_evm_i2c_init();
@@ -273,7 +274,7 @@ index 32ac816..5f156fe 100644
spi_register_board_info(omap3evm_spi_board_info,
ARRAY_SIZE(omap3evm_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
-index 9e8faf2..613ab58 100644
+index b91f74c..17ef547 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -253,14 +253,6 @@ static struct omap_dss_board_info pandora_dss_data = {
@@ -281,7 +282,7 @@ index 9e8faf2..613ab58 100644
};
-static struct platform_device pandora_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &pandora_dss_data,
@@ -291,7 +292,7 @@ index 9e8faf2..613ab58 100644
static void pandora_wl1251_init_card(struct mmc_card *card)
{
/*
-@@ -677,7 +669,6 @@ fail:
+@@ -676,7 +668,6 @@ fail:
static struct platform_device *omap3pandora_devices[] __initdata = {
&pandora_leds_gpio,
&pandora_keys_gpio,
@@ -299,7 +300,7 @@ index 9e8faf2..613ab58 100644
&pandora_vwlan_device,
};
-@@ -712,6 +703,7 @@ static void __init omap3pandora_init(void)
+@@ -711,6 +702,7 @@ static void __init omap3pandora_init(void)
pandora_wl1251_init();
platform_add_devices(omap3pandora_devices,
ARRAY_SIZE(omap3pandora_devices));
@@ -308,7 +309,7 @@ index 9e8faf2..613ab58 100644
spi_register_board_info(omap3pandora_spi_board_info,
ARRAY_SIZE(omap3pandora_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
-index 7b675cb..7671218 100644
+index 9c63c37..07006c3 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -240,14 +240,6 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
@@ -316,7 +317,7 @@ index 7b675cb..7671218 100644
};
-static struct platform_device omap3_stalker_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &omap3_stalker_dss_data,
@@ -326,7 +327,7 @@ index 7b675cb..7671218 100644
static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
.supply = "vmmc",
};
-@@ -600,7 +592,6 @@ static void __init omap3_stalker_init_irq(void)
+@@ -604,7 +596,6 @@ static void __init omap3_stalker_init_irq(void)
}
static struct platform_device *omap3_stalker_devices[] __initdata = {
@@ -334,7 +335,7 @@ index 7b675cb..7671218 100644
&keys_gpio,
};
-@@ -640,6 +631,7 @@ static void __init omap3_stalker_init(void)
+@@ -644,6 +635,7 @@ static void __init omap3_stalker_init(void)
platform_add_devices(omap3_stalker_devices,
ARRAY_SIZE(omap3_stalker_devices));
@@ -343,7 +344,7 @@ index 7b675cb..7671218 100644
ARRAY_SIZE(omap3stalker_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
-index 8140d05..89a66db 100644
+index acd6700..89a66db 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -66,18 +66,6 @@ static struct omap_dss_board_info rx51_dss_board_info = {
@@ -351,7 +352,7 @@ index 8140d05..89a66db 100644
};
-struct platform_device rx51_display_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &rx51_dss_board_info,
@@ -376,7 +377,7 @@ index 8140d05..89a66db 100644
}
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
-index d6b949d..37b84c2 100644
+index 6bcd436..37b84c2 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -130,14 +130,6 @@ static struct omap_dss_board_info zoom_dss_data = {
@@ -384,7 +385,7 @@ index d6b949d..37b84c2 100644
};
-static struct platform_device zoom_dss_device = {
-- .name = "omap_display",
+- .name = "omapdss",
- .id = -1,
- .dev = {
- .platform_data = &zoom_dss_data,
diff --git a/patches/for_next/0095-omap-iommu-Gracefully-fail-iommu_enable-if-no-arch_i.patch b/patches/for_next/0095-omap-iommu-Gracefully-fail-iommu_enable-if-no-arch_i.patch
new file mode 100644
index 0000000000000000000000000000000000000000..0ab58acd357b9f9ae77f9e882b6b5f420e14017b
--- /dev/null
+++ b/patches/for_next/0095-omap-iommu-Gracefully-fail-iommu_enable-if-no-arch_i.patch
@@ -0,0 +1,32 @@
+From 0d20c22cd173e914b20dd84f60dc685365b58bd3 Mon Sep 17 00:00:00 2001
+From: Martin Hostettler <martin@neutronstar.dyndns.org>
+Date: Thu, 24 Feb 2011 12:51:31 -0800
+Subject: [PATCH 095/254] omap: iommu: Gracefully fail iommu_enable if no arch_iommu is registered
+
+In a modular build of the iommu code it's possible that the arch iommu code
+isn't loaded when trying to enable the iommu. Instead of blindly following a
+null pointer return -NODEV in that case.
+
+Signed-off-by: Martin Hostettler <martin@neutronstar.dyndns.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/iommu.c | 3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
+index b1107c0..3d8f55e 100644
+--- a/arch/arm/plat-omap/iommu.c
++++ b/arch/arm/plat-omap/iommu.c
+@@ -104,6 +104,9 @@ static int iommu_enable(struct iommu *obj)
+ if (!obj)
+ return -EINVAL;
+
++ if (!arch_iommu)
++ return -ENODEV;
++
+ clk_enable(obj->clk);
+
+ err = arch_iommu->enable(obj);
+--
+1.7.1
+
diff --git a/patches/for_next/0096-omap-iommu-print-module-name-on-error-messages.patch b/patches/for_next/0096-omap-iommu-print-module-name-on-error-messages.patch
new file mode 100644
index 0000000000000000000000000000000000000000..78e5ddff22ade332b0734e5a9329e9d503edc901
--- /dev/null
+++ b/patches/for_next/0096-omap-iommu-print-module-name-on-error-messages.patch
@@ -0,0 +1,39 @@
+From 9235ed103b370349f832b8a0f58218bbd61160af Mon Sep 17 00:00:00 2001
+From: David Cohen <dacohen@gmail.com>
+Date: Thu, 24 Feb 2011 12:51:32 -0800
+Subject: [PATCH 096/254] omap: iommu: print module name on error messages
+
+OMAP IOMMU generic layer doesn't need ot print function name during
+error messages. Print module name instead which is more useful.
+
+Signed-off-by: David Cohen <dacohen@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/iommu.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
+index 3d8f55e..4b3218e 100644
+--- a/arch/arm/plat-omap/iommu.c
++++ b/arch/arm/plat-omap/iommu.c
+@@ -809,7 +809,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
+ iopgd = iopgd_offset(obj, da);
+
+ if (!iopgd_is_table(*iopgd)) {
+- dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
++ dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", obj->name,
+ da, iopgd, *iopgd);
+ return IRQ_NONE;
+ }
+@@ -817,7 +817,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
+ iopte = iopte_offset(iopgd, da);
+
+ dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
+- __func__, da, iopgd, *iopgd, iopte, *iopte);
++ obj->name, da, iopgd, *iopgd, iopte, *iopte);
+
+ return IRQ_NONE;
+ }
+--
+1.7.1
+
diff --git a/patches/for_next/0097-OMAP2-hwmod-data-add-mailbox-data.patch b/patches/for_next/0097-OMAP2-hwmod-data-add-mailbox-data.patch
new file mode 100644
index 0000000000000000000000000000000000000000..476401af8e3bcecf307f23d2aecf2a5721e61437
--- /dev/null
+++ b/patches/for_next/0097-OMAP2-hwmod-data-add-mailbox-data.patch
@@ -0,0 +1,198 @@
+From 21b9685ff2adac7a357133d5ad2b33685df03ee9 Mon Sep 17 00:00:00 2001
+From: Omar Ramirez Luna <omar.ramirez@ti.com>
+Date: Thu, 24 Feb 2011 12:51:32 -0800
+Subject: [PATCH 097/254] OMAP2: hwmod data: add mailbox data
+
+Mailbox hwmod data for omap2430 and 2420.
+
+Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 73 ++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 72 +++++++++++++++++++++++++++
+ 2 files changed, 145 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index f323c6b..19ad9d0 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -1208,6 +1208,76 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
+ };
+
+ /*
++ * 'mailbox' class
++ * mailbox module allowing communication between the on-chip processors
++ * using a queued mailbox-interrupt mechanism.
++ */
++
++static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
++ .rev_offs = 0x000,
++ .sysc_offs = 0x010,
++ .syss_offs = 0x014,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
++ .name = "mailbox",
++ .sysc = &omap2420_mailbox_sysc,
++};
++
++/* mailbox */
++static struct omap_hwmod omap2420_mailbox_hwmod;
++static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
++ { .name = "dsp", .irq = 26 },
++ { .name = "iva", .irq = 34 },
++};
++
++static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
++ {
++ .pa_start = 0x48094000,
++ .pa_end = 0x480941ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++/* l4_core -> mailbox */
++static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_mailbox_hwmod,
++ .addr = omap2420_mailbox_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mailbox slave ports */
++static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
++ &omap2420_l4_core__mailbox,
++};
++
++static struct omap_hwmod omap2420_mailbox_hwmod = {
++ .name = "mailbox",
++ .class = &omap2420_mailbox_hwmod_class,
++ .mpu_irqs = omap2420_mailbox_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
++ .main_clk = "mailboxes_ick",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
++ },
++ },
++ .slaves = omap2420_mailbox_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
++};
++
++/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+@@ -1348,6 +1418,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+ /* dma_system class*/
+ &omap2420_dma_system_hwmod,
+
++ /* mailbox class */
++ &omap2420_mailbox_hwmod,
++
+ /* mcspi class */
+ &omap2420_mcspi1_hwmod,
+ &omap2420_mcspi2_hwmod,
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 36d59ef..6e564f7 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -1295,6 +1295,75 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
+ };
+
+ /*
++ * 'mailbox' class
++ * mailbox module allowing communication between the on-chip processors
++ * using a queued mailbox-interrupt mechanism.
++ */
++
++static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
++ .rev_offs = 0x000,
++ .sysc_offs = 0x010,
++ .syss_offs = 0x014,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
++ .name = "mailbox",
++ .sysc = &omap2430_mailbox_sysc,
++};
++
++/* mailbox */
++static struct omap_hwmod omap2430_mailbox_hwmod;
++static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
++ { .irq = 26 },
++};
++
++static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
++ {
++ .pa_start = 0x48094000,
++ .pa_end = 0x480941ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++/* l4_core -> mailbox */
++static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mailbox_hwmod,
++ .addr = omap2430_mailbox_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mailbox slave ports */
++static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
++ &omap2430_l4_core__mailbox,
++};
++
++static struct omap_hwmod omap2430_mailbox_hwmod = {
++ .name = "mailbox",
++ .class = &omap2430_mailbox_hwmod_class,
++ .mpu_irqs = omap2430_mailbox_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
++ .main_clk = "mailboxes_ick",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
++ },
++ },
++ .slaves = omap2430_mailbox_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
++/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+@@ -1479,6 +1548,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ /* dma_system class*/
+ &omap2430_dma_system_hwmod,
+
++ /* mailbox class */
++ &omap2430_mailbox_hwmod,
++
+ /* mcspi class */
+ &omap2430_mcspi1_hwmod,
+ &omap2430_mcspi2_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0098-OMAP3-hwmod-data-add-mailbox-data.patch b/patches/for_next/0098-OMAP3-hwmod-data-add-mailbox-data.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d96b7b94e397681de6e7f1928786da2a704ec191
--- /dev/null
+++ b/patches/for_next/0098-OMAP3-hwmod-data-add-mailbox-data.patch
@@ -0,0 +1,106 @@
+From 73ec8ebe088b8667ba9e94d27b527832cf2f6e25 Mon Sep 17 00:00:00 2001
+From: Felipe Contreras <felipe.contreras@gmail.com>
+Date: Thu, 24 Feb 2011 12:51:32 -0800
+Subject: [PATCH 098/254] OMAP3: hwmod data: add mailbox data
+
+Mailbox hwmod data for omap3.
+
+Signed-off-by: Felipe Contreras <felipe.contreras@gmail.com>
+Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 71 ++++++++++++++++++++++++++++
+ 1 files changed, 71 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index a88767d..3585409 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1858,6 +1858,74 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+ };
+
++/*
++ * 'mailbox' class
++ * mailbox module allowing communication between the on-chip processors
++ * using a queued mailbox-interrupt mechanism.
++ */
++
++static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
++ .rev_offs = 0x000,
++ .sysc_offs = 0x010,
++ .syss_offs = 0x014,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
++ .name = "mailbox",
++ .sysc = &omap3xxx_mailbox_sysc,
++};
++
++static struct omap_hwmod omap3xxx_mailbox_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
++ { .irq = 26 },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
++ {
++ .pa_start = 0x48094000,
++ .pa_end = 0x480941ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++/* l4_core -> mailbox */
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_mailbox_hwmod,
++ .addr = omap3xxx_mailbox_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mailbox slave ports */
++static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
++ &omap3xxx_l4_core__mailbox,
++};
++
++static struct omap_hwmod omap3xxx_mailbox_hwmod = {
++ .name = "mailbox",
++ .class = &omap3xxx_mailbox_hwmod_class,
++ .mpu_irqs = omap3xxx_mailbox_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
++ .main_clk = "mailboxes_ick",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mailbox_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
+ /* l4 core -> mcspi1 interface */
+ static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
+ {
+@@ -2168,6 +2236,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ /* dma_system class*/
+ &omap3xxx_dma_system_hwmod,
+
++ /* mailbox class */
++ &omap3xxx_mailbox_hwmod,
++
+ /* mcspi class */
+ &omap34xx_mcspi1,
+ &omap34xx_mcspi2,
+--
+1.7.1
+
diff --git a/patches/for_next/0099-OMAP-mailbox-build-device-using-omap_device-omap_hwm.patch b/patches/for_next/0099-OMAP-mailbox-build-device-using-omap_device-omap_hwm.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8cd8764a80aaddc6e3e034d4947d616de8804bce
--- /dev/null
+++ b/patches/for_next/0099-OMAP-mailbox-build-device-using-omap_device-omap_hwm.patch
@@ -0,0 +1,171 @@
+From 140b111b2b199ea83b361fa72dee932a656805e2 Mon Sep 17 00:00:00 2001
+From: Felipe Contreras <felipe.contreras@gmail.com>
+Date: Thu, 24 Feb 2011 12:51:33 -0800
+Subject: [PATCH 099/254] OMAP: mailbox: build device using omap_device/omap_hwmod
+
+Remove static platform_device and resource data within
+omap mailbox driver; use the one defined in the hwmod
+database along with omap_device framework for device
+build and registration.
+
+Add device latency functions to be used, so clock can be
+enabled and sysconfig is configured.
+
+Signed-off-by: Felipe Contreras <felipe.contreras@gmail.com>
+Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/devices.c | 98 +++++++----------------------------------
+ arch/arm/mach-omap2/mailbox.c | 7 +--
+ 2 files changed, 19 insertions(+), 86 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index 9ee876f..d216976 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -184,95 +184,29 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
+ }
+
+ #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+-
+-#define MBOX_REG_SIZE 0x120
+-
+-#ifdef CONFIG_ARCH_OMAP2
+-static struct resource omap2_mbox_resources[] = {
+- {
+- .start = OMAP24XX_MAILBOX_BASE,
+- .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .start = INT_24XX_MAIL_U0_MPU,
+- .flags = IORESOURCE_IRQ,
+- .name = "dsp",
+- },
+- {
+- .start = INT_24XX_MAIL_U3_MPU,
+- .flags = IORESOURCE_IRQ,
+- .name = "iva",
+- },
+-};
+-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
+-#else
+-#define omap2_mbox_resources NULL
+-#define omap2_mbox_resources_sz 0
+-#endif
+-
+-#ifdef CONFIG_ARCH_OMAP3
+-static struct resource omap3_mbox_resources[] = {
+- {
+- .start = OMAP34XX_MAILBOX_BASE,
+- .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .start = INT_24XX_MAIL_U0_MPU,
+- .flags = IORESOURCE_IRQ,
+- .name = "dsp",
+- },
+-};
+-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
+-#else
+-#define omap3_mbox_resources NULL
+-#define omap3_mbox_resources_sz 0
+-#endif
+-
+-#ifdef CONFIG_ARCH_OMAP4
+-
+-#define OMAP4_MBOX_REG_SIZE 0x130
+-static struct resource omap4_mbox_resources[] = {
+- {
+- .start = OMAP44XX_MAILBOX_BASE,
+- .end = OMAP44XX_MAILBOX_BASE +
+- OMAP4_MBOX_REG_SIZE - 1,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .start = OMAP44XX_IRQ_MAIL_U0,
+- .flags = IORESOURCE_IRQ,
+- .name = "mbox",
++static struct omap_device_pm_latency mbox_latencies[] = {
++ [0] = {
++ .activate_func = omap_device_enable_hwmods,
++ .deactivate_func = omap_device_idle_hwmods,
++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+ };
+-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
+-#else
+-#define omap4_mbox_resources NULL
+-#define omap4_mbox_resources_sz 0
+-#endif
+-
+-static struct platform_device mbox_device = {
+- .name = "omap-mailbox",
+- .id = -1,
+-};
+
+ static inline void omap_init_mbox(void)
+ {
+- if (cpu_is_omap24xx()) {
+- mbox_device.resource = omap2_mbox_resources;
+- mbox_device.num_resources = omap2_mbox_resources_sz;
+- } else if (cpu_is_omap34xx()) {
+- mbox_device.resource = omap3_mbox_resources;
+- mbox_device.num_resources = omap3_mbox_resources_sz;
+- } else if (cpu_is_omap44xx()) {
+- mbox_device.resource = omap4_mbox_resources;
+- mbox_device.num_resources = omap4_mbox_resources_sz;
+- } else {
+- pr_err("%s: platform not supported\n", __func__);
++ struct omap_hwmod *oh;
++ struct omap_device *od;
++
++ oh = omap_hwmod_lookup("mailbox");
++ if (!oh) {
++ pr_err("%s: unable to find hwmod\n", __func__);
+ return;
+ }
+- platform_device_register(&mbox_device);
++
++ od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
++ mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
++ WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
++ __func__, PTR_ERR(od));
+ }
+ #else
+ static inline void omap_init_mbox(void) { }
+diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
+index 20b8777..6bf294d 100644
+--- a/arch/arm/mach-omap2/mailbox.c
++++ b/arch/arm/mach-omap2/mailbox.c
+@@ -400,14 +400,14 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
+ else if (cpu_is_omap34xx()) {
+ list = omap3_mboxes;
+
+- list[0]->irq = platform_get_irq_byname(pdev, "dsp");
++ list[0]->irq = platform_get_irq(pdev, 0);
+ }
+ #endif
+ #if defined(CONFIG_ARCH_OMAP2)
+ else if (cpu_is_omap2430()) {
+ list = omap2_mboxes;
+
+- list[0]->irq = platform_get_irq_byname(pdev, "dsp");
++ list[0]->irq = platform_get_irq(pdev, 0);
+ } else if (cpu_is_omap2420()) {
+ list = omap2_mboxes;
+
+@@ -419,8 +419,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
+ else if (cpu_is_omap44xx()) {
+ list = omap4_mboxes;
+
+- list[0]->irq = list[1]->irq =
+- platform_get_irq_byname(pdev, "mbox");
++ list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
+ }
+ #endif
+ else {
+--
+1.7.1
+
diff --git a/patches/for_next/0100-OMAP-mailbox-use-runtime-pm-for-clk-and-sysc-handlin.patch b/patches/for_next/0100-OMAP-mailbox-use-runtime-pm-for-clk-and-sysc-handlin.patch
new file mode 100644
index 0000000000000000000000000000000000000000..56cae20d0be123bc8b2559bfacc40a9f6ccaa208
--- /dev/null
+++ b/patches/for_next/0100-OMAP-mailbox-use-runtime-pm-for-clk-and-sysc-handlin.patch
@@ -0,0 +1,133 @@
+From f4ae145f8beb83a8a8cc96e78b4ddb9094dcf18a Mon Sep 17 00:00:00 2001
+From: Omar Ramirez Luna <omar.ramirez@ti.com>
+Date: Thu, 24 Feb 2011 12:51:33 -0800
+Subject: [PATCH 100/254] OMAP: mailbox: use runtime pm for clk and sysc handling
+
+Use runtime pm APIs to enable/disable mailbox clocks and
+to configure SYSC register.
+
+Based on the patch sent by Felipe Contreras:
+https://patchwork.kernel.org/patch/101662/
+
+Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/mailbox.c | 67 ++++-------------------------------------
+ 1 files changed, 6 insertions(+), 61 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
+index 6bf294d..86d564a 100644
+--- a/arch/arm/mach-omap2/mailbox.c
++++ b/arch/arm/mach-omap2/mailbox.c
+@@ -14,12 +14,11 @@
+ #include <linux/err.h>
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
++#include <linux/pm_runtime.h>
+ #include <plat/mailbox.h>
+ #include <mach/irqs.h>
+
+ #define MAILBOX_REVISION 0x000
+-#define MAILBOX_SYSCONFIG 0x010
+-#define MAILBOX_SYSSTATUS 0x014
+ #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
+ #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
+ #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
+@@ -33,17 +32,6 @@
+ #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
+ #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
+
+-/* SYSCONFIG: register bit definition */
+-#define AUTOIDLE (1 << 0)
+-#define SOFTRESET (1 << 1)
+-#define SMARTIDLE (2 << 3)
+-#define OMAP4_SOFTRESET (1 << 0)
+-#define OMAP4_NOIDLE (1 << 2)
+-#define OMAP4_SMARTIDLE (2 << 2)
+-
+-/* SYSSTATUS: register bit definition */
+-#define RESETDONE (1 << 0)
+-
+ #define MBOX_REG_SIZE 0x120
+
+ #define OMAP4_MBOX_REG_SIZE 0x130
+@@ -70,8 +58,6 @@ struct omap_mbox2_priv {
+ unsigned long irqdisable;
+ };
+
+-static struct clk *mbox_ick_handle;
+-
+ static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
+ omap_mbox_type_t irq);
+
+@@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
+ static int omap2_mbox_startup(struct omap_mbox *mbox)
+ {
+ u32 l;
+- unsigned long timeout;
+
+- mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
+- if (IS_ERR(mbox_ick_handle)) {
+- printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
+- PTR_ERR(mbox_ick_handle));
+- return PTR_ERR(mbox_ick_handle);
+- }
+- clk_enable(mbox_ick_handle);
+-
+- if (cpu_is_omap44xx()) {
+- mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
+- timeout = jiffies + msecs_to_jiffies(20);
+- do {
+- l = mbox_read_reg(MAILBOX_SYSCONFIG);
+- if (!(l & OMAP4_SOFTRESET))
+- break;
+- } while (!time_after(jiffies, timeout));
+-
+- if (l & OMAP4_SOFTRESET) {
+- pr_err("Can't take mailbox out of reset\n");
+- return -ENODEV;
+- }
+- } else {
+- mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
+- timeout = jiffies + msecs_to_jiffies(20);
+- do {
+- l = mbox_read_reg(MAILBOX_SYSSTATUS);
+- if (l & RESETDONE)
+- break;
+- } while (!time_after(jiffies, timeout));
+-
+- if (!(l & RESETDONE)) {
+- pr_err("Can't take mailbox out of reset\n");
+- return -ENODEV;
+- }
+- }
++ pm_runtime_enable(mbox->dev->parent);
++ pm_runtime_get_sync(mbox->dev->parent);
+
+ l = mbox_read_reg(MAILBOX_REVISION);
+ pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
+
+- if (cpu_is_omap44xx())
+- l = OMAP4_SMARTIDLE;
+- else
+- l = SMARTIDLE | AUTOIDLE;
+- mbox_write_reg(l, MAILBOX_SYSCONFIG);
+-
+ omap2_mbox_enable_irq(mbox, IRQ_RX);
+
+ return 0;
+@@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
+
+ static void omap2_mbox_shutdown(struct omap_mbox *mbox)
+ {
+- clk_disable(mbox_ick_handle);
+- clk_put(mbox_ick_handle);
+- mbox_ick_handle = NULL;
++ pm_runtime_put_sync(mbox->dev->parent);
++ pm_runtime_disable(mbox->dev->parent);
+ }
+
+ /* Mailbox FIFO handle functions */
+--
+1.7.1
+
diff --git a/patches/for_next/0101-OMAP-hwmod-allow-hwmod-to-provide-address-space-acce.patch b/patches/for_next/0101-OMAP-hwmod-allow-hwmod-to-provide-address-space-acce.patch
new file mode 100644
index 0000000000000000000000000000000000000000..45ff698da9c2b21a14b47e5229779685b08c94ca
--- /dev/null
+++ b/patches/for_next/0101-OMAP-hwmod-allow-hwmod-to-provide-address-space-acce.patch
@@ -0,0 +1,55 @@
+From cb71640e0e6ac73495332e32884b019c1f14d40d Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 12:51:45 -0800
+Subject: [PATCH 101/254] OMAP: hwmod: allow hwmod to provide address space accessible from SDMA
+
+Adds support for resource API to get address space info other than just MPU.
+The drivers can now use platform_get_resource_byname() to get resource of
+type 'IORESOURCE_MEM' by name.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Acked-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 1 +
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 4 +++-
+ 2 files changed, 4 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 9e89a58..c7762ab 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1883,6 +1883,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
+ os = oh->slaves[i];
+
+ for (j = 0; j < os->addr_cnt; j++) {
++ (res + r)->name = (os->addr + j)->name;
+ (res + r)->start = (os->addr + j)->pa_start;
+ (res + r)->end = (os->addr + j)->pa_end;
+ (res + r)->flags = IORESOURCE_MEM;
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index fedd829..04b1ea1 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -178,7 +178,8 @@ struct omap_hwmod_omap2_firewall {
+ #define ADDR_TYPE_RT (1 << 1)
+
+ /**
+- * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
++ * struct omap_hwmod_addr_space - address space handled by the hwmod
++ * @name: name of the address space
+ * @pa_start: starting physical address
+ * @pa_end: ending physical address
+ * @flags: (see omap_hwmod_addr_space.flags macros above)
+@@ -187,6 +188,7 @@ struct omap_hwmod_omap2_firewall {
+ * structure. GPMC is one example.
+ */
+ struct omap_hwmod_addr_space {
++ const char *name;
+ u32 pa_start;
+ u32 pa_end;
+ u8 flags;
+--
+1.7.1
+
diff --git a/patches/for_next/0102-OMAP-McBSP-Convert-McBSP-to-platform-device-model.patch b/patches/for_next/0102-OMAP-McBSP-Convert-McBSP-to-platform-device-model.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d0856fc83ef6cc98ad48a1651ff0815a7392be6f
--- /dev/null
+++ b/patches/for_next/0102-OMAP-McBSP-Convert-McBSP-to-platform-device-model.patch
@@ -0,0 +1,1308 @@
+From 3c89a9f5599c32bf7c190771e17600a248a65ed7 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 12:51:45 -0800
+Subject: [PATCH 102/254] OMAP: McBSP: Convert McBSP to platform device model
+
+Implement McBSP as platform device and add support for
+registering through platform device layer using resource
+structures.
+
+Later in this patch series, OMAP2+ McBSP driver would be modified to
+use hwmod framework after populating the omap2+ hwmod database.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/mcbsp.c | 327 +++++++++++++----
+ arch/arm/mach-omap2/mcbsp.c | 613 +++++++++++++++++++++++++------
+ arch/arm/plat-omap/devices.c | 10 +-
+ arch/arm/plat-omap/include/plat/mcbsp.h | 14 +-
+ arch/arm/plat-omap/mcbsp.c | 59 +++-
+ 5 files changed, 818 insertions(+), 205 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
+index 8209736..e68f6c0 100644
+--- a/arch/arm/mach-omap1/mcbsp.c
++++ b/arch/arm/mach-omap1/mcbsp.c
+@@ -10,6 +10,7 @@
+ *
+ * Multichannel mode not supported.
+ */
++#include <linux/ioport.h>
+ #include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/clk.h>
+@@ -78,100 +79,288 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
+ };
+
+ #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
++struct resource omap7xx_mcbsp_res[][6] = {
++ {
++ {
++ .start = OMAP7XX_MCBSP1_BASE,
++ .end = OMAP7XX_MCBSP1_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_7XX_McBSP1RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_7XX_McBSP1TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP_DMA_MCBSP1_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP_DMA_MCBSP1_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP7XX_MCBSP2_BASE,
++ .end = OMAP7XX_MCBSP2_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_7XX_McBSP2RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_7XX_McBSP2TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP_DMA_MCBSP3_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP_DMA_MCBSP3_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++};
++
+ static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
+ {
+- .phys_base = OMAP7XX_MCBSP1_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+- .rx_irq = INT_7XX_McBSP1RX,
+- .tx_irq = INT_7XX_McBSP1TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ {
+- .phys_base = OMAP7XX_MCBSP2_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+- .rx_irq = INT_7XX_McBSP2RX,
+- .tx_irq = INT_7XX_McBSP2TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ };
+-#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata)
+-#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
++#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
++#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
+ #else
++#define omap7xx_mcbsp_res NULL
+ #define omap7xx_mcbsp_pdata NULL
+-#define OMAP7XX_MCBSP_PDATA_SZ 0
+-#define OMAP7XX_MCBSP_REG_NUM 0
++#define OMAP7XX_MCBSP_RES_SZ 0
++#define OMAP7XX_MCBSP_COUNT 0
+ #endif
+
+ #ifdef CONFIG_ARCH_OMAP15XX
++struct resource omap15xx_mcbsp_res[][6] = {
++ {
++ {
++ .start = OMAP1510_MCBSP1_BASE,
++ .end = OMAP1510_MCBSP1_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_McBSP1RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_McBSP1TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP_DMA_MCBSP1_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP_DMA_MCBSP1_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP1510_MCBSP2_BASE,
++ .end = OMAP1510_MCBSP2_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_1510_SPI_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_1510_SPI_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP_DMA_MCBSP2_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP_DMA_MCBSP2_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP1510_MCBSP3_BASE,
++ .end = OMAP1510_MCBSP3_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_McBSP3RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_McBSP3TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP_DMA_MCBSP3_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP_DMA_MCBSP3_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++};
++
+ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
+ {
+- .phys_base = OMAP1510_MCBSP1_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+- .rx_irq = INT_McBSP1RX,
+- .tx_irq = INT_McBSP1TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ {
+- .phys_base = OMAP1510_MCBSP2_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+- .rx_irq = INT_1510_SPI_RX,
+- .tx_irq = INT_1510_SPI_TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ {
+- .phys_base = OMAP1510_MCBSP3_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+- .rx_irq = INT_McBSP3RX,
+- .tx_irq = INT_McBSP3TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ };
+-#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
+-#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
++#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
++#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
+ #else
++#define omap15xx_mcbsp_res NULL
+ #define omap15xx_mcbsp_pdata NULL
+-#define OMAP15XX_MCBSP_PDATA_SZ 0
+-#define OMAP15XX_MCBSP_REG_NUM 0
++#define OMAP15XX_MCBSP_RES_SZ 0
++#define OMAP15XX_MCBSP_COUNT 0
+ #endif
+
+ #ifdef CONFIG_ARCH_OMAP16XX
++struct resource omap16xx_mcbsp_res[][6] = {
++ {
++ {
++ .start = OMAP1610_MCBSP1_BASE,
++ .end = OMAP1610_MCBSP1_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_McBSP1RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_McBSP1TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP_DMA_MCBSP1_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP_DMA_MCBSP1_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP1610_MCBSP2_BASE,
++ .end = OMAP1610_MCBSP2_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_1610_McBSP2_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_1610_McBSP2_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP_DMA_MCBSP2_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP_DMA_MCBSP2_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP1610_MCBSP3_BASE,
++ .end = OMAP1610_MCBSP3_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_McBSP3RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_McBSP3TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP_DMA_MCBSP3_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP_DMA_MCBSP3_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++};
++
+ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
+ {
+- .phys_base = OMAP1610_MCBSP1_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+- .rx_irq = INT_McBSP1RX,
+- .tx_irq = INT_McBSP1TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ {
+- .phys_base = OMAP1610_MCBSP2_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+- .rx_irq = INT_1610_McBSP2_RX,
+- .tx_irq = INT_1610_McBSP2_TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ {
+- .phys_base = OMAP1610_MCBSP3_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+- .rx_irq = INT_McBSP3RX,
+- .tx_irq = INT_McBSP3TX,
+ .ops = &omap1_mcbsp_ops,
+ },
+ };
+-#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
+-#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
++#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
++#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
+ #else
++#define omap16xx_mcbsp_res NULL
+ #define omap16xx_mcbsp_pdata NULL
+-#define OMAP16XX_MCBSP_PDATA_SZ 0
+-#define OMAP16XX_MCBSP_REG_NUM 0
++#define OMAP16XX_MCBSP_RES_SZ 0
++#define OMAP16XX_MCBSP_COUNT 0
+ #endif
+
+ static int __init omap1_mcbsp_init(void)
+@@ -179,16 +368,12 @@ static int __init omap1_mcbsp_init(void)
+ if (!cpu_class_is_omap1())
+ return -ENODEV;
+
+- if (cpu_is_omap7xx()) {
+- omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
+- omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
+- } else if (cpu_is_omap15xx()) {
+- omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
+- omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16);
+- } else if (cpu_is_omap16xx()) {
+- omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
+- omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
+- }
++ if (cpu_is_omap7xx())
++ omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
++ else if (cpu_is_omap15xx())
++ omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
++ else if (cpu_is_omap16xx())
++ omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
+
+ mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
+ GFP_KERNEL);
+@@ -196,16 +381,22 @@ static int __init omap1_mcbsp_init(void)
+ return -ENOMEM;
+
+ if (cpu_is_omap7xx())
+- omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
+- OMAP7XX_MCBSP_PDATA_SZ);
++ omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0],
++ OMAP7XX_MCBSP_RES_SZ,
++ omap7xx_mcbsp_pdata,
++ OMAP7XX_MCBSP_COUNT);
+
+ if (cpu_is_omap15xx())
+- omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
+- OMAP15XX_MCBSP_PDATA_SZ);
++ omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0],
++ OMAP15XX_MCBSP_RES_SZ,
++ omap15xx_mcbsp_pdata,
++ OMAP15XX_MCBSP_COUNT);
+
+ if (cpu_is_omap16xx())
+- omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
+- OMAP16XX_MCBSP_PDATA_SZ);
++ omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0],
++ OMAP16XX_MCBSP_RES_SZ,
++ omap16xx_mcbsp_pdata,
++ OMAP16XX_MCBSP_COUNT);
+
+ return omap_mcbsp_init();
+ }
+diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
+index 0526b75..765ebe7 100644
+--- a/arch/arm/mach-omap2/mcbsp.c
++++ b/arch/arm/mach-omap2/mcbsp.c
+@@ -105,173 +105,542 @@ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
+ /* Platform data */
+
+ #ifdef CONFIG_SOC_OMAP2420
+-static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
++struct resource omap2420_mcbsp_res[][6] = {
+ {
+- .phys_base = OMAP24XX_MCBSP1_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
+- .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
++ {
++ .start = OMAP24XX_MCBSP1_BASE,
++ .end = OMAP24XX_MCBSP1_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP1_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP1_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP1_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP1_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ {
+- .phys_base = OMAP24XX_MCBSP2_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
+- .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
++ {
++ .start = OMAP24XX_MCBSP2_BASE,
++ .end = OMAP24XX_MCBSP2_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP2_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP2_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP2_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP2_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ };
+-#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
+-#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
++#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1])
++#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res)
+ #else
+-#define omap2420_mcbsp_pdata NULL
+-#define OMAP2420_MCBSP_PDATA_SZ 0
+-#define OMAP2420_MCBSP_REG_NUM 0
++#define omap2420_mcbsp_res NULL
++#define OMAP2420_MCBSP_RES_SZ 0
++#define OMAP2420_MCBSP_COUNT 0
+ #endif
+
++#define omap2420_mcbsp_pdata NULL
++
+ #ifdef CONFIG_SOC_OMAP2430
+-static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
++struct resource omap2430_mcbsp_res[][6] = {
+ {
+- .phys_base = OMAP24XX_MCBSP1_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
+- .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
++ {
++ .start = OMAP24XX_MCBSP1_BASE,
++ .end = OMAP24XX_MCBSP1_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP1_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP1_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP1_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP1_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ {
+- .phys_base = OMAP24XX_MCBSP2_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
+- .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
++ {
++ .start = OMAP24XX_MCBSP2_BASE,
++ .end = OMAP24XX_MCBSP2_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP2_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP2_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP2_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP2_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ {
+- .phys_base = OMAP2430_MCBSP3_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
+- .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
++ {
++ .start = OMAP2430_MCBSP3_BASE,
++ .end = OMAP2430_MCBSP3_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP3_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP3_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP3_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP3_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ {
+- .phys_base = OMAP2430_MCBSP4_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
+- .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
++ {
++ .start = OMAP2430_MCBSP4_BASE,
++ .end = OMAP2430_MCBSP4_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP4_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP4_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP4_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP4_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ {
+- .phys_base = OMAP2430_MCBSP5_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
+- .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
++ {
++ .start = OMAP2430_MCBSP5_BASE,
++ .end = OMAP2430_MCBSP5_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP5_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP5_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP5_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP5_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ };
+-#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
+-#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
++#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1])
++#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res)
+ #else
+-#define omap2430_mcbsp_pdata NULL
+-#define OMAP2430_MCBSP_PDATA_SZ 0
+-#define OMAP2430_MCBSP_REG_NUM 0
++#define omap2430_mcbsp_res NULL
++#define OMAP2430_MCBSP_RES_SZ 0
++#define OMAP2430_MCBSP_COUNT 0
+ #endif
+
++#define omap2430_mcbsp_pdata NULL
++
+ #ifdef CONFIG_ARCH_OMAP3
++struct resource omap34xx_mcbsp_res[][7] = {
++ {
++ {
++ .start = OMAP34XX_MCBSP1_BASE,
++ .end = OMAP34XX_MCBSP1_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP1_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP1_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP1_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP1_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP34XX_MCBSP2_BASE,
++ .end = OMAP34XX_MCBSP2_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "sidetone",
++ .start = OMAP34XX_MCBSP2_ST_BASE,
++ .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP2_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP2_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP2_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP2_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP34XX_MCBSP3_BASE,
++ .end = OMAP34XX_MCBSP3_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "sidetone",
++ .start = OMAP34XX_MCBSP3_ST_BASE,
++ .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP3_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP3_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP3_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP3_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP34XX_MCBSP4_BASE,
++ .end = OMAP34XX_MCBSP4_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP4_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP4_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP4_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP4_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++ {
++ {
++ .start = OMAP34XX_MCBSP5_BASE,
++ .end = OMAP34XX_MCBSP5_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = INT_24XX_MCBSP5_IRQ_RX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = INT_24XX_MCBSP5_IRQ_TX,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP24XX_DMA_MCBSP5_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP24XX_DMA_MCBSP5_TX,
++ .flags = IORESOURCE_DMA,
++ },
++ },
++};
++
+ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
+ {
+- .phys_base = OMAP34XX_MCBSP1_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
+- .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
+ .buffer_size = 0x80, /* The FIFO has 128 locations */
+ },
+ {
+- .phys_base = OMAP34XX_MCBSP2_BASE,
+- .phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
+- .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
+ .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
+ },
+ {
+- .phys_base = OMAP34XX_MCBSP3_BASE,
+- .phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
+- .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
+ .buffer_size = 0x80, /* The FIFO has 128 locations */
+ },
+ {
+- .phys_base = OMAP34XX_MCBSP4_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
+- .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
+ .buffer_size = 0x80, /* The FIFO has 128 locations */
+ },
+ {
+- .phys_base = OMAP34XX_MCBSP5_BASE,
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
+- .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
+ .buffer_size = 0x80, /* The FIFO has 128 locations */
+ },
+ };
+-#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
+-#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
++#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1])
++#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res)
+ #else
+ #define omap34xx_mcbsp_pdata NULL
+-#define OMAP34XX_MCBSP_PDATA_SZ 0
+-#define OMAP34XX_MCBSP_REG_NUM 0
++#define omap34XX_mcbsp_res NULL
++#define OMAP34XX_MCBSP_RES_SZ 0
++#define OMAP34XX_MCBSP_COUNT 0
+ #endif
+
+-static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
++struct resource omap44xx_mcbsp_res[][6] = {
+ {
+- .phys_base = OMAP44XX_MCBSP1_BASE,
+- .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
+- .tx_irq = OMAP44XX_IRQ_MCBSP1,
++ {
++ .name = "mpu",
++ .start = OMAP44XX_MCBSP1_BASE,
++ .end = OMAP44XX_MCBSP1_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "dma",
++ .start = OMAP44XX_MCBSP1_DMA_BASE,
++ .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = 0,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = OMAP44XX_IRQ_MCBSP1,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP44XX_DMA_MCBSP1_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP44XX_DMA_MCBSP1_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ {
+- .phys_base = OMAP44XX_MCBSP2_BASE,
+- .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
+- .tx_irq = OMAP44XX_IRQ_MCBSP2,
++ {
++ .name = "mpu",
++ .start = OMAP44XX_MCBSP2_BASE,
++ .end = OMAP44XX_MCBSP2_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "dma",
++ .start = OMAP44XX_MCBSP2_DMA_BASE,
++ .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = 0,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = OMAP44XX_IRQ_MCBSP2,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP44XX_DMA_MCBSP2_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP44XX_DMA_MCBSP2_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ {
+- .phys_base = OMAP44XX_MCBSP3_BASE,
+- .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
+- .tx_irq = OMAP44XX_IRQ_MCBSP3,
++ {
++ .name = "mpu",
++ .start = OMAP44XX_MCBSP3_BASE,
++ .end = OMAP44XX_MCBSP3_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "dma",
++ .start = OMAP44XX_MCBSP3_DMA_BASE,
++ .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = 0,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = OMAP44XX_IRQ_MCBSP3,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP44XX_DMA_MCBSP3_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP44XX_DMA_MCBSP3_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ {
+- .phys_base = OMAP44XX_MCBSP4_BASE,
+- .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
+- .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
+- .tx_irq = OMAP44XX_IRQ_MCBSP4,
++ {
++ .start = OMAP44XX_MCBSP4_BASE,
++ .end = OMAP44XX_MCBSP4_BASE + SZ_256,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "rx",
++ .start = 0,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "tx",
++ .start = OMAP44XX_IRQ_MCBSP4,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "rx",
++ .start = OMAP44XX_DMA_MCBSP4_RX,
++ .flags = IORESOURCE_DMA,
++ },
++ {
++ .name = "tx",
++ .start = OMAP44XX_DMA_MCBSP4_TX,
++ .flags = IORESOURCE_DMA,
++ },
+ },
+ };
+-#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
+-#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
++#define omap44xx_mcbsp_pdata NULL
++#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1])
++#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res)
+
+ static int __init omap2_mcbsp_init(void)
+ {
+- if (cpu_is_omap2420()) {
+- omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
+- omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
+- } else if (cpu_is_omap2430()) {
+- omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
+- omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
+- } else if (cpu_is_omap34xx()) {
+- omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
+- omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
+- } else if (cpu_is_omap44xx()) {
+- omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
+- omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
+- }
++ if (cpu_is_omap2420())
++ omap_mcbsp_count = OMAP2420_MCBSP_COUNT;
++ else if (cpu_is_omap2430())
++ omap_mcbsp_count = OMAP2430_MCBSP_COUNT;
++ else if (cpu_is_omap34xx())
++ omap_mcbsp_count = OMAP34XX_MCBSP_COUNT;
++ else if (cpu_is_omap44xx())
++ omap_mcbsp_count = OMAP44XX_MCBSP_COUNT;
+
+ mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
+ GFP_KERNEL);
+@@ -279,17 +648,25 @@ static int __init omap2_mcbsp_init(void)
+ return -ENOMEM;
+
+ if (cpu_is_omap2420())
+- omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
+- OMAP2420_MCBSP_PDATA_SZ);
++ omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0],
++ OMAP2420_MCBSP_RES_SZ,
++ omap2420_mcbsp_pdata,
++ OMAP2420_MCBSP_COUNT);
+ if (cpu_is_omap2430())
+- omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
+- OMAP2430_MCBSP_PDATA_SZ);
++ omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0],
++ OMAP2420_MCBSP_RES_SZ,
++ omap2430_mcbsp_pdata,
++ OMAP2430_MCBSP_COUNT);
+ if (cpu_is_omap34xx())
+- omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
+- OMAP34XX_MCBSP_PDATA_SZ);
++ omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0],
++ OMAP34XX_MCBSP_RES_SZ,
++ omap34xx_mcbsp_pdata,
++ OMAP34XX_MCBSP_COUNT);
+ if (cpu_is_omap44xx())
+- omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
+- OMAP44XX_MCBSP_PDATA_SZ);
++ omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0],
++ OMAP44XX_MCBSP_RES_SZ,
++ omap44xx_mcbsp_pdata,
++ OMAP44XX_MCBSP_COUNT);
+
+ return omap_mcbsp_init();
+ }
+diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
+index 10245b8..7d9f815 100644
+--- a/arch/arm/plat-omap/devices.c
++++ b/arch/arm/plat-omap/devices.c
+@@ -35,8 +35,8 @@
+
+ static struct platform_device **omap_mcbsp_devices;
+
+-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+- int size)
++void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
++ struct omap_mcbsp_platform_data *config, int size)
+ {
+ int i;
+
+@@ -54,6 +54,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+ new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
+ if (!new_mcbsp)
+ continue;
++ platform_device_add_resources(new_mcbsp, &res[i * res_count],
++ res_count);
+ new_mcbsp->dev.platform_data = &config[i];
+ ret = platform_device_add(new_mcbsp);
+ if (ret) {
+@@ -65,8 +67,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+ }
+
+ #else
+-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+- int size)
++void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
++ struct omap_mcbsp_platform_data *config, int size)
+ { }
+ #endif
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index 6ecf105..dc1a282 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -63,9 +63,12 @@ static struct platform_device omap_mcbsp##port_nr = { \
+ #define OMAP34XX_MCBSP4_BASE 0x49026000
+ #define OMAP34XX_MCBSP5_BASE 0x48096000
+
+-#define OMAP44XX_MCBSP1_BASE 0x49022000
+-#define OMAP44XX_MCBSP2_BASE 0x49024000
+-#define OMAP44XX_MCBSP3_BASE 0x49026000
++#define OMAP44XX_MCBSP1_BASE 0x40122000
++#define OMAP44XX_MCBSP1_DMA_BASE 0x49022000
++#define OMAP44XX_MCBSP2_BASE 0x40124000
++#define OMAP44XX_MCBSP2_DMA_BASE 0x49024000
++#define OMAP44XX_MCBSP3_BASE 0x40126000
++#define OMAP44XX_MCBSP3_DMA_BASE 0x49026000
+ #define OMAP44XX_MCBSP4_BASE 0x48096000
+
+ #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+@@ -431,6 +434,7 @@ struct omap_mcbsp_st_data {
+ struct omap_mcbsp {
+ struct device *dev;
+ unsigned long phys_base;
++ unsigned long phys_dma_base;
+ void __iomem *io_base;
+ u8 id;
+ u8 free;
+@@ -474,8 +478,8 @@ extern int omap_mcbsp_count, omap_mcbsp_cache_size;
+ #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
+
+ int omap_mcbsp_init(void);
+-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+- int size);
++void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
++ struct omap_mcbsp_platform_data *config, int size);
+ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
+ #ifdef CONFIG_ARCH_OMAP3
+ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index b5a6e17..5f25ae5 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -1649,7 +1649,8 @@ static const struct attribute_group sidetone_attr_group = {
+
+ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
+ {
+- struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
++ struct platform_device *pdev;
++ struct resource *res;
+ struct omap_mcbsp_st_data *st_data;
+ int err;
+
+@@ -1659,7 +1660,10 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
+ goto err1;
+ }
+
+- st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
++ pdev = container_of(mcbsp->dev, struct platform_device, dev);
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
++ st_data->io_base_st = ioremap(res->start, resource_size(res));
+ if (!st_data->io_base_st) {
+ err = -ENOMEM;
+ goto err2;
+@@ -1748,6 +1752,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
+ struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
+ struct omap_mcbsp *mcbsp;
+ int id = pdev->id - 1;
++ struct resource *res;
+ int ret = 0;
+
+ if (!pdata) {
+@@ -1777,25 +1782,59 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
+ mcbsp->dma_tx_lch = -1;
+ mcbsp->dma_rx_lch = -1;
+
+- mcbsp->phys_base = pdata->phys_base;
+- mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
++ if (!res) {
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
++ "resource\n", __func__, pdev->id);
++ ret = -ENOMEM;
++ goto exit;
++ }
++ }
++ mcbsp->phys_base = res->start;
++ omap_mcbsp_cache_size = resource_size(res);
++ mcbsp->io_base = ioremap(res->start, resource_size(res));
+ if (!mcbsp->io_base) {
+ ret = -ENOMEM;
+ goto err_ioremap;
+ }
+
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
++ if (!res)
++ mcbsp->phys_dma_base = mcbsp->phys_base;
++ else
++ mcbsp->phys_dma_base = res->start;
++
+ /* Default I/O is IRQ based */
+ mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
+- mcbsp->tx_irq = pdata->tx_irq;
+- mcbsp->rx_irq = pdata->rx_irq;
+- mcbsp->dma_rx_sync = pdata->dma_rx_sync;
+- mcbsp->dma_tx_sync = pdata->dma_tx_sync;
++
++ mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
++ mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
++ if (!res) {
++ dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
++ __func__, pdev->id);
++ ret = -ENODEV;
++ goto err_res;
++ }
++ mcbsp->dma_rx_sync = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
++ if (!res) {
++ dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
++ __func__, pdev->id);
++ ret = -ENODEV;
++ goto err_res;
++ }
++ mcbsp->dma_tx_sync = res->start;
+
+ mcbsp->iclk = clk_get(&pdev->dev, "ick");
+ if (IS_ERR(mcbsp->iclk)) {
+ ret = PTR_ERR(mcbsp->iclk);
+ dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
+- goto err_iclk;
++ goto err_res;
+ }
+
+ mcbsp->fclk = clk_get(&pdev->dev, "fck");
+@@ -1817,7 +1856,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
+
+ err_fclk:
+ clk_put(mcbsp->iclk);
+-err_iclk:
++err_res:
+ iounmap(mcbsp->io_base);
+ err_ioremap:
+ kfree(mcbsp);
+--
+1.7.1
+
diff --git a/patches/for_next/0103-OMAP2420-hwmod-data-Add-McBSP.patch b/patches/for_next/0103-OMAP2420-hwmod-data-Add-McBSP.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d917e1b34a7925f9c82525ee338d63683d362d76
--- /dev/null
+++ b/patches/for_next/0103-OMAP2420-hwmod-data-Add-McBSP.patch
@@ -0,0 +1,191 @@
+From f8c337067c3de51c741797b56df8ce00206ae0e2 Mon Sep 17 00:00:00 2001
+From: Charulatha V <charu@ti.com>
+Date: Thu, 24 Feb 2011 12:51:46 -0800
+Subject: [PATCH 103/254] OMAP2420: hwmod data: Add McBSP
+
+Add McBSP hwmod data for OMAP2420.
+
+Also add macros in prcm-common.h for idlest bit of OMAP24XX McBSP devices
+
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 129 ++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/prcm-common.h | 4 +
+ 2 files changed, 133 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 19ad9d0..e44ecb4 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -109,6 +109,8 @@ static struct omap_hwmod omap2420_uart2_hwmod;
+ static struct omap_hwmod omap2420_uart3_hwmod;
+ static struct omap_hwmod omap2420_i2c1_hwmod;
+ static struct omap_hwmod omap2420_i2c2_hwmod;
++static struct omap_hwmod omap2420_mcbsp1_hwmod;
++static struct omap_hwmod omap2420_mcbsp2_hwmod;
+
+ /* l4 core -> mcspi1 interface */
+ static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
+@@ -1390,6 +1392,129 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+ };
+
++/*
++ * 'mcbsp' class
++ * multi channel buffered serial port controller
++ */
++
++static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
++ .name = "mcbsp",
++};
++
++/* mcbsp1 */
++static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
++ { .name = "tx", .irq = 59 },
++ { .name = "rx", .irq = 60 },
++};
++
++static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
++ { .name = "rx", .dma_req = 32 },
++ { .name = "tx", .dma_req = 31 },
++};
++
++static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48074000,
++ .pa_end = 0x480740ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp1 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_mcbsp1_hwmod,
++ .clk = "mcbsp1_ick",
++ .addr = omap2420_mcbsp1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp1 slave ports */
++static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
++ &omap2420_l4_core__mcbsp1,
++};
++
++static struct omap_hwmod omap2420_mcbsp1_hwmod = {
++ .name = "mcbsp1",
++ .class = &omap2420_mcbsp_hwmod_class,
++ .mpu_irqs = omap2420_mcbsp1_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs),
++ .sdma_reqs = omap2420_mcbsp1_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
++ .main_clk = "mcbsp1_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
++ },
++ },
++ .slaves = omap2420_mcbsp1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
++};
++
++/* mcbsp2 */
++static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
++ { .name = "tx", .irq = 62 },
++ { .name = "rx", .irq = 63 },
++};
++
++static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
++ { .name = "rx", .dma_req = 34 },
++ { .name = "tx", .dma_req = 33 },
++};
++
++static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48076000,
++ .pa_end = 0x480760ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp2 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_mcbsp2_hwmod,
++ .clk = "mcbsp2_ick",
++ .addr = omap2420_mcbsp2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp2 slave ports */
++static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
++ &omap2420_l4_core__mcbsp2,
++};
++
++static struct omap_hwmod omap2420_mcbsp2_hwmod = {
++ .name = "mcbsp2",
++ .class = &omap2420_mcbsp_hwmod_class,
++ .mpu_irqs = omap2420_mcbsp2_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs),
++ .sdma_reqs = omap2420_mcbsp2_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
++ .main_clk = "mcbsp2_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
++ },
++ },
++ .slaves = omap2420_mcbsp2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
++};
++
+ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+ &omap2420_l3_main_hwmod,
+ &omap2420_l4_core_hwmod,
+@@ -1421,6 +1546,10 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+ /* mailbox class */
+ &omap2420_mailbox_hwmod,
+
++ /* mcbsp class */
++ &omap2420_mcbsp1_hwmod,
++ &omap2420_mcbsp2_hwmod,
++
+ /* mcspi class */
+ &omap2420_mcspi1_hwmod,
+ &omap2420_mcspi2_hwmod,
+diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
+index 87486f5..d4af21d 100644
+--- a/arch/arm/mach-omap2/prcm-common.h
++++ b/arch/arm/mach-omap2/prcm-common.h
+@@ -121,6 +121,10 @@
+ #define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
+ #define OMAP24XX_ST_MCSPI1_SHIFT 17
+ #define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
++#define OMAP24XX_ST_MCBSP2_SHIFT 16
++#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
++#define OMAP24XX_ST_MCBSP1_SHIFT 15
++#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
+ #define OMAP24XX_ST_GPT12_SHIFT 14
+ #define OMAP24XX_ST_GPT12_MASK (1 << 14)
+ #define OMAP24XX_ST_GPT11_SHIFT 13
+--
+1.7.1
+
diff --git a/patches/for_next/0104-OMAP2430-hwmod-data-Add-McBSP.patch b/patches/for_next/0104-OMAP2430-hwmod-data-Add-McBSP.patch
new file mode 100644
index 0000000000000000000000000000000000000000..83ee586e0d1d6a74879b5406b19bca1638da9e0f
--- /dev/null
+++ b/patches/for_next/0104-OMAP2430-hwmod-data-Add-McBSP.patch
@@ -0,0 +1,446 @@
+From 4ad8194193cfb1b7bf705affe804d00e811e3675 Mon Sep 17 00:00:00 2001
+From: Charulatha V <charu@ti.com>
+Date: Thu, 24 Feb 2011 12:51:46 -0800
+Subject: [PATCH 104/254] OMAP2430: hwmod data: Add McBSP
+
+Add McBSP hwmod data for OMAP2430.
+
+Added a revision member inorder to facilitate the driver to
+differentiate between mcbsp in different omap.
+
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 378 ++++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/mcbsp.h | 2 +
+ 2 files changed, 380 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 6e564f7..3b6d6d1 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -18,6 +18,7 @@
+ #include <plat/serial.h>
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
++#include <plat/mcbsp.h>
+ #include <plat/mcspi.h>
+ #include <plat/l3_2xxx.h>
+
+@@ -51,6 +52,11 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
+ static struct omap_hwmod omap2430_gpio4_hwmod;
+ static struct omap_hwmod omap2430_gpio5_hwmod;
+ static struct omap_hwmod omap2430_dma_system_hwmod;
++static struct omap_hwmod omap2430_mcbsp1_hwmod;
++static struct omap_hwmod omap2430_mcbsp2_hwmod;
++static struct omap_hwmod omap2430_mcbsp3_hwmod;
++static struct omap_hwmod omap2430_mcbsp4_hwmod;
++static struct omap_hwmod omap2430_mcbsp5_hwmod;
+ static struct omap_hwmod omap2430_mcspi1_hwmod;
+ static struct omap_hwmod omap2430_mcspi2_hwmod;
+ static struct omap_hwmod omap2430_mcspi3_hwmod;
+@@ -1519,6 +1525,371 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
++/*
++ * usbhsotg
++ */
++static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
++ .rev_offs = 0x0400,
++ .sysc_offs = 0x0404,
++ .syss_offs = 0x0408,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class usbotg_class = {
++ .name = "usbotg",
++ .sysc = &omap2430_usbhsotg_sysc,
++};
++
++/* usb_otg_hs */
++static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
++
++ { .name = "mc", .irq = 92 },
++ { .name = "dma", .irq = 93 },
++};
++
++static struct omap_hwmod omap2430_usbhsotg_hwmod = {
++ .name = "usb_otg_hs",
++ .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
++ .main_clk = "usbhs_ick",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP2430_EN_USBHS_MASK,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
++ },
++ },
++ .masters = omap2430_usbhsotg_masters,
++ .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
++ .slaves = omap2430_usbhsotg_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
++ .class = &usbotg_class,
++ /*
++ * Erratum ID: i479 idle_req / idle_ack mechanism potentially
++ * broken when autoidle is enabled
++ * workaround is to disable the autoidle bit at module level.
++ */
++ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
++ | HWMOD_SWSUP_MSTANDBY,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/*
++ * 'mcbsp' class
++ * multi channel buffered serial port controller
++ */
++
++static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
++ .rev_offs = 0x007C,
++ .sysc_offs = 0x008C,
++ .sysc_flags = (SYSC_HAS_SOFTRESET),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
++ .name = "mcbsp",
++ .sysc = &omap2430_mcbsp_sysc,
++ .rev = MCBSP_CONFIG_TYPE2,
++};
++
++/* mcbsp1 */
++static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
++ { .name = "tx", .irq = 59 },
++ { .name = "rx", .irq = 60 },
++ { .name = "ovr", .irq = 61 },
++ { .name = "common", .irq = 64 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
++ { .name = "rx", .dma_req = 32 },
++ { .name = "tx", .dma_req = 31 },
++};
++
++static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48074000,
++ .pa_end = 0x480740ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp1 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mcbsp1_hwmod,
++ .clk = "mcbsp1_ick",
++ .addr = omap2430_mcbsp1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp1 slave ports */
++static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
++ &omap2430_l4_core__mcbsp1,
++};
++
++static struct omap_hwmod omap2430_mcbsp1_hwmod = {
++ .name = "mcbsp1",
++ .class = &omap2430_mcbsp_hwmod_class,
++ .mpu_irqs = omap2430_mcbsp1_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs),
++ .sdma_reqs = omap2430_mcbsp1_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
++ .main_clk = "mcbsp1_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
++ },
++ },
++ .slaves = omap2430_mcbsp1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
++/* mcbsp2 */
++static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
++ { .name = "tx", .irq = 62 },
++ { .name = "rx", .irq = 63 },
++ { .name = "common", .irq = 16 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
++ { .name = "rx", .dma_req = 34 },
++ { .name = "tx", .dma_req = 33 },
++};
++
++static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48076000,
++ .pa_end = 0x480760ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp2 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mcbsp2_hwmod,
++ .clk = "mcbsp2_ick",
++ .addr = omap2430_mcbsp2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp2 slave ports */
++static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
++ &omap2430_l4_core__mcbsp2,
++};
++
++static struct omap_hwmod omap2430_mcbsp2_hwmod = {
++ .name = "mcbsp2",
++ .class = &omap2430_mcbsp_hwmod_class,
++ .mpu_irqs = omap2430_mcbsp2_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs),
++ .sdma_reqs = omap2430_mcbsp2_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
++ .main_clk = "mcbsp2_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
++ },
++ },
++ .slaves = omap2430_mcbsp2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
++/* mcbsp3 */
++static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
++ { .name = "tx", .irq = 89 },
++ { .name = "rx", .irq = 90 },
++ { .name = "common", .irq = 17 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
++ { .name = "rx", .dma_req = 18 },
++ { .name = "tx", .dma_req = 17 },
++};
++
++static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x4808C000,
++ .pa_end = 0x4808C0ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp3 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mcbsp3_hwmod,
++ .clk = "mcbsp3_ick",
++ .addr = omap2430_mcbsp3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp3 slave ports */
++static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
++ &omap2430_l4_core__mcbsp3,
++};
++
++static struct omap_hwmod omap2430_mcbsp3_hwmod = {
++ .name = "mcbsp3",
++ .class = &omap2430_mcbsp_hwmod_class,
++ .mpu_irqs = omap2430_mcbsp3_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs),
++ .sdma_reqs = omap2430_mcbsp3_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
++ .main_clk = "mcbsp3_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 2,
++ .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
++ },
++ },
++ .slaves = omap2430_mcbsp3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
++/* mcbsp4 */
++static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
++ { .name = "tx", .irq = 54 },
++ { .name = "rx", .irq = 55 },
++ { .name = "common", .irq = 18 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
++ { .name = "rx", .dma_req = 20 },
++ { .name = "tx", .dma_req = 19 },
++};
++
++static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x4808E000,
++ .pa_end = 0x4808E0ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp4 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mcbsp4_hwmod,
++ .clk = "mcbsp4_ick",
++ .addr = omap2430_mcbsp4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp4 slave ports */
++static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
++ &omap2430_l4_core__mcbsp4,
++};
++
++static struct omap_hwmod omap2430_mcbsp4_hwmod = {
++ .name = "mcbsp4",
++ .class = &omap2430_mcbsp_hwmod_class,
++ .mpu_irqs = omap2430_mcbsp4_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
++ .sdma_reqs = omap2430_mcbsp4_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
++ .main_clk = "mcbsp4_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 2,
++ .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
++ },
++ },
++ .slaves = omap2430_mcbsp4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
++/* mcbsp5 */
++static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
++ { .name = "tx", .irq = 81 },
++ { .name = "rx", .irq = 82 },
++ { .name = "common", .irq = 19 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
++ { .name = "rx", .dma_req = 22 },
++ { .name = "tx", .dma_req = 21 },
++};
++
++static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48096000,
++ .pa_end = 0x480960ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp5 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mcbsp5_hwmod,
++ .clk = "mcbsp5_ick",
++ .addr = omap2430_mcbsp5_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp5 slave ports */
++static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
++ &omap2430_l4_core__mcbsp5,
++};
++
++static struct omap_hwmod omap2430_mcbsp5_hwmod = {
++ .name = "mcbsp5",
++ .class = &omap2430_mcbsp_hwmod_class,
++ .mpu_irqs = omap2430_mcbsp5_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
++ .sdma_reqs = omap2430_mcbsp5_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
++ .main_clk = "mcbsp5_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 2,
++ .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
++ },
++ },
++ .slaves = omap2430_mcbsp5_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
+ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ &omap2430_l3_main_hwmod,
+ &omap2430_l4_core_hwmod,
+@@ -1548,6 +1919,13 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ /* dma_system class*/
+ &omap2430_dma_system_hwmod,
+
++ /* mcbsp class */
++ &omap2430_mcbsp1_hwmod,
++ &omap2430_mcbsp2_hwmod,
++ &omap2430_mcbsp3_hwmod,
++ &omap2430_mcbsp4_hwmod,
++ &omap2430_mcbsp5_hwmod,
++
+ /* mailbox class */
+ &omap2430_mailbox_hwmod,
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index dc1a282..64491a5 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -37,6 +37,8 @@ static struct platform_device omap_mcbsp##port_nr = { \
+ .id = OMAP_MCBSP##port_nr, \
+ }
+
++#define MCBSP_CONFIG_TYPE2 0x2
++
+ #define OMAP7XX_MCBSP1_BASE 0xfffb1000
+ #define OMAP7XX_MCBSP2_BASE 0xfffb1800
+
+--
+1.7.1
+
diff --git a/patches/for_next/0105-OMAP3-hwmod-data-Add-McBSP.patch b/patches/for_next/0105-OMAP3-hwmod-data-Add-McBSP.patch
new file mode 100644
index 0000000000000000000000000000000000000000..4f61d5c2d3bba65a9fcea1e1cef848673f2bc643
--- /dev/null
+++ b/patches/for_next/0105-OMAP3-hwmod-data-Add-McBSP.patch
@@ -0,0 +1,506 @@
+From 66bdb1e2eca59aa177f832df22ac08b76da6dcdd Mon Sep 17 00:00:00 2001
+From: Charulatha V <charu@ti.com>
+Date: Thu, 24 Feb 2011 15:16:49 +0530
+Subject: [PATCH 105/254] OMAP3: hwmod data: Add McBSP
+
+Add McBSP hwmod data for OMAP3.
+
+Added a revision member inorder to facilitate the driver to
+differentiate between mcbsp in different omap.
+
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 439 ++++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/mcbsp.h | 1 +
+ 2 files changed, 440 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 3585409..ea6d772 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -23,6 +23,7 @@
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
+ #include <plat/smartreflex.h>
++#include <plat/mcbsp.h>
+ #include <plat/mcspi.h>
+
+ #include "omap_hwmod_common_data.h"
+@@ -72,6 +73,14 @@ static struct omap_hwmod omap34xx_mcspi4;
+
+ static struct omap_hwmod omap3xxx_dma_system_hwmod;
+
++static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
++static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
++static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
++static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
++static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
++static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
++static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
++
+ /* L3 -> L4_CORE interface */
+ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
+ .master = &omap3xxx_l3_main_hwmod,
+@@ -1729,6 +1738,427 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
+ .flags = HWMOD_NO_IDLEST,
+ };
+
++/*
++ * 'mcbsp' class
++ * multi channel buffered serial port controller
++ */
++
++static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
++ .sysc_offs = 0x008c,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
++ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++ .clockact = 0x2,
++};
++
++static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
++ .name = "mcbsp",
++ .sysc = &omap3xxx_mcbsp_sysc,
++ .rev = MCBSP_CONFIG_TYPE3,
++};
++
++/* mcbsp1 */
++static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
++ { .name = "irq", .irq = 16 },
++ { .name = "tx", .irq = 59 },
++ { .name = "rx", .irq = 60 },
++};
++
++static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
++ { .name = "rx", .dma_req = 32 },
++ { .name = "tx", .dma_req = 31 },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48074000,
++ .pa_end = 0x480740ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp1 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_mcbsp1_hwmod,
++ .clk = "mcbsp1_ick",
++ .addr = omap3xxx_mcbsp1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp1 slave ports */
++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
++ &omap3xxx_l4_core__mcbsp1,
++};
++
++static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
++ .name = "mcbsp1",
++ .class = &omap3xxx_mcbsp_hwmod_class,
++ .mpu_irqs = omap3xxx_mcbsp1_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
++ .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
++ .main_clk = "mcbsp1_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mcbsp1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++/* mcbsp2 */
++static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
++ { .name = "irq", .irq = 17 },
++ { .name = "tx", .irq = 62 },
++ { .name = "rx", .irq = 63 },
++};
++
++static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
++ { .name = "rx", .dma_req = 34 },
++ { .name = "tx", .dma_req = 33 },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x49022000,
++ .pa_end = 0x490220ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcbsp2 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_mcbsp2_hwmod,
++ .clk = "mcbsp2_ick",
++ .addr = omap3xxx_mcbsp2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp2 slave ports */
++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
++ &omap3xxx_l4_per__mcbsp2,
++};
++
++static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
++ .name = "mcbsp2",
++ .class = &omap3xxx_mcbsp_hwmod_class,
++ .mpu_irqs = omap3xxx_mcbsp2_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
++ .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
++ .main_clk = "mcbsp2_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mcbsp2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++/* mcbsp3 */
++static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
++ { .name = "irq", .irq = 22 },
++ { .name = "tx", .irq = 89 },
++ { .name = "rx", .irq = 90 },
++};
++
++static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
++ { .name = "rx", .dma_req = 18 },
++ { .name = "tx", .dma_req = 17 },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x49024000,
++ .pa_end = 0x490240ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcbsp3 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_mcbsp3_hwmod,
++ .clk = "mcbsp3_ick",
++ .addr = omap3xxx_mcbsp3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp3 slave ports */
++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
++ &omap3xxx_l4_per__mcbsp3,
++};
++
++static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
++ .name = "mcbsp3",
++ .class = &omap3xxx_mcbsp_hwmod_class,
++ .mpu_irqs = omap3xxx_mcbsp3_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
++ .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
++ .main_clk = "mcbsp3_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mcbsp3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++/* mcbsp4 */
++static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
++ { .name = "irq", .irq = 23 },
++ { .name = "tx", .irq = 54 },
++ { .name = "rx", .irq = 55 },
++};
++
++static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
++ { .name = "rx", .dma_req = 20 },
++ { .name = "tx", .dma_req = 19 },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x49026000,
++ .pa_end = 0x490260ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcbsp4 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_mcbsp4_hwmod,
++ .clk = "mcbsp4_ick",
++ .addr = omap3xxx_mcbsp4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp4 slave ports */
++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
++ &omap3xxx_l4_per__mcbsp4,
++};
++
++static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
++ .name = "mcbsp4",
++ .class = &omap3xxx_mcbsp_hwmod_class,
++ .mpu_irqs = omap3xxx_mcbsp4_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
++ .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
++ .main_clk = "mcbsp4_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mcbsp4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++/* mcbsp5 */
++static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
++ { .name = "irq", .irq = 27 },
++ { .name = "tx", .irq = 81 },
++ { .name = "rx", .irq = 82 },
++};
++
++static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
++ { .name = "rx", .dma_req = 22 },
++ { .name = "tx", .dma_req = 21 },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
++ {
++ .name = "mpu",
++ .pa_start = 0x48096000,
++ .pa_end = 0x480960ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> mcbsp5 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_mcbsp5_hwmod,
++ .clk = "mcbsp5_ick",
++ .addr = omap3xxx_mcbsp5_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* mcbsp5 slave ports */
++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
++ &omap3xxx_l4_core__mcbsp5,
++};
++
++static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
++ .name = "mcbsp5",
++ .class = &omap3xxx_mcbsp_hwmod_class,
++ .mpu_irqs = omap3xxx_mcbsp5_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
++ .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
++ .main_clk = "mcbsp5_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mcbsp5_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++/* 'mcbsp sidetone' class */
++
++static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
++ .sysc_offs = 0x0010,
++ .sysc_flags = SYSC_HAS_AUTOIDLE,
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
++ .name = "mcbsp_sidetone",
++ .sysc = &omap3xxx_mcbsp_sidetone_sysc,
++};
++
++/* mcbsp2_sidetone */
++static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
++ { .name = "irq", .irq = 4 },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
++ {
++ .name = "sidetone",
++ .pa_start = 0x49028000,
++ .pa_end = 0x490280ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcbsp2_sidetone */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
++ .clk = "mcbsp2_ick",
++ .addr = omap3xxx_mcbsp2_sidetone_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
++ .user = OCP_USER_MPU,
++};
++
++/* mcbsp2_sidetone slave ports */
++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
++ &omap3xxx_l4_per__mcbsp2_sidetone,
++};
++
++static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
++ .name = "mcbsp2_sidetone",
++ .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
++ .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
++ .main_clk = "mcbsp2_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mcbsp2_sidetone_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++/* mcbsp3_sidetone */
++static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
++ { .name = "irq", .irq = 5 },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
++ {
++ .name = "sidetone",
++ .pa_start = 0x4902A000,
++ .pa_end = 0x4902A0ff,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> mcbsp3_sidetone */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
++ .clk = "mcbsp3_ick",
++ .addr = omap3xxx_mcbsp3_sidetone_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
++ .user = OCP_USER_MPU,
++};
++
++/* mcbsp3_sidetone slave ports */
++static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
++ &omap3xxx_l4_per__mcbsp3_sidetone,
++};
++
++static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
++ .name = "mcbsp3_sidetone",
++ .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
++ .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
++ .main_clk = "mcbsp3_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mcbsp3_sidetone_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++
+ /* SR common */
+ static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
+ .clkact_shift = 20,
+@@ -2236,6 +2666,15 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ /* dma_system class*/
+ &omap3xxx_dma_system_hwmod,
+
++ /* mcbsp class */
++ &omap3xxx_mcbsp1_hwmod,
++ &omap3xxx_mcbsp2_hwmod,
++ &omap3xxx_mcbsp3_hwmod,
++ &omap3xxx_mcbsp4_hwmod,
++ &omap3xxx_mcbsp5_hwmod,
++ &omap3xxx_mcbsp2_sidetone_hwmod,
++ &omap3xxx_mcbsp3_sidetone_hwmod,
++
+ /* mailbox class */
+ &omap3xxx_mailbox_hwmod,
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index 64491a5..f084b6a 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -38,6 +38,7 @@ static struct platform_device omap_mcbsp##port_nr = { \
+ }
+
+ #define MCBSP_CONFIG_TYPE2 0x2
++#define MCBSP_CONFIG_TYPE3 0x3
+
+ #define OMAP7XX_MCBSP1_BASE 0xfffb1000
+ #define OMAP7XX_MCBSP2_BASE 0xfffb1800
+--
+1.7.1
+
diff --git a/patches/for_next/0106-OMAP4-hwmod-Naming-of-address-space.patch b/patches/for_next/0106-OMAP4-hwmod-Naming-of-address-space.patch
new file mode 100644
index 0000000000000000000000000000000000000000..ffcbd83141a30d3d44a5dddbcb24364ca0f7c313
--- /dev/null
+++ b/patches/for_next/0106-OMAP4-hwmod-Naming-of-address-space.patch
@@ -0,0 +1,119 @@
+From e1a197869c00707fbbf209824498abea05b1fa39 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 15:16:50 +0530
+Subject: [PATCH 106/254] OMAP4: hwmod: Naming of address space
+
+Added a name to address space belonging to SDMA and MPU facilitating
+the driver to get the address space info by name. Added a revision
+member inorder to facilitate the driver to differentiate between
+mcbsp in different omap.
+Also added a platform_get_irq in probe to get irq number by index since
+from OMAP4, there will be a single irq line.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 8 ++++++++
+ arch/arm/plat-omap/include/plat/mcbsp.h | 1 +
+ arch/arm/plat-omap/mcbsp.c | 4 ++++
+ 3 files changed, 13 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 79a8601..673b011 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -25,6 +25,7 @@
+ #include <plat/gpio.h>
+ #include <plat/dma.h>
+ #include <plat/mcspi.h>
++#include <plat/mcbsp.h>
+
+ #include "omap_hwmod_common_data.h"
+
+@@ -2737,6 +2738,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
+ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
+ .name = "mcbsp",
+ .sysc = &omap44xx_mcbsp_sysc,
++ .rev = MCBSP_CONFIG_TYPE4,
+ };
+
+ /* mcbsp1 */
+@@ -2752,6 +2754,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
+ {
++ .name = "mpu",
+ .pa_start = 0x40122000,
+ .pa_end = 0x401220ff,
+ .flags = ADDR_TYPE_RT
+@@ -2770,6 +2773,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
+ {
++ .name = "dma",
+ .pa_start = 0x49022000,
+ .pa_end = 0x490220ff,
+ .flags = ADDR_TYPE_RT
+@@ -2823,6 +2827,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
+ {
++ .name = "mpu",
+ .pa_start = 0x40124000,
+ .pa_end = 0x401240ff,
+ .flags = ADDR_TYPE_RT
+@@ -2841,6 +2846,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
+ {
++ .name = "dma",
+ .pa_start = 0x49024000,
+ .pa_end = 0x490240ff,
+ .flags = ADDR_TYPE_RT
+@@ -2894,6 +2900,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
+ {
++ .name = "mpu",
+ .pa_start = 0x40126000,
+ .pa_end = 0x401260ff,
+ .flags = ADDR_TYPE_RT
+@@ -2912,6 +2919,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
+
+ static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
+ {
++ .name = "dma",
+ .pa_start = 0x49026000,
+ .pa_end = 0x490260ff,
+ .flags = ADDR_TYPE_RT
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index f084b6a..afcbb7b 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -39,6 +39,7 @@ static struct platform_device omap_mcbsp##port_nr = { \
+
+ #define MCBSP_CONFIG_TYPE2 0x2
+ #define MCBSP_CONFIG_TYPE3 0x3
++#define MCBSP_CONFIG_TYPE4 0x4
+
+ #define OMAP7XX_MCBSP1_BASE 0xfffb1000
+ #define OMAP7XX_MCBSP2_BASE 0xfffb1800
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index 5f25ae5..62bd073 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -1812,6 +1812,10 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
+ mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
+ mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
+
++ /* From OMAP4 there will be a single irq line */
++ if (mcbsp->tx_irq == -ENXIO)
++ mcbsp->tx_irq = platform_get_irq(pdev, 0);
++
+ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
+ if (!res) {
+ dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
+--
+1.7.1
+
diff --git a/patches/for_next/0107-OMAP3-hwmod-add-dev_attr-for-McBSP-sidetone.patch b/patches/for_next/0107-OMAP3-hwmod-add-dev_attr-for-McBSP-sidetone.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2cc10b07b750358251faf19c305823bb94447cd9
--- /dev/null
+++ b/patches/for_next/0107-OMAP3-hwmod-add-dev_attr-for-McBSP-sidetone.patch
@@ -0,0 +1,81 @@
+From 751b29de17bd4c9d4b8af1b93948b2ff9dc1e023 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 15:16:51 +0530
+Subject: [PATCH 107/254] OMAP3: hwmod: add dev_attr for McBSP sidetone
+
+Since the sidetone block is tightly coupled to the mcbsp, sidetone information
+is directly added to mcbsp2 & 3 hwmod dev_attr.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 10 ++++++++++
+ arch/arm/plat-omap/include/plat/mcbsp.h | 9 +++++++++
+ 2 files changed, 19 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index ea6d772..3dd6730 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1852,6 +1852,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
+ &omap3xxx_l4_per__mcbsp2,
+ };
+
++static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
++ .sidetone = "mcbsp2_sidetone",
++};
++
+ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
+ .name = "mcbsp2",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+@@ -1871,6 +1875,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
+ },
+ .slaves = omap3xxx_mcbsp2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
++ .dev_attr = &omap34xx_mcbsp2_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+
+@@ -1910,6 +1915,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
+ &omap3xxx_l4_per__mcbsp3,
+ };
+
++static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
++ .sidetone = "mcbsp3_sidetone",
++};
++
+ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
+ .name = "mcbsp3",
+ .class = &omap3xxx_mcbsp_hwmod_class,
+@@ -1929,6 +1938,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
+ },
+ .slaves = omap3xxx_mcbsp3_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
++ .dev_attr = &omap34xx_mcbsp3_dev_attr,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index afcbb7b..1fe0637 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -475,6 +475,15 @@ struct omap_mcbsp {
+ #endif
+ void *reg_cache;
+ };
++
++/**
++ * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
++ * @sidetone: name of the sidetone device
++ */
++struct omap_mcbsp_dev_attr {
++ const char *sidetone;
++};
++
+ extern struct omap_mcbsp **mcbsp_ptr;
+ extern int omap_mcbsp_count, omap_mcbsp_cache_size;
+
+--
+1.7.1
+
diff --git a/patches/for_next/0108-OMAP2-McBSP-hwmod-adaptation-for-McBSP.patch b/patches/for_next/0108-OMAP2-McBSP-hwmod-adaptation-for-McBSP.patch
new file mode 100644
index 0000000000000000000000000000000000000000..05f7d20e315885c9d2bb568c6dce9d5e71d9f9e1
--- /dev/null
+++ b/patches/for_next/0108-OMAP2-McBSP-hwmod-adaptation-for-McBSP.patch
@@ -0,0 +1,670 @@
+From d64838c2dcc3ddcfc29f7452ada0c4be2900f15f Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 15:16:52 +0530
+Subject: [PATCH 108/254] OMAP2+: McBSP: hwmod adaptation for McBSP
+
+Modify OMAP2+ McBSP to use omap hwmod framework APIs
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Charulatha V <charu@ti.com>
+Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/mcbsp.c | 595 +++----------------------------
+ arch/arm/plat-omap/include/plat/mcbsp.h | 2 +-
+ 2 files changed, 46 insertions(+), 551 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
+index 765ebe7..275d6cf 100644
+--- a/arch/arm/mach-omap2/mcbsp.c
++++ b/arch/arm/mach-omap2/mcbsp.c
+@@ -22,10 +22,10 @@
+ #include <plat/dma.h>
+ #include <plat/cpu.h>
+ #include <plat/mcbsp.h>
++#include <plat/omap_device.h>
+
+ #include "control.h"
+
+-
+ /* McBSP internal signal muxing functions */
+
+ void omap2_mcbsp1_mux_clkr_src(u8 mux)
+@@ -101,573 +101,68 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+ }
+ EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
+
+-
+-/* Platform data */
+-
+-#ifdef CONFIG_SOC_OMAP2420
+-struct resource omap2420_mcbsp_res[][6] = {
++struct omap_device_pm_latency omap2_mcbsp_latency[] = {
+ {
+- {
+- .start = OMAP24XX_MCBSP1_BASE,
+- .end = OMAP24XX_MCBSP1_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP1_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP1_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP1_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP1_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP24XX_MCBSP2_BASE,
+- .end = OMAP24XX_MCBSP2_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP2_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP2_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP2_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP2_TX,
+- .flags = IORESOURCE_DMA,
+- },
++ .deactivate_func = omap_device_idle_hwmods,
++ .activate_func = omap_device_enable_hwmods,
++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+ },
+ };
+-#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1])
+-#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res)
+-#else
+-#define omap2420_mcbsp_res NULL
+-#define OMAP2420_MCBSP_RES_SZ 0
+-#define OMAP2420_MCBSP_COUNT 0
+-#endif
+
+-#define omap2420_mcbsp_pdata NULL
++static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
++{
++ int id, count = 1;
++ char *name = "omap-mcbsp";
++ struct omap_hwmod *oh_device[2];
++ struct omap_mcbsp_platform_data *pdata = NULL;
++ struct omap_device *od;
+
+-#ifdef CONFIG_SOC_OMAP2430
+-struct resource omap2430_mcbsp_res[][6] = {
+- {
+- {
+- .start = OMAP24XX_MCBSP1_BASE,
+- .end = OMAP24XX_MCBSP1_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP1_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP1_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP1_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP1_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP24XX_MCBSP2_BASE,
+- .end = OMAP24XX_MCBSP2_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP2_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP2_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP2_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP2_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP2430_MCBSP3_BASE,
+- .end = OMAP2430_MCBSP3_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP3_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP3_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP3_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP3_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP2430_MCBSP4_BASE,
+- .end = OMAP2430_MCBSP4_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP4_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP4_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP4_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP4_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP2430_MCBSP5_BASE,
+- .end = OMAP2430_MCBSP5_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP5_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP5_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP5_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP5_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+-};
+-#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1])
+-#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res)
+-#else
+-#define omap2430_mcbsp_res NULL
+-#define OMAP2430_MCBSP_RES_SZ 0
+-#define OMAP2430_MCBSP_COUNT 0
+-#endif
++ sscanf(oh->name, "mcbsp%d", &id);
+
+-#define omap2430_mcbsp_pdata NULL
++ pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
++ if (!pdata) {
++ pr_err("%s: No memory for mcbsp\n", __func__);
++ return -ENOMEM;
++ }
+
+-#ifdef CONFIG_ARCH_OMAP3
+-struct resource omap34xx_mcbsp_res[][7] = {
+- {
+- {
+- .start = OMAP34XX_MCBSP1_BASE,
+- .end = OMAP34XX_MCBSP1_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP1_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP1_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP1_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP1_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP34XX_MCBSP2_BASE,
+- .end = OMAP34XX_MCBSP2_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "sidetone",
+- .start = OMAP34XX_MCBSP2_ST_BASE,
+- .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP2_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP2_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP2_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP2_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP34XX_MCBSP3_BASE,
+- .end = OMAP34XX_MCBSP3_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "sidetone",
+- .start = OMAP34XX_MCBSP3_ST_BASE,
+- .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP3_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP3_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP3_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP3_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP34XX_MCBSP4_BASE,
+- .end = OMAP34XX_MCBSP4_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP4_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP4_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP4_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP4_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP34XX_MCBSP5_BASE,
+- .end = OMAP34XX_MCBSP5_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = INT_24XX_MCBSP5_IRQ_RX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = INT_24XX_MCBSP5_IRQ_TX,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP24XX_DMA_MCBSP5_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP24XX_DMA_MCBSP5_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+-};
++ if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
++ if (id == 2)
++ /* The FIFO has 1024 + 256 locations */
++ pdata->buffer_size = 0x500;
++ else
++ /* The FIFO has 128 locations */
++ pdata->buffer_size = 0x80;
++ }
+
+-static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
+- {
+- .buffer_size = 0x80, /* The FIFO has 128 locations */
+- },
+- {
+- .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
+- },
+- {
+- .buffer_size = 0x80, /* The FIFO has 128 locations */
+- },
+- {
+- .buffer_size = 0x80, /* The FIFO has 128 locations */
+- },
+- {
+- .buffer_size = 0x80, /* The FIFO has 128 locations */
+- },
+-};
+-#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1])
+-#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res)
+-#else
+-#define omap34xx_mcbsp_pdata NULL
+-#define omap34XX_mcbsp_res NULL
+-#define OMAP34XX_MCBSP_RES_SZ 0
+-#define OMAP34XX_MCBSP_COUNT 0
+-#endif
++ oh_device[0] = oh;
+
+-struct resource omap44xx_mcbsp_res[][6] = {
+- {
+- {
+- .name = "mpu",
+- .start = OMAP44XX_MCBSP1_BASE,
+- .end = OMAP44XX_MCBSP1_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "dma",
+- .start = OMAP44XX_MCBSP1_DMA_BASE,
+- .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = 0,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = OMAP44XX_IRQ_MCBSP1,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP44XX_DMA_MCBSP1_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP44XX_DMA_MCBSP1_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .name = "mpu",
+- .start = OMAP44XX_MCBSP2_BASE,
+- .end = OMAP44XX_MCBSP2_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "dma",
+- .start = OMAP44XX_MCBSP2_DMA_BASE,
+- .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = 0,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = OMAP44XX_IRQ_MCBSP2,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP44XX_DMA_MCBSP2_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP44XX_DMA_MCBSP2_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .name = "mpu",
+- .start = OMAP44XX_MCBSP3_BASE,
+- .end = OMAP44XX_MCBSP3_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "dma",
+- .start = OMAP44XX_MCBSP3_DMA_BASE,
+- .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = 0,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = OMAP44XX_IRQ_MCBSP3,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP44XX_DMA_MCBSP3_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP44XX_DMA_MCBSP3_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+- {
+- {
+- .start = OMAP44XX_MCBSP4_BASE,
+- .end = OMAP44XX_MCBSP4_BASE + SZ_256,
+- .flags = IORESOURCE_MEM,
+- },
+- {
+- .name = "rx",
+- .start = 0,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "tx",
+- .start = OMAP44XX_IRQ_MCBSP4,
+- .flags = IORESOURCE_IRQ,
+- },
+- {
+- .name = "rx",
+- .start = OMAP44XX_DMA_MCBSP4_RX,
+- .flags = IORESOURCE_DMA,
+- },
+- {
+- .name = "tx",
+- .start = OMAP44XX_DMA_MCBSP4_TX,
+- .flags = IORESOURCE_DMA,
+- },
+- },
+-};
+-#define omap44xx_mcbsp_pdata NULL
+-#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1])
+-#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res)
++ if (oh->dev_attr) {
++ oh_device[1] = omap_hwmod_lookup((
++ (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
++ count++;
++ }
++ od = omap_device_build_ss(name, id, oh_device, count, pdata,
++ sizeof(*pdata), omap2_mcbsp_latency,
++ ARRAY_SIZE(omap2_mcbsp_latency), false);
++ kfree(pdata);
++ if (IS_ERR(od)) {
++ pr_err("%s: Cant build omap_device for %s:%s.\n", __func__,
++ name, oh->name);
++ return PTR_ERR(od);
++ }
++ omap_mcbsp_count++;
++ return 0;
++}
+
+ static int __init omap2_mcbsp_init(void)
+ {
+- if (cpu_is_omap2420())
+- omap_mcbsp_count = OMAP2420_MCBSP_COUNT;
+- else if (cpu_is_omap2430())
+- omap_mcbsp_count = OMAP2430_MCBSP_COUNT;
+- else if (cpu_is_omap34xx())
+- omap_mcbsp_count = OMAP34XX_MCBSP_COUNT;
+- else if (cpu_is_omap44xx())
+- omap_mcbsp_count = OMAP44XX_MCBSP_COUNT;
++ omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
+
+ mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
+ GFP_KERNEL);
+ if (!mcbsp_ptr)
+ return -ENOMEM;
+
+- if (cpu_is_omap2420())
+- omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0],
+- OMAP2420_MCBSP_RES_SZ,
+- omap2420_mcbsp_pdata,
+- OMAP2420_MCBSP_COUNT);
+- if (cpu_is_omap2430())
+- omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0],
+- OMAP2420_MCBSP_RES_SZ,
+- omap2430_mcbsp_pdata,
+- OMAP2430_MCBSP_COUNT);
+- if (cpu_is_omap34xx())
+- omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0],
+- OMAP34XX_MCBSP_RES_SZ,
+- omap34xx_mcbsp_pdata,
+- OMAP34XX_MCBSP_COUNT);
+- if (cpu_is_omap44xx())
+- omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0],
+- OMAP44XX_MCBSP_RES_SZ,
+- omap44xx_mcbsp_pdata,
+- OMAP44XX_MCBSP_COUNT);
+-
+ return omap_mcbsp_init();
+ }
+ arch_initcall(omap2_mcbsp_init);
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index 1fe0637..c6cabfc 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -421,8 +421,8 @@ struct omap_mcbsp_platform_data {
+ #ifdef CONFIG_ARCH_OMAP3
+ /* Sidetone block for McBSP 2 and 3 */
+ unsigned long phys_base_st;
+- u16 buffer_size;
+ #endif
++ u16 buffer_size;
+ };
+
+ struct omap_mcbsp_st_data {
+--
+1.7.1
+
diff --git a/patches/for_next/0109-OMAP-McBSP-use-omap_device-APIs-to-modify-SYSCONFIG.patch b/patches/for_next/0109-OMAP-McBSP-use-omap_device-APIs-to-modify-SYSCONFIG.patch
new file mode 100644
index 0000000000000000000000000000000000000000..50adc80db262451204d87f2d69634d5c001ec6e8
--- /dev/null
+++ b/patches/for_next/0109-OMAP-McBSP-use-omap_device-APIs-to-modify-SYSCONFIG.patch
@@ -0,0 +1,165 @@
+From b62d2c380a4cb8caf1ac087b841d48973437b258 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 15:16:53 +0530
+Subject: [PATCH 109/254] OMAP: McBSP: use omap_device APIs to modify SYSCONFIG
+
+McBSP2/3 in OMAP3 has sidetone feature which requires autoidle
+to be disabled before starting the sidetone. Also SYSCONFIG
+register has to be set with smart idle or no idle depending on the
+dma op mode (threshold or element sync). For doing these operations
+dynamically at runtime, omap_device APIs are used to modify SYSCONFIG register.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+[tony@atomide.com: updated to compile without omap_device idle calls]
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/mcbsp.c | 59 +++++++++++++++++++------------------------
+ 1 files changed, 26 insertions(+), 33 deletions(-)
+
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index 62bd073..67ec74e 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -27,6 +27,7 @@
+
+ #include <plat/dma.h>
+ #include <plat/mcbsp.h>
++#include <plat/omap_device.h>
+
+ /* XXX These "sideways" includes are a sign that something is wrong */
+ #include "../mach-omap2/cm2xxx_3xxx.h"
+@@ -228,9 +229,19 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
+ EXPORT_SYMBOL(omap_mcbsp_config);
+
+ #ifdef CONFIG_ARCH_OMAP3
++static struct omap_device *find_omap_device_by_dev(struct device *dev)
++{
++ struct platform_device *pdev = container_of(dev,
++ struct platform_device, dev);
++ return container_of(pdev, struct omap_device, pdev);
++}
++
+ static void omap_st_on(struct omap_mcbsp *mcbsp)
+ {
+ unsigned int w;
++ struct omap_device *od;
++
++ od = find_omap_device_by_dev(mcbsp->dev);
+
+ /*
+ * Sidetone uses McBSP ICLK - which must not idle when sidetones
+@@ -244,9 +255,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
+ w = MCBSP_READ(mcbsp, SSELCR);
+ MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
+
+- w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
+-
+ /* Enable Sidetone from Sidetone Core */
+ w = MCBSP_ST_READ(mcbsp, SSELCR);
+ MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
+@@ -255,13 +263,13 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
+ static void omap_st_off(struct omap_mcbsp *mcbsp)
+ {
+ unsigned int w;
++ struct omap_device *od;
++
++ od = find_omap_device_by_dev(mcbsp->dev);
+
+ w = MCBSP_ST_READ(mcbsp, SSELCR);
+ MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
+
+- w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
+-
+ w = MCBSP_READ(mcbsp, SSELCR);
+ MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
+
+@@ -273,9 +281,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
+ static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
+ {
+ u16 val, i;
++ struct omap_device *od;
+
+- val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
++ od = find_omap_device_by_dev(mcbsp->dev);
+
+ val = MCBSP_ST_READ(mcbsp, SSELCR);
+
+@@ -303,9 +311,9 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
+ {
+ u16 w;
+ struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
++ struct omap_device *od;
+
+- w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
++ od = find_omap_device_by_dev(mcbsp->dev);
+
+ w = MCBSP_ST_READ(mcbsp, SSELCR);
+
+@@ -648,48 +656,33 @@ EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
+
+ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
+ {
++ struct omap_device *od;
++
++ od = find_omap_device_by_dev(mcbsp->dev);
+ /*
+ * Enable wakup behavior, smart idle and all wakeups
+ * REVISIT: some wakeups may be unnecessary
+ */
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+- u16 syscon;
+-
+- syscon = MCBSP_READ(mcbsp, SYSCON);
+- syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
+-
+- if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
+- syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
+- CLOCKACTIVITY(0x02));
+- MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
+- } else {
+- syscon |= SIDLEMODE(0x01);
+- }
+-
+- MCBSP_WRITE(mcbsp, SYSCON, syscon);
++ MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
+ }
+ }
+
+ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
+ {
++ struct omap_device *od;
++
++ od = find_omap_device_by_dev(mcbsp->dev);
++
+ /*
+ * Disable wakup behavior, smart idle and all wakeups
+ */
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+- u16 syscon;
+-
+- syscon = MCBSP_READ(mcbsp, SYSCON);
+- syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
+ /*
+ * HW bug workaround - If no_idle mode is taken, we need to
+ * go to smart_idle before going to always_idle, or the
+ * device will not hit retention anymore.
+ */
+- syscon |= SIDLEMODE(0x02);
+- MCBSP_WRITE(mcbsp, SYSCON, syscon);
+-
+- syscon &= ~(SIDLEMODE(0x03));
+- MCBSP_WRITE(mcbsp, SYSCON, syscon);
+
+ MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
+ }
+--
+1.7.1
+
diff --git a/patches/for_next/0110-OMAP-McBSP-Add-pm-runtime-support.patch b/patches/for_next/0110-OMAP-McBSP-Add-pm-runtime-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..fac5a4ba0925f29df0f9e9346ae9cc381023226d
--- /dev/null
+++ b/patches/for_next/0110-OMAP-McBSP-Add-pm-runtime-support.patch
@@ -0,0 +1,151 @@
+From a0046591b682f5b370eb7ee063f9669aff834e01 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 15:16:54 +0530
+Subject: [PATCH 110/254] OMAP: McBSP: Add pm runtime support
+
+Add pm runtime support for McBSP driver.
+Reference to fclk is not removed because it is required when the
+functional clock is switched from one source to another.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/mcbsp.c | 5 +++--
+ arch/arm/plat-omap/include/plat/mcbsp.h | 1 -
+ arch/arm/plat-omap/mcbsp.c | 23 ++++++-----------------
+ 3 files changed, 9 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
+index 275d6cf..4ada6a9 100644
+--- a/arch/arm/mach-omap2/mcbsp.c
++++ b/arch/arm/mach-omap2/mcbsp.c
+@@ -23,6 +23,7 @@
+ #include <plat/cpu.h>
+ #include <plat/mcbsp.h>
+ #include <plat/omap_device.h>
++#include <linux/pm_runtime.h>
+
+ #include "control.h"
+
+@@ -83,7 +84,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+ return -EINVAL;
+ }
+
+- clk_disable(mcbsp->fclk);
++ pm_runtime_put_sync(mcbsp->dev);
+
+ r = clk_set_parent(mcbsp->fclk, fck_src);
+ if (IS_ERR_VALUE(r)) {
+@@ -93,7 +94,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+ return -EINVAL;
+ }
+
+- clk_enable(mcbsp->fclk);
++ pm_runtime_get_sync(mcbsp->dev);
+
+ clk_put(fck_src);
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index c6cabfc..964a940 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -465,7 +465,6 @@ struct omap_mcbsp {
+ /* Protect the field .free, while checking if the mcbsp is in use */
+ spinlock_t lock;
+ struct omap_mcbsp_platform_data *pdata;
+- struct clk *iclk;
+ struct clk *fclk;
+ #ifdef CONFIG_ARCH_OMAP3
+ struct omap_mcbsp_st_data *st_data;
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index 67ec74e..6d23016 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -28,6 +28,7 @@
+ #include <plat/dma.h>
+ #include <plat/mcbsp.h>
+ #include <plat/omap_device.h>
++#include <linux/pm_runtime.h>
+
+ /* XXX These "sideways" includes are a sign that something is wrong */
+ #include "../mach-omap2/cm2xxx_3xxx.h"
+@@ -757,8 +758,7 @@ int omap_mcbsp_request(unsigned int id)
+ if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
+ mcbsp->pdata->ops->request(id);
+
+- clk_enable(mcbsp->iclk);
+- clk_enable(mcbsp->fclk);
++ pm_runtime_get_sync(mcbsp->dev);
+
+ /* Do procedure specific to omap34xx arch, if applicable */
+ omap34xx_mcbsp_request(mcbsp);
+@@ -806,8 +806,7 @@ err_clk_disable:
+ /* Do procedure specific to omap34xx arch, if applicable */
+ omap34xx_mcbsp_free(mcbsp);
+
+- clk_disable(mcbsp->fclk);
+- clk_disable(mcbsp->iclk);
++ pm_runtime_put_sync(mcbsp->dev);
+
+ spin_lock(&mcbsp->lock);
+ mcbsp->free = true;
+@@ -837,8 +836,7 @@ void omap_mcbsp_free(unsigned int id)
+ /* Do procedure specific to omap34xx arch, if applicable */
+ omap34xx_mcbsp_free(mcbsp);
+
+- clk_disable(mcbsp->fclk);
+- clk_disable(mcbsp->iclk);
++ pm_runtime_put_sync(mcbsp->dev);
+
+ if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
+ /* Free IRQs */
+@@ -1827,32 +1825,24 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
+ }
+ mcbsp->dma_tx_sync = res->start;
+
+- mcbsp->iclk = clk_get(&pdev->dev, "ick");
+- if (IS_ERR(mcbsp->iclk)) {
+- ret = PTR_ERR(mcbsp->iclk);
+- dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
+- goto err_res;
+- }
+-
+ mcbsp->fclk = clk_get(&pdev->dev, "fck");
+ if (IS_ERR(mcbsp->fclk)) {
+ ret = PTR_ERR(mcbsp->fclk);
+ dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
+- goto err_fclk;
++ goto err_res;
+ }
+
+ mcbsp->pdata = pdata;
+ mcbsp->dev = &pdev->dev;
+ mcbsp_ptr[id] = mcbsp;
+ platform_set_drvdata(pdev, mcbsp);
++ pm_runtime_enable(mcbsp->dev);
+
+ /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
+ omap34xx_device_init(mcbsp);
+
+ return 0;
+
+-err_fclk:
+- clk_put(mcbsp->iclk);
+ err_res:
+ iounmap(mcbsp->io_base);
+ err_ioremap:
+@@ -1875,7 +1865,6 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
+ omap34xx_device_exit(mcbsp);
+
+ clk_put(mcbsp->fclk);
+- clk_put(mcbsp->iclk);
+
+ iounmap(mcbsp->io_base);
+ kfree(mcbsp);
+--
+1.7.1
+
diff --git a/patches/for_next/0111-OMAP-McBSP-APIs-to-pass-DMA-params-from-McBSP-driver.patch b/patches/for_next/0111-OMAP-McBSP-APIs-to-pass-DMA-params-from-McBSP-driver.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f4c6d3a20a4f1f916ad9273b9135c36e950fe4f6
--- /dev/null
+++ b/patches/for_next/0111-OMAP-McBSP-APIs-to-pass-DMA-params-from-McBSP-driver.patch
@@ -0,0 +1,160 @@
+From e2e6fea12727fc71687669779b9ac4af4c3248a6 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 15:16:55 +0530
+Subject: [PATCH 111/254] OMAP: McBSP: APIs to pass DMA params from McBSP driver to client drivers
+
+After McBSP driver is hwmod adapted, the information about the hw would be
+obtained from the hwmod database by the mcbsp driver. Since DMA programming is
+handled by the client driver, APIs are provided to pass the DMA channel number
+and base address of data register required by the client driver for DMA
+programming.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Charulatha V <charu@ti.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/mcbsp.c | 2 +
+ arch/arm/plat-omap/include/plat/mcbsp.h | 7 +++
+ arch/arm/plat-omap/mcbsp.c | 64 +++++++++++++++++++++++++++++++
+ 3 files changed, 73 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
+index 4ada6a9..565b906 100644
+--- a/arch/arm/mach-omap2/mcbsp.c
++++ b/arch/arm/mach-omap2/mcbsp.c
+@@ -126,6 +126,8 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
+ return -ENOMEM;
+ }
+
++ pdata->mcbsp_config_type = oh->class->rev;
++
+ if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
+ if (id == 2)
+ /* The FIFO has 1024 + 256 locations */
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index 964a940..21c9b10 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -81,6 +81,8 @@ static struct platform_device omap_mcbsp##port_nr = { \
+ #define OMAP_MCBSP_REG_DRR1 0x02
+ #define OMAP_MCBSP_REG_DXR2 0x04
+ #define OMAP_MCBSP_REG_DXR1 0x06
++#define OMAP_MCBSP_REG_DRR 0x02
++#define OMAP_MCBSP_REG_DXR 0x06
+ #define OMAP_MCBSP_REG_SPCR2 0x08
+ #define OMAP_MCBSP_REG_SPCR1 0x0a
+ #define OMAP_MCBSP_REG_RCR2 0x0c
+@@ -423,6 +425,7 @@ struct omap_mcbsp_platform_data {
+ unsigned long phys_base_st;
+ #endif
+ u16 buffer_size;
++ unsigned int mcbsp_config_type;
+ };
+
+ struct omap_mcbsp_st_data {
+@@ -473,6 +476,7 @@ struct omap_mcbsp {
+ u16 max_rx_thres;
+ #endif
+ void *reg_cache;
++ unsigned int mcbsp_config_type;
+ };
+
+ /**
+@@ -541,6 +545,9 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
+ void omap2_mcbsp1_mux_clkr_src(u8 mux);
+ void omap2_mcbsp1_mux_fsr_src(u8 mux);
+
++int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
++int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
++
+ #ifdef CONFIG_ARCH_OMAP3
+ /* Sidetone specific API */
+ int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index 6d23016..d598d9f 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -229,6 +229,69 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
+ }
+ EXPORT_SYMBOL(omap_mcbsp_config);
+
++/**
++ * omap_mcbsp_dma_params - returns the dma channel number
++ * @id - mcbsp id
++ * @stream - indicates the direction of data flow (rx or tx)
++ *
++ * Returns the dma channel number for the rx channel or tx channel
++ * based on the value of @stream for the requested mcbsp given by @id
++ */
++int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
++{
++ struct omap_mcbsp *mcbsp;
++
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
++ mcbsp = id_to_mcbsp_ptr(id);
++
++ if (stream)
++ return mcbsp->dma_rx_sync;
++ else
++ return mcbsp->dma_tx_sync;
++}
++EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
++
++/**
++ * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
++ * @id - mcbsp id
++ * @stream - indicates the direction of data flow (rx or tx)
++ *
++ * Returns the address of mcbsp data transmit register or data receive register
++ * to be used by DMA for transferring/receiving data based on the value of
++ * @stream for the requested mcbsp given by @id
++ */
++int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
++{
++ struct omap_mcbsp *mcbsp;
++ int data_reg;
++
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
++ mcbsp = id_to_mcbsp_ptr(id);
++
++ data_reg = mcbsp->phys_dma_base;
++
++ if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
++ if (stream)
++ data_reg += OMAP_MCBSP_REG_DRR1;
++ else
++ data_reg += OMAP_MCBSP_REG_DXR1;
++ } else {
++ if (stream)
++ data_reg += OMAP_MCBSP_REG_DRR;
++ else
++ data_reg += OMAP_MCBSP_REG_DXR;
++ }
++
++ return data_reg;
++}
++EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
++
+ #ifdef CONFIG_ARCH_OMAP3
+ static struct omap_device *find_omap_device_by_dev(struct device *dev)
+ {
+@@ -1835,6 +1898,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
+ mcbsp->pdata = pdata;
+ mcbsp->dev = &pdev->dev;
+ mcbsp_ptr[id] = mcbsp;
++ mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
+ platform_set_drvdata(pdev, mcbsp);
+ pm_runtime_enable(mcbsp->dev);
+
+--
+1.7.1
+
diff --git a/patches/for_next/0112-ASoC-McBSP-get-hw-params-from-McBSP-driver.patch b/patches/for_next/0112-ASoC-McBSP-get-hw-params-from-McBSP-driver.patch
new file mode 100644
index 0000000000000000000000000000000000000000..6dba32a609d50b14532cd07fa5e6cff02c8808bb
--- /dev/null
+++ b/patches/for_next/0112-ASoC-McBSP-get-hw-params-from-McBSP-driver.patch
@@ -0,0 +1,165 @@
+From 7e78c3f0c5309fbd48b4ffcb94a497a0585d1d6f Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 15:16:56 +0530
+Subject: [PATCH 112/254] ASoC: McBSP: get hw params from McBSP driver
+
+Removed the use of macros to obtain base address and DMA channel number.
+Instead use the McBSP driver API's that passes base address and DMA
+channel number to the client driver.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ sound/soc/omap/omap-mcbsp.c | 126 ++-----------------------------------------
+ 1 files changed, 4 insertions(+), 122 deletions(-)
+
+diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
+index ede6afd..2175f09 100644
+--- a/sound/soc/omap/omap-mcbsp.c
++++ b/sound/soc/omap/omap-mcbsp.c
+@@ -69,110 +69,6 @@ static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
+ */
+ static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
+
+-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
+-static const int omap1_dma_reqs[][2] = {
+- { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
+- { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
+- { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
+-};
+-static const unsigned long omap1_mcbsp_port[][2] = {
+- { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
+- OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
+- { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
+- OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
+- { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
+- OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
+-};
+-#else
+-static const int omap1_dma_reqs[][2] = {};
+-static const unsigned long omap1_mcbsp_port[][2] = {};
+-#endif
+-
+-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+-static const int omap24xx_dma_reqs[][2] = {
+- { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
+- { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
+-#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+- { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
+- { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
+- { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
+-#endif
+-};
+-#else
+-static const int omap24xx_dma_reqs[][2] = {};
+-#endif
+-
+-#if defined(CONFIG_ARCH_OMAP4)
+-static const int omap44xx_dma_reqs[][2] = {
+- { OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX },
+- { OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX },
+- { OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX },
+- { OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX },
+-};
+-#else
+-static const int omap44xx_dma_reqs[][2] = {};
+-#endif
+-
+-#if defined(CONFIG_SOC_OMAP2420)
+-static const unsigned long omap2420_mcbsp_port[][2] = {
+- { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
+- OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
+- { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
+- OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
+-};
+-#else
+-static const unsigned long omap2420_mcbsp_port[][2] = {};
+-#endif
+-
+-#if defined(CONFIG_SOC_OMAP2430)
+-static const unsigned long omap2430_mcbsp_port[][2] = {
+- { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
+-};
+-#else
+-static const unsigned long omap2430_mcbsp_port[][2] = {};
+-#endif
+-
+-#if defined(CONFIG_ARCH_OMAP3)
+-static const unsigned long omap34xx_mcbsp_port[][2] = {
+- { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
+-};
+-#else
+-static const unsigned long omap34xx_mcbsp_port[][2] = {};
+-#endif
+-
+-#if defined(CONFIG_ARCH_OMAP4)
+-static const unsigned long omap44xx_mcbsp_port[][2] = {
+- { OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
+- { OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
+- OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
+-};
+-#else
+-static const unsigned long omap44xx_mcbsp_port[][2] = {};
+-#endif
+-
+ static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+@@ -346,24 +242,10 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
+ unsigned int format, div, framesize, master;
+
+ dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
+- if (cpu_class_is_omap1()) {
+- dma = omap1_dma_reqs[bus_id][substream->stream];
+- port = omap1_mcbsp_port[bus_id][substream->stream];
+- } else if (cpu_is_omap2420()) {
+- dma = omap24xx_dma_reqs[bus_id][substream->stream];
+- port = omap2420_mcbsp_port[bus_id][substream->stream];
+- } else if (cpu_is_omap2430()) {
+- dma = omap24xx_dma_reqs[bus_id][substream->stream];
+- port = omap2430_mcbsp_port[bus_id][substream->stream];
+- } else if (cpu_is_omap343x()) {
+- dma = omap24xx_dma_reqs[bus_id][substream->stream];
+- port = omap34xx_mcbsp_port[bus_id][substream->stream];
+- } else if (cpu_is_omap44xx()) {
+- dma = omap44xx_dma_reqs[bus_id][substream->stream];
+- port = omap44xx_mcbsp_port[bus_id][substream->stream];
+- } else {
+- return -ENODEV;
+- }
++
++ dma = omap_mcbsp_dma_ch_params(bus_id, substream->stream);
++ port = omap_mcbsp_dma_reg_params(bus_id, substream->stream);
++
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
+--
+1.7.1
+
diff --git a/patches/for_next/0113-OMAP-hwmod-Removal-of-macros-for-data-that-is-obtain.patch b/patches/for_next/0113-OMAP-hwmod-Removal-of-macros-for-data-that-is-obtain.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9e81a09444d1bb74a18176d6759bd0cf21bc014f
--- /dev/null
+++ b/patches/for_next/0113-OMAP-hwmod-Removal-of-macros-for-data-that-is-obtain.patch
@@ -0,0 +1,58 @@
+From fa7664e9c95633c686c32812d113d91e7c66dda1 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 24 Feb 2011 15:16:57 +0530
+Subject: [PATCH 113/254] OMAP: hwmod: Removal of macros for data that is obtained from hwmod database
+
+Information like base address and DMA channel nubers should no longer
+be obtained using macros. These information should be obtained from
+hwmod database. Hence the macros that define the base address are removed.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Charulatha V <charu@ti.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/mcbsp.h | 25 +------------------------
+ 1 files changed, 1 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
+index 21c9b10..f8f690a 100644
+--- a/arch/arm/plat-omap/include/plat/mcbsp.h
++++ b/arch/arm/plat-omap/include/plat/mcbsp.h
+@@ -52,30 +52,7 @@ static struct platform_device omap_mcbsp##port_nr = { \
+ #define OMAP1610_MCBSP2_BASE 0xfffb1000
+ #define OMAP1610_MCBSP3_BASE 0xe1017000
+
+-#define OMAP24XX_MCBSP1_BASE 0x48074000
+-#define OMAP24XX_MCBSP2_BASE 0x48076000
+-#define OMAP2430_MCBSP3_BASE 0x4808c000
+-#define OMAP2430_MCBSP4_BASE 0x4808e000
+-#define OMAP2430_MCBSP5_BASE 0x48096000
+-
+-#define OMAP34XX_MCBSP1_BASE 0x48074000
+-#define OMAP34XX_MCBSP2_BASE 0x49022000
+-#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
+-#define OMAP34XX_MCBSP3_BASE 0x49024000
+-#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
+-#define OMAP34XX_MCBSP3_BASE 0x49024000
+-#define OMAP34XX_MCBSP4_BASE 0x49026000
+-#define OMAP34XX_MCBSP5_BASE 0x48096000
+-
+-#define OMAP44XX_MCBSP1_BASE 0x40122000
+-#define OMAP44XX_MCBSP1_DMA_BASE 0x49022000
+-#define OMAP44XX_MCBSP2_BASE 0x40124000
+-#define OMAP44XX_MCBSP2_DMA_BASE 0x49024000
+-#define OMAP44XX_MCBSP3_BASE 0x40126000
+-#define OMAP44XX_MCBSP3_DMA_BASE 0x49026000
+-#define OMAP44XX_MCBSP4_BASE 0x48096000
+-
+-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
++#ifdef CONFIG_ARCH_OMAP1
+
+ #define OMAP_MCBSP_REG_DRR2 0x00
+ #define OMAP_MCBSP_REG_DRR1 0x02
+--
+1.7.1
+
diff --git a/patches/for_next/0114-OMAP2-IOMMU-don-t-print-fault-warning-on-specific-la.patch b/patches/for_next/0114-OMAP2-IOMMU-don-t-print-fault-warning-on-specific-la.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9b919400fa26d5ba6425958af647b0db67714826
--- /dev/null
+++ b/patches/for_next/0114-OMAP2-IOMMU-don-t-print-fault-warning-on-specific-la.patch
@@ -0,0 +1,54 @@
+From bfb412549693fc0b2a92d1810e64a9b0516d6647 Mon Sep 17 00:00:00 2001
+From: David Cohen <dacohen@gmail.com>
+Date: Wed, 16 Feb 2011 19:35:50 +0000
+Subject: [PATCH 114/254] OMAP2+: IOMMU: don't print fault warning on specific layer
+
+IOMMU upper layer and user are responsible to handle a fault and to
+define whether it will end up as an error or not. OMAP2+ specific
+layer should not print anything in such case.
+
+Signed-off-by: David Cohen <dacohen@gmail.com>
+Acked-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/iommu2.c | 16 ----------------
+ 1 files changed, 0 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
+index 14ee686..49a1e5e 100644
+--- a/arch/arm/mach-omap2/iommu2.c
++++ b/arch/arm/mach-omap2/iommu2.c
+@@ -145,15 +145,7 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on)
+
+ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
+ {
+- int i;
+ u32 stat, da;
+- const char *err_msg[] = {
+- "tlb miss",
+- "translation fault",
+- "emulation miss",
+- "table walk fault",
+- "multi hit fault",
+- };
+
+ stat = iommu_read_reg(obj, MMU_IRQSTATUS);
+ stat &= MMU_IRQ_MASK;
+@@ -163,14 +155,6 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
+ da = iommu_read_reg(obj, MMU_FAULT_AD);
+ *ra = da;
+
+- dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
+-
+- for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
+- if (stat & (1 << i))
+- printk("%s ", err_msg[i]);
+- }
+- printk("\n");
+-
+ iommu_write_reg(obj, stat, MMU_IRQSTATUS);
+
+ return stat;
+--
+1.7.1
+
diff --git a/patches/for_next/0115-omap-IOMMU-add-support-to-callback-during-fault-hand.patch b/patches/for_next/0115-omap-IOMMU-add-support-to-callback-during-fault-hand.patch
new file mode 100644
index 0000000000000000000000000000000000000000..6385fea857d0209fdc2972bddb076e5ef898ddca
--- /dev/null
+++ b/patches/for_next/0115-omap-IOMMU-add-support-to-callback-during-fault-hand.patch
@@ -0,0 +1,196 @@
+From 3a8dbbfeaaf563a8f615595bdc4866cef8353a4f Mon Sep 17 00:00:00 2001
+From: David Cohen <dacohen@gmail.com>
+Date: Wed, 16 Feb 2011 19:35:51 +0000
+Subject: [PATCH 115/254] omap: IOMMU: add support to callback during fault handling
+
+Add support to register an isr for IOMMU fault situations and adapt it
+to allow such (*isr)() to be used as fault callback. Drivers using IOMMU
+module might want to be informed when errors happen in order to debug it
+or react.
+
+Signed-off-by: David Cohen <dacohen@gmail.com>
+Acked-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/iommu2.c | 17 +++++++++-
+ arch/arm/plat-omap/include/plat/iommu.h | 14 ++++++++-
+ arch/arm/plat-omap/iommu.c | 52 ++++++++++++++++++++++---------
+ 3 files changed, 65 insertions(+), 18 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
+index 49a1e5e..adb083e 100644
+--- a/arch/arm/mach-omap2/iommu2.c
++++ b/arch/arm/mach-omap2/iommu2.c
+@@ -146,18 +146,31 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on)
+ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
+ {
+ u32 stat, da;
++ u32 errs = 0;
+
+ stat = iommu_read_reg(obj, MMU_IRQSTATUS);
+ stat &= MMU_IRQ_MASK;
+- if (!stat)
++ if (!stat) {
++ *ra = 0;
+ return 0;
++ }
+
+ da = iommu_read_reg(obj, MMU_FAULT_AD);
+ *ra = da;
+
++ if (stat & MMU_IRQ_TLBMISS)
++ errs |= OMAP_IOMMU_ERR_TLB_MISS;
++ if (stat & MMU_IRQ_TRANSLATIONFAULT)
++ errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
++ if (stat & MMU_IRQ_EMUMISS)
++ errs |= OMAP_IOMMU_ERR_EMU_MISS;
++ if (stat & MMU_IRQ_TABLEWALKFAULT)
++ errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
++ if (stat & MMU_IRQ_MULTIHITFAULT)
++ errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
+ iommu_write_reg(obj, stat, MMU_IRQSTATUS);
+
+- return stat;
++ return errs;
+ }
+
+ static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
+diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
+index 19cbb5e..174f1b9 100644
+--- a/arch/arm/plat-omap/include/plat/iommu.h
++++ b/arch/arm/plat-omap/include/plat/iommu.h
+@@ -31,6 +31,7 @@ struct iommu {
+ struct clk *clk;
+ void __iomem *regbase;
+ struct device *dev;
++ void *isr_priv;
+
+ unsigned int refcount;
+ struct mutex iommu_lock; /* global for this whole object */
+@@ -47,7 +48,7 @@ struct iommu {
+ struct list_head mmap;
+ struct mutex mmap_lock; /* protect mmap */
+
+- int (*isr)(struct iommu *obj);
++ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
+
+ void *ctx; /* iommu context: registres saved area */
+ u32 da_start;
+@@ -109,6 +110,13 @@ struct iommu_platform_data {
+ u32 da_end;
+ };
+
++/* IOMMU errors */
++#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
++#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
++#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
++#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
++#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
++
+ #if defined(CONFIG_ARCH_OMAP1)
+ #error "iommu for this processor not implemented yet"
+ #else
+@@ -161,6 +169,10 @@ extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
+ extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
+ extern struct iommu *iommu_get(const char *name);
+ extern void iommu_put(struct iommu *obj);
++extern int iommu_set_isr(const char *name,
++ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
++ void *priv),
++ void *isr_priv);
+
+ extern void iommu_save_ctx(struct iommu *obj);
+ extern void iommu_restore_ctx(struct iommu *obj);
+diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
+index 4b3218e..e3eb038 100644
+--- a/arch/arm/plat-omap/iommu.c
++++ b/arch/arm/plat-omap/iommu.c
+@@ -783,25 +783,19 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
+ */
+ static irqreturn_t iommu_fault_handler(int irq, void *data)
+ {
+- u32 stat, da;
++ u32 da, errs;
+ u32 *iopgd, *iopte;
+- int err = -EIO;
+ struct iommu *obj = data;
+
+ if (!obj->refcount)
+ return IRQ_NONE;
+
+- /* Dynamic loading TLB or PTE */
+- if (obj->isr)
+- err = obj->isr(obj);
+-
+- if (!err)
+- return IRQ_HANDLED;
+-
+ clk_enable(obj->clk);
+- stat = iommu_report_fault(obj, &da);
++ errs = iommu_report_fault(obj, &da);
+ clk_disable(obj->clk);
+- if (!stat)
++
++ /* Fault callback or TLB/PTE Dynamic loading */
++ if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv))
+ return IRQ_HANDLED;
+
+ iommu_disable(obj);
+@@ -809,15 +803,16 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
+ iopgd = iopgd_offset(obj, da);
+
+ if (!iopgd_is_table(*iopgd)) {
+- dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", obj->name,
+- da, iopgd, *iopgd);
++ dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
++ "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
+ return IRQ_NONE;
+ }
+
+ iopte = iopte_offset(iopgd, da);
+
+- dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
+- obj->name, da, iopgd, *iopgd, iopte, *iopte);
++ dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
++ "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
++ iopte, *iopte);
+
+ return IRQ_NONE;
+ }
+@@ -920,6 +915,33 @@ void iommu_put(struct iommu *obj)
+ }
+ EXPORT_SYMBOL_GPL(iommu_put);
+
++int iommu_set_isr(const char *name,
++ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
++ void *priv),
++ void *isr_priv)
++{
++ struct device *dev;
++ struct iommu *obj;
++
++ dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
++ device_match_by_alias);
++ if (!dev)
++ return -ENODEV;
++
++ obj = to_iommu(dev);
++ mutex_lock(&obj->iommu_lock);
++ if (obj->refcount != 0) {
++ mutex_unlock(&obj->iommu_lock);
++ return -EBUSY;
++ }
++ obj->isr = isr;
++ obj->isr_priv = isr_priv;
++ mutex_unlock(&obj->iommu_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(iommu_set_isr);
++
+ /*
+ * OMAP Device MMU(IOMMU) detection
+ */
+--
+1.7.1
+
diff --git a/patches/for_next/0116-omap-Fix-compile-if-MTD_NAND_OMAP2-is-not-selected.patch b/patches/for_next/0116-omap-Fix-compile-if-MTD_NAND_OMAP2-is-not-selected.patch
new file mode 100644
index 0000000000000000000000000000000000000000..09992622c04656f0d8145ca9d3e1c26e2ff59c28
--- /dev/null
+++ b/patches/for_next/0116-omap-Fix-compile-if-MTD_NAND_OMAP2-is-not-selected.patch
@@ -0,0 +1,28 @@
+From 9282d558819d302dcba426434d5acf3b00d8113b Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Fri, 25 Feb 2011 10:11:15 -0800
+Subject: [PATCH 116/254] omap: Fix compile if MTD_NAND_OMAP2 is not selected
+
+Fix compile if MTD_NAND_OMAP2 is not selected
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-flash.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
+index c32c068..729892f 100644
+--- a/arch/arm/mach-omap2/board-flash.c
++++ b/arch/arm/mach-omap2/board-flash.c
+@@ -154,7 +154,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
+ }
+ #else
+ void
+-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
++__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
+ {
+ }
+ #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
+--
+1.7.1
+
diff --git a/patches/for_next/0117-omap-rx51-Add-SI4713-FM-transmitter.patch b/patches/for_next/0117-omap-rx51-Add-SI4713-FM-transmitter.patch
new file mode 100644
index 0000000000000000000000000000000000000000..06b649052aa65448825cc6f61c351312fd934eb5
--- /dev/null
+++ b/patches/for_next/0117-omap-rx51-Add-SI4713-FM-transmitter.patch
@@ -0,0 +1,111 @@
+From 9b582cf852e81af84cd12a724ffe9c677baea041 Mon Sep 17 00:00:00 2001
+From: Jarkko Nikula <jhnikula@gmail.com>
+Date: Mon, 21 Feb 2011 08:42:36 +0200
+Subject: [PATCH 117/254] omap: rx51: Add SI4713 FM transmitter
+
+Add SI4713 FM transmitter supplies, platform data and setup to RX-51/N900.
+It is connected to line output signals of TLV320AIC34 codec A part.
+Driver can be either built-in or a module. It can be tuned with v4l2-ctl
+from ivtv-utils. Following examples illustrate the use of it:
+
+ v4l2-ctl -d /dev/radio0 --set-ctrl=mute=0 (power up)
+ v4l2-ctl -d /dev/radio0 -f 107900 (tune 107.9 MHz)
+
+ v4l2-ctl -d /dev/radio0 --set-ctrl=mute=1 (power down)
+
+Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-rx51-peripherals.c | 44 ++++++++++++++++++++++++++
+ 1 files changed, 44 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
+index e75e240..d0998f8 100644
+--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
++++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
+@@ -36,6 +36,8 @@
+
+ #include <sound/tlv320aic3x.h>
+ #include <sound/tpa6130a2-plat.h>
++#include <media/radio-si4713.h>
++#include <media/si4713.h>
+
+ #include <../drivers/staging/iio/light/tsl2563.h>
+
+@@ -47,6 +49,8 @@
+
+ #define RX51_WL1251_POWER_GPIO 87
+ #define RX51_WL1251_IRQ_GPIO 42
++#define RX51_FMTX_RESET_GPIO 163
++#define RX51_FMTX_IRQ 53
+
+ /* list all spi devices here */
+ enum {
+@@ -357,10 +361,14 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
+ REGULATOR_SUPPLY("DVDD", "2-0018"),
+ REGULATOR_SUPPLY("IOVDD", "2-0019"),
+ REGULATOR_SUPPLY("DVDD", "2-0019"),
++ /* Si4713 IO supply */
++ REGULATOR_SUPPLY("vio", "2-0063"),
+ };
+
+ static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
+ REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
++ /* Si4713 supply */
++ REGULATOR_SUPPLY("vdd", "2-0063"),
+ };
+
+ static struct regulator_consumer_supply rx51_vdac_supply[] = {
+@@ -511,6 +519,41 @@ static struct regulator_init_data rx51_vio = {
+ .consumer_supplies = rx51_vio_supplies,
+ };
+
++static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
++ .gpio_reset = RX51_FMTX_RESET_GPIO,
++};
++
++static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
++ I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
++ .platform_data = &rx51_si4713_i2c_data,
++};
++
++static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
++ .i2c_bus = 2,
++ .subdev_board_info = &rx51_si4713_board_info,
++};
++
++static struct platform_device rx51_si4713_dev __initdata_or_module = {
++ .name = "radio-si4713",
++ .id = -1,
++ .dev = {
++ .platform_data = &rx51_si4713_data,
++ },
++};
++
++static __init void rx51_init_si4713(void)
++{
++ int err;
++
++ err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
++ if (err) {
++ printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
++ return;
++ }
++ rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
++ platform_device_register(&rx51_si4713_dev);
++}
++
+ static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
+ {
+ /* FIXME this gpio setup is just a placeholder for now */
+@@ -921,6 +964,7 @@ void __init rx51_peripherals_init(void)
+ board_smc91x_init();
+ rx51_add_gpio_keys();
+ rx51_init_wl1251();
++ rx51_init_si4713();
+ spi_register_board_info(rx51_peripherals_spi_board_info,
+ ARRAY_SIZE(rx51_peripherals_spi_board_info));
+
+--
+1.7.1
+
diff --git a/patches/for_next/0118-OMAP3-Touchbook-fix-board-initialization.patch b/patches/for_next/0118-OMAP3-Touchbook-fix-board-initialization.patch
new file mode 100644
index 0000000000000000000000000000000000000000..ffa81b2efb798948870925b12a392b9933ad34a9
--- /dev/null
+++ b/patches/for_next/0118-OMAP3-Touchbook-fix-board-initialization.patch
@@ -0,0 +1,37 @@
+From 319fb72434355b96db6f6c8854c200a91d05222f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Radek=20Pila=C5=99=20(Mrkva)?= <mrkva@mrkva.eu>
+Date: Thu, 24 Feb 2011 19:02:49 +0100
+Subject: [PATCH 118/254] OMAP3 Touchbook: fix board initialization
+
+init_early hook runs too early for omap3_mux_init(), so the board
+won't boot. Moved to init_machine, then it works just fine.
+
+Signed-off-by: Radek Pilar <mrkva@mrkva.eu>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3touchbook.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index 6a60f79..a35afe2 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -417,7 +417,6 @@ static struct omap_board_mux board_mux[] __initdata = {
+
+ static void __init omap3_touchbook_init_early(void)
+ {
+- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ omap_board_config = omap3_touchbook_config;
+ omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
+ omap2_init_common_infrastructure();
+@@ -514,6 +513,7 @@ static struct omap_musb_board_data musb_board_data = {
+
+ static void __init omap3_touchbook_init(void)
+ {
++ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ pm_power_off = omap3_touchbook_poweroff;
+
+ omap3_touchbook_i2c_init();
+--
+1.7.1
+
diff --git a/patches/for_next/0119-omap2-Minimize-board-specific-init_early-calls.patch b/patches/for_next/0119-omap2-Minimize-board-specific-init_early-calls.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2b3a0b1812b6fffcbd67ebb3ee6b61edd7181be9
--- /dev/null
+++ b/patches/for_next/0119-omap2-Minimize-board-specific-init_early-calls.patch
@@ -0,0 +1,462 @@
+From 0d513c9af0e1fd9ecb296dd295217b8f33957dcc Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Thu, 24 Feb 2011 14:36:03 -0800
+Subject: [PATCH 119/254] omap2+: Minimize board specific init_early calls
+
+We should only call init_common_infrastructure and
+init_common_devices from init_early.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-2430sdp.c | 5 +++--
+ arch/arm/mach-omap2/board-3430sdp.c | 6 +++---
+ arch/arm/mach-omap2/board-3630sdp.c | 4 ++--
+ arch/arm/mach-omap2/board-4430sdp.c | 5 +++--
+ arch/arm/mach-omap2/board-am3517crane.c | 6 +++---
+ arch/arm/mach-omap2/board-am3517evm.c | 10 +++++-----
+ arch/arm/mach-omap2/board-apollon.c | 4 ++--
+ arch/arm/mach-omap2/board-cm-t35.c | 11 +++++------
+ arch/arm/mach-omap2/board-cm-t3517.c | 5 ++---
+ arch/arm/mach-omap2/board-generic.c | 4 ++--
+ arch/arm/mach-omap2/board-h4.c | 5 +++--
+ arch/arm/mach-omap2/board-ldp.c | 4 ++--
+ arch/arm/mach-omap2/board-omap3evm.c | 5 +++--
+ arch/arm/mach-omap2/board-omap3stalker.c | 4 ++--
+ arch/arm/mach-omap2/board-omap3touchbook.c | 5 +++--
+ arch/arm/mach-omap2/board-overo.c | 4 ++--
+ arch/arm/mach-omap2/board-rx51.c | 6 +++---
+ arch/arm/mach-omap2/board-ti8168evm.c | 4 ++--
+ 18 files changed, 50 insertions(+), 47 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
+index cc42d47..59de1dc 100644
+--- a/arch/arm/mach-omap2/board-2430sdp.c
++++ b/arch/arm/mach-omap2/board-2430sdp.c
+@@ -142,8 +142,6 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
+
+ static void __init omap_2430sdp_init_early(void)
+ {
+- omap_board_config = sdp2430_config;
+- omap_board_config_size = ARRAY_SIZE(sdp2430_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -246,6 +244,9 @@ static void __init omap_2430sdp_init(void)
+
+ omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+
++ omap_board_config = sdp2430_config;
++ omap_board_config_size = ARRAY_SIZE(sdp2430_config);
++
+ omap2430_i2c_init();
+
+ platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 8465e80..719b441 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -315,9 +315,6 @@ static struct omap_board_config_kernel sdp3430_config[] __initdata = {
+
+ static void __init omap_3430sdp_init_early(void)
+ {
+- omap_board_config = sdp3430_config;
+- omap_board_config_size = ARRAY_SIZE(sdp3430_config);
+- omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
+ }
+@@ -793,6 +790,9 @@ static struct omap_musb_board_data musb_board_data = {
+ static void __init omap_3430sdp_init(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
++ omap_board_config = sdp3430_config;
++ omap_board_config_size = ARRAY_SIZE(sdp3430_config);
++ omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
+ omap3430_i2c_init();
+ omap_display_init(&sdp3430_dss_data);
+ if (omap_rev() > OMAP3430_REV_ES1_0)
+diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
+index 8d1c435..c4e22b3 100644
+--- a/arch/arm/mach-omap2/board-3630sdp.c
++++ b/arch/arm/mach-omap2/board-3630sdp.c
+@@ -72,8 +72,6 @@ static struct omap_board_config_kernel sdp_config[] __initdata = {
+
+ static void __init omap_sdp_init_early(void)
+ {
+- omap_board_config = sdp_config;
+- omap_board_config_size = ARRAY_SIZE(sdp_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
+ h8mbx00u0mer0em_sdrc_params);
+@@ -206,6 +204,8 @@ static struct flash_partitions sdp_flash_partitions[] = {
+ static void __init omap_sdp_init(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
++ omap_board_config = sdp_config;
++ omap_board_config_size = ARRAY_SIZE(sdp_config);
+ zoom_peripherals_init();
+ zoom_display_init();
+ board_smc91x_init();
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index 1a943be..81ef979 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -325,8 +325,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
+
+ static void __init omap_4430sdp_init_early(void)
+ {
+- omap_board_config = sdp4430_config;
+- omap_board_config_size = ARRAY_SIZE(sdp4430_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ #ifdef CONFIG_OMAP_32K_TIMER
+@@ -640,6 +638,9 @@ static void __init omap_4430sdp_init(void)
+ package = OMAP_PACKAGE_CBL;
+ omap4_mux_init(board_mux, package);
+
++ omap_board_config = sdp4430_config;
++ omap_board_config_size = ARRAY_SIZE(sdp4430_config);
++
+ omap4_i2c_init();
+ omap_sfh7741prox_init();
+ platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
+diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
+index ae3a83d..f53bbb2 100644
+--- a/arch/arm/mach-omap2/board-am3517crane.c
++++ b/arch/arm/mach-omap2/board-am3517crane.c
+@@ -51,9 +51,6 @@ static struct omap_board_mux board_mux[] __initdata = {
+
+ static void __init am3517_crane_init_early(void)
+ {
+- omap_board_config = am3517_crane_config;
+- omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
+-
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -76,6 +73,9 @@ static void __init am3517_crane_init(void)
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ omap_serial_init();
+
++ omap_board_config = am3517_crane_config;
++ omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
++
+ /* Configure GPIO for EHCI port */
+ if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
+ pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
+diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
+index 634fe65..30ec451 100644
+--- a/arch/arm/mach-omap2/board-am3517evm.c
++++ b/arch/arm/mach-omap2/board-am3517evm.c
+@@ -381,13 +381,8 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
+ /*
+ * Board initialization
+ */
+-static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
+-};
+-
+ static void __init am3517_evm_init_early(void)
+ {
+- omap_board_config = am3517_evm_config;
+- omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -481,8 +476,13 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
+ platform_device_register(&am3517_hecc_device);
+ }
+
++static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
++};
++
+ static void __init am3517_evm_init(void)
+ {
++ omap_board_config = am3517_evm_config;
++ omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+ am3517_evm_i2c_init();
+diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
+index 4ef4aad..f4f8374 100644
+--- a/arch/arm/mach-omap2/board-apollon.c
++++ b/arch/arm/mach-omap2/board-apollon.c
+@@ -276,8 +276,6 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
+
+ static void __init omap_apollon_init_early(void)
+ {
+- omap_board_config = apollon_config;
+- omap_board_config_size = ARRAY_SIZE(apollon_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -319,6 +317,8 @@ static void __init omap_apollon_init(void)
+ u32 v;
+
+ omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
++ omap_board_config = apollon_config;
++ omap_board_config_size = ARRAY_SIZE(apollon_config);
+
+ apollon_init_smc91x();
+ apollon_led_init();
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index 7311824..27bea54 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -668,14 +668,8 @@ static void __init cm_t35_init_i2c(void)
+ ARRAY_SIZE(cm_t35_i2c_boardinfo));
+ }
+
+-static struct omap_board_config_kernel cm_t35_config[] __initdata = {
+-};
+-
+ static void __init cm_t35_init_early(void)
+ {
+- omap_board_config = cm_t35_config;
+- omap_board_config_size = ARRAY_SIZE(cm_t35_config);
+-
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
+@@ -785,8 +779,13 @@ static struct omap_musb_board_data musb_board_data = {
+ .power = 100,
+ };
+
++static struct omap_board_config_kernel cm_t35_config[] __initdata = {
++};
++
+ static void __init cm_t35_init(void)
+ {
++ omap_board_config = cm_t35_config;
++ omap_board_config_size = ARRAY_SIZE(cm_t35_config);
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
+ omap_serial_init();
+ cm_t35_init_i2c();
+diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
+index 38bef6d..9da6e82 100644
+--- a/arch/arm/mach-omap2/board-cm-t3517.c
++++ b/arch/arm/mach-omap2/board-cm-t3517.c
+@@ -256,9 +256,6 @@ static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
+
+ static void __init cm_t3517_init_early(void)
+ {
+- omap_board_config = cm_t3517_config;
+- omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
+-
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -293,6 +290,8 @@ static void __init cm_t3517_init(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+ omap_serial_init();
++ omap_board_config = cm_t3517_config;
++ omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
+ cm_t3517_init_leds();
+ cm_t3517_init_nand();
+ cm_t3517_init_rtc();
+diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
+index 682da92..73e3c31 100644
+--- a/arch/arm/mach-omap2/board-generic.c
++++ b/arch/arm/mach-omap2/board-generic.c
+@@ -35,8 +35,6 @@ static struct omap_board_config_kernel generic_config[] = {
+
+ static void __init omap_generic_init_early(void)
+ {
+- omap_board_config = generic_config;
+- omap_board_config_size = ARRAY_SIZE(generic_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -44,6 +42,8 @@ static void __init omap_generic_init_early(void)
+ static void __init omap_generic_init(void)
+ {
+ omap_serial_init();
++ omap_board_config = generic_config;
++ omap_board_config_size = ARRAY_SIZE(generic_config);
+ }
+
+ static void __init omap_generic_map_io(void)
+diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
+index f6a3872..7e6bf4f 100644
+--- a/arch/arm/mach-omap2/board-h4.c
++++ b/arch/arm/mach-omap2/board-h4.c
+@@ -292,8 +292,6 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
+
+ static void __init omap_h4_init_early(void)
+ {
+- omap_board_config = h4_config;
+- omap_board_config_size = ARRAY_SIZE(h4_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -334,6 +332,9 @@ static void __init omap_h4_init(void)
+ {
+ omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
+
++ omap_board_config = h4_config;
++ omap_board_config_size = ARRAY_SIZE(h4_config);
++
+ /*
+ * Make sure the serial ports are muxed on at this point.
+ * You have to mux them off in device drivers later on
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index a3fae56..a69e594 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -290,8 +290,6 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
+
+ static void __init omap_ldp_init_early(void)
+ {
+- omap_board_config = ldp_config;
+- omap_board_config_size = ARRAY_SIZE(ldp_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -422,6 +420,8 @@ static struct mtd_partition ldp_nand_partitions[] = {
+ static void __init omap_ldp_init(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
++ omap_board_config = ldp_config;
++ omap_board_config_size = ARRAY_SIZE(ldp_config);
+ ldp_init_smsc911x();
+ omap_i2c_init();
+ platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 5364147..3d9b58a 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -732,8 +732,6 @@ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
+
+ static void __init omap3_evm_init_early(void)
+ {
+- omap_board_config = omap3_evm_config;
+- omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
+ }
+@@ -824,6 +822,9 @@ static void __init omap3_evm_init(void)
+ else
+ omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
+
++ omap_board_config = omap3_evm_config;
++ omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
++
+ omap3_evm_i2c_init();
+
+ omap_display_init(&omap3_evm_dss_data);
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index 07006c3..fd8b764 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -581,8 +581,6 @@ static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
+
+ static void __init omap3_stalker_init_early(void)
+ {
+- omap_board_config = omap3_stalker_config;
+- omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
+ }
+@@ -629,6 +627,8 @@ static struct omap_musb_board_data musb_board_data = {
+ static void __init omap3_stalker_init(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
++ omap_board_config = omap3_stalker_config;
++ omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
+
+ omap3_stalker_i2c_init();
+
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index a35afe2..8e2a7ba 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -417,8 +417,6 @@ static struct omap_board_mux board_mux[] __initdata = {
+
+ static void __init omap3_touchbook_init_early(void)
+ {
+- omap_board_config = omap3_touchbook_config;
+- omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
+@@ -514,6 +512,9 @@ static struct omap_musb_board_data musb_board_data = {
+ static void __init omap3_touchbook_init(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
++ omap_board_config = omap3_touchbook_config;
++ omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
++
+ pm_power_off = omap3_touchbook_poweroff;
+
+ omap3_touchbook_i2c_init();
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index a33ec0e..d480ddb 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -411,8 +411,6 @@ static struct omap_board_config_kernel overo_config[] __initdata = {
+
+ static void __init overo_init_early(void)
+ {
+- omap_board_config = overo_config;
+- omap_board_config_size = ARRAY_SIZE(overo_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+ mt46h32m32lf6_sdrc_params);
+@@ -448,6 +446,8 @@ static struct omap_musb_board_data musb_board_data = {
+ static void __init overo_init(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
++ omap_board_config = overo_config;
++ omap_board_config_size = ARRAY_SIZE(overo_config);
+ overo_i2c_init();
+ platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
+ omap_serial_init();
+diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
+index 3cf72fe..e964895 100644
+--- a/arch/arm/mach-omap2/board-rx51.c
++++ b/arch/arm/mach-omap2/board-rx51.c
+@@ -102,9 +102,6 @@ static void __init rx51_init_early(void)
+ {
+ struct omap_sdrc_params *sdrc_params;
+
+- omap_board_config = rx51_config;
+- omap_board_config_size = ARRAY_SIZE(rx51_config);
+- omap3_pm_init_cpuidle(rx51_cpuidle_params);
+ omap2_init_common_infrastructure();
+ sdrc_params = nokia_get_sdram_timings();
+ omap2_init_common_devices(sdrc_params, sdrc_params);
+@@ -127,6 +124,9 @@ static struct omap_musb_board_data musb_board_data = {
+ static void __init rx51_init(void)
+ {
+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
++ omap_board_config = rx51_config;
++ omap_board_config_size = ARRAY_SIZE(rx51_config);
++ omap3_pm_init_cpuidle(rx51_cpuidle_params);
+ omap_serial_init();
+ usb_musb_init(&musb_board_data);
+ rx51_peripherals_init();
+diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
+index f2b0971..09fa7bf 100644
+--- a/arch/arm/mach-omap2/board-ti8168evm.c
++++ b/arch/arm/mach-omap2/board-ti8168evm.c
+@@ -29,8 +29,6 @@ static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+
+ static void __init ti8168_init_early(void)
+ {
+- omap_board_config = ti8168_evm_config;
+- omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+ omap2_init_common_infrastructure();
+ omap2_init_common_devices(NULL, NULL);
+ }
+@@ -43,6 +41,8 @@ static void __init ti8168_evm_init_irq(void)
+ static void __init ti8168_evm_init(void)
+ {
+ omap_serial_init();
++ omap_board_config = ti8168_evm_config;
++ omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+ }
+
+ static void __init ti8168_evm_map_io(void)
+--
+1.7.1
+
diff --git a/patches/for_next/0120-OMAP-powerdomain-remove-unused-func-declaration.patch b/patches/for_next/0120-OMAP-powerdomain-remove-unused-func-declaration.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d56ecd89b97a7c96032215d3866ba0fb1f6397fa
--- /dev/null
+++ b/patches/for_next/0120-OMAP-powerdomain-remove-unused-func-declaration.patch
@@ -0,0 +1,29 @@
+From 33c03807faac2eb700337ed0c1bacb63d3e71345 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 16:06:46 -0700
+Subject: [PATCH 120/254] OMAP: powerdomain: remove unused func declaration
+
+Trivial fix to remove the unused function declaration
+from the powerdomain header.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/powerdomain.h | 1 -
+ 1 files changed, 0 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
+index c66431e..0b7a357 100644
+--- a/arch/arm/mach-omap2/powerdomain.h
++++ b/arch/arm/mach-omap2/powerdomain.h
+@@ -165,7 +165,6 @@ struct pwrdm_ops {
+ int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+ };
+
+-void pwrdm_fw_init(void);
+ void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
+
+ struct powerdomain *pwrdm_lookup(const char *name);
+--
+1.7.1
+
diff --git a/patches/for_next/0121-OMAP-clockdomain-Infrastructure-to-put-arch-specific.patch b/patches/for_next/0121-OMAP-clockdomain-Infrastructure-to-put-arch-specific.patch
new file mode 100644
index 0000000000000000000000000000000000000000..68f946de638fc9b1df8633cddfc1b7905990958a
--- /dev/null
+++ b/patches/for_next/0121-OMAP-clockdomain-Infrastructure-to-put-arch-specific.patch
@@ -0,0 +1,134 @@
+From 476e597179ebb34ace734750ff001b597149a207 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 16:06:47 -0700
+Subject: [PATCH 121/254] OMAP: clockdomain: Infrastructure to put arch specific code
+
+Put infrastructure in place, so arch specific func pointers
+can be hooked up to the platform-independent part of the
+framework.
+This is in preparation of splitting the clockdomain framework into
+platform-independent part (for all omaps) and platform-specific
+parts.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomain.c | 10 +++++-
+ arch/arm/mach-omap2/clockdomain.h | 37 +++++++++++++++++++++-
+ arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 2 +-
+ arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +-
+ 4 files changed, 47 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 58e42f7..f70b06a 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -44,6 +44,7 @@ static LIST_HEAD(clkdm_list);
+ /* array of clockdomain deps to be added/removed when clkdm in hwsup mode */
+ static struct clkdm_autodep *autodeps;
+
++static struct clkdm_ops *arch_clkdm;
+
+ /* Private functions */
+
+@@ -292,6 +293,7 @@ static void _disable_hwsup(struct clockdomain *clkdm)
+ * clkdm_init - set up the clockdomain layer
+ * @clkdms: optional pointer to an array of clockdomains to register
+ * @init_autodeps: optional pointer to an array of autodeps to register
++ * @custom_funcs: func pointers for arch specfic implementations
+ *
+ * Set up internal state. If a pointer to an array of clockdomains
+ * @clkdms was supplied, loop through the list of clockdomains,
+@@ -300,12 +302,18 @@ static void _disable_hwsup(struct clockdomain *clkdm)
+ * @init_autodeps was provided, register those. No return value.
+ */
+ void clkdm_init(struct clockdomain **clkdms,
+- struct clkdm_autodep *init_autodeps)
++ struct clkdm_autodep *init_autodeps,
++ struct clkdm_ops *custom_funcs)
+ {
+ struct clockdomain **c = NULL;
+ struct clockdomain *clkdm;
+ struct clkdm_autodep *autodep = NULL;
+
++ if (!custom_funcs)
++ WARN(1, "No custom clkdm functions registered\n");
++ else
++ arch_clkdm = custom_funcs;
++
+ if (clkdms)
+ for (c = clkdms; *c; c++)
+ _clkdm_register(*c);
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index 9b459c2..71ad265 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -116,7 +116,42 @@ struct clockdomain {
+ struct list_head node;
+ };
+
+-void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps);
++/**
++ * struct clkdm_ops - Arch specfic function implementations
++ * @clkdm_add_wkdep: Add a wakeup dependency between clk domains
++ * @clkdm_del_wkdep: Delete a wakeup dependency between clk domains
++ * @clkdm_read_wkdep: Read wakeup dependency state between clk domains
++ * @clkdm_clear_all_wkdeps: Remove all wakeup dependencies from the clk domain
++ * @clkdm_add_sleepdep: Add a sleep dependency between clk domains
++ * @clkdm_del_sleepdep: Delete a sleep dependency between clk domains
++ * @clkdm_read_sleepdep: Read sleep dependency state between clk domains
++ * @clkdm_clear_all_sleepdeps: Remove all sleep dependencies from the clk domain
++ * @clkdm_sleep: Force a clockdomain to sleep
++ * @clkdm_wakeup: Force a clockdomain to wakeup
++ * @clkdm_allow_idle: Enable hw supervised idle transitions for clock domain
++ * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain
++ * @clkdm_clk_enable: Put the clkdm in right state for a clock enable
++ * @clkdm_clk_disable: Put the clkdm in right state for a clock disable
++ */
++struct clkdm_ops {
++ int (*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
++ int (*clkdm_del_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
++ int (*clkdm_read_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
++ int (*clkdm_clear_all_wkdeps)(struct clockdomain *clkdm);
++ int (*clkdm_add_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
++ int (*clkdm_del_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
++ int (*clkdm_read_sleepdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
++ int (*clkdm_clear_all_sleepdeps)(struct clockdomain *clkdm);
++ int (*clkdm_sleep)(struct clockdomain *clkdm);
++ int (*clkdm_wakeup)(struct clockdomain *clkdm);
++ void (*clkdm_allow_idle)(struct clockdomain *clkdm);
++ void (*clkdm_deny_idle)(struct clockdomain *clkdm);
++ int (*clkdm_clk_enable)(struct clockdomain *clkdm);
++ int (*clkdm_clk_disable)(struct clockdomain *clkdm);
++};
++
++void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
++ struct clkdm_ops *custom_funcs);
+ struct clockdomain *clkdm_lookup(const char *name);
+
+ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
+diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+index e6f0d18..e2a959e 100644
+--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
++++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+@@ -856,5 +856,5 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
+
+ void __init omap2_clockdomains_init(void)
+ {
+- clkdm_init(clockdomains_omap2, clkdm_autodeps);
++ clkdm_init(clockdomains_omap2, clkdm_autodeps, NULL);
+ }
+diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
+index 10622c9..a5000d4 100644
+--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
++++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
+@@ -305,5 +305,5 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
+
+ void __init omap44xx_clockdomains_init(void)
+ {
+- clkdm_init(clockdomains_omap44xx, NULL);
++ clkdm_init(clockdomains_omap44xx, NULL, NULL);
+ }
+--
+1.7.1
+
diff --git a/patches/for_next/0122-OMAP-clockdomain-Arch-specific-funcs-to-handle-deps.patch b/patches/for_next/0122-OMAP-clockdomain-Arch-specific-funcs-to-handle-deps.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3d6ff0ccb4cb576cce489421baed14d93b15104b
--- /dev/null
+++ b/patches/for_next/0122-OMAP-clockdomain-Arch-specific-funcs-to-handle-deps.patch
@@ -0,0 +1,602 @@
+From 99929d5e6b6cb62546f18321c817e3d113ff0d65 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 16:06:47 -0700
+Subject: [PATCH 122/254] OMAP: clockdomain: Arch specific funcs to handle deps
+
+Define the following architecture specific funtions for omap2/3
+.clkdm_add_wkdep
+.clkdm_del_wkdep
+.clkdm_read_wkdep
+.clkdm_clear_all_wkdeps
+.clkdm_add_sleepdep
+.clkdm_del_sleepdep
+.clkdm_read_sleepdep
+.clkdm_clear_all_sleepdeps
+
+Convert the platform-independent framework to call these functions.
+With this also move the clkdm lookups for all wkdep_srcs and
+sleepdep_srcs at clkdm_init.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: fixed loop termination conditions in omap*_clkdm_clear_all_*();
+ thanks to Kevin Hilman for finding and helping fix those bugs; also
+ avoid re-resolving clockdomains during init; abstracted out clkdm_dep walk]
+Cc: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/Makefile | 2 +
+ arch/arm/mach-omap2/clockdomain.c | 177 ++++++++++++----------
+ arch/arm/mach-omap2/clockdomain.h | 6 +-
+ arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 130 ++++++++++++++++
+ arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 9 +-
+ arch/arm/mach-omap2/io.c | 6 +-
+ 6 files changed, 246 insertions(+), 84 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 1c3635d..be82ed3 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -102,8 +102,10 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
+
+ # PRCM clockdomain control
+ obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
++ clockdomain2xxx_3xxx.o \
+ clockdomains2xxx_3xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
++ clockdomain2xxx_3xxx.o \
+ clockdomains2xxx_3xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
+ clockdomains44xx_data.o
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index f70b06a..895c153 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -287,6 +287,32 @@ static void _disable_hwsup(struct clockdomain *clkdm)
+ BUG();
+ }
+
++/**
++ * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
++ * @clkdm: clockdomain that we are resolving dependencies for
++ * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
++ *
++ * Iterates through @clkdm_deps, looking up the struct clockdomain named by
++ * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
++ * No return value.
++ */
++static void _resolve_clkdm_deps(struct clockdomain *clkdm,
++ struct clkdm_dep *clkdm_deps)
++{
++ struct clkdm_dep *cd;
++
++ for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
++ if (!omap_chip_is(cd->omap_chip))
++ continue;
++ if (cd->clkdm)
++ continue;
++ cd->clkdm = _clkdm_lookup(cd->clkdm_name);
++
++ WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
++ clkdm->name, cd->clkdm_name);
++ }
++}
++
+ /* Public functions */
+
+ /**
+@@ -333,7 +359,10 @@ void clkdm_init(struct clockdomain **clkdms,
+ else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
+ omap2_clkdm_deny_idle(clkdm);
+
++ _resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
+ clkdm_clear_all_wkdeps(clkdm);
++
++ _resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
+ clkdm_clear_all_sleepdeps(clkdm);
+ }
+ }
+@@ -430,6 +459,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
+ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ {
+ struct clkdm_dep *cd;
++ int ret = 0;
+
+ if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
+ pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
+@@ -441,21 +471,26 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+- if (IS_ERR(cd)) {
++ if (IS_ERR(cd))
++ ret = PTR_ERR(cd);
++
++ if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
++ ret = -EINVAL;
++
++ if (ret) {
+ pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+- return PTR_ERR(cd);
++ return ret;
+ }
+
+ if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
+ pr_debug("clockdomain: hardware will wake up %s when %s wakes "
+ "up\n", clkdm1->name, clkdm2->name);
+
+- omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+- clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
++ ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
+ }
+
+- return 0;
++ return ret;
+ }
+
+ /**
+@@ -471,6 +506,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ {
+ struct clkdm_dep *cd;
++ int ret = 0;
+
+ if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
+ pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
+@@ -482,21 +518,26 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+- if (IS_ERR(cd)) {
++ if (IS_ERR(cd))
++ ret = PTR_ERR(cd);
++
++ if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
++ ret = -EINVAL;
++
++ if (ret) {
+ pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+- return PTR_ERR(cd);
++ return ret;
+ }
+
+ if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
+ pr_debug("clockdomain: hardware will no longer wake up %s "
+ "after %s wakes up\n", clkdm1->name, clkdm2->name);
+
+- omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+- clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
++ ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
+ }
+
+- return 0;
++ return ret;
+ }
+
+ /**
+@@ -516,6 +557,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ {
+ struct clkdm_dep *cd;
++ int ret = 0;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+@@ -527,15 +569,20 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ }
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+- if (IS_ERR(cd)) {
++ if (IS_ERR(cd))
++ ret = PTR_ERR(cd);
++
++ if (!arch_clkdm || !arch_clkdm->clkdm_read_wkdep)
++ ret = -EINVAL;
++
++ if (ret) {
+ pr_debug("clockdomain: hardware cannot set/clear wake up of "
+ "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+- return PTR_ERR(cd);
++ return ret;
+ }
+
+ /* XXX It's faster to return the atomic wkdep_usecount */
+- return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
+- (1 << clkdm2->dep_bit));
++ return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
+ }
+
+ /**
+@@ -550,9 +597,6 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ */
+ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+ {
+- struct clkdm_dep *cd;
+- u32 mask = 0;
+-
+ if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
+ pr_err("clockdomain: %s: %s: not yet implemented\n",
+ clkdm->name, __func__);
+@@ -562,21 +606,10 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+ if (!clkdm)
+ return -EINVAL;
+
+- for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
+- if (!omap_chip_is(cd->omap_chip))
+- continue;
+-
+- if (!cd->clkdm && cd->clkdm_name)
+- cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+-
+- /* PRM accesses are slow, so minimize them */
+- mask |= 1 << cd->clkdm->dep_bit;
+- atomic_set(&cd->wkdep_usecount, 0);
+- }
+-
+- omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
++ if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_wkdeps)
++ return -EINVAL;
+
+- return 0;
++ return arch_clkdm->clkdm_clear_all_wkdeps(clkdm);
+ }
+
+ /**
+@@ -594,31 +627,33 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ {
+ struct clkdm_dep *cd;
+-
+- if (!cpu_is_omap34xx())
+- return -EINVAL;
++ int ret = 0;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+- if (IS_ERR(cd)) {
++ if (IS_ERR(cd))
++ ret = PTR_ERR(cd);
++
++ if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
++ ret = -EINVAL;
++
++ if (ret) {
+ pr_debug("clockdomain: hardware cannot set/clear sleep "
+ "dependency affecting %s from %s\n", clkdm1->name,
+ clkdm2->name);
+- return PTR_ERR(cd);
++ return ret;
+ }
+
+ if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
+ pr_debug("clockdomain: will prevent %s from sleeping if %s "
+ "is active\n", clkdm1->name, clkdm2->name);
+
+- omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+- clkdm1->pwrdm.ptr->prcm_offs,
+- OMAP3430_CM_SLEEPDEP);
++ ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
+ }
+
+- return 0;
++ return ret;
+ }
+
+ /**
+@@ -636,19 +671,23 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ {
+ struct clkdm_dep *cd;
+-
+- if (!cpu_is_omap34xx())
+- return -EINVAL;
++ int ret = 0;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+- if (IS_ERR(cd)) {
++ if (IS_ERR(cd))
++ ret = PTR_ERR(cd);
++
++ if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
++ ret = -EINVAL;
++
++ if (ret) {
+ pr_debug("clockdomain: hardware cannot set/clear sleep "
+ "dependency affecting %s from %s\n", clkdm1->name,
+ clkdm2->name);
+- return PTR_ERR(cd);
++ return ret;
+ }
+
+ if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
+@@ -656,12 +695,10 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ "sleeping if %s is active\n", clkdm1->name,
+ clkdm2->name);
+
+- omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+- clkdm1->pwrdm.ptr->prcm_offs,
+- OMAP3430_CM_SLEEPDEP);
++ ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
+ }
+
+- return 0;
++ return ret;
+ }
+
+ /**
+@@ -683,25 +720,27 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ {
+ struct clkdm_dep *cd;
+-
+- if (!cpu_is_omap34xx())
+- return -EINVAL;
++ int ret = 0;
+
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
+- if (IS_ERR(cd)) {
++ if (IS_ERR(cd))
++ ret = PTR_ERR(cd);
++
++ if (!arch_clkdm || !arch_clkdm->clkdm_read_sleepdep)
++ ret = -EINVAL;
++
++ if (ret) {
+ pr_debug("clockdomain: hardware cannot set/clear sleep "
+ "dependency affecting %s from %s\n", clkdm1->name,
+ clkdm2->name);
+- return PTR_ERR(cd);
++ return ret;
+ }
+
+ /* XXX It's faster to return the atomic sleepdep_usecount */
+- return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+- OMAP3430_CM_SLEEPDEP,
+- (1 << clkdm2->dep_bit));
++ return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
+ }
+
+ /**
+@@ -716,31 +755,13 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ */
+ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+ {
+- struct clkdm_dep *cd;
+- u32 mask = 0;
+-
+- if (!cpu_is_omap34xx())
+- return -EINVAL;
+-
+ if (!clkdm)
+ return -EINVAL;
+
+- for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
+- if (!omap_chip_is(cd->omap_chip))
+- continue;
+-
+- if (!cd->clkdm && cd->clkdm_name)
+- cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+-
+- /* PRM accesses are slow, so minimize them */
+- mask |= 1 << cd->clkdm->dep_bit;
+- atomic_set(&cd->sleepdep_usecount, 0);
+- }
+-
+- omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+- OMAP3430_CM_SLEEPDEP);
++ if (!arch_clkdm || !arch_clkdm->clkdm_clear_all_sleepdeps)
++ return -EINVAL;
+
+- return 0;
++ return arch_clkdm->clkdm_clear_all_sleepdeps(clkdm);
+ }
+
+ /**
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index 71ad265..90b6d6a 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -176,7 +176,11 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm);
+ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
+ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+
+-extern void __init omap2_clockdomains_init(void);
++extern void __init omap2xxx_clockdomains_init(void);
++extern void __init omap3xxx_clockdomains_init(void);
+ extern void __init omap44xx_clockdomains_init(void);
+
++extern struct clkdm_ops omap2_clkdm_operations;
++extern struct clkdm_ops omap3_clkdm_operations;
++
+ #endif
+diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+new file mode 100644
+index 0000000..a1fd6fd
+--- /dev/null
++++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+@@ -0,0 +1,130 @@
++/*
++ * OMAP2 and OMAP3 clockdomain control
++ *
++ * Copyright (C) 2008-2010 Texas Instruments, Inc.
++ * Copyright (C) 2008-2010 Nokia Corporation
++ *
++ * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
++ * Rajendra Nayak <rnayak@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/types.h>
++#include <plat/prcm.h>
++#include "prm.h"
++#include "prm2xxx_3xxx.h"
++#include "cm.h"
++#include "cm2xxx_3xxx.h"
++#include "cm-regbits-24xx.h"
++#include "cm-regbits-34xx.h"
++#include "clockdomain.h"
++
++static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
++ clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
++ return 0;
++}
++
++static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
++ clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
++ return 0;
++}
++
++static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
++ PM_WKDEP, (1 << clkdm2->dep_bit));
++}
++
++static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
++{
++ struct clkdm_dep *cd;
++ u32 mask = 0;
++
++ for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
++ if (!omap_chip_is(cd->omap_chip))
++ continue;
++ if (!cd->clkdm)
++ continue; /* only happens if data is erroneous */
++
++ /* PRM accesses are slow, so minimize them */
++ mask |= 1 << cd->clkdm->dep_bit;
++ atomic_set(&cd->wkdep_usecount, 0);
++ }
++
++ omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
++ PM_WKDEP);
++ return 0;
++}
++
++static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
++ clkdm1->pwrdm.ptr->prcm_offs,
++ OMAP3430_CM_SLEEPDEP);
++ return 0;
++}
++
++static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
++ clkdm1->pwrdm.ptr->prcm_offs,
++ OMAP3430_CM_SLEEPDEP);
++ return 0;
++}
++
++static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
++ OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
++}
++
++static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
++{
++ struct clkdm_dep *cd;
++ u32 mask = 0;
++
++ for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
++ if (!omap_chip_is(cd->omap_chip))
++ continue;
++ if (!cd->clkdm)
++ continue; /* only happens if data is erroneous */
++
++ /* PRM accesses are slow, so minimize them */
++ mask |= 1 << cd->clkdm->dep_bit;
++ atomic_set(&cd->sleepdep_usecount, 0);
++ }
++ omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
++ OMAP3430_CM_SLEEPDEP);
++ return 0;
++}
++
++struct clkdm_ops omap2_clkdm_operations = {
++ .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
++ .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
++ .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
++ .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
++};
++
++struct clkdm_ops omap3_clkdm_operations = {
++ .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
++ .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
++ .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
++ .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
++ .clkdm_add_sleepdep = omap3_clkdm_add_sleepdep,
++ .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep,
++ .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep,
++ .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
++};
+diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+index e2a959e..ffdfe54 100644
+--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
++++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+@@ -854,7 +854,12 @@ static struct clockdomain *clockdomains_omap2[] __initdata = {
+ NULL,
+ };
+
+-void __init omap2_clockdomains_init(void)
++void __init omap2xxx_clockdomains_init(void)
+ {
+- clkdm_init(clockdomains_omap2, clkdm_autodeps, NULL);
++ clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
++}
++
++void __init omap3xxx_clockdomains_init(void)
++{
++ clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
+ }
+diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
+index 657f3c8..441e79d 100644
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -356,15 +356,15 @@ void __init omap2_init_common_infrastructure(void)
+
+ if (cpu_is_omap242x()) {
+ omap2xxx_powerdomains_init();
+- omap2_clockdomains_init();
++ omap2xxx_clockdomains_init();
+ omap2420_hwmod_init();
+ } else if (cpu_is_omap243x()) {
+ omap2xxx_powerdomains_init();
+- omap2_clockdomains_init();
++ omap2xxx_clockdomains_init();
+ omap2430_hwmod_init();
+ } else if (cpu_is_omap34xx()) {
+ omap3xxx_powerdomains_init();
+- omap2_clockdomains_init();
++ omap3xxx_clockdomains_init();
+ omap3xxx_hwmod_init();
+ } else if (cpu_is_omap44xx()) {
+ omap44xx_powerdomains_init();
+--
+1.7.1
+
diff --git a/patches/for_next/0123-OMAP-clockdomain-Arch-specific-funcs-for-sleep-wakeu.patch b/patches/for_next/0123-OMAP-clockdomain-Arch-specific-funcs-for-sleep-wakeu.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f57416d850c138ba8c9a29a8b2fc33726368f612
--- /dev/null
+++ b/patches/for_next/0123-OMAP-clockdomain-Arch-specific-funcs-for-sleep-wakeu.patch
@@ -0,0 +1,379 @@
+From 3fe734ced7f54c8e63c011b8b620aa91d10b0e56 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 16:06:47 -0700
+Subject: [PATCH 123/254] OMAP: clockdomain: Arch specific funcs for sleep/wakeup of clkdm
+
+Define the following architecture specific funtions for omap2/3/4
+.clkdm_sleep
+.clkdm_wakeup
+
+Convert the platform-independent framework to call these functions.
+Also rename the api's by removing the omap2_ preamble.
+Hence call omap2_clkdm_wakeup as clkdm_wakeup and
+omap2_clkdm_sleep as clkdm_sleep.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: fixed omap3_clkdm_clear_all_sleepdeps() and
+ omap2_clkdm_clear_all_wkdeps() to test against the correct
+ loop termination condition; thanks to Kevin Hilman for finding and
+ helping fix]
+Cc: Kevin Hilman <khilman@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/Makefile | 1 +
+ arch/arm/mach-omap2/clockdomain.c | 64 ++++++--------------------
+ arch/arm/mach-omap2/clockdomain.h | 5 +-
+ arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 35 +++++++++++++++
+ arch/arm/mach-omap2/clockdomain44xx.c | 35 +++++++++++++++
+ arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +-
+ arch/arm/mach-omap2/pm.c | 4 +-
+ arch/arm/mach-omap2/pm24xx.c | 6 +-
+ arch/arm/mach-omap2/pm34xx.c | 2 +-
+ 9 files changed, 96 insertions(+), 58 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/clockdomain44xx.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index be82ed3..48738ff 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -108,6 +108,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
+ clockdomain2xxx_3xxx.o \
+ clockdomains2xxx_3xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
++ clockdomain44xx.o \
+ clockdomains44xx_data.o
+ # Clock framework
+ obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 895c153..3035eb9 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -355,7 +355,7 @@ void clkdm_init(struct clockdomain **clkdms,
+ */
+ list_for_each_entry(clkdm, &clkdm_list, node) {
+ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+- omap2_clkdm_wakeup(clkdm);
++ clkdm_wakeup(clkdm);
+ else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
+ omap2_clkdm_deny_idle(clkdm);
+
+@@ -765,7 +765,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+ }
+
+ /**
+- * omap2_clkdm_sleep - force clockdomain sleep transition
++ * clkdm_sleep - force clockdomain sleep transition
+ * @clkdm: struct clockdomain *
+ *
+ * Instruct the CM to force a sleep transition on the specified
+@@ -773,7 +773,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+ * clockdomain does not support software-initiated sleep; 0 upon
+ * success.
+ */
+-int omap2_clkdm_sleep(struct clockdomain *clkdm)
++int clkdm_sleep(struct clockdomain *clkdm)
+ {
+ if (!clkdm)
+ return -EINVAL;
+@@ -784,33 +784,16 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
+ return -EINVAL;
+ }
+
+- pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
+-
+- if (cpu_is_omap24xx()) {
+-
+- omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+- clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
+-
+- } else if (cpu_is_omap34xx()) {
+-
+- omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+- clkdm->clktrctrl_mask);
+-
+- } else if (cpu_is_omap44xx()) {
+-
+- omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+- clkdm->cm_inst,
+- clkdm->clkdm_offs);
++ if (!arch_clkdm || !arch_clkdm->clkdm_sleep)
++ return -EINVAL;
+
+- } else {
+- BUG();
+- };
++ pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
+
+- return 0;
++ return arch_clkdm->clkdm_sleep(clkdm);
+ }
+
+ /**
+- * omap2_clkdm_wakeup - force clockdomain wakeup transition
++ * clkdm_wakeup - force clockdomain wakeup transition
+ * @clkdm: struct clockdomain *
+ *
+ * Instruct the CM to force a wakeup transition on the specified
+@@ -818,7 +801,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
+ * clockdomain does not support software-controlled wakeup; 0 upon
+ * success.
+ */
+-int omap2_clkdm_wakeup(struct clockdomain *clkdm)
++int clkdm_wakeup(struct clockdomain *clkdm)
+ {
+ if (!clkdm)
+ return -EINVAL;
+@@ -829,29 +812,12 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
+ return -EINVAL;
+ }
+
+- pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
+-
+- if (cpu_is_omap24xx()) {
+-
+- omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+- clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
+-
+- } else if (cpu_is_omap34xx()) {
+-
+- omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+- clkdm->clktrctrl_mask);
+-
+- } else if (cpu_is_omap44xx()) {
+-
+- omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
+- clkdm->cm_inst,
+- clkdm->clkdm_offs);
++ if (!arch_clkdm || !arch_clkdm->clkdm_wakeup)
++ return -EINVAL;
+
+- } else {
+- BUG();
+- };
++ pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
+
+- return 0;
++ return arch_clkdm->clkdm_wakeup(clkdm);
+ }
+
+ /**
+@@ -990,7 +956,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ _clkdm_add_autodeps(clkdm);
+ _enable_hwsup(clkdm);
+ } else {
+- omap2_clkdm_wakeup(clkdm);
++ clkdm_wakeup(clkdm);
+ }
+
+ pwrdm_wait_transition(clkdm->pwrdm.ptr);
+@@ -1062,7 +1028,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
+ _clkdm_del_autodeps(clkdm);
+ _enable_hwsup(clkdm);
+ } else {
+- omap2_clkdm_sleep(clkdm);
++ clkdm_sleep(clkdm);
+ }
+
+ pwrdm_clkdm_state_switch(clkdm);
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index 90b6d6a..7a5cb5c 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -170,8 +170,8 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+ void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
+ void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
+
+-int omap2_clkdm_wakeup(struct clockdomain *clkdm);
+-int omap2_clkdm_sleep(struct clockdomain *clkdm);
++int clkdm_wakeup(struct clockdomain *clkdm);
++int clkdm_sleep(struct clockdomain *clkdm);
+
+ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
+ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+@@ -182,5 +182,6 @@ extern void __init omap44xx_clockdomains_init(void);
+
+ extern struct clkdm_ops omap2_clkdm_operations;
+ extern struct clkdm_ops omap3_clkdm_operations;
++extern struct clkdm_ops omap4_clkdm_operations;
+
+ #endif
+diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+index a1fd6fd..08c87fe 100644
+--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+@@ -20,6 +20,7 @@
+ #include "cm2xxx_3xxx.h"
+ #include "cm-regbits-24xx.h"
+ #include "cm-regbits-34xx.h"
++#include "prm-regbits-24xx.h"
+ #include "clockdomain.h"
+
+ static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
+@@ -111,11 +112,43 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
+ return 0;
+ }
+
++static int omap2_clkdm_sleep(struct clockdomain *clkdm)
++{
++ omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
++ clkdm->pwrdm.ptr->prcm_offs,
++ OMAP2_PM_PWSTCTRL);
++ return 0;
++}
++
++static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
++{
++ omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
++ clkdm->pwrdm.ptr->prcm_offs,
++ OMAP2_PM_PWSTCTRL);
++ return 0;
++}
++
++static int omap3_clkdm_sleep(struct clockdomain *clkdm)
++{
++ omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++ return 0;
++}
++
++static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
++{
++ omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++ return 0;
++}
++
+ struct clkdm_ops omap2_clkdm_operations = {
+ .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
+ .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
+ .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
+ .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
++ .clkdm_sleep = omap2_clkdm_sleep,
++ .clkdm_wakeup = omap2_clkdm_wakeup,
+ };
+
+ struct clkdm_ops omap3_clkdm_operations = {
+@@ -127,4 +160,6 @@ struct clkdm_ops omap3_clkdm_operations = {
+ .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep,
+ .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep,
+ .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
++ .clkdm_sleep = omap3_clkdm_sleep,
++ .clkdm_wakeup = omap3_clkdm_wakeup,
+ };
+diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
+new file mode 100644
+index 0000000..9ccb406
+--- /dev/null
++++ b/arch/arm/mach-omap2/clockdomain44xx.c
+@@ -0,0 +1,35 @@
++/*
++ * OMAP4 clockdomain control
++ *
++ * Copyright (C) 2008-2010 Texas Instruments, Inc.
++ * Copyright (C) 2008-2010 Nokia Corporation
++ *
++ * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
++ * Rajendra Nayak <rnayak@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "clockdomain.h"
++#include "cminst44xx.h"
++
++static int omap4_clkdm_sleep(struct clockdomain *clkdm)
++{
++ omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
++ clkdm->cm_inst, clkdm->clkdm_offs);
++ return 0;
++}
++
++static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
++{
++ omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
++ clkdm->cm_inst, clkdm->clkdm_offs);
++ return 0;
++}
++
++struct clkdm_ops omap4_clkdm_operations = {
++ .clkdm_sleep = omap4_clkdm_sleep,
++ .clkdm_wakeup = omap4_clkdm_wakeup,
++};
+diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
+index a5000d4..eea6f8e 100644
+--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
++++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
+@@ -305,5 +305,5 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
+
+ void __init omap44xx_clockdomains_init(void)
+ {
+- clkdm_init(clockdomains_omap44xx, NULL, NULL);
++ clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
+ }
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index d5a102c..74c3100 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -124,7 +124,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+ (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
+ sleep_switch = LOWPOWERSTATE_SWITCH;
+ } else {
+- omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
++ clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+ pwrdm_wait_transition(pwrdm);
+ sleep_switch = FORCEWAKEUP_SWITCH;
+ }
+@@ -142,7 +142,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+ if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
+ omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+ else
+- omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
++ clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
+ break;
+ case LOWPOWERSTATE_SWITCH:
+ pwrdm_set_lowpwrstchange(pwrdm);
+diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
+index 97feb3a..4125621 100644
+--- a/arch/arm/mach-omap2/pm24xx.c
++++ b/arch/arm/mach-omap2/pm24xx.c
+@@ -370,7 +370,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+ omap2_clkdm_allow_idle(clkdm);
+ else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+ atomic_read(&clkdm->usecount) == 0)
+- omap2_clkdm_sleep(clkdm);
++ clkdm_sleep(clkdm);
+ return 0;
+ }
+
+@@ -405,11 +405,11 @@ static void __init prcm_setup_regs(void)
+
+ pwrdm = clkdm_get_pwrdm(dsp_clkdm);
+ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
+- omap2_clkdm_sleep(dsp_clkdm);
++ clkdm_sleep(dsp_clkdm);
+
+ pwrdm = clkdm_get_pwrdm(gfx_clkdm);
+ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
+- omap2_clkdm_sleep(gfx_clkdm);
++ clkdm_sleep(gfx_clkdm);
+
+ /*
+ * Clear clockdomain wakeup dependencies and enable
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index 2f864e4..81df2b1 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
++++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -993,7 +993,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+ omap2_clkdm_allow_idle(clkdm);
+ else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+ atomic_read(&clkdm->usecount) == 0)
+- omap2_clkdm_sleep(clkdm);
++ clkdm_sleep(clkdm);
+ return 0;
+ }
+
+--
+1.7.1
+
diff --git a/patches/for_next/0124-OMAP-clockdomain-Arch-specific-funcs-for-hwsup-contr.patch b/patches/for_next/0124-OMAP-clockdomain-Arch-specific-funcs-for-hwsup-contr.patch
new file mode 100644
index 0000000000000000000000000000000000000000..36bb08940c567fb061f140f507bc8837431c08d9
--- /dev/null
+++ b/patches/for_next/0124-OMAP-clockdomain-Arch-specific-funcs-for-hwsup-contr.patch
@@ -0,0 +1,339 @@
+From 0c6ae9313344791c4136a7a5fe6518972b1540f1 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 16:06:48 -0700
+Subject: [PATCH 124/254] OMAP: clockdomain: Arch specific funcs for hwsup control of clkdm
+
+Define the following architecture specific funtions for omap2/3/4
+.clkdm_allow_idle
+.clkdm_deny_idle
+
+Convert the platform-independent framework to call these functions.
+Also rename the api's by removing the omap2_ preamble.
+Hence call omap2_clkdm_allow_idle as clkdm_allow_idle and
+omap2_clkdm_deny_idle as clkdm_deny_idle.
+
+Make the _clkdm_add_autodeps and _clkdm_del_autodeps as non-static
+so they can be accessed from OMAP2/3 platform specific code.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomain.c | 47 +++++++++-------------------
+ arch/arm/mach-omap2/clockdomain.h | 6 ++-
+ arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 40 +++++++++++++++++++++++
+ arch/arm/mach-omap2/clockdomain44xx.c | 14 ++++++++
+ arch/arm/mach-omap2/cpuidle34xx.c | 4 +-
+ arch/arm/mach-omap2/pm.c | 2 +-
+ arch/arm/mach-omap2/pm24xx.c | 2 +-
+ arch/arm/mach-omap2/pm34xx.c | 4 +-
+ 8 files changed, 79 insertions(+), 40 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 3035eb9..44664e7 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -178,7 +178,7 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
+ */
+-static void _clkdm_add_autodeps(struct clockdomain *clkdm)
++void _clkdm_add_autodeps(struct clockdomain *clkdm)
+ {
+ struct clkdm_autodep *autodep;
+
+@@ -212,7 +212,7 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
+ */
+-static void _clkdm_del_autodeps(struct clockdomain *clkdm)
++void _clkdm_del_autodeps(struct clockdomain *clkdm)
+ {
+ struct clkdm_autodep *autodep;
+
+@@ -357,7 +357,7 @@ void clkdm_init(struct clockdomain **clkdms,
+ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ clkdm_wakeup(clkdm);
+ else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
+- omap2_clkdm_deny_idle(clkdm);
++ clkdm_deny_idle(clkdm);
+
+ _resolve_clkdm_deps(clkdm, clkdm->wkdep_srcs);
+ clkdm_clear_all_wkdeps(clkdm);
+@@ -821,7 +821,7 @@ int clkdm_wakeup(struct clockdomain *clkdm)
+ }
+
+ /**
+- * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
++ * clkdm_allow_idle - enable hwsup idle transitions for clkdm
+ * @clkdm: struct clockdomain *
+ *
+ * Allow the hardware to automatically switch the clockdomain @clkdm into
+@@ -830,7 +830,7 @@ int clkdm_wakeup(struct clockdomain *clkdm)
+ * framework, wkdep/sleepdep autodependencies are added; this is so
+ * device drivers can read and write to the device. No return value.
+ */
+-void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
++void clkdm_allow_idle(struct clockdomain *clkdm)
+ {
+ if (!clkdm)
+ return;
+@@ -841,27 +841,18 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
+ return;
+ }
+
++ if (!arch_clkdm || !arch_clkdm->clkdm_allow_idle)
++ return;
++
+ pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
+ clkdm->name);
+
+- /*
+- * XXX This should be removed once TI adds wakeup/sleep
+- * dependency code and data for OMAP4.
+- */
+- if (cpu_is_omap44xx()) {
+- pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name);
+- } else {
+- if (atomic_read(&clkdm->usecount) > 0)
+- _clkdm_add_autodeps(clkdm);
+- }
+-
+- _enable_hwsup(clkdm);
+-
++ arch_clkdm->clkdm_allow_idle(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+ }
+
+ /**
+- * omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm
++ * clkdm_deny_idle - disable hwsup idle transitions for clkdm
+ * @clkdm: struct clockdomain *
+ *
+ * Prevent the hardware from automatically switching the clockdomain
+@@ -869,7 +860,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
+ * downstream clocks enabled in the clock framework, wkdep/sleepdep
+ * autodependencies are removed. No return value.
+ */
+-void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
++void clkdm_deny_idle(struct clockdomain *clkdm)
+ {
+ if (!clkdm)
+ return;
+@@ -880,21 +871,13 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
+ return;
+ }
+
++ if (!arch_clkdm || !arch_clkdm->clkdm_deny_idle)
++ return;
++
+ pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
+ clkdm->name);
+
+- _disable_hwsup(clkdm);
+-
+- /*
+- * XXX This should be removed once TI adds wakeup/sleep
+- * dependency code and data for OMAP4.
+- */
+- if (cpu_is_omap44xx()) {
+- pr_err("clockdomain: %s: OMAP4 wakeup/sleep dependency support: not yet implemented\n", clkdm->name);
+- } else {
+- if (atomic_read(&clkdm->usecount) > 0)
+- _clkdm_del_autodeps(clkdm);
+- }
++ arch_clkdm->clkdm_deny_idle(clkdm);
+ }
+
+
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index 7a5cb5c..7126658 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -167,8 +167,8 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
+ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
+
+-void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
+-void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
++void clkdm_allow_idle(struct clockdomain *clkdm);
++void clkdm_deny_idle(struct clockdomain *clkdm);
+
+ int clkdm_wakeup(struct clockdomain *clkdm);
+ int clkdm_sleep(struct clockdomain *clkdm);
+@@ -179,6 +179,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+ extern void __init omap2xxx_clockdomains_init(void);
+ extern void __init omap3xxx_clockdomains_init(void);
+ extern void __init omap44xx_clockdomains_init(void);
++extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
++extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
+
+ extern struct clkdm_ops omap2_clkdm_operations;
+ extern struct clkdm_ops omap3_clkdm_operations;
+diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+index 08c87fe..25c27a5 100644
+--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+@@ -128,6 +128,24 @@ static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
+ return 0;
+ }
+
++static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
++{
++ if (atomic_read(&clkdm->usecount) > 0)
++ _clkdm_add_autodeps(clkdm);
++
++ omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++}
++
++static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
++{
++ omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++
++ if (atomic_read(&clkdm->usecount) > 0)
++ _clkdm_del_autodeps(clkdm);
++}
++
+ static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+ {
+ omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+@@ -142,6 +160,24 @@ static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
+ return 0;
+ }
+
++static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
++{
++ if (atomic_read(&clkdm->usecount) > 0)
++ _clkdm_add_autodeps(clkdm);
++
++ omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++}
++
++static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
++{
++ omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++
++ if (atomic_read(&clkdm->usecount) > 0)
++ _clkdm_del_autodeps(clkdm);
++}
++
+ struct clkdm_ops omap2_clkdm_operations = {
+ .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
+ .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
+@@ -149,6 +185,8 @@ struct clkdm_ops omap2_clkdm_operations = {
+ .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
+ .clkdm_sleep = omap2_clkdm_sleep,
+ .clkdm_wakeup = omap2_clkdm_wakeup,
++ .clkdm_allow_idle = omap2_clkdm_allow_idle,
++ .clkdm_deny_idle = omap2_clkdm_deny_idle,
+ };
+
+ struct clkdm_ops omap3_clkdm_operations = {
+@@ -162,4 +200,6 @@ struct clkdm_ops omap3_clkdm_operations = {
+ .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
+ .clkdm_sleep = omap3_clkdm_sleep,
+ .clkdm_wakeup = omap3_clkdm_wakeup,
++ .clkdm_allow_idle = omap3_clkdm_allow_idle,
++ .clkdm_deny_idle = omap3_clkdm_deny_idle,
+ };
+diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
+index 9ccb406..a46125f 100644
+--- a/arch/arm/mach-omap2/clockdomain44xx.c
++++ b/arch/arm/mach-omap2/clockdomain44xx.c
+@@ -29,7 +29,21 @@ static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
+ return 0;
+ }
+
++static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
++{
++ omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
++ clkdm->cm_inst, clkdm->clkdm_offs);
++}
++
++static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
++{
++ omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
++ clkdm->cm_inst, clkdm->clkdm_offs);
++}
++
+ struct clkdm_ops omap4_clkdm_operations = {
+ .clkdm_sleep = omap4_clkdm_sleep,
+ .clkdm_wakeup = omap4_clkdm_wakeup,
++ .clkdm_allow_idle = omap4_clkdm_allow_idle,
++ .clkdm_deny_idle = omap4_clkdm_deny_idle,
+ };
+diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
+index f7b22a1..7cc8071 100644
+--- a/arch/arm/mach-omap2/cpuidle34xx.c
++++ b/arch/arm/mach-omap2/cpuidle34xx.c
+@@ -99,14 +99,14 @@ static int omap3_idle_bm_check(void)
+ static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
+ struct clockdomain *clkdm)
+ {
+- omap2_clkdm_allow_idle(clkdm);
++ clkdm_allow_idle(clkdm);
+ return 0;
+ }
+
+ static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
+ struct clockdomain *clkdm)
+ {
+- omap2_clkdm_deny_idle(clkdm);
++ clkdm_deny_idle(clkdm);
+ return 0;
+ }
+
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index 74c3100..7bb64d8 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -140,7 +140,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+ switch (sleep_switch) {
+ case FORCEWAKEUP_SWITCH:
+ if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
+- omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
++ clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+ else
+ clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
+ break;
+diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
+index 4125621..e983c83 100644
+--- a/arch/arm/mach-omap2/pm24xx.c
++++ b/arch/arm/mach-omap2/pm24xx.c
+@@ -367,7 +367,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+ clkdm_clear_all_sleepdeps(clkdm);
+
+ if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+- omap2_clkdm_allow_idle(clkdm);
++ clkdm_allow_idle(clkdm);
+ else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+ atomic_read(&clkdm->usecount) == 0)
+ clkdm_sleep(clkdm);
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index 81df2b1..eda9a4e 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
++++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -496,7 +496,7 @@ console_still_active:
+
+ pwrdm_post_transition();
+
+- omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
++ clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
+ }
+
+ int omap3_can_sleep(void)
+@@ -990,7 +990,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
+ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+ {
+ if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+- omap2_clkdm_allow_idle(clkdm);
++ clkdm_allow_idle(clkdm);
+ else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+ atomic_read(&clkdm->usecount) == 0)
+ clkdm_sleep(clkdm);
+--
+1.7.1
+
diff --git a/patches/for_next/0125-OMAP-clockdomain-Arch-specific-funcs-for-clkdm_clk_e.patch b/patches/for_next/0125-OMAP-clockdomain-Arch-specific-funcs-for-clkdm_clk_e.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b76d216c74a3a779deb9f473d101fb97dacbacd0
--- /dev/null
+++ b/patches/for_next/0125-OMAP-clockdomain-Arch-specific-funcs-for-clkdm_clk_e.patch
@@ -0,0 +1,419 @@
+From 2a1a11145fbeaaef88c262593022d47e5068735f Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 16:06:48 -0700
+Subject: [PATCH 125/254] OMAP: clockdomain: Arch specific funcs for clkdm_clk_enable/disable
+
+Define the following architecture specific funtions for omap2/3/4
+.clkdm_clk_enable
+.clkdm_clk_disable
+
+Convert the platform-independent framework to call these functions.
+Also rename the api's by removing the omap2_ preamble.
+Hence call omap2_clkdm_k_enable as clkdm_clk_enable and
+omap2_clkdm_clk_disable as clkdm_clk_disable.a
+
+Remove unused functions (_enable/_disable_hwsup) and unsed
+headers from clockdomain.c file.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock.c | 6 +-
+ arch/arm/mach-omap2/clockdomain.c | 131 +++-------------------------
+ arch/arm/mach-omap2/clockdomain.h | 4 +-
+ arch/arm/mach-omap2/clockdomain2xxx_3xxx.c | 69 +++++++++++++++
+ arch/arm/mach-omap2/clockdomain44xx.c | 28 ++++++
+ 5 files changed, 114 insertions(+), 124 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
+index 2a2f152..e9625fc 100644
+--- a/arch/arm/mach-omap2/clock.c
++++ b/arch/arm/mach-omap2/clock.c
+@@ -264,7 +264,7 @@ void omap2_clk_disable(struct clk *clk)
+ clk->ops->disable(clk);
+
+ if (clk->clkdm)
+- omap2_clkdm_clk_disable(clk->clkdm, clk);
++ clkdm_clk_disable(clk->clkdm, clk);
+
+ if (clk->parent)
+ omap2_clk_disable(clk->parent);
+@@ -304,7 +304,7 @@ int omap2_clk_enable(struct clk *clk)
+ }
+
+ if (clk->clkdm) {
+- ret = omap2_clkdm_clk_enable(clk->clkdm, clk);
++ ret = clkdm_clk_enable(clk->clkdm, clk);
+ if (ret) {
+ WARN(1, "clock: %s: could not enable clockdomain %s: "
+ "%d\n", clk->name, clk->clkdm->name, ret);
+@@ -322,7 +322,7 @@ int omap2_clk_enable(struct clk *clk)
+
+ oce_err3:
+ if (clk->clkdm)
+- omap2_clkdm_clk_disable(clk->clkdm, clk);
++ clkdm_clk_disable(clk->clkdm, clk);
+ oce_err2:
+ if (clk->parent)
+ omap2_clk_disable(clk->parent);
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 44664e7..70d2420 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -26,17 +26,8 @@
+
+ #include <linux/bitops.h>
+
+-#include "prm2xxx_3xxx.h"
+-#include "prm-regbits-24xx.h"
+-#include "cm2xxx_3xxx.h"
+-#include "cm-regbits-24xx.h"
+-#include "cminst44xx.h"
+-#include "prcm44xx.h"
+-
+ #include <plat/clock.h>
+-#include "powerdomain.h"
+ #include "clockdomain.h"
+-#include <plat/prcm.h>
+
+ /* clkdm_list contains all registered struct clockdomains */
+ static LIST_HEAD(clkdm_list);
+@@ -236,58 +227,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
+ }
+
+ /**
+- * _enable_hwsup - place a clockdomain into hardware-supervised idle
+- * @clkdm: struct clockdomain *
+- *
+- * Place the clockdomain into hardware-supervised idle mode. No return
+- * value.
+- *
+- * XXX Should this return an error if the clockdomain does not support
+- * hardware-supervised idle mode?
+- */
+-static void _enable_hwsup(struct clockdomain *clkdm)
+-{
+- if (cpu_is_omap24xx())
+- omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+- clkdm->clktrctrl_mask);
+- else if (cpu_is_omap34xx())
+- omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+- clkdm->clktrctrl_mask);
+- else if (cpu_is_omap44xx())
+- return omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+- clkdm->cm_inst,
+- clkdm->clkdm_offs);
+- else
+- BUG();
+-}
+-
+-/**
+- * _disable_hwsup - place a clockdomain into software-supervised idle
+- * @clkdm: struct clockdomain *
+- *
+- * Place the clockdomain @clkdm into software-supervised idle mode.
+- * No return value.
+- *
+- * XXX Should this return an error if the clockdomain does not support
+- * software-supervised idle mode?
+- */
+-static void _disable_hwsup(struct clockdomain *clkdm)
+-{
+- if (cpu_is_omap24xx())
+- omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+- clkdm->clktrctrl_mask);
+- else if (cpu_is_omap34xx())
+- omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+- clkdm->clktrctrl_mask);
+- else if (cpu_is_omap44xx())
+- return omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
+- clkdm->cm_inst,
+- clkdm->clkdm_offs);
+- else
+- BUG();
+-}
+-
+-/**
+ * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
+ * @clkdm: clockdomain that we are resolving dependencies for
+ * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
+@@ -884,7 +823,7 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
+ /* Clockdomain-to-clock framework interface code */
+
+ /**
+- * omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm
++ * clkdm_clk_enable - add an enabled downstream clock to this clkdm
+ * @clkdm: struct clockdomain *
+ * @clk: struct clk * of the enabled downstream clock
+ *
+@@ -897,10 +836,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
+ * by on-chip processors. Returns -EINVAL if passed null pointers;
+ * returns 0 upon success or if the clockdomain is in hwsup idle mode.
+ */
+-int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
++int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ {
+- bool hwsup = false;
+-
+ /*
+ * XXX Rewrite this code to maintain a list of enabled
+ * downstream clocks for debugging purposes?
+@@ -909,6 +846,9 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ if (!clkdm || !clk)
+ return -EINVAL;
+
++ if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
++ return -EINVAL;
++
+ if (atomic_inc_return(&clkdm->usecount) > 1)
+ return 0;
+
+@@ -917,31 +857,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
+ clk->name);
+
+- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+-
+- if (!clkdm->clktrctrl_mask)
+- return 0;
+-
+- hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+- clkdm->clktrctrl_mask);
+-
+- } else if (cpu_is_omap44xx()) {
+-
+- hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+- clkdm->cm_inst,
+- clkdm->clkdm_offs);
+-
+- }
+-
+- if (hwsup) {
+- /* Disable HW transitions when we are changing deps */
+- _disable_hwsup(clkdm);
+- _clkdm_add_autodeps(clkdm);
+- _enable_hwsup(clkdm);
+- } else {
+- clkdm_wakeup(clkdm);
+- }
+-
++ arch_clkdm->clkdm_clk_enable(clkdm);
+ pwrdm_wait_transition(clkdm->pwrdm.ptr);
+ pwrdm_clkdm_state_switch(clkdm);
+
+@@ -949,7 +865,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ }
+
+ /**
+- * omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm
++ * clkdm_clk_disable - remove an enabled downstream clock from this clkdm
+ * @clkdm: struct clockdomain *
+ * @clk: struct clk * of the disabled downstream clock
+ *
+@@ -962,10 +878,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
+ * is enabled; or returns 0 upon success or if the clockdomain is in
+ * hwsup idle mode.
+ */
+-int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
++int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
+ {
+- bool hwsup = false;
+-
+ /*
+ * XXX Rewrite this code to maintain a list of enabled
+ * downstream clocks for debugging purposes?
+@@ -974,6 +888,9 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
+ if (!clkdm || !clk)
+ return -EINVAL;
+
++ if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable)
++ return -EINVAL;
++
+ #ifdef DEBUG
+ if (atomic_read(&clkdm->usecount) == 0) {
+ WARN_ON(1); /* underflow */
+@@ -989,31 +906,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
+ pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
+ clk->name);
+
+- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+-
+- if (!clkdm->clktrctrl_mask)
+- return 0;
+-
+- hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+- clkdm->clktrctrl_mask);
+-
+- } else if (cpu_is_omap44xx()) {
+-
+- hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+- clkdm->cm_inst,
+- clkdm->clkdm_offs);
+-
+- }
+-
+- if (hwsup) {
+- /* Disable HW transitions when we are changing deps */
+- _disable_hwsup(clkdm);
+- _clkdm_del_autodeps(clkdm);
+- _enable_hwsup(clkdm);
+- } else {
+- clkdm_sleep(clkdm);
+- }
+-
++ arch_clkdm->clkdm_clk_disable(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
+ return 0;
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index 7126658..de52f05 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -173,8 +173,8 @@ void clkdm_deny_idle(struct clockdomain *clkdm);
+ int clkdm_wakeup(struct clockdomain *clkdm);
+ int clkdm_sleep(struct clockdomain *clkdm);
+
+-int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
+-int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
++int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
++int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+
+ extern void __init omap2xxx_clockdomains_init(void);
+ extern void __init omap3xxx_clockdomains_init(void);
+diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+index 25c27a5..48d0db7 100644
+--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+@@ -146,6 +146,71 @@ static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
+ _clkdm_del_autodeps(clkdm);
+ }
+
++static void _enable_hwsup(struct clockdomain *clkdm)
++{
++ if (cpu_is_omap24xx())
++ omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++ else if (cpu_is_omap34xx())
++ omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++}
++
++static void _disable_hwsup(struct clockdomain *clkdm)
++{
++ if (cpu_is_omap24xx())
++ omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++ else if (cpu_is_omap34xx())
++ omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++}
++
++
++static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
++{
++ bool hwsup = false;
++
++ if (!clkdm->clktrctrl_mask)
++ return 0;
++
++ hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++
++ if (hwsup) {
++ /* Disable HW transitions when we are changing deps */
++ _disable_hwsup(clkdm);
++ _clkdm_add_autodeps(clkdm);
++ _enable_hwsup(clkdm);
++ } else {
++ clkdm_wakeup(clkdm);
++ }
++
++ return 0;
++}
++
++static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
++{
++ bool hwsup = false;
++
++ if (!clkdm->clktrctrl_mask)
++ return 0;
++
++ hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
++ clkdm->clktrctrl_mask);
++
++ if (hwsup) {
++ /* Disable HW transitions when we are changing deps */
++ _disable_hwsup(clkdm);
++ _clkdm_del_autodeps(clkdm);
++ _enable_hwsup(clkdm);
++ } else {
++ clkdm_sleep(clkdm);
++ }
++
++ return 0;
++}
++
+ static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+ {
+ omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+@@ -187,6 +252,8 @@ struct clkdm_ops omap2_clkdm_operations = {
+ .clkdm_wakeup = omap2_clkdm_wakeup,
+ .clkdm_allow_idle = omap2_clkdm_allow_idle,
+ .clkdm_deny_idle = omap2_clkdm_deny_idle,
++ .clkdm_clk_enable = omap2_clkdm_clk_enable,
++ .clkdm_clk_disable = omap2_clkdm_clk_disable,
+ };
+
+ struct clkdm_ops omap3_clkdm_operations = {
+@@ -202,4 +269,6 @@ struct clkdm_ops omap3_clkdm_operations = {
+ .clkdm_wakeup = omap3_clkdm_wakeup,
+ .clkdm_allow_idle = omap3_clkdm_allow_idle,
+ .clkdm_deny_idle = omap3_clkdm_deny_idle,
++ .clkdm_clk_enable = omap2_clkdm_clk_enable,
++ .clkdm_clk_disable = omap2_clkdm_clk_disable,
+ };
+diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
+index a46125f..c0ccc47 100644
+--- a/arch/arm/mach-omap2/clockdomain44xx.c
++++ b/arch/arm/mach-omap2/clockdomain44xx.c
+@@ -41,9 +41,37 @@ static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
+ clkdm->cm_inst, clkdm->clkdm_offs);
+ }
+
++static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
++{
++ bool hwsup = false;
++
++ hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
++ clkdm->cm_inst, clkdm->clkdm_offs);
++
++ if (!hwsup)
++ clkdm_wakeup(clkdm);
++
++ return 0;
++}
++
++static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
++{
++ bool hwsup = false;
++
++ hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
++ clkdm->cm_inst, clkdm->clkdm_offs);
++
++ if (!hwsup)
++ clkdm_sleep(clkdm);
++
++ return 0;
++}
++
+ struct clkdm_ops omap4_clkdm_operations = {
+ .clkdm_sleep = omap4_clkdm_sleep,
+ .clkdm_wakeup = omap4_clkdm_wakeup,
+ .clkdm_allow_idle = omap4_clkdm_allow_idle,
+ .clkdm_deny_idle = omap4_clkdm_deny_idle,
++ .clkdm_clk_enable = omap4_clkdm_clk_enable,
++ .clkdm_clk_disable = omap4_clkdm_clk_disable,
+ };
+--
+1.7.1
+
diff --git a/patches/for_next/0126-OMAP4-clockdomain-Add-clkdm-static-dependency-srcs.patch b/patches/for_next/0126-OMAP4-clockdomain-Add-clkdm-static-dependency-srcs.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d406835b2e2777a1545a856255695b4ec644cb97
--- /dev/null
+++ b/patches/for_next/0126-OMAP4-clockdomain-Add-clkdm-static-dependency-srcs.patch
@@ -0,0 +1,558 @@
+From c4bdaf3247736128fb4529098d175e5437525f5c Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:48:13 -0700
+Subject: [PATCH 126/254] OMAP4: clockdomain: Add clkdm static dependency srcs
+
+OMAP4 supports static dependencies and dynamic dependencies
+between clock domains. Static dependencies imply both
+wakeup as well as sleep dependencies.
+Generate all clockdomain static dependency sources.
+(Dynamic dependency sources are hardwired and
+cannot to controlled from software).
+
+The autogen scripts are updated to generate the contents
+of this patch.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomains44xx_data.c | 390 ++++++++++++++++++++++++++-
+ 1 files changed, 385 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
+index eea6f8e..f53258a 100644
+--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
++++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
+@@ -18,11 +18,6 @@
+ * published by the Free Software Foundation.
+ */
+
+-/*
+- * To-Do List
+- * -> Populate the Sleep/Wakeup dependencies for the domains
+- */
+-
+ #include <linux/kernel.h>
+ #include <linux/io.h>
+
+@@ -35,6 +30,355 @@
+ #include "prcm44xx.h"
+ #include "prcm_mpu44xx.h"
+
++/* Static Dependencies for OMAP4 Clock Domains */
++
++static struct clkdm_dep ducati_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "abe_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_2_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_dss_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_gfx_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_init_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_cfg_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_per_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_secure_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_wkup_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "tesla_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep iss_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "abe_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_2_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_init_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_cfg_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_per_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "abe_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "ducati_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_dss_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_init_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_cfg_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_per_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_secure_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_wkup_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_2_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "abe_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_cfg_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_per_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_secure_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_wkup_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_per_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "abe_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "ducati_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_2_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_dss_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_gfx_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_init_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_cfg_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_per_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_secure_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_wkup_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "tesla_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
++
++static struct clkdm_dep tesla_wkup_sleep_deps[] = {
++ {
++ .clkdm_name = "abe_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "ivahd_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_1_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_2_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_emif_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l3_init_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_cfg_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_per_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ {
++ .clkdm_name = "l4_wkup_clkdm",
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
++ },
++ { NULL },
++};
+
+ static struct clockdomain l4_cefuse_44xx_clkdm = {
+ .name = "l4_cefuse_clkdm",
+@@ -52,6 +396,7 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CORE_INST,
+ .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
++ .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -62,6 +407,9 @@ static struct clockdomain tesla_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM1_PARTITION,
+ .cm_inst = OMAP4430_CM1_TESLA_INST,
+ .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
++ .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
++ .wkdep_srcs = tesla_wkup_sleep_deps,
++ .sleepdep_srcs = tesla_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -72,6 +420,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_GFX_INST,
+ .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
++ .dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
++ .wkdep_srcs = l3_gfx_wkup_sleep_deps,
++ .sleepdep_srcs = l3_gfx_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -82,6 +433,9 @@ static struct clockdomain ivahd_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_IVAHD_INST,
+ .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
++ .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
++ .wkdep_srcs = ivahd_wkup_sleep_deps,
++ .sleepdep_srcs = ivahd_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -92,6 +446,9 @@ static struct clockdomain l4_secure_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_L4PER_INST,
+ .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
++ .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
++ .wkdep_srcs = l4_secure_wkup_sleep_deps,
++ .sleepdep_srcs = l4_secure_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -102,6 +459,7 @@ static struct clockdomain l4_per_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_L4PER_INST,
+ .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
++ .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -112,6 +470,7 @@ static struct clockdomain abe_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM1_PARTITION,
+ .cm_inst = OMAP4430_CM1_ABE_INST,
+ .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
++ .dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -131,6 +490,9 @@ static struct clockdomain l3_init_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_L3INIT_INST,
+ .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
++ .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
++ .wkdep_srcs = l3_init_wkup_sleep_deps,
++ .sleepdep_srcs = l3_init_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -141,6 +503,8 @@ static struct clockdomain mpuss_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM1_PARTITION,
+ .cm_inst = OMAP4430_CM1_MPU_INST,
+ .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
++ .wkdep_srcs = mpuss_wkup_sleep_deps,
++ .sleepdep_srcs = mpuss_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -171,6 +535,7 @@ static struct clockdomain l3_emif_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CORE_INST,
+ .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
++ .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -191,6 +556,9 @@ static struct clockdomain ducati_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CORE_INST,
+ .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
++ .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
++ .wkdep_srcs = ducati_wkup_sleep_deps,
++ .sleepdep_srcs = ducati_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -201,6 +569,7 @@ static struct clockdomain l3_2_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CORE_INST,
+ .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
++ .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -211,6 +580,7 @@ static struct clockdomain l3_1_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CORE_INST,
+ .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
++ .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -221,6 +591,8 @@ static struct clockdomain l3_d2d_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CORE_INST,
+ .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
++ .wkdep_srcs = l3_d2d_wkup_sleep_deps,
++ .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -231,6 +603,8 @@ static struct clockdomain iss_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CAM_INST,
+ .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
++ .wkdep_srcs = iss_wkup_sleep_deps,
++ .sleepdep_srcs = iss_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -241,6 +615,9 @@ static struct clockdomain l3_dss_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_DSS_INST,
+ .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
++ .dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
++ .wkdep_srcs = l3_dss_wkup_sleep_deps,
++ .sleepdep_srcs = l3_dss_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -251,6 +628,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .cm_inst = OMAP4430_PRM_WKUP_CM_INST,
+ .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
++ .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -271,6 +649,8 @@ static struct clockdomain l3_dma_44xx_clkdm = {
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CORE_INST,
+ .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
++ .wkdep_srcs = l3_dma_wkup_sleep_deps,
++ .sleepdep_srcs = l3_dma_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+--
+1.7.1
+
diff --git a/patches/for_next/0127-OMAP4-CM-Add-CM-accesor-api-for-bitwise-control.patch b/patches/for_next/0127-OMAP4-CM-Add-CM-accesor-api-for-bitwise-control.patch
new file mode 100644
index 0000000000000000000000000000000000000000..289ec4cbec8a6201be2a32e58eedcaf0d98891d0
--- /dev/null
+++ b/patches/for_next/0127-OMAP4-CM-Add-CM-accesor-api-for-bitwise-control.patch
@@ -0,0 +1,67 @@
+From 52c9e4106e6502660458a12af47bc1598a91b756 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:48:14 -0700
+Subject: [PATCH 127/254] OMAP4: CM: Add CM accesor api for bitwise control
+
+Add new OMAP4 CM accesor apis to set/clear and read
+bitfields (based on mask) from CM registers.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/cminst44xx.c | 21 +++++++++++++++++++++
+ arch/arm/mach-omap2/cminst44xx.h | 6 ++++++
+ 2 files changed, 27 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
+index c04bbbe..a482bfa 100644
+--- a/arch/arm/mach-omap2/cminst44xx.c
++++ b/arch/arm/mach-omap2/cminst44xx.c
+@@ -73,6 +73,27 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+ return v;
+ }
+
++u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
++{
++ return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
++}
++
++u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
++{
++ return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
++}
++
++u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
++{
++ u32 v;
++
++ v = omap4_cminst_read_inst_reg(part, inst, idx);
++ v &= mask;
++ v >>= __ffs(mask);
++
++ return v;
++}
++
+ /*
+ *
+ */
+diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
+index a6abd0a..2b32c18 100644
+--- a/arch/arm/mach-omap2/cminst44xx.h
++++ b/arch/arm/mach-omap2/cminst44xx.h
+@@ -25,6 +25,12 @@ extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
+ extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+ extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+ s16 inst, s16 idx);
++extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
++ s16 idx);
++extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
++ s16 idx);
++extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
++ u32 mask);
+
+ extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
+
+--
+1.7.1
+
diff --git a/patches/for_next/0128-OMAP4-clockdomain-Add-wkup-sleep-dependency-support.patch b/patches/for_next/0128-OMAP4-clockdomain-Add-wkup-sleep-dependency-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..aa45dedf887cc0e24a4ac7f79dd48d4b1e001b39
--- /dev/null
+++ b/patches/for_next/0128-OMAP4-clockdomain-Add-wkup-sleep-dependency-support.patch
@@ -0,0 +1,115 @@
+From 8be6b0967f9fe6d72e8a39780da5f91be843d32b Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:48:14 -0700
+Subject: [PATCH 128/254] OMAP4: clockdomain: Add wkup/sleep dependency support
+
+Add OMAP4 platform specific implementation to support clkdm
+wkup and sleep dependencies a.k.a static dependencies.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: removed comment about PRM; zero-prefixed STATICDEP
+ register offset; fixed loop termination condition in
+ omap4_clkdm_clear_all_wkup_sleep_deps(); thanks to Kevin Hilman for finding
+ and helping fix this bug]
+Cc: Kevin Hilman <khilman@deeprootsystems.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomain44xx.c | 60 +++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/cm44xx.h | 1 +
+ 2 files changed, 61 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
+index c0ccc47..a1a4ecd 100644
+--- a/arch/arm/mach-omap2/clockdomain44xx.c
++++ b/arch/arm/mach-omap2/clockdomain44xx.c
+@@ -12,8 +12,60 @@
+ * published by the Free Software Foundation.
+ */
+
++#include <linux/kernel.h>
+ #include "clockdomain.h"
+ #include "cminst44xx.h"
++#include "cm44xx.h"
++
++static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
++ clkdm1->prcm_partition,
++ clkdm1->cm_inst, clkdm1->clkdm_offs +
++ OMAP4_CM_STATICDEP);
++ return 0;
++}
++
++static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
++ clkdm1->prcm_partition,
++ clkdm1->cm_inst, clkdm1->clkdm_offs +
++ OMAP4_CM_STATICDEP);
++ return 0;
++}
++
++static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
++ struct clockdomain *clkdm2)
++{
++ return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
++ clkdm1->cm_inst, clkdm1->clkdm_offs +
++ OMAP4_CM_STATICDEP,
++ (1 << clkdm2->dep_bit));
++}
++
++static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
++{
++ struct clkdm_dep *cd;
++ u32 mask = 0;
++
++ for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
++ if (!omap_chip_is(cd->omap_chip))
++ continue;
++ if (!cd->clkdm)
++ continue; /* only happens if data is erroneous */
++
++ mask |= 1 << cd->clkdm->dep_bit;
++ atomic_set(&cd->wkdep_usecount, 0);
++ }
++
++ omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
++ clkdm->cm_inst, clkdm->clkdm_offs +
++ OMAP4_CM_STATICDEP);
++ return 0;
++}
+
+ static int omap4_clkdm_sleep(struct clockdomain *clkdm)
+ {
+@@ -68,6 +120,14 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
+ }
+
+ struct clkdm_ops omap4_clkdm_operations = {
++ .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
++ .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
++ .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
++ .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
++ .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
++ .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
++ .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep,
++ .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
+ .clkdm_sleep = omap4_clkdm_sleep,
+ .clkdm_wakeup = omap4_clkdm_wakeup,
+ .clkdm_allow_idle = omap4_clkdm_allow_idle,
+diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
+index 48fc3f4..0b87ec8 100644
+--- a/arch/arm/mach-omap2/cm44xx.h
++++ b/arch/arm/mach-omap2/cm44xx.h
+@@ -21,6 +21,7 @@
+ #include "cm.h"
+
+ #define OMAP4_CM_CLKSTCTRL 0x0000
++#define OMAP4_CM_STATICDEP 0x0004
+
+ /* Function prototypes */
+ # ifndef __ASSEMBLER__
+--
+1.7.1
+
diff --git a/patches/for_next/0129-OMAP4-clockdomain-Remove-pr_errs-stating-unsupported.patch b/patches/for_next/0129-OMAP4-clockdomain-Remove-pr_errs-stating-unsupported.patch
new file mode 100644
index 0000000000000000000000000000000000000000..da8b6db9befae1c07388e06f869df24c05e5fd53
--- /dev/null
+++ b/patches/for_next/0129-OMAP4-clockdomain-Remove-pr_errs-stating-unsupported.patch
@@ -0,0 +1,75 @@
+From 9bdbb5307f21c755d29b3c4ac67e5200d68fbea2 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:48:14 -0700
+Subject: [PATCH 129/254] OMAP4: clockdomain: Remove pr_errs' stating unsupported wkdep
+
+Now that wkup and sleep dependencies are supported (in the
+form of static deps) for OMAP4, remove all instances of
+pr_errs' stating dependencies are still unsupported
+on OMAP4.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomain.c | 24 ------------------------
+ 1 files changed, 0 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index 70d2420..a0341de 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -400,12 +400,6 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ struct clkdm_dep *cd;
+ int ret = 0;
+
+- if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
+- pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
+- clkdm1->name, clkdm2->name, __func__);
+- return -EINVAL;
+- }
+-
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+@@ -447,12 +441,6 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ struct clkdm_dep *cd;
+ int ret = 0;
+
+- if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
+- pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
+- clkdm1->name, clkdm2->name, __func__);
+- return -EINVAL;
+- }
+-
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+@@ -501,12 +489,6 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ if (!clkdm1 || !clkdm2)
+ return -EINVAL;
+
+- if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
+- pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
+- clkdm1->name, clkdm2->name, __func__);
+- return -EINVAL;
+- }
+-
+ cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
+ if (IS_ERR(cd))
+ ret = PTR_ERR(cd);
+@@ -536,12 +518,6 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
+ */
+ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
+ {
+- if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
+- pr_err("clockdomain: %s: %s: not yet implemented\n",
+- clkdm->name, __func__);
+- return -EINVAL;
+- }
+-
+ if (!clkdm)
+ return -EINVAL;
+
+--
+1.7.1
+
diff --git a/patches/for_next/0130-omap-clock-Check-for-enable-disable-ops-support.patch b/patches/for_next/0130-omap-clock-Check-for-enable-disable-ops-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a91422d344501e896b75430fb2ae7fb092ee1db6
--- /dev/null
+++ b/patches/for_next/0130-omap-clock-Check-for-enable-disable-ops-support.patch
@@ -0,0 +1,49 @@
+From de0f44f14e68429d41b634272b091c4755da6c47 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:48:36 -0700
+Subject: [PATCH 130/254] omap: clock: Check for enable/disable ops support
+
+Check if enable/disable operations are supported for a given
+clock node before attempting to call them.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock.c | 14 +++++++++-----
+ 1 files changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
+index e9625fc..b187596 100644
+--- a/arch/arm/mach-omap2/clock.c
++++ b/arch/arm/mach-omap2/clock.c
+@@ -261,7 +261,8 @@ void omap2_clk_disable(struct clk *clk)
+
+ pr_debug("clock: %s: disabling in hardware\n", clk->name);
+
+- clk->ops->disable(clk);
++ if (clk->ops && clk->ops->disable)
++ clk->ops->disable(clk);
+
+ if (clk->clkdm)
+ clkdm_clk_disable(clk->clkdm, clk);
+@@ -312,10 +313,13 @@ int omap2_clk_enable(struct clk *clk)
+ }
+ }
+
+- ret = clk->ops->enable(clk);
+- if (ret) {
+- WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
+- goto oce_err3;
++ if (clk->ops && clk->ops->enable) {
++ ret = clk->ops->enable(clk);
++ if (ret) {
++ WARN(1, "clock: %s: could not enable: %d\n",
++ clk->name, ret);
++ goto oce_err3;
++ }
+ }
+
+ return 0;
+--
+1.7.1
+
diff --git a/patches/for_next/0131-omap3-dpll-Populate-clkops-for-dpll1_ck.patch b/patches/for_next/0131-omap3-dpll-Populate-clkops-for-dpll1_ck.patch
new file mode 100644
index 0000000000000000000000000000000000000000..0c5d78c8d26b0955d381be7dd914c8d0b38ceab4
--- /dev/null
+++ b/patches/for_next/0131-omap3-dpll-Populate-clkops-for-dpll1_ck.patch
@@ -0,0 +1,33 @@
+From 8f75c0ed7780513fd045e59a4d987fc69d98b2f3 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:48:37 -0700
+Subject: [PATCH 131/254] omap3: dpll: Populate clkops for dpll1_ck
+
+DPLL1 on omap3 is very similar to the rest of
+the non-core dpll's.
+Hence populate clkops_omap3_noncore_dpll_ops
+as the clkops for it, instead of the
+currently populated clkops_null.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock3xxx_data.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
+index f14d986..0cdb834 100644
+--- a/arch/arm/mach-omap2/clock3xxx_data.c
++++ b/arch/arm/mach-omap2/clock3xxx_data.c
+@@ -296,7 +296,7 @@ static struct dpll_data dpll1_dd = {
+
+ static struct clk dpll1_ck = {
+ .name = "dpll1_ck",
+- .ops = &clkops_null,
++ .ops = &clkops_omap3_noncore_dpll_ops,
+ .parent = &sys_ck,
+ .dpll_data = &dpll1_dd,
+ .round_rate = &omap2_dpll_round_rate,
+--
+1.7.1
+
diff --git a/patches/for_next/0132-OMAP-clock-Add-allow_idle-deny_idle-support-in-clkop.patch b/patches/for_next/0132-OMAP-clock-Add-allow_idle-deny_idle-support-in-clkop.patch
new file mode 100644
index 0000000000000000000000000000000000000000..82640db527889c8fd2db10750a28f875b97e74bf
--- /dev/null
+++ b/patches/for_next/0132-OMAP-clock-Add-allow_idle-deny_idle-support-in-clkop.patch
@@ -0,0 +1,106 @@
+From a5d52c242be3f710176f5922a83589e84f4d9d03 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:49:00 -0700
+Subject: [PATCH 132/254] OMAP: clock: Add allow_idle/deny_idle support in clkops
+
+On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
+support hardware level autogating which can be controlled from
+software.
+Support such functionality by adding two new function pointer
+allow_idle and deny_idle in the clkops structure.
+
+These function pointers can be populated for any clock
+node which supports hardware level autogating.
+
+Also add 2 new functions (omap_clk_enable_autoidle_all and
+omap_clk_disable_autoidle_all) which can be called from
+architecture specific PM core code, if hardware level
+autogating (for all supported clock nodes) is to be
+enabled or disabled.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: use spinlock rather than mutex due to race; renamed functions;
+ functions now return ints]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/clock.c | 32 +++++++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/clock.h | 6 +++++
+ 2 files changed, 38 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
+index fc62fb5..0ae0eae 100644
+--- a/arch/arm/plat-omap/clock.c
++++ b/arch/arm/plat-omap/clock.c
+@@ -335,6 +335,38 @@ struct clk *omap_clk_get_by_name(const char *name)
+ return ret;
+ }
+
++int omap_clk_enable_autoidle_all(void)
++{
++ struct clk *c;
++ unsigned long flags;
++
++ spin_lock_irqsave(&clockfw_lock, flags);
++
++ list_for_each_entry(c, &clocks, node)
++ if (c->ops->allow_idle)
++ c->ops->allow_idle(c);
++
++ spin_unlock_irqrestore(&clockfw_lock, flags);
++
++ return 0;
++}
++
++int omap_clk_disable_autoidle_all(void)
++{
++ struct clk *c;
++ unsigned long flags;
++
++ spin_lock_irqsave(&clockfw_lock, flags);
++
++ list_for_each_entry(c, &clocks, node)
++ if (c->ops->deny_idle)
++ c->ops->deny_idle(c);
++
++ spin_unlock_irqrestore(&clockfw_lock, flags);
++
++ return 0;
++}
++
+ /*
+ * Low level helpers
+ */
+diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
+index d43e623..be69f5c 100644
+--- a/arch/arm/plat-omap/include/plat/clock.h
++++ b/arch/arm/plat-omap/include/plat/clock.h
+@@ -25,6 +25,8 @@ struct clockdomain;
+ * @disable: fn ptr that enables the current clock in hardware
+ * @find_idlest: function returning the IDLEST register for the clock's IP blk
+ * @find_companion: function returning the "companion" clk reg for the clock
++ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
++ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
+ *
+ * A "companion" clk is an accompanying clock to the one being queried
+ * that must be enabled for the IP module connected to the clock to
+@@ -42,6 +44,8 @@ struct clkops {
+ u8 *, u8 *);
+ void (*find_companion)(struct clk *, void __iomem **,
+ u8 *);
++ void (*allow_idle)(struct clk *);
++ void (*deny_idle)(struct clk *);
+ };
+
+ #ifdef CONFIG_ARCH_OMAP2PLUS
+@@ -293,6 +297,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+ extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
+ #endif
+ extern struct clk *omap_clk_get_by_name(const char *name);
++extern int omap_clk_enable_autoidle_all(void);
++extern int omap_clk_disable_autoidle_all(void);
+
+ extern const struct clkops clkops_null;
+
+--
+1.7.1
+
diff --git a/patches/for_next/0133-OMAP3-4-DPLL-Add-allow_idle-deny_idle-support-for-al.patch b/patches/for_next/0133-OMAP3-4-DPLL-Add-allow_idle-deny_idle-support-for-al.patch
new file mode 100644
index 0000000000000000000000000000000000000000..35a58b0452472f5b145a9288998235f51f241145
--- /dev/null
+++ b/patches/for_next/0133-OMAP3-4-DPLL-Add-allow_idle-deny_idle-support-for-al.patch
@@ -0,0 +1,80 @@
+From 5bffe265a24d11bfbcc814c9cf215756abc584e1 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:49:00 -0700
+Subject: [PATCH 133/254] OMAP3/4: DPLL: Add allow_idle/deny_idle support for all DPLL's
+
+All OMAP3/4 dpll's support hardware level autogating.
+Populate allow_idle/deny_idle function pointers for all
+DPLL's in clkops.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock.c | 8 +++++++-
+ arch/arm/mach-omap2/clock.h | 1 +
+ arch/arm/mach-omap2/clock3xxx_data.c | 2 +-
+ arch/arm/mach-omap2/clock44xx_data.c | 2 +-
+ 4 files changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
+index b187596..46d03cc 100644
+--- a/arch/arm/mach-omap2/clock.c
++++ b/arch/arm/mach-omap2/clock.c
+@@ -377,10 +377,16 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
+ const struct clkops clkops_omap3_noncore_dpll_ops = {
+ .enable = omap3_noncore_dpll_enable,
+ .disable = omap3_noncore_dpll_disable,
++ .allow_idle = omap3_dpll_allow_idle,
++ .deny_idle = omap3_dpll_deny_idle,
+ };
+
+-#endif
++const struct clkops clkops_omap3_core_dpll_ops = {
++ .allow_idle = omap3_dpll_allow_idle,
++ .deny_idle = omap3_dpll_deny_idle,
++};
+
++#endif
+
+ /*
+ * OMAP2+ clock reset and init functions
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index 896584e..2a939e5 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -146,5 +146,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+ #endif
+
+ extern const struct clkops clkops_omap3_noncore_dpll_ops;
++extern const struct clkops clkops_omap3_core_dpll_ops;
+
+ #endif
+diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
+index 0cdb834..78ea799 100644
+--- a/arch/arm/mach-omap2/clock3xxx_data.c
++++ b/arch/arm/mach-omap2/clock3xxx_data.c
+@@ -429,7 +429,7 @@ static struct dpll_data dpll3_dd = {
+
+ static struct clk dpll3_ck = {
+ .name = "dpll3_ck",
+- .ops = &clkops_null,
++ .ops = &clkops_omap3_core_dpll_ops,
+ .parent = &sys_ck,
+ .dpll_data = &dpll3_dd,
+ .round_rate = &omap2_dpll_round_rate,
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index de9ec8d..b843b6e 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -443,7 +443,7 @@ static struct clk dpll_core_ck = {
+ .parent = &sys_clkin_ck,
+ .dpll_data = &dpll_core_dd,
+ .init = &omap2_init_dpll_parent,
+- .ops = &clkops_null,
++ .ops = &clkops_omap3_core_dpll_ops,
+ .recalc = &omap3_dpll_recalc,
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0134-OMAP2-clock-autoidle-as-many-clocks-as-possible-if-C.patch b/patches/for_next/0134-OMAP2-clock-autoidle-as-many-clocks-as-possible-if-C.patch
new file mode 100644
index 0000000000000000000000000000000000000000..172d1524e5a7898c9b1f57fe367cae8e10340ed1
--- /dev/null
+++ b/patches/for_next/0134-OMAP2-clock-autoidle-as-many-clocks-as-possible-if-C.patch
@@ -0,0 +1,69 @@
+From 4ffcb2b5d7d1373a6a50e38ad1d8fa4832c67213 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:49:01 -0700
+Subject: [PATCH 134/254] OMAP2+: clock: autoidle as many clocks as possible if CONFIG_OMAP_RESET_CLOCKS
+
+Attempt to enable autoidle for as many clocks as possible in the
+OMAP2+-common CONFIG_OMAP_RESET_CLOCKS code. Currently, this only
+enables DPLL autoidle for OMAP3/4 DPLLs; but future patches will
+enable autoidle for other clocks and the OMAP2 DPLL/APLLs.
+
+In the long run, we should probably get rid of
+CONFIG_OMAP_RESET_CLOCKS, and unconditionally run the code that it
+selects. Otherwise, the state of the clock tree won't match the
+hardware state - this could result in clocks being enabled or disabled
+unpredictably.
+
+Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in
+the pm34xx.c/pm44xx.c code.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+---
+ arch/arm/mach-omap2/pm34xx.c | 17 -----------------
+ arch/arm/plat-omap/clock.c | 1 +
+ 2 files changed, 1 insertions(+), 17 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index eda9a4e..a99f296 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
++++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -814,23 +814,6 @@ static void __init prcm_setup_regs(void)
+ omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
+
+ /*
+- * Set all plls to autoidle. This is needed until autoidle is
+- * enabled by clockfw
+- */
+- omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
+- OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
+- omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
+- MPU_MOD,
+- CM_AUTOIDLE2);
+- omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+- (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
+- PLL_MOD,
+- CM_AUTOIDLE);
+- omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+- PLL_MOD,
+- CM_AUTOIDLE2);
+-
+- /*
+ * Enable control of expternal oscillator through
+ * sys_clkreq. In the long run clock framework should
+ * take care of this.
+diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
+index 0ae0eae..2770ddd 100644
+--- a/arch/arm/plat-omap/clock.c
++++ b/arch/arm/plat-omap/clock.c
+@@ -446,6 +446,7 @@ static int __init clk_disable_unused(void)
+ return 0;
+ }
+ late_initcall(clk_disable_unused);
++late_initcall(omap_clk_enable_autoidle_all);
+ #endif
+
+ int __init clk_init(struct clk_functions * custom_clocks)
+--
+1.7.1
+
diff --git a/patches/for_next/0135-OMAP4-DPLL-Add-dpll-api-to-control-GATE_CTRL.patch b/patches/for_next/0135-OMAP4-DPLL-Add-dpll-api-to-control-GATE_CTRL.patch
new file mode 100644
index 0000000000000000000000000000000000000000..83bb6eaa9cd3de09587e6be919b7ef0d515ebbeb
--- /dev/null
+++ b/patches/for_next/0135-OMAP4-DPLL-Add-dpll-api-to-control-GATE_CTRL.patch
@@ -0,0 +1,175 @@
+From 3e49227270da763246bec1f889ab23829fce4c1c Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:49:01 -0700
+Subject: [PATCH 135/254] OMAP4: DPLL: Add dpll api to control GATE_CTRL
+
+On OMAP4, the dpll post divider outputs (MX outputs)
+along with clockout_x2 output provide a way to allow/deny
+hardware level autogating.
+Allowing autoidle would mean that the hw would autogate
+this clock when there is no dependency for it.
+Denying idle would mean that this clock output will be
+forced to stay enabled.
+
+Add dpll api's to read/allow/deny idle control
+for these dpll mx postdividers.
+
+NOTE: The gatectrl bit set to 0 allows gatectrl,
+and the bit set to 1 denies gatectrl.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+[paul@pwsan.com: moved OMAP4-specific DPLL control code to
+ mach-omap2/dpll44xx.c; added some documentation for CLOCK_CLKOUTX2]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/Makefile | 2 +-
+ arch/arm/mach-omap2/clock.h | 3 +
+ arch/arm/mach-omap2/dpll44xx.c | 78 +++++++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/clock.h | 14 +++++-
+ 4 files changed, 95 insertions(+), 2 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/dpll44xx.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 48738ff..6874187 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -123,7 +123,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
+ clock3517.o clock36xx.o \
+ dpll3xxx.o clock3xxx_data.o
+ obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
+- dpll3xxx.o
++ dpll3xxx.o dpll44xx.o
+
+ # OMAP2 clock rate set data (old "OPP" data)
+ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index 2a939e5..c450d69 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
+ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+ int omap3_noncore_dpll_enable(struct clk *clk);
+ void omap3_noncore_dpll_disable(struct clk *clk);
++int omap4_dpllmx_gatectrl_read(struct clk *clk);
++void omap4_dpllmx_allow_gatectrl(struct clk *clk);
++void omap4_dpllmx_deny_gatectrl(struct clk *clk);
+
+ #ifdef CONFIG_OMAP_RESET_CLOCKS
+ void omap2_clk_disable_unused(struct clk *clk);
+diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
+new file mode 100644
+index 0000000..94a3592
+--- /dev/null
++++ b/arch/arm/mach-omap2/dpll44xx.c
+@@ -0,0 +1,78 @@
++/*
++ * OMAP4-specific DPLL control functions
++ *
++ * Copyright (C) 2011 Texas Instruments, Inc.
++ * Rajendra Nayak
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++
++#include <plat/cpu.h>
++#include <plat/clock.h>
++
++#include "clock.h"
++#include "cm-regbits-44xx.h"
++
++/* Supported only on OMAP4 */
++int omap4_dpllmx_gatectrl_read(struct clk *clk)
++{
++ u32 v;
++ u32 mask;
++
++ if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
++ return -EINVAL;
++
++ mask = clk->flags & CLOCK_CLKOUTX2 ?
++ OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
++ OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
++
++ v = __raw_readl(clk->clksel_reg);
++ v &= mask;
++ v >>= __ffs(mask);
++
++ return v;
++}
++
++void omap4_dpllmx_allow_gatectrl(struct clk *clk)
++{
++ u32 v;
++ u32 mask;
++
++ if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
++ return;
++
++ mask = clk->flags & CLOCK_CLKOUTX2 ?
++ OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
++ OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
++
++ v = __raw_readl(clk->clksel_reg);
++ /* Clear the bit to allow gatectrl */
++ v &= ~mask;
++ __raw_writel(v, clk->clksel_reg);
++}
++
++void omap4_dpllmx_deny_gatectrl(struct clk *clk)
++{
++ u32 v;
++ u32 mask;
++
++ if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
++ return;
++
++ mask = clk->flags & CLOCK_CLKOUTX2 ?
++ OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
++ OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
++
++ v = __raw_readl(clk->clksel_reg);
++ /* Set the bit to deny gatectrl */
++ v |= mask;
++ __raw_writel(v, clk->clksel_reg);
++}
+diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
+index be69f5c..dcd7bb8 100644
+--- a/arch/arm/plat-omap/include/plat/clock.h
++++ b/arch/arm/plat-omap/include/plat/clock.h
+@@ -176,12 +176,24 @@ struct dpll_data {
+
+ #endif
+
+-/* struct clk.flags possibilities */
++/*
++ * struct clk.flags possibilities
++ *
++ * XXX document the rest of the clock flags here
++ *
++ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
++ * bits share the same register. This flag allows the
++ * omap4_dpllmx*() code to determine which GATE_CTRL bit field
++ * should be used. This is a temporary solution - a better approach
++ * would be to associate clock type-specific data with the clock,
++ * similar to the struct dpll_data approach.
++ */
+ #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
+ #define CLOCK_IDLE_CONTROL (1 << 1)
+ #define CLOCK_NO_IDLE_PARENT (1 << 2)
+ #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
+ #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
++#define CLOCK_CLKOUTX2 (1 << 5)
+
+ /**
+ * struct clk - OMAP struct clk
+--
+1.7.1
+
diff --git a/patches/for_next/0136-omap4-dpll-Enable-auto-gate-control-for-all-MX-postd.patch b/patches/for_next/0136-omap4-dpll-Enable-auto-gate-control-for-all-MX-postd.patch
new file mode 100644
index 0000000000000000000000000000000000000000..1b61587535a7f94e1aaeb95d97a3d0eec1dfbf8c
--- /dev/null
+++ b/patches/for_next/0136-omap4-dpll-Enable-auto-gate-control-for-all-MX-postd.patch
@@ -0,0 +1,279 @@
+From c8ef6032c2a4406c3bea718a2e0561f70ad7a00c Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:49:02 -0700
+Subject: [PATCH 136/254] omap4: dpll: Enable auto gate control for all MX postdividers
+
+Enable hardware gate control for all dpll MX and X2 postdividers.
+This requires the allow_idle/deny_idle functions to be
+populated for all clock nodes (mx/x2 post dividers) in
+clkops.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock.h | 1 +
+ arch/arm/mach-omap2/clock44xx_data.c | 52 +++++++++++++++++++--------------
+ arch/arm/mach-omap2/dpll44xx.c | 6 ++++
+ 3 files changed, 37 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index c450d69..0725a6a 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -150,5 +150,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+
+ extern const struct clkops clkops_omap3_noncore_dpll_ops;
+ extern const struct clkops clkops_omap3_core_dpll_ops;
++extern const struct clkops clkops_omap4_dpllmx_ops;
+
+ #endif
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index b843b6e..dcbe105 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = {
+ static struct clk dpll_abe_x2_ck = {
+ .name = "dpll_abe_x2_ck",
+ .parent = &dpll_abe_ck,
+- .ops = &clkops_null,
++ .flags = CLOCK_CLKOUTX2,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap3_clkoutx2_recalc,
++ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
+ };
+
+ static const struct clksel_rate div31_1to31_rates[] = {
+@@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = {
+ .clksel = dpll_abe_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = {
+ .clksel = dpll_abe_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
+ .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -450,6 +452,7 @@ static struct clk dpll_core_ck = {
+ static struct clk dpll_core_x2_ck = {
+ .name = "dpll_core_x2_ck",
+ .parent = &dpll_core_ck,
++ .flags = CLOCK_CLKOUTX2,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+ };
+@@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = {
+ .clksel = dpll_core_m6x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = {
+ .clksel = dpll_core_m2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = {
+ .clksel = dpll_core_m6x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = {
+ .clksel = dpll_core_m6x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = {
+ .clksel = dpll_abe_m2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = {
+ .clksel = dpll_core_m6x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = {
+ static struct clk dpll_iva_x2_ck = {
+ .name = "dpll_iva_x2_ck",
+ .parent = &dpll_iva_ck,
++ .flags = CLOCK_CLKOUTX2,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+ };
+@@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = {
+ .clksel = dpll_iva_m4x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = {
+ .clksel = dpll_iva_m4x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
+ .clksel = dpll_mpu_m2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = {
+ .clksel = dpll_per_m2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = {
+ static struct clk dpll_per_x2_ck = {
+ .name = "dpll_per_x2_ck",
+ .parent = &dpll_per_ck,
+- .ops = &clkops_null,
++ .flags = CLOCK_CLKOUTX2,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap3_clkoutx2_recalc,
++ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
+ };
+
+ static const struct clksel dpll_per_m2x2_div[] = {
+@@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = {
+ .clksel = dpll_per_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = {
+ .clksel = dpll_per_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = {
+ .clksel = dpll_per_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = {
+ .clksel = dpll_per_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = {
+ .clksel = dpll_per_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
+ .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = {
+ static struct clk dpll_unipro_x2_ck = {
+ .name = "dpll_unipro_x2_ck",
+ .parent = &dpll_unipro_ck,
++ .flags = CLOCK_CLKOUTX2,
+ .ops = &clkops_null,
+ .recalc = &omap3_clkoutx2_recalc,
+ };
+@@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = {
+ .clksel = dpll_unipro_m2x2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+@@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = {
+ static struct clk dpll_usb_clkdcoldo_ck = {
+ .name = "dpll_usb_clkdcoldo_ck",
+ .parent = &dpll_usb_ck,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
++ .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
+ .recalc = &followparent_recalc,
+ };
+
+@@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
+ .clksel = dpll_usb_m2_div,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
+ .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
+- .ops = &clkops_null,
++ .ops = &clkops_omap4_dpllmx_ops,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
+index 94a3592..4e4da61 100644
+--- a/arch/arm/mach-omap2/dpll44xx.c
++++ b/arch/arm/mach-omap2/dpll44xx.c
+@@ -76,3 +76,9 @@ void omap4_dpllmx_deny_gatectrl(struct clk *clk)
+ v |= mask;
+ __raw_writel(v, clk->clksel_reg);
+ }
++
++const struct clkops clkops_omap4_dpllmx_ops = {
++ .allow_idle = omap4_dpllmx_allow_gatectrl,
++ .deny_idle = omap4_dpllmx_deny_gatectrl,
++};
++
+--
+1.7.1
+
diff --git a/patches/for_next/0137-OMAP2-clock-disable-autoidle-on-all-clocks-during-cl.patch b/patches/for_next/0137-OMAP2-clock-disable-autoidle-on-all-clocks-during-cl.patch
new file mode 100644
index 0000000000000000000000000000000000000000..6ebfb5c9283700e9d7338c27888b1380bb9139d2
--- /dev/null
+++ b/patches/for_next/0137-OMAP2-clock-disable-autoidle-on-all-clocks-during-cl.patch
@@ -0,0 +1,108 @@
+From 3dcd5d555550b2a8075253968db1c370b7e3a445 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:49:53 -0700
+Subject: [PATCH 137/254] OMAP2+: clock: disable autoidle on all clocks during clock init
+
+Disable autoidle on all clocks during clock framework initialization.
+(If CONFIG_PM is set, autoidle is re-enabled for all clocks later in
+the boot process.)
+
+The principle behind this patch, and some similar patches, is that the
+kernel should start with all power management features disabled.
+Later in the boot process, the PM code, if compiled in with CONFIG_PM,
+enables or re-enables power management features.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clock2420_data.c | 3 +++
+ arch/arm/mach-omap2/clock2430_data.c | 3 +++
+ arch/arm/mach-omap2/clock3xxx.c | 3 ---
+ arch/arm/mach-omap2/clock3xxx_data.c | 6 +++++-
+ arch/arm/mach-omap2/clock44xx_data.c | 3 +++
+ 5 files changed, 14 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 0a992bc..ee73e14 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -1913,6 +1913,9 @@ int __init omap2420_clk_init(void)
+ omap2_init_clk_clkdm(c->lk.clk);
+ }
+
++ /* Disable autoidle on all clocks; let the PM code enable it later */
++ omap_clk_disable_autoidle_all();
++
+ /* Check the MPU rate set by bootloader */
+ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index c047dcd..a1298e5 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -2028,6 +2028,9 @@ int __init omap2430_clk_init(void)
+ omap2_init_clk_clkdm(c->lk.clk);
+ }
+
++ /* Disable autoidle on all clocks; let the PM code enable it later */
++ omap_clk_disable_autoidle_all();
++
+ /* Check the MPU rate set by bootloader */
+ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
+ for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
+index e9f66b6..952c3e0 100644
+--- a/arch/arm/mach-omap2/clock3xxx.c
++++ b/arch/arm/mach-omap2/clock3xxx.c
+@@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void)
+ clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
+ clk_enable(dpll5_clk);
+
+- /* Enable autoidle to allow it to enter low power bypass */
+- omap3_dpll_allow_idle(dpll5_clk);
+-
+ /* Program dpll5_m2_clk divider for no division */
+ dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
+ clk_enable(dpll5_m2_clk);
+diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
+index 78ea799..65b79e6 100644
+--- a/arch/arm/mach-omap2/clock3xxx_data.c
++++ b/arch/arm/mach-omap2/clock3xxx_data.c
+@@ -3538,6 +3538,9 @@ int __init omap3xxx_clk_init(void)
+ omap2_init_clk_clkdm(c->lk.clk);
+ }
+
++ /* Disable autoidle on all clocks; let the PM code enable it later */
++ omap_clk_disable_autoidle_all();
++
+ recalculate_root_clocks();
+
+ pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+@@ -3551,7 +3554,8 @@ int __init omap3xxx_clk_init(void)
+ clk_enable_init_clocks();
+
+ /*
+- * Lock DPLL5 and put it in autoidle.
++ * Lock DPLL5 -- here only until other device init code can
++ * handle this
+ */
+ if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+ omap3_clk_lock_dpll5();
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index dcbe105..2795342 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -3309,6 +3309,9 @@ int __init omap4xxx_clk_init(void)
+ omap2_init_clk_clkdm(c->lk.clk);
+ }
+
++ /* Disable autoidle on all clocks; let the PM code enable it later */
++ omap_clk_disable_autoidle_all();
++
+ recalculate_root_clocks();
+
+ /*
+--
+1.7.1
+
diff --git a/patches/for_next/0138-OMAP2420-hwmod-data-add-dmtimer.patch b/patches/for_next/0138-OMAP2420-hwmod-data-add-dmtimer.patch
new file mode 100644
index 0000000000000000000000000000000000000000..bfccd2146cba5cc622c9cb98ed48b9b939ca4c44
--- /dev/null
+++ b/patches/for_next/0138-OMAP2420-hwmod-data-add-dmtimer.patch
@@ -0,0 +1,706 @@
+From 0a94ef632b835718011dfab40aa4a6fc4b52d583 Mon Sep 17 00:00:00 2001
+From: Thara Gopinath <thara@ti.com>
+Date: Wed, 23 Feb 2011 00:14:04 -0700
+Subject: [PATCH 138/254] OMAP2420: hwmod data: add dmtimer
+
+Add dmtimer data.
+
+Signed-off-by: Thara Gopinath <thara@ti.com>
+Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 634 ++++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/dmtimer.h | 11 +
+ 2 files changed, 645 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index e44ecb4..f4a38f1 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -19,6 +19,7 @@
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
+ #include <plat/mcspi.h>
++#include <plat/dmtimer.h>
+ #include <plat/l3_2xxx.h>
+ #include <plat/l4_2xxx.h>
+
+@@ -339,6 +340,625 @@ static struct omap_hwmod omap2420_iva_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+ };
+
++/* Timer Common */
++static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap2420_timer_hwmod_class = {
++ .name = "timer",
++ .sysc = &omap2420_timer_sysc,
++ .rev = OMAP_TIMER_IP_VERSION_1,
++};
++
++/* timer1 */
++static struct omap_hwmod omap2420_timer1_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
++ { .irq = 37, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
++ {
++ .pa_start = 0x48028000,
++ .pa_end = 0x48028000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_wkup -> timer1 */
++static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
++ .master = &omap2420_l4_wkup_hwmod,
++ .slave = &omap2420_timer1_hwmod,
++ .clk = "gpt1_ick",
++ .addr = omap2420_timer1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer1 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
++ &omap2420_l4_wkup__timer1,
++};
++
++/* timer1 hwmod */
++static struct omap_hwmod omap2420_timer1_hwmod = {
++ .name = "timer1",
++ .mpu_irqs = omap2420_timer1_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
++ .main_clk = "gpt1_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT1_SHIFT,
++ .module_offs = WKUP_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer2 */
++static struct omap_hwmod omap2420_timer2_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
++ { .irq = 38, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
++ {
++ .pa_start = 0x4802a000,
++ .pa_end = 0x4802a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer2 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer2_hwmod,
++ .clk = "gpt2_ick",
++ .addr = omap2420_timer2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer2 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
++ &omap2420_l4_core__timer2,
++};
++
++/* timer2 hwmod */
++static struct omap_hwmod omap2420_timer2_hwmod = {
++ .name = "timer2",
++ .mpu_irqs = omap2420_timer2_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
++ .main_clk = "gpt2_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT2_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer3 */
++static struct omap_hwmod omap2420_timer3_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
++ { .irq = 39, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
++ {
++ .pa_start = 0x48078000,
++ .pa_end = 0x48078000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer3 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer3_hwmod,
++ .clk = "gpt3_ick",
++ .addr = omap2420_timer3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer3 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
++ &omap2420_l4_core__timer3,
++};
++
++/* timer3 hwmod */
++static struct omap_hwmod omap2420_timer3_hwmod = {
++ .name = "timer3",
++ .mpu_irqs = omap2420_timer3_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
++ .main_clk = "gpt3_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT3_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer4 */
++static struct omap_hwmod omap2420_timer4_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
++ { .irq = 40, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
++ {
++ .pa_start = 0x4807a000,
++ .pa_end = 0x4807a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer4 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer4_hwmod,
++ .clk = "gpt4_ick",
++ .addr = omap2420_timer4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer4 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
++ &omap2420_l4_core__timer4,
++};
++
++/* timer4 hwmod */
++static struct omap_hwmod omap2420_timer4_hwmod = {
++ .name = "timer4",
++ .mpu_irqs = omap2420_timer4_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
++ .main_clk = "gpt4_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT4_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer5 */
++static struct omap_hwmod omap2420_timer5_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
++ { .irq = 41, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
++ {
++ .pa_start = 0x4807c000,
++ .pa_end = 0x4807c000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer5 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer5_hwmod,
++ .clk = "gpt5_ick",
++ .addr = omap2420_timer5_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer5 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
++ &omap2420_l4_core__timer5,
++};
++
++/* timer5 hwmod */
++static struct omap_hwmod omap2420_timer5_hwmod = {
++ .name = "timer5",
++ .mpu_irqs = omap2420_timer5_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
++ .main_clk = "gpt5_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT5_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer5_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++
++/* timer6 */
++static struct omap_hwmod omap2420_timer6_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
++ { .irq = 42, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
++ {
++ .pa_start = 0x4807e000,
++ .pa_end = 0x4807e000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer6 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer6_hwmod,
++ .clk = "gpt6_ick",
++ .addr = omap2420_timer6_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer6 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
++ &omap2420_l4_core__timer6,
++};
++
++/* timer6 hwmod */
++static struct omap_hwmod omap2420_timer6_hwmod = {
++ .name = "timer6",
++ .mpu_irqs = omap2420_timer6_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
++ .main_clk = "gpt6_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT6_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer6_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer7 */
++static struct omap_hwmod omap2420_timer7_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
++ { .irq = 43, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
++ {
++ .pa_start = 0x48080000,
++ .pa_end = 0x48080000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer7 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer7_hwmod,
++ .clk = "gpt7_ick",
++ .addr = omap2420_timer7_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer7 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
++ &omap2420_l4_core__timer7,
++};
++
++/* timer7 hwmod */
++static struct omap_hwmod omap2420_timer7_hwmod = {
++ .name = "timer7",
++ .mpu_irqs = omap2420_timer7_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
++ .main_clk = "gpt7_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT7_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer7_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer8 */
++static struct omap_hwmod omap2420_timer8_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
++ { .irq = 44, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
++ {
++ .pa_start = 0x48082000,
++ .pa_end = 0x48082000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer8 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer8_hwmod,
++ .clk = "gpt8_ick",
++ .addr = omap2420_timer8_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer8 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
++ &omap2420_l4_core__timer8,
++};
++
++/* timer8 hwmod */
++static struct omap_hwmod omap2420_timer8_hwmod = {
++ .name = "timer8",
++ .mpu_irqs = omap2420_timer8_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
++ .main_clk = "gpt8_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT8_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer8_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer9 */
++static struct omap_hwmod omap2420_timer9_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
++ { .irq = 45, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
++ {
++ .pa_start = 0x48084000,
++ .pa_end = 0x48084000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer9 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer9_hwmod,
++ .clk = "gpt9_ick",
++ .addr = omap2420_timer9_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer9 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
++ &omap2420_l4_core__timer9,
++};
++
++/* timer9 hwmod */
++static struct omap_hwmod omap2420_timer9_hwmod = {
++ .name = "timer9",
++ .mpu_irqs = omap2420_timer9_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
++ .main_clk = "gpt9_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT9_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer9_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer10 */
++static struct omap_hwmod omap2420_timer10_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
++ { .irq = 46, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
++ {
++ .pa_start = 0x48086000,
++ .pa_end = 0x48086000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer10 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer10_hwmod,
++ .clk = "gpt10_ick",
++ .addr = omap2420_timer10_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer10 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
++ &omap2420_l4_core__timer10,
++};
++
++/* timer10 hwmod */
++static struct omap_hwmod omap2420_timer10_hwmod = {
++ .name = "timer10",
++ .mpu_irqs = omap2420_timer10_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
++ .main_clk = "gpt10_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT10_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer10_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer11 */
++static struct omap_hwmod omap2420_timer11_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
++ { .irq = 47, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
++ {
++ .pa_start = 0x48088000,
++ .pa_end = 0x48088000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer11 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer11_hwmod,
++ .clk = "gpt11_ick",
++ .addr = omap2420_timer11_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer11 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
++ &omap2420_l4_core__timer11,
++};
++
++/* timer11 hwmod */
++static struct omap_hwmod omap2420_timer11_hwmod = {
++ .name = "timer11",
++ .mpu_irqs = omap2420_timer11_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
++ .main_clk = "gpt11_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT11_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer11_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
++/* timer12 */
++static struct omap_hwmod omap2420_timer12_hwmod;
++static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
++ { .irq = 48, },
++};
++
++static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
++ {
++ .pa_start = 0x4808a000,
++ .pa_end = 0x4808a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer12 */
++static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
++ .master = &omap2420_l4_core_hwmod,
++ .slave = &omap2420_timer12_hwmod,
++ .clk = "gpt12_ick",
++ .addr = omap2420_timer12_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer12 slave port */
++static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
++ &omap2420_l4_core__timer12,
++};
++
++/* timer12 hwmod */
++static struct omap_hwmod omap2420_timer12_hwmod = {
++ .name = "timer12",
++ .mpu_irqs = omap2420_timer12_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
++ .main_clk = "gpt12_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT12_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
++ },
++ },
++ .slaves = omap2420_timer12_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
++ .class = &omap2420_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
++};
++
+ /* l4_wkup -> wd_timer2 */
+ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
+ {
+@@ -1521,6 +2141,20 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+ &omap2420_l4_wkup_hwmod,
+ &omap2420_mpu_hwmod,
+ &omap2420_iva_hwmod,
++
++ &omap2420_timer1_hwmod,
++ &omap2420_timer2_hwmod,
++ &omap2420_timer3_hwmod,
++ &omap2420_timer4_hwmod,
++ &omap2420_timer5_hwmod,
++ &omap2420_timer6_hwmod,
++ &omap2420_timer7_hwmod,
++ &omap2420_timer8_hwmod,
++ &omap2420_timer9_hwmod,
++ &omap2420_timer10_hwmod,
++ &omap2420_timer11_hwmod,
++ &omap2420_timer12_hwmod,
++
+ &omap2420_wd_timer2_hwmod,
+ &omap2420_uart1_hwmod,
+ &omap2420_uart2_hwmod,
+diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
+index dfa3aff..d6c70d2 100644
+--- a/arch/arm/plat-omap/include/plat/dmtimer.h
++++ b/arch/arm/plat-omap/include/plat/dmtimer.h
+@@ -3,6 +3,12 @@
+ *
+ * OMAP Dual-Mode Timers
+ *
++ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
++ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Platform device conversion and hwmod support.
++ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
+ * PWM and clock framwork support by Timo Teras.
+@@ -44,6 +50,11 @@
+ #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
+ #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
+
++/*
++ * IP revision identifier so that Highlander IP
++ * in OMAP4 can be distinguished.
++ */
++#define OMAP_TIMER_IP_VERSION_1 0x1
+ struct omap_dm_timer;
+ extern struct omap_dm_timer *gptimer_wakeup;
+ extern struct sys_timer omap_timer;
+--
+1.7.1
+
diff --git a/patches/for_next/0139-OMAP2430-hwmod-data-add-dmtimer.patch b/patches/for_next/0139-OMAP2430-hwmod-data-add-dmtimer.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5d51d5d0b4c1c5ac53d021f13738c76a11ee685d
--- /dev/null
+++ b/patches/for_next/0139-OMAP2430-hwmod-data-add-dmtimer.patch
@@ -0,0 +1,675 @@
+From ff8953898e4e07eb126c88108eb48f5a99a82f2f Mon Sep 17 00:00:00 2001
+From: Thara Gopinath <thara@ti.com>
+Date: Wed, 23 Feb 2011 00:14:05 -0700
+Subject: [PATCH 139/254] OMAP2430: hwmod data: add dmtimer
+
+Add dmtimer data.
+
+Signed-off-by: Thara Gopinath <thara@ti.com>
+Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 633 ++++++++++++++++++++++++++++
+ 1 files changed, 633 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 3b6d6d1..461569c 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -20,6 +20,7 @@
+ #include <plat/gpio.h>
+ #include <plat/mcbsp.h>
+ #include <plat/mcspi.h>
++#include <plat/dmtimer.h>
+ #include <plat/l3_2xxx.h>
+
+ #include "omap_hwmod_common_data.h"
+@@ -399,6 +400,624 @@ static struct omap_hwmod omap2430_iva_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+ };
+
++/* Timer Common */
++static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap2430_timer_hwmod_class = {
++ .name = "timer",
++ .sysc = &omap2430_timer_sysc,
++ .rev = OMAP_TIMER_IP_VERSION_1,
++};
++
++/* timer1 */
++static struct omap_hwmod omap2430_timer1_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
++ { .irq = 37, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
++ {
++ .pa_start = 0x49018000,
++ .pa_end = 0x49018000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_wkup -> timer1 */
++static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
++ .master = &omap2430_l4_wkup_hwmod,
++ .slave = &omap2430_timer1_hwmod,
++ .clk = "gpt1_ick",
++ .addr = omap2430_timer1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer1 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
++ &omap2430_l4_wkup__timer1,
++};
++
++/* timer1 hwmod */
++static struct omap_hwmod omap2430_timer1_hwmod = {
++ .name = "timer1",
++ .mpu_irqs = omap2430_timer1_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
++ .main_clk = "gpt1_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT1_SHIFT,
++ .module_offs = WKUP_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer2 */
++static struct omap_hwmod omap2430_timer2_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
++ { .irq = 38, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
++ {
++ .pa_start = 0x4802a000,
++ .pa_end = 0x4802a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer2 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer2_hwmod,
++ .clk = "gpt2_ick",
++ .addr = omap2430_timer2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer2 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
++ &omap2430_l4_core__timer2,
++};
++
++/* timer2 hwmod */
++static struct omap_hwmod omap2430_timer2_hwmod = {
++ .name = "timer2",
++ .mpu_irqs = omap2430_timer2_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
++ .main_clk = "gpt2_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT2_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer3 */
++static struct omap_hwmod omap2430_timer3_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
++ { .irq = 39, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
++ {
++ .pa_start = 0x48078000,
++ .pa_end = 0x48078000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer3 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer3_hwmod,
++ .clk = "gpt3_ick",
++ .addr = omap2430_timer3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer3 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
++ &omap2430_l4_core__timer3,
++};
++
++/* timer3 hwmod */
++static struct omap_hwmod omap2430_timer3_hwmod = {
++ .name = "timer3",
++ .mpu_irqs = omap2430_timer3_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
++ .main_clk = "gpt3_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT3_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer4 */
++static struct omap_hwmod omap2430_timer4_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
++ { .irq = 40, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
++ {
++ .pa_start = 0x4807a000,
++ .pa_end = 0x4807a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer4 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer4_hwmod,
++ .clk = "gpt4_ick",
++ .addr = omap2430_timer4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer4 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
++ &omap2430_l4_core__timer4,
++};
++
++/* timer4 hwmod */
++static struct omap_hwmod omap2430_timer4_hwmod = {
++ .name = "timer4",
++ .mpu_irqs = omap2430_timer4_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
++ .main_clk = "gpt4_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT4_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer5 */
++static struct omap_hwmod omap2430_timer5_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
++ { .irq = 41, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
++ {
++ .pa_start = 0x4807c000,
++ .pa_end = 0x4807c000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer5 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer5_hwmod,
++ .clk = "gpt5_ick",
++ .addr = omap2430_timer5_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer5 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
++ &omap2430_l4_core__timer5,
++};
++
++/* timer5 hwmod */
++static struct omap_hwmod omap2430_timer5_hwmod = {
++ .name = "timer5",
++ .mpu_irqs = omap2430_timer5_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
++ .main_clk = "gpt5_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT5_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer5_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer6 */
++static struct omap_hwmod omap2430_timer6_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
++ { .irq = 42, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
++ {
++ .pa_start = 0x4807e000,
++ .pa_end = 0x4807e000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer6 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer6_hwmod,
++ .clk = "gpt6_ick",
++ .addr = omap2430_timer6_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer6 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
++ &omap2430_l4_core__timer6,
++};
++
++/* timer6 hwmod */
++static struct omap_hwmod omap2430_timer6_hwmod = {
++ .name = "timer6",
++ .mpu_irqs = omap2430_timer6_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
++ .main_clk = "gpt6_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT6_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer6_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer7 */
++static struct omap_hwmod omap2430_timer7_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
++ { .irq = 43, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
++ {
++ .pa_start = 0x48080000,
++ .pa_end = 0x48080000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer7 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer7_hwmod,
++ .clk = "gpt7_ick",
++ .addr = omap2430_timer7_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer7 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
++ &omap2430_l4_core__timer7,
++};
++
++/* timer7 hwmod */
++static struct omap_hwmod omap2430_timer7_hwmod = {
++ .name = "timer7",
++ .mpu_irqs = omap2430_timer7_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
++ .main_clk = "gpt7_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT7_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer7_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer8 */
++static struct omap_hwmod omap2430_timer8_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
++ { .irq = 44, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
++ {
++ .pa_start = 0x48082000,
++ .pa_end = 0x48082000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer8 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer8_hwmod,
++ .clk = "gpt8_ick",
++ .addr = omap2430_timer8_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer8 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
++ &omap2430_l4_core__timer8,
++};
++
++/* timer8 hwmod */
++static struct omap_hwmod omap2430_timer8_hwmod = {
++ .name = "timer8",
++ .mpu_irqs = omap2430_timer8_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
++ .main_clk = "gpt8_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT8_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer8_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer9 */
++static struct omap_hwmod omap2430_timer9_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
++ { .irq = 45, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
++ {
++ .pa_start = 0x48084000,
++ .pa_end = 0x48084000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer9 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer9_hwmod,
++ .clk = "gpt9_ick",
++ .addr = omap2430_timer9_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer9 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
++ &omap2430_l4_core__timer9,
++};
++
++/* timer9 hwmod */
++static struct omap_hwmod omap2430_timer9_hwmod = {
++ .name = "timer9",
++ .mpu_irqs = omap2430_timer9_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
++ .main_clk = "gpt9_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT9_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer9_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer10 */
++static struct omap_hwmod omap2430_timer10_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
++ { .irq = 46, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
++ {
++ .pa_start = 0x48086000,
++ .pa_end = 0x48086000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer10 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer10_hwmod,
++ .clk = "gpt10_ick",
++ .addr = omap2430_timer10_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer10 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
++ &omap2430_l4_core__timer10,
++};
++
++/* timer10 hwmod */
++static struct omap_hwmod omap2430_timer10_hwmod = {
++ .name = "timer10",
++ .mpu_irqs = omap2430_timer10_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
++ .main_clk = "gpt10_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT10_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer10_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer11 */
++static struct omap_hwmod omap2430_timer11_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
++ { .irq = 47, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
++ {
++ .pa_start = 0x48088000,
++ .pa_end = 0x48088000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer11 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer11_hwmod,
++ .clk = "gpt11_ick",
++ .addr = omap2430_timer11_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer11 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
++ &omap2430_l4_core__timer11,
++};
++
++/* timer11 hwmod */
++static struct omap_hwmod omap2430_timer11_hwmod = {
++ .name = "timer11",
++ .mpu_irqs = omap2430_timer11_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
++ .main_clk = "gpt11_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT11_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer11_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
++/* timer12 */
++static struct omap_hwmod omap2430_timer12_hwmod;
++static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
++ { .irq = 48, },
++};
++
++static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
++ {
++ .pa_start = 0x4808a000,
++ .pa_end = 0x4808a000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer12 */
++static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_timer12_hwmod,
++ .clk = "gpt12_ick",
++ .addr = omap2430_timer12_addrs,
++ .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer12 slave port */
++static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
++ &omap2430_l4_core__timer12,
++};
++
++/* timer12 hwmod */
++static struct omap_hwmod omap2430_timer12_hwmod = {
++ .name = "timer12",
++ .mpu_irqs = omap2430_timer12_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
++ .main_clk = "gpt12_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP24XX_EN_GPT12_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
++ },
++ },
++ .slaves = omap2430_timer12_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
++ .class = &omap2430_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
++};
++
+ /* l4_wkup -> wd_timer2 */
+ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
+ {
+@@ -1896,6 +2515,20 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ &omap2430_l4_wkup_hwmod,
+ &omap2430_mpu_hwmod,
+ &omap2430_iva_hwmod,
++
++ &omap2430_timer1_hwmod,
++ &omap2430_timer2_hwmod,
++ &omap2430_timer3_hwmod,
++ &omap2430_timer4_hwmod,
++ &omap2430_timer5_hwmod,
++ &omap2430_timer6_hwmod,
++ &omap2430_timer7_hwmod,
++ &omap2430_timer8_hwmod,
++ &omap2430_timer9_hwmod,
++ &omap2430_timer10_hwmod,
++ &omap2430_timer11_hwmod,
++ &omap2430_timer12_hwmod,
++
+ &omap2430_wd_timer2_hwmod,
+ &omap2430_uart1_hwmod,
+ &omap2430_uart2_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0140-OMAP3-hwmod-data-add-dmtimer.patch b/patches/for_next/0140-OMAP3-hwmod-data-add-dmtimer.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3b6b8e8f40420dd6148ebc5c14a453456b208a16
--- /dev/null
+++ b/patches/for_next/0140-OMAP3-hwmod-data-add-dmtimer.patch
@@ -0,0 +1,691 @@
+From 4bf3e33bb75315f1b3c2c0ba7d4c82203b05b9e5 Mon Sep 17 00:00:00 2001
+From: Thara Gopinath <thara@ti.com>
+Date: Wed, 23 Feb 2011 00:14:05 -0700
+Subject: [PATCH 140/254] OMAP3: hwmod data: add dmtimer
+
+Add dmtimer data.
+
+Signed-off-by: Thara Gopinath <thara@ti.com>
+Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 649 ++++++++++++++++++++++++++++
+ 1 files changed, 649 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 3dd6730..5f91e1f 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -25,6 +25,7 @@
+ #include <plat/smartreflex.h>
+ #include <plat/mcbsp.h>
+ #include <plat/mcspi.h>
++#include <plat/dmtimer.h>
+
+ #include "omap_hwmod_common_data.h"
+
+@@ -524,6 +525,640 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+ };
+
++/* timer class */
++static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
++ .name = "timer",
++ .sysc = &omap3xxx_timer_1ms_sysc,
++ .rev = OMAP_TIMER_IP_VERSION_1,
++};
++
++static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
++ .rev_offs = 0x0000,
++ .sysc_offs = 0x0010,
++ .syss_offs = 0x0014,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
++ .name = "timer",
++ .sysc = &omap3xxx_timer_sysc,
++ .rev = OMAP_TIMER_IP_VERSION_1,
++};
++
++/* timer1 */
++static struct omap_hwmod omap3xxx_timer1_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
++ { .irq = 37, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
++ {
++ .pa_start = 0x48318000,
++ .pa_end = 0x48318000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_wkup -> timer1 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
++ .master = &omap3xxx_l4_wkup_hwmod,
++ .slave = &omap3xxx_timer1_hwmod,
++ .clk = "gpt1_ick",
++ .addr = omap3xxx_timer1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer1 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
++ &omap3xxx_l4_wkup__timer1,
++};
++
++/* timer1 hwmod */
++static struct omap_hwmod omap3xxx_timer1_hwmod = {
++ .name = "timer1",
++ .mpu_irqs = omap3xxx_timer1_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
++ .main_clk = "gpt1_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT1_SHIFT,
++ .module_offs = WKUP_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
++ .class = &omap3xxx_timer_1ms_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer2 */
++static struct omap_hwmod omap3xxx_timer2_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
++ { .irq = 38, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
++ {
++ .pa_start = 0x49032000,
++ .pa_end = 0x49032000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer2 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_timer2_hwmod,
++ .clk = "gpt2_ick",
++ .addr = omap3xxx_timer2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer2 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
++ &omap3xxx_l4_per__timer2,
++};
++
++/* timer2 hwmod */
++static struct omap_hwmod omap3xxx_timer2_hwmod = {
++ .name = "timer2",
++ .mpu_irqs = omap3xxx_timer2_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
++ .main_clk = "gpt2_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT2_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
++ .class = &omap3xxx_timer_1ms_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer3 */
++static struct omap_hwmod omap3xxx_timer3_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
++ { .irq = 39, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
++ {
++ .pa_start = 0x49034000,
++ .pa_end = 0x49034000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer3 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_timer3_hwmod,
++ .clk = "gpt3_ick",
++ .addr = omap3xxx_timer3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer3 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
++ &omap3xxx_l4_per__timer3,
++};
++
++/* timer3 hwmod */
++static struct omap_hwmod omap3xxx_timer3_hwmod = {
++ .name = "timer3",
++ .mpu_irqs = omap3xxx_timer3_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
++ .main_clk = "gpt3_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT3_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer4 */
++static struct omap_hwmod omap3xxx_timer4_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
++ { .irq = 40, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
++ {
++ .pa_start = 0x49036000,
++ .pa_end = 0x49036000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer4 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_timer4_hwmod,
++ .clk = "gpt4_ick",
++ .addr = omap3xxx_timer4_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer4 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
++ &omap3xxx_l4_per__timer4,
++};
++
++/* timer4 hwmod */
++static struct omap_hwmod omap3xxx_timer4_hwmod = {
++ .name = "timer4",
++ .mpu_irqs = omap3xxx_timer4_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
++ .main_clk = "gpt4_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT4_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer4_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer5 */
++static struct omap_hwmod omap3xxx_timer5_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
++ { .irq = 41, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
++ {
++ .pa_start = 0x49038000,
++ .pa_end = 0x49038000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer5 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_timer5_hwmod,
++ .clk = "gpt5_ick",
++ .addr = omap3xxx_timer5_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer5 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
++ &omap3xxx_l4_per__timer5,
++};
++
++/* timer5 hwmod */
++static struct omap_hwmod omap3xxx_timer5_hwmod = {
++ .name = "timer5",
++ .mpu_irqs = omap3xxx_timer5_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
++ .main_clk = "gpt5_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT5_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer5_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer6 */
++static struct omap_hwmod omap3xxx_timer6_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
++ { .irq = 42, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
++ {
++ .pa_start = 0x4903A000,
++ .pa_end = 0x4903A000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer6 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_timer6_hwmod,
++ .clk = "gpt6_ick",
++ .addr = omap3xxx_timer6_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer6 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
++ &omap3xxx_l4_per__timer6,
++};
++
++/* timer6 hwmod */
++static struct omap_hwmod omap3xxx_timer6_hwmod = {
++ .name = "timer6",
++ .mpu_irqs = omap3xxx_timer6_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
++ .main_clk = "gpt6_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT6_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer6_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer7 */
++static struct omap_hwmod omap3xxx_timer7_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
++ { .irq = 43, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
++ {
++ .pa_start = 0x4903C000,
++ .pa_end = 0x4903C000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer7 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_timer7_hwmod,
++ .clk = "gpt7_ick",
++ .addr = omap3xxx_timer7_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer7 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
++ &omap3xxx_l4_per__timer7,
++};
++
++/* timer7 hwmod */
++static struct omap_hwmod omap3xxx_timer7_hwmod = {
++ .name = "timer7",
++ .mpu_irqs = omap3xxx_timer7_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
++ .main_clk = "gpt7_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT7_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer7_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer8 */
++static struct omap_hwmod omap3xxx_timer8_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
++ { .irq = 44, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
++ {
++ .pa_start = 0x4903E000,
++ .pa_end = 0x4903E000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer8 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_timer8_hwmod,
++ .clk = "gpt8_ick",
++ .addr = omap3xxx_timer8_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer8 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
++ &omap3xxx_l4_per__timer8,
++};
++
++/* timer8 hwmod */
++static struct omap_hwmod omap3xxx_timer8_hwmod = {
++ .name = "timer8",
++ .mpu_irqs = omap3xxx_timer8_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
++ .main_clk = "gpt8_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT8_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer8_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer9 */
++static struct omap_hwmod omap3xxx_timer9_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
++ { .irq = 45, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
++ {
++ .pa_start = 0x49040000,
++ .pa_end = 0x49040000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_per -> timer9 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
++ .master = &omap3xxx_l4_per_hwmod,
++ .slave = &omap3xxx_timer9_hwmod,
++ .clk = "gpt9_ick",
++ .addr = omap3xxx_timer9_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer9 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
++ &omap3xxx_l4_per__timer9,
++};
++
++/* timer9 hwmod */
++static struct omap_hwmod omap3xxx_timer9_hwmod = {
++ .name = "timer9",
++ .mpu_irqs = omap3xxx_timer9_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
++ .main_clk = "gpt9_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT9_SHIFT,
++ .module_offs = OMAP3430_PER_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer9_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer10 */
++static struct omap_hwmod omap3xxx_timer10_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
++ { .irq = 46, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
++ {
++ .pa_start = 0x48086000,
++ .pa_end = 0x48086000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer10 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_timer10_hwmod,
++ .clk = "gpt10_ick",
++ .addr = omap3xxx_timer10_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer10 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
++ &omap3xxx_l4_core__timer10,
++};
++
++/* timer10 hwmod */
++static struct omap_hwmod omap3xxx_timer10_hwmod = {
++ .name = "timer10",
++ .mpu_irqs = omap3xxx_timer10_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
++ .main_clk = "gpt10_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT10_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer10_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
++ .class = &omap3xxx_timer_1ms_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer11 */
++static struct omap_hwmod omap3xxx_timer11_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
++ { .irq = 47, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
++ {
++ .pa_start = 0x48088000,
++ .pa_end = 0x48088000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer11 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_timer11_hwmod,
++ .clk = "gpt11_ick",
++ .addr = omap3xxx_timer11_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer11 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
++ &omap3xxx_l4_core__timer11,
++};
++
++/* timer11 hwmod */
++static struct omap_hwmod omap3xxx_timer11_hwmod = {
++ .name = "timer11",
++ .mpu_irqs = omap3xxx_timer11_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
++ .main_clk = "gpt11_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT11_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer11_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* timer12*/
++static struct omap_hwmod omap3xxx_timer12_hwmod;
++static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
++ { .irq = 95, },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
++ {
++ .pa_start = 0x48304000,
++ .pa_end = 0x48304000 + SZ_1K - 1,
++ .flags = ADDR_TYPE_RT
++ },
++};
++
++/* l4_core -> timer12 */
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_timer12_hwmod,
++ .clk = "gpt12_ick",
++ .addr = omap3xxx_timer12_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* timer12 slave port */
++static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
++ &omap3xxx_l4_core__timer12,
++};
++
++/* timer12 hwmod */
++static struct omap_hwmod omap3xxx_timer12_hwmod = {
++ .name = "timer12",
++ .mpu_irqs = omap3xxx_timer12_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
++ .main_clk = "gpt12_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_GPT12_SHIFT,
++ .module_offs = WKUP_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_timer12_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
++ .class = &omap3xxx_timer_hwmod_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
+ /* l4_wkup -> wd_timer2 */
+ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
+ {
+@@ -2642,6 +3277,20 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ &omap3xxx_l4_wkup_hwmod,
+ &omap3xxx_mpu_hwmod,
+ &omap3xxx_iva_hwmod,
++
++ &omap3xxx_timer1_hwmod,
++ &omap3xxx_timer2_hwmod,
++ &omap3xxx_timer3_hwmod,
++ &omap3xxx_timer4_hwmod,
++ &omap3xxx_timer5_hwmod,
++ &omap3xxx_timer6_hwmod,
++ &omap3xxx_timer7_hwmod,
++ &omap3xxx_timer8_hwmod,
++ &omap3xxx_timer9_hwmod,
++ &omap3xxx_timer10_hwmod,
++ &omap3xxx_timer11_hwmod,
++ &omap3xxx_timer12_hwmod,
++
+ &omap3xxx_wd_timer2_hwmod,
+ &omap3xxx_uart1_hwmod,
+ &omap3xxx_uart2_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0141-OMAP2-hwmod-allow-multiple-calls-to-omap_hwmod_init.patch b/patches/for_next/0141-OMAP2-hwmod-allow-multiple-calls-to-omap_hwmod_init.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9514989e5d58068512043e16a5653e1eb3ca1dbd
--- /dev/null
+++ b/patches/for_next/0141-OMAP2-hwmod-allow-multiple-calls-to-omap_hwmod_init.patch
@@ -0,0 +1,77 @@
+From 161f2d2df88dc02c702a29aeb038fdd8c67a8475 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 23 Feb 2011 00:14:06 -0700
+Subject: [PATCH 141/254] OMAP2+: hwmod: allow multiple calls to omap_hwmod_init()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no longer any reason why we should prevent multiple
+calls to omap_hwmod_init(). It is now simply used to register an
+array of hwmods.
+
+This should allow a subset of hwmods (e.g., hwmods
+handling the system clocksource and clockevents) to be registered
+earlier than the remaining mass of hwmods.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 29 ++++++++++-------------------
+ 1 files changed, 10 insertions(+), 19 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index c7762ab..b3d2f15 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list);
+ /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
+ static struct omap_hwmod *mpu_oh;
+
+-/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */
+-static u8 inited;
+-
+
+ /* Private functions */
+
+@@ -1595,26 +1592,20 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+ */
+ int __init omap_hwmod_init(struct omap_hwmod **ohs)
+ {
+- struct omap_hwmod *oh;
+- int r;
+-
+- if (inited)
+- return -EINVAL;
+-
+- inited = 1;
++ int r, i;
+
+ if (!ohs)
+ return 0;
+
+- oh = *ohs;
+- while (oh) {
+- if (omap_chip_is(oh->omap_chip)) {
+- r = _register(oh);
+- WARN(r, "omap_hwmod: %s: _register returned "
+- "%d\n", oh->name, r);
+- }
+- oh = *++ohs;
+- }
++ i = 0;
++ do {
++ if (!omap_chip_is(ohs[i]->omap_chip))
++ continue;
++
++ r = _register(ohs[i]);
++ WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
++ r);
++ } while (ohs[++i]);
+
+ return 0;
+ }
+--
+1.7.1
+
diff --git a/patches/for_next/0142-OMAP2-hwmod-rename-some-init-functions.patch b/patches/for_next/0142-OMAP2-hwmod-rename-some-init-functions.patch
new file mode 100644
index 0000000000000000000000000000000000000000..cfc02fe06b8fa3888bc0a7bd03715e4482a87dc8
--- /dev/null
+++ b/patches/for_next/0142-OMAP2-hwmod-rename-some-init-functions.patch
@@ -0,0 +1,231 @@
+From 367b94e822fde6845f9635603ada14d0cf4a9f41 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Mon, 28 Feb 2011 11:58:14 -0700
+Subject: [PATCH 142/254] OMAP2+: hwmod: rename some init functions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Rename omap_hwmod_init() to omap_hwmod_register(). Rename
+omap_hwmod_late_init() to omap_hwmod_setup_all(). Also change all of
+the callers to reflect the new names. While here, update some
+copyrights.
+
+Suggested by Tony Lindgren <tony@atomide.com>.
+
+N.B. The comment in mach-omap2/serial.c may no longer be correct, given
+ recent changes in init order.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 33 +++++++++++--------------
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 2 +-
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 +-
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +-
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +-
+ arch/arm/mach-omap2/serial.c | 2 +-
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 6 +++-
+ 7 files changed, 24 insertions(+), 25 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index b3d2f15..2ce52ce 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1,7 +1,7 @@
+ /*
+ * omap_hwmod implementation for OMAP2/3/4
+ *
+- * Copyright (C) 2009-2010 Nokia Corporation
++ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Paul Walmsley, Benoît Cousson, Kevin Hilman
+ *
+@@ -901,7 +901,7 @@ static struct omap_hwmod *_lookup(const char *name)
+ * @oh: struct omap_hwmod *
+ * @data: not used; pass NULL
+ *
+- * Called by omap_hwmod_late_init() (after omap2_clk_init()).
++ * Called by omap_hwmod_setup_all() (after omap2_clk_init()).
+ * Resolves all clock names embedded in the hwmod. Returns -EINVAL if
+ * the omap_hwmod has not yet been registered or if the clocks have
+ * already been initialized, 0 on success, or a non-zero error on
+@@ -1580,17 +1580,15 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+ return ret;
+ }
+
+-
+ /**
+- * omap_hwmod_init - init omap_hwmod code and register hwmods
++ * omap_hwmod_register - register an array of hwmods
+ * @ohs: pointer to an array of omap_hwmods to register
+ *
+ * Intended to be called early in boot before the clock framework is
+ * initialized. If @ohs is not null, will register all omap_hwmods
+- * listed in @ohs that are valid for this chip. Returns -EINVAL if
+- * omap_hwmod_init() has already been called or 0 otherwise.
++ * listed in @ohs that are valid for this chip. Returns 0.
+ */
+-int __init omap_hwmod_init(struct omap_hwmod **ohs)
++int __init omap_hwmod_register(struct omap_hwmod **ohs)
+ {
+ int r, i;
+
+@@ -1613,9 +1611,8 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs)
+ /*
+ * _populate_mpu_rt_base - populate the virtual address for a hwmod
+ *
+- * Must be called only from omap_hwmod_late_init so ioremap works properly.
++ * Must be called only from omap_hwmod_setup_all() so ioremap works properly.
+ * Assumes the caller takes care of locking if needed.
+- *
+ */
+ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+ {
+@@ -1631,13 +1628,13 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+ }
+
+ /**
+- * omap_hwmod_late_init - do some post-clock framework initialization
++ * omap_hwmod_setup - do some post-clock framework initialization
+ *
+ * Must be called after omap2_clk_init(). Resolves the struct clk names
+ * to struct clk pointers for each registered omap_hwmod. Also calls
+ * _setup() on each hwmod. Returns 0.
+ */
+-static int __init omap_hwmod_late_init(void)
++static int __init omap_hwmod_setup_all(void)
+ {
+ int r;
+
+@@ -1645,7 +1642,7 @@ static int __init omap_hwmod_late_init(void)
+
+ /* XXX check return value */
+ r = omap_hwmod_for_each(_init_clocks, NULL);
+- WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");
++ WARN(r, "omap_hwmod: %s: _init_clocks failed\n", __func__);
+
+ mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
+ WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
+@@ -1655,7 +1652,7 @@ static int __init omap_hwmod_late_init(void)
+
+ return 0;
+ }
+-core_initcall(omap_hwmod_late_init);
++core_initcall(omap_hwmod_setup_all);
+
+ /**
+ * omap_hwmod_enable - enable an omap_hwmod
+@@ -2175,11 +2172,11 @@ int omap_hwmod_for_each_by_class(const char *classname,
+ * @oh: struct omap_hwmod *
+ * @state: state that _setup() should leave the hwmod in
+ *
+- * Sets the hwmod state that @oh will enter at the end of _setup() (called by
+- * omap_hwmod_late_init()). Only valid to call between calls to
+- * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or
+- * -EINVAL if there is a problem with the arguments or if the hwmod is
+- * in the wrong state.
++ * Sets the hwmod state that @oh will enter at the end of _setup()
++ * (called by omap_hwmod_setup_all()). Only valid to call between
++ * calling omap_hwmod_register() and omap_hwmod_setup_all(). Returns
++ * 0 upon success or -EINVAL if there is a problem with the arguments
++ * or if the hwmod is in the wrong state.
+ */
+ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
+ {
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index f4a38f1..e0bc2c7 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -2192,5 +2192,5 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+
+ int __init omap2420_hwmod_init(void)
+ {
+- return omap_hwmod_init(omap2420_hwmods);
++ return omap_hwmod_register(omap2420_hwmods);
+ }
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 461569c..c841678 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -2571,5 +2571,5 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+
+ int __init omap2430_hwmod_init(void)
+ {
+- return omap_hwmod_init(omap2430_hwmods);
++ return omap_hwmod_register(omap2430_hwmods);
+ }
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 5f91e1f..9cd116b 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -3347,5 +3347,5 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+
+ int __init omap3xxx_hwmod_init(void)
+ {
+- return omap_hwmod_init(omap3xxx_hwmods);
++ return omap_hwmod_register(omap3xxx_hwmods);
+ }
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 673b011..f6a4484 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -5133,6 +5133,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+
+ int __init omap44xx_hwmod_init(void)
+ {
+- return omap_hwmod_init(omap44xx_hwmods);
++ return omap_hwmod_register(omap44xx_hwmods);
+ }
+
+diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
+index 47eef48..1ac361b 100644
+--- a/arch/arm/mach-omap2/serial.c
++++ b/arch/arm/mach-omap2/serial.c
+@@ -680,7 +680,7 @@ static int __init omap_serial_early_init(void)
+ num_uarts++;
+
+ /*
+- * NOTE: omap_hwmod_init() has not yet been called,
++ * NOTE: omap_hwmod_setup*() has not yet been called,
+ * so no hwmod functions will work yet.
+ */
+
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 04b1ea1..1cd6911 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -1,7 +1,7 @@
+ /*
+ * omap_hwmod macros, structures
+ *
+- * Copyright (C) 2009-2010 Nokia Corporation
++ * Copyright (C) 2009-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * Created in collaboration with (alphabetical order): Benoît Cousson,
+@@ -372,8 +372,10 @@ struct omap_hwmod_omap4_prcm {
+ * of standby, rather than relying on module smart-standby
+ * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
+ * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
++ * XXX Should be HWMOD_SETUP_NO_RESET
+ * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
+ * controller, etc. XXX probably belongs outside the main hwmod file
++ * XXX Should be HWMOD_SETUP_NO_IDLE
+ * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ * when module is enabled, rather than the default, which is to
+ * enable autoidle
+@@ -537,7 +539,7 @@ struct omap_hwmod {
+ const struct omap_chip_id omap_chip;
+ };
+
+-int omap_hwmod_init(struct omap_hwmod **ohs);
++int omap_hwmod_register(struct omap_hwmod **ohs);
+ struct omap_hwmod *omap_hwmod_lookup(const char *name);
+ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+ void *data);
+--
+1.7.1
+
diff --git a/patches/for_next/0143-OMAP2-hwmod-find-MPU-initiator-hwmod-during-in-_regi.patch b/patches/for_next/0143-OMAP2-hwmod-find-MPU-initiator-hwmod-during-in-_regi.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8488ecabb28ca821628c500e5edce61e080aa043
--- /dev/null
+++ b/patches/for_next/0143-OMAP2-hwmod-find-MPU-initiator-hwmod-during-in-_regi.patch
@@ -0,0 +1,86 @@
+From 516db1cca7eb0e13df8e9ec7a43c87597e46e3b2 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 23 Feb 2011 00:14:06 -0700
+Subject: [PATCH 143/254] OMAP2+: hwmod: find MPU initiator hwmod during in _register()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Move the code that looks for the MPU initiator hwmod to run during
+the individual hwmod _register() function. (Previously, it ran after
+all hwmods were registered in the omap_hwmod_late_init() function.)
+
+This is done so code can late-initialize a few individual hwmods --
+for example, for the system timer -- before the entire set of hwmods is
+initialized later in boot via omap_hwmod_late_init().
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 23 +++++++++++++++--------
+ 1 files changed, 15 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 2ce52ce..d45c9b2 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1452,7 +1452,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
+ */
+ static int __init _register(struct omap_hwmod *oh)
+ {
+- int ret, ms_id;
++ int ms_id;
+
+ if (!oh || !oh->name || !oh->class || !oh->class->name ||
+ (oh->_state != _HWMOD_STATE_UNKNOWN))
+@@ -1475,9 +1475,14 @@ static int __init _register(struct omap_hwmod *oh)
+
+ oh->_state = _HWMOD_STATE_REGISTERED;
+
+- ret = 0;
++ /*
++ * XXX Rather than doing a strcmp(), this should test a flag
++ * set in the hwmod data, inserted by the autogenerator code.
++ */
++ if (!strcmp(oh->name, MPU_INITIATOR_NAME))
++ mpu_oh = oh;
+
+- return ret;
++ return 0;
+ }
+
+
+@@ -1632,22 +1637,24 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+ *
+ * Must be called after omap2_clk_init(). Resolves the struct clk names
+ * to struct clk pointers for each registered omap_hwmod. Also calls
+- * _setup() on each hwmod. Returns 0.
++ * _setup() on each hwmod. Returns 0 upon success or -EINVAL upon error.
+ */
+ static int __init omap_hwmod_setup_all(void)
+ {
+ int r;
+
++ if (!mpu_oh) {
++ pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
++ __func__, MPU_INITIATOR_NAME);
++ return -EINVAL;
++ }
++
+ r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
+
+ /* XXX check return value */
+ r = omap_hwmod_for_each(_init_clocks, NULL);
+ WARN(r, "omap_hwmod: %s: _init_clocks failed\n", __func__);
+
+- mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
+- WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
+- MPU_INITIATOR_NAME);
+-
+ omap_hwmod_for_each(_setup, NULL);
+
+ return 0;
+--
+1.7.1
+
diff --git a/patches/for_next/0144-OMAP2-hwmod-ignore-attempts-to-re-setup-a-hwmod.patch b/patches/for_next/0144-OMAP2-hwmod-ignore-attempts-to-re-setup-a-hwmod.patch
new file mode 100644
index 0000000000000000000000000000000000000000..0a9642f17e38cc7ae2a944d5c7846385c54157e1
--- /dev/null
+++ b/patches/for_next/0144-OMAP2-hwmod-ignore-attempts-to-re-setup-a-hwmod.patch
@@ -0,0 +1,80 @@
+From 2354f64c5574daa2fce858d083a12feec5eb6fb3 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 23 Feb 2011 00:14:07 -0700
+Subject: [PATCH 144/254] OMAP2+: hwmod: ignore attempts to re-setup a hwmod
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Previously, if a hwmod had already been set up, and the code attempted
+to set up the hwmod again, an error would be returned. This is not
+really useful behavior if we wish to allow the OMAP core code to setup
+the hwmods needed for the Linux clocksources and clockevents before
+the rest of the hwmods are setup. So, instead of generating errors,
+just ignore the attempt to re-setup the hwmod.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 19 +++++++++++--------
+ 1 files changed, 11 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index d45c9b2..6107ef4 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -902,17 +902,15 @@ static struct omap_hwmod *_lookup(const char *name)
+ * @data: not used; pass NULL
+ *
+ * Called by omap_hwmod_setup_all() (after omap2_clk_init()).
+- * Resolves all clock names embedded in the hwmod. Returns -EINVAL if
+- * the omap_hwmod has not yet been registered or if the clocks have
+- * already been initialized, 0 on success, or a non-zero error on
+- * failure.
++ * Resolves all clock names embedded in the hwmod. Returns 0 on
++ * success, or a negative error code on failure.
+ */
+ static int _init_clocks(struct omap_hwmod *oh, void *data)
+ {
+ int ret = 0;
+
+- if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED))
+- return -EINVAL;
++ if (oh->_state != _HWMOD_STATE_REGISTERED)
++ return 0;
+
+ pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
+
+@@ -1351,14 +1349,16 @@ static int _shutdown(struct omap_hwmod *oh)
+ * @oh: struct omap_hwmod *
+ *
+ * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
+- * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the
+- * wrong state or returns 0.
++ * OCP_SYSCONFIG register. Returns 0.
+ */
+ static int _setup(struct omap_hwmod *oh, void *data)
+ {
+ int i, r;
+ u8 postsetup_state;
+
++ if (oh->_state != _HWMOD_STATE_CLKS_INITED)
++ return 0;
++
+ /* Set iclk autoidle mode */
+ if (oh->slaves_cnt > 0) {
+ for (i = 0; i < oh->slaves_cnt; i++) {
+@@ -1621,6 +1621,9 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
+ */
+ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+ {
++ if (oh->_state != _HWMOD_STATE_REGISTERED)
++ return 0;
++
+ if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ return 0;
+
+--
+1.7.1
+
diff --git a/patches/for_next/0145-OMAP2-hwmod-add-ability-to-setup-individual-hwmods.patch b/patches/for_next/0145-OMAP2-hwmod-add-ability-to-setup-individual-hwmods.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8d70e947c5dac3a4d00dbb117259ee3b0e11788b
--- /dev/null
+++ b/patches/for_next/0145-OMAP2-hwmod-add-ability-to-setup-individual-hwmods.patch
@@ -0,0 +1,155 @@
+From c00a5be7577e577421a9e32a9bf98305e3365a8e Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 23 Feb 2011 00:14:07 -0700
+Subject: [PATCH 145/254] OMAP2+: hwmod: add ability to setup individual hwmods
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add omap_hwmod_setup_one(), which is intended for use early in boot to
+selectively setup the hwmods needed for system clocksources and
+clockevents, and any other hwmod that is needed in early boot.
+omap_hwmod_setup_all() can then be called later in the boot process.
+The point is to minimize the amount of code that needs to be run
+early.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 62 +++++++++++++++++++++++---
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 +
+ 2 files changed, 58 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 6107ef4..1125134 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -901,7 +901,7 @@ static struct omap_hwmod *_lookup(const char *name)
+ * @oh: struct omap_hwmod *
+ * @data: not used; pass NULL
+ *
+- * Called by omap_hwmod_setup_all() (after omap2_clk_init()).
++ * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
+ * Resolves all clock names embedded in the hwmod. Returns 0 on
+ * success, or a negative error code on failure.
+ */
+@@ -1616,7 +1616,7 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
+ /*
+ * _populate_mpu_rt_base - populate the virtual address for a hwmod
+ *
+- * Must be called only from omap_hwmod_setup_all() so ioremap works properly.
++ * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
+ * Assumes the caller takes care of locking if needed.
+ */
+ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+@@ -1636,11 +1636,59 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+ }
+
+ /**
++ * omap_hwmod_setup_one - set up a single hwmod
++ * @oh_name: const char * name of the already-registered hwmod to set up
++ *
++ * Must be called after omap2_clk_init(). Resolves the struct clk
++ * names to struct clk pointers for each registered omap_hwmod. Also
++ * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon
++ * success.
++ */
++int __init omap_hwmod_setup_one(const char *oh_name)
++{
++ struct omap_hwmod *oh;
++ int r;
++
++ pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
++
++ if (!mpu_oh) {
++ pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
++ oh_name, MPU_INITIATOR_NAME);
++ return -EINVAL;
++ }
++
++ oh = _lookup(oh_name);
++ if (!oh) {
++ WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
++ return -EINVAL;
++ }
++
++ if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
++ omap_hwmod_setup_one(MPU_INITIATOR_NAME);
++
++ r = _populate_mpu_rt_base(oh, NULL);
++ if (IS_ERR_VALUE(r)) {
++ WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
++ return -EINVAL;
++ }
++
++ r = _init_clocks(oh, NULL);
++ if (IS_ERR_VALUE(r)) {
++ WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
++ return -EINVAL;
++ }
++
++ _setup(oh, NULL);
++
++ return 0;
++}
++
++/**
+ * omap_hwmod_setup - do some post-clock framework initialization
+ *
+ * Must be called after omap2_clk_init(). Resolves the struct clk names
+ * to struct clk pointers for each registered omap_hwmod. Also calls
+- * _setup() on each hwmod. Returns 0 upon success or -EINVAL upon error.
++ * _setup() on each hwmod. Returns 0 upon success.
+ */
+ static int __init omap_hwmod_setup_all(void)
+ {
+@@ -1654,9 +1702,9 @@ static int __init omap_hwmod_setup_all(void)
+
+ r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
+
+- /* XXX check return value */
+ r = omap_hwmod_for_each(_init_clocks, NULL);
+- WARN(r, "omap_hwmod: %s: _init_clocks failed\n", __func__);
++ WARN(IS_ERR_VALUE(r),
++ "omap_hwmod: %s: _init_clocks failed\n", __func__);
+
+ omap_hwmod_for_each(_setup, NULL);
+
+@@ -2183,8 +2231,8 @@ int omap_hwmod_for_each_by_class(const char *classname,
+ * @state: state that _setup() should leave the hwmod in
+ *
+ * Sets the hwmod state that @oh will enter at the end of _setup()
+- * (called by omap_hwmod_setup_all()). Only valid to call between
+- * calling omap_hwmod_register() and omap_hwmod_setup_all(). Returns
++ * (called by omap_hwmod_setup_*()). Only valid to call between
++ * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns
+ * 0 upon success or -EINVAL if there is a problem with the arguments
+ * or if the hwmod is in the wrong state.
+ */
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 1cd6911..97aa8e7 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -30,6 +30,7 @@
+ #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
+
+ #include <linux/kernel.h>
++#include <linux/init.h>
+ #include <linux/list.h>
+ #include <linux/ioport.h>
+ #include <linux/spinlock.h>
+@@ -544,6 +545,8 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name);
+ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
+ void *data);
+
++int __init omap_hwmod_setup_one(const char *name);
++
+ int omap_hwmod_enable(struct omap_hwmod *oh);
+ int _omap_hwmod_enable(struct omap_hwmod *oh);
+ int omap_hwmod_idle(struct omap_hwmod *oh);
+--
+1.7.1
+
diff --git a/patches/for_next/0146-OMAP2-clockevent-set-up-GPTIMER-clockevent-hwmod-rig.patch b/patches/for_next/0146-OMAP2-clockevent-set-up-GPTIMER-clockevent-hwmod-rig.patch
new file mode 100644
index 0000000000000000000000000000000000000000..47adeacf722f286fa227e986a63acc97c38fb962
--- /dev/null
+++ b/patches/for_next/0146-OMAP2-clockevent-set-up-GPTIMER-clockevent-hwmod-rig.patch
@@ -0,0 +1,66 @@
+From 5051bf5e7f2a57477b3be6311d66e4168ce010ff Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 23 Feb 2011 00:14:08 -0700
+Subject: [PATCH 146/254] OMAP2+: clockevent: set up GPTIMER clockevent hwmod right before timer init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Set up the GPTIMER hwmod used for the clockevent source immediately
+before it is used. This avoids the need to set up all of the hwmods
+until the boot process is further along. (In general, we want to defer
+as much as possible until late in the boot process.)
+
+This second version fixes a bug pointed out by Santosh Shilimkar
+<santosh.shilimkar@ti.com>, that would cause the kernel to use an
+incorrect timer hwmod name if the selected GPTIMER was not 1 or 12 -
+thanks Santosh. Also, Tarun Kanti DebBarma <tarun.kanti@ti.com>
+pointed out that the original patch did not apply cleanly; this has
+now been fixed.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Cc: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+---
+ arch/arm/mach-omap2/timer-gp.c | 8 ++++++--
+ 1 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
+index 0fc550e..1887dd0 100644
+--- a/arch/arm/mach-omap2/timer-gp.c
++++ b/arch/arm/mach-omap2/timer-gp.c
+@@ -39,11 +39,11 @@
+ #include <asm/mach/time.h>
+ #include <plat/dmtimer.h>
+ #include <asm/localtimer.h>
+-#include <asm/sched_clock.h>
++#include <plat/common.h>
++#include <plat/omap_hwmod.h>
+
+ #include "timer-gp.h"
+
+-#include <plat/common.h>
+
+ /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
+ #define MAX_GPTIMER_ID 12
+@@ -133,9 +133,13 @@ static void __init omap2_gp_clockevent_init(void)
+ {
+ u32 tick_rate;
+ int src;
++ char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
+
+ inited = 1;
+
++ sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
++ omap_hwmod_setup_one(clockevent_hwmod_name);
++
+ gptimer = omap_dm_timer_request_specific(gptimer_id);
+ BUG_ON(gptimer == NULL);
+ gptimer_wakeup = gptimer;
+--
+1.7.1
+
diff --git a/patches/for_next/0147-OMAP2-sdrc-fix-compile-break-on-OMAP4-only-config-on.patch b/patches/for_next/0147-OMAP2-sdrc-fix-compile-break-on-OMAP4-only-config-on.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e20c61aebf3cd882a306524a0d831a9439f00d91
--- /dev/null
+++ b/patches/for_next/0147-OMAP2-sdrc-fix-compile-break-on-OMAP4-only-config-on.patch
@@ -0,0 +1,47 @@
+From fa428c7db2b8d1b7b0cc1f5304f2fdf5459bbda1 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 17:38:25 -0700
+Subject: [PATCH 147/254] OMAP2+: sdrc: fix compile break on OMAP4-only config on current omap-for-linus
+
+On non-OMAP2 and non-OMAP3 kernel configs, turn omap2_sdrc_init() into
+a no-op. Otherwise, compilation breaks on an OMAP4-only config with
+the current omap-for-linus branch:
+
+arch/arm/mach-omap2/built-in.o: In function `omap2_init_common_devices':
+../mach-omap2/io.c:421: undefined reference to `omap2_sdrc_init'
+
+Thanks to Sergei Shtylyov <sshtylyov@mvista.com> for suggesting the use
+of a empty static inline function rather than a macro.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Sergei Shtylyov <sshtylyov@mvista.com>
+[tony@atomide.com: updated not to use __init for inline omap2_sdrc_init]
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/sdrc.h | 8 +++++++-
+ 1 files changed, 7 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
+index efd87c8..925b12b 100644
+--- a/arch/arm/plat-omap/include/plat/sdrc.h
++++ b/arch/arm/plat-omap/include/plat/sdrc.h
+@@ -124,8 +124,14 @@ struct omap_sdrc_params {
+ u32 mr;
+ };
+
+-void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
++#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
++void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+ struct omap_sdrc_params *sdrc_cs1);
++#else
++static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
++ struct omap_sdrc_params *sdrc_cs1) {};
++#endif
++
+ int omap2_sdrc_get_params(unsigned long r,
+ struct omap_sdrc_params **sdrc_cs0,
+ struct omap_sdrc_params **sdrc_cs1);
+--
+1.7.1
+
diff --git a/patches/for_next/0148-omap-omap3evm-add-support-for-the-WL12xx-WLAN-module.patch b/patches/for_next/0148-omap-omap3evm-add-support-for-the-WL12xx-WLAN-module.patch
new file mode 100644
index 0000000000000000000000000000000000000000..dba8cf20de272fff014086259e8d01598def41a6
--- /dev/null
+++ b/patches/for_next/0148-omap-omap3evm-add-support-for-the-WL12xx-WLAN-module.patch
@@ -0,0 +1,106 @@
+From 3ea234e98a7cc069471b7e2edd6c8f0042844b3c Mon Sep 17 00:00:00 2001
+From: Eyal Reizer <eyalr@ti.com>
+Date: Sun, 27 Feb 2011 10:45:18 +0000
+Subject: [PATCH 148/254] omap: omap3evm: add support for the WL12xx WLAN module to the omap3evm
+
+This patch is again current omap-for-linus branch
+
+Adds platform initialization for working with the WLAN module
+attached to the omap3evm.
+The patch includes MMC2 initialization, SDIO and control pins
+muxing and platform device registration.
+
+Signed-off-by: Eyal Reizer <eyalr@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c | 32 ++++++++++++++++++++++----------
+ 1 files changed, 22 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 3d9b58a..c0ad17b 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -411,7 +411,7 @@ static struct omap2_hsmmc_info mmc[] = {
+ #ifdef CONFIG_WL12XX_PLATFORM_DATA
+ {
+ .name = "wl1271",
+- .mmc = 2,
++ .mmc = 2,
+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+ .gpio_wp = -EINVAL,
+ .gpio_cd = -EINVAL,
+@@ -603,10 +603,8 @@ static struct regulator_init_data omap3evm_vio = {
+ #define OMAP3EVM_WLAN_PMENA_GPIO (150)
+ #define OMAP3EVM_WLAN_IRQ_GPIO (149)
+
+-static struct regulator_consumer_supply omap3evm_vmmc2_supply = {
+- .supply = "vmmc",
+- .dev_name = "mmci-omap-hs.1",
+-};
++static struct regulator_consumer_supply omap3evm_vmmc2_supply =
++ REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+
+ /* VMMC2 for driving the WL12xx module */
+ static struct regulator_init_data omap3evm_vmmc2 = {
+@@ -627,7 +625,7 @@ static struct fixed_voltage_config omap3evm_vwlan = {
+ .init_data = &omap3evm_vmmc2,
+ };
+
+-static struct platform_device omap3evm_vwlan_device = {
++static struct platform_device omap3evm_wlan_regulator = {
+ .name = "reg-fixed-voltage",
+ .id = 1,
+ .dev = {
+@@ -637,8 +635,7 @@ static struct platform_device omap3evm_vwlan_device = {
+
+ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
+ .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
+- /* ref clock is 38.4 MHz */
+- .board_ref_clock = 2,
++ .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
+ };
+ #endif
+
+@@ -763,7 +760,7 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = {
+ OMAP_PIN_OFF_NONE),
+ #ifdef CONFIG_WL12XX_PLATFORM_DATA
+ /* WLAN IRQ - GPIO 149 */
+- OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+ /* WLAN POWER ENABLE - GPIO 150 */
+ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+@@ -799,6 +796,21 @@ static struct omap_board_mux omap36x_board_mux[] __initdata = {
+ OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+ OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
++#ifdef CONFIG_WL12XX_PLATFORM_DATA
++ /* WLAN IRQ - GPIO 149 */
++ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
++
++ /* WLAN POWER ENABLE - GPIO 150 */
++ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
++
++ /* MMC2 SDIO pin muxes for WL12xx */
++ OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++ OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
++#endif
+
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
+@@ -872,7 +884,7 @@ static void __init omap3_evm_init(void)
+ /* WL12xx WLAN Init */
+ if (wl12xx_set_platform_data(&omap3evm_wlan_data))
+ pr_err("error setting wl12xx data\n");
+- platform_device_register(&omap3evm_vwlan_device);
++ platform_device_register(&omap3evm_wlan_regulator);
+ #endif
+ }
+
+--
+1.7.1
+
diff --git a/patches/for_next/0149-omap-mmc-split-out-init-for-2420.patch b/patches/for_next/0149-omap-mmc-split-out-init-for-2420.patch
new file mode 100644
index 0000000000000000000000000000000000000000..6ae4ed61b27c2806f680d6861f11ecdc3baab049
--- /dev/null
+++ b/patches/for_next/0149-omap-mmc-split-out-init-for-2420.patch
@@ -0,0 +1,185 @@
+From a3fac14e79f6074ee752c03fbbd3ef0c0a1316c7 Mon Sep 17 00:00:00 2001
+From: Anand Gadiyar <gadiyar@ti.com>
+Date: Tue, 1 Mar 2011 13:12:55 -0800
+Subject: [PATCH 149/254] omap: mmc: split out init for 2420
+
+The MMC controller on the OMAP2420 is different from those
+on the OMAP2430, OMAP3 and OMAP4 families - all of the latter
+are identical. The one on the OMAP2420 is closer to that
+on OMAP1 chips.
+
+Currently, the n8x0 is the only OMAP2420 platform supported
+in mainline which registers the MMC controller. Upcoming
+changes to register the controllers using hwmod data are
+potentially invasive. To reduce the risk, separate out the
+2420 controller registration from the common init function
+and update its only user. Also seperating out mux settings
+for OMAP2420.
+
+Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Madhusudhan Chikkature <madhu.cr@ti.com>
+Cc: Chris Ball <cjb@laptop.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-n8x0.c | 2 +-
+ arch/arm/mach-omap2/devices.c | 88 +++++++++++++++++++++------------
+ arch/arm/plat-omap/include/plat/mmc.h | 4 ++
+ 3 files changed, 61 insertions(+), 33 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
+index b36cbd2..e710cd9 100644
+--- a/arch/arm/mach-omap2/board-n8x0.c
++++ b/arch/arm/mach-omap2/board-n8x0.c
+@@ -536,7 +536,7 @@ static void __init n8x0_mmc_init(void)
+ }
+
+ mmc_data[0] = &mmc1_data;
+- omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC);
++ omap242x_init_mmc(mmc_data);
+ }
+ #else
+
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index d216976..ba45ac6 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -584,11 +584,10 @@ err1:
+ static inline void omap_hsmmc_reset(void) {}
+ #endif
+
+-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
+- defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
++#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+
+-static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
+- int controller_nr)
++static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
++ *mmc_controller)
+ {
+ if ((mmc_controller->slots[0].switch_pin > 0) && \
+ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
+@@ -599,33 +598,61 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
+ omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
+ OMAP_PIN_INPUT_PULLUP);
+
+- if (cpu_is_omap2420() && controller_nr == 0) {
+- omap_mux_init_signal("sdmmc_cmd", 0);
+- omap_mux_init_signal("sdmmc_clki", 0);
+- omap_mux_init_signal("sdmmc_clko", 0);
+- omap_mux_init_signal("sdmmc_dat0", 0);
+- omap_mux_init_signal("sdmmc_dat_dir0", 0);
+- omap_mux_init_signal("sdmmc_cmd_dir", 0);
+- if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
+- omap_mux_init_signal("sdmmc_dat1", 0);
+- omap_mux_init_signal("sdmmc_dat2", 0);
+- omap_mux_init_signal("sdmmc_dat3", 0);
+- omap_mux_init_signal("sdmmc_dat_dir1", 0);
+- omap_mux_init_signal("sdmmc_dat_dir2", 0);
+- omap_mux_init_signal("sdmmc_dat_dir3", 0);
+- }
++ omap_mux_init_signal("sdmmc_cmd", 0);
++ omap_mux_init_signal("sdmmc_clki", 0);
++ omap_mux_init_signal("sdmmc_clko", 0);
++ omap_mux_init_signal("sdmmc_dat0", 0);
++ omap_mux_init_signal("sdmmc_dat_dir0", 0);
++ omap_mux_init_signal("sdmmc_cmd_dir", 0);
++ if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
++ omap_mux_init_signal("sdmmc_dat1", 0);
++ omap_mux_init_signal("sdmmc_dat2", 0);
++ omap_mux_init_signal("sdmmc_dat3", 0);
++ omap_mux_init_signal("sdmmc_dat_dir1", 0);
++ omap_mux_init_signal("sdmmc_dat_dir2", 0);
++ omap_mux_init_signal("sdmmc_dat_dir3", 0);
++ }
+
+- /*
+- * Use internal loop-back in MMC/SDIO Module Input Clock
+- * selection
+- */
+- if (mmc_controller->slots[0].internal_clock) {
+- u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+- v |= (1 << 24);
+- omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
+- }
++ /*
++ * Use internal loop-back in MMC/SDIO Module Input Clock
++ * selection
++ */
++ if (mmc_controller->slots[0].internal_clock) {
++ u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
++ v |= (1 << 24);
++ omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
++ }
++}
++
++void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
++{
++ char *name = "mmci-omap";
++
++ if (!mmc_data[0]) {
++ pr_err("%s fails: Incomplete platform data\n", __func__);
++ return;
+ }
+
++ omap242x_mmc_mux(mmc_data[0]);
++ omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
++ INT_24XX_MMC_IRQ, mmc_data[0]);
++}
++
++#endif
++
++#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
++
++static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
++ int controller_nr)
++{
++ if ((mmc_controller->slots[0].switch_pin > 0) && \
++ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
++ omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
++ OMAP_PIN_INPUT_PULLUP);
++ if ((mmc_controller->slots[0].gpio_wp > 0) && \
++ (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
++ omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
++ OMAP_PIN_INPUT_PULLUP);
+ if (cpu_is_omap34xx()) {
+ if (controller_nr == 0) {
+ omap_mux_init_signal("sdmmc1_clk",
+@@ -742,10 +769,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ continue;
+ }
+
+- if (cpu_is_omap2420()) {
+- size = OMAP2420_MMC_SIZE;
+- name = "mmci-omap";
+- } else if (cpu_is_omap44xx()) {
++ if (cpu_is_omap44xx()) {
+ if (i < 3)
+ irq += OMAP44XX_IRQ_GIC_START;
+ size = OMAP4_HSMMC_SIZE;
+diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
+index f57f36a..e5de5d4 100644
+--- a/arch/arm/plat-omap/include/plat/mmc.h
++++ b/arch/arm/plat-omap/include/plat/mmc.h
+@@ -159,6 +159,7 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
+ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+ void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers);
++void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
+ void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers);
+ int omap_mmc_add(const char *name, int id, unsigned long base,
+@@ -169,6 +170,9 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers)
+ {
+ }
++static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
++{
++}
+ static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers)
+ {
+--
+1.7.1
+
diff --git a/patches/for_next/0150-OMAP2430-hwmod-data-Add-HSMMC.patch b/patches/for_next/0150-OMAP2430-hwmod-data-Add-HSMMC.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a79746bb40f93173a2ddc94014756a1d5af2b946
--- /dev/null
+++ b/patches/for_next/0150-OMAP2430-hwmod-data-Add-HSMMC.patch
@@ -0,0 +1,207 @@
+From 02a2ac87012184c0bbf3c7092041b46ec717dfec Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Tue, 1 Mar 2011 13:12:55 -0800
+Subject: [PATCH 150/254] OMAP2430: hwmod data: Add HSMMC
+
+Update the omap2430 hwmod data with the HSMMC info.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
+Signed-off-by: Rajendra Nayak <rnayak@ti.com
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 148 ++++++++++++++++++++++++++++
+ 1 files changed, 148 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index c841678..a0f67c6 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -61,6 +61,8 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod;
+ static struct omap_hwmod omap2430_mcspi1_hwmod;
+ static struct omap_hwmod omap2430_mcspi2_hwmod;
+ static struct omap_hwmod omap2430_mcspi3_hwmod;
++static struct omap_hwmod omap2430_mmc1_hwmod;
++static struct omap_hwmod omap2430_mmc2_hwmod;
+
+ /* L3 -> L4_CORE interface */
+ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
+@@ -257,6 +259,42 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
+ &omap2430_l4_core__usbhsotg,
+ };
+
++/* L4 CORE -> MMC1 interface */
++static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
++ {
++ .pa_start = 0x4809c000,
++ .pa_end = 0x4809c1ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mmc1_hwmod,
++ .clk = "mmchs1_ick",
++ .addr = omap2430_mmc1_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
++/* L4 CORE -> MMC2 interface */
++static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
++ {
++ .pa_start = 0x480b4000,
++ .pa_end = 0x480b41ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
++ .master = &omap2430_l4_core_hwmod,
++ .slave = &omap2430_mmc2_hwmod,
++ .addr = omap2430_mmc2_addr_space,
++ .clk = "mmchs2_ick",
++ .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++};
++
+ /* Slave interfaces on the L4_CORE interconnect */
+ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
+ &omap2430_l3_main__l4_core,
+@@ -265,6 +303,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
+ /* Master interfaces on the L4_CORE interconnect */
+ static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
+ &omap2430_l4_core__l4_wkup,
++ &omap2430_l4_core__mmc1,
++ &omap2430_l4_core__mmc2,
+ };
+
+ /* L4 CORE */
+@@ -2509,6 +2549,112 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ };
+
++/* MMC/SD/SDIO common */
++
++static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
++ .rev_offs = 0x1fc,
++ .sysc_offs = 0x10,
++ .syss_offs = 0x14,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap2430_mmc_class = {
++ .name = "mmc",
++ .sysc = &omap2430_mmc_sysc,
++};
++
++/* MMC/SD/SDIO1 */
++
++static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
++ { .irq = 83 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
++ { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
++};
++
++static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
++ { .role = "dbck", .clk = "mmchsdb1_fck" },
++};
++
++static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
++ &omap2430_l4_core__mmc1,
++};
++
++static struct omap_hwmod omap2430_mmc1_hwmod = {
++ .name = "mmc1",
++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
++ .mpu_irqs = omap2430_mmc1_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
++ .sdma_reqs = omap2430_mmc1_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
++ .opt_clks = omap2430_mmc1_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
++ .main_clk = "mmchs1_fck",
++ .prcm = {
++ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 2,
++ .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
++ .idlest_reg_id = 2,
++ .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
++ },
++ },
++ .slaves = omap2430_mmc1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
++ .class = &omap2430_mmc_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
++/* MMC/SD/SDIO2 */
++
++static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
++ { .irq = 86 },
++};
++
++static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
++ { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
++};
++
++static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
++ { .role = "dbck", .clk = "mmchsdb2_fck" },
++};
++
++static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
++ &omap2430_l4_core__mmc2,
++};
++
++static struct omap_hwmod omap2430_mmc2_hwmod = {
++ .name = "mmc2",
++ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
++ .mpu_irqs = omap2430_mmc2_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
++ .sdma_reqs = omap2430_mmc2_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
++ .opt_clks = omap2430_mmc2_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
++ .main_clk = "mmchs2_fck",
++ .prcm = {
++ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 2,
++ .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
++ .idlest_reg_id = 2,
++ .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
++ },
++ },
++ .slaves = omap2430_mmc2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
++ .class = &omap2430_mmc_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
++};
++
+ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ &omap2430_l3_main_hwmod,
+ &omap2430_l4_core_hwmod,
+@@ -2541,6 +2687,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+ /* i2c class */
+ &omap2430_i2c1_hwmod,
+ &omap2430_i2c2_hwmod,
++ &omap2430_mmc1_hwmod,
++ &omap2430_mmc2_hwmod,
+
+ /* gpio class */
+ &omap2430_gpio1_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0151-OMAP3-hwmod-data-Add-HSMMC.patch b/patches/for_next/0151-OMAP3-hwmod-data-Add-HSMMC.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2158d4622ae034c291d8dd7a842098596d4cef17
--- /dev/null
+++ b/patches/for_next/0151-OMAP3-hwmod-data-Add-HSMMC.patch
@@ -0,0 +1,369 @@
+From 380220d1b150449494cb3816c3e303214a03246b Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Tue, 1 Mar 2011 13:12:56 -0800
+Subject: [PATCH 151/254] OMAP3: hwmod data: Add HSMMC
+
+Update the omap3 hwmod data with the HSMMC info.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 296 +++++++++++++++++++++++++++-
+ arch/arm/mach-omap2/prcm-common.h | 4 +
+ 2 files changed, 299 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 9cd116b..1726a1a 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -70,7 +70,10 @@ static struct omap_hwmod omap34xx_mcspi1;
+ static struct omap_hwmod omap34xx_mcspi2;
+ static struct omap_hwmod omap34xx_mcspi3;
+ static struct omap_hwmod omap34xx_mcspi4;
+-
++static struct omap_hwmod omap3xxx_mmc1_hwmod;
++static struct omap_hwmod omap3xxx_mmc2_hwmod;
++static struct omap_hwmod omap3xxx_mmc3_hwmod;
++static struct omap_hwmod am35xx_usbhsotg_hwmod;
+
+ static struct omap_hwmod omap3xxx_dma_system_hwmod;
+
+@@ -168,6 +171,63 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
++/* L4 CORE -> MMC1 interface */
++static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
++ {
++ .pa_start = 0x4809c000,
++ .pa_end = 0x4809c1ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_mmc1_hwmod,
++ .clk = "mmchs1_ick",
++ .addr = omap3xxx_mmc1_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++ .flags = OMAP_FIREWALL_L4
++};
++
++/* L4 CORE -> MMC2 interface */
++static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
++ {
++ .pa_start = 0x480b4000,
++ .pa_end = 0x480b41ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_mmc2_hwmod,
++ .clk = "mmchs2_ick",
++ .addr = omap3xxx_mmc2_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++ .flags = OMAP_FIREWALL_L4
++};
++
++/* L4 CORE -> MMC3 interface */
++static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
++ {
++ .pa_start = 0x480ad000,
++ .pa_end = 0x480ad1ff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
++static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
++ .master = &omap3xxx_l4_core_hwmod,
++ .slave = &omap3xxx_mmc3_hwmod,
++ .clk = "mmchs3_ick",
++ .addr = omap3xxx_mmc3_addr_space,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
++ .user = OCP_USER_MPU | OCP_USER_SDMA,
++ .flags = OMAP_FIREWALL_L4
++};
++
+ /* L4 CORE -> UART1 interface */
+ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+ {
+@@ -3270,11 +3330,245 @@ static struct omap_hwmod omap34xx_mcspi4 = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ };
+
++/*
++ * usbhsotg
++ */
++static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
++ .rev_offs = 0x0400,
++ .sysc_offs = 0x0404,
++ .syss_offs = 0x0408,
++ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
++ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class usbotg_class = {
++ .name = "usbotg",
++ .sysc = &omap3xxx_usbhsotg_sysc,
++};
++/* usb_otg_hs */
++static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
++
++ { .name = "mc", .irq = 92 },
++ { .name = "dma", .irq = 93 },
++};
++
++static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
++ .name = "usb_otg_hs",
++ .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
++ .main_clk = "hsotgusb_ick",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
++ .module_offs = CORE_MOD,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
++ .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
++ },
++ },
++ .masters = omap3xxx_usbhsotg_masters,
++ .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
++ .slaves = omap3xxx_usbhsotg_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
++ .class = &usbotg_class,
++
++ /*
++ * Erratum ID: i479 idle_req / idle_ack mechanism potentially
++ * broken when autoidle is enabled
++ * workaround is to disable the autoidle bit at module level.
++ */
++ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
++ | HWMOD_SWSUP_MSTANDBY,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
++};
++
++/* usb_otg_hs */
++static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
++
++ { .name = "mc", .irq = 71 },
++};
++
++static struct omap_hwmod_class am35xx_usbotg_class = {
++ .name = "am35xx_usbotg",
++ .sysc = NULL,
++};
++
++static struct omap_hwmod am35xx_usbhsotg_hwmod = {
++ .name = "am35x_otg_hs",
++ .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
++ .main_clk = NULL,
++ .prcm = {
++ .omap2 = {
++ },
++ },
++ .masters = am35xx_usbhsotg_masters,
++ .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
++ .slaves = am35xx_usbhsotg_slaves,
++ .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
++ .class = &am35xx_usbotg_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
++};
++
++/* MMC/SD/SDIO common */
++
++static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
++ .rev_offs = 0x1fc,
++ .sysc_offs = 0x10,
++ .syss_offs = 0x14,
++ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
++ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
++ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
++ .sysc_fields = &omap_hwmod_sysc_type1,
++};
++
++static struct omap_hwmod_class omap34xx_mmc_class = {
++ .name = "mmc",
++ .sysc = &omap34xx_mmc_sysc,
++};
++
++/* MMC/SD/SDIO1 */
++
++static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
++ { .irq = 83, },
++};
++
++static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 61, },
++ { .name = "rx", .dma_req = 62, },
++};
++
++static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
++ { .role = "dbck", .clk = "omap_32k_fck", },
++};
++
++static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
++ &omap3xxx_l4_core__mmc1,
++};
++
++static struct omap_hwmod omap3xxx_mmc1_hwmod = {
++ .name = "mmc1",
++ .mpu_irqs = omap34xx_mmc1_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
++ .sdma_reqs = omap34xx_mmc1_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
++ .opt_clks = omap34xx_mmc1_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
++ .main_clk = "mmchs1_fck",
++ .prcm = {
++ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MMC1_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mmc1_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
++ .class = &omap34xx_mmc_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++/* MMC/SD/SDIO2 */
++
++static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
++ { .irq = INT_24XX_MMC2_IRQ, },
++};
++
++static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 47, },
++ { .name = "rx", .dma_req = 48, },
++};
++
++static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
++ { .role = "dbck", .clk = "omap_32k_fck", },
++};
++
++static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
++ &omap3xxx_l4_core__mmc2,
++};
++
++static struct omap_hwmod omap3xxx_mmc2_hwmod = {
++ .name = "mmc2",
++ .mpu_irqs = omap34xx_mmc2_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
++ .sdma_reqs = omap34xx_mmc2_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
++ .opt_clks = omap34xx_mmc2_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
++ .main_clk = "mmchs2_fck",
++ .prcm = {
++ .omap2 = {
++ .module_offs = CORE_MOD,
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MMC2_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mmc2_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
++ .class = &omap34xx_mmc_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
++/* MMC/SD/SDIO3 */
++
++static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
++ { .irq = 94, },
++};
++
++static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
++ { .name = "tx", .dma_req = 77, },
++ { .name = "rx", .dma_req = 78, },
++};
++
++static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
++ { .role = "dbck", .clk = "omap_32k_fck", },
++};
++
++static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
++ &omap3xxx_l4_core__mmc3,
++};
++
++static struct omap_hwmod omap3xxx_mmc3_hwmod = {
++ .name = "mmc3",
++ .mpu_irqs = omap34xx_mmc3_mpu_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
++ .sdma_reqs = omap34xx_mmc3_sdma_reqs,
++ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
++ .opt_clks = omap34xx_mmc3_opt_clks,
++ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
++ .main_clk = "mmchs3_fck",
++ .prcm = {
++ .omap2 = {
++ .prcm_reg_id = 1,
++ .module_bit = OMAP3430_EN_MMC3_SHIFT,
++ .idlest_reg_id = 1,
++ .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
++ },
++ },
++ .slaves = omap3xxx_mmc3_slaves,
++ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
++ .class = &omap34xx_mmc_class,
++ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++};
++
+ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
+ &omap3xxx_l3_main_hwmod,
+ &omap3xxx_l4_core_hwmod,
+ &omap3xxx_l4_per_hwmod,
+ &omap3xxx_l4_wkup_hwmod,
++ &omap3xxx_mmc1_hwmod,
++ &omap3xxx_mmc2_hwmod,
++ &omap3xxx_mmc3_hwmod,
+ &omap3xxx_mpu_hwmod,
+ &omap3xxx_iva_hwmod,
+
+diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
+index d4af21d..0363dcb 100644
+--- a/arch/arm/mach-omap2/prcm-common.h
++++ b/arch/arm/mach-omap2/prcm-common.h
+@@ -195,6 +195,8 @@
+ #define OMAP3430_AUTOIDLE_MASK (1 << 0)
+
+ /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
++#define OMAP3430_EN_MMC3_MASK (1 << 30)
++#define OMAP3430_EN_MMC3_SHIFT 30
+ #define OMAP3430_EN_MMC2_MASK (1 << 25)
+ #define OMAP3430_EN_MMC2_SHIFT 25
+ #define OMAP3430_EN_MMC1_MASK (1 << 24)
+@@ -235,6 +237,8 @@
+ #define OMAP3430_EN_HSOTGUSB_SHIFT 4
+
+ /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
++#define OMAP3430_ST_MMC3_SHIFT 30
++#define OMAP3430_ST_MMC3_MASK (1 << 30)
+ #define OMAP3430_ST_MMC2_SHIFT 25
+ #define OMAP3430_ST_MMC2_MASK (1 << 25)
+ #define OMAP3430_ST_MMC1_SHIFT 24
+--
+1.7.1
+
diff --git a/patches/for_next/0152-OMAP4-hwmod-data-enable-HSMMC.patch b/patches/for_next/0152-OMAP4-hwmod-data-enable-HSMMC.patch
new file mode 100644
index 0000000000000000000000000000000000000000..49d4d1ef06ec48f2ad672b01c2488cc267718de2
--- /dev/null
+++ b/patches/for_next/0152-OMAP4-hwmod-data-enable-HSMMC.patch
@@ -0,0 +1,39 @@
+From 05a40955f0a9efb151e676a6b2f3fb5fe40d7292 Mon Sep 17 00:00:00 2001
+From: Anand Gadiyar <gadiyar@ti.com>
+Date: Tue, 1 Mar 2011 13:12:56 -0800
+Subject: [PATCH 152/254] OMAP4: hwmod data: enable HSMMC
+
+Enabling hsmmc hwmod for OMAP4
+
+Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Acked-by: Benoit Cousson<b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 10 +++++-----
+ 1 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index f6a4484..2c6537e 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -5085,11 +5085,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+ &omap44xx_mcspi4_hwmod,
+
+ /* mmc class */
+-/* &omap44xx_mmc1_hwmod, */
+-/* &omap44xx_mmc2_hwmod, */
+-/* &omap44xx_mmc3_hwmod, */
+-/* &omap44xx_mmc4_hwmod, */
+-/* &omap44xx_mmc5_hwmod, */
++ &omap44xx_mmc1_hwmod,
++ &omap44xx_mmc2_hwmod,
++ &omap44xx_mmc3_hwmod,
++ &omap44xx_mmc4_hwmod,
++ &omap44xx_mmc5_hwmod,
+
+ /* mpu class */
+ &omap44xx_mpu_hwmod,
+--
+1.7.1
+
diff --git a/patches/for_next/0153-OMAP-hwmod-data-Add-dev_attr-and-use-in-the-host-dri.patch b/patches/for_next/0153-OMAP-hwmod-data-Add-dev_attr-and-use-in-the-host-dri.patch
new file mode 100644
index 0000000000000000000000000000000000000000..55c889aee2619c86bc1b1316b10ea9a4d0103e57
--- /dev/null
+++ b/patches/for_next/0153-OMAP-hwmod-data-Add-dev_attr-and-use-in-the-host-dri.patch
@@ -0,0 +1,154 @@
+From b399860936ec7779e694201a068487977e4eb558 Mon Sep 17 00:00:00 2001
+From: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Date: Tue, 1 Mar 2011 13:12:56 -0800
+Subject: [PATCH 153/254] OMAP: hwmod data: Add dev_attr and use in the host driver
+
+Add a device attribute to hwmod data of omap2430, omap3, omap4.
+Currently the device attribute holds information regarding dual volt MMC card
+support by the controller which will be later passed to the host driver via
+platform data.
+
+Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Acked-by: Benoit Cousson<b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 6 ++++++
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 6 ++++++
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 9 ++++++++-
+ arch/arm/plat-omap/include/plat/mmc.h | 9 +++++++++
+ 4 files changed, 29 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index a0f67c6..abb3574 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -21,6 +21,7 @@
+ #include <plat/mcbsp.h>
+ #include <plat/mcspi.h>
+ #include <plat/dmtimer.h>
++#include <plat/mmc.h>
+ #include <plat/l3_2xxx.h>
+
+ #include "omap_hwmod_common_data.h"
+@@ -2586,6 +2587,10 @@ static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
+ &omap2430_l4_core__mmc1,
+ };
+
++static struct omap_mmc_dev_attr mmc1_dev_attr = {
++ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
++};
++
+ static struct omap_hwmod omap2430_mmc1_hwmod = {
+ .name = "mmc1",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+@@ -2605,6 +2610,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
+ .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
+ },
+ },
++ .dev_attr = &mmc1_dev_attr,
+ .slaves = omap2430_mmc1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
+ .class = &omap2430_mmc_class,
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 1726a1a..05c8305 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -22,6 +22,7 @@
+ #include <plat/l4_3xxx.h>
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
++#include <plat/mmc.h>
+ #include <plat/smartreflex.h>
+ #include <plat/mcbsp.h>
+ #include <plat/mcspi.h>
+@@ -3452,6 +3453,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
+ &omap3xxx_l4_core__mmc1,
+ };
+
++static struct omap_mmc_dev_attr mmc1_dev_attr = {
++ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
++};
++
+ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+ .name = "mmc1",
+ .mpu_irqs = omap34xx_mmc1_mpu_irqs,
+@@ -3470,6 +3475,7 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+ .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
+ },
+ },
++ .dev_attr = &mmc1_dev_attr,
+ .slaves = omap3xxx_mmc1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
+ .class = &omap34xx_mmc_class,
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 2c6537e..1b38ed1 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -25,7 +25,7 @@
+ #include <plat/gpio.h>
+ #include <plat/dma.h>
+ #include <plat/mcspi.h>
+-#include <plat/mcbsp.h>
++#include <plat/mmc.h>
+
+ #include "omap_hwmod_common_data.h"
+
+@@ -3391,6 +3391,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
+ };
+
+ /* mmc1 */
++
+ static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
+ { .irq = 83 + OMAP44XX_IRQ_GIC_START },
+ };
+@@ -3428,6 +3429,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
+ &omap44xx_l4_per__mmc1,
+ };
+
++/* mmc1 dev_attr */
++static struct omap_mmc_dev_attr mmc1_dev_attr = {
++ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
++};
++
+ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .name = "mmc1",
+ .class = &omap44xx_mmc_hwmod_class,
+@@ -3441,6 +3447,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
+ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+ },
+ },
++ .dev_attr = &mmc1_dev_attr,
+ .slaves = omap44xx_mmc1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
+ .masters = omap44xx_mmc1_masters,
+diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
+index e5de5d4..a7afab0 100644
+--- a/arch/arm/plat-omap/include/plat/mmc.h
++++ b/arch/arm/plat-omap/include/plat/mmc.h
+@@ -43,6 +43,12 @@
+
+ #define OMAP_MMC_MAX_SLOTS 2
+
++#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1)
++
++struct omap_mmc_dev_attr {
++ u8 flags;
++};
++
+ struct omap_mmc_platform_data {
+ /* back-link to device */
+ struct device *dev;
+@@ -71,6 +77,9 @@ struct omap_mmc_platform_data {
+
+ u64 dma_mask;
+
++ /* Integrating attributes from the omap_hwmod layer */
++ u8 controller_flags;
++
+ /* Register offset deviation */
+ u16 reg_offset;
+
+--
+1.7.1
+
diff --git a/patches/for_next/0154-OMAP-hsmmc-Move-mux-configuration-to-hsmmc.c.patch b/patches/for_next/0154-OMAP-hsmmc-Move-mux-configuration-to-hsmmc.c.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a7bbc3e221051f68410f4892079b78b26f62e200
--- /dev/null
+++ b/patches/for_next/0154-OMAP-hsmmc-Move-mux-configuration-to-hsmmc.c.patch
@@ -0,0 +1,232 @@
+From 9c8b9d7e2c6b4dbfbcb19a301e9fdc1e2694f9f4 Mon Sep 17 00:00:00 2001
+From: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Date: Mon, 28 Feb 2011 20:48:03 +0530
+Subject: [PATCH 154/254] OMAP: hsmmc: Move mux configuration to hsmmc.c
+
+Moving the definition of mux setting API from devices.c to hsmmc.c
+and renaming it from "omap2_mmc_mux" to "omap_hsmmc_mux".
+Also calling "omap_hsmmc_mux" from omap2_hsmmc_init.
+
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Cc: Chris Ball <cjb@laptop.org
+Cc: Tony Lindgren <tony@atomide.com
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/devices.c | 83 ----------------------------------------
+ arch/arm/mach-omap2/hsmmc.c | 84 +++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 84 insertions(+), 83 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index ba45ac6..eb87879 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -642,87 +642,6 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
+
+ #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+
+-static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
+- int controller_nr)
+-{
+- if ((mmc_controller->slots[0].switch_pin > 0) && \
+- (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
+- omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
+- OMAP_PIN_INPUT_PULLUP);
+- if ((mmc_controller->slots[0].gpio_wp > 0) && \
+- (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
+- omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
+- OMAP_PIN_INPUT_PULLUP);
+- if (cpu_is_omap34xx()) {
+- if (controller_nr == 0) {
+- omap_mux_init_signal("sdmmc1_clk",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc1_cmd",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc1_dat0",
+- OMAP_PIN_INPUT_PULLUP);
+- if (mmc_controller->slots[0].caps &
+- (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
+- omap_mux_init_signal("sdmmc1_dat1",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc1_dat2",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc1_dat3",
+- OMAP_PIN_INPUT_PULLUP);
+- }
+- if (mmc_controller->slots[0].caps &
+- MMC_CAP_8_BIT_DATA) {
+- omap_mux_init_signal("sdmmc1_dat4",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc1_dat5",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc1_dat6",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc1_dat7",
+- OMAP_PIN_INPUT_PULLUP);
+- }
+- }
+- if (controller_nr == 1) {
+- /* MMC2 */
+- omap_mux_init_signal("sdmmc2_clk",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc2_cmd",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc2_dat0",
+- OMAP_PIN_INPUT_PULLUP);
+-
+- /*
+- * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
+- * in the board-*.c files
+- */
+- if (mmc_controller->slots[0].caps &
+- (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
+- omap_mux_init_signal("sdmmc2_dat1",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc2_dat2",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc2_dat3",
+- OMAP_PIN_INPUT_PULLUP);
+- }
+- if (mmc_controller->slots[0].caps &
+- MMC_CAP_8_BIT_DATA) {
+- omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
+- OMAP_PIN_INPUT_PULLUP);
+- omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
+- OMAP_PIN_INPUT_PULLUP);
+- }
+- }
+-
+- /*
+- * For MMC3 the pins need to be muxed in the board-*.c files
+- */
+- }
+-}
+-
+ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers)
+ {
+@@ -736,8 +655,6 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ if (!mmc_data[i])
+ continue;
+
+- omap2_mmc_mux(mmc_data[i], i);
+-
+ switch (i) {
+ case 0:
+ base = OMAP2_MMC1_BASE;
+diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
+index 5496bc7..1348ac3 100644
+--- a/arch/arm/mach-omap2/hsmmc.c
++++ b/arch/arm/mach-omap2/hsmmc.c
+@@ -16,7 +16,9 @@
+ #include <mach/hardware.h>
+ #include <plat/mmc.h>
+ #include <plat/omap-pm.h>
++#include <plat/mux.h>
+
++#include "mux.h"
+ #include "hsmmc.h"
+ #include "control.h"
+
+@@ -204,6 +206,87 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
+ return 0;
+ }
+
++static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
++ int controller_nr)
++{
++ if ((mmc_controller->slots[0].switch_pin > 0) && \
++ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
++ omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
++ OMAP_PIN_INPUT_PULLUP);
++ if ((mmc_controller->slots[0].gpio_wp > 0) && \
++ (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
++ omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
++ OMAP_PIN_INPUT_PULLUP);
++ if (cpu_is_omap34xx()) {
++ if (controller_nr == 0) {
++ omap_mux_init_signal("sdmmc1_clk",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc1_cmd",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc1_dat0",
++ OMAP_PIN_INPUT_PULLUP);
++ if (mmc_controller->slots[0].caps &
++ (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
++ omap_mux_init_signal("sdmmc1_dat1",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc1_dat2",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc1_dat3",
++ OMAP_PIN_INPUT_PULLUP);
++ }
++ if (mmc_controller->slots[0].caps &
++ MMC_CAP_8_BIT_DATA) {
++ omap_mux_init_signal("sdmmc1_dat4",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc1_dat5",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc1_dat6",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc1_dat7",
++ OMAP_PIN_INPUT_PULLUP);
++ }
++ }
++ if (controller_nr == 1) {
++ /* MMC2 */
++ omap_mux_init_signal("sdmmc2_clk",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc2_cmd",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc2_dat0",
++ OMAP_PIN_INPUT_PULLUP);
++
++ /*
++ * For 8 wire configurations, Lines DAT4, 5, 6 and 7
++ * need to be muxed in the board-*.c files
++ */
++ if (mmc_controller->slots[0].caps &
++ (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
++ omap_mux_init_signal("sdmmc2_dat1",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc2_dat2",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc2_dat3",
++ OMAP_PIN_INPUT_PULLUP);
++ }
++ if (mmc_controller->slots[0].caps &
++ MMC_CAP_8_BIT_DATA) {
++ omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
++ OMAP_PIN_INPUT_PULLUP);
++ omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
++ OMAP_PIN_INPUT_PULLUP);
++ }
++ }
++
++ /*
++ * For MMC3 the pins need to be muxed in the board-*.c files
++ */
++ }
++}
++
+ static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
+
+ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+@@ -361,6 +444,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+ continue;
+ }
+ hsmmc_data[c->mmc - 1] = mmc;
++ omap_hsmmc_mux(hsmmc_data[c->mmc - 1], (c->mmc - 1));
+ }
+
+ omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
+--
+1.7.1
+
diff --git a/patches/for_next/0155-OMAP-adapt-hsmmc-to-hwmod-framework.patch b/patches/for_next/0155-OMAP-adapt-hsmmc-to-hwmod-framework.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2e1b09b212ff3bb0de940fd4f9bdeaf4f5b8509c
--- /dev/null
+++ b/patches/for_next/0155-OMAP-adapt-hsmmc-to-hwmod-framework.patch
@@ -0,0 +1,681 @@
+From 9a87f5339d4a5d4782f002609931f0ca82b35f99 Mon Sep 17 00:00:00 2001
+From: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Date: Mon, 28 Feb 2011 20:48:04 +0530
+Subject: [PATCH 155/254] OMAP: adapt hsmmc to hwmod framework
+
+OMAP2420 platform consists of mmc block as in omap1 and not the
+hsmmc block as present in omap2430, omap3, omap4 platforms.
+Removing all base address macro defines except keeping one for OMAP2420 and
+adapting only hsmmc device registration and driver to hwmod framework.
+
+Changes involves:
+1) Remove controller reset in devices.c which is taken care of
+ by hwmod framework.
+2) Using omap-device layer to register device and utilizing data from
+ hwmod data file for base address, dma channel number, Irq_number,
+ device attribute.
+3) Update the driver to use dev_attr to find whether controller
+ supports dual volt cards
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Reviewed-by: Balaji T K <balajitk@ti.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+CC: Kevin Hilman <khilman@deeprootsystems.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/devices.c | 168 ----------------
+ arch/arm/mach-omap2/hsmmc.c | 346 +++++++++++++++++++--------------
+ arch/arm/plat-omap/include/plat/mmc.h | 20 +--
+ drivers/mmc/host/omap_hsmmc.c | 4 +-
+ 4 files changed, 200 insertions(+), 338 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index eb87879..2cb720b 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -478,112 +478,6 @@ static inline void omap_init_aes(void) { }
+
+ /*-------------------------------------------------------------------------*/
+
+-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+-
+-#define MMCHS_SYSCONFIG 0x0010
+-#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
+-#define MMCHS_SYSSTATUS 0x0014
+-#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
+-
+-static struct platform_device dummy_pdev = {
+- .dev = {
+- .bus = &platform_bus_type,
+- },
+-};
+-
+-/**
+- * omap_hsmmc_reset() - Full reset of each HS-MMC controller
+- *
+- * Ensure that each MMC controller is fully reset. Controllers
+- * left in an unknown state (by bootloader) may prevent retention
+- * or OFF-mode. This is especially important in cases where the
+- * MMC driver is not enabled, _or_ built as a module.
+- *
+- * In order for reset to work, interface, functional and debounce
+- * clocks must be enabled. The debounce clock comes from func_32k_clk
+- * and is not under SW control, so we only enable i- and f-clocks.
+- **/
+-static void __init omap_hsmmc_reset(void)
+-{
+- u32 i, nr_controllers;
+- struct clk *iclk, *fclk;
+-
+- if (cpu_is_omap242x())
+- return;
+-
+- nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
+- (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
+-
+- for (i = 0; i < nr_controllers; i++) {
+- u32 v, base = 0;
+- struct device *dev = &dummy_pdev.dev;
+-
+- switch (i) {
+- case 0:
+- base = OMAP2_MMC1_BASE;
+- break;
+- case 1:
+- base = OMAP2_MMC2_BASE;
+- break;
+- case 2:
+- base = OMAP3_MMC3_BASE;
+- break;
+- case 3:
+- if (!cpu_is_omap44xx())
+- return;
+- base = OMAP4_MMC4_BASE;
+- break;
+- case 4:
+- if (!cpu_is_omap44xx())
+- return;
+- base = OMAP4_MMC5_BASE;
+- break;
+- }
+-
+- if (cpu_is_omap44xx())
+- base += OMAP4_MMC_REG_OFFSET;
+-
+- dummy_pdev.id = i;
+- dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
+- iclk = clk_get(dev, "ick");
+- if (IS_ERR(iclk))
+- goto err1;
+- if (clk_enable(iclk))
+- goto err2;
+-
+- fclk = clk_get(dev, "fck");
+- if (IS_ERR(fclk))
+- goto err3;
+- if (clk_enable(fclk))
+- goto err4;
+-
+- omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
+- v = omap_readl(base + MMCHS_SYSSTATUS);
+- while (!(omap_readl(base + MMCHS_SYSSTATUS) &
+- MMCHS_SYSSTATUS_RESETDONE))
+- cpu_relax();
+-
+- clk_disable(fclk);
+- clk_put(fclk);
+- clk_disable(iclk);
+- clk_put(iclk);
+- }
+- return;
+-
+-err4:
+- clk_put(fclk);
+-err3:
+- clk_disable(iclk);
+-err2:
+- clk_put(iclk);
+-err1:
+- printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
+- "cannot reset.\n", __func__, i);
+-}
+-#else
+-static inline void omap_hsmmc_reset(void) {}
+-#endif
+-
+ #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+
+ static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
+@@ -640,67 +534,6 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
+
+ #endif
+
+-#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+-
+-void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+- int nr_controllers)
+-{
+- int i;
+- char *name;
+-
+- for (i = 0; i < nr_controllers; i++) {
+- unsigned long base, size;
+- unsigned int irq = 0;
+-
+- if (!mmc_data[i])
+- continue;
+-
+- switch (i) {
+- case 0:
+- base = OMAP2_MMC1_BASE;
+- irq = INT_24XX_MMC_IRQ;
+- break;
+- case 1:
+- base = OMAP2_MMC2_BASE;
+- irq = INT_24XX_MMC2_IRQ;
+- break;
+- case 2:
+- if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
+- return;
+- base = OMAP3_MMC3_BASE;
+- irq = INT_34XX_MMC3_IRQ;
+- break;
+- case 3:
+- if (!cpu_is_omap44xx())
+- return;
+- base = OMAP4_MMC4_BASE;
+- irq = OMAP44XX_IRQ_MMC4;
+- break;
+- case 4:
+- if (!cpu_is_omap44xx())
+- return;
+- base = OMAP4_MMC5_BASE;
+- irq = OMAP44XX_IRQ_MMC5;
+- break;
+- default:
+- continue;
+- }
+-
+- if (cpu_is_omap44xx()) {
+- if (i < 3)
+- irq += OMAP44XX_IRQ_GIC_START;
+- size = OMAP4_HSMMC_SIZE;
+- name = "mmci-omap-hs";
+- } else {
+- size = OMAP3_HSMMC_SIZE;
+- name = "mmci-omap-hs";
+- }
+- omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
+- };
+-}
+-
+-#endif
+-
+ /*-------------------------------------------------------------------------*/
+
+ #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
+@@ -770,7 +603,6 @@ static int __init omap2_init_devices(void)
+ * please keep these calls, and their implementations above,
+ * in alphabetical order so they're easier to sort through.
+ */
+- omap_hsmmc_reset();
+ omap_init_audio();
+ omap_init_camera();
+ omap_init_mbox();
+diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
+index 1348ac3..d492bc4 100644
+--- a/arch/arm/mach-omap2/hsmmc.c
++++ b/arch/arm/mach-omap2/hsmmc.c
+@@ -17,6 +17,7 @@
+ #include <plat/mmc.h>
+ #include <plat/omap-pm.h>
+ #include <plat/mux.h>
++#include <plat/omap_device.h>
+
+ #include "mux.h"
+ #include "hsmmc.h"
+@@ -30,10 +31,6 @@ static u16 control_mmc1;
+
+ #define HSMMC_NAME_LEN 9
+
+-static struct hsmmc_controller {
+- char name[HSMMC_NAME_LEN + 1];
+-} hsmmc[OMAP34XX_NR_MMC];
+-
+ #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
+
+ static int hsmmc_get_context_loss(struct device *dev)
+@@ -287,13 +284,203 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
+ }
+ }
+
+-static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
++static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
++ struct omap_mmc_platform_data *mmc)
++{
++ char *hc_name;
++
++ hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
++ if (!hc_name) {
++ pr_err("Cannot allocate memory for controller slot name\n");
++ kfree(hc_name);
++ return -ENOMEM;
++ }
++
++ if (c->name)
++ strncpy(hc_name, c->name, HSMMC_NAME_LEN);
++ else
++ snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
++ c->mmc, 1);
++ mmc->slots[0].name = hc_name;
++ mmc->nr_slots = 1;
++ mmc->slots[0].caps = c->caps;
++ mmc->slots[0].internal_clock = !c->ext_clock;
++ mmc->dma_mask = 0xffffffff;
++ if (cpu_is_omap44xx())
++ mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
++ else
++ mmc->reg_offset = 0;
++
++ mmc->get_context_loss_count = hsmmc_get_context_loss;
++
++ mmc->slots[0].switch_pin = c->gpio_cd;
++ mmc->slots[0].gpio_wp = c->gpio_wp;
++
++ mmc->slots[0].remux = c->remux;
++ mmc->slots[0].init_card = c->init_card;
++
++ if (c->cover_only)
++ mmc->slots[0].cover = 1;
++
++ if (c->nonremovable)
++ mmc->slots[0].nonremovable = 1;
++
++ if (c->power_saving)
++ mmc->slots[0].power_saving = 1;
++
++ if (c->no_off)
++ mmc->slots[0].no_off = 1;
++
++ if (c->vcc_aux_disable_is_sleep)
++ mmc->slots[0].vcc_aux_disable_is_sleep = 1;
++
++ /*
++ * NOTE: MMC slots should have a Vcc regulator set up.
++ * This may be from a TWL4030-family chip, another
++ * controllable regulator, or a fixed supply.
++ *
++ * temporary HACK: ocr_mask instead of fixed supply
++ */
++ mmc->slots[0].ocr_mask = c->ocr_mask;
++
++ if (cpu_is_omap3517() || cpu_is_omap3505())
++ mmc->slots[0].set_power = nop_mmc_set_power;
++ else
++ mmc->slots[0].features |= HSMMC_HAS_PBIAS;
++
++ if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
++ mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
++
++ switch (c->mmc) {
++ case 1:
++ if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
++ /* on-chip level shifting via PBIAS0/PBIAS1 */
++ if (cpu_is_omap44xx()) {
++ mmc->slots[0].before_set_reg =
++ omap4_hsmmc1_before_set_reg;
++ mmc->slots[0].after_set_reg =
++ omap4_hsmmc1_after_set_reg;
++ } else {
++ mmc->slots[0].before_set_reg =
++ omap_hsmmc1_before_set_reg;
++ mmc->slots[0].after_set_reg =
++ omap_hsmmc1_after_set_reg;
++ }
++ }
++
++ /* OMAP3630 HSMMC1 supports only 4-bit */
++ if (cpu_is_omap3630() &&
++ (c->caps & MMC_CAP_8_BIT_DATA)) {
++ c->caps &= ~MMC_CAP_8_BIT_DATA;
++ c->caps |= MMC_CAP_4_BIT_DATA;
++ mmc->slots[0].caps = c->caps;
++ }
++ break;
++ case 2:
++ if (c->ext_clock)
++ c->transceiver = 1;
++ if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
++ c->caps &= ~MMC_CAP_8_BIT_DATA;
++ c->caps |= MMC_CAP_4_BIT_DATA;
++ }
++ /* FALLTHROUGH */
++ case 3:
++ if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
++ /* off-chip level shifting, or none */
++ mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
++ mmc->slots[0].after_set_reg = NULL;
++ }
++ break;
++ case 4:
++ case 5:
++ mmc->slots[0].before_set_reg = NULL;
++ mmc->slots[0].after_set_reg = NULL;
++ break;
++ default:
++ pr_err("MMC%d configuration not supported!\n", c->mmc);
++ kfree(hc_name);
++ return -ENODEV;
++ }
++ return 0;
++}
++
++static struct omap_device_pm_latency omap_hsmmc_latency[] = {
++ [0] = {
++ .deactivate_func = omap_device_idle_hwmods,
++ .activate_func = omap_device_enable_hwmods,
++ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
++ },
++ /*
++ * XXX There should also be an entry here to power off/on the
++ * MMC regulators/PBIAS cells, etc.
++ */
++};
++
++#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
++
++void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
++{
++ struct omap_hwmod *oh;
++ struct omap_device *od;
++ struct omap_device_pm_latency *ohl;
++ char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
++ struct omap_mmc_platform_data *mmc_data;
++ struct omap_mmc_dev_attr *mmc_dev_attr;
++ char *name;
++ int l;
++ int ohl_cnt = 0;
++
++ mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
++ if (!mmc_data) {
++ pr_err("Cannot allocate memory for mmc device!\n");
++ goto done;
++ }
++
++ if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
++ pr_err("%s fails!\n", __func__);
++ goto done;
++ }
++ omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
++
++ name = "mmci-omap-hs";
++ ohl = omap_hsmmc_latency;
++ ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
++
++ l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
++ "mmc%d", ctrl_nr);
++ WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
++ "String buffer overflow in MMC%d device setup\n", ctrl_nr);
++ oh = omap_hwmod_lookup(oh_name);
++ if (!oh) {
++ pr_err("Could not look up %s\n", oh_name);
++ kfree(mmc_data->slots[0].name);
++ goto done;
++ }
++
++ if (oh->dev_attr != NULL) {
++ mmc_dev_attr = oh->dev_attr;
++ mmc_data->controller_flags = mmc_dev_attr->flags;
++ }
++
++ od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
++ sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
++ if (IS_ERR(od)) {
++ WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
++ kfree(mmc_data->slots[0].name);
++ goto done;
++ }
++ /*
++ * return device handle to board setup code
++ * required to populate for regulator framework structure
++ */
++ hsmmcinfo->dev = &od->pdev.dev;
++
++done:
++ kfree(mmc_data);
++}
+
+ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+ {
+- struct omap2_hsmmc_info *c;
+- int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
+- int i;
+ u32 reg;
+
+ if (!cpu_is_omap44xx()) {
+@@ -319,148 +506,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+ omap4_ctrl_pad_writel(reg, control_mmc1);
+ }
+
+- for (c = controllers; c->mmc; c++) {
+- struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
+- struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
+-
+- if (!c->mmc || c->mmc > nr_hsmmc) {
+- pr_debug("MMC%d: no such controller\n", c->mmc);
+- continue;
+- }
+- if (mmc) {
+- pr_debug("MMC%d: already configured\n", c->mmc);
+- continue;
+- }
+-
+- mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
+- GFP_KERNEL);
+- if (!mmc) {
+- pr_err("Cannot allocate memory for mmc device!\n");
+- goto done;
+- }
+-
+- if (c->name)
+- strncpy(hc->name, c->name, HSMMC_NAME_LEN);
+- else
+- snprintf(hc->name, ARRAY_SIZE(hc->name),
+- "mmc%islot%i", c->mmc, 1);
+- mmc->slots[0].name = hc->name;
+- mmc->nr_slots = 1;
+- mmc->slots[0].caps = c->caps;
+- mmc->slots[0].internal_clock = !c->ext_clock;
+- mmc->dma_mask = 0xffffffff;
+- if (cpu_is_omap44xx())
+- mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
+- else
+- mmc->reg_offset = 0;
+-
+- mmc->get_context_loss_count = hsmmc_get_context_loss;
+-
+- mmc->slots[0].switch_pin = c->gpio_cd;
+- mmc->slots[0].gpio_wp = c->gpio_wp;
+-
+- mmc->slots[0].remux = c->remux;
+- mmc->slots[0].init_card = c->init_card;
+-
+- if (c->cover_only)
+- mmc->slots[0].cover = 1;
+-
+- if (c->nonremovable)
+- mmc->slots[0].nonremovable = 1;
+-
+- if (c->power_saving)
+- mmc->slots[0].power_saving = 1;
+-
+- if (c->no_off)
+- mmc->slots[0].no_off = 1;
+-
+- if (c->vcc_aux_disable_is_sleep)
+- mmc->slots[0].vcc_aux_disable_is_sleep = 1;
+-
+- /* NOTE: MMC slots should have a Vcc regulator set up.
+- * This may be from a TWL4030-family chip, another
+- * controllable regulator, or a fixed supply.
+- *
+- * temporary HACK: ocr_mask instead of fixed supply
+- */
+- mmc->slots[0].ocr_mask = c->ocr_mask;
+-
+- if (cpu_is_omap3517() || cpu_is_omap3505())
+- mmc->slots[0].set_power = nop_mmc_set_power;
+- else
+- mmc->slots[0].features |= HSMMC_HAS_PBIAS;
+-
+- if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
+- mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+-
+- switch (c->mmc) {
+- case 1:
+- if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+- /* on-chip level shifting via PBIAS0/PBIAS1 */
+- if (cpu_is_omap44xx()) {
+- mmc->slots[0].before_set_reg =
+- omap4_hsmmc1_before_set_reg;
+- mmc->slots[0].after_set_reg =
+- omap4_hsmmc1_after_set_reg;
+- } else {
+- mmc->slots[0].before_set_reg =
+- omap_hsmmc1_before_set_reg;
+- mmc->slots[0].after_set_reg =
+- omap_hsmmc1_after_set_reg;
+- }
+- }
+-
+- /* Omap3630 HSMMC1 supports only 4-bit */
+- if (cpu_is_omap3630() &&
+- (c->caps & MMC_CAP_8_BIT_DATA)) {
+- c->caps &= ~MMC_CAP_8_BIT_DATA;
+- c->caps |= MMC_CAP_4_BIT_DATA;
+- mmc->slots[0].caps = c->caps;
+- }
+- break;
+- case 2:
+- if (c->ext_clock)
+- c->transceiver = 1;
+- if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
+- c->caps &= ~MMC_CAP_8_BIT_DATA;
+- c->caps |= MMC_CAP_4_BIT_DATA;
+- }
+- /* FALLTHROUGH */
+- case 3:
+- if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+- /* off-chip level shifting, or none */
+- mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
+- mmc->slots[0].after_set_reg = NULL;
+- }
+- break;
+- case 4:
+- case 5:
+- mmc->slots[0].before_set_reg = NULL;
+- mmc->slots[0].after_set_reg = NULL;
+- break;
+- default:
+- pr_err("MMC%d configuration not supported!\n", c->mmc);
+- kfree(mmc);
+- continue;
+- }
+- hsmmc_data[c->mmc - 1] = mmc;
+- omap_hsmmc_mux(hsmmc_data[c->mmc - 1], (c->mmc - 1));
+- }
+-
+- omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
+-
+- /* pass the device nodes back to board setup code */
+- for (c = controllers; c->mmc; c++) {
+- struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
++ for (; controllers->mmc; controllers++)
++ omap_init_hsmmc(controllers, controllers->mmc);
+
+- if (!c->mmc || c->mmc > nr_hsmmc)
+- continue;
+- c->dev = mmc->dev;
+- }
+-
+-done:
+- for (i = 0; i < nr_hsmmc; i++)
+- kfree(hsmmc_data[i]);
+ }
+
+ #endif
+diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
+index a7afab0..f38fef9 100644
+--- a/arch/arm/plat-omap/include/plat/mmc.h
++++ b/arch/arm/plat-omap/include/plat/mmc.h
+@@ -24,22 +24,10 @@
+ #define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
+
+ #define OMAP24XX_NR_MMC 2
+-#define OMAP34XX_NR_MMC 3
+-#define OMAP44XX_NR_MMC 5
+ #define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
+-#define OMAP3_HSMMC_SIZE 0x200
+-#define OMAP4_HSMMC_SIZE 0x1000
+ #define OMAP2_MMC1_BASE 0x4809c000
+-#define OMAP2_MMC2_BASE 0x480b4000
+-#define OMAP3_MMC3_BASE 0x480ad000
+-#define OMAP4_MMC4_BASE 0x480d1000
+-#define OMAP4_MMC5_BASE 0x480d5000
++
+ #define OMAP4_MMC_REG_OFFSET 0x100
+-#define HSMMC5 (1 << 4)
+-#define HSMMC4 (1 << 3)
+-#define HSMMC3 (1 << 2)
+-#define HSMMC2 (1 << 1)
+-#define HSMMC1 (1 << 0)
+
+ #define OMAP_MMC_MAX_SLOTS 2
+
+@@ -169,8 +157,6 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
+ void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ int nr_controllers);
+ void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
+-void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+- int nr_controllers);
+ int omap_mmc_add(const char *name, int id, unsigned long base,
+ unsigned long size, unsigned int irq,
+ struct omap_mmc_platform_data *data);
+@@ -182,10 +168,6 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
+ static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
+ {
+ }
+-static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+- int nr_controllers)
+-{
+-}
+ static inline int omap_mmc_add(const char *name, int id, unsigned long base,
+ unsigned long size, unsigned int irq,
+ struct omap_mmc_platform_data *data)
+diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
+index 8c42573..d0bd2b4 100644
+--- a/drivers/mmc/host/omap_hsmmc.c
++++ b/drivers/mmc/host/omap_hsmmc.c
+@@ -1571,7 +1571,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ break;
+ }
+
+- if (host->id == OMAP_MMC1_DEVID) {
++ if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
+ /* Only MMC1 can interface at 3V without some flavor
+ * of external transceiver; but they all handle 1.8V.
+ */
+@@ -1663,7 +1663,7 @@ static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
+ u32 hctl, capa, value;
+
+ /* Only MMC1 supports 3.0V */
+- if (host->id == OMAP_MMC1_DEVID) {
++ if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
+ hctl = SDVS30;
+ capa = VS30 | VS18;
+ } else {
+--
+1.7.1
+
diff --git a/patches/for_next/0156-OMAP-hsmmc-Rename-the-device-and-driver.patch b/patches/for_next/0156-OMAP-hsmmc-Rename-the-device-and-driver.patch
new file mode 100644
index 0000000000000000000000000000000000000000..8c2132878c5ec641647f28207dd6243ba4d61c5f
--- /dev/null
+++ b/patches/for_next/0156-OMAP-hsmmc-Rename-the-device-and-driver.patch
@@ -0,0 +1,423 @@
+From 0af5efd8ba8fef24ffe6234bbdc76f0e274c9705 Mon Sep 17 00:00:00 2001
+From: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Date: Mon, 28 Feb 2011 20:48:05 +0530
+Subject: [PATCH 156/254] OMAP: hsmmc: Rename the device and driver
+
+Modifying the device & driver name from "mmci-omap-hs" to
+"omap_hsmmc".
+
+Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Acked-by: Benoit Cousson<b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-2430sdp.c | 2 +-
+ arch/arm/mach-omap2/board-3430sdp.c | 6 +++---
+ arch/arm/mach-omap2/board-4430sdp.c | 14 +++++++-------
+ arch/arm/mach-omap2/board-devkit8000.c | 2 +-
+ arch/arm/mach-omap2/board-igep0020.c | 6 +++---
+ arch/arm/mach-omap2/board-igep0030.c | 6 +++---
+ arch/arm/mach-omap2/board-omap3evm.c | 2 +-
+ arch/arm/mach-omap2/board-omap3pandora.c | 6 +++---
+ arch/arm/mach-omap2/board-omap4panda.c | 4 ++--
+ arch/arm/mach-omap2/board-rm680.c | 2 +-
+ arch/arm/mach-omap2/board-rx51-peripherals.c | 8 ++++----
+ arch/arm/mach-omap2/board-zoom-peripherals.c | 2 +-
+ arch/arm/mach-omap2/clock2430_data.c | 12 ++++++------
+ arch/arm/mach-omap2/clock3xxx_data.c | 12 ++++++------
+ arch/arm/mach-omap2/clock44xx_data.c | 20 ++++++++++----------
+ arch/arm/mach-omap2/hsmmc.c | 2 +-
+ drivers/mmc/host/omap_hsmmc.c | 2 +-
+ 17 files changed, 54 insertions(+), 54 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
+index 59de1dc..1fa6bb8 100644
+--- a/arch/arm/mach-omap2/board-2430sdp.c
++++ b/arch/arm/mach-omap2/board-2430sdp.c
+@@ -147,7 +147,7 @@ static void __init omap_2430sdp_init_early(void)
+ }
+
+ static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"),
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+ /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 719b441..4e9e081 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -407,15 +407,15 @@ static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
+ };
+
+ static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"),
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+ };
+
+ static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
+- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.0"),
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+ };
+
+ static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+ };
+
+ /*
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index 81ef979..85805d4 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -347,11 +347,6 @@ static struct twl4030_usb_data omap4_usbphy_data = {
+
+ static struct omap2_hsmmc_info mmc[] = {
+ {
+- .mmc = 1,
+- .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+- .gpio_wp = -EINVAL,
+- },
+- {
+ .mmc = 2,
+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+ .gpio_cd = -EINVAL,
+@@ -359,19 +354,24 @@ static struct omap2_hsmmc_info mmc[] = {
+ .nonremovable = true,
+ .ocr_mask = MMC_VDD_29_30,
+ },
++ {
++ .mmc = 1,
++ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
++ .gpio_wp = -EINVAL,
++ },
+ {} /* Terminator */
+ };
+
+ static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
+ {
+ .supply = "vmmc",
+- .dev_name = "mmci-omap-hs.1",
++ .dev_name = "omap_hsmmc.1",
+ },
+ };
+ static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
+ {
+ .supply = "vmmc",
+- .dev_name = "mmci-omap-hs.0",
++ .dev_name = "omap_hsmmc.0",
+ },
+ };
+
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index 54abdd0..c9170f4 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -140,7 +140,7 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
+ }
+
+ static struct regulator_consumer_supply devkit8000_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+
+
+ /* ads7846 on SPI */
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index 54e6318..1877c28 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -250,7 +250,7 @@ static inline void __init igep2_init_smsc911x(void) { }
+ #endif
+
+ static struct regulator_consumer_supply igep2_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+
+ /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+ static struct regulator_init_data igep2_vmmc1 = {
+@@ -268,7 +268,7 @@ static struct regulator_init_data igep2_vmmc1 = {
+ };
+
+ static struct regulator_consumer_supply igep2_vio_supply =
+- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
+
+ static struct regulator_init_data igep2_vio = {
+ .constraints = {
+@@ -286,7 +286,7 @@ static struct regulator_init_data igep2_vio = {
+ };
+
+ static struct regulator_consumer_supply igep2_vmmc2_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+ static struct regulator_init_data igep2_vmmc2 = {
+ .constraints = {
+diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
+index d75028e..4273d06 100644
+--- a/arch/arm/mach-omap2/board-igep0030.c
++++ b/arch/arm/mach-omap2/board-igep0030.c
+@@ -142,7 +142,7 @@ static void __init igep3_flash_init(void) {}
+ #endif
+
+ static struct regulator_consumer_supply igep3_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+
+ /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+ static struct regulator_init_data igep3_vmmc1 = {
+@@ -160,7 +160,7 @@ static struct regulator_init_data igep3_vmmc1 = {
+ };
+
+ static struct regulator_consumer_supply igep3_vio_supply =
+- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
+
+ static struct regulator_init_data igep3_vio = {
+ .constraints = {
+@@ -178,7 +178,7 @@ static struct regulator_init_data igep3_vio = {
+ };
+
+ static struct regulator_consumer_supply igep3_vmmc2_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+ static struct regulator_init_data igep3_vmmc2 = {
+ .constraints = {
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index c0ad17b..7d6e2b2 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -604,7 +604,7 @@ static struct regulator_init_data omap3evm_vio = {
+ #define OMAP3EVM_WLAN_IRQ_GPIO (149)
+
+ static struct regulator_consumer_supply omap3evm_vmmc2_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+ /* VMMC2 for driving the WL12xx module */
+ static struct regulator_init_data omap3evm_vmmc2 = {
+diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
+index 17ef547..ed13869 100644
+--- a/arch/arm/mach-omap2/board-omap3pandora.c
++++ b/arch/arm/mach-omap2/board-omap3pandora.c
+@@ -333,13 +333,13 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
+ };
+
+ static struct regulator_consumer_supply pandora_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+
+ static struct regulator_consumer_supply pandora_vmmc2_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+ static struct regulator_consumer_supply pandora_vmmc3_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
+
+ static struct regulator_consumer_supply pandora_vdda_dac_supply =
+ REGULATOR_SUPPLY("vdda_dac", "omapdss");
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index 3dd241b..12bf09a 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -180,13 +180,13 @@ static struct omap2_hsmmc_info mmc[] = {
+ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
+ {
+ .supply = "vmmc",
+- .dev_name = "mmci-omap-hs.0",
++ .dev_name = "omap_hsmmc.0",
+ },
+ };
+
+ static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
+ .supply = "vmmc",
+- .dev_name = "mmci-omap-hs.4",
++ .dev_name = "omap_hsmmc.4",
+ };
+
+ static struct regulator_init_data panda_vmmc5 = {
+diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
+index bdebcb7..2af8b05 100644
+--- a/arch/arm/mach-omap2/board-rm680.c
++++ b/arch/arm/mach-omap2/board-rm680.c
+@@ -33,7 +33,7 @@
+ #include "sdram-nokia.h"
+
+ static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+ };
+
+ /* Fixed regulator for internal eMMC */
+diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
+index d0998f8..f4881a7 100644
+--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
++++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
+@@ -335,13 +335,13 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
+ };
+
+ static struct regulator_consumer_supply rx51_vmmc1_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+
+ static struct regulator_consumer_supply rx51_vaux3_supply =
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+ static struct regulator_consumer_supply rx51_vsim_supply =
+- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
++ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
+
+ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
+ /* tlv320aic3x analog supplies */
+@@ -352,7 +352,7 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
+ /* tpa6130a2 */
+ REGULATOR_SUPPLY("Vdd", "2-0060"),
+ /* Keep vmmc as last item. It is not iterated for newer boards */
+- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
++ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+ };
+
+ static struct regulator_consumer_supply rx51_vio_supplies[] = {
+diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
+index e0e040f..7a098a4 100644
+--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
++++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
+@@ -118,7 +118,7 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = {
+
+ static struct regulator_consumer_supply zoom_vmmc3_supply = {
+ .supply = "vmmc",
+- .dev_name = "mmci-omap-hs.2",
++ .dev_name = "omap_hsmmc.2",
+ };
+
+ /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index a1298e5..7d68495 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -1984,15 +1984,15 @@ static struct omap_clk omap2430_clks[] = {
+ CLK(NULL, "pka_ick", &pka_ick, CK_243X),
+ CLK(NULL, "usb_fck", &usb_fck, CK_243X),
+ CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
+- CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
+- CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
+- CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
+- CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
++ CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
++ CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X),
++ CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
++ CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X),
+ CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
+ CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
+ CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
+- CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
+- CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
++ CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
++ CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
+ };
+
+ /*
+diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
+index 65b79e6..f18c5e2 100644
+--- a/arch/arm/mach-omap2/clock3xxx_data.c
++++ b/arch/arm/mach-omap2/clock3xxx_data.c
+@@ -3290,10 +3290,10 @@ static struct omap_clk omap3xxx_clks[] = {
+ CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
+ CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
+ CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
+- CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+- CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
++ CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
++ CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
+ CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
+- CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
++ CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
+ CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
+ CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
+ CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
+@@ -3323,13 +3323,13 @@ static struct omap_clk omap3xxx_clks[] = {
+ CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
+ CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+- CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
++ CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
+ CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
+ CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
+ CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
+- CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
+- CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
++ CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
++ CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
+ CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
+ CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
+ CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
+diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
+index 2795342..f1fedb7 100644
+--- a/arch/arm/mach-omap2/clock44xx_data.c
++++ b/arch/arm/mach-omap2/clock44xx_data.c
+@@ -3166,11 +3166,11 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
+ CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
+ CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
+- CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X),
+- CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X),
+- CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
+- CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
+- CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
++ CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X),
++ CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X),
++ CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X),
++ CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X),
++ CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X),
+ CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
+ CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
+ CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
+@@ -3253,11 +3253,11 @@ static struct omap_clk omap44xx_clks[] = {
+ CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
+ CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
+ CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
+- CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
+- CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
+- CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
+- CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
+- CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
++ CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
++ CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
++ CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
++ CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
++ CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
+ CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
+ CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
+ CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
+diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
+index d492bc4..137e1a5 100644
+--- a/arch/arm/mach-omap2/hsmmc.c
++++ b/arch/arm/mach-omap2/hsmmc.c
+@@ -442,7 +442,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
+ }
+ omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
+
+- name = "mmci-omap-hs";
++ name = "omap_hsmmc";
+ ohl = omap_hsmmc_latency;
+ ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
+
+diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
+index d0bd2b4..191332b 100644
+--- a/drivers/mmc/host/omap_hsmmc.c
++++ b/drivers/mmc/host/omap_hsmmc.c
+@@ -118,7 +118,7 @@
+
+ #define MMC_TIMEOUT_MS 20
+ #define OMAP_MMC_MASTER_CLOCK 96000000
+-#define DRIVER_NAME "mmci-omap-hs"
++#define DRIVER_NAME "omap_hsmmc"
+
+ /* Timeouts for entering power saving states on inactivity, msec */
+ #define OMAP_MMC_DISABLED_TIMEOUT 100
+--
+1.7.1
+
diff --git a/patches/for_next/0157-omap4-clockdomain-Fix-the-CPUx-domain-name.patch b/patches/for_next/0157-omap4-clockdomain-Fix-the-CPUx-domain-name.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e9be74f34987f00a7a9d00c2764bf8a26b0ab534
--- /dev/null
+++ b/patches/for_next/0157-omap4-clockdomain-Fix-the-CPUx-domain-name.patch
@@ -0,0 +1,65 @@
+From 34f1cac4de6b40f8aece9471bd09428859462590 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Tue, 8 Feb 2011 14:30:31 -0700
+Subject: [PATCH 157/254] omap4: clockdomain: Fix the CPUx domain name
+
+The register naming convention for clock domain control inside
+power domain instance is:
+OMAPXXXX_<partition>_<power_domain>_<clock_domain>_CDOFFS
+
+Both CPU0 and CPU1 use MPU as clock domain name instead of CPU0
+and CPU1.
+
+Change the name to stick to the convention.
+The autogen scripts are updated accordingly.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomains44xx_data.c | 4 ++--
+ arch/arm/mach-omap2/prcm_mpu44xx.h | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
+index f53258a..a607ec1 100644
+--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
++++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
+@@ -514,7 +514,7 @@ static struct clockdomain mpu0_44xx_clkdm = {
+ .pwrdm = { .name = "cpu0_pwrdm" },
+ .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
+ .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
+- .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS,
++ .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+@@ -524,7 +524,7 @@ static struct clockdomain mpu1_44xx_clkdm = {
+ .pwrdm = { .name = "cpu1_pwrdm" },
+ .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
+ .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
+- .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS,
++ .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ };
+diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
+index 3300ff6..d22d1b4 100644
+--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
++++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
+@@ -38,8 +38,8 @@
+ #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
+
+ /* PRCM_MPU clockdomain register offsets (from instance start) */
+-#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0018
+-#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0018
++#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
++#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
+
+
+ /*
+--
+1.7.1
+
diff --git a/patches/for_next/0158-omap4-powerdomain-Use-intended-PWRSTS_-flags-instead.patch b/patches/for_next/0158-omap4-powerdomain-Use-intended-PWRSTS_-flags-instead.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9811b8132218adb2c458ff50a4c89f5466dd1a73
--- /dev/null
+++ b/patches/for_next/0158-omap4-powerdomain-Use-intended-PWRSTS_-flags-instead.patch
@@ -0,0 +1,42 @@
+From ca472ec3aa5c48bb0f6b57c3fb34828cecd200e8 Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Fri, 25 Feb 2011 15:21:17 -0700
+Subject: [PATCH 158/254] omap4: powerdomain: Use intended PWRSTS_* flags instead of values
+
+IVAHD and ABE power domain logic state is populated using directly
+value instead of the capability flags.
+
+Fix the same.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+[paul@pwsan.com: updated to apply at a different point on the tree]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/powerdomains44xx_data.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
+index 26d7641..226e01a 100644
+--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
++++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
+@@ -80,7 +80,7 @@ static struct powerdomain abe_44xx_pwrdm = {
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_OFF,
++ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_RET, /* aessmem */
+@@ -227,7 +227,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
+ .prcm_partition = OMAP4430_PRM_PARTITION,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_OFF,
++ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 4,
+ .pwrsts_mem_ret = {
+ [0] = PWRDM_POWER_OFF, /* hwa_mem */
+--
+1.7.1
+
diff --git a/patches/for_next/0159-OMAP2-omap_device-clock-Do-not-expect-an-entry-in-cl.patch b/patches/for_next/0159-OMAP2-omap_device-clock-Do-not-expect-an-entry-in-cl.patch
new file mode 100644
index 0000000000000000000000000000000000000000..df40cca6165ba435df392be5a878d480269605ce
--- /dev/null
+++ b/patches/for_next/0159-OMAP2-omap_device-clock-Do-not-expect-an-entry-in-cl.patch
@@ -0,0 +1,125 @@
+From a8acbc9324822592fa1c9267624f17e11cc119f1 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Fri, 25 Feb 2011 15:40:21 -0700
+Subject: [PATCH 159/254] OMAP2+: omap_device/clock: Do not expect an entry in clkdev for opt_clks
+
+The _add_optional_clock_alias function expects an entry
+already existing in the clkdev table in the form of
+<dev-id=NULL, con-id=role> which might not be the case
+always.
+
+Instead, just check if an entry already exists in clkdev
+in the <dev-id=dev_name, con-id=role> form, else go ahead
+and add one.
+
+Remove any assumption of an entry already existing in clkdev
+table in any form.
+
+Since this means, adding a new entry in clkdev if it does
+not already exist, and not really adding an 'alias',
+also rename the function name
+(s/_add_optional_clock_alias/_add_optional_clock_clkdev)
+to reflect this.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Reported-by: Sumit Semwal <sumit.semwal@ti.com>
+Cc: Sumit Semwal <sumit.semwal@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Partha Basak <p-basak2@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/omap_device.c | 36 ++++++++++++++++++++++++++----------
+ 1 files changed, 26 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
+index 57adb27..9bbda9a 100644
+--- a/arch/arm/plat-omap/omap_device.c
++++ b/arch/arm/plat-omap/omap_device.c
+@@ -83,9 +83,11 @@
+ #include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/clk.h>
++#include <linux/clkdev.h>
+
+ #include <plat/omap_device.h>
+ #include <plat/omap_hwmod.h>
++#include <plat/clock.h>
+
+ /* These parameters are passed to _omap_device_{de,}activate() */
+ #define USE_WAKEUP_LAT 0
+@@ -239,12 +241,12 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
+ }
+
+ /**
+- * _add_optional_clock_alias - Add clock alias for hwmod optional clocks
++ * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
+ * @od: struct omap_device *od
+ *
+ * For every optional clock present per hwmod per omap_device, this function
+- * adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role>
+- * if an entry is already present in it with the form <dev-id=NULL, con-id=role>
++ * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
++ * if it does not exist already.
+ *
+ * The function is called from inside omap_device_build_ss(), after
+ * omap_device_register.
+@@ -254,25 +256,39 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
+ *
+ * No return value.
+ */
+-static void _add_optional_clock_alias(struct omap_device *od,
++static void _add_optional_clock_clkdev(struct omap_device *od,
+ struct omap_hwmod *oh)
+ {
+ int i;
+
+ for (i = 0; i < oh->opt_clks_cnt; i++) {
+ struct omap_hwmod_opt_clk *oc;
+- int r;
++ struct clk *r;
++ struct clk_lookup *l;
+
+ oc = &oh->opt_clks[i];
+
+ if (!oc->_clk)
+ continue;
+
+- r = clk_add_alias(oc->role, dev_name(&od->pdev.dev),
+- (char *)oc->clk, &od->pdev.dev);
+- if (r)
+- pr_err("omap_device: %s: clk_add_alias for %s failed\n",
++ r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
++ if (!IS_ERR(r))
++ continue; /* clkdev entry exists */
++
++ r = omap_clk_get_by_name((char *)oc->clk);
++ if (IS_ERR(r)) {
++ pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
++ dev_name(&od->pdev.dev), oc->clk);
++ continue;
++ }
++
++ l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
++ if (!l) {
++ pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
+ dev_name(&od->pdev.dev), oc->role);
++ return;
++ }
++ clkdev_add(l);
+ }
+ }
+
+@@ -480,7 +496,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+
+ for (i = 0; i < oh_cnt; i++) {
+ hwmods[i]->od = od;
+- _add_optional_clock_alias(od, hwmods[i]);
++ _add_optional_clock_clkdev(od, hwmods[i]);
+ }
+
+ if (ret)
+--
+1.7.1
+
diff --git a/patches/for_next/0160-MMC-omap_hsmmc-enable-interface-clock-before-calling.patch b/patches/for_next/0160-MMC-omap_hsmmc-enable-interface-clock-before-calling.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5590a1bb37ea1721ca880e05cc70e4855bd96100
--- /dev/null
+++ b/patches/for_next/0160-MMC-omap_hsmmc-enable-interface-clock-before-calling.patch
@@ -0,0 +1,49 @@
+From 829c6061598db1cd06d62b609994ad719fe9b48d Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 18:22:08 -0700
+Subject: [PATCH 160/254] MMC: omap_hsmmc: enable interface clock before calling mmc_host_enable()
+
+The code path entered via mmc_host_enable() can include register
+accesses to the HSMMC IP block. For this to work, both the device
+interface clock and functional clock need to be enabled before
+mmc_host_enable() is called. However, omap_hsmmc_probe() calls
+mmc_host_enable() before enabling the device interface clock.
+
+Fix by calling mmc_host_enable() after the device interface clock is
+enabled.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Madhusudhan Chikkature Rajashekar <madhu.cr@ti.com>
+Cc: Adrian Hunter <adrian.hunter@nokia.com>
+Cc: Kishore Kadiyala <kishore.kadiyala@ti.com>
+Cc: Tero Kristo <Tero.Kristo@nokia.com>
+Acked-by: Madhusudhan Chikkature Rajashekar <madhu.cr@ti.com>
+---
+ drivers/mmc/host/omap_hsmmc.c | 6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
+index 191332b..158c0ee 100644
+--- a/drivers/mmc/host/omap_hsmmc.c
++++ b/drivers/mmc/host/omap_hsmmc.c
+@@ -2117,14 +2117,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
+ /* we start off in DISABLED state */
+ host->dpm_state = DISABLED;
+
+- if (mmc_host_enable(host->mmc) != 0) {
++ if (clk_enable(host->iclk) != 0) {
+ clk_put(host->iclk);
+ clk_put(host->fclk);
+ goto err1;
+ }
+
+- if (clk_enable(host->iclk) != 0) {
+- mmc_host_disable(host->mmc);
++ if (mmc_host_enable(host->mmc) != 0) {
++ clk_disable(host->iclk);
+ clk_put(host->iclk);
+ clk_put(host->fclk);
+ goto err1;
+--
+1.7.1
+
diff --git a/patches/for_next/0161-arm-omap-fix-section-mismatch-warning.patch b/patches/for_next/0161-arm-omap-fix-section-mismatch-warning.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3bcd2db58641d59be90dfafc43c3cc599adec1c8
--- /dev/null
+++ b/patches/for_next/0161-arm-omap-fix-section-mismatch-warning.patch
@@ -0,0 +1,34 @@
+From 88a7b674e965ef190f47bc65d88ea39259e99916 Mon Sep 17 00:00:00 2001
+From: Ming Lei <tom.leiming@gmail.com>
+Date: Thu, 3 Mar 2011 06:41:46 +0800
+Subject: [PATCH 161/254] arm: omap: fix section mismatch warning
+
+WARNING: arch/arm/plat-omap/built-in.o(.data+0x6d4): Section mismatch in reference from the variable omap_driver to the function .init.text:omap_cpu_init()
+The variable omap_driver references
+the function __init omap_cpu_init()
+If the reference is valid then annotate the
+variable with __init* or __refdata (see linux/init.h) or name the variable:
+*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,
+
+Signed-off-by: Ming Lei <tom.leiming@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/cpu-omap.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
+index 11c54ec..da4f68d 100644
+--- a/arch/arm/plat-omap/cpu-omap.c
++++ b/arch/arm/plat-omap/cpu-omap.c
+@@ -101,7 +101,7 @@ static int omap_target(struct cpufreq_policy *policy,
+ return ret;
+ }
+
+-static int __init omap_cpu_init(struct cpufreq_policy *policy)
++static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
+ {
+ int result = 0;
+
+--
+1.7.1
+
diff --git a/patches/for_next/0162-ldp-Fix-regulator-mapping-for-ads7846-TS-controller.patch b/patches/for_next/0162-ldp-Fix-regulator-mapping-for-ads7846-TS-controller.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5857f544871f442cd0037eda6b8a7f0da09a00ca
--- /dev/null
+++ b/patches/for_next/0162-ldp-Fix-regulator-mapping-for-ads7846-TS-controller.patch
@@ -0,0 +1,60 @@
+From e3206921b99ccebbbea35c17ff750d9d31f12d21 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <Nayak>
+Date: Thu, 24 Feb 2011 12:56:42 +0000
+Subject: [PATCH 162/254] ldp: Fix regulator mapping for ads7846 TS controller
+
+On the OMAP3430LDP board, the ads7846 touchscreen controller
+is powered by VAUX1 regulator (supplying 3.0v).
+Fix this mapping in the board file, and hence prevent
+the ads7846 driver init to fail with the below error..
+
+ads7846 spi1.0: unable to get regulator: -19
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-ldp.c | 21 +++++++++++++++++++++
+ 1 files changed, 21 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
+index a69e594..e2ba779 100644
+--- a/arch/arm/mach-omap2/board-ldp.c
++++ b/arch/arm/mach-omap2/board-ldp.c
+@@ -327,6 +327,26 @@ static struct regulator_init_data ldp_vmmc1 = {
+ .consumer_supplies = &ldp_vmmc1_supply,
+ };
+
++/* ads7846 on SPI */
++static struct regulator_consumer_supply ldp_vaux1_supplies[] = {
++ REGULATOR_SUPPLY("vcc", "spi1.0"),
++};
++
++/* VAUX1 */
++static struct regulator_init_data ldp_vaux1 = {
++ .constraints = {
++ .min_uV = 3000000,
++ .max_uV = 3000000,
++ .apply_uV = true,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL
++ | REGULATOR_MODE_STANDBY,
++ .valid_ops_mask = REGULATOR_CHANGE_MODE
++ | REGULATOR_CHANGE_STATUS,
++ },
++ .num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies),
++ .consumer_supplies = ldp_vaux1_supplies,
++};
++
+ static struct twl4030_platform_data ldp_twldata = {
+ .irq_base = TWL4030_IRQ_BASE,
+ .irq_end = TWL4030_IRQ_END,
+@@ -335,6 +355,7 @@ static struct twl4030_platform_data ldp_twldata = {
+ .madc = &ldp_madc_data,
+ .usb = &ldp_usb_data,
+ .vmmc1 = &ldp_vmmc1,
++ .vaux1 = &ldp_vaux1,
+ .gpio = &ldp_gpio_data,
+ .keypad = &ldp_kp_twl4030_data,
+ };
+--
+1.7.1
+
diff --git a/patches/for_next/0163-omap-panda-Add-TI-ST-driver-support.patch b/patches/for_next/0163-omap-panda-Add-TI-ST-driver-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2e6b1e892157aa7c70567e31bf3bf2b012d8fb1f
--- /dev/null
+++ b/patches/for_next/0163-omap-panda-Add-TI-ST-driver-support.patch
@@ -0,0 +1,48 @@
+From 9f5ce1dc1a1e3b3c1ebb858f1d1d390fd2d4b66e Mon Sep 17 00:00:00 2001
+From: Guy Eilam <guy@wizery.com>
+Date: Fri, 25 Feb 2011 06:52:35 +0000
+Subject: [PATCH 163/254] omap: panda: Add TI-ST driver support
+
+Added the KIM (Kernel initialization module for the
+Shared Transport driver) device entry in the board file
+
+Only the Blutooth enable GPIO is set for now
+
+Signed-off-by: Guy Eilam <guy@wizery.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap4panda.c | 11 +++++++++++
+ 1 files changed, 11 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index 12bf09a..a94ce07 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -50,6 +50,16 @@
+ #define GPIO_WIFI_PMENA 43
+ #define GPIO_WIFI_IRQ 53
+
++/* wl127x BT, FM, GPS connectivity chip */
++static int wl1271_gpios[] = {46, -1, -1};
++static struct platform_device wl1271_device = {
++ .name = "kim",
++ .id = -1,
++ .dev = {
++ .platform_data = &wl1271_gpios,
++ },
++};
++
+ static struct gpio_led gpio_leds[] = {
+ {
+ .name = "pandaboard::status1",
+@@ -78,6 +88,7 @@ static struct platform_device leds_gpio = {
+
+ static struct platform_device *panda_devices[] __initdata = {
+ &leds_gpio,
++ &wl1271_device,
+ };
+
+ static void __init omap4_panda_init_early(void)
+--
+1.7.1
+
diff --git a/patches/for_next/0164-omap-rx51-Add-support-for-vibra.patch b/patches/for_next/0164-omap-rx51-Add-support-for-vibra.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3f0bd1c94c1274e1c9fdba3367e24c10909aff32
--- /dev/null
+++ b/patches/for_next/0164-omap-rx51-Add-support-for-vibra.patch
@@ -0,0 +1,43 @@
+From c22ac8abe697d4f26d1294a722940af5dcad38b7 Mon Sep 17 00:00:00 2001
+From: Ilkka Koskinen <ilkka.koskinen@nokia.com>
+Date: Fri, 25 Feb 2011 08:46:23 +0000
+Subject: [PATCH 164/254] omap: rx51: Add support for vibra
+
+Add support for vibra
+
+Signed-off-by: Ilkka Koskinen <ilkka.koskinen@nokia.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-rx51-peripherals.c | 9 +++++++++
+ 1 files changed, 9 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
+index f4881a7..5f1900c 100644
+--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
++++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
+@@ -742,6 +742,14 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
+ .resource_config = twl4030_rconfig,
+ };
+
++struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
++ .coexist = 0,
++};
++
++struct twl4030_codec_data rx51_codec_data __initdata = {
++ .audio_mclk = 26000000,
++ .vibra = &rx51_vibra_data,
++};
+
+ static struct twl4030_platform_data rx51_twldata __initdata = {
+ .irq_base = TWL4030_IRQ_BASE,
+@@ -753,6 +761,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
+ .madc = &rx51_madc_data,
+ .usb = &rx51_usb_data,
+ .power = &rx51_t2scripts_data,
++ .codec = &rx51_codec_data,
+
+ .vaux1 = &rx51_vaux1,
+ .vaux2 = &rx51_vaux2,
+--
+1.7.1
+
diff --git a/patches/for_next/0165-omap-Remove-unnecessary-twl4030_codec_audio-settings.patch b/patches/for_next/0165-omap-Remove-unnecessary-twl4030_codec_audio-settings.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b380921fc2532d600b2978988a4900b1261324a2
--- /dev/null
+++ b/patches/for_next/0165-omap-Remove-unnecessary-twl4030_codec_audio-settings.patch
@@ -0,0 +1,179 @@
+From 0cccaff0af21be96c602d4c0175cb4c1241d9e7b Mon Sep 17 00:00:00 2001
+From: Ilkka Koskinen <ilkka.koskinen@nokia.com>
+Date: Wed, 2 Mar 2011 13:24:05 +0000
+Subject: [PATCH 165/254] omap: Remove unnecessary twl4030_codec_audio settings from board files
+
+twl4030_codec_audio and twl4030_codec_vibra_data has unused field.
+In order to remove it, corresponding settings needs to be removed
+from board files.
+
+Signed-off-by: Ilkka Koskinen <ilkka.koskinen@nokia.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 4 +---
+ arch/arm/mach-omap2/board-devkit8000.c | 4 +---
+ arch/arm/mach-omap2/board-igep0020.c | 4 +---
+ arch/arm/mach-omap2/board-omap3beagle.c | 4 +---
+ arch/arm/mach-omap2/board-omap3evm.c | 4 +---
+ arch/arm/mach-omap2/board-omap3pandora.c | 4 +---
+ arch/arm/mach-omap2/board-omap3stalker.c | 4 +---
+ arch/arm/mach-omap2/board-omap3touchbook.c | 4 +---
+ arch/arm/mach-omap2/board-overo.c | 4 +---
+ arch/arm/mach-omap2/board-zoom-peripherals.c | 4 +---
+ 10 files changed, 10 insertions(+), 30 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 4e9e081..85c0b5c 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -557,9 +557,7 @@ static struct regulator_init_data sdp3430_vpll2 = {
+ .consumer_supplies = sdp3430_vpll2_supplies,
+ };
+
+-static struct twl4030_codec_audio_data sdp3430_audio = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data sdp3430_audio;
+
+ static struct twl4030_codec_data sdp3430_codec = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index c9170f4..728f27c 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -342,9 +342,7 @@ static struct twl4030_usb_data devkit8000_usb_data = {
+ .usb_mode = T2_USB_MODE_ULPI,
+ };
+
+-static struct twl4030_codec_audio_data devkit8000_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data devkit8000_audio_data;
+
+ static struct twl4030_codec_data devkit8000_codec_data = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
+index 1877c28..c4b3c1c 100644
+--- a/arch/arm/mach-omap2/board-igep0020.c
++++ b/arch/arm/mach-omap2/board-igep0020.c
+@@ -521,9 +521,7 @@ static void __init igep2_init_early(void)
+ m65kxxxxam_sdrc_params);
+ }
+
+-static struct twl4030_codec_audio_data igep2_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data igep2_audio_data;
+
+ static struct twl4030_codec_data igep2_codec_data = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index a1faea3..b6752ac 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -427,9 +427,7 @@ static struct twl4030_usb_data beagle_usb_data = {
+ .usb_mode = T2_USB_MODE_ULPI,
+ };
+
+-static struct twl4030_codec_audio_data beagle_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data beagle_audio_data;
+
+ static struct twl4030_codec_data beagle_codec_data = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index 7d6e2b2..b65848c 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -534,9 +534,7 @@ static struct twl4030_madc_platform_data omap3evm_madc_data = {
+ .irq_line = 1,
+ };
+
+-static struct twl4030_codec_audio_data omap3evm_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data omap3evm_audio_data;
+
+ static struct twl4030_codec_data omap3evm_codec_data = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
+index ed13869..5386a81 100644
+--- a/arch/arm/mach-omap2/board-omap3pandora.c
++++ b/arch/arm/mach-omap2/board-omap3pandora.c
+@@ -516,9 +516,7 @@ static struct twl4030_usb_data omap3pandora_usb_data = {
+ .usb_mode = T2_USB_MODE_ULPI,
+ };
+
+-static struct twl4030_codec_audio_data omap3pandora_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data omap3pandora_audio_data;
+
+ static struct twl4030_codec_data omap3pandora_codec_data = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
+index fd8b764..15ede8b 100644
+--- a/arch/arm/mach-omap2/board-omap3stalker.c
++++ b/arch/arm/mach-omap2/board-omap3stalker.c
+@@ -431,9 +431,7 @@ static struct twl4030_madc_platform_data omap3stalker_madc_data = {
+ .irq_line = 1,
+ };
+
+-static struct twl4030_codec_audio_data omap3stalker_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data omap3stalker_audio_data;
+
+ static struct twl4030_codec_data omap3stalker_codec_data = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
+index 8e2a7ba..5554f58 100644
+--- a/arch/arm/mach-omap2/board-omap3touchbook.c
++++ b/arch/arm/mach-omap2/board-omap3touchbook.c
+@@ -252,9 +252,7 @@ static struct twl4030_usb_data touchbook_usb_data = {
+ .usb_mode = T2_USB_MODE_ULPI,
+ };
+
+-static struct twl4030_codec_audio_data touchbook_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data touchbook_audio_data;
+
+ static struct twl4030_codec_data touchbook_codec_data = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
+index d480ddb..60f8db3 100644
+--- a/arch/arm/mach-omap2/board-overo.c
++++ b/arch/arm/mach-omap2/board-overo.c
+@@ -358,9 +358,7 @@ static struct regulator_init_data overo_vmmc1 = {
+ .consumer_supplies = &overo_vmmc1_supply,
+ };
+
+-static struct twl4030_codec_audio_data overo_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data overo_audio_data;
+
+ static struct twl4030_codec_data overo_codec_data = {
+ .audio_mclk = 26000000,
+diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
+index 7a098a4..448ab60 100644
+--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
++++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
+@@ -322,9 +322,7 @@ static struct twl4030_madc_platform_data zoom_madc_data = {
+ .irq_line = 1,
+ };
+
+-static struct twl4030_codec_audio_data zoom_audio_data = {
+- .audio_mclk = 26000000,
+-};
++static struct twl4030_codec_audio_data zoom_audio_data;
+
+ static struct twl4030_codec_data zoom_codec_data = {
+ .audio_mclk = 26000000,
+--
+1.7.1
+
diff --git a/patches/for_next/0166-mfd-twl4030_codec-Remove-unused-and-duplicate-audio_.patch b/patches/for_next/0166-mfd-twl4030_codec-Remove-unused-and-duplicate-audio_.patch
new file mode 100644
index 0000000000000000000000000000000000000000..cb70cdecbabedcf98dc33693648fa4989acd518e
--- /dev/null
+++ b/patches/for_next/0166-mfd-twl4030_codec-Remove-unused-and-duplicate-audio_.patch
@@ -0,0 +1,41 @@
+From 4c3489a6baf3e6e89729e9d1724e06f4f78c30bb Mon Sep 17 00:00:00 2001
+From: Ilkka Koskinen <ilkka.koskinen@nokia.com>
+Date: Wed, 2 Mar 2011 13:24:06 +0000
+Subject: [PATCH 166/254] mfd: twl4030_codec: Remove unused and duplicate audio_mclk fields
+
+audio_mclk can be queried from mfd driver. Therefore, it is not
+needed in twl4030_codec_audio_data or in twl4030_codec_vibra_data
+anymore.
+
+Signed-off-by: Ilkka Koskinen <ilkka.koskinen@nokia.com>
+Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
+Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+Acked-by: Samuel Ortiz <sameo@linux.intel.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ include/linux/i2c/twl.h | 2 --
+ 1 files changed, 0 insertions(+), 2 deletions(-)
+
+diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
+index 61b9609..9d88b71 100644
+--- a/include/linux/i2c/twl.h
++++ b/include/linux/i2c/twl.h
+@@ -637,7 +637,6 @@ extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
+ extern int twl4030_remove_script(u8 flags);
+
+ struct twl4030_codec_audio_data {
+- unsigned int audio_mclk; /* not used, will be removed */
+ unsigned int digimic_delay; /* in ms */
+ unsigned int ramp_delay_value;
+ unsigned int offset_cncl_path;
+@@ -648,7 +647,6 @@ struct twl4030_codec_audio_data {
+ };
+
+ struct twl4030_codec_vibra_data {
+- unsigned int audio_mclk;
+ unsigned int coexist;
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0167-Revert-OMAP4-hwmod-data-Prevent-timer1-to-be-reset-a.patch b/patches/for_next/0167-Revert-OMAP4-hwmod-data-Prevent-timer1-to-be-reset-a.patch
new file mode 100644
index 0000000000000000000000000000000000000000..659cfc126134ad60541804ffc249a4876decd17e
--- /dev/null
+++ b/patches/for_next/0167-Revert-OMAP4-hwmod-data-Prevent-timer1-to-be-reset-a.patch
@@ -0,0 +1,35 @@
+From b76c7861157dc77e075bfa7a7d1c90b3dc82afcb Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 4 Mar 2011 16:01:43 +0100
+Subject: [PATCH 167/254] Revert "OMAP4: hwmod data: Prevent timer1 to be reset and idle during init"
+
+The following commit: 38698be:
+OMAP2+: clockevent: set up GPTIMER clockevent hwmod right before timer init
+
+Fixed properly the issue with early init for the timer1
+
+So reverts commit 3b03b58dab847883e6b9a431558c7d8e43fa94c6 that is now
+generated a warning at boot time.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Reviewed-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 -
+ 1 files changed, 0 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index 1b38ed1..ee60325 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -4004,7 +4004,6 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
+ static struct omap_hwmod omap44xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &omap44xx_timer_1ms_hwmod_class,
+- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = omap44xx_timer1_irqs,
+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
+ .main_clk = "timer1_fck",
+--
+1.7.1
+
diff --git a/patches/for_next/0168-OMAP2-3-WKUP-powerdomain-mark-as-being-always-on.patch b/patches/for_next/0168-OMAP2-3-WKUP-powerdomain-mark-as-being-always-on.patch
new file mode 100644
index 0000000000000000000000000000000000000000..ccf371bc04bde7fa335c1880e971843f12bccd45
--- /dev/null
+++ b/patches/for_next/0168-OMAP2-3-WKUP-powerdomain-mark-as-being-always-on.patch
@@ -0,0 +1,37 @@
+From 494ee100a43b635d81cdb0ebad84a9430495fe54 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Mon, 7 Mar 2011 19:28:15 -0700
+Subject: [PATCH 168/254] OMAP2/3: WKUP powerdomain: mark as being always on
+
+Mark the WKUP powerdomain as being always on -- at least, as long as the
+chip has power. This will be used to enable the powerdomain code to
+determine whether a given powerdomain is ever able to power off. While
+here, update the file copyright.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+index 5b4dd97..96cda13 100644
+--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
++++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+@@ -2,7 +2,7 @@
+ * OMAP2/3 common powerdomain definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+- * Copyright (C) 2007-2010 Nokia Corporation
++ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+@@ -76,4 +76,5 @@ struct powerdomain wkup_omap2_pwrdm = {
+ .name = "wkup_pwrdm",
+ .prcm_offs = WKUP_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
++ .pwrsts = PWRSTS_ON,
+ };
+--
+1.7.1
+
diff --git a/patches/for_next/0169-OMAP2-powerdomain-fix-bank-power-state-bitfields.patch b/patches/for_next/0169-OMAP2-powerdomain-fix-bank-power-state-bitfields.patch
new file mode 100644
index 0000000000000000000000000000000000000000..1713481f63fc8db47ea9e2cbc6451dd7552ab76d
--- /dev/null
+++ b/patches/for_next/0169-OMAP2-powerdomain-fix-bank-power-state-bitfields.patch
@@ -0,0 +1,460 @@
+From 1cc79f38c3c1aba201545f43670291c67d567ce2 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Mon, 7 Mar 2011 19:28:15 -0700
+Subject: [PATCH 169/254] OMAP2+: powerdomain: fix bank power state bitfields
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The bank power state bitfields in the powerdomain data are
+encoded incorrectly. These fields are intended to be bitfields,
+representing a set of power states that the memory banks support.
+However, when only one power state was supported by a given bank,
+the field was incorrectly set to the bit shift -- not the mask.
+While here, update some file copyrights.
+
+The OMAP4 autogeneration scripts have been updated accordingly.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
+---
+ arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 6 +-
+ arch/arm/mach-omap2/powerdomains2xxx_data.c | 18 +++---
+ arch/arm/mach-omap2/powerdomains3xxx_data.c | 38 +++++-----
+ arch/arm/mach-omap2/powerdomains44xx_data.c | 84 +++++++++++-----------
+ 4 files changed, 73 insertions(+), 73 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+index 96cda13..4210c33 100644
+--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
++++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+@@ -62,13 +62,13 @@ struct powerdomain gfx_omap2_pwrdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
+ CHIP_IS_OMAP3430ES1),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_RET,
++ .pwrsts_logic_ret = PWRSTS_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
++ [0] = PWRSTS_RET, /* MEMRETSTATE */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* MEMONSTATE */
++ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
+ };
+
+diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
+index 78739e1..cc389fb 100644
+--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
++++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
+@@ -2,7 +2,7 @@
+ * OMAP2XXX powerdomain definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+- * Copyright (C) 2007-2010 Nokia Corporation
++ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+@@ -30,13 +30,13 @@ static struct powerdomain dsp_pwrdm = {
+ .prcm_offs = OMAP24XX_DSP_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_RET,
++ .pwrsts_logic_ret = PWRSTS_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET,
++ [0] = PWRSTS_RET,
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON,
++ [0] = PWRSTS_ON,
+ },
+ };
+
+@@ -48,10 +48,10 @@ static struct powerdomain mpu_24xx_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET,
++ [0] = PWRSTS_RET,
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON,
++ [0] = PWRSTS_ON,
+ },
+ };
+
+@@ -87,13 +87,13 @@ static struct powerdomain mdm_pwrdm = {
+ .prcm_offs = OMAP2430_MDM_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_RET,
++ .pwrsts_logic_ret = PWRSTS_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
++ [0] = PWRSTS_RET, /* MEMRETSTATE */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* MEMONSTATE */
++ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
+ };
+
+diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
+index e1bec56..9c9c113 100644
+--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
++++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
+@@ -2,7 +2,7 @@
+ * OMAP3 powerdomain definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+- * Copyright (C) 2007-2010 Nokia Corporation
++ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ *
+@@ -47,10 +47,10 @@ static struct powerdomain iva2_pwrdm = {
+ [3] = PWRSTS_OFF_RET,
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON,
+- [1] = PWRDM_POWER_ON,
++ [0] = PWRSTS_ON,
++ [1] = PWRSTS_ON,
+ [2] = PWRSTS_OFF_ON,
+- [3] = PWRDM_POWER_ON,
++ [3] = PWRSTS_ON,
+ },
+ };
+
+@@ -128,13 +128,13 @@ static struct powerdomain dss_pwrdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .prcm_offs = OMAP3430_DSS_MOD,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_RET,
++ .pwrsts_logic_ret = PWRSTS_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
++ [0] = PWRSTS_RET, /* MEMRETSTATE */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* MEMONSTATE */
++ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
+ };
+
+@@ -149,13 +149,13 @@ static struct powerdomain sgx_pwrdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
+ /* XXX This is accurate for 3430 SGX, but what about GFX? */
+ .pwrsts = PWRSTS_OFF_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_RET,
++ .pwrsts_logic_ret = PWRSTS_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
++ [0] = PWRSTS_RET, /* MEMRETSTATE */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* MEMONSTATE */
++ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
+ };
+
+@@ -164,13 +164,13 @@ static struct powerdomain cam_pwrdm = {
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .prcm_offs = OMAP3430_CAM_MOD,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_RET,
++ .pwrsts_logic_ret = PWRSTS_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
++ [0] = PWRSTS_RET, /* MEMRETSTATE */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* MEMONSTATE */
++ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
+ };
+
+@@ -182,10 +182,10 @@ static struct powerdomain per_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
++ [0] = PWRSTS_RET, /* MEMRETSTATE */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* MEMONSTATE */
++ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
+ };
+
+@@ -200,7 +200,7 @@ static struct powerdomain neon_pwrdm = {
+ .prcm_offs = OMAP3430_NEON_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_RET,
++ .pwrsts_logic_ret = PWRSTS_RET,
+ };
+
+ static struct powerdomain usbhost_pwrdm = {
+@@ -208,7 +208,7 @@ static struct powerdomain usbhost_pwrdm = {
+ .prcm_offs = OMAP3430ES2_USBHOST_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+- .pwrsts_logic_ret = PWRDM_POWER_RET,
++ .pwrsts_logic_ret = PWRSTS_RET,
+ /*
+ * REVISIT: Enabling usb host save and restore mechanism seems to
+ * leave the usb host domain permanently in ACTIVE mode after
+@@ -218,10 +218,10 @@ static struct powerdomain usbhost_pwrdm = {
+ /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
++ [0] = PWRSTS_RET, /* MEMRETSTATE */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* MEMONSTATE */
++ [0] = PWRSTS_ON, /* MEMONSTATE */
+ },
+ };
+
+diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
+index 226e01a..c4222c7 100644
+--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
++++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
+@@ -2,7 +2,7 @@
+ * OMAP4 Power domains framework
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+- * Copyright (C) 2009-2010 Nokia Corporation
++ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+@@ -40,18 +40,18 @@ static struct powerdomain core_44xx_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 5,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* core_nret_bank */
++ [0] = PWRSTS_OFF, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+- [2] = PWRDM_POWER_RET, /* core_other_bank */
++ [2] = PWRSTS_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ducati_unicache */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* core_nret_bank */
++ [0] = PWRSTS_ON, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+- [2] = PWRDM_POWER_ON, /* core_other_bank */
+- [3] = PWRDM_POWER_ON, /* ducati_l2ram */
+- [4] = PWRDM_POWER_ON, /* ducati_unicache */
++ [2] = PWRSTS_ON, /* core_other_bank */
++ [3] = PWRSTS_ON, /* ducati_l2ram */
++ [4] = PWRSTS_ON, /* ducati_unicache */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+@@ -65,10 +65,10 @@ static struct powerdomain gfx_44xx_pwrdm = {
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* gfx_mem */
++ [0] = PWRSTS_OFF, /* gfx_mem */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* gfx_mem */
++ [0] = PWRSTS_ON, /* gfx_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+@@ -83,12 +83,12 @@ static struct powerdomain abe_44xx_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* aessmem */
+- [1] = PWRDM_POWER_OFF, /* periphmem */
++ [0] = PWRSTS_RET, /* aessmem */
++ [1] = PWRSTS_OFF, /* periphmem */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* aessmem */
+- [1] = PWRDM_POWER_ON, /* periphmem */
++ [0] = PWRSTS_ON, /* aessmem */
++ [1] = PWRSTS_ON, /* periphmem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+@@ -103,10 +103,10 @@ static struct powerdomain dss_44xx_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* dss_mem */
++ [0] = PWRSTS_OFF, /* dss_mem */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* dss_mem */
++ [0] = PWRSTS_ON, /* dss_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+@@ -121,14 +121,14 @@ static struct powerdomain tesla_44xx_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_RET, /* tesla_edma */
++ [0] = PWRSTS_RET, /* tesla_edma */
+ [1] = PWRSTS_OFF_RET, /* tesla_l1 */
+ [2] = PWRSTS_OFF_RET, /* tesla_l2 */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* tesla_edma */
+- [1] = PWRDM_POWER_ON, /* tesla_l1 */
+- [2] = PWRDM_POWER_ON, /* tesla_l2 */
++ [0] = PWRSTS_ON, /* tesla_edma */
++ [1] = PWRSTS_ON, /* tesla_l1 */
++ [2] = PWRSTS_ON, /* tesla_l2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+@@ -142,10 +142,10 @@ static struct powerdomain wkup_44xx_pwrdm = {
+ .pwrsts = PWRSTS_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* wkup_bank */
++ [0] = PWRSTS_OFF, /* wkup_bank */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* wkup_bank */
++ [0] = PWRSTS_ON, /* wkup_bank */
+ },
+ };
+
+@@ -162,7 +162,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
+ [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* cpu0_l1 */
++ [0] = PWRSTS_ON, /* cpu0_l1 */
+ },
+ };
+
+@@ -179,7 +179,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
+ [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* cpu1_l1 */
++ [0] = PWRSTS_ON, /* cpu1_l1 */
+ },
+ };
+
+@@ -192,10 +192,10 @@ static struct powerdomain emu_44xx_pwrdm = {
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* emu_bank */
++ [0] = PWRSTS_OFF, /* emu_bank */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* emu_bank */
++ [0] = PWRSTS_ON, /* emu_bank */
+ },
+ };
+
+@@ -211,12 +211,12 @@ static struct powerdomain mpu_44xx_pwrdm = {
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l1 */
+ [1] = PWRSTS_OFF_RET, /* mpu_l2 */
+- [2] = PWRDM_POWER_RET, /* mpu_ram */
++ [2] = PWRSTS_RET, /* mpu_ram */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* mpu_l1 */
+- [1] = PWRDM_POWER_ON, /* mpu_l2 */
+- [2] = PWRDM_POWER_ON, /* mpu_ram */
++ [0] = PWRSTS_ON, /* mpu_l1 */
++ [1] = PWRSTS_ON, /* mpu_l2 */
++ [2] = PWRSTS_ON, /* mpu_ram */
+ },
+ };
+
+@@ -230,16 +230,16 @@ static struct powerdomain ivahd_44xx_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 4,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* hwa_mem */
++ [0] = PWRSTS_OFF, /* hwa_mem */
+ [1] = PWRSTS_OFF_RET, /* sl2_mem */
+ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
+ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* hwa_mem */
+- [1] = PWRDM_POWER_ON, /* sl2_mem */
+- [2] = PWRDM_POWER_ON, /* tcm1_mem */
+- [3] = PWRDM_POWER_ON, /* tcm2_mem */
++ [0] = PWRSTS_ON, /* hwa_mem */
++ [1] = PWRSTS_ON, /* sl2_mem */
++ [2] = PWRSTS_ON, /* tcm1_mem */
++ [3] = PWRSTS_ON, /* tcm2_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+@@ -253,10 +253,10 @@ static struct powerdomain cam_44xx_pwrdm = {
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* cam_mem */
++ [0] = PWRSTS_OFF, /* cam_mem */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* cam_mem */
++ [0] = PWRSTS_ON, /* cam_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+@@ -271,10 +271,10 @@ static struct powerdomain l3init_44xx_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* l3init_bank1 */
++ [0] = PWRSTS_OFF, /* l3init_bank1 */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* l3init_bank1 */
++ [0] = PWRSTS_ON, /* l3init_bank1 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+@@ -289,12 +289,12 @@ static struct powerdomain l4per_44xx_pwrdm = {
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+- [0] = PWRDM_POWER_OFF, /* nonretained_bank */
+- [1] = PWRDM_POWER_RET, /* retained_bank */
++ [0] = PWRSTS_OFF, /* nonretained_bank */
++ [1] = PWRSTS_RET, /* retained_bank */
+ },
+ .pwrsts_mem_on = {
+- [0] = PWRDM_POWER_ON, /* nonretained_bank */
+- [1] = PWRDM_POWER_ON, /* retained_bank */
++ [0] = PWRSTS_ON, /* nonretained_bank */
++ [1] = PWRSTS_ON, /* retained_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ };
+--
+1.7.1
+
diff --git a/patches/for_next/0170-OMAP2-powerdomain-add-pwrdm_can_ever_lose_context.patch b/patches/for_next/0170-OMAP2-powerdomain-add-pwrdm_can_ever_lose_context.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a680fe44caa1764f90fcad5f12c5bae82b9613a7
--- /dev/null
+++ b/patches/for_next/0170-OMAP2-powerdomain-add-pwrdm_can_ever_lose_context.patch
@@ -0,0 +1,132 @@
+From 48cac49323ddb2ab227ef80b1a0e13992e6d8ff4 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Mon, 7 Mar 2011 19:28:15 -0700
+Subject: [PATCH 170/254] OMAP2+: powerdomain: add pwrdm_can_ever_lose_context()
+
+Some drivers wish to know whether the device that they control can
+ever lose context, for example, when the device's enclosing
+powerdomain loses power. They can use this information to determine
+whether it is necessary to save and restore device context, or whether
+it can be skipped. Implement the powerdomain portion of this by
+adding the function pwrdm_can_ever_lose_context(). This is not for
+use directly from driver code, but instead is intended to be called
+from driver-subarch integration code (i.e., arch/arm/*omap* code).
+
+Currently, the result from this function should be passed into the
+driver code via struct platform_data, but at some point this should
+be part of some common or OMAP-specific device code.
+
+While here, update file copyrights.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/powerdomain.c | 43 ++++++++++++++++++++++++++++++++++++-
+ arch/arm/mach-omap2/powerdomain.h | 18 +++++++--------
+ 2 files changed, 50 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
+index eaed0df..a11be81 100644
+--- a/arch/arm/mach-omap2/powerdomain.c
++++ b/arch/arm/mach-omap2/powerdomain.c
+@@ -2,7 +2,7 @@
+ * OMAP powerdomain control
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+- * Copyright (C) 2007-2009 Nokia Corporation
++ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
+@@ -938,3 +938,44 @@ u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
+
+ return count;
+ }
++
++/**
++ * pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
++ * @pwrdm: struct powerdomain *
++ *
++ * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
++ * can lose either memory or logic context or if @pwrdm is invalid, or
++ * returns 0 otherwise. This function is not concerned with how the
++ * powerdomain registers are programmed (i.e., to go off or not); it's
++ * concerned with whether it's ever possible for this powerdomain to
++ * go off while some other part of the chip is active. This function
++ * assumes that every powerdomain can go to either ON or INACTIVE.
++ */
++bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
++{
++ int i;
++
++ if (IS_ERR_OR_NULL(pwrdm)) {
++ pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
++ __func__);
++ return 1;
++ }
++
++ if (pwrdm->pwrsts & PWRSTS_OFF)
++ return 1;
++
++ if (pwrdm->pwrsts & PWRSTS_RET) {
++ if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
++ return 1;
++
++ for (i = 0; i < pwrdm->banks; i++)
++ if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
++ return 1;
++ }
++
++ for (i = 0; i < pwrdm->banks; i++)
++ if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
++ return 1;
++
++ return 0;
++}
+diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
+index 0b7a357..027f40b 100644
+--- a/arch/arm/mach-omap2/powerdomain.h
++++ b/arch/arm/mach-omap2/powerdomain.h
+@@ -2,7 +2,7 @@
+ * OMAP2/3/4 powerdomain control
+ *
+ * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
+- * Copyright (C) 2007-2010 Nokia Corporation
++ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+@@ -34,17 +34,14 @@
+
+ /* Powerdomain allowable state bitfields */
+ #define PWRSTS_ON (1 << PWRDM_POWER_ON)
++#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
++#define PWRSTS_RET (1 << PWRDM_POWER_RET)
+ #define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
+-#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
+- (1 << PWRDM_POWER_ON))
+
+-#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
+- (1 << PWRDM_POWER_RET))
+-
+-#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
+- (1 << PWRDM_POWER_ON))
+-
+-#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
++#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
++#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
++#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
++#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
+
+
+ /* Powerdomain flags */
+@@ -211,6 +208,7 @@ int pwrdm_pre_transition(void);
+ int pwrdm_post_transition(void);
+ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
+ u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
++bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
+
+ extern void omap2xxx_powerdomains_init(void);
+ extern void omap3xxx_powerdomains_init(void);
+--
+1.7.1
+
diff --git a/patches/for_next/0171-OMAP2-clock-add-DPLL-autoidle-support.patch b/patches/for_next/0171-OMAP2-clock-add-DPLL-autoidle-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d1de622fefe4890ff09866ffdd8e7bb336c87346
--- /dev/null
+++ b/patches/for_next/0171-OMAP2-clock-add-DPLL-autoidle-support.patch
@@ -0,0 +1,241 @@
+From 895a975c2df9afe2d14b5d8cffa5a19f0abc50ff Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:49:53 -0700
+Subject: [PATCH 171/254] OMAP2: clock: add DPLL autoidle support
+
+Add the necessary code and data to allow the clock framework to enable
+and disable the OMAP2 DPLL autoidle state. This is so the direct
+register access can be moved out of the mach-omap2/pm24xx.c code, and other
+code that needs to control this (e.g., CPUIdle) can do so via an API.
+As part of this patch, remove the pm24xx.c code that formerly wrote
+directly to the autoidle bits.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 3 +-
+ arch/arm/mach-omap2/clkt2xxx_dpll.c | 63 ++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/clock.h | 1 +
+ arch/arm/mach-omap2/clock2420_data.c | 2 +-
+ arch/arm/mach-omap2/clock2430_data.c | 2 +-
+ arch/arm/mach-omap2/cm2xxx_3xxx.c | 27 ++++++++++++++
+ arch/arm/mach-omap2/cm2xxx_3xxx.h | 3 ++
+ arch/arm/mach-omap2/pm24xx.c | 12 ++++---
+ 8 files changed, 105 insertions(+), 8 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/clkt2xxx_dpll.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 6874187..f64c428 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -115,7 +115,8 @@ obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
+ clkt2xxx_sys.o \
+ clkt2xxx_dpllcore.o \
+ clkt2xxx_virt_prcm_set.o \
+- clkt2xxx_apll.o clkt2xxx_osc.o
++ clkt2xxx_apll.o clkt2xxx_osc.o \
++ clkt2xxx_dpll.o
+ obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
+ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
+diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
+new file mode 100644
+index 0000000..1502a7b
+--- /dev/null
++++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
+@@ -0,0 +1,63 @@
++/*
++ * OMAP2-specific DPLL control functions
++ *
++ * Copyright (C) 2011 Nokia Corporation
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++
++#include <plat/clock.h>
++
++#include "clock.h"
++#include "cm2xxx_3xxx.h"
++#include "cm-regbits-24xx.h"
++
++/* Private functions */
++
++/**
++ * _allow_idle - enable DPLL autoidle bits
++ * @clk: struct clk * of the DPLL to operate on
++ *
++ * Enable DPLL automatic idle control. The DPLL will enter low-power
++ * stop when its downstream clocks are gated. No return value.
++ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
++ * instead. Add some mechanism to optionally enter this mode.
++ */
++static void _allow_idle(struct clk *clk)
++{
++ if (!clk || !clk->dpll_data)
++ return;
++
++ omap2xxx_cm_set_dpll_auto_low_power_stop();
++}
++
++/**
++ * _deny_idle - prevent DPLL from automatically idling
++ * @clk: struct clk * of the DPLL to operate on
++ *
++ * Disable DPLL automatic idle control. No return value.
++ */
++static void _deny_idle(struct clk *clk)
++{
++ if (!clk || !clk->dpll_data)
++ return;
++
++ omap2xxx_cm_set_dpll_disable_autoidle();
++}
++
++
++/* Public data */
++
++const struct clkops clkops_omap2xxx_dpll_ops = {
++ .allow_idle = _allow_idle,
++ .deny_idle = _deny_idle,
++};
++
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index 0725a6a..9972d89 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -148,6 +148,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+ #define omap2_clk_exit_cpufreq_table 0
+ #endif
+
++extern const struct clkops clkops_omap2xxx_dpll_ops;
+ extern const struct clkops clkops_omap3_noncore_dpll_ops;
+ extern const struct clkops clkops_omap3_core_dpll_ops;
+ extern const struct clkops clkops_omap4_dpllmx_ops;
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index ee73e14..30fbcbd 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -125,7 +125,7 @@ static struct dpll_data dpll_dd = {
+ */
+ static struct clk dpll_ck = {
+ .name = "dpll_ck",
+- .ops = &clkops_null,
++ .ops = &clkops_omap2xxx_dpll_ops,
+ .parent = &sys_ck, /* Can be func_32k also */
+ .dpll_data = &dpll_dd,
+ .clkdm_name = "wkup_clkdm",
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 7d68495..8c774ec 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -125,7 +125,7 @@ static struct dpll_data dpll_dd = {
+ */
+ static struct clk dpll_ck = {
+ .name = "dpll_ck",
+- .ops = &clkops_null,
++ .ops = &clkops_omap2xxx_dpll_ops,
+ .parent = &sys_ck, /* Can be func_32k also */
+ .dpll_data = &dpll_dd,
+ .clkdm_name = "wkup_clkdm",
+diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
+index 96954aa..6b0c7c8 100644
+--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
+@@ -25,6 +25,10 @@
+ #include "cm-regbits-24xx.h"
+ #include "cm-regbits-34xx.h"
+
++/* CM_AUTOIDLE_PLL.AUTO_* bit values */
++#define DPLL_AUTOIDLE_DISABLE 0x0
++#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
++
+ static const u8 cm_idlest_offs[] = {
+ CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+ };
+@@ -125,6 +129,29 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
+ _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
+ }
+
++/*
++ * DPLL autoidle control
++ */
++
++static void _omap2xxx_set_dpll_autoidle(u8 m)
++{
++ u32 v;
++
++ v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
++ v &= ~OMAP24XX_AUTO_DPLL_MASK;
++ v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
++ omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
++}
++
++void omap2xxx_cm_set_dpll_disable_autoidle(void)
++{
++ _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
++}
++
++void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
++{
++ _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
++}
+
+ /*
+ *
+diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
+index 5e9ea5b..5f4df1c 100644
+--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
++++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
+@@ -122,6 +122,9 @@ extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+ extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
+ extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+
++extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
++extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
++
+ #endif
+
+ /* CM register bits shared between 24XX and 3430 */
+diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
+index e983c83..297bb21 100644
+--- a/arch/arm/mach-omap2/pm24xx.c
++++ b/arch/arm/mach-omap2/pm24xx.c
+@@ -378,6 +378,7 @@ static void __init prcm_setup_regs(void)
+ {
+ int i, num_mem_banks;
+ struct powerdomain *pwrdm;
++ u32 v;
+
+ /* Enable autoidle */
+ omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
+@@ -468,11 +469,12 @@ static void __init prcm_setup_regs(void)
+ omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
+ CM_AUTOIDLE);
+
+- /* Put DPLL and both APLLs into autoidle mode */
+- omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
+- (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
+- (0x03 << OMAP24XX_AUTO_54M_SHIFT),
+- PLL_MOD, CM_AUTOIDLE);
++ /* Put both APLLs into autoidle mode */
++ v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
++ v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT);
++ v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
++ (0x03 << OMAP24XX_AUTO_54M_SHIFT);
++ omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+
+ omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
+ OMAP24XX_AUTO_WDT1_MASK |
+--
+1.7.1
+
diff --git a/patches/for_next/0172-OMAP2xxx-clock-add-clockfw-autoidle-support-for-APLL.patch b/patches/for_next/0172-OMAP2xxx-clock-add-clockfw-autoidle-support-for-APLL.patch
new file mode 100644
index 0000000000000000000000000000000000000000..146026b9d9c6f0966e8bc3f33730b59fe85fe02b
--- /dev/null
+++ b/patches/for_next/0172-OMAP2xxx-clock-add-clockfw-autoidle-support-for-APLL.patch
@@ -0,0 +1,179 @@
+From 10904bf7651ff4722a6a714c1cb42d09cdafc54a Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:27 -0700
+Subject: [PATCH 172/254] OMAP2xxx: clock: add clockfw autoidle support for APLLs
+
+OMAP2xxx devices have two on-chip APLLs. These APLLs can
+automatically enter idle when not in use. Connect the APLL autoidle
+code to the clock code, so that the clock framework can handle this
+process. As part of this patch, remove the code in mach-omap2/pm24xx.c
+that previously handled APLL autoidle control.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clkt2xxx_apll.c | 24 +++++++++++++++++++
+ arch/arm/mach-omap2/cm2xxx_3xxx.c | 44 ++++++++++++++++++++++++++++++++++-
+ arch/arm/mach-omap2/cm2xxx_3xxx.h | 5 ++++
+ arch/arm/mach-omap2/pm24xx.c | 8 ------
+ 4 files changed, 72 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
+index f51cffd..b19a1f7 100644
+--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
++++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
+@@ -78,6 +78,26 @@ static int omap2_clk_apll54_enable(struct clk *clk)
+ return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
+ }
+
++static void _apll96_allow_idle(struct clk *clk)
++{
++ omap2xxx_cm_set_apll96_auto_low_power_stop();
++}
++
++static void _apll96_deny_idle(struct clk *clk)
++{
++ omap2xxx_cm_set_apll96_disable_autoidle();
++}
++
++static void _apll54_allow_idle(struct clk *clk)
++{
++ omap2xxx_cm_set_apll54_auto_low_power_stop();
++}
++
++static void _apll54_deny_idle(struct clk *clk)
++{
++ omap2xxx_cm_set_apll54_disable_autoidle();
++}
++
+ /* Stop APLL */
+ static void omap2_clk_apll_disable(struct clk *clk)
+ {
+@@ -93,11 +113,15 @@ static void omap2_clk_apll_disable(struct clk *clk)
+ const struct clkops clkops_apll96 = {
+ .enable = omap2_clk_apll96_enable,
+ .disable = omap2_clk_apll_disable,
++ .allow_idle = _apll96_allow_idle,
++ .deny_idle = _apll96_deny_idle,
+ };
+
+ const struct clkops clkops_apll54 = {
+ .enable = omap2_clk_apll54_enable,
+ .disable = omap2_clk_apll_disable,
++ .allow_idle = _apll54_allow_idle,
++ .deny_idle = _apll54_deny_idle,
+ };
+
+ /* Public functions */
+diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
+index 6b0c7c8..9d0dec8 100644
+--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
+@@ -25,10 +25,14 @@
+ #include "cm-regbits-24xx.h"
+ #include "cm-regbits-34xx.h"
+
+-/* CM_AUTOIDLE_PLL.AUTO_* bit values */
++/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
+ #define DPLL_AUTOIDLE_DISABLE 0x0
+ #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
+
++/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
++#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
++#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
++
+ static const u8 cm_idlest_offs[] = {
+ CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+ };
+@@ -154,6 +158,44 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+ }
+
+ /*
++ * APLL autoidle control
++ */
++
++static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
++{
++ u32 v;
++
++ v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
++ v &= ~mask;
++ v |= m << __ffs(mask);
++ omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
++}
++
++void omap2xxx_cm_set_apll54_disable_autoidle(void)
++{
++ _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
++ OMAP24XX_AUTO_54M_MASK);
++}
++
++void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
++{
++ _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
++ OMAP24XX_AUTO_54M_MASK);
++}
++
++void omap2xxx_cm_set_apll96_disable_autoidle(void)
++{
++ _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
++ OMAP24XX_AUTO_96M_MASK);
++}
++
++void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
++{
++ _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
++ OMAP24XX_AUTO_96M_MASK);
++}
++
++/*
+ *
+ */
+
+diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
+index 5f4df1c..088bbad 100644
+--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
++++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
+@@ -125,6 +125,11 @@ extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+ extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
+ extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+
++extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
++extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
++extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
++extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
++
+ #endif
+
+ /* CM register bits shared between 24XX and 3430 */
+diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
+index 297bb21..abe08f4 100644
+--- a/arch/arm/mach-omap2/pm24xx.c
++++ b/arch/arm/mach-omap2/pm24xx.c
+@@ -378,7 +378,6 @@ static void __init prcm_setup_regs(void)
+ {
+ int i, num_mem_banks;
+ struct powerdomain *pwrdm;
+- u32 v;
+
+ /* Enable autoidle */
+ omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
+@@ -469,13 +468,6 @@ static void __init prcm_setup_regs(void)
+ omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
+ CM_AUTOIDLE);
+
+- /* Put both APLLs into autoidle mode */
+- v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+- v &= ~(OMAP24XX_AUTO_96M_MASK | OMAP24XX_AUTO_54M_SHIFT);
+- v |= (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
+- (0x03 << OMAP24XX_AUTO_54M_SHIFT);
+- omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+-
+ omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
+ OMAP24XX_AUTO_WDT1_MASK |
+ OMAP24XX_AUTO_MPU_WDT_MASK |
+--
+1.7.1
+
diff --git a/patches/for_next/0173-OMAP2-clock-comment-that-osc_ck-osc_sys_ck-should-us.patch b/patches/for_next/0173-OMAP2-clock-comment-that-osc_ck-osc_sys_ck-should-us.patch
new file mode 100644
index 0000000000000000000000000000000000000000..28cf0f115547c75aa8d5620f3088a2f4789b74f8
--- /dev/null
+++ b/patches/for_next/0173-OMAP2-clock-comment-that-osc_ck-osc_sys_ck-should-us.patch
@@ -0,0 +1,51 @@
+From a37f004cdad5df7c9f80d011bf863e9994c353b1 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:27 -0700
+Subject: [PATCH 173/254] OMAP2+: clock: comment that osc_ck/osc_sys_ck should use clockfw autoidle control
+
+Place some comments in the OMAP oscillator clock control code to note that
+its autoidle mode should eventually be controlled via the new OMAP clockfw
+autoidle control interface.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clkt2xxx_osc.c | 14 ++++++++++++++
+ 1 files changed, 14 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
+index df7b805..c346092 100644
+--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
++++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
+@@ -30,6 +30,13 @@
+ #include "prm2xxx_3xxx.h"
+ #include "prm-regbits-24xx.h"
+
++/*
++ * XXX This does not actually enable the osc_ck, since the osc_ck must
++ * be running for this function to be called. Instead, this function
++ * is used to disable an autoidle mode on the osc_ck. The existing
++ * clk_enable/clk_disable()-based usecounting for osc_ck should be
++ * replaced with autoidle-based usecounting.
++ */
+ static int omap2_enable_osc_ck(struct clk *clk)
+ {
+ u32 pcc;
+@@ -41,6 +48,13 @@ static int omap2_enable_osc_ck(struct clk *clk)
+ return 0;
+ }
+
++/*
++ * XXX This does not actually disable the osc_ck, since doing so would
++ * immediately halt the system. Instead, this function is used to
++ * enable an autoidle mode on the osc_ck. The existing
++ * clk_enable/clk_disable()-based usecounting for osc_ck should be
++ * replaced with autoidle-based usecounting.
++ */
+ static void omap2_disable_osc_ck(struct clk *clk)
+ {
+ u32 pcc;
+--
+1.7.1
+
diff --git a/patches/for_next/0174-OMAP2-clock-add-interface-clock-type-code-with-autoi.patch b/patches/for_next/0174-OMAP2-clock-add-interface-clock-type-code-with-autoi.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2f5ea1147108c79fad340dcf6f3dfea89d2514cf
--- /dev/null
+++ b/patches/for_next/0174-OMAP2-clock-add-interface-clock-type-code-with-autoi.patch
@@ -0,0 +1,164 @@
+From 404fc3705d8f4745511ef741e3b0640061e99184 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:28 -0700
+Subject: [PATCH 174/254] OMAP2+: clock: add interface clock type code with autoidle support
+
+Add interface clock type code with autoidle enable/disable support.
+The clkops structures created in this file will be used for all
+OMAP2/3 interface clocks with autoidle support. They will enable the
+clock framework to control interface clock autoidle directly.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 6 ++-
+ arch/arm/mach-omap2/clkt_iclk.c | 73 +++++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/clock.h | 9 ++++-
+ 3 files changed, 85 insertions(+), 3 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/clkt_iclk.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index f64c428..39b02bc 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -110,19 +110,21 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
+ obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
+ clockdomain44xx.o \
+ clockdomains44xx_data.o
++
+ # Clock framework
+ obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
+ clkt2xxx_sys.o \
+ clkt2xxx_dpllcore.o \
+ clkt2xxx_virt_prcm_set.o \
+ clkt2xxx_apll.o clkt2xxx_osc.o \
+- clkt2xxx_dpll.o
++ clkt2xxx_dpll.o clkt_iclk.o
+ obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
+ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
+ obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
+ clock34xx.o clkt34xx_dpll3m2.o \
+ clock3517.o clock36xx.o \
+- dpll3xxx.o clock3xxx_data.o
++ dpll3xxx.o clock3xxx_data.o \
++ clkt_iclk.o
+ obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
+ dpll3xxx.o dpll44xx.o
+
+diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
+new file mode 100644
+index 0000000..dd8a6d3
+--- /dev/null
++++ b/arch/arm/mach-omap2/clkt_iclk.c
+@@ -0,0 +1,73 @@
++/*
++ * OMAP2/3 interface clock control
++ *
++ * Copyright (C) 2011 Nokia Corporation
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#undef DEBUG
++
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++
++#include <plat/clock.h>
++#include <plat/prcm.h>
++
++#include "clock.h"
++#include "clock2xxx.h"
++#include "cm2xxx_3xxx.h"
++#include "cm-regbits-24xx.h"
++
++/* Private functions */
++
++/* XXX */
++void omap2_clkt_iclk_allow_idle(struct clk *clk)
++{
++ u32 v, r;
++
++ r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
++
++ v = __raw_readl((__force void __iomem *)r);
++ v |= (1 << clk->enable_bit);
++ __raw_writel(v, (__force void __iomem *)r);
++}
++
++/* XXX */
++void omap2_clkt_iclk_deny_idle(struct clk *clk)
++{
++ u32 v, r;
++
++ r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
++
++ v = __raw_readl((__force void __iomem *)r);
++ v &= ~(1 << clk->enable_bit);
++ __raw_writel(v, (__force void __iomem *)r);
++}
++
++/* Public data */
++
++const struct clkops clkops_omap2_iclk_dflt_wait = {
++ .enable = omap2_dflt_clk_enable,
++ .disable = omap2_dflt_clk_disable,
++ .find_companion = omap2_clk_dflt_find_companion,
++ .find_idlest = omap2_clk_dflt_find_idlest,
++ .allow_idle = omap2_clkt_iclk_allow_idle,
++ .deny_idle = omap2_clkt_iclk_deny_idle,
++};
++
++const struct clkops clkops_omap2_iclk_dflt = {
++ .enable = omap2_dflt_clk_enable,
++ .disable = omap2_dflt_clk_disable,
++ .allow_idle = omap2_clkt_iclk_allow_idle,
++ .deny_idle = omap2_clkt_iclk_deny_idle,
++};
++
++const struct clkops clkops_omap2_iclk_idle_only = {
++ .allow_idle = omap2_clkt_iclk_allow_idle,
++ .deny_idle = omap2_clkt_iclk_deny_idle,
++};
++
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index 9972d89..5008f14 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -2,7 +2,7 @@
+ * linux/arch/arm/mach-omap2/clock.h
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+- * Copyright (C) 2004-2009 Nokia Corporation
++ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+@@ -86,6 +86,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
+ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
+
++/* clkt_iclk.c public functions */
++extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
++extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
++
+ u32 omap2_get_dpll_rate(struct clk *clk);
+ void omap2_init_dpll_parent(struct clk *clk);
+
+@@ -148,6 +152,9 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+ #define omap2_clk_exit_cpufreq_table 0
+ #endif
+
++extern const struct clkops clkops_omap2_iclk_dflt_wait;
++extern const struct clkops clkops_omap2_iclk_dflt;
++extern const struct clkops clkops_omap2_iclk_idle_only;
+ extern const struct clkops clkops_omap2xxx_dpll_ops;
+ extern const struct clkops clkops_omap3_noncore_dpll_ops;
+ extern const struct clkops clkops_omap3_core_dpll_ops;
+--
+1.7.1
+
diff --git a/patches/for_next/0175-OMAP2420-clock-add-sdrc_ick.patch b/patches/for_next/0175-OMAP2420-clock-add-sdrc_ick.patch
new file mode 100644
index 0000000000000000000000000000000000000000..fd5567f99ca29aaeb8f1132e03d8237238b26c24
--- /dev/null
+++ b/patches/for_next/0175-OMAP2420-clock-add-sdrc_ick.patch
@@ -0,0 +1,65 @@
+From 77c4b0ed9eac594cf98a1b9daf9c9e525aa2a0f2 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:29 -0700
+Subject: [PATCH 175/254] OMAP2420: clock: add sdrc_ick
+
+Add sdrc_ick to the OMAP2420 clock data so the clock code can control
+the CM_AUTOIDLE bit associated with this clock.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clock2420_data.c | 16 ++++++++++++++++
+ arch/arm/mach-omap2/cm-regbits-24xx.h | 1 +
+ 2 files changed, 17 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 30fbcbd..63ed481 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -1608,6 +1608,21 @@ static struct clk sdma_ick = {
+ .recalc = &followparent_recalc,
+ };
+
++/*
++ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
++ * accesses derived from this data.
++ */
++static struct clk sdrc_ick = {
++ .name = "sdrc_ick",
++ .ops = &clkops_omap2_iclk_idle_only,
++ .parent = &core_l3_ck,
++ .flags = ENABLE_ON_INIT,
++ .clkdm_name = "core_l3_clkdm",
++ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
++ .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
++ .recalc = &followparent_recalc,
++};
++
+ static struct clk vlynq_ick = {
+ .name = "vlynq_ick",
+ .ops = &clkops_omap2_dflt_wait,
+@@ -1869,6 +1884,7 @@ static struct omap_clk omap2420_clks[] = {
+ CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
+ CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
+ CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
++ CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
+ CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
+ CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
+ CLK(NULL, "des_ick", &des_ick, CK_242X),
+diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
+index d70660e..409c813 100644
+--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
++++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
+@@ -210,6 +210,7 @@
+ #define OMAP24XX_AUTO_USB_MASK (1 << 0)
+
+ /* CM_AUTOIDLE3_CORE */
++#define OMAP24XX_AUTO_SDRC_SHIFT 2
+ #define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
+ #define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
+ #define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
+--
+1.7.1
+
diff --git a/patches/for_next/0176-OMAP2420-clock-use-autoidle-clkops-for-all-autoidle-.patch b/patches/for_next/0176-OMAP2420-clock-use-autoidle-clkops-for-all-autoidle-.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a62c666aa5664c8fcfd2fee6aa5419e67068ba87
--- /dev/null
+++ b/patches/for_next/0176-OMAP2420-clock-use-autoidle-clkops-for-all-autoidle-.patch
@@ -0,0 +1,500 @@
+From bca1b651fb3e91446ef005acec6126e26a419372 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:29 -0700
+Subject: [PATCH 176/254] OMAP2420: clock: use autoidle clkops for all autoidle-controllable interface clocks
+
+Mark each interface clock with a corresponding CM_AUTOIDLE bit with
+a clkops that has the allow_idle/deny_idle function pointers populated.
+This allows the OMAP clock framework to enable and disable autoidle for
+these clocks.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clock2420_data.c | 109 ++++++++++++++++++--------------
+ arch/arm/mach-omap2/cm-regbits-24xx.h | 2 +
+ 2 files changed, 63 insertions(+), 48 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 63ed481..68c0369 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -2,7 +2,7 @@
+ * linux/arch/arm/mach-omap2/clock2420_data.c
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+- * Copyright (C) 2004-2010 Nokia Corporation
++ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+@@ -481,7 +481,7 @@ static struct clk dsp_irate_ick = {
+ /* 2420 only */
+ static struct clk dsp_ick = {
+ .name = "dsp_ick", /* apparently ipi and isp */
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &dsp_irate_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
+@@ -579,7 +579,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
+ /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
+ static struct clk usb_l4_ick = { /* FS-USB interface clock */
+ .name = "usb_l4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -661,7 +661,7 @@ static struct clk ssi_ssr_sst_fck = {
+ */
+ static struct clk ssi_l4_ick = {
+ .name = "ssi_l4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -716,6 +716,7 @@ static struct clk gfx_2d_fck = {
+ .recalc = &omap2_clksel_recalc,
+ };
+
++/* This interface clock does not have a CM_AUTOIDLE bit */
+ static struct clk gfx_ick = {
+ .name = "gfx_ick", /* From l3 */
+ .ops = &clkops_omap2_dflt_wait,
+@@ -763,7 +764,7 @@ static const struct clksel dss1_fck_clksel[] = {
+
+ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
+ .name = "dss_ick",
+- .ops = &clkops_omap2_dflt,
++ .ops = &clkops_omap2_iclk_dflt,
+ .parent = &l4_ck, /* really both l3 and l4 */
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -845,7 +846,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
+
+ static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -871,7 +872,7 @@ static struct clk gpt1_fck = {
+
+ static struct clk gpt2_ick = {
+ .name = "gpt2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -895,7 +896,7 @@ static struct clk gpt2_fck = {
+
+ static struct clk gpt3_ick = {
+ .name = "gpt3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -919,7 +920,7 @@ static struct clk gpt3_fck = {
+
+ static struct clk gpt4_ick = {
+ .name = "gpt4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -943,7 +944,7 @@ static struct clk gpt4_fck = {
+
+ static struct clk gpt5_ick = {
+ .name = "gpt5_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -967,7 +968,7 @@ static struct clk gpt5_fck = {
+
+ static struct clk gpt6_ick = {
+ .name = "gpt6_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -991,7 +992,7 @@ static struct clk gpt6_fck = {
+
+ static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+@@ -1014,7 +1015,7 @@ static struct clk gpt7_fck = {
+
+ static struct clk gpt8_ick = {
+ .name = "gpt8_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1038,7 +1039,7 @@ static struct clk gpt8_fck = {
+
+ static struct clk gpt9_ick = {
+ .name = "gpt9_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1062,7 +1063,7 @@ static struct clk gpt9_fck = {
+
+ static struct clk gpt10_ick = {
+ .name = "gpt10_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1086,7 +1087,7 @@ static struct clk gpt10_fck = {
+
+ static struct clk gpt11_ick = {
+ .name = "gpt11_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1110,7 +1111,7 @@ static struct clk gpt11_fck = {
+
+ static struct clk gpt12_ick = {
+ .name = "gpt12_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1134,7 +1135,7 @@ static struct clk gpt12_fck = {
+
+ static struct clk mcbsp1_ick = {
+ .name = "mcbsp1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1174,7 +1175,7 @@ static struct clk mcbsp1_fck = {
+
+ static struct clk mcbsp2_ick = {
+ .name = "mcbsp2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1198,7 +1199,7 @@ static struct clk mcbsp2_fck = {
+
+ static struct clk mcspi1_ick = {
+ .name = "mcspi1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1218,7 +1219,7 @@ static struct clk mcspi1_fck = {
+
+ static struct clk mcspi2_ick = {
+ .name = "mcspi2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1238,7 +1239,7 @@ static struct clk mcspi2_fck = {
+
+ static struct clk uart1_ick = {
+ .name = "uart1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1258,7 +1259,7 @@ static struct clk uart1_fck = {
+
+ static struct clk uart2_ick = {
+ .name = "uart2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1278,7 +1279,7 @@ static struct clk uart2_fck = {
+
+ static struct clk uart3_ick = {
+ .name = "uart3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1298,7 +1299,7 @@ static struct clk uart3_fck = {
+
+ static struct clk gpios_ick = {
+ .name = "gpios_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -1318,7 +1319,7 @@ static struct clk gpios_fck = {
+
+ static struct clk mpu_wdt_ick = {
+ .name = "mpu_wdt_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -1338,7 +1339,7 @@ static struct clk mpu_wdt_fck = {
+
+ static struct clk sync_32k_ick = {
+ .name = "sync_32k_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l4_clkdm",
+@@ -1349,7 +1350,7 @@ static struct clk sync_32k_ick = {
+
+ static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -1359,7 +1360,7 @@ static struct clk wdt1_ick = {
+
+ static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l4_clkdm",
+@@ -1370,7 +1371,7 @@ static struct clk omapctrl_ick = {
+
+ static struct clk cam_ick = {
+ .name = "cam_ick",
+- .ops = &clkops_omap2_dflt,
++ .ops = &clkops_omap2_iclk_dflt,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1395,7 +1396,7 @@ static struct clk cam_fck = {
+
+ static struct clk mailboxes_ick = {
+ .name = "mailboxes_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1405,7 +1406,7 @@ static struct clk mailboxes_ick = {
+
+ static struct clk wdt4_ick = {
+ .name = "wdt4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1425,7 +1426,7 @@ static struct clk wdt4_fck = {
+
+ static struct clk wdt3_ick = {
+ .name = "wdt3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1445,7 +1446,7 @@ static struct clk wdt3_fck = {
+
+ static struct clk mspro_ick = {
+ .name = "mspro_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1465,7 +1466,7 @@ static struct clk mspro_fck = {
+
+ static struct clk mmc_ick = {
+ .name = "mmc_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1485,7 +1486,7 @@ static struct clk mmc_fck = {
+
+ static struct clk fac_ick = {
+ .name = "fac_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1505,7 +1506,7 @@ static struct clk fac_fck = {
+
+ static struct clk eac_ick = {
+ .name = "eac_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1525,7 +1526,7 @@ static struct clk eac_fck = {
+
+ static struct clk hdq_ick = {
+ .name = "hdq_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1545,7 +1546,7 @@ static struct clk hdq_fck = {
+
+ static struct clk i2c2_ick = {
+ .name = "i2c2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1565,7 +1566,7 @@ static struct clk i2c2_fck = {
+
+ static struct clk i2c1_ick = {
+ .name = "i2c1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1583,12 +1584,18 @@ static struct clk i2c1_fck = {
+ .recalc = &followparent_recalc,
+ };
+
++/*
++ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
++ * accesses derived from this data.
++ */
+ static struct clk gpmc_fck = {
+ .name = "gpmc_fck",
+- .ops = &clkops_null, /* RMK: missing? */
++ .ops = &clkops_omap2_iclk_idle_only,
+ .parent = &core_l3_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
++ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
++ .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
+ .recalc = &followparent_recalc,
+ };
+
+@@ -1600,11 +1607,17 @@ static struct clk sdma_fck = {
+ .recalc = &followparent_recalc,
+ };
+
++/*
++ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
++ * accesses derived from this data.
++ */
+ static struct clk sdma_ick = {
+ .name = "sdma_ick",
+- .ops = &clkops_null, /* RMK: missing? */
++ .ops = &clkops_omap2_iclk_idle_only,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l3_clkdm",
++ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
++ .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
+ .recalc = &followparent_recalc,
+ };
+
+@@ -1625,7 +1638,7 @@ static struct clk sdrc_ick = {
+
+ static struct clk vlynq_ick = {
+ .name = "vlynq_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1674,7 +1687,7 @@ static struct clk vlynq_fck = {
+
+ static struct clk des_ick = {
+ .name = "des_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1684,7 +1697,7 @@ static struct clk des_ick = {
+
+ static struct clk sha_ick = {
+ .name = "sha_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1694,7 +1707,7 @@ static struct clk sha_ick = {
+
+ static struct clk rng_ick = {
+ .name = "rng_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1704,7 +1717,7 @@ static struct clk rng_ick = {
+
+ static struct clk aes_ick = {
+ .name = "aes_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1714,7 +1727,7 @@ static struct clk aes_ick = {
+
+ static struct clk pka_ick = {
+ .name = "pka_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
+index 409c813..6862904 100644
+--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
++++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
+@@ -212,7 +212,9 @@
+ /* CM_AUTOIDLE3_CORE */
+ #define OMAP24XX_AUTO_SDRC_SHIFT 2
+ #define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
++#define OMAP24XX_AUTO_GPMC_SHIFT 1
+ #define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
++#define OMAP24XX_AUTO_SDMA_SHIFT 0
+ #define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
+
+ /* CM_AUTOIDLE4_CORE */
+--
+1.7.1
+
diff --git a/patches/for_next/0177-OMAP2430-3xxx-clock-add-modem-clock-autoidle-support.patch b/patches/for_next/0177-OMAP2430-3xxx-clock-add-modem-clock-autoidle-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..821215841dab64ba2e9b4d2a28789f50c7fc2fac
--- /dev/null
+++ b/patches/for_next/0177-OMAP2430-3xxx-clock-add-modem-clock-autoidle-support.patch
@@ -0,0 +1,49 @@
+From 8a6d23303eeb0a4cab6da2525696662e67970d95 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:29 -0700
+Subject: [PATCH 177/254] OMAP2430/3xxx: clock: add modem clock autoidle support
+
+OMAP2430 and OMAP3xxx have modem autoidle bits that are actually
+attached to clocks with CM_FCLKEN bits; add the code and data to
+handle these.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clkt_iclk.c | 9 +++++++++
+ arch/arm/mach-omap2/clock.h | 1 +
+ 2 files changed, 10 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
+index dd8a6d3..3d43fba 100644
+--- a/arch/arm/mach-omap2/clkt_iclk.c
++++ b/arch/arm/mach-omap2/clkt_iclk.c
+@@ -71,3 +71,12 @@ const struct clkops clkops_omap2_iclk_idle_only = {
+ .deny_idle = omap2_clkt_iclk_deny_idle,
+ };
+
++const struct clkops clkops_omap2_mdmclk_dflt_wait = {
++ .enable = omap2_dflt_clk_enable,
++ .disable = omap2_dflt_clk_disable,
++ .find_companion = omap2_clk_dflt_find_companion,
++ .find_idlest = omap2_clk_dflt_find_idlest,
++ .allow_idle = omap2_clkt_iclk_allow_idle,
++ .deny_idle = omap2_clkt_iclk_deny_idle,
++};
++
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index 5008f14..70f8b07 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -155,6 +155,7 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+ extern const struct clkops clkops_omap2_iclk_dflt_wait;
+ extern const struct clkops clkops_omap2_iclk_dflt;
+ extern const struct clkops clkops_omap2_iclk_idle_only;
++extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
+ extern const struct clkops clkops_omap2xxx_dpll_ops;
+ extern const struct clkops clkops_omap3_noncore_dpll_ops;
+ extern const struct clkops clkops_omap3_core_dpll_ops;
+--
+1.7.1
+
diff --git a/patches/for_next/0178-OMAP2430-clock-use-autoidle-clkops-for-all-autoidle-.patch b/patches/for_next/0178-OMAP2430-clock-use-autoidle-clkops-for-all-autoidle-.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d0d29fb2f9e79e1652c52da7e76e1ef655aa1128
--- /dev/null
+++ b/patches/for_next/0178-OMAP2430-clock-use-autoidle-clkops-for-all-autoidle-.patch
@@ -0,0 +1,555 @@
+From 7cdf948c8be3c368129026ac4581d06888b9b2a4 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:30 -0700
+Subject: [PATCH 178/254] OMAP2430: clock: use autoidle clkops for all autoidle-controllable interface clocks
+
+Mark each interface clock with a corresponding CM_AUTOIDLE bit with
+a clkops that has the allow_idle/deny_idle function pointers populated.
+This allows the OMAP clock framework to enable and disable autoidle for
+these clocks.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clock2430_data.c | 125 +++++++++++++++++++---------------
+ 1 files changed, 69 insertions(+), 56 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 8c774ec..2aea882 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -2,7 +2,7 @@
+ * linux/arch/arm/mach-omap2/clock2430_data.c
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+- * Copyright (C) 2004-2010 Nokia Corporation
++ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+@@ -525,7 +525,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
+ /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
+ static struct clk usb_l4_ick = { /* FS-USB interface clock */
+ .name = "usb_l4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -606,7 +606,7 @@ static struct clk ssi_ssr_sst_fck = {
+ */
+ static struct clk ssi_l4_ick = {
+ .name = "ssi_l4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -661,6 +661,7 @@ static struct clk gfx_2d_fck = {
+ .recalc = &omap2_clksel_recalc,
+ };
+
++/* This interface clock does not have a CM_AUTOIDLE bit */
+ static struct clk gfx_ick = {
+ .name = "gfx_ick", /* From l3 */
+ .ops = &clkops_omap2_dflt_wait,
+@@ -693,7 +694,7 @@ static const struct clksel mdm_ick_clksel[] = {
+
+ static struct clk mdm_ick = { /* used both as a ick and fck */
+ .name = "mdm_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_ck,
+ .clkdm_name = "mdm_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+@@ -706,7 +707,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
+
+ static struct clk mdm_osc_ck = {
+ .name = "mdm_osc_ck",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_mdmclk_dflt_wait,
+ .parent = &osc_ck,
+ .clkdm_name = "mdm_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
+@@ -751,7 +752,7 @@ static const struct clksel dss1_fck_clksel[] = {
+
+ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
+ .name = "dss_ick",
+- .ops = &clkops_omap2_dflt,
++ .ops = &clkops_omap2_iclk_dflt,
+ .parent = &l4_ck, /* really both l3 and l4 */
+ .clkdm_name = "dss_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -833,7 +834,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
+
+ static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -859,7 +860,7 @@ static struct clk gpt1_fck = {
+
+ static struct clk gpt2_ick = {
+ .name = "gpt2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -883,7 +884,7 @@ static struct clk gpt2_fck = {
+
+ static struct clk gpt3_ick = {
+ .name = "gpt3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -907,7 +908,7 @@ static struct clk gpt3_fck = {
+
+ static struct clk gpt4_ick = {
+ .name = "gpt4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -931,7 +932,7 @@ static struct clk gpt4_fck = {
+
+ static struct clk gpt5_ick = {
+ .name = "gpt5_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -955,7 +956,7 @@ static struct clk gpt5_fck = {
+
+ static struct clk gpt6_ick = {
+ .name = "gpt6_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -979,7 +980,7 @@ static struct clk gpt6_fck = {
+
+ static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+@@ -1002,7 +1003,7 @@ static struct clk gpt7_fck = {
+
+ static struct clk gpt8_ick = {
+ .name = "gpt8_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1026,7 +1027,7 @@ static struct clk gpt8_fck = {
+
+ static struct clk gpt9_ick = {
+ .name = "gpt9_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1050,7 +1051,7 @@ static struct clk gpt9_fck = {
+
+ static struct clk gpt10_ick = {
+ .name = "gpt10_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1074,7 +1075,7 @@ static struct clk gpt10_fck = {
+
+ static struct clk gpt11_ick = {
+ .name = "gpt11_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1098,7 +1099,7 @@ static struct clk gpt11_fck = {
+
+ static struct clk gpt12_ick = {
+ .name = "gpt12_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1122,7 +1123,7 @@ static struct clk gpt12_fck = {
+
+ static struct clk mcbsp1_ick = {
+ .name = "mcbsp1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1162,7 +1163,7 @@ static struct clk mcbsp1_fck = {
+
+ static struct clk mcbsp2_ick = {
+ .name = "mcbsp2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1186,7 +1187,7 @@ static struct clk mcbsp2_fck = {
+
+ static struct clk mcbsp3_ick = {
+ .name = "mcbsp3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1210,7 +1211,7 @@ static struct clk mcbsp3_fck = {
+
+ static struct clk mcbsp4_ick = {
+ .name = "mcbsp4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1234,7 +1235,7 @@ static struct clk mcbsp4_fck = {
+
+ static struct clk mcbsp5_ick = {
+ .name = "mcbsp5_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1258,7 +1259,7 @@ static struct clk mcbsp5_fck = {
+
+ static struct clk mcspi1_ick = {
+ .name = "mcspi1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1278,7 +1279,7 @@ static struct clk mcspi1_fck = {
+
+ static struct clk mcspi2_ick = {
+ .name = "mcspi2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1298,7 +1299,7 @@ static struct clk mcspi2_fck = {
+
+ static struct clk mcspi3_ick = {
+ .name = "mcspi3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1318,7 +1319,7 @@ static struct clk mcspi3_fck = {
+
+ static struct clk uart1_ick = {
+ .name = "uart1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1338,7 +1339,7 @@ static struct clk uart1_fck = {
+
+ static struct clk uart2_ick = {
+ .name = "uart2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1358,7 +1359,7 @@ static struct clk uart2_fck = {
+
+ static struct clk uart3_ick = {
+ .name = "uart3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1378,7 +1379,7 @@ static struct clk uart3_fck = {
+
+ static struct clk gpios_ick = {
+ .name = "gpios_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -1398,7 +1399,7 @@ static struct clk gpios_fck = {
+
+ static struct clk mpu_wdt_ick = {
+ .name = "mpu_wdt_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -1418,7 +1419,7 @@ static struct clk mpu_wdt_fck = {
+
+ static struct clk sync_32k_ick = {
+ .name = "sync_32k_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l4_clkdm",
+@@ -1429,7 +1430,7 @@ static struct clk sync_32k_ick = {
+
+ static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -1439,7 +1440,7 @@ static struct clk wdt1_ick = {
+
+ static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l4_clkdm",
+@@ -1450,7 +1451,7 @@ static struct clk omapctrl_ick = {
+
+ static struct clk icr_ick = {
+ .name = "icr_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+@@ -1460,7 +1461,7 @@ static struct clk icr_ick = {
+
+ static struct clk cam_ick = {
+ .name = "cam_ick",
+- .ops = &clkops_omap2_dflt,
++ .ops = &clkops_omap2_iclk_dflt,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1485,7 +1486,7 @@ static struct clk cam_fck = {
+
+ static struct clk mailboxes_ick = {
+ .name = "mailboxes_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1495,7 +1496,7 @@ static struct clk mailboxes_ick = {
+
+ static struct clk wdt4_ick = {
+ .name = "wdt4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1515,7 +1516,7 @@ static struct clk wdt4_fck = {
+
+ static struct clk mspro_ick = {
+ .name = "mspro_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1535,7 +1536,7 @@ static struct clk mspro_fck = {
+
+ static struct clk fac_ick = {
+ .name = "fac_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1555,7 +1556,7 @@ static struct clk fac_fck = {
+
+ static struct clk hdq_ick = {
+ .name = "hdq_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1579,7 +1580,7 @@ static struct clk hdq_fck = {
+ */
+ static struct clk i2c2_ick = {
+ .name = "i2c2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1603,7 +1604,7 @@ static struct clk i2chs2_fck = {
+ */
+ static struct clk i2c1_ick = {
+ .name = "i2c1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -1621,12 +1622,18 @@ static struct clk i2chs1_fck = {
+ .recalc = &followparent_recalc,
+ };
+
++/*
++ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
++ * accesses derived from this data.
++ */
+ static struct clk gpmc_fck = {
+ .name = "gpmc_fck",
+- .ops = &clkops_null, /* RMK: missing? */
++ .ops = &clkops_omap2_iclk_idle_only,
+ .parent = &core_l3_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l3_clkdm",
++ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
++ .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
+ .recalc = &followparent_recalc,
+ };
+
+@@ -1638,17 +1645,23 @@ static struct clk sdma_fck = {
+ .recalc = &followparent_recalc,
+ };
+
++/*
++ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
++ * accesses derived from this data.
++ */
+ static struct clk sdma_ick = {
+ .name = "sdma_ick",
+- .ops = &clkops_null, /* RMK: missing? */
++ .ops = &clkops_omap2_iclk_idle_only,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l3_clkdm",
++ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
++ .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
+ .recalc = &followparent_recalc,
+ };
+
+ static struct clk sdrc_ick = {
+ .name = "sdrc_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_idle_only,
+ .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+ .clkdm_name = "core_l4_clkdm",
+@@ -1659,7 +1672,7 @@ static struct clk sdrc_ick = {
+
+ static struct clk des_ick = {
+ .name = "des_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1669,7 +1682,7 @@ static struct clk des_ick = {
+
+ static struct clk sha_ick = {
+ .name = "sha_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1679,7 +1692,7 @@ static struct clk sha_ick = {
+
+ static struct clk rng_ick = {
+ .name = "rng_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1689,7 +1702,7 @@ static struct clk rng_ick = {
+
+ static struct clk aes_ick = {
+ .name = "aes_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1699,7 +1712,7 @@ static struct clk aes_ick = {
+
+ static struct clk pka_ick = {
+ .name = "pka_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+@@ -1719,7 +1732,7 @@ static struct clk usb_fck = {
+
+ static struct clk usbhs_ick = {
+ .name = "usbhs_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l3_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1729,7 +1742,7 @@ static struct clk usbhs_ick = {
+
+ static struct clk mmchs1_ick = {
+ .name = "mmchs1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1749,7 +1762,7 @@ static struct clk mmchs1_fck = {
+
+ static struct clk mmchs2_ick = {
+ .name = "mmchs2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1768,7 +1781,7 @@ static struct clk mmchs2_fck = {
+
+ static struct clk gpio5_ick = {
+ .name = "gpio5_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+@@ -1788,7 +1801,7 @@ static struct clk gpio5_fck = {
+
+ static struct clk mdm_intc_ick = {
+ .name = "mdm_intc_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
+ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+--
+1.7.1
+
diff --git a/patches/for_next/0179-OMAP3-clock-use-autoidle-clkops-for-all-autoidle-con.patch b/patches/for_next/0179-OMAP3-clock-use-autoidle-clkops-for-all-autoidle-con.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3095a59034ae683688393a7b38f4206ca1add0b8
--- /dev/null
+++ b/patches/for_next/0179-OMAP3-clock-use-autoidle-clkops-for-all-autoidle-con.patch
@@ -0,0 +1,797 @@
+From 7bd20a4957cac6531f44221af93e3be889fc59c2 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:30 -0700
+Subject: [PATCH 179/254] OMAP3: clock: use autoidle clkops for all autoidle-controllable interface clocks
+
+Mark each interface clock with a corresponding CM_AUTOIDLE bit with
+a clkops that has the allow_idle/deny_idle function pointers populated.
+This allows the OMAP clock framework to enable and disable autoidle for
+these clocks.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clock34xx.c | 29 +++++++-
+ arch/arm/mach-omap2/clock34xx.h | 5 +-
+ arch/arm/mach-omap2/clock3517.c | 4 +-
+ arch/arm/mach-omap2/clock3xxx_data.c | 149 +++++++++++++++++----------------
+ 4 files changed, 112 insertions(+), 75 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
+index 287abc4..1fc96b9 100644
+--- a/arch/arm/mach-omap2/clock34xx.c
++++ b/arch/arm/mach-omap2/clock34xx.c
+@@ -2,7 +2,7 @@
+ * OMAP3-specific clock framework functions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+- * Copyright (C) 2007-2010 Nokia Corporation
++ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Jouni Högander
+@@ -59,6 +59,15 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
+ .find_companion = omap2_clk_dflt_find_companion,
+ };
+
++const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
++ .enable = omap2_dflt_clk_enable,
++ .disable = omap2_dflt_clk_disable,
++ .find_idlest = omap3430es2_clk_ssi_find_idlest,
++ .find_companion = omap2_clk_dflt_find_companion,
++ .allow_idle = omap2_clkt_iclk_allow_idle,
++ .deny_idle = omap2_clkt_iclk_deny_idle,
++};
++
+ /**
+ * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
+ * @clk: struct clk * being enabled
+@@ -94,6 +103,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
+ .find_companion = omap2_clk_dflt_find_companion,
+ };
+
++const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
++ .enable = omap2_dflt_clk_enable,
++ .disable = omap2_dflt_clk_disable,
++ .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
++ .find_companion = omap2_clk_dflt_find_companion,
++ .allow_idle = omap2_clkt_iclk_allow_idle,
++ .deny_idle = omap2_clkt_iclk_deny_idle,
++};
++
+ /**
+ * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
+ * @clk: struct clk * being enabled
+@@ -124,3 +142,12 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
+ .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+ };
++
++const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = {
++ .enable = omap2_dflt_clk_enable,
++ .disable = omap2_dflt_clk_disable,
++ .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
++ .find_companion = omap2_clk_dflt_find_companion,
++ .allow_idle = omap2_clkt_iclk_allow_idle,
++ .deny_idle = omap2_clkt_iclk_deny_idle,
++};
+diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
+index 628e8de..084ba71 100644
+--- a/arch/arm/mach-omap2/clock34xx.h
++++ b/arch/arm/mach-omap2/clock34xx.h
+@@ -2,14 +2,17 @@
+ * OMAP34xx clock function prototypes and macros
+ *
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+- * Copyright (C) 2007-2010 Nokia Corporation
++ * Copyright (C) 2007-2011 Nokia Corporation
+ */
+
+ #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+ #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+
+ extern const struct clkops clkops_omap3430es2_ssi_wait;
++extern const struct clkops clkops_omap3430es2_iclk_ssi_wait;
+ extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
++extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait;
+ extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
++extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait;
+
+ #endif
+diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
+index 74116a3..2e97d08 100644
+--- a/arch/arm/mach-omap2/clock3517.c
++++ b/arch/arm/mach-omap2/clock3517.c
+@@ -2,7 +2,7 @@
+ * OMAP3517/3505-specific clock framework functions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+- * Copyright (C) 2010 Nokia Corporation
++ * Copyright (C) 2011 Nokia Corporation
+ *
+ * Ranjith Lohithakshan
+ * Paul Walmsley
+@@ -119,6 +119,8 @@ const struct clkops clkops_am35xx_ipss_wait = {
+ .disable = omap2_dflt_clk_disable,
+ .find_idlest = am35xx_clk_ipss_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
++ .allow_idle = omap2_clkt_iclk_allow_idle,
++ .deny_idle = omap2_clkt_iclk_deny_idle,
+ };
+
+
+diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
+index f18c5e2..52f991c 100644
+--- a/arch/arm/mach-omap2/clock3xxx_data.c
++++ b/arch/arm/mach-omap2/clock3xxx_data.c
+@@ -2,7 +2,7 @@
+ * OMAP3 clock data
+ *
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+- * Copyright (C) 2007-2010 Nokia Corporation
++ * Copyright (C) 2007-2011 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * With many device clock fixes by Kevin Hilman and Jouni Högander
+@@ -1205,7 +1205,10 @@ static const struct clksel gfx_l3_clksel[] = {
+ { .parent = NULL }
+ };
+
+-/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
++/*
++ * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
++ * This interface clock does not have a CM_AUTOIDLE bit
++ */
+ static struct clk gfx_l3_ck = {
+ .name = "gfx_l3_ck",
+ .ops = &clkops_omap2_dflt_wait,
+@@ -1304,6 +1307,7 @@ static struct clk sgx_fck = {
+ .round_rate = &omap2_clksel_round_rate
+ };
+
++/* This interface clock does not have a CM_AUTOIDLE bit */
+ static struct clk sgx_ick = {
+ .name = "sgx_ick",
+ .ops = &clkops_omap2_dflt_wait,
+@@ -1328,7 +1332,7 @@ static struct clk d2d_26m_fck = {
+
+ static struct clk modem_fck = {
+ .name = "modem_fck",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_mdmclk_dflt_wait,
+ .parent = &sys_ck,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MODEM_SHIFT,
+@@ -1338,7 +1342,7 @@ static struct clk modem_fck = {
+
+ static struct clk sad2d_ick = {
+ .name = "sad2d_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
+@@ -1348,7 +1352,7 @@ static struct clk sad2d_ick = {
+
+ static struct clk mad2d_ick = {
+ .name = "mad2d_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
+@@ -1718,7 +1722,7 @@ static struct clk core_l3_ick = {
+
+ static struct clk hsotgusb_ick_3430es1 = {
+ .name = "hsotgusb_ick",
+- .ops = &clkops_omap2_dflt,
++ .ops = &clkops_omap2_iclk_dflt,
+ .parent = &core_l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
+@@ -1728,7 +1732,7 @@ static struct clk hsotgusb_ick_3430es1 = {
+
+ static struct clk hsotgusb_ick_3430es2 = {
+ .name = "hsotgusb_ick",
+- .ops = &clkops_omap3430es2_hsotgusb_wait,
++ .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
+ .parent = &core_l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
+@@ -1736,6 +1740,7 @@ static struct clk hsotgusb_ick_3430es2 = {
+ .recalc = &followparent_recalc,
+ };
+
++/* This interface clock does not have a CM_AUTOIDLE bit */
+ static struct clk sdrc_ick = {
+ .name = "sdrc_ick",
+ .ops = &clkops_omap2_dflt_wait,
+@@ -1767,7 +1772,7 @@ static struct clk security_l3_ick = {
+
+ static struct clk pka_ick = {
+ .name = "pka_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &security_l3_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_PKA_SHIFT,
+@@ -1786,7 +1791,7 @@ static struct clk core_l4_ick = {
+
+ static struct clk usbtll_ick = {
+ .name = "usbtll_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+@@ -1796,7 +1801,7 @@ static struct clk usbtll_ick = {
+
+ static struct clk mmchs3_ick = {
+ .name = "mmchs3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
+@@ -1807,7 +1812,7 @@ static struct clk mmchs3_ick = {
+ /* Intersystem Communication Registers - chassis mode only */
+ static struct clk icr_ick = {
+ .name = "icr_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_ICR_SHIFT,
+@@ -1817,7 +1822,7 @@ static struct clk icr_ick = {
+
+ static struct clk aes2_ick = {
+ .name = "aes2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_AES2_SHIFT,
+@@ -1827,7 +1832,7 @@ static struct clk aes2_ick = {
+
+ static struct clk sha12_ick = {
+ .name = "sha12_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_SHA12_SHIFT,
+@@ -1837,7 +1842,7 @@ static struct clk sha12_ick = {
+
+ static struct clk des2_ick = {
+ .name = "des2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_DES2_SHIFT,
+@@ -1847,7 +1852,7 @@ static struct clk des2_ick = {
+
+ static struct clk mmchs2_ick = {
+ .name = "mmchs2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MMC2_SHIFT,
+@@ -1857,7 +1862,7 @@ static struct clk mmchs2_ick = {
+
+ static struct clk mmchs1_ick = {
+ .name = "mmchs1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MMC1_SHIFT,
+@@ -1867,7 +1872,7 @@ static struct clk mmchs1_ick = {
+
+ static struct clk mspro_ick = {
+ .name = "mspro_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
+@@ -1877,7 +1882,7 @@ static struct clk mspro_ick = {
+
+ static struct clk hdq_ick = {
+ .name = "hdq_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_HDQ_SHIFT,
+@@ -1887,7 +1892,7 @@ static struct clk hdq_ick = {
+
+ static struct clk mcspi4_ick = {
+ .name = "mcspi4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
+@@ -1897,7 +1902,7 @@ static struct clk mcspi4_ick = {
+
+ static struct clk mcspi3_ick = {
+ .name = "mcspi3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
+@@ -1907,7 +1912,7 @@ static struct clk mcspi3_ick = {
+
+ static struct clk mcspi2_ick = {
+ .name = "mcspi2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
+@@ -1917,7 +1922,7 @@ static struct clk mcspi2_ick = {
+
+ static struct clk mcspi1_ick = {
+ .name = "mcspi1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
+@@ -1927,7 +1932,7 @@ static struct clk mcspi1_ick = {
+
+ static struct clk i2c3_ick = {
+ .name = "i2c3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_I2C3_SHIFT,
+@@ -1937,7 +1942,7 @@ static struct clk i2c3_ick = {
+
+ static struct clk i2c2_ick = {
+ .name = "i2c2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_I2C2_SHIFT,
+@@ -1947,7 +1952,7 @@ static struct clk i2c2_ick = {
+
+ static struct clk i2c1_ick = {
+ .name = "i2c1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_I2C1_SHIFT,
+@@ -1957,7 +1962,7 @@ static struct clk i2c1_ick = {
+
+ static struct clk uart2_ick = {
+ .name = "uart2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_UART2_SHIFT,
+@@ -1967,7 +1972,7 @@ static struct clk uart2_ick = {
+
+ static struct clk uart1_ick = {
+ .name = "uart1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_UART1_SHIFT,
+@@ -1977,7 +1982,7 @@ static struct clk uart1_ick = {
+
+ static struct clk gpt11_ick = {
+ .name = "gpt11_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_GPT11_SHIFT,
+@@ -1987,7 +1992,7 @@ static struct clk gpt11_ick = {
+
+ static struct clk gpt10_ick = {
+ .name = "gpt10_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_GPT10_SHIFT,
+@@ -1997,7 +2002,7 @@ static struct clk gpt10_ick = {
+
+ static struct clk mcbsp5_ick = {
+ .name = "mcbsp5_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
+@@ -2007,7 +2012,7 @@ static struct clk mcbsp5_ick = {
+
+ static struct clk mcbsp1_ick = {
+ .name = "mcbsp1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
+@@ -2017,7 +2022,7 @@ static struct clk mcbsp1_ick = {
+
+ static struct clk fac_ick = {
+ .name = "fac_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
+@@ -2027,7 +2032,7 @@ static struct clk fac_ick = {
+
+ static struct clk mailboxes_ick = {
+ .name = "mailboxes_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+@@ -2037,7 +2042,7 @@ static struct clk mailboxes_ick = {
+
+ static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
+@@ -2057,7 +2062,7 @@ static struct clk ssi_l4_ick = {
+
+ static struct clk ssi_ick_3430es1 = {
+ .name = "ssi_ick",
+- .ops = &clkops_omap2_dflt,
++ .ops = &clkops_omap2_iclk_dflt,
+ .parent = &ssi_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_SSI_SHIFT,
+@@ -2067,7 +2072,7 @@ static struct clk ssi_ick_3430es1 = {
+
+ static struct clk ssi_ick_3430es2 = {
+ .name = "ssi_ick",
+- .ops = &clkops_omap3430es2_ssi_wait,
++ .ops = &clkops_omap3430es2_iclk_ssi_wait,
+ .parent = &ssi_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_SSI_SHIFT,
+@@ -2085,7 +2090,7 @@ static const struct clksel usb_l4_clksel[] = {
+
+ static struct clk usb_l4_ick = {
+ .name = "usb_l4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ick,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+@@ -2107,7 +2112,7 @@ static struct clk security_l4_ick2 = {
+
+ static struct clk aes1_ick = {
+ .name = "aes1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &security_l4_ick2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_AES1_SHIFT,
+@@ -2116,7 +2121,7 @@ static struct clk aes1_ick = {
+
+ static struct clk rng_ick = {
+ .name = "rng_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &security_l4_ick2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_RNG_SHIFT,
+@@ -2125,7 +2130,7 @@ static struct clk rng_ick = {
+
+ static struct clk sha11_ick = {
+ .name = "sha11_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &security_l4_ick2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_SHA11_SHIFT,
+@@ -2134,7 +2139,7 @@ static struct clk sha11_ick = {
+
+ static struct clk des1_ick = {
+ .name = "des1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &security_l4_ick2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP3430_EN_DES1_SHIFT,
+@@ -2195,7 +2200,7 @@ static struct clk dss2_alwon_fck = {
+ static struct clk dss_ick_3430es1 = {
+ /* Handles both L3 and L4 clocks */
+ .name = "dss_ick",
+- .ops = &clkops_omap2_dflt,
++ .ops = &clkops_omap2_iclk_dflt,
+ .parent = &l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+@@ -2206,7 +2211,7 @@ static struct clk dss_ick_3430es1 = {
+ static struct clk dss_ick_3430es2 = {
+ /* Handles both L3 and L4 clocks */
+ .name = "dss_ick",
+- .ops = &clkops_omap3430es2_dss_usbhost_wait,
++ .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
+ .parent = &l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+@@ -2229,7 +2234,7 @@ static struct clk cam_mclk = {
+ static struct clk cam_ick = {
+ /* Handles both L3 and L4 clocks */
+ .name = "cam_ick",
+- .ops = &clkops_omap2_dflt,
++ .ops = &clkops_omap2_iclk_dflt,
+ .parent = &l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_CAM_SHIFT,
+@@ -2272,7 +2277,7 @@ static struct clk usbhost_48m_fck = {
+ static struct clk usbhost_ick = {
+ /* Handles both L3 and L4 clocks */
+ .name = "usbhost_ick",
+- .ops = &clkops_omap3430es2_dss_usbhost_wait,
++ .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
+ .parent = &l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
+@@ -2372,7 +2377,7 @@ static struct clk wkup_l4_ick = {
+ /* Never specifically named in the TRM, so we have to infer a likely name */
+ static struct clk usim_ick = {
+ .name = "usim_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
+@@ -2382,7 +2387,7 @@ static struct clk usim_ick = {
+
+ static struct clk wdt2_ick = {
+ .name = "wdt2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_WDT2_SHIFT,
+@@ -2392,7 +2397,7 @@ static struct clk wdt2_ick = {
+
+ static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_WDT1_SHIFT,
+@@ -2402,7 +2407,7 @@ static struct clk wdt1_ick = {
+
+ static struct clk gpio1_ick = {
+ .name = "gpio1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
+@@ -2412,7 +2417,7 @@ static struct clk gpio1_ick = {
+
+ static struct clk omap_32ksync_ick = {
+ .name = "omap_32ksync_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
+@@ -2423,7 +2428,7 @@ static struct clk omap_32ksync_ick = {
+ /* XXX This clock no longer exists in 3430 TRM rev F */
+ static struct clk gpt12_ick = {
+ .name = "gpt12_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT12_SHIFT,
+@@ -2433,7 +2438,7 @@ static struct clk gpt12_ick = {
+
+ static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &wkup_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT1_SHIFT,
+@@ -2663,7 +2668,7 @@ static struct clk per_l4_ick = {
+
+ static struct clk gpio6_ick = {
+ .name = "gpio6_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
+@@ -2673,7 +2678,7 @@ static struct clk gpio6_ick = {
+
+ static struct clk gpio5_ick = {
+ .name = "gpio5_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
+@@ -2683,7 +2688,7 @@ static struct clk gpio5_ick = {
+
+ static struct clk gpio4_ick = {
+ .name = "gpio4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
+@@ -2693,7 +2698,7 @@ static struct clk gpio4_ick = {
+
+ static struct clk gpio3_ick = {
+ .name = "gpio3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
+@@ -2703,7 +2708,7 @@ static struct clk gpio3_ick = {
+
+ static struct clk gpio2_ick = {
+ .name = "gpio2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
+@@ -2713,7 +2718,7 @@ static struct clk gpio2_ick = {
+
+ static struct clk wdt3_ick = {
+ .name = "wdt3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_WDT3_SHIFT,
+@@ -2723,7 +2728,7 @@ static struct clk wdt3_ick = {
+
+ static struct clk uart3_ick = {
+ .name = "uart3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_UART3_SHIFT,
+@@ -2733,7 +2738,7 @@ static struct clk uart3_ick = {
+
+ static struct clk uart4_ick = {
+ .name = "uart4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3630_EN_UART4_SHIFT,
+@@ -2743,7 +2748,7 @@ static struct clk uart4_ick = {
+
+ static struct clk gpt9_ick = {
+ .name = "gpt9_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT9_SHIFT,
+@@ -2753,7 +2758,7 @@ static struct clk gpt9_ick = {
+
+ static struct clk gpt8_ick = {
+ .name = "gpt8_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT8_SHIFT,
+@@ -2763,7 +2768,7 @@ static struct clk gpt8_ick = {
+
+ static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT7_SHIFT,
+@@ -2773,7 +2778,7 @@ static struct clk gpt7_ick = {
+
+ static struct clk gpt6_ick = {
+ .name = "gpt6_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT6_SHIFT,
+@@ -2783,7 +2788,7 @@ static struct clk gpt6_ick = {
+
+ static struct clk gpt5_ick = {
+ .name = "gpt5_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT5_SHIFT,
+@@ -2793,7 +2798,7 @@ static struct clk gpt5_ick = {
+
+ static struct clk gpt4_ick = {
+ .name = "gpt4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT4_SHIFT,
+@@ -2803,7 +2808,7 @@ static struct clk gpt4_ick = {
+
+ static struct clk gpt3_ick = {
+ .name = "gpt3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT3_SHIFT,
+@@ -2813,7 +2818,7 @@ static struct clk gpt3_ick = {
+
+ static struct clk gpt2_ick = {
+ .name = "gpt2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_GPT2_SHIFT,
+@@ -2823,7 +2828,7 @@ static struct clk gpt2_ick = {
+
+ static struct clk mcbsp2_ick = {
+ .name = "mcbsp2_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
+@@ -2833,7 +2838,7 @@ static struct clk mcbsp2_ick = {
+
+ static struct clk mcbsp3_ick = {
+ .name = "mcbsp3_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
+@@ -2843,7 +2848,7 @@ static struct clk mcbsp3_ick = {
+
+ static struct clk mcbsp4_ick = {
+ .name = "mcbsp4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
+@@ -3186,7 +3191,7 @@ static struct clk vpfe_fck = {
+ */
+ static struct clk uart4_ick_am35xx = {
+ .name = "uart4_ick",
+- .ops = &clkops_omap2_dflt_wait,
++ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = AM35XX_EN_UART4_SHIFT,
+--
+1.7.1
+
diff --git a/patches/for_next/0180-OMAP2-3-PM-remove-manual-CM_AUTOIDLE-bit-setting-in-.patch b/patches/for_next/0180-OMAP2-3-PM-remove-manual-CM_AUTOIDLE-bit-setting-in-.patch
new file mode 100644
index 0000000000000000000000000000000000000000..33ab9a969709ef1126e823553897b3a922a99260
--- /dev/null
+++ b/patches/for_next/0180-OMAP2-3-PM-remove-manual-CM_AUTOIDLE-bit-setting-in-.patch
@@ -0,0 +1,236 @@
+From 343d28ec653091073a66d78c142b528c2be76ea0 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:39:30 -0700
+Subject: [PATCH 180/254] OMAP2/3: PM: remove manual CM_AUTOIDLE bit setting in mach-omap2/pm*xx.c
+
+These CM_AUTOIDLE bits are now set by the clock code via the common PM
+code in mach-omap2/pm.c.
+
+N.B.: The pm24xx.c code that this patch removes didn't ensure that the
+CM_AUTOIDLE bits were set for several 2430-only modules, such as
+GPIO5, MDM_INTC, MMCHS1/2, the modem oscillator clock, and USBHS.
+Similarly, the pm34xx.c code that this patch removes didn't ensure
+that the CM_AUTOIDLE bits were set for USIM and the AM3517 UART4.
+Those cases should now be handled.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Tested-by: Rajendra Nayak <rnayak@ti.com>
+Reviewed-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/pm24xx.c | 63 ++-----------------------
+ arch/arm/mach-omap2/pm34xx.c | 105 +-----------------------------------------
+ 2 files changed, 5 insertions(+), 163 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
+index abe08f4..96907da 100644
+--- a/arch/arm/mach-omap2/pm24xx.c
++++ b/arch/arm/mach-omap2/pm24xx.c
+@@ -379,7 +379,10 @@ static void __init prcm_setup_regs(void)
+ int i, num_mem_banks;
+ struct powerdomain *pwrdm;
+
+- /* Enable autoidle */
++ /*
++ * Enable autoidle
++ * XXX This should be handled by hwmod code or PRCM init code
++ */
+ omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
+ OMAP2_PRCM_SYSCONFIG_OFFSET);
+
+@@ -418,64 +421,6 @@ static void __init prcm_setup_regs(void)
+ clkdm_for_each(clkdms_setup, NULL);
+ clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
+
+- /* Enable clock autoidle for all domains */
+- omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
+- OMAP24XX_AUTO_MAILBOXES_MASK |
+- OMAP24XX_AUTO_WDT4_MASK |
+- OMAP2420_AUTO_WDT3_MASK |
+- OMAP24XX_AUTO_MSPRO_MASK |
+- OMAP2420_AUTO_MMC_MASK |
+- OMAP24XX_AUTO_FAC_MASK |
+- OMAP2420_AUTO_EAC_MASK |
+- OMAP24XX_AUTO_HDQ_MASK |
+- OMAP24XX_AUTO_UART2_MASK |
+- OMAP24XX_AUTO_UART1_MASK |
+- OMAP24XX_AUTO_I2C2_MASK |
+- OMAP24XX_AUTO_I2C1_MASK |
+- OMAP24XX_AUTO_MCSPI2_MASK |
+- OMAP24XX_AUTO_MCSPI1_MASK |
+- OMAP24XX_AUTO_MCBSP2_MASK |
+- OMAP24XX_AUTO_MCBSP1_MASK |
+- OMAP24XX_AUTO_GPT12_MASK |
+- OMAP24XX_AUTO_GPT11_MASK |
+- OMAP24XX_AUTO_GPT10_MASK |
+- OMAP24XX_AUTO_GPT9_MASK |
+- OMAP24XX_AUTO_GPT8_MASK |
+- OMAP24XX_AUTO_GPT7_MASK |
+- OMAP24XX_AUTO_GPT6_MASK |
+- OMAP24XX_AUTO_GPT5_MASK |
+- OMAP24XX_AUTO_GPT4_MASK |
+- OMAP24XX_AUTO_GPT3_MASK |
+- OMAP24XX_AUTO_GPT2_MASK |
+- OMAP2420_AUTO_VLYNQ_MASK |
+- OMAP24XX_AUTO_DSS_MASK,
+- CORE_MOD, CM_AUTOIDLE1);
+- omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
+- OMAP24XX_AUTO_SSI_MASK |
+- OMAP24XX_AUTO_USB_MASK,
+- CORE_MOD, CM_AUTOIDLE2);
+- omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
+- OMAP24XX_AUTO_GPMC_MASK |
+- OMAP24XX_AUTO_SDMA_MASK,
+- CORE_MOD, CM_AUTOIDLE3);
+- omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
+- OMAP24XX_AUTO_AES_MASK |
+- OMAP24XX_AUTO_RNG_MASK |
+- OMAP24XX_AUTO_SHA_MASK |
+- OMAP24XX_AUTO_DES_MASK,
+- CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
+-
+- omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
+- CM_AUTOIDLE);
+-
+- omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
+- OMAP24XX_AUTO_WDT1_MASK |
+- OMAP24XX_AUTO_MPU_WDT_MASK |
+- OMAP24XX_AUTO_GPIOS_MASK |
+- OMAP24XX_AUTO_32KSYNC_MASK |
+- OMAP24XX_AUTO_GPT1_MASK,
+- WKUP_MOD, CM_AUTOIDLE);
+-
+ /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
+ * stabilisation */
+ omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index a99f296..3d6a00e 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
++++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -688,14 +688,11 @@ static void __init omap3_d2d_idle(void)
+
+ static void __init prcm_setup_regs(void)
+ {
+- u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
+- OMAP3630_AUTO_UART4_MASK : 0;
+ u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
+ OMAP3630_EN_UART4_MASK : 0;
+ u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
+ OMAP3630_GRPSEL_UART4_MASK : 0;
+
+-
+ /* XXX Reset all wkdeps. This should be done when initializing
+ * powerdomains */
+ omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+@@ -710,107 +707,7 @@ static void __init prcm_setup_regs(void)
+ } else
+ omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+
+- /*
+- * Enable interface clock autoidle for all modules.
+- * Note that in the long run this should be done by clockfw
+- */
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_MODEM_MASK |
+- OMAP3430ES2_AUTO_MMC3_MASK |
+- OMAP3430ES2_AUTO_ICR_MASK |
+- OMAP3430_AUTO_AES2_MASK |
+- OMAP3430_AUTO_SHA12_MASK |
+- OMAP3430_AUTO_DES2_MASK |
+- OMAP3430_AUTO_MMC2_MASK |
+- OMAP3430_AUTO_MMC1_MASK |
+- OMAP3430_AUTO_MSPRO_MASK |
+- OMAP3430_AUTO_HDQ_MASK |
+- OMAP3430_AUTO_MCSPI4_MASK |
+- OMAP3430_AUTO_MCSPI3_MASK |
+- OMAP3430_AUTO_MCSPI2_MASK |
+- OMAP3430_AUTO_MCSPI1_MASK |
+- OMAP3430_AUTO_I2C3_MASK |
+- OMAP3430_AUTO_I2C2_MASK |
+- OMAP3430_AUTO_I2C1_MASK |
+- OMAP3430_AUTO_UART2_MASK |
+- OMAP3430_AUTO_UART1_MASK |
+- OMAP3430_AUTO_GPT11_MASK |
+- OMAP3430_AUTO_GPT10_MASK |
+- OMAP3430_AUTO_MCBSP5_MASK |
+- OMAP3430_AUTO_MCBSP1_MASK |
+- OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
+- OMAP3430_AUTO_MAILBOXES_MASK |
+- OMAP3430_AUTO_OMAPCTRL_MASK |
+- OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
+- OMAP3430_AUTO_HSOTGUSB_MASK |
+- OMAP3430_AUTO_SAD2D_MASK |
+- OMAP3430_AUTO_SSI_MASK,
+- CORE_MOD, CM_AUTOIDLE1);
+-
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_PKA_MASK |
+- OMAP3430_AUTO_AES1_MASK |
+- OMAP3430_AUTO_RNG_MASK |
+- OMAP3430_AUTO_SHA11_MASK |
+- OMAP3430_AUTO_DES1_MASK,
+- CORE_MOD, CM_AUTOIDLE2);
+-
+- if (omap_rev() > OMAP3430_REV_ES1_0) {
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_MAD2D_MASK |
+- OMAP3430ES2_AUTO_USBTLL_MASK,
+- CORE_MOD, CM_AUTOIDLE3);
+- }
+-
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_WDT2_MASK |
+- OMAP3430_AUTO_WDT1_MASK |
+- OMAP3430_AUTO_GPIO1_MASK |
+- OMAP3430_AUTO_32KSYNC_MASK |
+- OMAP3430_AUTO_GPT12_MASK |
+- OMAP3430_AUTO_GPT1_MASK,
+- WKUP_MOD, CM_AUTOIDLE);
+-
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_DSS_MASK,
+- OMAP3430_DSS_MOD,
+- CM_AUTOIDLE);
+-
+- omap2_cm_write_mod_reg(
+- OMAP3430_AUTO_CAM_MASK,
+- OMAP3430_CAM_MOD,
+- CM_AUTOIDLE);
+-
+- omap2_cm_write_mod_reg(
+- omap3630_auto_uart4_mask |
+- OMAP3430_AUTO_GPIO6_MASK |
+- OMAP3430_AUTO_GPIO5_MASK |
+- OMAP3430_AUTO_GPIO4_MASK |
+- OMAP3430_AUTO_GPIO3_MASK |
+- OMAP3430_AUTO_GPIO2_MASK |
+- OMAP3430_AUTO_WDT3_MASK |
+- OMAP3430_AUTO_UART3_MASK |
+- OMAP3430_AUTO_GPT9_MASK |
+- OMAP3430_AUTO_GPT8_MASK |
+- OMAP3430_AUTO_GPT7_MASK |
+- OMAP3430_AUTO_GPT6_MASK |
+- OMAP3430_AUTO_GPT5_MASK |
+- OMAP3430_AUTO_GPT4_MASK |
+- OMAP3430_AUTO_GPT3_MASK |
+- OMAP3430_AUTO_GPT2_MASK |
+- OMAP3430_AUTO_MCBSP4_MASK |
+- OMAP3430_AUTO_MCBSP3_MASK |
+- OMAP3430_AUTO_MCBSP2_MASK,
+- OMAP3430_PER_MOD,
+- CM_AUTOIDLE);
+-
+- if (omap_rev() > OMAP3430_REV_ES1_0) {
+- omap2_cm_write_mod_reg(
+- OMAP3430ES2_AUTO_USBHOST_MASK,
+- OMAP3430ES2_USBHOST_MOD,
+- CM_AUTOIDLE);
+- }
+-
++ /* XXX This should be handled by hwmod code or SCM init code */
+ omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
+
+ /*
+--
+1.7.1
+
diff --git a/patches/for_next/0181-OMAP-smartreflex-move-plat-smartreflex.h-to-mach-oma.patch b/patches/for_next/0181-OMAP-smartreflex-move-plat-smartreflex.h-to-mach-oma.patch
new file mode 100644
index 0000000000000000000000000000000000000000..23ba71482632f40856417a2cf6ade5ee652c113a
--- /dev/null
+++ b/patches/for_next/0181-OMAP-smartreflex-move-plat-smartreflex.h-to-mach-oma.patch
@@ -0,0 +1,592 @@
+From 22a1dec1ec1cbd65118d030c3516c142db9cc0ee Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:54:33 -0700
+Subject: [PATCH 181/254] OMAP: smartreflex: move plat/smartreflex.h to mach-omap2/smartreflex.h
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no reason for this header file to be in
+plat-omap/include/plat/smartreflex.h. The hardware devices are in
+OMAP2+ SoCs only. Leaving this header file in plat-omap causes
+problems due to cross-dependencies with other header files that should
+live in mach-omap2/.
+
+Thanks to Benoît Cousson <b-cousson@ti.com> for suggesting the removal
+of the smartreflex.h include from the OMAP3xxx hwmod data.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 3 -
+ arch/arm/mach-omap2/smartreflex-class3.c | 2 +-
+ arch/arm/mach-omap2/smartreflex.c | 2 +-
+ arch/arm/mach-omap2/smartreflex.h | 245 +++++++++++++++++++++++++
+ arch/arm/mach-omap2/sr_device.c | 2 +-
+ arch/arm/plat-omap/include/plat/smartreflex.h | 245 -------------------------
+ 6 files changed, 248 insertions(+), 251 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/smartreflex.h
+ delete mode 100644 arch/arm/plat-omap/include/plat/smartreflex.h
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 05c8305..6d59698 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -22,9 +22,6 @@
+ #include <plat/l4_3xxx.h>
+ #include <plat/i2c.h>
+ #include <plat/gpio.h>
+-#include <plat/mmc.h>
+-#include <plat/smartreflex.h>
+-#include <plat/mcbsp.h>
+ #include <plat/mcspi.h>
+ #include <plat/dmtimer.h>
+
+diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
+index 60e7055..f438cf4 100644
+--- a/arch/arm/mach-omap2/smartreflex-class3.c
++++ b/arch/arm/mach-omap2/smartreflex-class3.c
+@@ -11,7 +11,7 @@
+ * published by the Free Software Foundation.
+ */
+
+-#include <plat/smartreflex.h>
++#include "smartreflex.h"
+
+ static int sr_class3_enable(struct voltagedomain *voltdm)
+ {
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index 1a777e3..81e23eb 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -26,9 +26,9 @@
+ #include <linux/pm_runtime.h>
+
+ #include <plat/common.h>
+-#include <plat/smartreflex.h>
+
+ #include "pm.h"
++#include "smartreflex.h"
+
+ #define SMARTREFLEX_NAME_LEN 16
+ #define NVALUE_NAME_LEN 40
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+new file mode 100644
+index 0000000..6568c88
+--- /dev/null
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -0,0 +1,245 @@
++/*
++ * OMAP Smartreflex Defines and Routines
++ *
++ * Author: Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2010 Texas Instruments, Inc.
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Kalle Jokiniemi
++ *
++ * Copyright (C) 2007 Texas Instruments, Inc.
++ * Lesly A M <x0080970@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
++#define __ASM_ARM_OMAP_SMARTREFLEX_H
++
++#include <linux/platform_device.h>
++#include <plat/voltage.h>
++
++/*
++ * Different Smartreflex IPs version. The v1 is the 65nm version used in
++ * OMAP3430. The v2 is the update for the 45nm version of the IP
++ * used in OMAP3630 and OMAP4430
++ */
++#define SR_TYPE_V1 1
++#define SR_TYPE_V2 2
++
++/* SMART REFLEX REG ADDRESS OFFSET */
++#define SRCONFIG 0x00
++#define SRSTATUS 0x04
++#define SENVAL 0x08
++#define SENMIN 0x0C
++#define SENMAX 0x10
++#define SENAVG 0x14
++#define AVGWEIGHT 0x18
++#define NVALUERECIPROCAL 0x1c
++#define SENERROR_V1 0x20
++#define ERRCONFIG_V1 0x24
++#define IRQ_EOI 0x20
++#define IRQSTATUS_RAW 0x24
++#define IRQSTATUS 0x28
++#define IRQENABLE_SET 0x2C
++#define IRQENABLE_CLR 0x30
++#define SENERROR_V2 0x34
++#define ERRCONFIG_V2 0x38
++
++/* Bit/Shift Positions */
++
++/* SRCONFIG */
++#define SRCONFIG_ACCUMDATA_SHIFT 22
++#define SRCONFIG_SRCLKLENGTH_SHIFT 12
++#define SRCONFIG_SENNENABLE_V1_SHIFT 5
++#define SRCONFIG_SENPENABLE_V1_SHIFT 3
++#define SRCONFIG_SENNENABLE_V2_SHIFT 1
++#define SRCONFIG_SENPENABLE_V2_SHIFT 0
++#define SRCONFIG_CLKCTRL_SHIFT 0
++
++#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22)
++
++#define SRCONFIG_SRENABLE BIT(11)
++#define SRCONFIG_SENENABLE BIT(10)
++#define SRCONFIG_ERRGEN_EN BIT(9)
++#define SRCONFIG_MINMAXAVG_EN BIT(8)
++#define SRCONFIG_DELAYCTRL BIT(2)
++
++/* AVGWEIGHT */
++#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2
++#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0
++
++/* NVALUERECIPROCAL */
++#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
++#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
++#define NVALUERECIPROCAL_RNSENP_SHIFT 8
++#define NVALUERECIPROCAL_RNSENN_SHIFT 0
++
++/* ERRCONFIG */
++#define ERRCONFIG_ERRWEIGHT_SHIFT 16
++#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
++#define ERRCONFIG_ERRMINLIMIT_SHIFT 0
++
++#define SR_ERRWEIGHT_MASK (0x07 << 16)
++#define SR_ERRMAXLIMIT_MASK (0xff << 8)
++#define SR_ERRMINLIMIT_MASK (0xff << 0)
++
++#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
++#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
++#define ERRCONFIG_MCUACCUMINTEN BIT(29)
++#define ERRCONFIG_MCUACCUMINTST BIT(28)
++#define ERRCONFIG_MCUVALIDINTEN BIT(27)
++#define ERRCONFIG_MCUVALIDINTST BIT(26)
++#define ERRCONFIG_MCUBOUNDINTEN BIT(25)
++#define ERRCONFIG_MCUBOUNDINTST BIT(24)
++#define ERRCONFIG_MCUDISACKINTEN BIT(23)
++#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23)
++#define ERRCONFIG_MCUDISACKINTST BIT(22)
++#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22)
++
++#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \
++ ERRCONFIG_MCUACCUMINTST | \
++ ERRCONFIG_MCUVALIDINTST | \
++ ERRCONFIG_MCUBOUNDINTST | \
++ ERRCONFIG_MCUDISACKINTST)
++/* IRQSTATUS */
++#define IRQSTATUS_MCUACCUMINT BIT(3)
++#define IRQSTATUS_MCVALIDINT BIT(2)
++#define IRQSTATUS_MCBOUNDSINT BIT(1)
++#define IRQSTATUS_MCUDISABLEACKINT BIT(0)
++
++/* IRQENABLE_SET and IRQENABLE_CLEAR */
++#define IRQENABLE_MCUACCUMINT BIT(3)
++#define IRQENABLE_MCUVALIDINT BIT(2)
++#define IRQENABLE_MCUBOUNDSINT BIT(1)
++#define IRQENABLE_MCUDISABLEACKINT BIT(0)
++
++/* Common Bit values */
++
++#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c
++#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
++#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
++#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
++#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
++
++/*
++ * 3430 specific values. Maybe these should be passed from board file or
++ * pmic structures.
++ */
++#define OMAP3430_SR_ACCUMDATA 0x1f4
++
++#define OMAP3430_SR1_SENPAVGWEIGHT 0x03
++#define OMAP3430_SR1_SENNAVGWEIGHT 0x03
++
++#define OMAP3430_SR2_SENPAVGWEIGHT 0x01
++#define OMAP3430_SR2_SENNAVGWEIGHT 0x01
++
++#define OMAP3430_SR_ERRWEIGHT 0x04
++#define OMAP3430_SR_ERRMAXLIMIT 0x02
++
++/**
++ * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
++ * pmic specific info to smartreflex driver
++ *
++ * @sr_pmic_init: API to initialize smartreflex on the PMIC side.
++ */
++struct omap_sr_pmic_data {
++ void (*sr_pmic_init) (void);
++};
++
++#ifdef CONFIG_OMAP_SMARTREFLEX
++/*
++ * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
++ * The smartreflex class driver should pass the class type.
++ * Should be used to populate the class_type field of the
++ * omap_smartreflex_class_data structure.
++ */
++#define SR_CLASS1 0x1
++#define SR_CLASS2 0x2
++#define SR_CLASS3 0x3
++
++/**
++ * struct omap_sr_class_data - Smartreflex class driver info
++ *
++ * @enable: API to enable a particular class smaartreflex.
++ * @disable: API to disable a particular class smartreflex.
++ * @configure: API to configure a particular class smartreflex.
++ * @notify: API to notify the class driver about an event in SR.
++ * Not needed for class3.
++ * @notify_flags: specify the events to be notified to the class driver
++ * @class_type: specify which smartreflex class.
++ * Can be used by the SR driver to take any class
++ * based decisions.
++ */
++struct omap_sr_class_data {
++ int (*enable)(struct voltagedomain *voltdm);
++ int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
++ int (*configure)(struct voltagedomain *voltdm);
++ int (*notify)(struct voltagedomain *voltdm, u32 status);
++ u8 notify_flags;
++ u8 class_type;
++};
++
++/**
++ * struct omap_sr_nvalue_table - Smartreflex n-target value info
++ *
++ * @efuse_offs: The offset of the efuse where n-target values are stored.
++ * @nvalue: The n-target value.
++ */
++struct omap_sr_nvalue_table {
++ u32 efuse_offs;
++ u32 nvalue;
++};
++
++/**
++ * struct omap_sr_data - Smartreflex platform data.
++ *
++ * @ip_type: Smartreflex IP type.
++ * @senp_mod: SENPENABLE value for the sr
++ * @senn_mod: SENNENABLE value for sr
++ * @nvalue_count: Number of distinct nvalues in the nvalue table
++ * @enable_on_init: whether this sr module needs to enabled at
++ * boot up or not.
++ * @nvalue_table: table containing the efuse offsets and nvalues
++ * corresponding to them.
++ * @voltdm: Pointer to the voltage domain associated with the SR
++ */
++struct omap_sr_data {
++ int ip_type;
++ u32 senp_mod;
++ u32 senn_mod;
++ int nvalue_count;
++ bool enable_on_init;
++ struct omap_sr_nvalue_table *nvalue_table;
++ struct voltagedomain *voltdm;
++};
++
++/* Smartreflex module enable/disable interface */
++void omap_sr_enable(struct voltagedomain *voltdm);
++void omap_sr_disable(struct voltagedomain *voltdm);
++void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
++
++/* API to register the pmic specific data with the smartreflex driver. */
++void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
++
++/* Smartreflex driver hooks to be called from Smartreflex class driver */
++int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
++void sr_disable(struct voltagedomain *voltdm);
++int sr_configure_errgen(struct voltagedomain *voltdm);
++int sr_configure_minmax(struct voltagedomain *voltdm);
++
++/* API to register the smartreflex class driver with the smartreflex driver */
++int sr_register_class(struct omap_sr_class_data *class_data);
++#else
++static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
++static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
++static inline void omap_sr_disable_reset_volt(
++ struct voltagedomain *voltdm) {}
++static inline void omap_sr_register_pmic(
++ struct omap_sr_pmic_data *pmic_data) {}
++#endif
++#endif
+diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
+index b1e0af1..a636604 100644
+--- a/arch/arm/mach-omap2/sr_device.c
++++ b/arch/arm/mach-omap2/sr_device.c
+@@ -23,9 +23,9 @@
+ #include <linux/io.h>
+
+ #include <plat/omap_device.h>
+-#include <plat/smartreflex.h>
+ #include <plat/voltage.h>
+
++#include "smartreflex.h"
+ #include "control.h"
+ #include "pm.h"
+
+diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
+deleted file mode 100644
+index 6568c88..0000000
+--- a/arch/arm/plat-omap/include/plat/smartreflex.h
++++ /dev/null
+@@ -1,245 +0,0 @@
+-/*
+- * OMAP Smartreflex Defines and Routines
+- *
+- * Author: Thara Gopinath <thara@ti.com>
+- *
+- * Copyright (C) 2010 Texas Instruments, Inc.
+- * Thara Gopinath <thara@ti.com>
+- *
+- * Copyright (C) 2008 Nokia Corporation
+- * Kalle Jokiniemi
+- *
+- * Copyright (C) 2007 Texas Instruments, Inc.
+- * Lesly A M <x0080970@ti.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
+-#define __ASM_ARM_OMAP_SMARTREFLEX_H
+-
+-#include <linux/platform_device.h>
+-#include <plat/voltage.h>
+-
+-/*
+- * Different Smartreflex IPs version. The v1 is the 65nm version used in
+- * OMAP3430. The v2 is the update for the 45nm version of the IP
+- * used in OMAP3630 and OMAP4430
+- */
+-#define SR_TYPE_V1 1
+-#define SR_TYPE_V2 2
+-
+-/* SMART REFLEX REG ADDRESS OFFSET */
+-#define SRCONFIG 0x00
+-#define SRSTATUS 0x04
+-#define SENVAL 0x08
+-#define SENMIN 0x0C
+-#define SENMAX 0x10
+-#define SENAVG 0x14
+-#define AVGWEIGHT 0x18
+-#define NVALUERECIPROCAL 0x1c
+-#define SENERROR_V1 0x20
+-#define ERRCONFIG_V1 0x24
+-#define IRQ_EOI 0x20
+-#define IRQSTATUS_RAW 0x24
+-#define IRQSTATUS 0x28
+-#define IRQENABLE_SET 0x2C
+-#define IRQENABLE_CLR 0x30
+-#define SENERROR_V2 0x34
+-#define ERRCONFIG_V2 0x38
+-
+-/* Bit/Shift Positions */
+-
+-/* SRCONFIG */
+-#define SRCONFIG_ACCUMDATA_SHIFT 22
+-#define SRCONFIG_SRCLKLENGTH_SHIFT 12
+-#define SRCONFIG_SENNENABLE_V1_SHIFT 5
+-#define SRCONFIG_SENPENABLE_V1_SHIFT 3
+-#define SRCONFIG_SENNENABLE_V2_SHIFT 1
+-#define SRCONFIG_SENPENABLE_V2_SHIFT 0
+-#define SRCONFIG_CLKCTRL_SHIFT 0
+-
+-#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22)
+-
+-#define SRCONFIG_SRENABLE BIT(11)
+-#define SRCONFIG_SENENABLE BIT(10)
+-#define SRCONFIG_ERRGEN_EN BIT(9)
+-#define SRCONFIG_MINMAXAVG_EN BIT(8)
+-#define SRCONFIG_DELAYCTRL BIT(2)
+-
+-/* AVGWEIGHT */
+-#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2
+-#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0
+-
+-/* NVALUERECIPROCAL */
+-#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
+-#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
+-#define NVALUERECIPROCAL_RNSENP_SHIFT 8
+-#define NVALUERECIPROCAL_RNSENN_SHIFT 0
+-
+-/* ERRCONFIG */
+-#define ERRCONFIG_ERRWEIGHT_SHIFT 16
+-#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
+-#define ERRCONFIG_ERRMINLIMIT_SHIFT 0
+-
+-#define SR_ERRWEIGHT_MASK (0x07 << 16)
+-#define SR_ERRMAXLIMIT_MASK (0xff << 8)
+-#define SR_ERRMINLIMIT_MASK (0xff << 0)
+-
+-#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
+-#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
+-#define ERRCONFIG_MCUACCUMINTEN BIT(29)
+-#define ERRCONFIG_MCUACCUMINTST BIT(28)
+-#define ERRCONFIG_MCUVALIDINTEN BIT(27)
+-#define ERRCONFIG_MCUVALIDINTST BIT(26)
+-#define ERRCONFIG_MCUBOUNDINTEN BIT(25)
+-#define ERRCONFIG_MCUBOUNDINTST BIT(24)
+-#define ERRCONFIG_MCUDISACKINTEN BIT(23)
+-#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23)
+-#define ERRCONFIG_MCUDISACKINTST BIT(22)
+-#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22)
+-
+-#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \
+- ERRCONFIG_MCUACCUMINTST | \
+- ERRCONFIG_MCUVALIDINTST | \
+- ERRCONFIG_MCUBOUNDINTST | \
+- ERRCONFIG_MCUDISACKINTST)
+-/* IRQSTATUS */
+-#define IRQSTATUS_MCUACCUMINT BIT(3)
+-#define IRQSTATUS_MCVALIDINT BIT(2)
+-#define IRQSTATUS_MCBOUNDSINT BIT(1)
+-#define IRQSTATUS_MCUDISABLEACKINT BIT(0)
+-
+-/* IRQENABLE_SET and IRQENABLE_CLEAR */
+-#define IRQENABLE_MCUACCUMINT BIT(3)
+-#define IRQENABLE_MCUVALIDINT BIT(2)
+-#define IRQENABLE_MCUBOUNDSINT BIT(1)
+-#define IRQENABLE_MCUDISABLEACKINT BIT(0)
+-
+-/* Common Bit values */
+-
+-#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c
+-#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
+-#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
+-#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
+-#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
+-
+-/*
+- * 3430 specific values. Maybe these should be passed from board file or
+- * pmic structures.
+- */
+-#define OMAP3430_SR_ACCUMDATA 0x1f4
+-
+-#define OMAP3430_SR1_SENPAVGWEIGHT 0x03
+-#define OMAP3430_SR1_SENNAVGWEIGHT 0x03
+-
+-#define OMAP3430_SR2_SENPAVGWEIGHT 0x01
+-#define OMAP3430_SR2_SENNAVGWEIGHT 0x01
+-
+-#define OMAP3430_SR_ERRWEIGHT 0x04
+-#define OMAP3430_SR_ERRMAXLIMIT 0x02
+-
+-/**
+- * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
+- * pmic specific info to smartreflex driver
+- *
+- * @sr_pmic_init: API to initialize smartreflex on the PMIC side.
+- */
+-struct omap_sr_pmic_data {
+- void (*sr_pmic_init) (void);
+-};
+-
+-#ifdef CONFIG_OMAP_SMARTREFLEX
+-/*
+- * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
+- * The smartreflex class driver should pass the class type.
+- * Should be used to populate the class_type field of the
+- * omap_smartreflex_class_data structure.
+- */
+-#define SR_CLASS1 0x1
+-#define SR_CLASS2 0x2
+-#define SR_CLASS3 0x3
+-
+-/**
+- * struct omap_sr_class_data - Smartreflex class driver info
+- *
+- * @enable: API to enable a particular class smaartreflex.
+- * @disable: API to disable a particular class smartreflex.
+- * @configure: API to configure a particular class smartreflex.
+- * @notify: API to notify the class driver about an event in SR.
+- * Not needed for class3.
+- * @notify_flags: specify the events to be notified to the class driver
+- * @class_type: specify which smartreflex class.
+- * Can be used by the SR driver to take any class
+- * based decisions.
+- */
+-struct omap_sr_class_data {
+- int (*enable)(struct voltagedomain *voltdm);
+- int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+- int (*configure)(struct voltagedomain *voltdm);
+- int (*notify)(struct voltagedomain *voltdm, u32 status);
+- u8 notify_flags;
+- u8 class_type;
+-};
+-
+-/**
+- * struct omap_sr_nvalue_table - Smartreflex n-target value info
+- *
+- * @efuse_offs: The offset of the efuse where n-target values are stored.
+- * @nvalue: The n-target value.
+- */
+-struct omap_sr_nvalue_table {
+- u32 efuse_offs;
+- u32 nvalue;
+-};
+-
+-/**
+- * struct omap_sr_data - Smartreflex platform data.
+- *
+- * @ip_type: Smartreflex IP type.
+- * @senp_mod: SENPENABLE value for the sr
+- * @senn_mod: SENNENABLE value for sr
+- * @nvalue_count: Number of distinct nvalues in the nvalue table
+- * @enable_on_init: whether this sr module needs to enabled at
+- * boot up or not.
+- * @nvalue_table: table containing the efuse offsets and nvalues
+- * corresponding to them.
+- * @voltdm: Pointer to the voltage domain associated with the SR
+- */
+-struct omap_sr_data {
+- int ip_type;
+- u32 senp_mod;
+- u32 senn_mod;
+- int nvalue_count;
+- bool enable_on_init;
+- struct omap_sr_nvalue_table *nvalue_table;
+- struct voltagedomain *voltdm;
+-};
+-
+-/* Smartreflex module enable/disable interface */
+-void omap_sr_enable(struct voltagedomain *voltdm);
+-void omap_sr_disable(struct voltagedomain *voltdm);
+-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+-
+-/* API to register the pmic specific data with the smartreflex driver. */
+-void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
+-
+-/* Smartreflex driver hooks to be called from Smartreflex class driver */
+-int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+-void sr_disable(struct voltagedomain *voltdm);
+-int sr_configure_errgen(struct voltagedomain *voltdm);
+-int sr_configure_minmax(struct voltagedomain *voltdm);
+-
+-/* API to register the smartreflex class driver with the smartreflex driver */
+-int sr_register_class(struct omap_sr_class_data *class_data);
+-#else
+-static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+-static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+-static inline void omap_sr_disable_reset_volt(
+- struct voltagedomain *voltdm) {}
+-static inline void omap_sr_register_pmic(
+- struct omap_sr_pmic_data *pmic_data) {}
+-#endif
+-#endif
+--
+1.7.1
+
diff --git a/patches/for_next/0182-OMAP-voltage-move-plat-voltage.h-to-mach-omap2-volta.patch b/patches/for_next/0182-OMAP-voltage-move-plat-voltage.h-to-mach-omap2-volta.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d5dfb7a9b4718fab625cd8b0fa44067bd3ee3d40
--- /dev/null
+++ b/patches/for_next/0182-OMAP-voltage-move-plat-voltage.h-to-mach-omap2-volta.patch
@@ -0,0 +1,437 @@
+From e3a9cd399f6a966c11d2b95f9309766c20579d7d Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:54:33 -0700
+Subject: [PATCH 182/254] OMAP: voltage: move plat/voltage.h to mach-omap2/voltage.h
+
+At this point in time, there's no reason for this header file to be in
+plat-omap/include/plat/voltage.h. It should not be included by device
+drivers, and the code that uses it is currently all under mach-omap2/.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_twl.c | 2 +-
+ arch/arm/mach-omap2/pm.c | 2 +-
+ arch/arm/mach-omap2/smartreflex.h | 3 +-
+ arch/arm/mach-omap2/sr_device.c | 2 +-
+ arch/arm/mach-omap2/voltage.c | 3 +-
+ arch/arm/mach-omap2/voltage.h | 155 ++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 -
+ arch/arm/plat-omap/include/plat/voltage.h | 155 --------------------------
+ 8 files changed, 162 insertions(+), 161 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/voltage.h
+ delete mode 100644 arch/arm/plat-omap/include/plat/voltage.h
+
+diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
+index 00e1d2b..ad8c18a 100644
+--- a/arch/arm/mach-omap2/omap_twl.c
++++ b/arch/arm/mach-omap2/omap_twl.c
+@@ -18,7 +18,7 @@
+ #include <linux/kernel.h>
+ #include <linux/i2c/twl.h>
+
+-#include <plat/voltage.h>
++#include "voltage.h"
+
+ #include "pm.h"
+
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index 7bb64d8..2c3a253 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -18,8 +18,8 @@
+ #include <plat/omap-pm.h>
+ #include <plat/omap_device.h>
+ #include <plat/common.h>
+-#include <plat/voltage.h>
+
++#include "voltage.h"
+ #include "powerdomain.h"
+ #include "clockdomain.h"
+ #include "pm.h"
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 6568c88..5f35b9e 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -21,7 +21,8 @@
+ #define __ASM_ARM_OMAP_SMARTREFLEX_H
+
+ #include <linux/platform_device.h>
+-#include <plat/voltage.h>
++
++#include "voltage.h"
+
+ /*
+ * Different Smartreflex IPs version. The v1 is the 65nm version used in
+diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
+index a636604..10d3c5e 100644
+--- a/arch/arm/mach-omap2/sr_device.c
++++ b/arch/arm/mach-omap2/sr_device.c
+@@ -23,9 +23,9 @@
+ #include <linux/io.h>
+
+ #include <plat/omap_device.h>
+-#include <plat/voltage.h>
+
+ #include "smartreflex.h"
++#include "voltage.h"
+ #include "control.h"
+ #include "pm.h"
+
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 12be525..3c9bcdc 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -26,7 +26,6 @@
+ #include <linux/slab.h>
+
+ #include <plat/common.h>
+-#include <plat/voltage.h>
+
+ #include "prm-regbits-34xx.h"
+ #include "prm-regbits-44xx.h"
+@@ -35,6 +34,8 @@
+ #include "prminst44xx.h"
+ #include "control.h"
+
++#include "voltage.h"
++
+ #define VP_IDLE_TIMEOUT 200
+ #define VP_TRANXDONE_TIMEOUT 300
+ #define VOLTAGE_DIR_SIZE 16
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+new file mode 100644
+index 0000000..5bd204e
+--- /dev/null
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -0,0 +1,155 @@
++/*
++ * OMAP Voltage Management Routines
++ *
++ * Author: Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2009 Texas Instruments, Inc.
++ * Thara Gopinath <thara@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
++#define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
++
++#include <linux/err.h>
++
++#define VOLTSCALE_VPFORCEUPDATE 1
++#define VOLTSCALE_VCBYPASS 2
++
++/*
++ * OMAP3 GENERIC setup times. Revisit to see if these needs to be
++ * passed from board or PMIC file
++ */
++#define OMAP3_CLKSETUP 0xff
++#define OMAP3_VOLTOFFSET 0xff
++#define OMAP3_VOLTSETUP2 0xff
++
++/* Voltage value defines */
++#define OMAP3430_VDD_MPU_OPP1_UV 975000
++#define OMAP3430_VDD_MPU_OPP2_UV 1075000
++#define OMAP3430_VDD_MPU_OPP3_UV 1200000
++#define OMAP3430_VDD_MPU_OPP4_UV 1270000
++#define OMAP3430_VDD_MPU_OPP5_UV 1350000
++
++#define OMAP3430_VDD_CORE_OPP1_UV 975000
++#define OMAP3430_VDD_CORE_OPP2_UV 1050000
++#define OMAP3430_VDD_CORE_OPP3_UV 1150000
++
++#define OMAP3630_VDD_MPU_OPP50_UV 1012500
++#define OMAP3630_VDD_MPU_OPP100_UV 1200000
++#define OMAP3630_VDD_MPU_OPP120_UV 1325000
++#define OMAP3630_VDD_MPU_OPP1G_UV 1375000
++
++#define OMAP3630_VDD_CORE_OPP50_UV 1000000
++#define OMAP3630_VDD_CORE_OPP100_UV 1200000
++
++#define OMAP4430_VDD_MPU_OPP50_UV 930000
++#define OMAP4430_VDD_MPU_OPP100_UV 1100000
++#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000
++#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000
++
++#define OMAP4430_VDD_IVA_OPP50_UV 930000
++#define OMAP4430_VDD_IVA_OPP100_UV 1100000
++#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000
++
++#define OMAP4430_VDD_CORE_OPP50_UV 930000
++#define OMAP4430_VDD_CORE_OPP100_UV 1100000
++
++/**
++ * struct voltagedomain - omap voltage domain global structure.
++ * @name: Name of the voltage domain which can be used as a unique
++ * identifier.
++ */
++struct voltagedomain {
++ char *name;
++};
++
++/**
++ * struct omap_volt_data - Omap voltage specific data.
++ * @voltage_nominal: The possible voltage value in uV
++ * @sr_efuse_offs: The offset of the efuse register(from system
++ * control module base address) from where to read
++ * the n-target value for the smartreflex module.
++ * @sr_errminlimit: Error min limit value for smartreflex. This value
++ * differs at differnet opp and thus is linked
++ * with voltage.
++ * @vp_errorgain: Error gain value for the voltage processor. This
++ * field also differs according to the voltage/opp.
++ */
++struct omap_volt_data {
++ u32 volt_nominal;
++ u32 sr_efuse_offs;
++ u8 sr_errminlimit;
++ u8 vp_errgain;
++};
++
++/**
++ * struct omap_volt_pmic_info - PMIC specific data required by voltage driver.
++ * @slew_rate: PMIC slew rate (in uv/us)
++ * @step_size: PMIC voltage step size (in uv)
++ * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
++ * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
++ */
++struct omap_volt_pmic_info {
++ int slew_rate;
++ int step_size;
++ u32 on_volt;
++ u32 onlp_volt;
++ u32 ret_volt;
++ u32 off_volt;
++ u16 volt_setup_time;
++ u8 vp_erroroffset;
++ u8 vp_vstepmin;
++ u8 vp_vstepmax;
++ u8 vp_vddmin;
++ u8 vp_vddmax;
++ u8 vp_timeout_us;
++ u8 i2c_slave_addr;
++ u8 pmic_reg;
++ unsigned long (*vsel_to_uv) (const u8 vsel);
++ u8 (*uv_to_vsel) (unsigned long uV);
++};
++
++unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
++void omap_vp_enable(struct voltagedomain *voltdm);
++void omap_vp_disable(struct voltagedomain *voltdm);
++int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
++ unsigned long target_volt);
++void omap_voltage_reset(struct voltagedomain *voltdm);
++void omap_voltage_get_volttable(struct voltagedomain *voltdm,
++ struct omap_volt_data **volt_data);
++struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
++ unsigned long volt);
++unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
++struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
++#ifdef CONFIG_PM
++int omap_voltage_register_pmic(struct voltagedomain *voltdm,
++ struct omap_volt_pmic_info *pmic_info);
++void omap_change_voltscale_method(struct voltagedomain *voltdm,
++ int voltscale_method);
++/* API to get the voltagedomain pointer */
++struct voltagedomain *omap_voltage_domain_lookup(char *name);
++
++int omap_voltage_late_init(void);
++#else
++static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
++ struct omap_volt_pmic_info *pmic_info)
++{
++ return -EINVAL;
++}
++static inline void omap_change_voltscale_method(struct voltagedomain *voltdm,
++ int voltscale_method) {}
++static inline int omap_voltage_late_init(void)
++{
++ return -EINVAL;
++}
++static inline struct voltagedomain *omap_voltage_domain_lookup(char *name)
++{
++ return ERR_PTR(-EINVAL);
++}
++#endif
++
++#endif
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 97aa8e7..59349c2 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -35,7 +35,6 @@
+ #include <linux/ioport.h>
+ #include <linux/spinlock.h>
+ #include <plat/cpu.h>
+-#include <plat/voltage.h>
+
+ struct omap_device;
+
+diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
+deleted file mode 100644
+index 5bd204e..0000000
+--- a/arch/arm/plat-omap/include/plat/voltage.h
++++ /dev/null
+@@ -1,155 +0,0 @@
+-/*
+- * OMAP Voltage Management Routines
+- *
+- * Author: Thara Gopinath <thara@ti.com>
+- *
+- * Copyright (C) 2009 Texas Instruments, Inc.
+- * Thara Gopinath <thara@ti.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
+-#define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
+-
+-#include <linux/err.h>
+-
+-#define VOLTSCALE_VPFORCEUPDATE 1
+-#define VOLTSCALE_VCBYPASS 2
+-
+-/*
+- * OMAP3 GENERIC setup times. Revisit to see if these needs to be
+- * passed from board or PMIC file
+- */
+-#define OMAP3_CLKSETUP 0xff
+-#define OMAP3_VOLTOFFSET 0xff
+-#define OMAP3_VOLTSETUP2 0xff
+-
+-/* Voltage value defines */
+-#define OMAP3430_VDD_MPU_OPP1_UV 975000
+-#define OMAP3430_VDD_MPU_OPP2_UV 1075000
+-#define OMAP3430_VDD_MPU_OPP3_UV 1200000
+-#define OMAP3430_VDD_MPU_OPP4_UV 1270000
+-#define OMAP3430_VDD_MPU_OPP5_UV 1350000
+-
+-#define OMAP3430_VDD_CORE_OPP1_UV 975000
+-#define OMAP3430_VDD_CORE_OPP2_UV 1050000
+-#define OMAP3430_VDD_CORE_OPP3_UV 1150000
+-
+-#define OMAP3630_VDD_MPU_OPP50_UV 1012500
+-#define OMAP3630_VDD_MPU_OPP100_UV 1200000
+-#define OMAP3630_VDD_MPU_OPP120_UV 1325000
+-#define OMAP3630_VDD_MPU_OPP1G_UV 1375000
+-
+-#define OMAP3630_VDD_CORE_OPP50_UV 1000000
+-#define OMAP3630_VDD_CORE_OPP100_UV 1200000
+-
+-#define OMAP4430_VDD_MPU_OPP50_UV 930000
+-#define OMAP4430_VDD_MPU_OPP100_UV 1100000
+-#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000
+-#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000
+-
+-#define OMAP4430_VDD_IVA_OPP50_UV 930000
+-#define OMAP4430_VDD_IVA_OPP100_UV 1100000
+-#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000
+-
+-#define OMAP4430_VDD_CORE_OPP50_UV 930000
+-#define OMAP4430_VDD_CORE_OPP100_UV 1100000
+-
+-/**
+- * struct voltagedomain - omap voltage domain global structure.
+- * @name: Name of the voltage domain which can be used as a unique
+- * identifier.
+- */
+-struct voltagedomain {
+- char *name;
+-};
+-
+-/**
+- * struct omap_volt_data - Omap voltage specific data.
+- * @voltage_nominal: The possible voltage value in uV
+- * @sr_efuse_offs: The offset of the efuse register(from system
+- * control module base address) from where to read
+- * the n-target value for the smartreflex module.
+- * @sr_errminlimit: Error min limit value for smartreflex. This value
+- * differs at differnet opp and thus is linked
+- * with voltage.
+- * @vp_errorgain: Error gain value for the voltage processor. This
+- * field also differs according to the voltage/opp.
+- */
+-struct omap_volt_data {
+- u32 volt_nominal;
+- u32 sr_efuse_offs;
+- u8 sr_errminlimit;
+- u8 vp_errgain;
+-};
+-
+-/**
+- * struct omap_volt_pmic_info - PMIC specific data required by voltage driver.
+- * @slew_rate: PMIC slew rate (in uv/us)
+- * @step_size: PMIC voltage step size (in uv)
+- * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
+- * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
+- */
+-struct omap_volt_pmic_info {
+- int slew_rate;
+- int step_size;
+- u32 on_volt;
+- u32 onlp_volt;
+- u32 ret_volt;
+- u32 off_volt;
+- u16 volt_setup_time;
+- u8 vp_erroroffset;
+- u8 vp_vstepmin;
+- u8 vp_vstepmax;
+- u8 vp_vddmin;
+- u8 vp_vddmax;
+- u8 vp_timeout_us;
+- u8 i2c_slave_addr;
+- u8 pmic_reg;
+- unsigned long (*vsel_to_uv) (const u8 vsel);
+- u8 (*uv_to_vsel) (unsigned long uV);
+-};
+-
+-unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
+-void omap_vp_enable(struct voltagedomain *voltdm);
+-void omap_vp_disable(struct voltagedomain *voltdm);
+-int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+- unsigned long target_volt);
+-void omap_voltage_reset(struct voltagedomain *voltdm);
+-void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+- struct omap_volt_data **volt_data);
+-struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+- unsigned long volt);
+-unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+-struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
+-#ifdef CONFIG_PM
+-int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+- struct omap_volt_pmic_info *pmic_info);
+-void omap_change_voltscale_method(struct voltagedomain *voltdm,
+- int voltscale_method);
+-/* API to get the voltagedomain pointer */
+-struct voltagedomain *omap_voltage_domain_lookup(char *name);
+-
+-int omap_voltage_late_init(void);
+-#else
+-static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+- struct omap_volt_pmic_info *pmic_info)
+-{
+- return -EINVAL;
+-}
+-static inline void omap_change_voltscale_method(struct voltagedomain *voltdm,
+- int voltscale_method) {}
+-static inline int omap_voltage_late_init(void)
+-{
+- return -EINVAL;
+-}
+-static inline struct voltagedomain *omap_voltage_domain_lookup(char *name)
+-{
+- return ERR_PTR(-EINVAL);
+-}
+-#endif
+-
+-#endif
+--
+1.7.1
+
diff --git a/patches/for_next/0183-OMAP2xxx-clock-fix-parents-for-L3-derived-clocks.patch b/patches/for_next/0183-OMAP2xxx-clock-fix-parents-for-L3-derived-clocks.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2a1c68149b63a6dfa83778ca9761607d497907c6
--- /dev/null
+++ b/patches/for_next/0183-OMAP2xxx-clock-fix-parents-for-L3-derived-clocks.patch
@@ -0,0 +1,55 @@
+From 0f49e071d165df147c494a4643d7342294084d6d Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:51:02 -0700
+Subject: [PATCH 183/254] OMAP2xxx: clock: fix parents for L3-derived clocks
+
+Several clocks are listed as having the core L4 clock as their parent,
+when they are actually derived from the L3 clock. Fix these.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock2420_data.c | 2 +-
+ arch/arm/mach-omap2/clock2430_data.c | 6 +++---
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 68c0369..693a0a8 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -1614,7 +1614,7 @@ static struct clk sdma_fck = {
+ static struct clk sdma_ick = {
+ .name = "sdma_ick",
+ .ops = &clkops_omap2_iclk_idle_only,
+- .parent = &l4_ck,
++ .parent = &core_l3_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 2aea882..799ccdf 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -1652,7 +1652,7 @@ static struct clk sdma_fck = {
+ static struct clk sdma_ick = {
+ .name = "sdma_ick",
+ .ops = &clkops_omap2_iclk_idle_only,
+- .parent = &l4_ck,
++ .parent = &core_l3_ck,
+ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
+@@ -1662,9 +1662,9 @@ static struct clk sdma_ick = {
+ static struct clk sdrc_ick = {
+ .name = "sdrc_ick",
+ .ops = &clkops_omap2_iclk_idle_only,
+- .parent = &l4_ck,
++ .parent = &core_l3_ck,
+ .flags = ENABLE_ON_INIT,
+- .clkdm_name = "core_l4_clkdm",
++ .clkdm_name = "core_l3_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+ .enable_bit = OMAP2430_EN_SDRC_SHIFT,
+ .recalc = &followparent_recalc,
+--
+1.7.1
+
diff --git a/patches/for_next/0184-OMAP2xxx-clock-fix-low-frequency-oscillator-clock-ra.patch b/patches/for_next/0184-OMAP2xxx-clock-fix-low-frequency-oscillator-clock-ra.patch
new file mode 100644
index 0000000000000000000000000000000000000000..69777a5642d503bc3ca35a7e5986468822e677e7
--- /dev/null
+++ b/patches/for_next/0184-OMAP2xxx-clock-fix-low-frequency-oscillator-clock-ra.patch
@@ -0,0 +1,52 @@
+From ce7c2c57e8f2d8a9b986cba9226f2c29af98af85 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 16 Feb 2011 15:38:38 -0700
+Subject: [PATCH 184/254] OMAP2xxx: clock: fix low-frequency oscillator clock rate
+
+The OMAP2420/2430 external 32-kHz low-frequency oscillator is a 32768
+Hz oscillator, not a 32,000 Hz oscillator[1][2]. Fix this in the clock
+tree.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+
+1. OMAP2420/22 Multimedia Processor Data Manual, Version P [SWPS019P],
+ section 5.1.4 "External 32-kHz CMOS Clock" (note that it refers to
+ a "32.768-kHz" clock; this presumably should be "32.768-KHz")
+
+2. OMAP2430 Multimedia Processor ES2.1 Data Manual, Version V [SWPS023V],
+ section 5.1.4 "External 32-kHz CMOS Clock" (note that it refers to
+ a "32.768-kHz" clock; this presumably should be "32.768-KHz")
+---
+ arch/arm/mach-omap2/clock2420_data.c | 2 +-
+ arch/arm/mach-omap2/clock2430_data.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 693a0a8..fd5ba90 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -55,7 +55,7 @@
+ static struct clk func_32k_ck = {
+ .name = "func_32k_ck",
+ .ops = &clkops_null,
+- .rate = 32000,
++ .rate = 32768,
+ .clkdm_name = "wkup_clkdm",
+ };
+
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 799ccdf..1bd66ee 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -55,7 +55,7 @@
+ static struct clk func_32k_ck = {
+ .name = "func_32k_ck",
+ .ops = &clkops_null,
+- .rate = 32000,
++ .rate = 32768,
+ .clkdm_name = "wkup_clkdm",
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0185-OMAP2xxx-clock-fix-interface-clocks-and-clockdomains.patch b/patches/for_next/0185-OMAP2xxx-clock-fix-interface-clocks-and-clockdomains.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2e65e0302c2dbc293f1254d8876791e46db2d757
--- /dev/null
+++ b/patches/for_next/0185-OMAP2xxx-clock-fix-interface-clocks-and-clockdomains.patch
@@ -0,0 +1,227 @@
+From f0ed79ca55ad33df2ade67befb9dbc148a6f6291 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 16 Feb 2011 15:38:38 -0700
+Subject: [PATCH 185/254] OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
+
+The parent of the interface clocks for GPTIMER1, MPU_WDT,
+SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
+being l4_ck. This isn't accurate; these modules exist inside the WKUP
+domain, and the interface clock to these modules runs at the SYS_CLK
+rate rather than the CORE L4 rate.
+
+So, create a new clock "wu_l4_ick", similar to the OMAP3
+"wkup_l4_ick", that serves as the parent for these clocks.
+
+Also, these clocks were listed as existing inside core_l4_clkdm;
+wkup_clkdm is probably more accurate.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock2420_data.c | 33 +++++++++++++++++++-----------
+ arch/arm/mach-omap2/clock2430_data.c | 37 +++++++++++++++++++++------------
+ 2 files changed, 44 insertions(+), 26 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index fd5ba90..6e9d20d 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -826,6 +826,14 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
+ .recalc = &followparent_recalc,
+ };
+
++static struct clk wu_l4_ick = {
++ .name = "wu_l4_ick",
++ .ops = &clkops_null,
++ .parent = &sys_ck,
++ .clkdm_name = "wkup_clkdm",
++ .recalc = &followparent_recalc,
++};
++
+ /*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+@@ -847,8 +855,8 @@ static const struct clksel omap24xx_gpt_clksel[] = {
+ static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1300,8 +1308,8 @@ static struct clk uart3_fck = {
+ static struct clk gpios_ick = {
+ .name = "gpios_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1320,8 +1328,8 @@ static struct clk gpios_fck = {
+ static struct clk mpu_wdt_ick = {
+ .name = "mpu_wdt_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1340,9 +1348,9 @@ static struct clk mpu_wdt_fck = {
+ static struct clk sync_32k_ick = {
+ .name = "sync_32k_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .flags = ENABLE_ON_INIT,
+- .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1351,8 +1359,8 @@ static struct clk sync_32k_ick = {
+ static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1361,9 +1369,9 @@ static struct clk wdt1_ick = {
+ static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .flags = ENABLE_ON_INIT,
+- .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1825,6 +1833,7 @@ static struct omap_clk omap2420_clks[] = {
+ /* L4 domain clocks */
+ CLK(NULL, "l4_ck", &l4_ck, CK_242X),
+ CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
++ CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
+ /* virtual meta-group clock */
+ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
+ /* general l4 interface ck, multi-parent functional clk */
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 1bd66ee..2c90559 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -814,6 +814,14 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
+ .recalc = &followparent_recalc,
+ };
+
++static struct clk wu_l4_ick = {
++ .name = "wu_l4_ick",
++ .ops = &clkops_null,
++ .parent = &sys_ck,
++ .clkdm_name = "wkup_clkdm",
++ .recalc = &followparent_recalc,
++};
++
+ /*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+@@ -835,8 +843,8 @@ static const struct clksel omap24xx_gpt_clksel[] = {
+ static struct clk gpt1_ick = {
+ .name = "gpt1_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1380,8 +1388,8 @@ static struct clk uart3_fck = {
+ static struct clk gpios_ick = {
+ .name = "gpios_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1400,8 +1408,8 @@ static struct clk gpios_fck = {
+ static struct clk mpu_wdt_ick = {
+ .name = "mpu_wdt_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1420,9 +1428,9 @@ static struct clk mpu_wdt_fck = {
+ static struct clk sync_32k_ick = {
+ .name = "sync_32k_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1431,8 +1439,8 @@ static struct clk sync_32k_ick = {
+ static struct clk wdt1_ick = {
+ .name = "wdt1_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1441,9 +1449,9 @@ static struct clk wdt1_ick = {
+ static struct clk omapctrl_ick = {
+ .name = "omapctrl_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+ .flags = ENABLE_ON_INIT,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1452,8 +1460,8 @@ static struct clk omapctrl_ick = {
+ static struct clk icr_ick = {
+ .name = "icr_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &l4_ck,
+- .clkdm_name = "core_l4_clkdm",
++ .parent = &wu_l4_ick,
++ .clkdm_name = "wkup_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2430_EN_ICR_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1914,6 +1922,7 @@ static struct omap_clk omap2430_clks[] = {
+ /* L4 domain clocks */
+ CLK(NULL, "l4_ck", &l4_ck, CK_243X),
+ CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
++ CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
+ /* virtual meta-group clock */
+ CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
+ /* general l4 interface ck, multi-parent functional clk */
+--
+1.7.1
+
diff --git a/patches/for_next/0186-OMAP-clock-bail-out-early-if-arch_clock-functions-no.patch b/patches/for_next/0186-OMAP-clock-bail-out-early-if-arch_clock-functions-no.patch
new file mode 100644
index 0000000000000000000000000000000000000000..1f0a2fbae21b8a44d5f9592da1ce54f9b677467b
--- /dev/null
+++ b/patches/for_next/0186-OMAP-clock-bail-out-early-if-arch_clock-functions-no.patch
@@ -0,0 +1,180 @@
+From 9246d918ea1956c5f64aa098d26e9bfc9dacc745 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 16 Feb 2011 15:38:38 -0700
+Subject: [PATCH 186/254] OMAP: clock: bail out early if arch_clock functions not implemented
+
+Bail out before we take the clockfw_lock spinlock if the corresponding
+OMAP1 or OMAP2+ clock function is not defined. The intention is to
+reduce and simplify the work that is done inside the spinlock.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/clock.c | 66 +++++++++++++++++++++++++------------------
+ 1 files changed, 38 insertions(+), 28 deletions(-)
+
+diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
+index 2770ddd..c9122dd 100644
+--- a/arch/arm/plat-omap/clock.c
++++ b/arch/arm/plat-omap/clock.c
+@@ -37,14 +37,16 @@ static struct clk_functions *arch_clock;
+ int clk_enable(struct clk *clk)
+ {
+ unsigned long flags;
+- int ret = 0;
++ int ret;
+
+ if (clk == NULL || IS_ERR(clk))
+ return -EINVAL;
+
++ if (!arch_clock || !arch_clock->clk_enable)
++ return -EINVAL;
++
+ spin_lock_irqsave(&clockfw_lock, flags);
+- if (arch_clock->clk_enable)
+- ret = arch_clock->clk_enable(clk);
++ ret = arch_clock->clk_enable(clk);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+
+ return ret;
+@@ -58,6 +60,9 @@ void clk_disable(struct clk *clk)
+ if (clk == NULL || IS_ERR(clk))
+ return;
+
++ if (!arch_clock || !arch_clock->clk_disable)
++ return;
++
+ spin_lock_irqsave(&clockfw_lock, flags);
+ if (clk->usecount == 0) {
+ pr_err("Trying disable clock %s with 0 usecount\n",
+@@ -66,8 +71,7 @@ void clk_disable(struct clk *clk)
+ goto out;
+ }
+
+- if (arch_clock->clk_disable)
+- arch_clock->clk_disable(clk);
++ arch_clock->clk_disable(clk);
+
+ out:
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+@@ -77,7 +81,7 @@ EXPORT_SYMBOL(clk_disable);
+ unsigned long clk_get_rate(struct clk *clk)
+ {
+ unsigned long flags;
+- unsigned long ret = 0;
++ unsigned long ret;
+
+ if (clk == NULL || IS_ERR(clk))
+ return 0;
+@@ -97,14 +101,16 @@ EXPORT_SYMBOL(clk_get_rate);
+ long clk_round_rate(struct clk *clk, unsigned long rate)
+ {
+ unsigned long flags;
+- long ret = 0;
++ long ret;
+
+ if (clk == NULL || IS_ERR(clk))
+- return ret;
++ return 0;
++
++ if (!arch_clock || !arch_clock->clk_round_rate)
++ return 0;
+
+ spin_lock_irqsave(&clockfw_lock, flags);
+- if (arch_clock->clk_round_rate)
+- ret = arch_clock->clk_round_rate(clk, rate);
++ ret = arch_clock->clk_round_rate(clk, rate);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+
+ return ret;
+@@ -119,14 +125,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
+ if (clk == NULL || IS_ERR(clk))
+ return ret;
+
++ if (!arch_clock || !arch_clock->clk_set_rate)
++ return ret;
++
+ spin_lock_irqsave(&clockfw_lock, flags);
+- if (arch_clock->clk_set_rate)
+- ret = arch_clock->clk_set_rate(clk, rate);
+- if (ret == 0) {
+- if (clk->recalc)
+- clk->rate = clk->recalc(clk);
++ ret = arch_clock->clk_set_rate(clk, rate);
++ if (ret == 0)
+ propagate_rate(clk);
+- }
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+
+ return ret;
+@@ -141,15 +146,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
+ if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
+ return ret;
+
++ if (!arch_clock || !arch_clock->clk_set_parent)
++ return ret;
++
+ spin_lock_irqsave(&clockfw_lock, flags);
+ if (clk->usecount == 0) {
+- if (arch_clock->clk_set_parent)
+- ret = arch_clock->clk_set_parent(clk, parent);
+- if (ret == 0) {
+- if (clk->recalc)
+- clk->rate = clk->recalc(clk);
++ ret = arch_clock->clk_set_parent(clk, parent);
++ if (ret == 0)
+ propagate_rate(clk);
+- }
+ } else
+ ret = -EBUSY;
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+@@ -399,9 +403,11 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+ {
+ unsigned long flags;
+
++ if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
++ return;
++
+ spin_lock_irqsave(&clockfw_lock, flags);
+- if (arch_clock->clk_init_cpufreq_table)
+- arch_clock->clk_init_cpufreq_table(table);
++ arch_clock->clk_init_cpufreq_table(table);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+ }
+
+@@ -409,9 +415,11 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
+ {
+ unsigned long flags;
+
++ if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
++ return;
++
+ spin_lock_irqsave(&clockfw_lock, flags);
+- if (arch_clock->clk_exit_cpufreq_table)
+- arch_clock->clk_exit_cpufreq_table(table);
++ arch_clock->clk_exit_cpufreq_table(table);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+ }
+ #endif
+@@ -429,6 +437,9 @@ static int __init clk_disable_unused(void)
+ struct clk *ck;
+ unsigned long flags;
+
++ if (!arch_clock || !arch_clock->clk_disable_unused)
++ return 0;
++
+ pr_info("clock: disabling unused clocks to save power\n");
+ list_for_each_entry(ck, &clocks, node) {
+ if (ck->ops == &clkops_null)
+@@ -438,8 +449,7 @@ static int __init clk_disable_unused(void)
+ continue;
+
+ spin_lock_irqsave(&clockfw_lock, flags);
+- if (arch_clock->clk_disable_unused)
+- arch_clock->clk_disable_unused(ck);
++ arch_clock->clk_disable_unused(ck);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+ }
+
+--
+1.7.1
+
diff --git a/patches/for_next/0187-OMAP2-clock-remove-the-DPLL-rate-tolerance-code.patch b/patches/for_next/0187-OMAP2-clock-remove-the-DPLL-rate-tolerance-code.patch
new file mode 100644
index 0000000000000000000000000000000000000000..69d1ab60dacf8ee0c2465c185d85efef9bc25936
--- /dev/null
+++ b/patches/for_next/0187-OMAP2-clock-remove-the-DPLL-rate-tolerance-code.patch
@@ -0,0 +1,296 @@
+From 3b37eb712e7906f605f6ca7aedd50414191bd4f2 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 16 Feb 2011 15:38:39 -0700
+Subject: [PATCH 187/254] OMAP2+: clock: remove the DPLL rate tolerance code
+
+Remove the DPLL rate tolerance code that is called during rate
+rounding. As far as I know, this code is never used, since it's been
+more important for callers of the DPLL round_rate()/set_rate()
+functions to obtain an exact rate than it is to save a relatively
+small amount of power.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clkt_dpll.c | 91 ++++++++-----------------------
+ arch/arm/mach-omap2/clock.h | 4 --
+ arch/arm/mach-omap2/clock2420_data.c | 1 -
+ arch/arm/mach-omap2/clock2430_data.c | 1 -
+ arch/arm/mach-omap2/clock3xxx_data.c | 6 --
+ arch/arm/plat-omap/include/plat/clock.h | 7 +--
+ 6 files changed, 24 insertions(+), 86 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
+index acb7ae5..bcffee0 100644
+--- a/arch/arm/mach-omap2/clkt_dpll.c
++++ b/arch/arm/mach-omap2/clkt_dpll.c
+@@ -178,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk)
+ if (!dd)
+ return;
+
+- /* Return bypass rate if DPLL is bypassed */
+ v = __raw_readl(dd->control_reg);
+ v &= dd->enable_mask;
+ v >>= __ffs(dd->enable_mask);
+
+- /* Reparent in case the dpll is in bypass */
++ /* Reparent the struct clk in case the dpll is in bypass */
+ if (cpu_is_omap24xx()) {
+ if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+ v == OMAP2XXX_EN_DPLL_FRBYPASS)
+@@ -260,50 +259,22 @@ u32 omap2_get_dpll_rate(struct clk *clk)
+ /* DPLL rate rounding code */
+
+ /**
+- * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
+- * @clk: struct clk * of the DPLL
+- * @tolerance: maximum rate error tolerance
+- *
+- * Set the maximum DPLL rate error tolerance for the rate rounding
+- * algorithm. The rate tolerance is an attempt to balance DPLL power
+- * saving (the least divider value "n") vs. rate fidelity (the least
+- * difference between the desired DPLL target rate and the rounded
+- * rate out of the algorithm). So, increasing the tolerance is likely
+- * to decrease DPLL power consumption and increase DPLL rate error.
+- * Returns -EINVAL if provided a null clock ptr or a clk that is not a
+- * DPLL; or 0 upon success.
+- */
+-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
+-{
+- if (!clk || !clk->dpll_data)
+- return -EINVAL;
+-
+- clk->dpll_data->rate_tolerance = tolerance;
+-
+- return 0;
+-}
+-
+-/**
+ * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
+ * @clk: struct clk * for a DPLL
+ * @target_rate: desired DPLL clock rate
+ *
+- * Given a DPLL, a desired target rate, and a rate tolerance, round
+- * the target rate to a possible, programmable rate for this DPLL.
+- * Rate tolerance is assumed to be set by the caller before this
+- * function is called. Attempts to select the minimum possible n
+- * within the tolerance to reduce power consumption. Stores the
+- * computed (m, n) in the DPLL's dpll_data structure so set_rate()
+- * will not need to call this (expensive) function again. Returns ~0
+- * if the target rate cannot be rounded, either because the rate is
+- * too low or because the rate tolerance is set too tightly; or the
+- * rounded rate upon success.
++ * Given a DPLL and a desired target rate, round the target rate to a
++ * possible, programmable rate for this DPLL. Attempts to select the
++ * minimum possible n. Stores the computed (m, n) in the DPLL's
++ * dpll_data structure so set_rate() will not need to call this
++ * (expensive) function again. Returns ~0 if the target rate cannot
++ * be rounded, or the rounded rate upon success.
+ */
+ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+ {
+- int m, n, r, e, scaled_max_m;
+- unsigned long scaled_rt_rp, new_rate;
+- int min_e = -1, min_e_m = -1, min_e_n = -1;
++ int m, n, r, scaled_max_m;
++ unsigned long scaled_rt_rp;
++ unsigned long new_rate = 0;
+ struct dpll_data *dd;
+
+ if (!clk || !clk->dpll_data)
+@@ -311,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+
+ dd = clk->dpll_data;
+
+- pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
+- "%ld\n", clk->name, target_rate);
++ pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
++ clk->name, target_rate);
+
+ scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+ scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
+@@ -347,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
+ if (r == DPLL_MULT_UNDERFLOW)
+ continue;
+
+- e = target_rate - new_rate;
+- pr_debug("clock: n = %d: m = %d: rate error is %d "
+- "(new_rate = %ld)\n", n, m, e, new_rate);
+-
+- if (min_e == -1 ||
+- min_e >= (int)(abs(e) - dd->rate_tolerance)) {
+- min_e = e;
+- min_e_m = m;
+- min_e_n = n;
+-
+- pr_debug("clock: found new least error %d\n", min_e);
++ pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
++ clk->name, m, n, new_rate);
+
+- /* We found good settings -- bail out now */
+- if (min_e <= dd->rate_tolerance)
+- break;
++ if (target_rate == new_rate) {
++ dd->last_rounded_m = m;
++ dd->last_rounded_n = n;
++ dd->last_rounded_rate = target_rate;
++ break;
+ }
+ }
+
+- if (min_e < 0) {
+- pr_debug("clock: error: target rate or tolerance too low\n");
++ if (target_rate != new_rate) {
++ pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
++ target_rate);
+ return ~0;
+ }
+
+- dd->last_rounded_m = min_e_m;
+- dd->last_rounded_n = min_e_n;
+- dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
+- min_e_m, min_e_n);
+-
+- pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
+- min_e, min_e_m, min_e_n);
+- pr_debug("clock: final rate: %ld (target rate: %ld)\n",
+- dd->last_rounded_rate, target_rate);
+-
+- return dd->last_rounded_rate;
++ return target_rate;
+ }
+
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index 70f8b07..62cfd6c 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -18,9 +18,6 @@
+
+ #include <plat/clock.h>
+
+-/* The maximum error between a target DPLL rate and the rounded rate in Hz */
+-#define DEFAULT_DPLL_RATE_TOLERANCE 50000
+-
+ /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
+ #define CORE_CLK_SRC_32K 0x0
+ #define CORE_CLK_SRC_DPLL 0x1
+@@ -55,7 +52,6 @@ void omap2_clk_disable(struct clk *clk);
+ long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
+ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
+ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
+-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
+ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
+ unsigned long omap3_dpll_recalc(struct clk *clk);
+ unsigned long omap3_clkoutx2_recalc(struct clk *clk);
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 6e9d20d..22eeafc 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -116,7 +116,6 @@ static struct dpll_data dpll_dd = {
+ .max_multiplier = 1023,
+ .min_divider = 1,
+ .max_divider = 16,
+- .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+ };
+
+ /*
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 2c90559..1185e8c 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -116,7 +116,6 @@ static struct dpll_data dpll_dd = {
+ .max_multiplier = 1023,
+ .min_divider = 1,
+ .max_divider = 16,
+- .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+ };
+
+ /*
+diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
+index 52f991c..d905ecc 100644
+--- a/arch/arm/mach-omap2/clock3xxx_data.c
++++ b/arch/arm/mach-omap2/clock3xxx_data.c
+@@ -291,7 +291,6 @@ static struct dpll_data dpll1_dd = {
+ .max_multiplier = OMAP3_MAX_DPLL_MULT,
+ .min_divider = 1,
+ .max_divider = OMAP3_MAX_DPLL_DIV,
+- .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+ };
+
+ static struct clk dpll1_ck = {
+@@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = {
+ .max_multiplier = OMAP3_MAX_DPLL_MULT,
+ .min_divider = 1,
+ .max_divider = OMAP3_MAX_DPLL_DIV,
+- .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+ };
+
+ static struct clk dpll2_ck = {
+@@ -424,7 +422,6 @@ static struct dpll_data dpll3_dd = {
+ .max_multiplier = OMAP3_MAX_DPLL_MULT,
+ .min_divider = 1,
+ .max_divider = OMAP3_MAX_DPLL_DIV,
+- .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+ };
+
+ static struct clk dpll3_ck = {
+@@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = {
+ .max_multiplier = OMAP3_MAX_DPLL_MULT,
+ .min_divider = 1,
+ .max_divider = OMAP3_MAX_DPLL_DIV,
+- .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+ };
+
+ static struct dpll_data dpll4_dd_3630 __initdata = {
+@@ -607,7 +603,6 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
+ .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
+ .min_divider = 1,
+ .max_divider = OMAP3_MAX_DPLL_DIV,
+- .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
+ .flags = DPLL_J_TYPE
+ };
+
+@@ -939,7 +934,6 @@ static struct dpll_data dpll5_dd = {
+ .max_multiplier = OMAP3_MAX_DPLL_MULT,
+ .min_divider = 1,
+ .max_divider = OMAP3_MAX_DPLL_DIV,
+- .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+ };
+
+ static struct clk dpll5_ck = {
+diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
+index dcd7bb8..006e599 100644
+--- a/arch/arm/plat-omap/include/plat/clock.h
++++ b/arch/arm/plat-omap/include/plat/clock.h
+@@ -109,7 +109,6 @@ struct clksel {
+ * @clk_ref: struct clk pointer to the clock's reference clock input
+ * @control_reg: register containing the DPLL mode bitfield
+ * @enable_mask: mask of the DPLL mode bitfield in @control_reg
+- * @rate_tolerance: maximum variance allowed from target rate (in Hz)
+ * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
+ * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
+ * @max_multiplier: maximum valid non-bypass multiplier value (actual)
+@@ -135,12 +134,9 @@ struct clksel {
+ * XXX Some DPLLs have multiple bypass inputs, so it's not technically
+ * correct to only have one @clk_bypass pointer.
+ *
+- * XXX @rate_tolerance should probably be deprecated - currently there
+- * don't seem to be any usecases for DPLL rounding that is not exact.
+- *
+ * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
+ * @last_rounded_n) should be separated from the runtime-fixed fields
+- * and placed into a differenct structure, so that the runtime-fixed data
++ * and placed into a different structure, so that the runtime-fixed data
+ * can be placed into read-only space.
+ */
+ struct dpll_data {
+@@ -151,7 +147,6 @@ struct dpll_data {
+ struct clk *clk_ref;
+ void __iomem *control_reg;
+ u32 enable_mask;
+- unsigned int rate_tolerance;
+ unsigned long last_rounded_rate;
+ u16 last_rounded_m;
+ u16 max_multiplier;
+--
+1.7.1
+
diff --git a/patches/for_next/0188-OMAP2xxx-clock-remove-dsp_irate_ick.patch b/patches/for_next/0188-OMAP2xxx-clock-remove-dsp_irate_ick.patch
new file mode 100644
index 0000000000000000000000000000000000000000..4b2af6d79b469369f0f0ff6e6f38dd414b66e7b2
--- /dev/null
+++ b/patches/for_next/0188-OMAP2xxx-clock-remove-dsp_irate_ick.patch
@@ -0,0 +1,163 @@
+From 8dbcc37e91f1dbda395f83adff576e3ef68c7cc8 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 15:52:04 -0700
+Subject: [PATCH 188/254] OMAP2xxx: clock: remove dsp_irate_ick
+
+After commit 81b34fbecbfbf24ed95c2d80d5cb14149652408f ("OMAP2 clock:
+split OMAP2420, OMAP2430 clock data into their own files"), it's
+possible to remove dsp_irate_ick from the OMAP2420 and OMAP2430 clock
+files. It was originally only needed due to a 2420/2430 clock tree difference,
+and now that the data is in separate files, it's superfluous.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock.h | 1 +
+ arch/arm/mach-omap2/clock2420_data.c | 31 ++++++++-----------------------
+ arch/arm/mach-omap2/clock2430_data.c | 31 ++++++++-----------------------
+ arch/arm/mach-omap2/clock_common_data.c | 6 ++++++
+ 4 files changed, 23 insertions(+), 46 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
+index 62cfd6c..e10ff2b 100644
+--- a/arch/arm/mach-omap2/clock.h
++++ b/arch/arm/mach-omap2/clock.h
+@@ -139,6 +139,7 @@ extern struct clk *vclk, *sclk;
+ extern const struct clksel_rate gpt_32k_rates[];
+ extern const struct clksel_rate gpt_sys_rates[];
+ extern const struct clksel_rate gfx_l3_rates[];
++extern const struct clksel_rate dsp_ick_rates[];
+
+ #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
+ extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 22eeafc..53bd999 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -454,36 +454,22 @@ static struct clk dsp_fck = {
+ .recalc = &omap2_clksel_recalc,
+ };
+
+-/* DSP interface clock */
+-static const struct clksel_rate dsp_irate_ick_rates[] = {
+- { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+- { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+- { .div = 0 },
+-};
+-
+-static const struct clksel dsp_irate_ick_clksel[] = {
+- { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
++static const struct clksel dsp_ick_clksel[] = {
++ { .parent = &dsp_fck, .rates = dsp_ick_rates },
+ { .parent = NULL }
+ };
+
+-/* This clock does not exist as such in the TRM. */
+-static struct clk dsp_irate_ick = {
+- .name = "dsp_irate_ick",
+- .ops = &clkops_null,
+- .parent = &dsp_fck,
+- .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+- .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
+- .clksel = dsp_irate_ick_clksel,
+- .recalc = &omap2_clksel_recalc,
+-};
+-
+-/* 2420 only */
+ static struct clk dsp_ick = {
+ .name = "dsp_ick", /* apparently ipi and isp */
+ .ops = &clkops_omap2_iclk_dflt_wait,
+- .parent = &dsp_irate_ick,
++ .parent = &dsp_fck,
++ .clkdm_name = "dsp_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
++ .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
++ .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
++ .clksel = dsp_ick_clksel,
++ .recalc = &omap2_clksel_recalc,
+ };
+
+ /*
+@@ -1812,7 +1798,6 @@ static struct omap_clk omap2420_clks[] = {
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
+ /* dsp domain clocks */
+ CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
+- CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_242X),
+ CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
+ CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
+ CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 1185e8c..d3a1173 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -433,37 +433,23 @@ static struct clk dsp_fck = {
+ .recalc = &omap2_clksel_recalc,
+ };
+
+-/* DSP interface clock */
+-static const struct clksel_rate dsp_irate_ick_rates[] = {
+- { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+- { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+- { .div = 3, .val = 3, .flags = RATE_IN_243X },
+- { .div = 0 },
+-};
+-
+-static const struct clksel dsp_irate_ick_clksel[] = {
+- { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
++static const struct clksel dsp_ick_clksel[] = {
++ { .parent = &dsp_fck, .rates = dsp_ick_rates },
+ { .parent = NULL }
+ };
+
+-/* This clock does not exist as such in the TRM. */
+-static struct clk dsp_irate_ick = {
+- .name = "dsp_irate_ick",
+- .ops = &clkops_null,
+- .parent = &dsp_fck,
+- .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+- .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
+- .clksel = dsp_irate_ick_clksel,
+- .recalc = &omap2_clksel_recalc,
+-};
+-
+ /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
+ static struct clk iva2_1_ick = {
+ .name = "iva2_1_ick",
+ .ops = &clkops_omap2_dflt_wait,
+- .parent = &dsp_irate_ick,
++ .parent = &dsp_fck,
++ .clkdm_name = "dsp_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+ .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
++ .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
++ .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
++ .clksel = dsp_ick_clksel,
++ .recalc = &omap2_clksel_recalc,
+ };
+
+ /*
+@@ -1900,7 +1886,6 @@ static struct omap_clk omap2430_clks[] = {
+ CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
+ /* dsp domain clocks */
+ CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
+- CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X),
+ CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
+ /* GFX domain clocks */
+ CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
+diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
+index 1cf8131..6424d46 100644
+--- a/arch/arm/mach-omap2/clock_common_data.c
++++ b/arch/arm/mach-omap2/clock_common_data.c
+@@ -37,3 +37,9 @@ const struct clksel_rate gfx_l3_rates[] = {
+ { .div = 0 }
+ };
+
++const struct clksel_rate dsp_ick_rates[] = {
++ { .div = 1, .val = 1, .flags = RATE_IN_24XX },
++ { .div = 2, .val = 2, .flags = RATE_IN_24XX },
++ { .div = 3, .val = 3, .flags = RATE_IN_243X },
++ { .div = 0 },
++};
+--
+1.7.1
+
diff --git a/patches/for_next/0189-omap2-3-clockdomains-fix-compile-time-warnings.patch b/patches/for_next/0189-omap2-3-clockdomains-fix-compile-time-warnings.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9378c16d8b360ea732253b3dd7a000520fcc0eec
--- /dev/null
+++ b/patches/for_next/0189-omap2-3-clockdomains-fix-compile-time-warnings.patch
@@ -0,0 +1,49 @@
+From 981c9c96bb3dd7c0a46a3dfc3ccee52631f8cf58 Mon Sep 17 00:00:00 2001
+From: Sanjeev Premi <premi@ti.com>
+Date: Fri, 11 Feb 2011 09:05:00 +0000
+Subject: [PATCH 189/254] omap2/3: clockdomains: fix compile-time warnings
+
+This patch fixes these warnings when building kernel for OMAP3EVM
+only.
+
+ CC arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.o
+arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c:95: warning:
+ 'dsp_24xx_wkdeps' defined but not used
+arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c:119: warning:
+ 'mpu_24xx_wkdeps' defined but not used
+arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c:147: warning:
+ 'core_24xx_wkdeps' defined but not used
+
+The problem should be noticed when building for other OMAP3
+platforms (only) as well.
+
+Signed-off-by: Sanjeev Premi <premi@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+index ffdfe54..13bde95 100644
+--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
++++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+@@ -89,6 +89,8 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = {
+
+ /* 24XX-specific possible dependencies */
+
++#ifdef CONFIG_ARCH_OMAP2
++
+ /* Wakeup dependency source arrays */
+
+ /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
+@@ -168,6 +170,7 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
+ { NULL },
+ };
+
++#endif /* CONFIG_ARCH_OMAP2 */
+
+ /* 2430-specific possible wakeup dependencies */
+
+--
+1.7.1
+
diff --git a/patches/for_next/0190-OMAP2xxx-clock-fix-clockdomains-on-gpt7_ick-2430-mmc.patch b/patches/for_next/0190-OMAP2xxx-clock-fix-clockdomains-on-gpt7_ick-2430-mmc.patch
new file mode 100644
index 0000000000000000000000000000000000000000..97b7bba20aafe840e3df63d73a860511257cda96
--- /dev/null
+++ b/patches/for_next/0190-OMAP2xxx-clock-fix-clockdomains-on-gpt7_ick-2430-mmc.patch
@@ -0,0 +1,61 @@
+From 0c9d3d366d4d1c358016805a56c52989cdb692c2 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 14:53:40 -0700
+Subject: [PATCH 190/254] OMAP2xxx: clock: fix clockdomains on gpt7_ick, 2430 mmchs2_fck clocks
+
+Add a clockdomain to the GPTIMER7 interface and 2430 HSMMC2 functional
+clocks - both were previously missing them.
+
+Also, the 2430 mmchs1_fck is in core_l3_clkdm, but should be in
+core_l4_clkdm; fix this.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock2420_data.c | 1 +
+ arch/arm/mach-omap2/clock2430_data.c | 4 +++-
+ 2 files changed, 4 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 53bd999..5e80d3d 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -987,6 +987,7 @@ static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
++ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .recalc = &followparent_recalc,
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index d3a1173..795cfaf 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -975,6 +975,7 @@ static struct clk gpt7_ick = {
+ .name = "gpt7_ick",
+ .ops = &clkops_omap2_iclk_dflt_wait,
+ .parent = &l4_ck,
++ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1747,7 +1748,7 @@ static struct clk mmchs1_fck = {
+ .name = "mmchs1_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_96m_ck,
+- .clkdm_name = "core_l3_clkdm",
++ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
+ .recalc = &followparent_recalc,
+@@ -1767,6 +1768,7 @@ static struct clk mmchs2_fck = {
+ .name = "mmchs2_fck",
+ .ops = &clkops_omap2_dflt_wait,
+ .parent = &func_96m_ck,
++ .clkdm_name = "core_l4_clkdm",
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
+ .recalc = &followparent_recalc,
+--
+1.7.1
+
diff --git a/patches/for_next/0191-OMAP2xxx-clock-data-clean-up-some-comments.patch b/patches/for_next/0191-OMAP2xxx-clock-data-clean-up-some-comments.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f941f77d8fa1103c5cd47e0b4890bba93f77828a
--- /dev/null
+++ b/patches/for_next/0191-OMAP2xxx-clock-data-clean-up-some-comments.patch
@@ -0,0 +1,108 @@
+From de471c3f6493ee36f0f46a89a3f7b9a83d6c5814 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 25 Feb 2011 13:56:40 -0700
+Subject: [PATCH 191/254] OMAP2xxx: clock data: clean up some comments
+
+Minor cleanup of some clock data comments. No functional changes.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock2420_data.c | 23 ++++++++++-------------
+ arch/arm/mach-omap2/clock2430_data.c | 23 ++++++++++-------------
+ 2 files changed, 20 insertions(+), 26 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
+index 5e80d3d..b6f65d4 100644
+--- a/arch/arm/mach-omap2/clock2420_data.c
++++ b/arch/arm/mach-omap2/clock2420_data.c
+@@ -1,12 +1,12 @@
+ /*
+- * linux/arch/arm/mach-omap2/clock2420_data.c
++ * OMAP2420 clock data
+ *
+- * Copyright (C) 2005-2009 Texas Instruments, Inc.
+- * Copyright (C) 2004-2011 Nokia Corporation
++ * Copyright (C) 2005-2009 Texas Instruments, Inc.
++ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+- * Contacts:
+- * Richard Woodruff <r-woodruff2@ti.com>
+- * Paul Walmsley
++ * Contacts:
++ * Richard Woodruff <r-woodruff2@ti.com>
++ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -34,18 +34,15 @@
+ /*
+ * 2420 clock tree.
+ *
+- * NOTE:In many cases here we are assigning a 'default' parent. In many
+- * cases the parent is selectable. The get/set parent calls will also
+- * switch sources.
+- *
+- * Many some clocks say always_enabled, but they can be auto idled for
+- * power savings. They will always be available upon clock request.
++ * NOTE:In many cases here we are assigning a 'default' parent. In
++ * many cases the parent is selectable. The set parent calls will
++ * also switch sources.
+ *
+ * Several sources are given initial rates which may be wrong, this will
+ * be fixed up in the init func.
+ *
+ * Things are broadly separated below by clock domains. It is
+- * noteworthy that most periferals have dependencies on multiple clock
++ * noteworthy that most peripherals have dependencies on multiple clock
+ * domains. Many get their interface clocks from the L4 domain, but get
+ * functional clocks from fixed sources or other core domain derived
+ * clocks.
+diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
+index 795cfaf..bba0183 100644
+--- a/arch/arm/mach-omap2/clock2430_data.c
++++ b/arch/arm/mach-omap2/clock2430_data.c
+@@ -1,12 +1,12 @@
+ /*
+- * linux/arch/arm/mach-omap2/clock2430_data.c
++ * OMAP2430 clock data
+ *
+- * Copyright (C) 2005-2009 Texas Instruments, Inc.
+- * Copyright (C) 2004-2011 Nokia Corporation
++ * Copyright (C) 2005-2009 Texas Instruments, Inc.
++ * Copyright (C) 2004-2011 Nokia Corporation
+ *
+- * Contacts:
+- * Richard Woodruff <r-woodruff2@ti.com>
+- * Paul Walmsley
++ * Contacts:
++ * Richard Woodruff <r-woodruff2@ti.com>
++ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -34,18 +34,15 @@
+ /*
+ * 2430 clock tree.
+ *
+- * NOTE:In many cases here we are assigning a 'default' parent. In many
+- * cases the parent is selectable. The get/set parent calls will also
+- * switch sources.
+- *
+- * Many some clocks say always_enabled, but they can be auto idled for
+- * power savings. They will always be available upon clock request.
++ * NOTE:In many cases here we are assigning a 'default' parent. In
++ * many cases the parent is selectable. The set parent calls will
++ * also switch sources.
+ *
+ * Several sources are given initial rates which may be wrong, this will
+ * be fixed up in the init func.
+ *
+ * Things are broadly separated below by clock domains. It is
+- * noteworthy that most periferals have dependencies on multiple clock
++ * noteworthy that most peripherals have dependencies on multiple clock
+ * domains. Many get their interface clocks from the L4 domain, but get
+ * functional clocks from fixed sources or other core domain derived
+ * clocks.
+--
+1.7.1
+
diff --git a/patches/for_next/0192-OMAP1-McBSP-fix-build-break-for-non-multi-OMAP1-conf.patch b/patches/for_next/0192-OMAP1-McBSP-fix-build-break-for-non-multi-OMAP1-conf.patch
new file mode 100644
index 0000000000000000000000000000000000000000..cf410643d56bb086beac490ef771b2ab803f6aec
--- /dev/null
+++ b/patches/for_next/0192-OMAP1-McBSP-fix-build-break-for-non-multi-OMAP1-conf.patch
@@ -0,0 +1,112 @@
+From acb9c5266165bb6a2867ea477ee1b71d66f049b6 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 4 Mar 2011 22:36:46 +0000
+Subject: [PATCH 192/254] OMAP1: McBSP: fix build break for non-multi-OMAP1 configs
+
+Commit 3cf32bba8ca0e0052ca41d74d455a5805b7fea85 ("OMAP: McBSP: Convert
+McBSP to platform device model") breaks compilation with non-multi-OMAP1
+configs:
+
+ CC arch/arm/mach-omap1/mcbsp.o
+arch/arm/mach-omap1/mcbsp.c: In function 'omap1_mcbsp_init':
+arch/arm/mach-omap1/mcbsp.c:384: warning: dereferencing 'void *' pointer
+arch/arm/mach-omap1/mcbsp.c:387: error: invalid use of void expression
+arch/arm/mach-omap1/mcbsp.c:390: warning: dereferencing 'void *' pointer
+arch/arm/mach-omap1/mcbsp.c:393: error: invalid use of void expression
+
+Fix by avoiding NULL dereferences.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Kishon Vijay Abraham I <kishon@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+[tony@atomide.com: updated description not to remove unnecessary branch name]
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap1/mcbsp.c | 18 ++++++++++++------
+ 1 files changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
+index e68f6c0..d9af981 100644
+--- a/arch/arm/mach-omap1/mcbsp.c
++++ b/arch/arm/mach-omap1/mcbsp.c
+@@ -136,6 +136,8 @@ struct resource omap7xx_mcbsp_res[][6] = {
+ },
+ };
+
++#define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
++
+ static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
+ {
+ .ops = &omap1_mcbsp_ops,
+@@ -147,7 +149,7 @@ static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
+ #define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
+ #define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
+ #else
+-#define omap7xx_mcbsp_res NULL
++#define omap7xx_mcbsp_res_0 NULL
+ #define omap7xx_mcbsp_pdata NULL
+ #define OMAP7XX_MCBSP_RES_SZ 0
+ #define OMAP7XX_MCBSP_COUNT 0
+@@ -238,6 +240,8 @@ struct resource omap15xx_mcbsp_res[][6] = {
+ },
+ };
+
++#define omap15xx_mcbsp_res_0 omap15xx_mcbsp_res[0]
++
+ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
+ {
+ .ops = &omap1_mcbsp_ops,
+@@ -252,7 +256,7 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
+ #define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
+ #define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
+ #else
+-#define omap15xx_mcbsp_res NULL
++#define omap15xx_mcbsp_res_0 NULL
+ #define omap15xx_mcbsp_pdata NULL
+ #define OMAP15XX_MCBSP_RES_SZ 0
+ #define OMAP15XX_MCBSP_COUNT 0
+@@ -343,6 +347,8 @@ struct resource omap16xx_mcbsp_res[][6] = {
+ },
+ };
+
++#define omap16xx_mcbsp_res_0 omap16xx_mcbsp_res[0]
++
+ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
+ {
+ .ops = &omap1_mcbsp_ops,
+@@ -357,7 +363,7 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
+ #define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
+ #define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
+ #else
+-#define omap16xx_mcbsp_res NULL
++#define omap16xx_mcbsp_res_0 NULL
+ #define omap16xx_mcbsp_pdata NULL
+ #define OMAP16XX_MCBSP_RES_SZ 0
+ #define OMAP16XX_MCBSP_COUNT 0
+@@ -381,19 +387,19 @@ static int __init omap1_mcbsp_init(void)
+ return -ENOMEM;
+
+ if (cpu_is_omap7xx())
+- omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0],
++ omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
+ OMAP7XX_MCBSP_RES_SZ,
+ omap7xx_mcbsp_pdata,
+ OMAP7XX_MCBSP_COUNT);
+
+ if (cpu_is_omap15xx())
+- omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0],
++ omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
+ OMAP15XX_MCBSP_RES_SZ,
+ omap15xx_mcbsp_pdata,
+ OMAP15XX_MCBSP_COUNT);
+
+ if (cpu_is_omap16xx())
+- omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0],
++ omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
+ OMAP16XX_MCBSP_RES_SZ,
+ omap16xx_mcbsp_pdata,
+ OMAP16XX_MCBSP_COUNT);
+--
+1.7.1
+
diff --git a/patches/for_next/0193-audio-AM3517-Adding-i2c-info-for-AIC23-codec.patch b/patches/for_next/0193-audio-AM3517-Adding-i2c-info-for-AIC23-codec.patch
new file mode 100644
index 0000000000000000000000000000000000000000..ff46d6f9af81957ef27b394ebf72fae2afcc4da0
--- /dev/null
+++ b/patches/for_next/0193-audio-AM3517-Adding-i2c-info-for-AIC23-codec.patch
@@ -0,0 +1,32 @@
+From 3895f6de4af2e0bc68a89bfa58454acf340456b0 Mon Sep 17 00:00:00 2001
+From: Abhilash Vadakkepat Koyamangalath <x0151633@psplinux051.india.ti.com>
+Date: Tue, 8 Mar 2011 15:13:24 +0000
+Subject: [PATCH 193/254] audio : AM3517 : Adding i2c info for AIC23 codec
+
+The i2c_board_info entry supporting AIC23 codec was added into
+the i2c2 bus.
+
+Signed-off-by: Abhilash K V <abhilash.kv@ti.com>
+Acked-by: Jarkko Nikula <jhnikula@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-am3517evm.c | 3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
+index 30ec451..77541cf 100644
+--- a/arch/arm/mach-omap2/board-am3517evm.c
++++ b/arch/arm/mach-omap2/board-am3517evm.c
+@@ -200,6 +200,9 @@ static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
+ };
+ static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
+ {
++ I2C_BOARD_INFO("tlv320aic23", 0x1A),
++ },
++ {
+ I2C_BOARD_INFO("tca6416", 0x21),
+ .platform_data = &am3517evm_gpio_expander_info_0,
+ },
+--
+1.7.1
+
diff --git a/patches/for_next/0194-OMAP3-hwmod_data-Add-address-space-and-irq-in-L3-hwm.patch b/patches/for_next/0194-OMAP3-hwmod_data-Add-address-space-and-irq-in-L3-hwm.patch
new file mode 100644
index 0000000000000000000000000000000000000000..017297e64c05f3e3d83e74fce8d0a44829972bd5
--- /dev/null
+++ b/patches/for_next/0194-OMAP3-hwmod_data-Add-address-space-and-irq-in-L3-hwm.patch
@@ -0,0 +1,74 @@
+From 6f599d7084c2231e9cbafcea112e7af33f517fa1 Mon Sep 17 00:00:00 2001
+From: sricharan <r.sricharan@ti.com>
+Date: Tue, 8 Feb 2011 22:13:37 +0530
+Subject: [PATCH 194/254] OMAP3: hwmod_data: Add address space and irq in L3 hwmod.
+
+Add the address spaces, irqs of the l3 interconnect to the
+hwmod data. The hwmod changes are aligned with Benoit Cousson.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 22 ++++++++++++++++++++--
+ arch/arm/plat-omap/include/plat/irqs.h | 2 ++
+ 2 files changed, 22 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 6d59698..1d10389 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -97,10 +97,26 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
++/* L3 taret configuration and error log registers */
++static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
++ { .irq = INT_34XX_L3_DBG_IRQ },
++ { .irq = INT_34XX_L3_APP_IRQ },
++};
++
++static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
++ {
++ .pa_start = 0x68000000,
++ .pa_end = 0x6800ffff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
+ /* MPU -> L3 interface */
+ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
+- .master = &omap3xxx_mpu_hwmod,
+- .slave = &omap3xxx_l3_main_hwmod,
++ .master = &omap3xxx_mpu_hwmod,
++ .slave = &omap3xxx_l3_main_hwmod,
++ .addr = omap3xxx_l3_main_addrs,
++ .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
+ .user = OCP_USER_MPU,
+ };
+
+@@ -132,6 +148,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
+ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
+ .name = "l3_main",
+ .class = &l3_hwmod_class,
++ .mpu_irqs = omap3xxx_l3_main_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
+ .masters = omap3xxx_l3_main_masters,
+ .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
+ .slaves = omap3xxx_l3_main_slaves,
+diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
+index 1b91168..d779283 100644
+--- a/arch/arm/plat-omap/include/plat/irqs.h
++++ b/arch/arm/plat-omap/include/plat/irqs.h
+@@ -315,6 +315,8 @@
+ #define INT_34XX_SSM_ABORT_IRQ 6
+ #define INT_34XX_SYS_NIRQ 7
+ #define INT_34XX_D2D_FW_IRQ 8
++#define INT_34XX_L3_DBG_IRQ 9
++#define INT_34XX_L3_APP_IRQ 10
+ #define INT_34XX_PRCM_MPU_IRQ 11
+ #define INT_34XX_MCBSP1_IRQ 16
+ #define INT_34XX_MCBSP2_IRQ 17
+--
+1.7.1
+
diff --git a/patches/for_next/0195-OMAP3-devices-Initialise-the-l3-device-with-the-hwmo.patch b/patches/for_next/0195-OMAP3-devices-Initialise-the-l3-device-with-the-hwmo.patch
new file mode 100644
index 0000000000000000000000000000000000000000..fa1d9acd363c17211f3ab6954bc319f934ffa256
--- /dev/null
+++ b/patches/for_next/0195-OMAP3-devices-Initialise-the-l3-device-with-the-hwmo.patch
@@ -0,0 +1,62 @@
+From 2acd56fead8bdd897c75a678841bf6d469a13e71 Mon Sep 17 00:00:00 2001
+From: sricharan <r.sricharan@ti.com>
+Date: Tue, 8 Feb 2011 14:10:45 +0530
+Subject: [PATCH 195/254] OMAP3: devices: Initialise the l3 device with the hwmod data.
+
+The l3 interconnect device is build with all the data required
+to handle the error logging. The data is extracted from the
+hwmod database.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/devices.c | 32 ++++++++++++++++++++++++++++++++
+ 1 files changed, 32 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index 2cb720b..6a320b6 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -36,6 +36,38 @@
+ #include "mux.h"
+ #include "control.h"
+
++#define L3_MODULES_MAX_LEN 12
++
++static int __init omap3_l3_init(void)
++{
++ int l;
++ struct omap_hwmod *oh;
++ struct omap_device *od;
++ char oh_name[L3_MODULES_MAX_LEN];
++
++ /*
++ * To avoid code running on other OMAPs in
++ * multi-omap builds
++ */
++ if (!(cpu_is_omap34xx()))
++ return -ENODEV;
++
++ l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
++
++ oh = omap_hwmod_lookup(oh_name);
++
++ if (!oh)
++ pr_err("could not look up %s\n", oh_name);
++
++ od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
++ NULL, 0, 0);
++
++ WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
++
++ return PTR_ERR(od);
++}
++postcore_initcall(omap3_l3_init);
++
+ #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
+
+ static struct resource cam_resources[] = {
+--
+1.7.1
+
diff --git a/patches/for_next/0196-OMAP3-l3-Introduce-l3-interconnect-error-handling-dr.patch b/patches/for_next/0196-OMAP3-l3-Introduce-l3-interconnect-error-handling-dr.patch
new file mode 100644
index 0000000000000000000000000000000000000000..541a7cbe2d61e7386e4c8ffd77917a1e3dd2f7ed
--- /dev/null
+++ b/patches/for_next/0196-OMAP3-l3-Introduce-l3-interconnect-error-handling-dr.patch
@@ -0,0 +1,707 @@
+From 7f7f61abfc4debccfcc1a321ad65e97c22a29b51 Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Mon, 7 Mar 2011 19:35:20 +0530
+Subject: [PATCH 196/254] OMAP3: l3: Introduce l3-interconnect error handling driver
+
+The driver provides the information regarding the ocp errors
+that gets logged in the interconnect.The error info provides
+the details regarding the master or the target that
+generated the error, type of error and the corresponding address.
+The stack dump is also provided.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+[r.sricharan@ti.com: Enhacements, major cleanup and made it functional]
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+[santosh.shilimkar@ti.com: Driver design changes as per OMAP4 version]
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+[balbi@ti.com: Initial version of the driver]
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 3 +
+ arch/arm/mach-omap2/omap_l3_smx.c | 314 ++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/omap_l3_smx.h | 338 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 655 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/omap_l3_smx.c
+ create mode 100644 arch/arm/mach-omap2/omap_l3_smx.h
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 39b02bc..eb35111 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -141,6 +141,9 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
+ # EMU peripherals
+ obj-$(CONFIG_OMAP3_EMU) += emu.o
+
++# L3 interconnect
++obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
++
+ obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
+ mailbox_mach-objs := mailbox.o
+
+diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
+new file mode 100644
+index 0000000..265bff3
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap_l3_smx.c
+@@ -0,0 +1,314 @@
++ /*
++ * OMAP3XXX L3 Interconnect Driver
++ *
++ * Copyright (C) 2011 Texas Corporation
++ * Felipe Balbi <balbi@ti.com>
++ * Santosh Shilimkar <santosh.shilimkar@ti.com>
++ * Sricharan <r.sricharan@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
++ * USA
++ */
++
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include "omap_l3_smx.h"
++
++static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
++{
++ return __raw_readll(base + reg);
++}
++
++static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
++{
++ __raw_writell(value, base + reg);
++}
++
++static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
++{
++ return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
++}
++
++static inline u32 omap3_l3_decode_addr(u64 error_addr)
++{
++ return error_addr & 0xffffffff;
++}
++
++static inline unsigned omap3_l3_decode_cmd(u64 error)
++{
++ return (error & 0x07) >> L3_ERROR_LOG_CMD;
++}
++
++static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
++{
++ return (error & 0xff00) >> L3_ERROR_LOG_INITID;
++}
++
++static inline unsigned omap3_l3_decode_req_info(u64 error)
++{
++ return (error >> 32) & 0xffff;
++}
++
++static char *omap3_l3_code_string(u8 code)
++{
++ switch (code) {
++ case OMAP_L3_CODE_NOERROR:
++ return "No Error";
++ case OMAP_L3_CODE_UNSUP_CMD:
++ return "Unsupported Command";
++ case OMAP_L3_CODE_ADDR_HOLE:
++ return "Address Hole";
++ case OMAP_L3_CODE_PROTECT_VIOLATION:
++ return "Protection Violation";
++ case OMAP_L3_CODE_IN_BAND_ERR:
++ return "In-band Error";
++ case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
++ return "Request Timeout Not Accepted";
++ case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
++ return "Request Timeout, no response";
++ default:
++ return "UNKNOWN error";
++ }
++}
++
++static char *omap3_l3_initiator_string(u8 initid)
++{
++ switch (initid) {
++ case OMAP_L3_LCD:
++ return "LCD";
++ case OMAP_L3_SAD2D:
++ return "SAD2D";
++ case OMAP_L3_IA_MPU_SS_1:
++ case OMAP_L3_IA_MPU_SS_2:
++ case OMAP_L3_IA_MPU_SS_3:
++ case OMAP_L3_IA_MPU_SS_4:
++ case OMAP_L3_IA_MPU_SS_5:
++ return "MPU";
++ case OMAP_L3_IA_IVA_SS_1:
++ case OMAP_L3_IA_IVA_SS_2:
++ case OMAP_L3_IA_IVA_SS_3:
++ return "IVA_SS";
++ case OMAP_L3_IA_IVA_SS_DMA_1:
++ case OMAP_L3_IA_IVA_SS_DMA_2:
++ case OMAP_L3_IA_IVA_SS_DMA_3:
++ case OMAP_L3_IA_IVA_SS_DMA_4:
++ case OMAP_L3_IA_IVA_SS_DMA_5:
++ case OMAP_L3_IA_IVA_SS_DMA_6:
++ return "IVA_SS_DMA";
++ case OMAP_L3_IA_SGX:
++ return "SGX";
++ case OMAP_L3_IA_CAM_1:
++ case OMAP_L3_IA_CAM_2:
++ case OMAP_L3_IA_CAM_3:
++ return "CAM";
++ case OMAP_L3_IA_DAP:
++ return "DAP";
++ case OMAP_L3_SDMA_WR_1:
++ case OMAP_L3_SDMA_WR_2:
++ return "SDMA_WR";
++ case OMAP_L3_SDMA_RD_1:
++ case OMAP_L3_SDMA_RD_2:
++ case OMAP_L3_SDMA_RD_3:
++ case OMAP_L3_SDMA_RD_4:
++ return "SDMA_RD";
++ case OMAP_L3_USBOTG:
++ return "USB_OTG";
++ case OMAP_L3_USBHOST:
++ return "USB_HOST";
++ default:
++ return "UNKNOWN Initiator";
++ }
++}
++
++/**
++ * omap3_l3_block_irq - handles a register block's irq
++ * @l3: struct omap3_l3 *
++ * @base: register block base address
++ * @error: L3_ERROR_LOG register of our block
++ *
++ * Called in hard-irq context. Caller should take care of locking
++ *
++ * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
++ * Analysis Sequence, we are following that sequence here, please
++ * refer to that Figure for more information on the subject.
++ */
++static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
++ u64 error, int error_addr)
++{
++ u8 code = omap3_l3_decode_error_code(error);
++ u8 initid = omap3_l3_decode_initid(error);
++ u8 multi = error & L3_ERROR_LOG_MULTI;
++ u32 address = omap3_l3_decode_addr(error_addr);
++
++ WARN(true, "%s Error seen by %s %s at address %x\n",
++ omap3_l3_code_string(code),
++ omap3_l3_initiator_string(initid),
++ multi ? "Multiple Errors" : "",
++ address);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
++{
++ struct omap3_l3 *l3 = _l3;
++
++ u64 status, clear;
++ u64 error;
++ u64 error_addr;
++ u64 err_source = 0;
++ void __iomem *base;
++ int int_type;
++
++ irqreturn_t ret = IRQ_NONE;
++
++ if (irq == l3->app_irq)
++ int_type = L3_APPLICATION_ERROR;
++ else
++ int_type = L3_DEBUG_ERROR;
++
++ if (!int_type) {
++ status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
++ /*
++ * if we have a timeout error, there's nothing we can
++ * do besides rebooting the board. So let's BUG on any
++ * of such errors and handle the others. timeout error
++ * is severe and not expected to occur.
++ */
++ BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
++ } else {
++ status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
++ /* No timeout error for debug sources */
++ }
++
++ base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source)));
++
++ /* identify the error source */
++ for (err_source = 0; !(status & (1 << err_source)); err_source++)
++ ;
++ error = omap3_l3_readll(base, L3_ERROR_LOG);
++
++ if (error) {
++ error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
++
++ ret |= omap3_l3_block_irq(l3, error, error_addr);
++ }
++
++ /* Clear the status register */
++ clear = ((L3_AGENT_STATUS_CLEAR_IA << int_type) |
++ (L3_AGENT_STATUS_CLEAR_TA));
++
++ omap3_l3_writell(base, L3_AGENT_STATUS, clear);
++
++ /* clear the error log register */
++ omap3_l3_writell(base, L3_ERROR_LOG, error);
++
++ return ret;
++}
++
++static int __init omap3_l3_probe(struct platform_device *pdev)
++{
++ struct omap3_l3 *l3;
++ struct resource *res;
++ int ret;
++ int irq;
++
++ l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
++ if (!l3) {
++ ret = -ENOMEM;
++ goto err0;
++ }
++
++ platform_set_drvdata(pdev, l3);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "couldn't find resource\n");
++ ret = -ENODEV;
++ goto err1;
++ }
++ l3->rt = ioremap(res->start, resource_size(res));
++ if (!(l3->rt)) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto err2;
++ }
++
++ irq = platform_get_irq(pdev, 0);
++ ret = request_irq(irq, omap3_l3_app_irq,
++ IRQF_DISABLED | IRQF_TRIGGER_RISING,
++ "l3-debug-irq", l3);
++ if (ret) {
++ dev_err(&pdev->dev, "couldn't request debug irq\n");
++ goto err3;
++ }
++ l3->debug_irq = irq;
++
++ irq = platform_get_irq(pdev, 1);
++ ret = request_irq(irq, omap3_l3_app_irq,
++ IRQF_DISABLED | IRQF_TRIGGER_RISING,
++ "l3-app-irq", l3);
++
++ if (ret) {
++ dev_err(&pdev->dev, "couldn't request app irq\n");
++ goto err4;
++ }
++
++ l3->app_irq = irq;
++ goto err0;
++
++err4:
++err3:
++ iounmap(l3->rt);
++err2:
++err1:
++ kfree(l3);
++err0:
++ return ret;
++}
++
++static int __exit omap3_l3_remove(struct platform_device *pdev)
++{
++ struct omap3_l3 *l3 = platform_get_drvdata(pdev);
++
++ free_irq(l3->app_irq, l3);
++ free_irq(l3->debug_irq, l3);
++ iounmap(l3->rt);
++ kfree(l3);
++
++ return 0;
++}
++
++static struct platform_driver omap3_l3_driver = {
++ .remove = __exit_p(omap3_l3_remove),
++ .driver = {
++ .name = "omap_l3_smx",
++ },
++};
++
++static int __init omap3_l3_init(void)
++{
++ return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
++}
++postcore_initcall_sync(omap3_l3_init);
++
++static void __exit omap3_l3_exit(void)
++{
++ platform_driver_unregister(&omap3_l3_driver);
++}
++module_exit(omap3_l3_exit);
+diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
+new file mode 100644
+index 0000000..ba2ed9a
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap_l3_smx.h
+@@ -0,0 +1,338 @@
++ /*
++ * OMAP3XXX L3 Interconnect Driver header
++ *
++ * Copyright (C) 2011 Texas Corporation
++ * Felipe Balbi <balbi@ti.com>
++ * Santosh Shilimkar <santosh.shilimkar@ti.com>
++ * sricharan <r.sricharan@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
++ * USA
++ */
++#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
++#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
++
++/* Register definitions. All 64-bit wide */
++#define L3_COMPONENT 0x000
++#define L3_CORE 0x018
++#define L3_AGENT_CONTROL 0x020
++#define L3_AGENT_STATUS 0x028
++#define L3_ERROR_LOG 0x058
++
++#define L3_ERROR_LOG_MULTI (1 << 31)
++#define L3_ERROR_LOG_SECONDARY (1 << 30)
++
++#define L3_ERROR_LOG_ADDR 0x060
++
++/* Register definitions for Sideband Interconnect */
++#define L3_SI_CONTROL 0x020
++#define L3_SI_FLAG_STATUS_0 0x510
++
++const u64 shift = 1;
++
++#define L3_STATUS_0_MPUIA_BRST (shift << 0)
++#define L3_STATUS_0_MPUIA_RSP (shift << 1)
++#define L3_STATUS_0_MPUIA_INBAND (shift << 2)
++#define L3_STATUS_0_IVAIA_BRST (shift << 6)
++#define L3_STATUS_0_IVAIA_RSP (shift << 7)
++#define L3_STATUS_0_IVAIA_INBAND (shift << 8)
++#define L3_STATUS_0_SGXIA_BRST (shift << 9)
++#define L3_STATUS_0_SGXIA_RSP (shift << 10)
++#define L3_STATUS_0_SGXIA_MERROR (shift << 11)
++#define L3_STATUS_0_CAMIA_BRST (shift << 12)
++#define L3_STATUS_0_CAMIA_RSP (shift << 13)
++#define L3_STATUS_0_CAMIA_INBAND (shift << 14)
++#define L3_STATUS_0_DISPIA_BRST (shift << 15)
++#define L3_STATUS_0_DISPIA_RSP (shift << 16)
++#define L3_STATUS_0_DMARDIA_BRST (shift << 18)
++#define L3_STATUS_0_DMARDIA_RSP (shift << 19)
++#define L3_STATUS_0_DMAWRIA_BRST (shift << 21)
++#define L3_STATUS_0_DMAWRIA_RSP (shift << 22)
++#define L3_STATUS_0_USBOTGIA_BRST (shift << 24)
++#define L3_STATUS_0_USBOTGIA_RSP (shift << 25)
++#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26)
++#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27)
++#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28)
++#define L3_STATUS_0_SMSTA_REQ (shift << 48)
++#define L3_STATUS_0_GPMCTA_REQ (shift << 49)
++#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50)
++#define L3_STATUS_0_OCMROMTA_REQ (shift << 51)
++#define L3_STATUS_0_IVATA_REQ (shift << 54)
++#define L3_STATUS_0_SGXTA_REQ (shift << 55)
++#define L3_STATUS_0_SGXTA_SERROR (shift << 56)
++#define L3_STATUS_0_GPMCTA_SERROR (shift << 57)
++#define L3_STATUS_0_L4CORETA_REQ (shift << 58)
++#define L3_STATUS_0_L4PERTA_REQ (shift << 59)
++#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
++#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
++
++#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
++ | L3_STATUS_0_MPUIA_RSP \
++ | L3_STATUS_0_IVAIA_BRST \
++ | L3_STATUS_0_IVAIA_RSP \
++ | L3_STATUS_0_SGXIA_BRST \
++ | L3_STATUS_0_SGXIA_RSP \
++ | L3_STATUS_0_CAMIA_BRST \
++ | L3_STATUS_0_CAMIA_RSP \
++ | L3_STATUS_0_DISPIA_BRST \
++ | L3_STATUS_0_DISPIA_RSP \
++ | L3_STATUS_0_DMARDIA_BRST \
++ | L3_STATUS_0_DMARDIA_RSP \
++ | L3_STATUS_0_DMAWRIA_BRST \
++ | L3_STATUS_0_DMAWRIA_RSP \
++ | L3_STATUS_0_USBOTGIA_BRST \
++ | L3_STATUS_0_USBOTGIA_RSP \
++ | L3_STATUS_0_USBHOSTIA_BRST \
++ | L3_STATUS_0_SMSTA_REQ \
++ | L3_STATUS_0_GPMCTA_REQ \
++ | L3_STATUS_0_OCMRAMTA_REQ \
++ | L3_STATUS_0_OCMROMTA_REQ \
++ | L3_STATUS_0_IVATA_REQ \
++ | L3_STATUS_0_SGXTA_REQ \
++ | L3_STATUS_0_L4CORETA_REQ \
++ | L3_STATUS_0_L4PERTA_REQ \
++ | L3_STATUS_0_L4EMUTA_REQ \
++ | L3_STATUS_0_MAD2DTA_REQ)
++
++#define L3_SI_FLAG_STATUS_1 0x530
++
++#define L3_STATUS_1_MPU_DATAIA (1 << 0)
++#define L3_STATUS_1_DAPIA0 (1 << 3)
++#define L3_STATUS_1_DAPIA1 (1 << 4)
++#define L3_STATUS_1_IVAIA (1 << 6)
++
++#define L3_PM_ERROR_LOG 0x020
++#define L3_PM_CONTROL 0x028
++#define L3_PM_ERROR_CLEAR_SINGLE 0x030
++#define L3_PM_ERROR_CLEAR_MULTI 0x038
++#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n))
++#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n))
++#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n))
++#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n))
++
++/* L3 error log bit fields. Common for IA and TA */
++#define L3_ERROR_LOG_CODE 24
++#define L3_ERROR_LOG_INITID 8
++#define L3_ERROR_LOG_CMD 0
++
++/* L3 agent status bit fields. */
++#define L3_AGENT_STATUS_CLEAR_IA 0x10000000
++#define L3_AGENT_STATUS_CLEAR_TA 0x01000000
++
++#define OMAP34xx_IRQ_L3_APP 10
++#define L3_APPLICATION_ERROR 0x0
++#define L3_DEBUG_ERROR 0x1
++
++enum omap3_l3_initiator_id {
++ /* LCD has 1 ID */
++ OMAP_L3_LCD = 29,
++ /* SAD2D has 1 ID */
++ OMAP_L3_SAD2D = 28,
++ /* MPU has 5 IDs */
++ OMAP_L3_IA_MPU_SS_1 = 27,
++ OMAP_L3_IA_MPU_SS_2 = 26,
++ OMAP_L3_IA_MPU_SS_3 = 25,
++ OMAP_L3_IA_MPU_SS_4 = 24,
++ OMAP_L3_IA_MPU_SS_5 = 23,
++ /* IVA2.2 SS has 3 IDs*/
++ OMAP_L3_IA_IVA_SS_1 = 22,
++ OMAP_L3_IA_IVA_SS_2 = 21,
++ OMAP_L3_IA_IVA_SS_3 = 20,
++ /* IVA 2.2 SS DMA has 6 IDS */
++ OMAP_L3_IA_IVA_SS_DMA_1 = 19,
++ OMAP_L3_IA_IVA_SS_DMA_2 = 18,
++ OMAP_L3_IA_IVA_SS_DMA_3 = 17,
++ OMAP_L3_IA_IVA_SS_DMA_4 = 16,
++ OMAP_L3_IA_IVA_SS_DMA_5 = 15,
++ OMAP_L3_IA_IVA_SS_DMA_6 = 14,
++ /* SGX has 1 ID */
++ OMAP_L3_IA_SGX = 13,
++ /* CAM has 3 ID */
++ OMAP_L3_IA_CAM_1 = 12,
++ OMAP_L3_IA_CAM_2 = 11,
++ OMAP_L3_IA_CAM_3 = 10,
++ /* DAP has 1 ID */
++ OMAP_L3_IA_DAP = 9,
++ /* SDMA WR has 2 IDs */
++ OMAP_L3_SDMA_WR_1 = 8,
++ OMAP_L3_SDMA_WR_2 = 7,
++ /* SDMA RD has 4 IDs */
++ OMAP_L3_SDMA_RD_1 = 6,
++ OMAP_L3_SDMA_RD_2 = 5,
++ OMAP_L3_SDMA_RD_3 = 4,
++ OMAP_L3_SDMA_RD_4 = 3,
++ /* HSUSB OTG has 1 ID */
++ OMAP_L3_USBOTG = 2,
++ /* HSUSB HOST has 1 ID */
++ OMAP_L3_USBHOST = 1,
++};
++
++enum omap3_l3_code {
++ OMAP_L3_CODE_NOERROR = 0,
++ OMAP_L3_CODE_UNSUP_CMD = 1,
++ OMAP_L3_CODE_ADDR_HOLE = 2,
++ OMAP_L3_CODE_PROTECT_VIOLATION = 3,
++ OMAP_L3_CODE_IN_BAND_ERR = 4,
++ /* codes 5 and 6 are reserved */
++ OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
++ OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
++ /* codes 9 - 15 are also reserved */
++};
++
++struct omap3_l3 {
++ struct device *dev;
++ struct clk *ick;
++
++ /* memory base*/
++ void __iomem *rt;
++
++ int debug_irq;
++ int app_irq;
++
++ /* true when and inband functional error occurs */
++ unsigned inband:1;
++};
++
++/* offsets for l3 agents in order with the Flag status register */
++unsigned int __iomem omap3_l3_app_bases[] = {
++ /* MPU IA */
++ 0x1400,
++ 0x1400,
++ 0x1400,
++ /* RESERVED */
++ 0,
++ 0,
++ 0,
++ /* IVA 2.2 IA */
++ 0x1800,
++ 0x1800,
++ 0x1800,
++ /* SGX IA */
++ 0x1c00,
++ 0x1c00,
++ /* RESERVED */
++ 0,
++ /* CAMERA IA */
++ 0x5800,
++ 0x5800,
++ 0x5800,
++ /* DISPLAY IA */
++ 0x5400,
++ 0x5400,
++ /* RESERVED */
++ 0,
++ /*SDMA RD IA */
++ 0x4c00,
++ 0x4c00,
++ /* RESERVED */
++ 0,
++ /* SDMA WR IA */
++ 0x5000,
++ 0x5000,
++ /* RESERVED */
++ 0,
++ /* USB OTG IA */
++ 0x4400,
++ 0x4400,
++ 0x4400,
++ /* USB HOST IA */
++ 0x4000,
++ 0x4000,
++ /* RESERVED */
++ 0,
++ 0,
++ 0,
++ 0,
++ /* SAD2D IA */
++ 0x3000,
++ 0x3000,
++ 0x3000,
++ /* RESERVED */
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ 0,
++ /* SMA TA */
++ 0x2000,
++ /* GPMC TA */
++ 0x2400,
++ /* OCM RAM TA */
++ 0x2800,
++ /* OCM ROM TA */
++ 0x2C00,
++ /* L4 CORE TA */
++ 0x6800,
++ /* L4 PER TA */
++ 0x6c00,
++ /* IVA 2.2 TA */
++ 0x6000,
++ /* SGX TA */
++ 0x6400,
++ /* L4 EMU TA */
++ 0x7000,
++ /* GPMC TA */
++ 0x2400,
++ /* L4 CORE TA */
++ 0x6800,
++ /* L4 PER TA */
++ 0x6c00,
++ /* L4 EMU TA */
++ 0x7000,
++ /* MAD2D TA */
++ 0x3400,
++ /* RESERVED */
++ 0,
++ 0,
++};
++
++unsigned int __iomem omap3_l3_debug_bases[] = {
++ /* MPU DATA IA */
++ 0x1400,
++ /* RESERVED */
++ 0,
++ 0,
++ /* DAP IA */
++ 0x5c00,
++ 0x5c00,
++ /* RESERVED */
++ 0,
++ /* IVA 2.2 IA */
++ 0x1800,
++ /* REST RESERVED */
++};
++
++u32 *omap3_l3_bases[] = {
++ omap3_l3_app_bases,
++ omap3_l3_debug_bases,
++};
++
++/*
++ * REVISIT define __raw_readll/__raw_writell here, but move them to
++ * <asm/io.h> at some point
++ */
++#define __raw_writell(v, a) (__chk_io_ptr(a), \
++ *(volatile u64 __force *)(a) = (v))
++#define __raw_readll(a) (__chk_io_ptr(a), \
++ *(volatile u64 __force *)(a))
++
++#endif
+--
+1.7.1
+
diff --git a/patches/for_next/0197-OMAP4-hwmod_data-Add-address-space-and-irq-in-L3-hwm.patch b/patches/for_next/0197-OMAP4-hwmod_data-Add-address-space-and-irq-in-L3-hwm.patch
new file mode 100644
index 0000000000000000000000000000000000000000..cae818443d57890f858f32e9a58aabf5fad9ec24
--- /dev/null
+++ b/patches/for_next/0197-OMAP4-hwmod_data-Add-address-space-and-irq-in-L3-hwm.patch
@@ -0,0 +1,103 @@
+From b74a3b6f41e85cb05ae889c4a118287d3c680c76 Mon Sep 17 00:00:00 2001
+From: sricharan <r.sricharan@ti.com>
+Date: Mon, 7 Feb 2011 21:12:11 +0530
+Subject: [PATCH 197/254] OMAP4: hwmod_data: Add address space and irq in L3 hwmod.
+
+Add the address spaces, irqs of the l3 interconnect to the
+hwmod data. The hwmod change is aligned with Benoit Cousson.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 38 ++++++++++++++++++++++++++++
+ 1 files changed, 38 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+index ee60325..eaef28f 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+@@ -263,11 +263,27 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
++/* L3 target configuration and error log registers */
++static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
++ { .irq = 9 + OMAP44XX_IRQ_GIC_START },
++ { .irq = 10 + OMAP44XX_IRQ_GIC_START },
++};
++
++static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
++ {
++ .pa_start = 0x44000000,
++ .pa_end = 0x44000fff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
+ /* mpu -> l3_main_1 */
+ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+ .master = &omap44xx_mpu_hwmod,
+ .slave = &omap44xx_l3_main_1_hwmod,
+ .clk = "l3_div_ck",
++ .addr = omap44xx_l3_main_1_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -285,6 +301,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+ .name = "l3_main_1",
+ .class = &omap44xx_l3_hwmod_class,
++ .mpu_irqs = omap44xx_l3_targ_irqs,
++ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
+ .slaves = omap44xx_l3_main_1_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+@@ -331,11 +349,21 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
++static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
++ {
++ .pa_start = 0x44800000,
++ .pa_end = 0x44801fff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
+ /* l3_main_1 -> l3_main_2 */
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_l3_main_2_hwmod,
+ .clk = "l3_div_ck",
++ .addr = omap44xx_l3_main_2_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+@@ -376,11 +404,21 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+ };
+
+ /* l3_main_3 interface data */
++static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
++ {
++ .pa_start = 0x45000000,
++ .pa_end = 0x45000fff,
++ .flags = ADDR_TYPE_RT,
++ },
++};
++
+ /* l3_main_1 -> l3_main_3 */
+ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+ .master = &omap44xx_l3_main_1_hwmod,
+ .slave = &omap44xx_l3_main_3_hwmod,
+ .clk = "l3_div_ck",
++ .addr = omap44xx_l3_main_3_addrs,
++ .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0198-OMAP4-Initialise-the-l3-device-with-the-hwmod-data.patch b/patches/for_next/0198-OMAP4-Initialise-the-l3-device-with-the-hwmod-data.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2274b9ea07a9025274ce97a05aa9985da00f1913
--- /dev/null
+++ b/patches/for_next/0198-OMAP4-Initialise-the-l3-device-with-the-hwmod-data.patch
@@ -0,0 +1,69 @@
+From 8ad7c525e55ed541e443a7abb78fd5beab30faae Mon Sep 17 00:00:00 2001
+From: sricharan <r.sricharan@ti.com>
+Date: Wed, 9 Mar 2011 16:00:29 +0530
+Subject: [PATCH 198/254] OMAP4: Initialise the l3 device with the hwmod data.
+
+The l3 interconnect device is build with all the data required
+to handle the error logging. The data is extracted from the
+hwmod data base.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/devices.c | 32 ++++++++++++++++++++++++++++++++
+ 1 files changed, 32 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
+index 6a320b6..0d2d6a9 100644
+--- a/arch/arm/mach-omap2/devices.c
++++ b/arch/arm/mach-omap2/devices.c
+@@ -37,6 +37,7 @@
+ #include "control.h"
+
+ #define L3_MODULES_MAX_LEN 12
++#define L3_MODULES 3
+
+ static int __init omap3_l3_init(void)
+ {
+@@ -68,6 +69,37 @@ static int __init omap3_l3_init(void)
+ }
+ postcore_initcall(omap3_l3_init);
+
++static int __init omap4_l3_init(void)
++{
++ int l, i;
++ struct omap_hwmod *oh[3];
++ struct omap_device *od;
++ char oh_name[L3_MODULES_MAX_LEN];
++
++ /*
++ * To avoid code running on other OMAPs in
++ * multi-omap builds
++ */
++ if (!(cpu_is_omap44xx()))
++ return -ENODEV;
++
++ for (i = 0; i < L3_MODULES; i++) {
++ l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
++
++ oh[i] = omap_hwmod_lookup(oh_name);
++ if (!(oh[i]))
++ pr_err("could not look up %s\n", oh_name);
++ }
++
++ od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
++ 0, NULL, 0, 0);
++
++ WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
++
++ return PTR_ERR(od);
++}
++postcore_initcall(omap4_l3_init);
++
+ #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
+
+ static struct resource cam_resources[] = {
+--
+1.7.1
+
diff --git a/patches/for_next/0199-OMAP4-l3-Introduce-l3-interconnect-error-handling-dr.patch b/patches/for_next/0199-OMAP4-l3-Introduce-l3-interconnect-error-handling-dr.patch
new file mode 100644
index 0000000000000000000000000000000000000000..14f52d876adce2237907e0c8b0ed553001fa65a0
--- /dev/null
+++ b/patches/for_next/0199-OMAP4-l3-Introduce-l3-interconnect-error-handling-dr.patch
@@ -0,0 +1,433 @@
+From 3a9a19ade917b9ce62558a33a42341a208b347ee Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Mon, 7 Mar 2011 20:53:10 +0530
+Subject: [PATCH 199/254] OMAP4: l3: Introduce l3-interconnect error handling driver
+
+The driver provides the information regarding the ocp errors
+that gets logged in the interconnect. The error information
+gives the detail regarding the target that was attempted
+to be accessed and its corresponding address.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 1 +
+ arch/arm/mach-omap2/omap_l3_noc.c | 253 +++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/omap_l3_noc.h | 132 +++++++++++++++++++
+ 3 files changed, 386 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/omap_l3_noc.c
+ create mode 100644 arch/arm/mach-omap2/omap_l3_noc.h
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index eb35111..534d89a 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -143,6 +143,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o
+
+ # L3 interconnect
+ obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
++obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
+
+ obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
+ mailbox_mach-objs := mailbox.o
+diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
+new file mode 100644
+index 0000000..82632c2
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap_l3_noc.c
+@@ -0,0 +1,253 @@
++/*
++ * OMAP4XXX L3 Interconnect error handling driver
++ *
++ * Copyright (C) 2011 Texas Corporation
++ * Santosh Shilimkar <santosh.shilimkar@ti.com>
++ * Sricharan <r.sricharan@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
++ * USA
++ */
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++
++#include "omap_l3_noc.h"
++
++/*
++ * Interrupt Handler for L3 error detection.
++ * 1) Identify the L3 clockdomain partition to which the error belongs to.
++ * 2) Identify the slave where the error information is logged
++ * 3) Print the logged information.
++ * 4) Add dump stack to provide kernel trace.
++ *
++ * Two Types of errors :
++ * 1) Custom errors in L3 :
++ * Target like DMM/FW/EMIF generates SRESP=ERR error
++ * 2) Standard L3 error:
++ * - Unsupported CMD.
++ * L3 tries to access target while it is idle
++ * - OCP disconnect.
++ * - Address hole error:
++ * If DSS/ISS/FDIF/USBHOSTFS access a target where they
++ * do not have connectivity, the error is logged in
++ * their default target which is DMM2.
++ *
++ * On High Secure devices, firewall errors are possible and those
++ * can be trapped as well. But the trapping is implemented as part
++ * secure software and hence need not be implemented here.
++ */
++static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
++{
++
++ struct omap4_l3 *l3 = _l3;
++ int inttype, i, j;
++ int err_src = 0;
++ u32 std_err_main_addr, std_err_main, err_reg;
++ u32 base, slave_addr, clear;
++ char *source_name;
++
++ /* Get the Type of interrupt */
++ if (irq == l3->app_irq)
++ inttype = L3_APPLICATION_ERROR;
++ else
++ inttype = L3_DEBUG_ERROR;
++
++ for (i = 0; i < L3_MODULES; i++) {
++ /*
++ * Read the regerr register of the clock domain
++ * to determine the source
++ */
++ base = (u32)l3->l3_base[i];
++ err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
++
++ /* Get the corresponding error and analyse */
++ if (err_reg) {
++ /* Identify the source from control status register */
++ for (j = 0; !(err_reg & (1 << j)); j++)
++ ;
++
++ err_src = j;
++ /* Read the stderrlog_main_source from clk domain */
++ std_err_main_addr = base + (*(l3_targ[i] + err_src));
++ std_err_main = readl(std_err_main_addr);
++
++ switch ((std_err_main & CUSTOM_ERROR)) {
++ case STANDARD_ERROR:
++ source_name =
++ l3_targ_stderrlog_main_name[i][err_src];
++
++ slave_addr = std_err_main_addr +
++ L3_SLAVE_ADDRESS_OFFSET;
++ WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
++ source_name, readl(slave_addr));
++ /* clear the std error log*/
++ clear = std_err_main | CLEAR_STDERR_LOG;
++ writel(clear, std_err_main_addr);
++ break;
++
++ case CUSTOM_ERROR:
++ source_name =
++ l3_targ_stderrlog_main_name[i][err_src];
++
++ WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
++ source_name);
++ /* clear the std error log*/
++ clear = std_err_main | CLEAR_STDERR_LOG;
++ writel(clear, std_err_main_addr);
++ break;
++
++ default:
++ /* Nothing to be handled here as of now */
++ break;
++ }
++ /* Error found so break the for loop */
++ break;
++ }
++ }
++ return IRQ_HANDLED;
++}
++
++static int __init omap4_l3_probe(struct platform_device *pdev)
++{
++ static struct omap4_l3 *l3;
++ struct resource *res;
++ int ret;
++ int irq;
++
++ l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
++ if (!l3)
++ ret = -ENOMEM;
++
++ platform_set_drvdata(pdev, l3);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "couldn't find resource 0\n");
++ ret = -ENODEV;
++ goto err1;
++ }
++
++ l3->l3_base[0] = ioremap(res->start, resource_size(res));
++ if (!(l3->l3_base[0])) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto err2;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ if (!res) {
++ dev_err(&pdev->dev, "couldn't find resource 1\n");
++ ret = -ENODEV;
++ goto err3;
++ }
++
++ l3->l3_base[1] = ioremap(res->start, resource_size(res));
++ if (!(l3->l3_base[1])) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto err4;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
++ if (!res) {
++ dev_err(&pdev->dev, "couldn't find resource 2\n");
++ ret = -ENODEV;
++ goto err5;
++ }
++
++ l3->l3_base[2] = ioremap(res->start, resource_size(res));
++ if (!(l3->l3_base[2])) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto err6;
++ }
++
++ /*
++ * Setup interrupt Handlers
++ */
++ irq = platform_get_irq(pdev, 0);
++ ret = request_irq(irq,
++ l3_interrupt_handler,
++ IRQF_DISABLED, "l3-dbg-irq", l3);
++ if (ret) {
++ pr_crit("L3: request_irq failed to register for 0x%x\n",
++ OMAP44XX_IRQ_L3_DBG);
++ goto err7;
++ }
++ l3->debug_irq = irq;
++
++ irq = platform_get_irq(pdev, 1);
++ ret = request_irq(irq,
++ l3_interrupt_handler,
++ IRQF_DISABLED, "l3-app-irq", l3);
++ if (ret) {
++ pr_crit("L3: request_irq failed to register for 0x%x\n",
++ OMAP44XX_IRQ_L3_APP);
++ goto err8;
++ }
++ l3->app_irq = irq;
++
++ goto err0;
++err8:
++err7:
++ iounmap(l3->l3_base[2]);
++err6:
++err5:
++ iounmap(l3->l3_base[1]);
++err4:
++err3:
++ iounmap(l3->l3_base[0]);
++err2:
++err1:
++ kfree(l3);
++err0:
++ return ret;
++}
++
++static int __exit omap4_l3_remove(struct platform_device *pdev)
++{
++ struct omap4_l3 *l3 = platform_get_drvdata(pdev);
++
++ free_irq(l3->app_irq, l3);
++ free_irq(l3->debug_irq, l3);
++ iounmap(l3->l3_base[0]);
++ iounmap(l3->l3_base[1]);
++ iounmap(l3->l3_base[2]);
++ kfree(l3);
++
++ return 0;
++}
++
++static struct platform_driver omap4_l3_driver = {
++ .remove = __exit_p(omap4_l3_remove),
++ .driver = {
++ .name = "omap_l3_noc",
++ },
++};
++
++static int __init omap4_l3_init(void)
++{
++ return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
++}
++postcore_initcall_sync(omap4_l3_init);
++
++static void __exit omap4_l3_exit(void)
++{
++ platform_driver_unregister(&omap4_l3_driver);
++}
++module_exit(omap4_l3_exit);
+diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
+new file mode 100644
+index 0000000..359b833
+--- /dev/null
++++ b/arch/arm/mach-omap2/omap_l3_noc.h
+@@ -0,0 +1,132 @@
++ /*
++ * OMAP4XXX L3 Interconnect error handling driver header
++ *
++ * Copyright (C) 2011 Texas Corporation
++ * Santosh Shilimkar <santosh.shilimkar@ti.com>
++ * sricharan <r.sricharan@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
++ * USA
++ */
++#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
++#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
++
++/*
++ * L3 register offsets
++ */
++#define L3_MODULES 3
++#define CLEAR_STDERR_LOG (1 << 31)
++#define CUSTOM_ERROR 0x2
++#define STANDARD_ERROR 0x0
++#define INBAND_ERROR 0x0
++#define EMIF_KERRLOG_OFFSET 0x10
++#define L3_SLAVE_ADDRESS_OFFSET 0x14
++#define LOGICAL_ADDR_ERRORLOG 0x4
++#define L3_APPLICATION_ERROR 0x0
++#define L3_DEBUG_ERROR 0x1
++
++u32 l3_flagmux[L3_MODULES] = {
++ 0x50C,
++ 0x100C,
++ 0X020C
++};
++
++/*
++ * L3 Target standard Error register offsets
++ */
++u32 l3_targ_stderrlog_main_clk1[] = {
++ 0x148, /* DMM1 */
++ 0x248, /* DMM2 */
++ 0x348, /* ABE */
++ 0x448, /* L4CFG */
++ 0x648 /* CLK2 PWR DISC */
++};
++
++u32 l3_targ_stderrlog_main_clk2[] = {
++ 0x548, /* CORTEX M3 */
++ 0x348, /* DSS */
++ 0x148, /* GPMC */
++ 0x448, /* ISS */
++ 0x748, /* IVAHD */
++ 0xD48, /* missing in TRM corresponds to AES1*/
++ 0x948, /* L4 PER0*/
++ 0x248, /* OCMRAM */
++ 0x148, /* missing in TRM corresponds to GPMC sERROR*/
++ 0x648, /* SGX */
++ 0x848, /* SL2 */
++ 0x1648, /* C2C */
++ 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
++ 0xF48, /* missing in TRM corrsponds to SHA1*/
++ 0xE48, /* missing in TRM corresponds to AES2*/
++ 0xC48, /* L4 PER3 */
++ 0xA48, /* L4 PER1*/
++ 0xB48 /* L4 PER2*/
++};
++
++u32 l3_targ_stderrlog_main_clk3[] = {
++ 0x0148 /* EMUSS */
++};
++
++char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
++ {
++ "DMM1",
++ "DMM2",
++ "ABE",
++ "L4CFG",
++ "CLK2 PWR DISC",
++ },
++ {
++ "CORTEX M3" ,
++ "DSS ",
++ "GPMC ",
++ "ISS ",
++ "IVAHD ",
++ "AES1",
++ "L4 PER0",
++ "OCMRAM ",
++ "GPMC sERROR",
++ "SGX ",
++ "SL2 ",
++ "C2C ",
++ "PWR DISC CLK1",
++ "SHA1",
++ "AES2",
++ "L4 PER3",
++ "L4 PER1",
++ "L4 PER2",
++ },
++ {
++ "EMUSS",
++ },
++};
++
++u32 *l3_targ[L3_MODULES] = {
++ l3_targ_stderrlog_main_clk1,
++ l3_targ_stderrlog_main_clk2,
++ l3_targ_stderrlog_main_clk3,
++};
++
++struct omap4_l3 {
++ struct device *dev;
++ struct clk *ick;
++
++ /* memory base */
++ void __iomem *l3_base[4];
++
++ int debug_irq;
++ int app_irq;
++};
++
++#endif
+--
+1.7.1
+
diff --git a/patches/for_next/0200-OMAP2-3-VENC-hwmod-add-OCPIF_SWSUP_IDLE-flag-to-inte.patch b/patches/for_next/0200-OMAP2-3-VENC-hwmod-add-OCPIF_SWSUP_IDLE-flag-to-inte.patch
new file mode 100644
index 0000000000000000000000000000000000000000..29d9599c1684b843c2a10117a47087b7ebf2315a
--- /dev/null
+++ b/patches/for_next/0200-OMAP2-3-VENC-hwmod-add-OCPIF_SWSUP_IDLE-flag-to-inte.patch
@@ -0,0 +1,80 @@
+From 7938d8418cc2857ff8c0a2227f41cac08940ae7b Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Fri, 4 Mar 2011 06:02:15 +0000
+Subject: [PATCH 200/254] OMAP2/3: VENC hwmod: add OCPIF_SWSUP_IDLE flag to interface
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+According to the hwmod interface data, the DSS submodule "VENC" uses a
+clock, "dss_54m_fck"/"dss_tv_fck", which the PRCM cannot autoidle. By
+default, the hwmod code assumes that interface clocks can be autoidled
+by the PRCM. When the interface clock can't be autoidled by the PRCM,
+those interfaces must be marked with the OCPIF_SWSUP_IDLE flag.
+Otherwise, the "interface clock" will always have a non-zero use
+count, and the device won't enter idle. This problem was observed on
+N8x0.
+
+Fix the immediate problem by marking the VENC interface with the
+OCPIF_SWSUP_IDLE flag. But it's not clear that
+"dss_54m_fck"/"dss_tv_fck" is really the correct interface clock for
+VENC. It may be that the VENC interface should use a
+hardware-autoidling interface clock. This is the situation on OMAP4,
+which uses "l3_div_ck" as the VENC interface clock, which can be
+autoidled by the PRCM. Clarification from TI is needed.
+
+Problem found and patch tested on N8x0 by Tony Lindgren
+<tony@atomide.com>.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Cc: Senthilvadivu Guruswamy <svadivu@ti.com>
+Cc: Sumit Semwal <sumit.semwal@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Cc: Benoît Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 1 +
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 1 +
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 1 +
+ 3 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index e0bc2c7..61e58bd 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -1410,6 +1410,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
++ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index abb3574..0da754e 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -1485,6 +1485,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
+ .clk = "dss_54m_fck",
+ .addr = omap2430_dss_venc_addrs,
+ .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
++ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 1d10389..d0d1d8f 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1859,6 +1859,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+ .flags = OMAP_FIREWALL_L4,
+ }
+ },
++ .flags = OCPIF_SWSUP_IDLE,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+ };
+
+--
+1.7.1
+
diff --git a/patches/dvfs/for-2.6.39/0001-MAINTAINERS-update-Kevin-s-email-for-OMAP-PM-section.patch b/patches/for_next/0201-MAINTAINERS-update-Kevin-s-email-for-OMAP-PM-section.patch
similarity index 72%
rename from patches/dvfs/for-2.6.39/0001-MAINTAINERS-update-Kevin-s-email-for-OMAP-PM-section.patch
rename to patches/for_next/0201-MAINTAINERS-update-Kevin-s-email-for-OMAP-PM-section.patch
index fca58f08e471b0ccebcb39c5a70b702a4f6efb18..34cb9b11ea7b8f36f45834b30f81edb584033dae 100644
--- a/patches/dvfs/for-2.6.39/0001-MAINTAINERS-update-Kevin-s-email-for-OMAP-PM-section.patch
+++ b/patches/for_next/0201-MAINTAINERS-update-Kevin-s-email-for-OMAP-PM-section.patch
@@ -1,7 +1,7 @@
-From 95c1a64ae0dd3b5830a275ecae95267cdd4b738a Mon Sep 17 00:00:00 2001
+From a4b88a8396369eb0abdbca56f85a0401a1faf31d Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman@ti.com>
Date: Tue, 4 Jan 2011 15:33:08 -0800
-Subject: [PATCH 01/10] MAINTAINERS: update Kevin's email for OMAP PM section
+Subject: [PATCH 201/254] MAINTAINERS: update Kevin's email for OMAP PM section
Change my email to TI email address for OMAP PM maintenance.
@@ -11,10 +11,10 @@ Signed-off-by: Kevin Hilman <khilman@ti.com>
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
-index 8afba63..6a58c8d 100644
+index 560ecce..939e852 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -4491,7 +4491,7 @@ S: Maintained
+@@ -4501,7 +4501,7 @@ S: Maintained
F: arch/arm/*omap*/*clock*
OMAP POWER MANAGEMENT SUPPORT
diff --git a/patches/dvfs/for-2.6.39/0002-OMAP3630-PM-don-t-warn-the-user-with-a-trace-in-case.patch b/patches/for_next/0202-OMAP3630-PM-don-t-warn-the-user-with-a-trace-in-case.patch
similarity index 84%
rename from patches/dvfs/for-2.6.39/0002-OMAP3630-PM-don-t-warn-the-user-with-a-trace-in-case.patch
rename to patches/for_next/0202-OMAP3630-PM-don-t-warn-the-user-with-a-trace-in-case.patch
index c94283047e6aa717271e0df5a5787205c0029374..bb982dbba0a62e39e9860c89f036a74cd26ce32c 100644
--- a/patches/dvfs/for-2.6.39/0002-OMAP3630-PM-don-t-warn-the-user-with-a-trace-in-case.patch
+++ b/patches/for_next/0202-OMAP3630-PM-don-t-warn-the-user-with-a-trace-in-case.patch
@@ -1,7 +1,7 @@
-From f1c987b37dbec67d33df0ff36647cfc1c47c82bd Mon Sep 17 00:00:00 2001
+From 16d99a2aa23e6ea23aa51e04a8f3e998084d64fb Mon Sep 17 00:00:00 2001
From: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
Date: Mon, 31 Jan 2011 11:35:25 -0200
-Subject: [PATCH 02/10] OMAP3630: PM: don't warn the user with a trace in case of PM34XX_ERRATUM
+Subject: [PATCH 202/254] OMAP3630: PM: don't warn the user with a trace in case of PM34XX_ERRATUM
In case in user has a OMAP3630 < ES1.2 the kernel should warn the user
about the ERRATUM, but using pr_warn instead of WARN_ON is already
@@ -16,7 +16,7 @@ Signed-off-by: Kevin Hilman <khilman@ti.com>
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
-index f7b22a1..876eeca 100644
+index 7cc8071..4331498 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -464,7 +464,7 @@ void omap_init_power_states(void)
@@ -29,10 +29,10 @@ index f7b22a1..876eeca 100644
}
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
-index 2f864e4..6ade4ea 100644
+index 3d6a00e..a3f725f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
-@@ -928,8 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
+@@ -808,8 +808,7 @@ void omap3_pm_off_mode_enable(int enable)
pwrst->pwrdm == core_pwrdm &&
state == PWRDM_POWER_OFF) {
pwrst->next_state = PWRDM_POWER_RET;
diff --git a/patches/dvfs/for-2.6.39/0003-OMAP3-4-OPP-make-omapx_opp_init-non-static.patch b/patches/for_next/0203-OMAP3-4-OPP-make-omapx_opp_init-non-static.patch
similarity index 93%
rename from patches/dvfs/for-2.6.39/0003-OMAP3-4-OPP-make-omapx_opp_init-non-static.patch
rename to patches/for_next/0203-OMAP3-4-OPP-make-omapx_opp_init-non-static.patch
index 9976908d3ff7833a2220675c0ee102e9037eb10d..a9b4ab2346c8475dee30f78c364910f025af09a4 100644
--- a/patches/dvfs/for-2.6.39/0003-OMAP3-4-OPP-make-omapx_opp_init-non-static.patch
+++ b/patches/for_next/0203-OMAP3-4-OPP-make-omapx_opp_init-non-static.patch
@@ -1,7 +1,7 @@
-From 48d72409c62bf155dd61280cff7bbc858dc0bbb3 Mon Sep 17 00:00:00 2001
+From b249d9d27fd61322d937db360d78d9a3454dc63d Mon Sep 17 00:00:00 2001
From: Menon, Nishanth <nm@ti.com>
Date: Wed, 5 Jan 2011 20:49:35 +0000
-Subject: [PATCH 03/10] OMAP3|4: OPP: make omapx_opp_init non-static
+Subject: [PATCH 203/254] OMAP3|4: OPP: make omapx_opp_init non-static
omap3 and omap4 opp_init should be made non-static to allow
for platform specific opp table tweaking. making these static
diff --git a/patches/dvfs/for-2.6.39/0004-OMAP3-beagle-xm-enable-up-to-800MHz-OPP.patch b/patches/for_next/0204-OMAP3-beagle-xm-enable-up-to-800MHz-OPP.patch
similarity index 90%
rename from patches/dvfs/for-2.6.39/0004-OMAP3-beagle-xm-enable-up-to-800MHz-OPP.patch
rename to patches/for_next/0204-OMAP3-beagle-xm-enable-up-to-800MHz-OPP.patch
index 166c7e6e6f71e18dcc21f6b1846d10aeb7f30cd0..c7b269dbffa655ecd2bbeeee9a8b765dfb0990b3 100644
--- a/patches/dvfs/for-2.6.39/0004-OMAP3-beagle-xm-enable-up-to-800MHz-OPP.patch
+++ b/patches/for_next/0204-OMAP3-beagle-xm-enable-up-to-800MHz-OPP.patch
@@ -1,7 +1,7 @@
-From 30e21dcfcd931372c108a0cadf2bf6cb55716879 Mon Sep 17 00:00:00 2001
+From 9fb4af0fa0a37922adfade4635a8064cbe9f68d9 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Fri, 7 Jan 2011 09:41:13 -0600
-Subject: [PATCH 04/10] OMAP3: beagle xm: enable up to 800MHz OPP
+Subject: [PATCH 204/254] OMAP3: beagle xm: enable up to 800MHz OPP
OMP3630 silicon can enable higher frequencies only depending on the board
characteristics meeting the recommended standards, and has to be selectively
@@ -22,7 +22,7 @@ Signed-off-by: Kevin Hilman <khilman@ti.com>
1 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index 46d814a..91b4e14 100644
+index b6752ac..20c5dbe 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -23,6 +23,7 @@
@@ -46,7 +46,7 @@ index 46d814a..91b4e14 100644
#define NAND_BLOCK_SIZE SZ_128K
-@@ -610,6 +613,52 @@ static struct omap_musb_board_data musb_board_data = {
+@@ -603,6 +606,52 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
@@ -99,7 +99,7 @@ index 46d814a..91b4e14 100644
static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-@@ -633,6 +682,7 @@ static void __init omap3_beagle_init(void)
+@@ -627,6 +676,7 @@ static void __init omap3_beagle_init(void)
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
beagle_display_init();
diff --git a/patches/dvfs/for-2.6.39/0005-OMAP-PM-SmartReflex-fix-potential-NULL-dereference.patch b/patches/for_next/0205-OMAP-PM-SmartReflex-fix-potential-NULL-dereference.patch
similarity index 86%
rename from patches/dvfs/for-2.6.39/0005-OMAP-PM-SmartReflex-fix-potential-NULL-dereference.patch
rename to patches/for_next/0205-OMAP-PM-SmartReflex-fix-potential-NULL-dereference.patch
index 6109f3fa67ef7e15e475efd686b0bfeb97477150..def9d6c77aad600c16e143384e902cb990e2bae6 100644
--- a/patches/dvfs/for-2.6.39/0005-OMAP-PM-SmartReflex-fix-potential-NULL-dereference.patch
+++ b/patches/for_next/0205-OMAP-PM-SmartReflex-fix-potential-NULL-dereference.patch
@@ -1,7 +1,7 @@
-From 538b274aaac2a84c13401759aca6b2e571fb1cdd Mon Sep 17 00:00:00 2001
+From 95b25a406404005a183b95c22ddd06aa7a875ac3 Mon Sep 17 00:00:00 2001
From: Vasiliy Kulikov <segoon@openwall.com>
Date: Wed, 19 Jan 2011 15:57:22 +0300
-Subject: [PATCH 05/10] OMAP: PM: SmartReflex: fix potential NULL dereference
+Subject: [PATCH 205/254] OMAP: PM: SmartReflex: fix potential NULL dereference
kzalloc() may fail, if so return -ENOMEM. Also Walter Harms suggested
to use kasprintf() instead of kzalloc+strcpy+strcat.
@@ -13,7 +13,7 @@ Signed-off-by: Kevin Hilman <khilman@ti.com>
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
-index 95ac336..a1f532e 100644
+index 81e23eb..2566552 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -260,9 +260,11 @@ static int sr_late_init(struct omap_sr *sr_info)
diff --git a/patches/dvfs/for-2.6.39/0006-OMAP2-remove-unused-UART-base-addresses-from-omap_gl.patch b/patches/for_next/0206-OMAP2-remove-unused-UART-base-addresses-from-omap_gl.patch
similarity index 90%
rename from patches/dvfs/for-2.6.39/0006-OMAP2-remove-unused-UART-base-addresses-from-omap_gl.patch
rename to patches/for_next/0206-OMAP2-remove-unused-UART-base-addresses-from-omap_gl.patch
index 6f69fcce810c895a754174e9e0459d14a78879c3..b38d3b378899d9f05ce9f6b1a0d4071ef8e2a84b 100644
--- a/patches/dvfs/for-2.6.39/0006-OMAP2-remove-unused-UART-base-addresses-from-omap_gl.patch
+++ b/patches/for_next/0206-OMAP2-remove-unused-UART-base-addresses-from-omap_gl.patch
@@ -1,7 +1,7 @@
-From 110655bb8832e52170d2d2ed952304704f27669c Mon Sep 17 00:00:00 2001
+From e75edd75be9544cef711443c4b93b5349b97abc9 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman@ti.com>
Date: Fri, 21 Jan 2011 14:30:15 -0800
-Subject: [PATCH 06/10] OMAP2+: remove unused UART base addresses from omap_globals
+Subject: [PATCH 206/254] OMAP2+: remove unused UART base addresses from omap_globals
Now that omap_hwmod + omap_device is used for OMAP UART device and
driver code, we no longer need the UART physical addresses in
@@ -19,7 +19,7 @@ Signed-off-by: Kevin Hilman <khilman@ti.com>
2 files changed, 0 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
-index 778929f..994f0f0 100644
+index 48de451..3f20cbb 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -50,9 +50,6 @@ static struct omap_globals omap242x_globals = {
@@ -53,7 +53,7 @@ index 778929f..994f0f0 100644
};
void __init omap2_set_globals_3xxx(void)
-@@ -119,10 +109,6 @@ static struct omap_globals omap4_globals = {
+@@ -140,10 +130,6 @@ static struct omap_globals omap4_globals = {
.prm = OMAP4430_PRM_BASE,
.cm = OMAP4430_CM_BASE,
.cm2 = OMAP4430_CM2_BASE,
@@ -65,7 +65,7 @@ index 778929f..994f0f0 100644
void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
-index 29b2afb..1b8095b 100644
+index 1dd97e7..5288130 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -56,10 +56,6 @@ struct omap_globals {
diff --git a/patches/for_next/0207-OMAP2-3-PM-remove-unnecessary-wakeup-sleep-dependenc.patch b/patches/for_next/0207-OMAP2-3-PM-remove-unnecessary-wakeup-sleep-dependenc.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7a7a6ee09cee330a1367aa6c3c18a3f907a8da31
--- /dev/null
+++ b/patches/for_next/0207-OMAP2-3-PM-remove-unnecessary-wakeup-sleep-dependenc.patch
@@ -0,0 +1,172 @@
+From cc04eb0b75571ed0caf0ce1f5de96a14f270fca2 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Thu, 27 Jan 2011 02:52:55 -0700
+Subject: [PATCH 207/254] OMAP2/3: PM: remove unnecessary wakeup/sleep dependency clear
+
+The OMAP2 and OMAP3 PM code clears clockdomain wakeup and sleep
+dependencies. This is unnecessary after commit
+6f7f63cc9adf3192e6fcac4e8bed5cc10fd924aa ("OMAP clockdomain:
+initialize clockdomain registers when the clockdomain layer starts")
+which clears these dependencies during clockdomain init.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/pm24xx.c | 8 +---
+ arch/arm/mach-omap2/pm34xx.c | 112 +++++++++++++++++++++++++++++++++++++-----
+ 2 files changed, 100 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
+index 96907da..df3ded6 100644
+--- a/arch/arm/mach-omap2/pm24xx.c
++++ b/arch/arm/mach-omap2/pm24xx.c
+@@ -363,9 +363,6 @@ static const struct platform_suspend_ops __initdata omap_pm_ops;
+ /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
+ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+ {
+- clkdm_clear_all_wkdeps(clkdm);
+- clkdm_clear_all_sleepdeps(clkdm);
+-
+ if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+ clkdm_allow_idle(clkdm);
+ else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+@@ -414,10 +411,7 @@ static void __init prcm_setup_regs(void)
+ pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
+ clkdm_sleep(gfx_clkdm);
+
+- /*
+- * Clear clockdomain wakeup dependencies and enable
+- * hardware-supervised idle for all clkdms
+- */
++ /* Enable hardware-supervised idle for all clkdms */
+ clkdm_for_each(clkdms_setup, NULL);
+ clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
+
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index a3f725f..4f50cac 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
++++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -693,21 +693,107 @@ static void __init prcm_setup_regs(void)
+ u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
+ OMAP3630_GRPSEL_UART4_MASK : 0;
+
+- /* XXX Reset all wkdeps. This should be done when initializing
+- * powerdomains */
+- omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+- omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
+- omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
+- omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
+- omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
+- omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
++ /*
++ * Enable interface clock autoidle for all modules.
++ * Note that in the long run this should be done by clockfw
++ */
++ omap2_cm_write_mod_reg(
++ OMAP3430_AUTO_MODEM_MASK |
++ OMAP3430ES2_AUTO_MMC3_MASK |
++ OMAP3430ES2_AUTO_ICR_MASK |
++ OMAP3430_AUTO_AES2_MASK |
++ OMAP3430_AUTO_SHA12_MASK |
++ OMAP3430_AUTO_DES2_MASK |
++ OMAP3430_AUTO_MMC2_MASK |
++ OMAP3430_AUTO_MMC1_MASK |
++ OMAP3430_AUTO_MSPRO_MASK |
++ OMAP3430_AUTO_HDQ_MASK |
++ OMAP3430_AUTO_MCSPI4_MASK |
++ OMAP3430_AUTO_MCSPI3_MASK |
++ OMAP3430_AUTO_MCSPI2_MASK |
++ OMAP3430_AUTO_MCSPI1_MASK |
++ OMAP3430_AUTO_I2C3_MASK |
++ OMAP3430_AUTO_I2C2_MASK |
++ OMAP3430_AUTO_I2C1_MASK |
++ OMAP3430_AUTO_UART2_MASK |
++ OMAP3430_AUTO_UART1_MASK |
++ OMAP3430_AUTO_GPT11_MASK |
++ OMAP3430_AUTO_GPT10_MASK |
++ OMAP3430_AUTO_MCBSP5_MASK |
++ OMAP3430_AUTO_MCBSP1_MASK |
++ OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
++ OMAP3430_AUTO_MAILBOXES_MASK |
++ OMAP3430_AUTO_OMAPCTRL_MASK |
++ OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
++ OMAP3430_AUTO_HSOTGUSB_MASK |
++ OMAP3430_AUTO_SAD2D_MASK |
++ OMAP3430_AUTO_SSI_MASK,
++ CORE_MOD, CM_AUTOIDLE1);
++
++ omap2_cm_write_mod_reg(
++ OMAP3430_AUTO_PKA_MASK |
++ OMAP3430_AUTO_AES1_MASK |
++ OMAP3430_AUTO_RNG_MASK |
++ OMAP3430_AUTO_SHA11_MASK |
++ OMAP3430_AUTO_DES1_MASK,
++ CORE_MOD, CM_AUTOIDLE2);
++
++ if (omap_rev() > OMAP3430_REV_ES1_0) {
++ omap2_cm_write_mod_reg(
++ OMAP3430_AUTO_MAD2D_MASK |
++ OMAP3430ES2_AUTO_USBTLL_MASK,
++ CORE_MOD, CM_AUTOIDLE3);
++ }
++
++ omap2_cm_write_mod_reg(
++ OMAP3430_AUTO_WDT2_MASK |
++ OMAP3430_AUTO_WDT1_MASK |
++ OMAP3430_AUTO_GPIO1_MASK |
++ OMAP3430_AUTO_32KSYNC_MASK |
++ OMAP3430_AUTO_GPT12_MASK |
++ OMAP3430_AUTO_GPT1_MASK,
++ WKUP_MOD, CM_AUTOIDLE);
++
++ omap2_cm_write_mod_reg(
++ OMAP3430_AUTO_DSS_MASK,
++ OMAP3430_DSS_MOD,
++ CM_AUTOIDLE);
++
++ omap2_cm_write_mod_reg(
++ OMAP3430_AUTO_CAM_MASK,
++ OMAP3430_CAM_MOD,
++ CM_AUTOIDLE);
++
++ omap2_cm_write_mod_reg(
++ omap3630_auto_uart4_mask |
++ OMAP3430_AUTO_GPIO6_MASK |
++ OMAP3430_AUTO_GPIO5_MASK |
++ OMAP3430_AUTO_GPIO4_MASK |
++ OMAP3430_AUTO_GPIO3_MASK |
++ OMAP3430_AUTO_GPIO2_MASK |
++ OMAP3430_AUTO_WDT3_MASK |
++ OMAP3430_AUTO_UART3_MASK |
++ OMAP3430_AUTO_GPT9_MASK |
++ OMAP3430_AUTO_GPT8_MASK |
++ OMAP3430_AUTO_GPT7_MASK |
++ OMAP3430_AUTO_GPT6_MASK |
++ OMAP3430_AUTO_GPT5_MASK |
++ OMAP3430_AUTO_GPT4_MASK |
++ OMAP3430_AUTO_GPT3_MASK |
++ OMAP3430_AUTO_GPT2_MASK |
++ OMAP3430_AUTO_MCBSP4_MASK |
++ OMAP3430_AUTO_MCBSP3_MASK |
++ OMAP3430_AUTO_MCBSP2_MASK,
++ OMAP3430_PER_MOD,
++ CM_AUTOIDLE);
++
+ if (omap_rev() > OMAP3430_REV_ES1_0) {
+- omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
+- omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
+- } else
+- omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
++ omap2_cm_write_mod_reg(
++ OMAP3430ES2_AUTO_USBHOST_MASK,
++ OMAP3430ES2_USBHOST_MOD,
++ CM_AUTOIDLE);
++ }
+
+- /* XXX This should be handled by hwmod code or SCM init code */
+ omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
+
+ /*
+--
+1.7.1
+
diff --git a/patches/dvfs/for-2.6.39/0008-omap3-pm-Use-exported-set_cr-instead-of-a-custom-one.patch b/patches/for_next/0208-omap3-pm-Use-exported-set_cr-instead-of-a-custom-one.patch
similarity index 88%
rename from patches/dvfs/for-2.6.39/0008-omap3-pm-Use-exported-set_cr-instead-of-a-custom-one.patch
rename to patches/for_next/0208-omap3-pm-Use-exported-set_cr-instead-of-a-custom-one.patch
index e855f66eb771bfa7df6bc88736c04bb921857b6b..d8d7fd99bbf5f17406774f061dff000db21c2395 100644
--- a/patches/dvfs/for-2.6.39/0008-omap3-pm-Use-exported-set_cr-instead-of-a-custom-one.patch
+++ b/patches/for_next/0208-omap3-pm-Use-exported-set_cr-instead-of-a-custom-one.patch
@@ -1,7 +1,7 @@
-From 8704ef72ae49373f60ef4a678745cfd00106d99a Mon Sep 17 00:00:00 2001
+From e75bcb8e2f2bca1ed09cbf4e2e4a156a4601e49c Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Fri, 11 Feb 2011 20:42:11 +0530
-Subject: [PATCH 08/10] omap3: pm: Use exported set_cr() instead of a custom one.
+Subject: [PATCH 208/254] omap3: pm: Use exported set_cr() instead of a custom one.
Remove the custom restore_control_register() and use the exported
set_cr() instead to set the system control register(SCTRL) value.
@@ -16,7 +16,7 @@ Signed-off-by: Kevin Hilman <khilman@ti.com>
1 files changed, 1 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
-index b9427c7..1883a46 100644
+index 4f50cac..abc551e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -311,11 +311,6 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
diff --git a/patches/dvfs/for-2.6.39/0009-omap3-cpuidle-Add-description-field-to-each-C-state.patch b/patches/for_next/0209-omap3-cpuidle-Add-description-field-to-each-C-state.patch
similarity index 95%
rename from patches/dvfs/for-2.6.39/0009-omap3-cpuidle-Add-description-field-to-each-C-state.patch
rename to patches/for_next/0209-omap3-cpuidle-Add-description-field-to-each-C-state.patch
index 05273a0210f6e7dd52166cd762d7cde1541a8868..1691d76e3bff9778e3b55498537a8373c76bef27 100644
--- a/patches/dvfs/for-2.6.39/0009-omap3-cpuidle-Add-description-field-to-each-C-state.patch
+++ b/patches/for_next/0209-omap3-cpuidle-Add-description-field-to-each-C-state.patch
@@ -1,7 +1,7 @@
-From ae7531ad0a84cb796309afb4a203501c980e8cf1 Mon Sep 17 00:00:00 2001
+From aa5c1fef1b336ebc0a5ef908d1bcddb58761ab2b Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
Date: Fri, 11 Feb 2011 20:42:12 +0530
-Subject: [PATCH 09/10] omap3: cpuidle: Add description field to each C-state.
+Subject: [PATCH 209/254] omap3: cpuidle: Add description field to each C-state.
Add a description field to each idle C-state. This helps to give
better data with PowerTop and one don't have to refer to the code
@@ -18,7 +18,7 @@ Signed-off-by: Kevin Hilman <khilman@ti.com>
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
-index 876eeca..cba437d 100644
+index 4331498..a44c523 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -58,6 +58,7 @@ struct omap3_processor_cx {
diff --git a/patches/dvfs/for-2.6.39/0010-OMAP3-PM-Set-clear-T2-bit-for-Smartreflex-on-TWL.patch b/patches/for_next/0210-OMAP3-PM-Set-clear-T2-bit-for-Smartreflex-on-TWL.patch
similarity index 95%
rename from patches/dvfs/for-2.6.39/0010-OMAP3-PM-Set-clear-T2-bit-for-Smartreflex-on-TWL.patch
rename to patches/for_next/0210-OMAP3-PM-Set-clear-T2-bit-for-Smartreflex-on-TWL.patch
index e13f3431c8ccf42f21fbabd665d96e93b6eb13a9..f6e476a66102ef8c4d6911feef4be64052bba259 100644
--- a/patches/dvfs/for-2.6.39/0010-OMAP3-PM-Set-clear-T2-bit-for-Smartreflex-on-TWL.patch
+++ b/patches/for_next/0210-OMAP3-PM-Set-clear-T2-bit-for-Smartreflex-on-TWL.patch
@@ -1,7 +1,7 @@
-From 82789764b2be72b6d4192ce25e3dc706ba08cf48 Mon Sep 17 00:00:00 2001
+From c28dbee280ca7208b09d0a844c58fdb701d1fa51 Mon Sep 17 00:00:00 2001
From: Thara Gopinath <thara@ti.com>
Date: Tue, 15 Feb 2011 13:28:58 +0530
-Subject: [PATCH 10/10] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
+Subject: [PATCH 210/254] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
Voltage control on TWL can be done using VMODE/I2C1/I2C_SR.
Since almost all platforms use I2C_SR on omap3, omap3_twl_init by
@@ -22,7 +22,7 @@ Signed-off-by: Kevin Hilman <khilman@ti.com>
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
-index 00e1d2b..b341c36 100644
+index ad8c18a..0a8e74e 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -59,8 +59,15 @@
diff --git a/patches/for_next/0211-OMAP3-PM-Initialize-IVA-only-if-available.patch b/patches/for_next/0211-OMAP3-PM-Initialize-IVA-only-if-available.patch
new file mode 100644
index 0000000000000000000000000000000000000000..18ff1a76e27817bed1669cdd4b6b31abe7e13789
--- /dev/null
+++ b/patches/for_next/0211-OMAP3-PM-Initialize-IVA-only-if-available.patch
@@ -0,0 +1,34 @@
+From b78dda8fe5c4134c3a88dcba540dae1cb6a9a40a Mon Sep 17 00:00:00 2001
+From: Sanjeev Premi <premi@ti.com>
+Date: Fri, 25 Feb 2011 18:57:20 +0530
+Subject: [PATCH 211/254] OMAP3: PM: Initialize IVA only if available
+
+IVA device is not present in many OMAP3 variants.
+
+This patch ensures that initialization is tied to
+the presence of IVA on the device.
+
+Signed-off-by: Sanjeev Premi <premi@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/pm.c | 4 +++-
+ 1 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
+index 2c3a253..30af335 100644
+--- a/arch/arm/mach-omap2/pm.c
++++ b/arch/arm/mach-omap2/pm.c
+@@ -83,7 +83,9 @@ static int _init_omap_device(char *name, struct device **new_dev)
+ static void omap2_init_processor_devices(void)
+ {
+ _init_omap_device("mpu", &mpu_dev);
+- _init_omap_device("iva", &iva_dev);
++ if (omap3_has_iva())
++ _init_omap_device("iva", &iva_dev);
++
+ if (cpu_is_omap44xx()) {
+ _init_omap_device("l3_main_1", &l3_dev);
+ _init_omap_device("dsp", &dsp_dev);
+--
+1.7.1
+
diff --git a/patches/for_next/0212-ARM-omap4-Provide-do_wfi-for-Thumb-2.patch b/patches/for_next/0212-ARM-omap4-Provide-do_wfi-for-Thumb-2.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7a275076e3c61d3945172cc5a4c7e436e7806d33
--- /dev/null
+++ b/patches/for_next/0212-ARM-omap4-Provide-do_wfi-for-Thumb-2.patch
@@ -0,0 +1,39 @@
+From e44b0ec7409ecfbd8ed12797ec8da82d243c7daf Mon Sep 17 00:00:00 2001
+From: Dave Martin <dave.martin@linaro.org>
+Date: Fri, 4 Mar 2011 15:33:53 +0000
+Subject: [PATCH 212/254] ARM: omap4: Provide do_wfi() for Thumb-2
+
+For CONFIG_THUMB2_KERNEL, the existing definition of do_wfi() will
+insert invalid code into the instruction stream.
+
+Any assembler which can assemble Thumb-2 is guaranteed to accept
+the "wfi" mnemonic, so for the Thumb-2 case, just use the mnemonic.
+
+The ARM case is left as-is.
+
+Signed-off-by: Dave Martin <dave.martin@linaro.org>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/include/mach/omap4-common.h | 4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
+index 5b0270b..de441c0 100644
+--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
++++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
+@@ -17,8 +17,12 @@
+ * wfi used in low power code. Directly opcode is used instead
+ * of instruction to avoid mulit-omap build break
+ */
++#ifdef CONFIG_THUMB2_KERNEL
++#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
++#else
+ #define do_wfi() \
+ __asm__ __volatile__ (".word 0xe320f003" : : : "memory")
++#endif
+
+ #ifdef CONFIG_CACHE_L2X0
+ extern void __iomem *l2cache_base;
+--
+1.7.1
+
diff --git a/patches/for_next/0213-ARM-omap4-Convert-END-to-ENDPROC-for-correct-linkage.patch b/patches/for_next/0213-ARM-omap4-Convert-END-to-ENDPROC-for-correct-linkage.patch
new file mode 100644
index 0000000000000000000000000000000000000000..1bfa7db2086a15c8ed45f70f719e33af373b2536
--- /dev/null
+++ b/patches/for_next/0213-ARM-omap4-Convert-END-to-ENDPROC-for-correct-linkage.patch
@@ -0,0 +1,73 @@
+From 1296f15aa46ce5901f415bbe9b831f7bdb642c61 Mon Sep 17 00:00:00 2001
+From: Dave Martin <dave.martin@linaro.org>
+Date: Fri, 4 Mar 2011 15:33:54 +0000
+Subject: [PATCH 213/254] ARM: omap4: Convert END() to ENDPROC() for correct linkage with CONFIG_THUMB2_KERNEL
+
+Code marked with ENTRY() also needs a matching ENDPROC() directive,
+in order to ensure that the type and instruction set of the
+symbol are correctly annotated.
+
+ENDPROC() tags the affected symbol as a function symbol, which will
+ensure that link-time fixups don't accidentally switch to the
+wrong instruction set.
+
+Signed-off-by: Dave Martin <dave.martin@linaro.org>
+Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap-headsmp.S | 2 +-
+ arch/arm/mach-omap2/omap44xx-smc.S | 8 ++++----
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
+index 6ae937a..4ee6aec 100644
+--- a/arch/arm/mach-omap2/omap-headsmp.S
++++ b/arch/arm/mach-omap2/omap-headsmp.S
+@@ -45,5 +45,5 @@ hold: ldr r12,=0x103
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+-END(omap_secondary_startup)
++ENDPROC(omap_secondary_startup)
+
+diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
+index 1980dc3..e69d37d 100644
+--- a/arch/arm/mach-omap2/omap44xx-smc.S
++++ b/arch/arm/mach-omap2/omap44xx-smc.S
+@@ -29,7 +29,7 @@ ENTRY(omap_smc1)
+ dsb
+ smc #0
+ ldmfd sp!, {r2-r12, pc}
+-END(omap_smc1)
++ENDPROC(omap_smc1)
+
+ ENTRY(omap_modify_auxcoreboot0)
+ stmfd sp!, {r1-r12, lr}
+@@ -37,7 +37,7 @@ ENTRY(omap_modify_auxcoreboot0)
+ dsb
+ smc #0
+ ldmfd sp!, {r1-r12, pc}
+-END(omap_modify_auxcoreboot0)
++ENDPROC(omap_modify_auxcoreboot0)
+
+ ENTRY(omap_auxcoreboot_addr)
+ stmfd sp!, {r2-r12, lr}
+@@ -45,7 +45,7 @@ ENTRY(omap_auxcoreboot_addr)
+ dsb
+ smc #0
+ ldmfd sp!, {r2-r12, pc}
+-END(omap_auxcoreboot_addr)
++ENDPROC(omap_auxcoreboot_addr)
+
+ ENTRY(omap_read_auxcoreboot0)
+ stmfd sp!, {r2-r12, lr}
+@@ -54,4 +54,4 @@ ENTRY(omap_read_auxcoreboot0)
+ smc #0
+ mov r0, r0, lsr #9
+ ldmfd sp!, {r2-r12, pc}
+-END(omap_read_auxcoreboot0)
++ENDPROC(omap_read_auxcoreboot0)
+--
+1.7.1
+
diff --git a/patches/for_next/0214-ARM-omap3-Remove-hand-encoded-SMC-instructions.patch b/patches/for_next/0214-ARM-omap3-Remove-hand-encoded-SMC-instructions.patch
new file mode 100644
index 0000000000000000000000000000000000000000..18234098831dcf45fd1f066a4dc9bef71974f1bf
--- /dev/null
+++ b/patches/for_next/0214-ARM-omap3-Remove-hand-encoded-SMC-instructions.patch
@@ -0,0 +1,88 @@
+From 956ab9d61db30be5178b6ef431701342a5616276 Mon Sep 17 00:00:00 2001
+From: Dave Martin <dave.martin@linaro.org>
+Date: Fri, 4 Mar 2011 15:33:55 +0000
+Subject: [PATCH 214/254] ARM: omap3: Remove hand-encoded SMC instructions
+
+For various reasons, Linux now only officially supports being built
+with tools which are new enough to understand the SMC instruction.
+
+Replacing the hand-encoded instructions when the mnemonic also
+allows for correct assembly in Thumb-2 (otherwise, the result is
+random data in the middle of the code).
+
+The Makefile already ensures that this file is built with a high
+enough gcc -march= flag (armv7-a).
+
+Signed-off-by: Dave Martin <dave.martin@linaro.org>
+Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Tested-by: Jean Pihet <j-pihet@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/sleep34xx.S | 14 +++++++-------
+ 1 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index 98d8232..a05c348 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -133,7 +133,7 @@ ENTRY(save_secure_ram_context)
+ mov r6, #0xff
+ mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+ mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
+- .word 0xE1600071 @ call SMI monitor (smi #1)
++ smc #1 @ call SMI monitor (smi #1)
+ nop
+ nop
+ nop
+@@ -408,7 +408,7 @@ skipl2dis:
+ adr r3, l2_inv_api_params @ r3 points to dummy parameters
+ mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+ mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
+- .word 0xE1600071 @ call SMI monitor (smi #1)
++ smc #1 @ call SMI monitor (smi #1)
+ /* Write to Aux control register to set some bits */
+ mov r0, #42 @ set service ID for PPA
+ mov r12, r0 @ copy secure Service ID in r12
+@@ -419,7 +419,7 @@ skipl2dis:
+ ldr r3, [r4, #0xBC] @ r3 points to parameters
+ mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+ mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
+- .word 0xE1600071 @ call SMI monitor (smi #1)
++ smc #1 @ call SMI monitor (smi #1)
+
+ #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+ /* Restore L2 aux control register */
+@@ -434,7 +434,7 @@ skipl2dis:
+ adds r3, r3, #8 @ r3 points to parameters
+ mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+ mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
+- .word 0xE1600071 @ call SMI monitor (smi #1)
++ smc #1 @ call SMI monitor (smi #1)
+ #endif
+ b logic_l1_restore
+
+@@ -443,18 +443,18 @@ l2_inv_api_params:
+ l2_inv_gp:
+ /* Execute smi to invalidate L2 cache */
+ mov r12, #0x1 @ set up to invalidate L2
+- .word 0xE1600070 @ Call SMI monitor (smieq)
++ smc #0 @ Call SMI monitor (smieq)
+ /* Write to Aux control register to set some bits */
+ ldr r4, scratchpad_base
+ ldr r3, [r4,#0xBC]
+ ldr r0, [r3,#4]
+ mov r12, #0x3
+- .word 0xE1600070 @ Call SMI monitor (smieq)
++ smc #0 @ Call SMI monitor (smieq)
+ ldr r4, scratchpad_base
+ ldr r3, [r4,#0xBC]
+ ldr r0, [r3,#12]
+ mov r12, #0x2
+- .word 0xE1600070 @ Call SMI monitor (smieq)
++ smc #0 @ Call SMI monitor (smieq)
+ logic_l1_restore:
+ ldr r1, l2dis_3630
+ cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
+--
+1.7.1
+
diff --git a/patches/for_next/0215-ARM-omap3-Thumb-2-compatibility-for-sram34xx.S.patch b/patches/for_next/0215-ARM-omap3-Thumb-2-compatibility-for-sram34xx.S.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f12687b4fb24214f32a9979e1cef5ab6ab73ebbe
--- /dev/null
+++ b/patches/for_next/0215-ARM-omap3-Thumb-2-compatibility-for-sram34xx.S.patch
@@ -0,0 +1,102 @@
+From 544ed2e5b4ecb05b11e9a16945058b0c1175356b Mon Sep 17 00:00:00 2001
+From: Dave Martin <dave.martin@linaro.org>
+Date: Fri, 4 Mar 2011 15:33:56 +0000
+Subject: [PATCH 215/254] ARM: omap3: Thumb-2 compatibility for sram34xx.S
+
+ * Build unconditionally as ARM for correct interoperation with
+ OMAP firmware.
+
+ * Remove deprecated PC-relative stores
+
+ * Add the required ENDPROC() directive for each ENTRY().
+
+ * .align before data words
+
+Signed-off-by: Dave Martin <dave.martin@linaro.org>
+Tested-by: Jean Pihet <j-pihet@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/sram34xx.S | 36 ++++++++++++++++++++++++++++--------
+ 1 files changed, 28 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
+index 7f893a2..1078bfb 100644
+--- a/arch/arm/mach-omap2/sram34xx.S
++++ b/arch/arm/mach-omap2/sram34xx.S
+@@ -34,6 +34,12 @@
+ #include "sdrc.h"
+ #include "cm2xxx_3xxx.h"
+
++/*
++ * This file needs be built unconditionally as ARM to interoperate correctly
++ * with non-Thumb-2-capable firmware.
++ */
++ .arm
++
+ .text
+
+ /* r1 parameters */
+@@ -116,24 +122,36 @@ ENTRY(omap3_sram_configure_core_dpll)
+
+ @ pull the extra args off the stack
+ @ and store them in SRAM
++
++/*
++ * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
++ * in Thumb-2: use a r7 as a base instead.
++ * Be careful not to clobber r7 when maintaing this file.
++ */
++ THUMB( adr r7, omap3_sram_configure_core_dpll )
++ .macro strtext Rt:req, label:req
++ ARM( str \Rt, \label )
++ THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] )
++ .endm
++
+ ldr r4, [sp, #52]
+- str r4, omap_sdrc_rfr_ctrl_0_val
++ strtext r4, omap_sdrc_rfr_ctrl_0_val
+ ldr r4, [sp, #56]
+- str r4, omap_sdrc_actim_ctrl_a_0_val
++ strtext r4, omap_sdrc_actim_ctrl_a_0_val
+ ldr r4, [sp, #60]
+- str r4, omap_sdrc_actim_ctrl_b_0_val
++ strtext r4, omap_sdrc_actim_ctrl_b_0_val
+ ldr r4, [sp, #64]
+- str r4, omap_sdrc_mr_0_val
++ strtext r4, omap_sdrc_mr_0_val
+ ldr r4, [sp, #68]
+- str r4, omap_sdrc_rfr_ctrl_1_val
++ strtext r4, omap_sdrc_rfr_ctrl_1_val
+ cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
+ beq skip_cs1_params @ do not use cs1 params
+ ldr r4, [sp, #72]
+- str r4, omap_sdrc_actim_ctrl_a_1_val
++ strtext r4, omap_sdrc_actim_ctrl_a_1_val
+ ldr r4, [sp, #76]
+- str r4, omap_sdrc_actim_ctrl_b_1_val
++ strtext r4, omap_sdrc_actim_ctrl_b_1_val
+ ldr r4, [sp, #80]
+- str r4, omap_sdrc_mr_1_val
++ strtext r4, omap_sdrc_mr_1_val
+ skip_cs1_params:
+ mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
+ bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
+@@ -271,6 +289,7 @@ skip_cs1_prog:
+ ldr r12, [r11] @ posted-write barrier for SDRC
+ bx lr
+
++ .align
+ omap3_sdrc_power:
+ .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
+ omap3_cm_clksel1_pll:
+@@ -319,6 +338,7 @@ omap3_sdrc_dlla_ctrl:
+ .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
+ core_m2_mask_val:
+ .word 0x07FFFFFF
++ENDPROC(omap3_sram_configure_core_dpll)
+
+ ENTRY(omap3_sram_configure_core_dpll_sz)
+ .word . - omap3_sram_configure_core_dpll
+--
+1.7.1
+
diff --git a/patches/for_next/0216-ARM-omap3-Thumb-2-compatibility-for-sleep34xx.S.patch b/patches/for_next/0216-ARM-omap3-Thumb-2-compatibility-for-sleep34xx.S.patch
new file mode 100644
index 0000000000000000000000000000000000000000..839982d90ea997d714f9fd3e72166e4339232153
--- /dev/null
+++ b/patches/for_next/0216-ARM-omap3-Thumb-2-compatibility-for-sleep34xx.S.patch
@@ -0,0 +1,196 @@
+From 171b78c18cffbba6ea4553683caabf533b31a28a Mon Sep 17 00:00:00 2001
+From: Dave Martin <dave.martin@linaro.org>
+Date: Fri, 4 Mar 2011 15:33:57 +0000
+Subject: [PATCH 216/254] ARM: omap3: Thumb-2 compatibility for sleep34xx.S
+
+ * Build unconditionally as ARM for correct interoperation with
+ OMAP firmware.
+
+ * Fix an out-of-range ADR when building for ARM.
+
+ * Remove deprecated PC-relative stores.
+
+ * Add the required ENDPROC() directive for each ENTRY().
+
+ * .align before data words.
+
+ * Handle non-interworking return from v7_flush_dcache_all.
+
+Signed-off-by: Dave Martin <dave.martin@linaro.org>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/sleep34xx.S | 48 ++++++++++++++++++++++++++++++++++----
+ 1 files changed, 43 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index a05c348..0c1b335 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -64,6 +64,11 @@
+ #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
+ #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
+
++/*
++ * This file needs be built unconditionally as ARM to interoperate correctly
++ * with non-Thumb-2-capable firmware.
++ */
++ .arm
+
+ /*
+ * API functions
+@@ -82,6 +87,8 @@ ENTRY(get_restore_pointer)
+ stmfd sp!, {lr} @ save registers on stack
+ adr r0, restore
+ ldmfd sp!, {pc} @ restore regs and return
++ENDPROC(get_restore_pointer)
++ .align
+ ENTRY(get_restore_pointer_sz)
+ .word . - get_restore_pointer
+
+@@ -91,6 +98,8 @@ ENTRY(get_omap3630_restore_pointer)
+ stmfd sp!, {lr} @ save registers on stack
+ adr r0, restore_3630
+ ldmfd sp!, {pc} @ restore regs and return
++ENDPROC(get_omap3630_restore_pointer)
++ .align
+ ENTRY(get_omap3630_restore_pointer_sz)
+ .word . - get_omap3630_restore_pointer
+
+@@ -100,6 +109,8 @@ ENTRY(get_es3_restore_pointer)
+ stmfd sp!, {lr} @ save registers on stack
+ adr r0, restore_es3
+ ldmfd sp!, {pc} @ restore regs and return
++ENDPROC(get_es3_restore_pointer)
++ .align
+ ENTRY(get_es3_restore_pointer_sz)
+ .word . - get_es3_restore_pointer
+
+@@ -113,8 +124,10 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
+ stmfd sp!, {lr} @ save registers on stack
+ /* Setup so that we will disable and enable l2 */
+ mov r1, #0x1
+- str r1, l2dis_3630
++ adrl r2, l2dis_3630 @ may be too distant for plain adr
++ str r1, [r2]
+ ldmfd sp!, {pc} @ restore regs and return
++ENDPROC(enable_omap3630_toggle_l2_on_restore)
+
+ .text
+ /* Function to call rom code to save secure ram context */
+@@ -139,12 +152,14 @@ ENTRY(save_secure_ram_context)
+ nop
+ nop
+ ldmfd sp!, {r1-r12, pc}
++ .align
+ sram_phy_addr_mask:
+ .word SRAM_BASE_P
+ high_mask:
+ .word 0xffff
+ api_params:
+ .word 0x4, 0x0, 0x0, 0x1, 0x1
++ENDPROC(save_secure_ram_context)
+ ENTRY(save_secure_ram_context_sz)
+ .word . - save_secure_ram_context
+
+@@ -279,8 +294,18 @@ clean_l2:
+ * - 'might' have to copy address, load and jump to it
+ */
+ ldr r1, kernel_flush
+- mov lr, pc
+- bx r1
++ blx r1
++ /*
++ * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
++ * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
++ * This sequence switches back to ARM. Note that .align may insert a
++ * nop: bx pc needs to be word-aligned in order to work.
++ */
++ THUMB( .thumb )
++ THUMB( .align )
++ THUMB( bx pc )
++ THUMB( nop )
++ .arm
+
+ omap3_do_wfi:
+ ldr r4, sdrc_power @ read the SDRC_POWER register
+@@ -438,6 +463,7 @@ skipl2dis:
+ #endif
+ b logic_l1_restore
+
++ .align
+ l2_inv_api_params:
+ .word 0x1, 0x00
+ l2_inv_gp:
+@@ -607,6 +633,7 @@ usettbr0:
+
+ /* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
+ .text
++ .align 3
+ ENTRY(es3_sdrc_fix)
+ ldr r4, sdrc_syscfg @ get config addr
+ ldr r5, [r4] @ get value
+@@ -634,6 +661,7 @@ ENTRY(es3_sdrc_fix)
+ str r5, [r4] @ kick off refreshes
+ bx lr
+
++ .align
+ sdrc_syscfg:
+ .word SDRC_SYSCONFIG_P
+ sdrc_mr_0:
+@@ -648,6 +676,7 @@ sdrc_emr2_1:
+ .word SDRC_EMR2_1_P
+ sdrc_manual_1:
+ .word SDRC_MANUAL_1_P
++ENDPROC(es3_sdrc_fix)
+ ENTRY(es3_sdrc_fix_sz)
+ .word . - es3_sdrc_fix
+
+@@ -682,6 +711,12 @@ wait_sdrc_ready:
+ bic r5, r5, #0x40
+ str r5, [r4]
+
++/*
++ * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
++ * base instead.
++ * Be careful not to clobber r7 when maintaing this code.
++ */
++
+ is_dll_in_lock_mode:
+ /* Is dll in lock mode? */
+ ldr r4, sdrc_dlla_ctrl
+@@ -689,10 +724,11 @@ is_dll_in_lock_mode:
+ tst r5, #0x4
+ bxne lr @ Return if locked
+ /* wait till dll locks */
++ adr r7, kick_counter
+ wait_dll_lock_timed:
+ ldr r4, wait_dll_lock_counter
+ add r4, r4, #1
+- str r4, wait_dll_lock_counter
++ str r4, [r7, #wait_dll_lock_counter - kick_counter]
+ ldr r4, sdrc_dlla_status
+ /* Wait 20uS for lock */
+ mov r6, #8
+@@ -718,9 +754,10 @@ kick_dll:
+ dsb
+ ldr r4, kick_counter
+ add r4, r4, #1
+- str r4, kick_counter
++ str r4, [r7] @ kick_counter
+ b wait_dll_lock_timed
+
++ .align
+ cm_idlest1_core:
+ .word CM_IDLEST1_CORE_V
+ cm_idlest_ckgen:
+@@ -763,6 +800,7 @@ kick_counter:
+ .word 0
+ wait_dll_lock_counter:
+ .word 0
++ENDPROC(omap34xx_cpu_suspend)
+
+ ENTRY(omap34xx_cpu_suspend_sz)
+ .word . - omap34xx_cpu_suspend
+--
+1.7.1
+
diff --git a/patches/for_next/0217-OMAP2-smartreflex-remove-SR-debug-directory-in-omap_.patch b/patches/for_next/0217-OMAP2-smartreflex-remove-SR-debug-directory-in-omap_.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7deac44f3b7b90e6bb8c6c8b9dd91088234a20d9
--- /dev/null
+++ b/patches/for_next/0217-OMAP2-smartreflex-remove-SR-debug-directory-in-omap_.patch
@@ -0,0 +1,84 @@
+From 06f17a114b9b3e693273f944b47604091cfd73f2 Mon Sep 17 00:00:00 2001
+From: Anand S Sawant <sawant@ti.com>
+Date: Thu, 17 Feb 2011 21:27:30 +0530
+Subject: [PATCH 217/254] OMAP2+: smartreflex: remove SR debug directory in omap_sr_remove()
+
+omap_sr_probe() creates the smartreflex debug directory and its
+underlying nvalue debug directory. These directories are removed in
+omap_sr_remove().
+
+Basic smartreflex functionality tested on OMAP3630 Zoom3 & OMAP4430 SDP
+
+Signed-off-by: Anand S Sawant <sawant@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/smartreflex.c | 23 +++++++++++++----------
+ 1 files changed, 13 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index 2566552..8f674c9 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -54,6 +54,7 @@ struct omap_sr {
+ struct list_head node;
+ struct omap_sr_nvalue_table *nvalue_table;
+ struct voltagedomain *voltdm;
++ struct dentry *dbg_dir;
+ };
+
+ /* sr_list contains all the instances of smartreflex module */
+@@ -823,7 +824,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
+ struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+ struct omap_sr_data *pdata = pdev->dev.platform_data;
+ struct resource *mem, *irq;
+- struct dentry *vdd_dbg_dir, *dbg_dir, *nvalue_dir;
++ struct dentry *vdd_dbg_dir, *nvalue_dir;
+ struct omap_volt_data *volt_data;
+ int i, ret = 0;
+
+@@ -898,24 +899,24 @@ static int __init omap_sr_probe(struct platform_device *pdev)
+ goto err_release_region;
+ }
+
+- dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
+- if (IS_ERR(dbg_dir)) {
++ sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
++ if (IS_ERR(sr_info->dbg_dir)) {
+ dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
+ __func__);
+- ret = PTR_ERR(dbg_dir);
++ ret = PTR_ERR(sr_info->dbg_dir);
+ goto err_release_region;
+ }
+
+- (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
+- (void *)sr_info, &pm_sr_fops);
+- (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
++ (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
++ sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
++ (void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
+ &sr_info->err_weight);
+- (void) debugfs_create_x32("errmaxlimit", S_IRUGO, dbg_dir,
++ (void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
+ &sr_info->err_maxlimit);
+- (void) debugfs_create_x32("errminlimit", S_IRUGO, dbg_dir,
++ (void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
+ &sr_info->err_minlimit);
+
+- nvalue_dir = debugfs_create_dir("nvalue", dbg_dir);
++ nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
+ if (IS_ERR(nvalue_dir)) {
+ dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
+ "for n-values\n", __func__);
+@@ -972,6 +973,8 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
+
+ if (sr_info->autocomp_active)
+ sr_stop_vddautocomp(sr_info);
++ if (sr_info->dbg_dir)
++ debugfs_remove_recursive(sr_info->dbg_dir);
+
+ list_del(&sr_info->node);
+ iounmap(sr_info->base);
+--
+1.7.1
+
diff --git a/patches/for_next/0218-OMAP-clock-fix-compile-warning.patch b/patches/for_next/0218-OMAP-clock-fix-compile-warning.patch
new file mode 100644
index 0000000000000000000000000000000000000000..24d90764eb02326c2a2a633ead70f20e6018f836
--- /dev/null
+++ b/patches/for_next/0218-OMAP-clock-fix-compile-warning.patch
@@ -0,0 +1,41 @@
+From e0c13e808f06e065e3e81fa3df6e20c40fc473a8 Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <balbi@ti.com>
+Date: Wed, 9 Mar 2011 18:44:28 -0700
+Subject: [PATCH 218/254] OMAP: clock: fix compile warning
+
+if building kernels without OMAP2 support, we
+will see a warning such as:
+
+arch/arm/mach-omap2/io.c: In function 'omap2_init_common_infrastructure':
+arch/arm/mach-omap2/io.c:389:3: warning: statement with no effect
+arch/arm/mach-omap2/io.c:391:3: warning: statement with no effect
+
+Signed-off-by: Felipe Balbi <balbi@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/clock2xxx.h | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
+index cc5c8d4..cb6df8c 100644
+--- a/arch/arm/mach-omap2/clock2xxx.h
++++ b/arch/arm/mach-omap2/clock2xxx.h
+@@ -23,13 +23,13 @@ void omap2xxx_clk_prepare_for_reboot(void);
+ #ifdef CONFIG_SOC_OMAP2420
+ int omap2420_clk_init(void);
+ #else
+-#define omap2420_clk_init() 0
++#define omap2420_clk_init() do { } while(0)
+ #endif
+
+ #ifdef CONFIG_SOC_OMAP2430
+ int omap2430_clk_init(void);
+ #else
+-#define omap2430_clk_init() 0
++#define omap2430_clk_init() do { } while(0)
+ #endif
+
+ extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;
+--
+1.7.1
+
diff --git a/patches/for_next/0219-MAINTAINERS-add-entry-for-OMAP-powerdomain-clockdoma.patch b/patches/for_next/0219-MAINTAINERS-add-entry-for-OMAP-powerdomain-clockdoma.patch
new file mode 100644
index 0000000000000000000000000000000000000000..c60689cf08873095a1ba2526f0905b67b31e8249
--- /dev/null
+++ b/patches/for_next/0219-MAINTAINERS-add-entry-for-OMAP-powerdomain-clockdoma.patch
@@ -0,0 +1,44 @@
+From 4abd6f4492bd543360e63de74680219f6a7b907c Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Wed, 9 Mar 2011 18:44:28 -0700
+Subject: [PATCH 219/254] MAINTAINERS: add entry for OMAP powerdomain/clockdomain per-SoC layer support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add Rajendra Nayak and myself as maintainers for the OMAP
+powerdomain/clockdomain per-SoC layer code.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Benoît Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ MAINTAINERS | 10 ++++++++++
+ 1 files changed, 10 insertions(+), 0 deletions(-)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 939e852..44fb121 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -4506,6 +4506,16 @@ L: linux-omap@vger.kernel.org
+ S: Maintained
+ F: arch/arm/*omap*/*pm*
+
++OMAP POWERDOMAIN/CLOCKDOMAIN SOC ADAPTATION LAYER SUPPORT
++M: Rajendra Nayak <rnayak@ti.com>
++M: Paul Walmsley <paul@pwsan.com>
++L: linux-omap@vger.kernel.org
++S: Maintained
++F: arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
++F: arch/arm/mach-omap2/powerdomain44xx.c
++F: arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
++F: arch/arm/mach-omap2/clockdomain44xx.c
++
+ OMAP AUDIO SUPPORT
+ M: Jarkko Nikula <jhnikula@gmail.com>
+ L: alsa-devel@alsa-project.org (subscribers-only)
+--
+1.7.1
+
diff --git a/patches/for_next/0220-OMAP3-hwmod-data-Fix-incorrect-SmartReflex-L4-CORE-i.patch b/patches/for_next/0220-OMAP3-hwmod-data-Fix-incorrect-SmartReflex-L4-CORE-i.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3c54d620663a4907f6f392862ec637ee1817f9a9
--- /dev/null
+++ b/patches/for_next/0220-OMAP3-hwmod-data-Fix-incorrect-SmartReflex-L4-CORE-i.patch
@@ -0,0 +1,57 @@
+From f89c343600138e326d2d583b8c3302b956e007fa Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Thu, 10 Mar 2011 10:53:15 +0100
+Subject: [PATCH 220/254] OMAP3: hwmod data: Fix incorrect SmartReflex -> L4 CORE interconnect links
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Commit d34427267186827dfd62bd8cf726601fffb22534 ("OMAP3: PM: Adding
+smartreflex hwmod data") added data that claims that the L4 CORE has
+two slave interfaces that originate from the SmartReflex modules,
+omap3_l4_core__sr1 and omap3_l4_core__sr2. But as those two data
+structure records show, it's L4 CORE that has a master port towards
+SR1 and SR2.
+Move the incorrect data from slaves list to master list.
+
+Based on a path by Paul Walmsley <paul@pwsan.com>
+
+ https://patchwork.kernel.org/patch/623171/
+
+That is based on a patch by Benoît Cousson <b-cousson@ti.com>:
+
+ https://patchwork.kernel.org/patch/590561/
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Benoît Cousson <b-cousson@ti.com>
+Cc: Sanjeev Premi <premi@ti.com>
+Cc: Thara Gopinath <thara@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index d0d1d8f..0e9f70e 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -488,8 +488,6 @@ static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
+ /* Slave interfaces on the L4_CORE interconnect */
+ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
+ &omap3xxx_l3_main__l4_core,
+- &omap3_l4_core__sr1,
+- &omap3_l4_core__sr2,
+ };
+
+ /* Master interfaces on the L4_CORE interconnect */
+@@ -500,6 +498,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
+ &omap3_l4_core__i2c1,
+ &omap3_l4_core__i2c2,
+ &omap3_l4_core__i2c3,
++ &omap3_l4_core__sr1,
++ &omap3_l4_core__sr2,
+ };
+
+ /* L4 CORE */
+--
+1.7.1
+
diff --git a/patches/for_next/0221-OMAP3-hwmod-data-Remove-masters-port-links-for-inter.patch b/patches/for_next/0221-OMAP3-hwmod-data-Remove-masters-port-links-for-inter.patch
new file mode 100644
index 0000000000000000000000000000000000000000..42297e05e748a472ff144c95e48da60eb3123267
--- /dev/null
+++ b/patches/for_next/0221-OMAP3-hwmod-data-Remove-masters-port-links-for-inter.patch
@@ -0,0 +1,88 @@
+From 7b0786c6b56da0a036fac29c519b9e457bfaeca8 Mon Sep 17 00:00:00 2001
+From: Benoit Cousson <b-cousson@ti.com>
+Date: Fri, 25 Feb 2011 17:46:33 +0100
+Subject: [PATCH 221/254] OMAP3: hwmod data: Remove masters port links for interconnects.
+
+Master ports from interconnect are generating some annoying circular
+references that become tricky to handle if we have to dynamically
+remove some IP on some variant platforms.
+Since they are not used for the moment, and since we can still build
+that relation using the reverse relation (slave port from the IP
+toward master port of the interconnect), let remove them for the
+moment like it is done on OMAP4.
+
+Signed-off-by: Benoit Cousson <b-cousson@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Sanjeev Premi <premi@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 28 ----------------------------
+ 1 files changed, 0 insertions(+), 28 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 0e9f70e..11f4a24 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -490,24 +490,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
+ &omap3xxx_l3_main__l4_core,
+ };
+
+-/* Master interfaces on the L4_CORE interconnect */
+-static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
+- &omap3xxx_l4_core__l4_wkup,
+- &omap3_l4_core__uart1,
+- &omap3_l4_core__uart2,
+- &omap3_l4_core__i2c1,
+- &omap3_l4_core__i2c2,
+- &omap3_l4_core__i2c3,
+- &omap3_l4_core__sr1,
+- &omap3_l4_core__sr2,
+-};
+-
+ /* L4 CORE */
+ static struct omap_hwmod omap3xxx_l4_core_hwmod = {
+ .name = "l4_core",
+ .class = &l4_hwmod_class,
+- .masters = omap3xxx_l4_core_masters,
+- .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
+ .slaves = omap3xxx_l4_core_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+@@ -519,18 +505,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
+ &omap3xxx_l3_main__l4_per,
+ };
+
+-/* Master interfaces on the L4_PER interconnect */
+-static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
+- &omap3_l4_per__uart3,
+- &omap3_l4_per__uart4,
+-};
+-
+ /* L4 PER */
+ static struct omap_hwmod omap3xxx_l4_per_hwmod = {
+ .name = "l4_per",
+ .class = &l4_hwmod_class,
+- .masters = omap3xxx_l4_per_masters,
+- .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
+ .slaves = omap3xxx_l4_per_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+@@ -542,16 +520,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
+ &omap3xxx_l4_core__l4_wkup,
+ };
+
+-/* Master interfaces on the L4_WKUP interconnect */
+-static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
+-};
+-
+ /* L4 WKUP */
+ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &l4_hwmod_class,
+- .masters = omap3xxx_l4_wkup_masters,
+- .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
+ .slaves = omap3xxx_l4_wkup_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+--
+1.7.1
+
diff --git a/patches/for_next/0222-OMAP2-hwmod-fix-incorrect-computation-of-autoidle_ma.patch b/patches/for_next/0222-OMAP2-hwmod-fix-incorrect-computation-of-autoidle_ma.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7bc9cfa874449ad5bed07731f665961519b3fd19
--- /dev/null
+++ b/patches/for_next/0222-OMAP2-hwmod-fix-incorrect-computation-of-autoidle_ma.patch
@@ -0,0 +1,43 @@
+From d72878129cd43348f88aab1ae56dd5b78327935d Mon Sep 17 00:00:00 2001
+From: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+Date: Thu, 3 Mar 2011 14:22:46 -0700
+Subject: [PATCH 222/254] OMAP2+: hwmod: fix incorrect computation of autoidle_mask
+
+Autoidle is a single bit, TIOCP_CFG[0], setting on OMAP1/2/3/4 platforms.
+In _set_module_autoidle() I am seeing 0x3 value where the mask is computed.
+This should be 0x1.
+
+v2:
+(1) Modified the subject.
+(2) Modified the description with further specific information.
+
+Baseline:
+git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+
+Tested Info:
+Boot tested on OMAP 1/2/3/4.
+
+Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
+Acked-by: Rajendra Nayak <rnayak@ti.com>
+Acked-by: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 1125134..61f2cef 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -370,7 +370,7 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
+ }
+
+ autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
+- autoidle_mask = (0x3 << autoidle_shift);
++ autoidle_mask = (0x1 << autoidle_shift);
+
+ *v &= ~autoidle_mask;
+ *v |= autoidle << autoidle_shift;
+--
+1.7.1
+
diff --git a/patches/for_next/0223-omap-hwmod-add-syss-reset-done-flags-to-omap2-omap3-.patch b/patches/for_next/0223-omap-hwmod-add-syss-reset-done-flags-to-omap2-omap3-.patch
new file mode 100644
index 0000000000000000000000000000000000000000..952396458fe09c1ae1893a53847710267ef134aa
--- /dev/null
+++ b/patches/for_next/0223-omap-hwmod-add-syss-reset-done-flags-to-omap2-omap3-.patch
@@ -0,0 +1,180 @@
+From 7b331c16a12fc252c3279a07eca5b938e65cf0d3 Mon Sep 17 00:00:00 2001
+From: Avinash.H.M <avinashhm@ti.com>
+Date: Thu, 3 Mar 2011 14:22:46 -0700
+Subject: [PATCH 223/254] omap: hwmod: add syss reset done flags to omap2, omap3 hwmods
+
+Some of the omap2, omap3 peripherals support software reset. This
+can be done through the softreset bit in sysconfig register.
+The reset status can be checked through resetdone bit of
+sysstatus register. syss_has_reset_status is added to the hwmod
+database of peripherals which have resetdone bit in sysstatus register.
+
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+Reviewed-by: Govindraj.R <govindraj.raja@ti.com>
+Signed-off-by: Avinash.H.M <avinashhm@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_2420_data.c | 11 ++++++-----
+ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 12 +++++++-----
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 13 ++++++++-----
+ 3 files changed, 21 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+index 61e58bd..6282346 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+@@ -988,7 +988,7 @@ static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+
+@@ -1029,7 +1029,7 @@ static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+@@ -1441,7 +1441,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x20,
+ .syss_offs = 0x10,
+- .sysc_flags = SYSC_HAS_SOFTRESET,
++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+
+@@ -1613,7 +1613,8 @@ static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
++ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+@@ -1755,7 +1756,7 @@ static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+- SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+index 0da754e..5afe27d 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+@@ -1088,7 +1088,7 @@ static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+
+@@ -1129,7 +1129,7 @@ static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+@@ -1516,7 +1516,8 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x20,
+ .syss_offs = 0x10,
+- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
++ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+
+@@ -1714,7 +1715,8 @@ static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
++ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+@@ -1886,7 +1888,7 @@ static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+- SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 11f4a24..6a5de99 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1237,7 +1237,8 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
++ SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
++ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+@@ -1249,7 +1250,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
+ .syss_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+@@ -1291,7 +1292,7 @@ static struct omap_hwmod_class_sysconfig uart_sysc = {
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+- SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+@@ -2097,7 +2098,8 @@ static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
++ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+ };
+@@ -2351,7 +2353,8 @@ static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+- SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
++ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
++ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+--
+1.7.1
+
diff --git a/patches/for_next/0224-OMAP2-hwmod-Fix-what-_init_clock-returns.patch b/patches/for_next/0224-OMAP2-hwmod-Fix-what-_init_clock-returns.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f805a0649d5affa7cbbbc9cd0aa7cd23e8846b7f
--- /dev/null
+++ b/patches/for_next/0224-OMAP2-hwmod-Fix-what-_init_clock-returns.patch
@@ -0,0 +1,36 @@
+From fd58a5be52611be6f8c89f9ba9c06d74d5ccfa4c Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@ti.com>
+Date: Wed, 16 Feb 2011 12:11:24 +0000
+Subject: [PATCH 224/254] OMAP2+: hwmod: Fix what _init_clock returns
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+_init_clock always returns 0 and does
+not propogate the error (in case of failure)
+back to the caller, causing _init_clocks to
+fail silently.
+
+Signed-off-by: Rajendra Nayak <rnayak@ti.com>
+Acked-by: Benoît Cousson <b-cousson@ti.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 61f2cef..faba82e 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -921,7 +921,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
+ if (!ret)
+ oh->_state = _HWMOD_STATE_CLKS_INITED;
+
+- return 0;
++ return ret;
+ }
+
+ /**
+--
+1.7.1
+
diff --git a/patches/for_next/0225-OMAP2-hwmod-fix-a-documentation-bug-with-HWMOD_NO_OC.patch b/patches/for_next/0225-OMAP2-hwmod-fix-a-documentation-bug-with-HWMOD_NO_OC.patch
new file mode 100644
index 0000000000000000000000000000000000000000..0108745abaf5e911652b833be5070c7694b8771b
--- /dev/null
+++ b/patches/for_next/0225-OMAP2-hwmod-fix-a-documentation-bug-with-HWMOD_NO_OC.patch
@@ -0,0 +1,29 @@
+From 3598a9e4bed9d9f92a9e69a0333a160e65b85d3f Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Thu, 3 Mar 2011 15:22:42 -0700
+Subject: [PATCH 225/254] OMAP2+: hwmod: fix a documentation bug with HWMOD_NO_OCP_AUTOIDLE
+
+The documented name of the HWMOD_NO_OCP_AUTOIDLE flag was incorrect; fix it.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 +--
+ 1 files changed, 1 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 59349c2..6145116 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -375,8 +375,7 @@ struct omap_hwmod_omap4_prcm {
+ * XXX Should be HWMOD_SETUP_NO_RESET
+ * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
+ * controller, etc. XXX probably belongs outside the main hwmod file
+- * XXX Should be HWMOD_SETUP_NO_IDLE
+- * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
++ * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ * when module is enabled, rather than the default, which is to
+ * enable autoidle
+ * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
+--
+1.7.1
+
diff --git a/patches/for_next/0226-OMAP2-hwmod-use-status-bit-info-for-reset-line.patch b/patches/for_next/0226-OMAP2-hwmod-use-status-bit-info-for-reset-line.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a70b4df24020be58c76fef67eeb80c16f7a215e3
--- /dev/null
+++ b/patches/for_next/0226-OMAP2-hwmod-use-status-bit-info-for-reset-line.patch
@@ -0,0 +1,268 @@
+From e4fba8c87506cb1bd187cd414b1c8db04abcd8b7 Mon Sep 17 00:00:00 2001
+From: omar ramirez <omar.ramirez@ti.com>
+Date: Fri, 4 Mar 2011 13:32:44 -0700
+Subject: [PATCH 226/254] OMAP2+: hwmod: use status bit info for reset line
+
+On OMAP2 and OMAP3 the reset ctrl shift doesn't match the
+status bit, as it does on OMAP4, when handling the reset lines.
+
+This patch adds a new member in the reset info structure, so now it
+can be added as part of hwmod data, and checked accordingly for
+OMAP2 or 3; otherwise, there could be cases when the shift masks
+doesn't match both of the registers, and a successful reset might
+throw an error message or vice versa.
+
+Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
+[paul@pwsan.com: added a warning if st_shift used on OMAP4; renamed 'r'
+ variable; improved some documentation]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 75 +++++++++++++++-----------
+ arch/arm/mach-omap2/prm2xxx_3xxx.c | 18 ++++---
+ arch/arm/mach-omap2/prm2xxx_3xxx.h | 5 +-
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 +
+ 4 files changed, 58 insertions(+), 42 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index faba82e..551d4a9 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -967,25 +967,29 @@ static int _wait_target_ready(struct omap_hwmod *oh)
+ }
+
+ /**
+- * _lookup_hardreset - return the register bit shift for this hwmod/reset line
++ * _lookup_hardreset - fill register bit info for this hwmod/reset line
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line in the context of this hwmod
++ * @ohri: struct omap_hwmod_rst_info * that this function will fill in
+ *
+ * Return the bit position of the reset line that match the
+ * input name. Return -ENOENT if not found.
+ */
+-static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name)
++static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
++ struct omap_hwmod_rst_info *ohri)
+ {
+ int i;
+
+ for (i = 0; i < oh->rst_lines_cnt; i++) {
+ const char *rst_line = oh->rst_lines[i].name;
+ if (!strcmp(rst_line, name)) {
+- u8 shift = oh->rst_lines[i].rst_shift;
+- pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n",
+- oh->name, rst_line, shift);
++ ohri->rst_shift = oh->rst_lines[i].rst_shift;
++ ohri->st_shift = oh->rst_lines[i].st_shift;
++ pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n",
++ oh->name, __func__, rst_line, ohri->rst_shift,
++ ohri->st_shift);
+
+- return shift;
++ return 0;
+ }
+ }
+
+@@ -1004,21 +1008,22 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name)
+ */
+ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
+ {
+- u8 shift;
++ struct omap_hwmod_rst_info ohri;
++ u8 ret;
+
+ if (!oh)
+ return -EINVAL;
+
+- shift = _lookup_hardreset(oh, name);
+- if (IS_ERR_VALUE(shift))
+- return shift;
++ ret = _lookup_hardreset(oh, name, &ohri);
++ if (IS_ERR_VALUE(ret))
++ return ret;
+
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
+- shift);
++ ohri.rst_shift);
+ else if (cpu_is_omap44xx())
+ return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
+- shift);
++ ohri.rst_shift);
+ else
+ return -EINVAL;
+ }
+@@ -1035,29 +1040,34 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
+ */
+ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
+ {
+- u8 shift;
+- int r;
++ struct omap_hwmod_rst_info ohri;
++ int ret;
+
+ if (!oh)
+ return -EINVAL;
+
+- shift = _lookup_hardreset(oh, name);
+- if (IS_ERR_VALUE(shift))
+- return shift;
++ ret = _lookup_hardreset(oh, name, &ohri);
++ if (IS_ERR_VALUE(ret))
++ return ret;
+
+- if (cpu_is_omap24xx() || cpu_is_omap34xx())
+- r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
+- shift);
+- else if (cpu_is_omap44xx())
+- r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
+- shift);
+- else
++ if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
++ ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
++ ohri.rst_shift,
++ ohri.st_shift);
++ } else if (cpu_is_omap44xx()) {
++ if (ohri.st_shift)
++ pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
++ oh->name, name);
++ ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
++ ohri.rst_shift);
++ } else {
+ return -EINVAL;
++ }
+
+- if (r == -EBUSY)
++ if (ret == -EBUSY)
+ pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
+
+- return r;
++ return ret;
+ }
+
+ /**
+@@ -1070,21 +1080,22 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
+ */
+ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
+ {
+- u8 shift;
++ struct omap_hwmod_rst_info ohri;
++ u8 ret;
+
+ if (!oh)
+ return -EINVAL;
+
+- shift = _lookup_hardreset(oh, name);
+- if (IS_ERR_VALUE(shift))
+- return shift;
++ ret = _lookup_hardreset(oh, name, &ohri);
++ if (IS_ERR_VALUE(ret))
++ return ret;
+
+ if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+ return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
+- shift);
++ ohri.st_shift);
+ } else if (cpu_is_omap44xx()) {
+ return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
+- shift);
++ ohri.rst_shift);
+ } else {
+ return -EINVAL;
+ }
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+index ec03625..051213f 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
+@@ -118,7 +118,8 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+ /**
+ * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+- * @shift: register bit shift corresponding to the reset line to deassert
++ * @rst_shift: register bit shift corresponding to the reset line to deassert
++ * @st_shift: register bit shift for the status of the deasserted submodule
+ *
+ * Some IPs like dsp or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+@@ -129,27 +130,28 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+-int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
++int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
+ {
+- u32 mask;
++ u32 rst, st;
+ int c;
+
+ if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+ return -EINVAL;
+
+- mask = 1 << shift;
++ rst = 1 << rst_shift;
++ st = 1 << st_shift;
+
+ /* Check the current status to avoid de-asserting the line twice */
+- if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0)
++ if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
+ return -EEXIST;
+
+ /* Clear the reset status by writing 1 to the status bit */
+- omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST);
++ omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
+ /* de-assert the reset control line */
+- omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL);
++ omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
+ /* wait the status to be set */
+ omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
+- mask),
++ st),
+ MAX_MODULE_HARDRESET_WAIT, c);
+
+ return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+index 49654c8..a1fc62a 100644
+--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
++++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
+@@ -282,7 +282,8 @@ static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+ "not suppose to be used on omap4\n");
+ return 0;
+ }
+-static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
++static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
++ u8 st_shift)
+ {
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+@@ -300,7 +301,7 @@ extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+ /* These omap2_ PRM functions apply to both OMAP2 and 3 */
+ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+ extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+-extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
++extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+
+ #endif /* CONFIG_ARCH_OMAP4 */
+ #endif
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index 6145116..ecaf8c5 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -124,6 +124,7 @@ struct omap_hwmod_dma_info {
+ * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
+ * @name: name of the reset line (module local name)
+ * @rst_shift: Offset of the reset bit
++ * @st_shift: Offset of the reset status bit (OMAP2/3 only)
+ *
+ * @name should be something short, e.g., "cpu0" or "rst". It is defined
+ * locally to the hwmod.
+@@ -131,6 +132,7 @@ struct omap_hwmod_dma_info {
+ struct omap_hwmod_rst_info {
+ const char *name;
+ u8 rst_shift;
++ u8 st_shift;
+ };
+
+ /**
+--
+1.7.1
+
diff --git a/patches/for_next/0227-OMAP2-hwmod-allow-board-files-to-prevent-devices-fro.patch b/patches/for_next/0227-OMAP2-hwmod-allow-board-files-to-prevent-devices-fro.patch
new file mode 100644
index 0000000000000000000000000000000000000000..4e28060a9e8c91cda52d171e339f4f07a78b9c2b
--- /dev/null
+++ b/patches/for_next/0227-OMAP2-hwmod-allow-board-files-to-prevent-devices-fro.patch
@@ -0,0 +1,74 @@
+From 4d2f12b8bfc8c7568a4cda00b02b29dda0ca1b79 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Thu, 10 Mar 2011 03:50:07 -0700
+Subject: [PATCH 227/254] OMAP2+: hwmod: allow board files to prevent devices from being reset upon init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Some boards can't tolerate IP blocks being reset when they are initialized.
+Michael Büsch cites a case with the Nokia N810:
+
+ http://www.spinics.net/lists/linux-omap/msg47277.html
+
+To allow such boards to continue working normally, allow board file
+maintainers to mark IP blocks to prevent them from being reset upon
+init. This is done via a hwmod function, omap_hwmod_no_setup_reset().
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Michael Buesch <mb@bu3sch.de>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 26 ++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 2 ++
+ 2 files changed, 28 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 551d4a9..e2108e5 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -2297,3 +2297,29 @@ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
+
+ return ret;
+ }
++
++/**
++ * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
++ * @oh: struct omap_hwmod *
++ *
++ * Prevent the hwmod @oh from being reset during the setup process.
++ * Intended for use by board-*.c files on boards with devices that
++ * cannot tolerate being reset. Must be called before the hwmod has
++ * been set up. Returns 0 upon success or negative error code upon
++ * failure.
++ */
++int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
++{
++ if (!oh)
++ return -EINVAL;
++
++ if (oh->_state != _HWMOD_STATE_REGISTERED) {
++ pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
++ oh->name);
++ return -EINVAL;
++ }
++
++ oh->flags |= HWMOD_INIT_NO_RESET;
++
++ return 0;
++}
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index ecaf8c5..b32fb6f 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -595,6 +595,8 @@ int omap_hwmod_for_each_by_class(const char *classname,
+ int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
+ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
+
++int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
++
+ /*
+ * Chip variant-specific hwmod init routines - XXX should be converted
+ * to use initcalls once the initial boot ordering is straightened out
+--
+1.7.1
+
diff --git a/patches/for_next/0228-OMAP2-hwmod-add-API-to-handle-autoidle-mode.patch b/patches/for_next/0228-OMAP2-hwmod-add-API-to-handle-autoidle-mode.patch
new file mode 100644
index 0000000000000000000000000000000000000000..777f9948ebd6a473f46ed49509997aa7adeb44f0
--- /dev/null
+++ b/patches/for_next/0228-OMAP2-hwmod-add-API-to-handle-autoidle-mode.patch
@@ -0,0 +1,86 @@
+From 248c2ea07462db10def2b99b90b1162c35995c87 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Thu, 10 Mar 2011 03:50:08 -0700
+Subject: [PATCH 228/254] OMAP2+: hwmod: add API to handle autoidle mode
+
+Create a new API that forms a wrapper to _set_module_autoidle()
+to modify the AUTOIDLE bit.
+
+This API is intended to be used by drivers that requires direct
+manipulation of the AUTOIDLE bits in SYSCONFIG register.
+McBSP driver requires autoidle bit to be enabled/disabled while
+using sidetone feature.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Cc: Paul Walmsley <paul@pwsan.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+[paul@pwsan.com: restrict the hwmod states that the autoidle bit can be changed
+ in; changed function name; dropped "int" from "unsigned int long"]
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/mach-omap2/omap_hwmod.c | 36 ++++++++++++++++++++++++++
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 +
+ 2 files changed, 37 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index e2108e5..a60ac38 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1294,6 +1294,42 @@ static int _idle(struct omap_hwmod *oh)
+ }
+
+ /**
++ * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
++ * @oh: struct omap_hwmod *
++ * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
++ *
++ * Sets the IP block's OCP autoidle bit in hardware, and updates our
++ * local copy. Intended to be used by drivers that require
++ * direct manipulation of the AUTOIDLE bits.
++ * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
++ * along the return value from _set_module_autoidle().
++ *
++ * Any users of this function should be scrutinized carefully.
++ */
++int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
++{
++ u32 v;
++ int retval = 0;
++ unsigned long flags;
++
++ if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
++ return -EINVAL;
++
++ spin_lock_irqsave(&oh->_lock, flags);
++
++ v = oh->_sysc_cache;
++
++ retval = _set_module_autoidle(oh, autoidle, &v);
++
++ if (!retval)
++ _write_sysconfig(v, oh);
++
++ spin_unlock_irqrestore(&oh->_lock, flags);
++
++ return retval;
++}
++
++/**
+ * _shutdown - shutdown an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index b32fb6f..d1bc1f3 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -561,6 +561,7 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
+ int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
+
+ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
++int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
+
+ int omap_hwmod_reset(struct omap_hwmod *oh);
+ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
+--
+1.7.1
+
diff --git a/patches/for_next/0229-OMAP2-clockdomain-add-flag-that-will-block-autodeps-.patch b/patches/for_next/0229-OMAP2-clockdomain-add-flag-that-will-block-autodeps-.patch
new file mode 100644
index 0000000000000000000000000000000000000000..6a81490f98585de5e8e35fdedfa8191ec0c12399
--- /dev/null
+++ b/patches/for_next/0229-OMAP2-clockdomain-add-flag-that-will-block-autodeps-.patch
@@ -0,0 +1,135 @@
+From 8c8007cdc97c24fac64e3ff5fec163a6366780c7 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Thu, 10 Mar 2011 03:50:09 -0700
+Subject: [PATCH 229/254] OMAP2+: clockdomain: add flag that will block autodeps from being added for a clockdomain
+
+Add a new clockdomain flag, CLKDM_NO_AUTODEPS, which, when marked on a
+clockdomain, will prevent "autodeps" from being associated with the
+clockdomain. ("Autodeps" are sleep dependencies and wakeup
+dependencies from/to processor modules that are automatically added to
+a clockdomain when it is in hardware-supervised idle mode. They are
+deprecated -- a relic from the old CDP trees -- but are still in use
+for OMAP3.)
+
+Also, prevent the hwmod code from adding or removing initiator
+dependencies for clockdomains with this flag set.
+
+This patch should allow others to test which clockdomains actually
+still need autodeps.
+
+Thanks to Kevin Hilman <khilman@ti.com> for noting that the original
+version should also modify the hwmod code.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/clockdomain.c | 4 ++--
+ arch/arm/mach-omap2/clockdomain.h | 12 ++++++++++--
+ arch/arm/mach-omap2/omap_hwmod.c | 16 ++++++++++++----
+ 3 files changed, 24 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
+index a0341de..ab87854 100644
+--- a/arch/arm/mach-omap2/clockdomain.c
++++ b/arch/arm/mach-omap2/clockdomain.c
+@@ -173,7 +173,7 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
+ {
+ struct clkdm_autodep *autodep;
+
+- if (!autodeps)
++ if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
+ return;
+
+ for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+@@ -207,7 +207,7 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
+ {
+ struct clkdm_autodep *autodep;
+
+- if (!autodeps)
++ if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
+ return;
+
+ for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
+diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
+index de52f05..85b3dce 100644
+--- a/arch/arm/mach-omap2/clockdomain.h
++++ b/arch/arm/mach-omap2/clockdomain.h
+@@ -4,7 +4,7 @@
+ * OMAP2/3 clockdomain framework functions
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+- * Copyright (C) 2008-2010 Nokia Corporation
++ * Copyright (C) 2008-2011 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+@@ -22,11 +22,19 @@
+ #include <plat/clock.h>
+ #include <plat/cpu.h>
+
+-/* Clockdomain capability flags */
++/*
++ * Clockdomain flags
++ *
++ * XXX Document CLKDM_CAN_* flags
++ *
++ * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
++ * clockdomain. (Currently, this applies to OMAP3 clockdomains only.)
++ */
+ #define CLKDM_CAN_FORCE_SLEEP (1 << 0)
+ #define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
+ #define CLKDM_CAN_ENABLE_AUTO (1 << 2)
+ #define CLKDM_CAN_DISABLE_AUTO (1 << 3)
++#define CLKDM_NO_AUTODEPS (1 << 4)
+
+ #define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
+ #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index a60ac38..4c8329e 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -457,14 +457,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
+ * will be accessed by a particular initiator (e.g., if a module will
+ * be accessed by the IVA, there should be a sleepdep between the IVA
+ * initiator and the module). Only applies to modules in smart-idle
+- * mode. Returns -EINVAL upon error or passes along
+- * clkdm_add_sleepdep() value upon success.
++ * mode. If the clockdomain is marked as not needing autodeps, return
++ * 0 without doing anything. Otherwise, returns -EINVAL upon error or
++ * passes along clkdm_add_sleepdep() value upon success.
+ */
+ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
+ {
+ if (!oh->_clk)
+ return -EINVAL;
+
++ if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
++ return 0;
++
+ return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
+ }
+
+@@ -477,14 +481,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
+ * be accessed by a particular initiator (e.g., if a module will not
+ * be accessed by the IVA, there should be no sleepdep between the IVA
+ * initiator and the module). Only applies to modules in smart-idle
+- * mode. Returns -EINVAL upon error or passes along
+- * clkdm_del_sleepdep() value upon success.
++ * mode. If the clockdomain is marked as not needing autodeps, return
++ * 0 without doing anything. Returns -EINVAL upon error or passes
++ * along clkdm_del_sleepdep() value upon success.
+ */
+ static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
+ {
+ if (!oh->_clk)
+ return -EINVAL;
+
++ if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
++ return 0;
++
+ return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
+ }
+
+--
+1.7.1
+
diff --git a/patches/for_next/0230-omap2-3-dmtimer-Enable-autoidle.patch b/patches/for_next/0230-omap2-3-dmtimer-Enable-autoidle.patch
new file mode 100644
index 0000000000000000000000000000000000000000..137464e277576053142128ccd3088bbc44d75771
--- /dev/null
+++ b/patches/for_next/0230-omap2-3-dmtimer-Enable-autoidle.patch
@@ -0,0 +1,32 @@
+From b830e9805cddaee5e0924746013e1e94c3746b0d Mon Sep 17 00:00:00 2001
+From: Tero Kristo <tero.kristo@nokia.com>
+Date: Thu, 10 Mar 2011 03:50:54 -0700
+Subject: [PATCH 230/254] omap2/3: dmtimer: Enable autoidle
+
+This saves some power. OMAP4 version should check for GPT module ID, as
+autoidle is only supported on a subset of these.
+
+Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+ arch/arm/plat-omap/dmtimer.c | 4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
+index 1d706cf..ee9f6eb 100644
+--- a/arch/arm/plat-omap/dmtimer.c
++++ b/arch/arm/plat-omap/dmtimer.c
+@@ -342,6 +342,10 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
+ l |= 0x02 << 3; /* Set to smart-idle mode */
+ l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
+
++ /* Enable autoidle on OMAP2 / OMAP3 */
++ if (cpu_is_omap24xx() || cpu_is_omap34xx())
++ l |= 0x1 << 0;
++
+ /*
+ * Enable wake-up on OMAP2 CPUs.
+ */
+--
+1.7.1
+
diff --git a/patches/for_next/0231-omap-Fix-H4-init_irq-to-not-call-h4_init_flash.patch b/patches/for_next/0231-omap-Fix-H4-init_irq-to-not-call-h4_init_flash.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e92563e594449c1f8aa840c9ca8ab167ef18ee0d
--- /dev/null
+++ b/patches/for_next/0231-omap-Fix-H4-init_irq-to-not-call-h4_init_flash.patch
@@ -0,0 +1,36 @@
+From 385e3a9503ae6ac3444d246566940f72a7ea9ed3 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Thu, 10 Mar 2011 09:51:29 -0800
+Subject: [PATCH 231/254] omap: Fix H4 init_irq to not call h4_init_flash
+
+There should be no reason to call h4_init_flash this
+early. It causes problems as things are not yet initialized.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-h4.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
+index 7e6bf4f..bac7933 100644
+--- a/arch/arm/mach-omap2/board-h4.c
++++ b/arch/arm/mach-omap2/board-h4.c
+@@ -299,7 +299,6 @@ static void __init omap_h4_init_early(void)
+ static void __init omap_h4_init_irq(void)
+ {
+ omap_init_irq();
+- h4_init_flash();
+ }
+
+ static struct at24_platform_data m24c01 = {
+@@ -372,6 +371,7 @@ static void __init omap_h4_init(void)
+ platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
+ omap2_usbfs_init(&h4_usb_config);
+ omap_serial_init();
++ h4_init_flash();
+ }
+
+ static void __init omap_h4_map_io(void)
+--
+1.7.1
+
diff --git a/patches/for_next/0232-OMAP3-PM-Use-ARMv7-supported-instructions-instead-of.patch b/patches/for_next/0232-OMAP3-PM-Use-ARMv7-supported-instructions-instead-of.patch
new file mode 100644
index 0000000000000000000000000000000000000000..49d773e2796e6fa10f5d1bc3c153c2066c4c4a55
--- /dev/null
+++ b/patches/for_next/0232-OMAP3-PM-Use-ARMv7-supported-instructions-instead-of.patch
@@ -0,0 +1,78 @@
+From a1d3ebe416c25befa861e92b7c690bf493cd104e Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Sun, 23 Jan 2011 19:00:34 +0530
+Subject: [PATCH 232/254] OMAP3: PM: Use ARMv7 supported instructions instead of legacy CP15 ones
+
+On ARMv7 dsb, dmb instructions are supported and can be used directly
+instead of their cp15 equivalnet. Also remove the opcodes for smc
+and use the available instruction directly in OMAP3 low power asm code
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/sleep34xx.S | 21 ++++++++++-----------
+ 1 files changed, 10 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index 0c1b335..1c17ee8 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -144,8 +144,8 @@ ENTRY(save_secure_ram_context)
+ mov r1, #0 @ set task id for ROM code in r1
+ mov r2, #4 @ set some flags in r2, r6
+ mov r6, #0xff
+- mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+- mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
++ dsb @ data write barrier
++ dmb @ data memory barrier
+ smc #1 @ call SMI monitor (smi #1)
+ nop
+ nop
+@@ -314,9 +314,8 @@ omap3_do_wfi:
+ str r5, [r4] @ write back to SDRC_POWER register
+
+ /* Data memory barrier and Data sync barrier */
+- mov r1, #0
+- mcr p15, 0, r1, c7, c10, 4
+- mcr p15, 0, r1, c7, c10, 5
++ dsb
++ dmb
+
+ /*
+ * ===================================
+@@ -431,8 +430,8 @@ skipl2dis:
+ mov r2, #4 @ set some flags in r2, r6
+ mov r6, #0xff
+ adr r3, l2_inv_api_params @ r3 points to dummy parameters
+- mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+- mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
++ dsb @ data write barrier
++ dmb @ data memory barrier
+ smc #1 @ call SMI monitor (smi #1)
+ /* Write to Aux control register to set some bits */
+ mov r0, #42 @ set service ID for PPA
+@@ -442,8 +441,8 @@ skipl2dis:
+ mov r6, #0xff
+ ldr r4, scratchpad_base
+ ldr r3, [r4, #0xBC] @ r3 points to parameters
+- mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+- mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
++ dsb @ data write barrier
++ dmb @ data memory barrier
+ smc #1 @ call SMI monitor (smi #1)
+
+ #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
+@@ -457,8 +456,8 @@ skipl2dis:
+ ldr r4, scratchpad_base
+ ldr r3, [r4, #0xBC]
+ adds r3, r3, #8 @ r3 points to parameters
+- mcr p15, 0, r0, c7, c10, 4 @ data write barrier
+- mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
++ dsb @ data write barrier
++ dmb @ data memory barrier
+ smc #1 @ call SMI monitor (smi #1)
+ #endif
+ b logic_l1_restore
+--
+1.7.1
+
diff --git a/patches/for_next/0233-OMAP3-PM-Fix-the-MMU-on-sequence-in-the-asm-code.patch b/patches/for_next/0233-OMAP3-PM-Fix-the-MMU-on-sequence-in-the-asm-code.patch
new file mode 100644
index 0000000000000000000000000000000000000000..049c31165c4882bc7f80de712d8c8bf7cb0473b5
--- /dev/null
+++ b/patches/for_next/0233-OMAP3-PM-Fix-the-MMU-on-sequence-in-the-asm-code.patch
@@ -0,0 +1,39 @@
+From 121111442a3e03ba7d48adc7db50f2abe0bcee20 Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Sun, 23 Jan 2011 16:04:39 +0530
+Subject: [PATCH 233/254] OMAP3: PM: Fix the MMU on sequence in the asm code
+
+Add necessary barriers after enabling MMU. Also use the sane way to
+load pc and jump to it instead of executing ldma first up.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/sleep34xx.S | 5 +++++
+ 1 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index 1c17ee8..a31845a 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -617,12 +617,17 @@ usettbr0:
+ ldr r2, cache_pred_disable_mask
+ and r4, r2
+ mcr p15, 0, r4, c1, c0, 0
++ dsb
++ isb
++ ldr r0, =restoremmu_on
++ bx r0
+
+ /*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
++restoremmu_on:
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
+
+
+--
+1.7.1
+
diff --git a/patches/for_next/0234-OMAP3-PM-Allow-the-cache-clean-when-L1-is-lost.patch b/patches/for_next/0234-OMAP3-PM-Allow-the-cache-clean-when-L1-is-lost.patch
new file mode 100644
index 0000000000000000000000000000000000000000..60e2cb4253eb21deec342aa3a3259c9a1f898eb6
--- /dev/null
+++ b/patches/for_next/0234-OMAP3-PM-Allow-the-cache-clean-when-L1-is-lost.patch
@@ -0,0 +1,56 @@
+From e4f2322bfc345f173e1bb70a3022c2a9b504a1e4 Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Sun, 23 Jan 2011 19:33:53 +0530
+Subject: [PATCH 234/254] OMAP3: PM: Allow the cache clean when L1 is lost.
+
+When L1 cache is suppose to be lost, it needs to be cleaned before
+entrering to the low power mode.
+
+While at this, also fix few comments and remove un-necessary
+clean_l2 lable.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/sleep34xx.S | 15 +++------------
+ 1 files changed, 3 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index a31845a..f75a166 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -188,12 +188,12 @@ ENTRY(omap34xx_cpu_suspend)
+ stmfd sp!, {r0-r12, lr} @ save registers on stack
+
+ /*
+- * r0 contains restore pointer in sdram
++ * r0 contains CPU context save/restore pointer in sdram
+ * r1 contains information about saving context:
+ * 0 - No context lost
+ * 1 - Only L1 and logic lost
+- * 2 - Only L2 lost
+- * 3 - Both L1 and L2 lost
++ * 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
++ * 3 - Both L1 and L2 lost and logic lost
+ */
+
+ /* Directly jump to WFI is the context save is not required */
+@@ -278,15 +278,6 @@ l1_logic_lost:
+
+ clean_caches:
+ /*
+- * Clean Data or unified cache to POU
+- * How to invalidate only L1 cache???? - #FIX_ME#
+- * mcr p15, 0, r11, c7, c11, 1
+- */
+- cmp r1, #0x1 @ Check whether L2 inval is required
+- beq omap3_do_wfi
+-
+-clean_l2:
+- /*
+ * jump out to kernel flush routine
+ * - reuse that code is better
+ * - it executes in a cached space so is faster than refetch per-block
+--
+1.7.1
+
diff --git a/patches/for_next/0235-OMAP3-PM-Remove-un-necessary-cp15-registers-form-low.patch b/patches/for_next/0235-OMAP3-PM-Remove-un-necessary-cp15-registers-form-low.patch
new file mode 100644
index 0000000000000000000000000000000000000000..bfb9c094bda3d61235c8c8f7454a63ed60b30c9d
--- /dev/null
+++ b/patches/for_next/0235-OMAP3-PM-Remove-un-necessary-cp15-registers-form-low.patch
@@ -0,0 +1,200 @@
+From c2b782bbce12c991743d7ff9ea50cf5aaf1798ba Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Sun, 23 Jan 2011 21:37:03 +0530
+Subject: [PATCH 235/254] OMAP3: PM: Remove un-necessary cp15 registers form low power cpu context
+
+The current code saves few un-necessary registers which are read-only or
+write-only, unused CP15 registers.
+
+Remove them and keep only necessary CP15 registers part of
+low power context save/restore.
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/sleep34xx.S | 156 ++++++++++-----------------------------
+ 1 files changed, 40 insertions(+), 116 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index f75a166..99e43cc 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -214,66 +214,29 @@ save_context_wfi:
+ beq clean_caches
+
+ l1_logic_lost:
+- /* Store sp and spsr to SDRAM */
+- mov r4, sp
+- mrs r5, spsr
+- mov r6, lr
++ mov r4, sp @ Store sp
++ mrs r5, spsr @ Store spsr
++ mov r6, lr @ Store lr
+ stmia r8!, {r4-r6}
+- /* Save all ARM registers */
+- /* Coprocessor access control register */
+- mrc p15, 0, r6, c1, c0, 2
+- stmia r8!, {r6}
+- /* TTBR0, TTBR1 and Translation table base control */
+- mrc p15, 0, r4, c2, c0, 0
+- mrc p15, 0, r5, c2, c0, 1
+- mrc p15, 0, r6, c2, c0, 2
+- stmia r8!, {r4-r6}
+- /*
+- * Domain access control register, data fault status register,
+- * and instruction fault status register
+- */
+- mrc p15, 0, r4, c3, c0, 0
+- mrc p15, 0, r5, c5, c0, 0
+- mrc p15, 0, r6, c5, c0, 1
+- stmia r8!, {r4-r6}
+- /*
+- * Data aux fault status register, instruction aux fault status,
+- * data fault address register and instruction fault address register
+- */
+- mrc p15, 0, r4, c5, c1, 0
+- mrc p15, 0, r5, c5, c1, 1
+- mrc p15, 0, r6, c6, c0, 0
+- mrc p15, 0, r7, c6, c0, 2
+- stmia r8!, {r4-r7}
+- /*
+- * user r/w thread and process ID, user r/o thread and process ID,
+- * priv only thread and process ID, cache size selection
+- */
+- mrc p15, 0, r4, c13, c0, 2
+- mrc p15, 0, r5, c13, c0, 3
+- mrc p15, 0, r6, c13, c0, 4
+- mrc p15, 2, r7, c0, c0, 0
++
++ mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
++ mrc p15, 0, r5, c2, c0, 0 @ TTBR0
++ mrc p15, 0, r6, c2, c0, 1 @ TTBR1
++ mrc p15, 0, r7, c2, c0, 2 @ TTBCR
+ stmia r8!, {r4-r7}
+- /* Data TLB lockdown, instruction TLB lockdown registers */
+- mrc p15, 0, r5, c10, c0, 0
+- mrc p15, 0, r6, c10, c0, 1
+- stmia r8!, {r5-r6}
+- /* Secure or non secure vector base address, FCSE PID, Context PID*/
+- mrc p15, 0, r4, c12, c0, 0
+- mrc p15, 0, r5, c13, c0, 0
+- mrc p15, 0, r6, c13, c0, 1
+- stmia r8!, {r4-r6}
+- /* Primary remap, normal remap registers */
+- mrc p15, 0, r4, c10, c2, 0
+- mrc p15, 0, r5, c10, c2, 1
+- stmia r8!,{r4-r5}
+
+- /* Store current cpsr*/
+- mrs r2, cpsr
+- stmia r8!, {r2}
++ mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
++ mrc p15, 0, r5, c10, c2, 0 @ PRRR
++ mrc p15, 0, r6, c10, c2, 1 @ NMRR
++ stmia r8!,{r4-r6}
++
++ mrc p15, 0, r4, c13, c0, 1 @ Context ID
++ mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
++ mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
++ mrs r7, cpsr @ Store current cpsr
++ stmia r8!, {r4-r7}
+
+- mrc p15, 0, r4, c1, c0, 0
+- /* save control register */
++ mrc p15, 0, r4, c1, c0, 0 @ save control register
+ stmia r8!, {r4}
+
+ clean_caches:
+@@ -489,68 +452,29 @@ skipl2reen:
+ ldr r4, scratchpad_base
+ ldr r3, [r4,#0xBC]
+ adds r3, r3, #16
++
+ ldmia r3!, {r4-r6}
+- mov sp, r4
+- msr spsr_cxsf, r5
+- mov lr, r6
+-
+- ldmia r3!, {r4-r9}
+- /* Coprocessor access Control Register */
+- mcr p15, 0, r4, c1, c0, 2
+-
+- /* TTBR0 */
+- MCR p15, 0, r5, c2, c0, 0
+- /* TTBR1 */
+- MCR p15, 0, r6, c2, c0, 1
+- /* Translation table base control register */
+- MCR p15, 0, r7, c2, c0, 2
+- /* Domain access Control Register */
+- MCR p15, 0, r8, c3, c0, 0
+- /* Data fault status Register */
+- MCR p15, 0, r9, c5, c0, 0
+-
+- ldmia r3!,{r4-r8}
+- /* Instruction fault status Register */
+- MCR p15, 0, r4, c5, c0, 1
+- /* Data Auxiliary Fault Status Register */
+- MCR p15, 0, r5, c5, c1, 0
+- /* Instruction Auxiliary Fault Status Register*/
+- MCR p15, 0, r6, c5, c1, 1
+- /* Data Fault Address Register */
+- MCR p15, 0, r7, c6, c0, 0
+- /* Instruction Fault Address Register*/
+- MCR p15, 0, r8, c6, c0, 2
+- ldmia r3!,{r4-r7}
++ mov sp, r4 @ Restore sp
++ msr spsr_cxsf, r5 @ Restore spsr
++ mov lr, r6 @ Restore lr
+
+- /* User r/w thread and process ID */
+- MCR p15, 0, r4, c13, c0, 2
+- /* User ro thread and process ID */
+- MCR p15, 0, r5, c13, c0, 3
+- /* Privileged only thread and process ID */
+- MCR p15, 0, r6, c13, c0, 4
+- /* Cache size selection */
+- MCR p15, 2, r7, c0, c0, 0
+- ldmia r3!,{r4-r8}
+- /* Data TLB lockdown registers */
+- MCR p15, 0, r4, c10, c0, 0
+- /* Instruction TLB lockdown registers */
+- MCR p15, 0, r5, c10, c0, 1
+- /* Secure or Nonsecure Vector Base Address */
+- MCR p15, 0, r6, c12, c0, 0
+- /* FCSE PID */
+- MCR p15, 0, r7, c13, c0, 0
+- /* Context PID */
+- MCR p15, 0, r8, c13, c0, 1
+-
+- ldmia r3!,{r4-r5}
+- /* Primary memory remap register */
+- MCR p15, 0, r4, c10, c2, 0
+- /* Normal memory remap register */
+- MCR p15, 0, r5, c10, c2, 1
+-
+- /* Restore cpsr */
+- ldmia r3!,{r4} @ load CPSR from SDRAM
+- msr cpsr, r4 @ store cpsr
++ ldmia r3!, {r4-r7}
++ mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
++ mcr p15, 0, r5, c2, c0, 0 @ TTBR0
++ mcr p15, 0, r6, c2, c0, 1 @ TTBR1
++ mcr p15, 0, r7, c2, c0, 2 @ TTBCR
++
++ ldmia r3!,{r4-r6}
++ mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
++ mcr p15, 0, r5, c10, c2, 0 @ PRRR
++ mcr p15, 0, r6, c10, c2, 1 @ NMRR
++
++
++ ldmia r3!,{r4-r7}
++ mcr p15, 0, r4, c13, c0, 1 @ Context ID
++ mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
++ mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
++ msr cpsr, r7 @ store cpsr
+
+ /* Enabling MMU here */
+ mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
+--
+1.7.1
+
diff --git a/patches/for_next/0236-OMAP3-PM-Clear-the-SCTLR-C-bit-in-asm-code-to-preven.patch b/patches/for_next/0236-OMAP3-PM-Clear-the-SCTLR-C-bit-in-asm-code-to-preven.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5d6d4f1e3718651d205bbf00e7b120258ad4c6d0
--- /dev/null
+++ b/patches/for_next/0236-OMAP3-PM-Clear-the-SCTLR-C-bit-in-asm-code-to-preven.patch
@@ -0,0 +1,65 @@
+From 7a9ea7da89e6fc64794ba3c5308deea569364bbe Mon Sep 17 00:00:00 2001
+From: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Date: Sun, 23 Jan 2011 22:51:09 +0530
+Subject: [PATCH 236/254] OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation
+
+On the newer ARM processors like CortexA8, CortexA9, the caches can be
+speculatively loaded while they are getting flushed.
+
+Clear the SCTLR C bit to prevent further data cache allocation as
+part of cache clean routine
+
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/sleep34xx.S | 27 +++++++++++++++++++++++++++
+ 1 files changed, 27 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index 99e43cc..e60ac1f 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -246,6 +246,27 @@ clean_caches:
+ * - it executes in a cached space so is faster than refetch per-block
+ * - should be faster and will change with kernel
+ * - 'might' have to copy address, load and jump to it
++ * Flush all data from the L1 data cache before disabling
++ * SCTLR.C bit.
++ */
++ ldr r1, kernel_flush
++ mov lr, pc
++ bx r1
++
++ /*
++ * Clear the SCTLR.C bit to prevent further data cache
++ * allocation. Clearing SCTLR.C would make all the data accesses
++ * strongly ordered and would not hit the cache.
++ */
++ mrc p15, 0, r0, c1, c0, 0
++ bic r0, r0, #(1 << 2) @ Disable the C bit
++ mcr p15, 0, r0, c1, c0, 0
++ isb
++
++ /*
++ * Invalidate L1 data cache. Even though only invalidate is
++ * necessary exported flush API is used here. Doing clean
++ * on already clean cache would be almost NOP.
+ */
+ ldr r1, kernel_flush
+ blx r1
+@@ -295,6 +316,12 @@ omap3_do_wfi:
+ nop
+ bl wait_sdrc_ok
+
++ mrc p15, 0, r0, c1, c0, 0
++ tst r0, #(1 << 2) @ Check C bit enabled?
++ orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
++ mcreq p15, 0, r0, c1, c0, 0
++ isb
++
+ /*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+--
+1.7.1
+
diff --git a/patches/for_next/0237-OMAP2-voltage-reorganize-split-code-from-data.patch b/patches/for_next/0237-OMAP2-voltage-reorganize-split-code-from-data.patch
new file mode 100644
index 0000000000000000000000000000000000000000..ab5ce66e18c7d30d32811c69563d339c6b510668
--- /dev/null
+++ b/patches/for_next/0237-OMAP2-voltage-reorganize-split-code-from-data.patch
@@ -0,0 +1,2583 @@
+From cae1a62b77ed722f4cf0de65fbb76bdafa9b0fa5 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Thu, 10 Mar 2011 22:17:45 -0700
+Subject: [PATCH 237/254] OMAP2+: voltage: reorganize, split code from data
+
+This is a first pass at reorganizing mach-omap2/voltage.c:
+
+- Separate almost all of the data from the code of mach-omap2/voltage.c.
+ The code remains in mach-omap2/voltage.c. The data goes into one
+ of several places, depending on what type of data it is:
+
+ - Silicon process/validation data: mach-omap2/opp*_data.c
+ - VC (Voltage Controller) data: mach-omap2/vc*_data.c
+ - VP (Voltage Processor) data: mach-omap2/vp*_data.c
+ - Voltage domain data: mach-omap2/voltagedomains*_data.c
+
+ The ultimate goal is for all this data to be autogenerated, the same
+ way we autogenerate the rest of our data.
+
+- Separate VC and VP common data from VDD-specific VC and VP data.
+
+- Separate common voltage.c code from SoC-specific code; reuse common code.
+
+- Reorganize structures to avoid unnecessary memory loss due to unpacked
+ fields.
+
+There is much left to be done. VC code and VP code should be separated out
+into vc*.c and vp*.c files. Many fields in the existing structures are
+superfluous, and should be removed. Some code in voltage.c seems to be
+duplicated; that code should be moved into functions of its own. Proper
+voltage domain code should be created, as was done with the powerdomain
+and clockdomains, and powerdomains should reference voltagedomains.
+
+Thanks to Shweta Gulati <shweta.gulati@ti.com> for comments. Thanks
+to Rajendra Nayak <rnayak@ti.com> for finding and fixing some bugs
+that prevented OMAP4 from booting:
+
+ https://patchwork.kernel.org/patch/587311/
+
+His patch has been folded into this one to avoid breaking OMAP4
+between patches. Thanks also to Kevin Hilman <khilman@ti.com> for
+finding and fixing a compile problem when !CONFIG_PM:
+
+ http://www.spinics.net/lists/arm-kernel/msg118067.html
+
+His patch has also been folded into this one to avoid breaking
+!CONFIG_PM builds.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Shweta Gulati <shweta.gulati@ti.com>
+Cc: Rajendra Nayak <rnayak@ti.com>
+Cc: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/Makefile | 22 +-
+ arch/arm/mach-omap2/omap_opp_data.h | 24 +
+ arch/arm/mach-omap2/opp3xxx_data.c | 66 ++-
+ arch/arm/mach-omap2/opp4xxx_data.c | 43 +-
+ arch/arm/mach-omap2/vc.h | 83 ++
+ arch/arm/mach-omap2/vc3xxx_data.c | 63 ++
+ arch/arm/mach-omap2/vc44xx_data.c | 75 ++
+ arch/arm/mach-omap2/voltage.c | 1017 +++++++------------------
+ arch/arm/mach-omap2/voltage.h | 89 ++-
+ arch/arm/mach-omap2/voltagedomains3xxx_data.c | 95 +++
+ arch/arm/mach-omap2/voltagedomains44xx_data.c | 102 +++
+ arch/arm/mach-omap2/vp.h | 143 ++++
+ arch/arm/mach-omap2/vp3xxx_data.c | 82 ++
+ arch/arm/mach-omap2/vp44xx_data.c | 100 +++
+ 14 files changed, 1226 insertions(+), 778 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/vc.h
+ create mode 100644 arch/arm/mach-omap2/vc3xxx_data.c
+ create mode 100644 arch/arm/mach-omap2/vc44xx_data.c
+ create mode 100644 arch/arm/mach-omap2/voltagedomains3xxx_data.c
+ create mode 100644 arch/arm/mach-omap2/voltagedomains44xx_data.c
+ create mode 100644 arch/arm/mach-omap2/vp.h
+ create mode 100644 arch/arm/mach-omap2/vp3xxx_data.c
+ create mode 100644 arch/arm/mach-omap2/vp44xx_data.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 534d89a..82b2a67 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -59,10 +59,10 @@ endif
+ # Power Management
+ ifeq ($(CONFIG_PM),y)
+ obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
+-obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o voltage.o
+-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \
++obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o
++obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \
+ cpuidle34xx.o pm_bus.o
+-obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o
++obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o
+ obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+ obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
+ obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
+@@ -78,13 +78,25 @@ endif
+
+ # PRCM
+ obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+-obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
++obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
++ vc3xxx_data.o vp3xxx_data.o
+ # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
+ # will be removed once the OMAP4 part of the codebase is converted to
+ # use OMAP4-specific PRCM functions.
+ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
+ cm44xx.o prcm_mpu44xx.o \
+- prminst44xx.o
++ prminst44xx.o vc44xx_data.o \
++ vp44xx_data.o
++
++# OMAP voltage domains
++ifeq ($(CONFIG_PM),y)
++voltagedomain-common := voltage.o
++obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
++obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
++ voltagedomains3xxx_data.o
++obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \
++ voltagedomains44xx_data.o
++endif
+
+ # OMAP powerdomain framework
+ powerdomain-common += powerdomain.o powerdomain-common.o
+diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
+index 46ac27d..c784c12 100644
+--- a/arch/arm/mach-omap2/omap_opp_data.h
++++ b/arch/arm/mach-omap2/omap_opp_data.h
+@@ -21,6 +21,8 @@
+
+ #include <plat/omap_hwmod.h>
+
++#include "voltage.h"
++
+ /*
+ * *BIG FAT WARNING*:
+ * USE the following ONLY in opp data initialization common to an SoC.
+@@ -65,8 +67,30 @@ struct omap_opp_def {
+ .u_volt = _uv, \
+ }
+
++/*
++ * Initialization wrapper used to define SmartReflex process data
++ * XXX Is this needed? Just use C99 initializers in data files?
++ */
++#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain) \
++{ \
++ .volt_nominal = _v_nom, \
++ .sr_efuse_offs = _efuse_offs, \
++ .sr_errminlimit = _errminlimit, \
++ .vp_errgain = _errgain \
++}
++
+ /* Use this to initialize the default table */
+ extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+ u32 opp_def_size);
+
++
++extern struct omap_volt_data omap34xx_vddmpu_volt_data[];
++extern struct omap_volt_data omap34xx_vddcore_volt_data[];
++extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
++extern struct omap_volt_data omap36xx_vddcore_volt_data[];
++
++extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[];
++extern struct omap_volt_data omap44xx_vdd_iva_volt_data[];
++extern struct omap_volt_data omap44xx_vdd_core_volt_data[];
++
+ #endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
+diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
+index fd3a1af..d2bd1bd 100644
+--- a/arch/arm/mach-omap2/opp3xxx_data.c
++++ b/arch/arm/mach-omap2/opp3xxx_data.c
+@@ -4,8 +4,9 @@
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Nishanth Menon
+ * Kevin Hilman
+- * Copyright (C) 2010 Nokia Corporation.
++ * Copyright (C) 2010-2011 Nokia Corporation.
+ * Eduardo Valentin
++ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -20,9 +21,72 @@
+
+ #include <plat/cpu.h>
+
++#include "control.h"
+ #include "omap_opp_data.h"
+ #include "pm.h"
+
++/* 34xx */
++
++/* VDD1 */
++
++#define OMAP3430_VDD_MPU_OPP1_UV 975000
++#define OMAP3430_VDD_MPU_OPP2_UV 1075000
++#define OMAP3430_VDD_MPU_OPP3_UV 1200000
++#define OMAP3430_VDD_MPU_OPP4_UV 1270000
++#define OMAP3430_VDD_MPU_OPP5_UV 1350000
++
++struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
++ VOLT_DATA_DEFINE(0, 0, 0, 0),
++};
++
++/* VDD2 */
++
++#define OMAP3430_VDD_CORE_OPP1_UV 975000
++#define OMAP3430_VDD_CORE_OPP2_UV 1050000
++#define OMAP3430_VDD_CORE_OPP3_UV 1150000
++
++struct omap_volt_data omap34xx_vddcore_volt_data[] = {
++ VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
++ VOLT_DATA_DEFINE(0, 0, 0, 0),
++};
++
++/* 36xx */
++
++/* VDD1 */
++
++#define OMAP3630_VDD_MPU_OPP50_UV 1012500
++#define OMAP3630_VDD_MPU_OPP100_UV 1200000
++#define OMAP3630_VDD_MPU_OPP120_UV 1325000
++#define OMAP3630_VDD_MPU_OPP1G_UV 1375000
++
++struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
++ VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
++ VOLT_DATA_DEFINE(0, 0, 0, 0),
++};
++
++/* VDD2 */
++
++#define OMAP3630_VDD_CORE_OPP50_UV 1000000
++#define OMAP3630_VDD_CORE_OPP100_UV 1200000
++
++struct omap_volt_data omap36xx_vddcore_volt_data[] = {
++ VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
++ VOLT_DATA_DEFINE(0, 0, 0, 0),
++};
++
++/* OPP data */
++
+ static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
+ /* MPU OPP1 */
+ OPP_INITIALIZER("mpu", true, 125000000, 975000),
+diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
+index f0e9939..5030794 100644
+--- a/arch/arm/mach-omap2/opp4xxx_data.c
++++ b/arch/arm/mach-omap2/opp4xxx_data.c
+@@ -5,8 +5,9 @@
+ * Nishanth Menon
+ * Kevin Hilman
+ * Thara Gopinath
+- * Copyright (C) 2010 Nokia Corporation.
++ * Copyright (C) 2010-2011 Nokia Corporation.
+ * Eduardo Valentin
++ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -21,9 +22,49 @@
+
+ #include <plat/cpu.h>
+
++#include "control.h"
+ #include "omap_opp_data.h"
+ #include "pm.h"
+
++/*
++ * Structures containing OMAP4430 voltage supported and various
++ * voltage dependent data for each VDD.
++ */
++
++#define OMAP4430_VDD_MPU_OPP50_UV 930000
++#define OMAP4430_VDD_MPU_OPP100_UV 1100000
++#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000
++#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000
++
++struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
++ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
++ VOLT_DATA_DEFINE(0, 0, 0, 0),
++};
++
++#define OMAP4430_VDD_IVA_OPP50_UV 930000
++#define OMAP4430_VDD_IVA_OPP100_UV 1100000
++#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000
++
++struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
++ VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
++ VOLT_DATA_DEFINE(0, 0, 0, 0),
++};
++
++#define OMAP4430_VDD_CORE_OPP50_UV 930000
++#define OMAP4430_VDD_CORE_OPP100_UV 1100000
++
++struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
++ VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
++ VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
++ VOLT_DATA_DEFINE(0, 0, 0, 0),
++};
++
++
+ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+ /* MPU OPP1 - OPP50 */
+ OPP_INITIALIZER("mpu", true, 300000000, 1100000),
+diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
+new file mode 100644
+index 0000000..e776777
+--- /dev/null
++++ b/arch/arm/mach-omap2/vc.h
+@@ -0,0 +1,83 @@
++/*
++ * OMAP3/4 Voltage Controller (VC) structure and macro definitions
++ *
++ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
++ * Rajendra Nayak <rnayak@ti.com>
++ * Lesly A M <x0080970@ti.com>
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2008, 2011 Nokia Corporation
++ * Kalle Jokiniemi
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License version
++ * 2 as published by the Free Software Foundation.
++ */
++#ifndef __ARCH_ARM_MACH_OMAP2_VC_H
++#define __ARCH_ARM_MACH_OMAP2_VC_H
++
++#include <linux/kernel.h>
++
++/**
++ * struct omap_vc_common_data - per-VC register/bitfield data
++ * @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
++ * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
++ * @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
++ * @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
++ * @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
++ * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
++ * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
++ * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
++ * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
++ * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
++ * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
++ * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
++ *
++ * XXX One of cmd_on_mask and cmd_on_shift are not needed
++ * XXX VALID should probably be a shift, not a mask
++ */
++struct omap_vc_common_data {
++ u32 cmd_on_mask;
++ u32 valid;
++ u8 smps_sa_reg;
++ u8 smps_volra_reg;
++ u8 bypass_val_reg;
++ u8 data_shift;
++ u8 slaveaddr_shift;
++ u8 regaddr_shift;
++ u8 cmd_on_shift;
++ u8 cmd_onlp_shift;
++ u8 cmd_ret_shift;
++ u8 cmd_off_shift;
++};
++
++/**
++ * struct omap_vc_instance_data - VC per-instance data
++ * @vc_common: pointer to VC common data for this platform
++ * @smps_sa_mask: SA* bitmask in the PRM_VC_SMPS_SA register
++ * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
++ * @smps_sa_shift: SA* field shift in the PRM_VC_SMPS_SA register
++ * @smps_volra_shift: VOLRA* field shift in the PRM_VC_VOL_RA register
++ *
++ * XXX It is not necessary to have both a *_mask and a *_shift -
++ * remove one
++ */
++struct omap_vc_instance_data {
++ const struct omap_vc_common_data *vc_common;
++ u32 smps_sa_mask;
++ u32 smps_volra_mask;
++ u8 cmdval_reg;
++ u8 smps_sa_shift;
++ u8 smps_volra_shift;
++};
++
++extern struct omap_vc_instance_data omap3_vc1_data;
++extern struct omap_vc_instance_data omap3_vc2_data;
++
++extern struct omap_vc_instance_data omap4_vc_mpu_data;
++extern struct omap_vc_instance_data omap4_vc_iva_data;
++extern struct omap_vc_instance_data omap4_vc_core_data;
++
++#endif
++
+diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
+new file mode 100644
+index 0000000..f37dc4b
+--- /dev/null
++++ b/arch/arm/mach-omap2/vc3xxx_data.c
+@@ -0,0 +1,63 @@
++/*
++ * OMAP3 Voltage Controller (VC) data
++ *
++ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
++ * Rajendra Nayak <rnayak@ti.com>
++ * Lesly A M <x0080970@ti.com>
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2008, 2011 Nokia Corporation
++ * Kalle Jokiniemi
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/init.h>
++
++#include <plat/common.h>
++
++#include "prm-regbits-34xx.h"
++#include "voltage.h"
++
++#include "vc.h"
++
++/*
++ * VC data common to 34xx/36xx chips
++ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
++ */
++static struct omap_vc_common_data omap3_vc_common = {
++ .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET,
++ .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
++ .bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
++ .data_shift = OMAP3430_DATA_SHIFT,
++ .slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
++ .regaddr_shift = OMAP3430_REGADDR_SHIFT,
++ .valid = OMAP3430_VALID_MASK,
++ .cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT,
++ .cmd_on_mask = OMAP3430_VC_CMD_ON_MASK,
++ .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
++ .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
++ .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
++};
++
++struct omap_vc_instance_data omap3_vc1_data = {
++ .vc_common = &omap3_vc_common,
++ .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
++ .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
++ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
++ .smps_volra_shift = OMAP3430_VOLRA0_SHIFT,
++ .smps_volra_mask = OMAP3430_VOLRA0_MASK,
++};
++
++struct omap_vc_instance_data omap3_vc2_data = {
++ .vc_common = &omap3_vc_common,
++ .cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
++ .smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
++ .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
++ .smps_volra_shift = OMAP3430_VOLRA1_SHIFT,
++ .smps_volra_mask = OMAP3430_VOLRA1_MASK,
++};
+diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
+new file mode 100644
+index 0000000..a98da8d
+--- /dev/null
++++ b/arch/arm/mach-omap2/vc44xx_data.c
+@@ -0,0 +1,75 @@
++/*
++ * OMAP4 Voltage Controller (VC) data
++ *
++ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
++ * Rajendra Nayak <rnayak@ti.com>
++ * Lesly A M <x0080970@ti.com>
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2008, 2011 Nokia Corporation
++ * Kalle Jokiniemi
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/init.h>
++
++#include <plat/common.h>
++
++#include "prm44xx.h"
++#include "prm-regbits-44xx.h"
++#include "voltage.h"
++
++#include "vc.h"
++
++/*
++ * VC data common to 44xx chips
++ * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
++ */
++static const struct omap_vc_common_data omap4_vc_common = {
++ .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
++ .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
++ .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
++ .data_shift = OMAP4430_DATA_SHIFT,
++ .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT,
++ .regaddr_shift = OMAP4430_REGADDR_SHIFT,
++ .valid = OMAP4430_VALID_MASK,
++ .cmd_on_shift = OMAP4430_ON_SHIFT,
++ .cmd_on_mask = OMAP4430_ON_MASK,
++ .cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
++ .cmd_ret_shift = OMAP4430_RET_SHIFT,
++ .cmd_off_shift = OMAP4430_OFF_SHIFT,
++};
++
++/* VC instance data for each controllable voltage line */
++struct omap_vc_instance_data omap4_vc_mpu_data = {
++ .vc_common = &omap4_vc_common,
++ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
++ .smps_sa_shift = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT,
++ .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
++ .smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT,
++ .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
++};
++
++struct omap_vc_instance_data omap4_vc_iva_data = {
++ .vc_common = &omap4_vc_common,
++ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
++ .smps_sa_shift = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT,
++ .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
++ .smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT,
++ .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
++};
++
++struct omap_vc_instance_data omap4_vc_core_data = {
++ .vc_common = &omap4_vc_common,
++ .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
++ .smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT,
++ .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
++ .smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT,
++ .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
++};
++
+diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
+index 3c9bcdc..c6facf7 100644
+--- a/arch/arm/mach-omap2/voltage.c
++++ b/arch/arm/mach-omap2/voltage.c
+@@ -7,8 +7,9 @@
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ *
+- * Copyright (C) 2008 Nokia Corporation
++ * Copyright (C) 2008, 2011 Nokia Corporation
+ * Kalle Jokiniemi
++ * Paul Walmsley
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+@@ -36,284 +37,28 @@
+
+ #include "voltage.h"
+
+-#define VP_IDLE_TIMEOUT 200
+-#define VP_TRANXDONE_TIMEOUT 300
++#include "vc.h"
++#include "vp.h"
++
+ #define VOLTAGE_DIR_SIZE 16
+
+-/* Voltage processor register offsets */
+-struct vp_reg_offs {
+- u8 vpconfig;
+- u8 vstepmin;
+- u8 vstepmax;
+- u8 vlimitto;
+- u8 vstatus;
+- u8 voltage;
+-};
+-
+-/* Voltage Processor bit field values, shifts and masks */
+-struct vp_reg_val {
+- /* PRM module */
+- u16 prm_mod;
+- /* VPx_VPCONFIG */
+- u32 vpconfig_erroroffset;
+- u16 vpconfig_errorgain;
+- u32 vpconfig_errorgain_mask;
+- u8 vpconfig_errorgain_shift;
+- u32 vpconfig_initvoltage_mask;
+- u8 vpconfig_initvoltage_shift;
+- u32 vpconfig_timeouten;
+- u32 vpconfig_initvdd;
+- u32 vpconfig_forceupdate;
+- u32 vpconfig_vpenable;
+- /* VPx_VSTEPMIN */
+- u8 vstepmin_stepmin;
+- u16 vstepmin_smpswaittimemin;
+- u8 vstepmin_stepmin_shift;
+- u8 vstepmin_smpswaittimemin_shift;
+- /* VPx_VSTEPMAX */
+- u8 vstepmax_stepmax;
+- u16 vstepmax_smpswaittimemax;
+- u8 vstepmax_stepmax_shift;
+- u8 vstepmax_smpswaittimemax_shift;
+- /* VPx_VLIMITTO */
+- u8 vlimitto_vddmin;
+- u8 vlimitto_vddmax;
+- u16 vlimitto_timeout;
+- u8 vlimitto_vddmin_shift;
+- u8 vlimitto_vddmax_shift;
+- u8 vlimitto_timeout_shift;
+- /* PRM_IRQSTATUS*/
+- u32 tranxdone_status;
+-};
+-
+-/* Voltage controller registers and offsets */
+-struct vc_reg_info {
+- /* PRM module */
+- u16 prm_mod;
+- /* VC register offsets */
+- u8 smps_sa_reg;
+- u8 smps_volra_reg;
+- u8 bypass_val_reg;
+- u8 cmdval_reg;
+- u8 voltsetup_reg;
+- /*VC_SMPS_SA*/
+- u8 smps_sa_shift;
+- u32 smps_sa_mask;
+- /* VC_SMPS_VOL_RA */
+- u8 smps_volra_shift;
+- u32 smps_volra_mask;
+- /* VC_BYPASS_VAL */
+- u8 data_shift;
+- u8 slaveaddr_shift;
+- u8 regaddr_shift;
+- u32 valid;
+- /* VC_CMD_VAL */
+- u8 cmd_on_shift;
+- u8 cmd_onlp_shift;
+- u8 cmd_ret_shift;
+- u8 cmd_off_shift;
+- u32 cmd_on_mask;
+- /* PRM_VOLTSETUP */
+- u8 voltsetup_shift;
+- u32 voltsetup_mask;
+-};
+
+-/**
+- * omap_vdd_info - Per Voltage Domain info
+- *
+- * @volt_data : voltage table having the distinct voltages supported
+- * by the domain and other associated per voltage data.
+- * @pmic_info : pmic specific parameters which should be populted by
+- * the pmic drivers.
+- * @vp_offs : structure containing the offsets for various
+- * vp registers
+- * @vp_reg : the register values, shifts, masks for various
+- * vp registers
+- * @vc_reg : structure containing various various vc registers,
+- * shifts, masks etc.
+- * @voltdm : pointer to the voltage domain structure
+- * @debug_dir : debug directory for this voltage domain.
+- * @curr_volt : current voltage for this vdd.
+- * @ocp_mod : The prm module for accessing the prm irqstatus reg.
+- * @prm_irqst_reg : prm irqstatus register.
+- * @vp_enabled : flag to keep track of whether vp is enabled or not
+- * @volt_scale : API to scale the voltage of the vdd.
+- */
+-struct omap_vdd_info {
+- struct omap_volt_data *volt_data;
+- struct omap_volt_pmic_info *pmic_info;
+- struct vp_reg_offs vp_offs;
+- struct vp_reg_val vp_reg;
+- struct vc_reg_info vc_reg;
+- struct voltagedomain voltdm;
+- struct dentry *debug_dir;
+- u32 curr_volt;
+- u16 ocp_mod;
+- u8 prm_irqst_reg;
+- bool vp_enabled;
+- u32 (*read_reg) (u16 mod, u8 offset);
+- void (*write_reg) (u32 val, u16 mod, u8 offset);
+- int (*volt_scale) (struct omap_vdd_info *vdd,
+- unsigned long target_volt);
+-};
+-
+-static struct omap_vdd_info *vdd_info;
++static struct omap_vdd_info **vdd_info;
++
+ /*
+ * Number of scalable voltage domains.
+ */
+ static int nr_scalable_vdd;
+
+-/* OMAP3 VDD sturctures */
+-static struct omap_vdd_info omap3_vdd_info[] = {
+- {
+- .vp_offs = {
+- .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
+- .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
+- .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
+- .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
+- .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
+- .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
+- },
+- .voltdm = {
+- .name = "mpu",
+- },
+- },
+- {
+- .vp_offs = {
+- .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
+- .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
+- .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
+- .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
+- .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
+- .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
+- },
+- .voltdm = {
+- .name = "core",
+- },
+- },
+-};
+-
+-#define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info)
+-
+-/* OMAP4 VDD sturctures */
+-static struct omap_vdd_info omap4_vdd_info[] = {
+- {
+- .vp_offs = {
+- .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+- .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+- .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
+- .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
+- .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
+- .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
+- },
+- .voltdm = {
+- .name = "mpu",
+- },
+- },
+- {
+- .vp_offs = {
+- .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+- .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+- .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
+- .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
+- .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
+- .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
+- },
+- .voltdm = {
+- .name = "iva",
+- },
+- },
+- {
+- .vp_offs = {
+- .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+- .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+- .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
+- .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
+- .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
+- .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
+- },
+- .voltdm = {
+- .name = "core",
+- },
+- },
+-};
+-
+-#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info)
+-
+-/*
+- * Structures containing OMAP3430/OMAP3630 voltage supported and various
+- * voltage dependent data for each VDD.
+- */
+-#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain) \
+-{ \
+- .volt_nominal = _v_nom, \
+- .sr_efuse_offs = _efuse_offs, \
+- .sr_errminlimit = _errminlimit, \
+- .vp_errgain = _errgain \
+-}
+-
+-/* VDD1 */
+-static struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
+-};
+-
+-static struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
+- VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
+-};
+-
+-/* VDD2 */
+-static struct omap_volt_data omap34xx_vddcore_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
+-};
+-
+-static struct omap_volt_data omap36xx_vddcore_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
+-};
+-
+-/*
+- * Structures containing OMAP4430 voltage supported and various
+- * voltage dependent data for each VDD.
+- */
+-static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
+-};
+-
+-static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
+-};
+-
+-static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+- VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
+- VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
+- VOLT_DATA_DEFINE(0, 0, 0, 0),
+-};
++/* XXX document */
++static s16 prm_mod_offs;
++static s16 prm_irqst_ocp_mod_offs;
+
+ static struct dentry *voltage_dir;
+
+ /* Init function pointers */
+-static void (*vc_init) (struct omap_vdd_info *vdd);
+-static int (*vdd_data_configure) (struct omap_vdd_info *vdd);
++static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
++ unsigned long target_volt);
+
+ static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
+ {
+@@ -336,6 +81,62 @@ static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
+ omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
+ }
+
++static int __init _config_common_vdd_data(struct omap_vdd_info *vdd)
++{
++ char *sys_ck_name;
++ struct clk *sys_ck;
++ u32 sys_clk_speed, timeout_val, waittime;
++
++ /*
++ * XXX Clockfw should handle this, or this should be in a
++ * struct record
++ */
++ if (cpu_is_omap24xx() || cpu_is_omap34xx())
++ sys_ck_name = "sys_ck";
++ else if (cpu_is_omap44xx())
++ sys_ck_name = "sys_clkin_ck";
++ else
++ return -EINVAL;
++
++ /*
++ * Sys clk rate is require to calculate vp timeout value and
++ * smpswaittimemin and smpswaittimemax.
++ */
++ sys_ck = clk_get(NULL, sys_ck_name);
++ if (IS_ERR(sys_ck)) {
++ pr_warning("%s: Could not get the sys clk to calculate"
++ "various vdd_%s params\n", __func__, vdd->voltdm.name);
++ return -EINVAL;
++ }
++ sys_clk_speed = clk_get_rate(sys_ck);
++ clk_put(sys_ck);
++ /* Divide to avoid overflow */
++ sys_clk_speed /= 1000;
++
++ /* Generic voltage parameters */
++ vdd->curr_volt = 1200000;
++ vdd->volt_scale = vp_forceupdate_scale_voltage;
++ vdd->vp_enabled = false;
++
++ vdd->vp_rt_data.vpconfig_erroroffset =
++ (vdd->pmic_info->vp_erroroffset <<
++ vdd->vp_data->vp_common->vpconfig_erroroffset_shift);
++
++ timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
++ vdd->vp_rt_data.vlimitto_timeout = timeout_val;
++ vdd->vp_rt_data.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
++ vdd->vp_rt_data.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
++
++ waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
++ sys_clk_speed) / 1000;
++ vdd->vp_rt_data.vstepmin_smpswaittimemin = waittime;
++ vdd->vp_rt_data.vstepmax_smpswaittimemax = waittime;
++ vdd->vp_rt_data.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
++ vdd->vp_rt_data.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
++
++ return 0;
++}
++
+ /* Voltage debugfs support */
+ static int vp_volt_debug_get(void *data, u64 *val)
+ {
+@@ -347,7 +148,7 @@ static int vp_volt_debug_get(void *data, u64 *val)
+ return -EINVAL;
+ }
+
+- vsel = vdd->read_reg(vdd->vp_reg.prm_mod, vdd->vp_offs.voltage);
++ vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
+ pr_notice("curr_vsel = %x\n", vsel);
+
+ if (!vdd->pmic_info->vsel_to_uv) {
+@@ -380,7 +181,6 @@ DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
+ static void vp_latch_vsel(struct omap_vdd_info *vdd)
+ {
+ u32 vpconfig;
+- u16 mod;
+ unsigned long uvdc;
+ char vsel;
+
+@@ -397,30 +197,27 @@ static void vp_latch_vsel(struct omap_vdd_info *vdd)
+ return;
+ }
+
+- mod = vdd->vp_reg.prm_mod;
+-
+ vsel = vdd->pmic_info->uv_to_vsel(uvdc);
+
+- vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+- vpconfig &= ~(vdd->vp_reg.vpconfig_initvoltage_mask |
+- vdd->vp_reg.vpconfig_initvdd);
+- vpconfig |= vsel << vdd->vp_reg.vpconfig_initvoltage_shift;
++ vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvoltage_mask |
++ vdd->vp_data->vp_common->vpconfig_initvdd);
++ vpconfig |= vsel << vdd->vp_data->vp_common->vpconfig_initvoltage_shift;
+
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+- vdd->write_reg((vpconfig | vdd->vp_reg.vpconfig_initvdd), mod,
+- vdd->vp_offs.vpconfig);
++ vdd->write_reg((vpconfig | vdd->vp_data->vp_common->vpconfig_initvdd),
++ prm_mod_offs, vdd->vp_data->vpconfig);
+
+ /* Clear initVDD copy trigger bit */
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+ }
+
+ /* Generic voltage init functions */
+ static void __init vp_init(struct omap_vdd_info *vdd)
+ {
+ u32 vp_val;
+- u16 mod;
+
+ if (!vdd->read_reg || !vdd->write_reg) {
+ pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+@@ -428,33 +225,31 @@ static void __init vp_init(struct omap_vdd_info *vdd)
+ return;
+ }
+
+- mod = vdd->vp_reg.prm_mod;
+-
+- vp_val = vdd->vp_reg.vpconfig_erroroffset |
+- (vdd->vp_reg.vpconfig_errorgain <<
+- vdd->vp_reg.vpconfig_errorgain_shift) |
+- vdd->vp_reg.vpconfig_timeouten;
+- vdd->write_reg(vp_val, mod, vdd->vp_offs.vpconfig);
+-
+- vp_val = ((vdd->vp_reg.vstepmin_smpswaittimemin <<
+- vdd->vp_reg.vstepmin_smpswaittimemin_shift) |
+- (vdd->vp_reg.vstepmin_stepmin <<
+- vdd->vp_reg.vstepmin_stepmin_shift));
+- vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmin);
+-
+- vp_val = ((vdd->vp_reg.vstepmax_smpswaittimemax <<
+- vdd->vp_reg.vstepmax_smpswaittimemax_shift) |
+- (vdd->vp_reg.vstepmax_stepmax <<
+- vdd->vp_reg.vstepmax_stepmax_shift));
+- vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmax);
+-
+- vp_val = ((vdd->vp_reg.vlimitto_vddmax <<
+- vdd->vp_reg.vlimitto_vddmax_shift) |
+- (vdd->vp_reg.vlimitto_vddmin <<
+- vdd->vp_reg.vlimitto_vddmin_shift) |
+- (vdd->vp_reg.vlimitto_timeout <<
+- vdd->vp_reg.vlimitto_timeout_shift));
+- vdd->write_reg(vp_val, mod, vdd->vp_offs.vlimitto);
++ vp_val = vdd->vp_rt_data.vpconfig_erroroffset |
++ (vdd->vp_rt_data.vpconfig_errorgain <<
++ vdd->vp_data->vp_common->vpconfig_errorgain_shift) |
++ vdd->vp_data->vp_common->vpconfig_timeouten;
++ vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vpconfig);
++
++ vp_val = ((vdd->vp_rt_data.vstepmin_smpswaittimemin <<
++ vdd->vp_data->vp_common->vstepmin_smpswaittimemin_shift) |
++ (vdd->vp_rt_data.vstepmin_stepmin <<
++ vdd->vp_data->vp_common->vstepmin_stepmin_shift));
++ vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmin);
++
++ vp_val = ((vdd->vp_rt_data.vstepmax_smpswaittimemax <<
++ vdd->vp_data->vp_common->vstepmax_smpswaittimemax_shift) |
++ (vdd->vp_rt_data.vstepmax_stepmax <<
++ vdd->vp_data->vp_common->vstepmax_stepmax_shift));
++ vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vstepmax);
++
++ vp_val = ((vdd->vp_rt_data.vlimitto_vddmax <<
++ vdd->vp_data->vp_common->vlimitto_vddmax_shift) |
++ (vdd->vp_rt_data.vlimitto_vddmin <<
++ vdd->vp_data->vp_common->vlimitto_vddmin_shift) |
++ (vdd->vp_rt_data.vlimitto_timeout <<
++ vdd->vp_data->vp_common->vlimitto_timeout_shift));
++ vdd->write_reg(vp_val, prm_mod_offs, vdd->vp_data->vlimitto);
+ }
+
+ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
+@@ -481,23 +276,23 @@ static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
+ }
+
+ (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_reg.vpconfig_errorgain));
++ &(vdd->vp_rt_data.vpconfig_errorgain));
+ (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO,
+ vdd->debug_dir,
+- &(vdd->vp_reg.vstepmin_smpswaittimemin));
++ &(vdd->vp_rt_data.vstepmin_smpswaittimemin));
+ (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_reg.vstepmin_stepmin));
++ &(vdd->vp_rt_data.vstepmin_stepmin));
+ (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO,
+ vdd->debug_dir,
+- &(vdd->vp_reg.vstepmax_smpswaittimemax));
++ &(vdd->vp_rt_data.vstepmax_smpswaittimemax));
+ (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_reg.vstepmax_stepmax));
++ &(vdd->vp_rt_data.vstepmax_stepmax));
+ (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_reg.vlimitto_vddmax));
++ &(vdd->vp_rt_data.vlimitto_vddmax));
+ (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_reg.vlimitto_vddmin));
++ &(vdd->vp_rt_data.vlimitto_vddmin));
+ (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir,
+- &(vdd->vp_reg.vlimitto_timeout));
++ &(vdd->vp_rt_data.vlimitto_timeout));
+ (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir,
+ (void *) vdd, &vp_volt_debug_fops);
+ (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
+@@ -510,8 +305,12 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
+ unsigned long target_volt, u8 *target_vsel, u8 *current_vsel)
+ {
+ struct omap_volt_data *volt_data;
++ const struct omap_vc_common_data *vc_common;
++ const struct omap_vp_common_data *vp_common;
+ u32 vc_cmdval, vp_errgain_val;
+- u16 vp_mod, vc_mod;
++
++ vc_common = vdd->vc_data->vc_common;
++ vp_common = vdd->vp_data->vp_common;
+
+ /* Check if suffiecient pmic info is available for this vdd */
+ if (!vdd->pmic_info) {
+@@ -533,33 +332,30 @@ static int _pre_volt_scale(struct omap_vdd_info *vdd,
+ return -EINVAL;
+ }
+
+- vp_mod = vdd->vp_reg.prm_mod;
+- vc_mod = vdd->vc_reg.prm_mod;
+-
+ /* Get volt_data corresponding to target_volt */
+ volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt);
+ if (IS_ERR(volt_data))
+ volt_data = NULL;
+
+ *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
+- *current_vsel = vdd->read_reg(vp_mod, vdd->vp_offs.voltage);
++ *current_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
+
+ /* Setting the ON voltage to the new target voltage */
+- vc_cmdval = vdd->read_reg(vc_mod, vdd->vc_reg.cmdval_reg);
+- vc_cmdval &= ~vdd->vc_reg.cmd_on_mask;
+- vc_cmdval |= (*target_vsel << vdd->vc_reg.cmd_on_shift);
+- vdd->write_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg);
++ vc_cmdval = vdd->read_reg(prm_mod_offs, vdd->vc_data->cmdval_reg);
++ vc_cmdval &= ~vc_common->cmd_on_mask;
++ vc_cmdval |= (*target_vsel << vc_common->cmd_on_shift);
++ vdd->write_reg(vc_cmdval, prm_mod_offs, vdd->vc_data->cmdval_reg);
+
+ /* Setting vp errorgain based on the voltage */
+ if (volt_data) {
+- vp_errgain_val = vdd->read_reg(vp_mod,
+- vdd->vp_offs.vpconfig);
+- vdd->vp_reg.vpconfig_errorgain = volt_data->vp_errgain;
+- vp_errgain_val &= ~vdd->vp_reg.vpconfig_errorgain_mask;
+- vp_errgain_val |= vdd->vp_reg.vpconfig_errorgain <<
+- vdd->vp_reg.vpconfig_errorgain_shift;
+- vdd->write_reg(vp_errgain_val, vp_mod,
+- vdd->vp_offs.vpconfig);
++ vp_errgain_val = vdd->read_reg(prm_mod_offs,
++ vdd->vp_data->vpconfig);
++ vdd->vp_rt_data.vpconfig_errorgain = volt_data->vp_errgain;
++ vp_errgain_val &= ~vp_common->vpconfig_errorgain_mask;
++ vp_errgain_val |= vdd->vp_rt_data.vpconfig_errorgain <<
++ vp_common->vpconfig_errorgain_shift;
++ vdd->write_reg(vp_errgain_val, prm_mod_offs,
++ vdd->vp_data->vpconfig);
+ }
+
+ return 0;
+@@ -585,7 +381,6 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+ {
+ u32 loop_cnt = 0, retries_cnt = 0;
+ u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+- u16 mod;
+ u8 target_vsel, current_vsel;
+ int ret;
+
+@@ -593,20 +388,19 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+ if (ret)
+ return ret;
+
+- mod = vdd->vc_reg.prm_mod;
+-
+- vc_valid = vdd->vc_reg.valid;
+- vc_bypass_val_reg = vdd->vc_reg.bypass_val_reg;
+- vc_bypass_value = (target_vsel << vdd->vc_reg.data_shift) |
++ vc_valid = vdd->vc_data->vc_common->valid;
++ vc_bypass_val_reg = vdd->vc_data->vc_common->bypass_val_reg;
++ vc_bypass_value = (target_vsel << vdd->vc_data->vc_common->data_shift) |
+ (vdd->pmic_info->pmic_reg <<
+- vdd->vc_reg.regaddr_shift) |
++ vdd->vc_data->vc_common->regaddr_shift) |
+ (vdd->pmic_info->i2c_slave_addr <<
+- vdd->vc_reg.slaveaddr_shift);
++ vdd->vc_data->vc_common->slaveaddr_shift);
+
+- vdd->write_reg(vc_bypass_value, mod, vc_bypass_val_reg);
+- vdd->write_reg(vc_bypass_value | vc_valid, mod, vc_bypass_val_reg);
++ vdd->write_reg(vc_bypass_value, prm_mod_offs, vc_bypass_val_reg);
++ vdd->write_reg(vc_bypass_value | vc_valid, prm_mod_offs,
++ vc_bypass_val_reg);
+
+- vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg);
++ vc_bypass_value = vdd->read_reg(prm_mod_offs, vc_bypass_val_reg);
+ /*
+ * Loop till the bypass command is acknowledged from the SMPS.
+ * NOTE: This is legacy code. The loop count and retry count needs
+@@ -625,7 +419,8 @@ static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+ loop_cnt = 0;
+ udelay(10);
+ }
+- vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg);
++ vc_bypass_value = vdd->read_reg(prm_mod_offs,
++ vc_bypass_val_reg);
+ }
+
+ _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
+@@ -637,7 +432,6 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ unsigned long target_volt)
+ {
+ u32 vpconfig;
+- u16 mod, ocp_mod;
+ u8 target_vsel, current_vsel, prm_irqst_reg;
+ int ret, timeout = 0;
+
+@@ -645,20 +439,18 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ if (ret)
+ return ret;
+
+- mod = vdd->vp_reg.prm_mod;
+- ocp_mod = vdd->ocp_mod;
+- prm_irqst_reg = vdd->prm_irqst_reg;
++ prm_irqst_reg = vdd->vp_data->prm_irqst_data->prm_irqst_reg;
+
+ /*
+ * Clear all pending TransactionDone interrupt/status. Typical latency
+ * is <3us
+ */
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+- vdd->write_reg(vdd->vp_reg.tranxdone_status,
+- ocp_mod, prm_irqst_reg);
+- if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) &
+- vdd->vp_reg.tranxdone_status))
+- break;
++ vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
++ prm_irqst_ocp_mod_offs, prm_irqst_reg);
++ if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
++ vdd->vp_data->prm_irqst_data->tranxdone_status))
++ break;
+ udelay(1);
+ }
+ if (timeout >= VP_TRANXDONE_TIMEOUT) {
+@@ -668,30 +460,30 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ }
+
+ /* Configure for VP-Force Update */
+- vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+- vpconfig &= ~(vdd->vp_reg.vpconfig_initvdd |
+- vdd->vp_reg.vpconfig_forceupdate |
+- vdd->vp_reg.vpconfig_initvoltage_mask);
++ vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig &= ~(vdd->vp_data->vp_common->vpconfig_initvdd |
++ vdd->vp_data->vp_common->vpconfig_forceupdate |
++ vdd->vp_data->vp_common->vpconfig_initvoltage_mask);
+ vpconfig |= ((target_vsel <<
+- vdd->vp_reg.vpconfig_initvoltage_shift));
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vdd->vp_data->vp_common->vpconfig_initvoltage_shift));
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+ /* Trigger initVDD value copy to voltage processor */
+- vpconfig |= vdd->vp_reg.vpconfig_initvdd;
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vpconfig |= vdd->vp_data->vp_common->vpconfig_initvdd;
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+ /* Force update of voltage */
+- vpconfig |= vdd->vp_reg.vpconfig_forceupdate;
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vpconfig |= vdd->vp_data->vp_common->vpconfig_forceupdate;
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+ /*
+ * Wait for TransactionDone. Typical latency is <200us.
+ * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+ */
+ timeout = 0;
+- omap_test_timeout((vdd->read_reg(ocp_mod, prm_irqst_reg) &
+- vdd->vp_reg.tranxdone_status),
+- VP_TRANXDONE_TIMEOUT, timeout);
++ omap_test_timeout((vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
++ vdd->vp_data->prm_irqst_data->tranxdone_status),
++ VP_TRANXDONE_TIMEOUT, timeout);
+ if (timeout >= VP_TRANXDONE_TIMEOUT)
+ pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+ "TRANXDONE never got set after the voltage update\n",
+@@ -705,11 +497,11 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ */
+ timeout = 0;
+ while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+- vdd->write_reg(vdd->vp_reg.tranxdone_status,
+- ocp_mod, prm_irqst_reg);
+- if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) &
+- vdd->vp_reg.tranxdone_status))
+- break;
++ vdd->write_reg(vdd->vp_data->prm_irqst_data->tranxdone_status,
++ prm_irqst_ocp_mod_offs, prm_irqst_reg);
++ if (!(vdd->read_reg(prm_irqst_ocp_mod_offs, prm_irqst_reg) &
++ vdd->vp_data->prm_irqst_data->tranxdone_status))
++ break;
+ udelay(1);
+ }
+
+@@ -718,222 +510,95 @@ static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+ "to clear the TRANXDONE status\n",
+ __func__, vdd->voltdm.name);
+
+- vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
++ vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
+ /* Clear initVDD copy trigger bit */
+- vpconfig &= ~vdd->vp_reg.vpconfig_initvdd;;
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vpconfig &= ~vdd->vp_data->vp_common->vpconfig_initvdd;
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+ /* Clear force bit */
+- vpconfig &= ~vdd->vp_reg.vpconfig_forceupdate;
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vpconfig &= ~vdd->vp_data->vp_common->vpconfig_forceupdate;
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+ return 0;
+ }
+
+-/* OMAP3 specific voltage init functions */
++static void __init omap3_vfsm_init(struct omap_vdd_info *vdd)
++{
++ /*
++ * Voltage Manager FSM parameters init
++ * XXX This data should be passed in from the board file
++ */
++ vdd->write_reg(OMAP3_CLKSETUP, prm_mod_offs, OMAP3_PRM_CLKSETUP_OFFSET);
++ vdd->write_reg(OMAP3_VOLTOFFSET, prm_mod_offs,
++ OMAP3_PRM_VOLTOFFSET_OFFSET);
++ vdd->write_reg(OMAP3_VOLTSETUP2, prm_mod_offs,
++ OMAP3_PRM_VOLTSETUP2_OFFSET);
++}
+
+-/*
+- * Intializes the voltage controller registers with the PMIC and board
+- * specific parameters and voltage setup times for OMAP3.
+- */
+ static void __init omap3_vc_init(struct omap_vdd_info *vdd)
+ {
+- u32 vc_val;
+- u16 mod;
+- u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+ static bool is_initialized;
++ u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
++ u32 vc_val;
+
+- if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+- pr_err("%s: PMIC info requried to configure vc for"
+- "vdd_%s not populated.Hence cannot initialize vc\n",
+- __func__, vdd->voltdm.name);
+- return;
+- }
+-
+- if (!vdd->read_reg || !vdd->write_reg) {
+- pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+- __func__, vdd->voltdm.name);
++ if (is_initialized)
+ return;
+- }
+-
+- mod = vdd->vc_reg.prm_mod;
+-
+- /* Set up the SMPS_SA(i2c slave address in VC */
+- vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
+- vc_val &= ~vdd->vc_reg.smps_sa_mask;
+- vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
+- vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
+-
+- /* Setup the VOLRA(pmic reg addr) in VC */
+- vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
+- vc_val &= ~vdd->vc_reg.smps_volra_mask;
+- vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
+- vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
+-
+- /*Configure the setup times */
+- vc_val = vdd->read_reg(mod, vdd->vc_reg.voltsetup_reg);
+- vc_val &= ~vdd->vc_reg.voltsetup_mask;
+- vc_val |= vdd->pmic_info->volt_setup_time <<
+- vdd->vc_reg.voltsetup_shift;
+- vdd->write_reg(vc_val, mod, vdd->vc_reg.voltsetup_reg);
+
+ /* Set up the on, inactive, retention and off voltage */
+ on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
+ onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
+ ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
+ off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
+- vc_val = ((on_vsel << vdd->vc_reg.cmd_on_shift) |
+- (onlp_vsel << vdd->vc_reg.cmd_onlp_shift) |
+- (ret_vsel << vdd->vc_reg.cmd_ret_shift) |
+- (off_vsel << vdd->vc_reg.cmd_off_shift));
+- vdd->write_reg(vc_val, mod, vdd->vc_reg.cmdval_reg);
+-
+- if (is_initialized)
+- return;
++ vc_val = ((on_vsel << vdd->vc_data->vc_common->cmd_on_shift) |
++ (onlp_vsel << vdd->vc_data->vc_common->cmd_onlp_shift) |
++ (ret_vsel << vdd->vc_data->vc_common->cmd_ret_shift) |
++ (off_vsel << vdd->vc_data->vc_common->cmd_off_shift));
++ vdd->write_reg(vc_val, prm_mod_offs, vdd->vc_data->cmdval_reg);
+
+- /* Generic VC parameters init */
+- vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, mod,
++ /*
++ * Generic VC parameters init
++ * XXX This data should be abstracted out
++ */
++ vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, prm_mod_offs,
+ OMAP3_PRM_VC_CH_CONF_OFFSET);
+- vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, mod,
++ vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, prm_mod_offs,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+- vdd->write_reg(OMAP3_CLKSETUP, mod, OMAP3_PRM_CLKSETUP_OFFSET);
+- vdd->write_reg(OMAP3_VOLTOFFSET, mod, OMAP3_PRM_VOLTOFFSET_OFFSET);
+- vdd->write_reg(OMAP3_VOLTSETUP2, mod, OMAP3_PRM_VOLTSETUP2_OFFSET);
++
++ omap3_vfsm_init(vdd);
++
+ is_initialized = true;
+ }
+
+-/* Sets up all the VDD related info for OMAP3 */
+-static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd)
++
++/* OMAP4 specific voltage init functions */
++static void __init omap4_vc_init(struct omap_vdd_info *vdd)
+ {
+- struct clk *sys_ck;
+- u32 sys_clk_speed, timeout_val, waittime;
++ static bool is_initialized;
++ u32 vc_val;
+
+- if (!vdd->pmic_info) {
+- pr_err("%s: PMIC info requried to configure vdd_%s not"
+- "populated.Hence cannot initialize vdd_%s\n",
+- __func__, vdd->voltdm.name, vdd->voltdm.name);
+- return -EINVAL;
+- }
++ if (is_initialized)
++ return;
+
+- if (!strcmp(vdd->voltdm.name, "mpu")) {
+- if (cpu_is_omap3630())
+- vdd->volt_data = omap36xx_vddmpu_volt_data;
+- else
+- vdd->volt_data = omap34xx_vddmpu_volt_data;
+-
+- vdd->vp_reg.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK;
+- vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET;
+- vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT;
+- vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK;
+- vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA0_SHIFT;
+- vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA0_MASK;
+- vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT;
+- vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK;
+- } else if (!strcmp(vdd->voltdm.name, "core")) {
+- if (cpu_is_omap3630())
+- vdd->volt_data = omap36xx_vddcore_volt_data;
+- else
+- vdd->volt_data = omap34xx_vddcore_volt_data;
+-
+- vdd->vp_reg.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK;
+- vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET;
+- vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT;
+- vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK;
+- vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA1_SHIFT;
+- vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA1_MASK;
+- vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT;
+- vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME2_MASK;
+- } else {
+- pr_warning("%s: vdd_%s does not exisit in OMAP3\n",
+- __func__, vdd->voltdm.name);
+- return -EINVAL;
+- }
++ /* TODO: Configure setup times and CMD_VAL values*/
+
+ /*
+- * Sys clk rate is require to calculate vp timeout value and
+- * smpswaittimemin and smpswaittimemax.
++ * Generic VC parameters init
++ * XXX This data should be abstracted out
+ */
+- sys_ck = clk_get(NULL, "sys_ck");
+- if (IS_ERR(sys_ck)) {
+- pr_warning("%s: Could not get the sys clk to calculate"
+- "various vdd_%s params\n", __func__, vdd->voltdm.name);
+- return -EINVAL;
+- }
+- sys_clk_speed = clk_get_rate(sys_ck);
+- clk_put(sys_ck);
+- /* Divide to avoid overflow */
+- sys_clk_speed /= 1000;
+-
+- /* Generic voltage parameters */
+- vdd->curr_volt = 1200000;
+- vdd->ocp_mod = OCP_MOD;
+- vdd->prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET;
+- vdd->read_reg = omap3_voltage_read_reg;
+- vdd->write_reg = omap3_voltage_write_reg;
+- vdd->volt_scale = vp_forceupdate_scale_voltage;
+- vdd->vp_enabled = false;
++ vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
++ OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
++ OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
++ vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+
+- /* VC parameters */
+- vdd->vc_reg.prm_mod = OMAP3430_GR_MOD;
+- vdd->vc_reg.smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET;
+- vdd->vc_reg.smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET;
+- vdd->vc_reg.bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET;
+- vdd->vc_reg.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET;
+- vdd->vc_reg.data_shift = OMAP3430_DATA_SHIFT;
+- vdd->vc_reg.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT;
+- vdd->vc_reg.regaddr_shift = OMAP3430_REGADDR_SHIFT;
+- vdd->vc_reg.valid = OMAP3430_VALID_MASK;
+- vdd->vc_reg.cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT;
+- vdd->vc_reg.cmd_on_mask = OMAP3430_VC_CMD_ON_MASK;
+- vdd->vc_reg.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT;
+- vdd->vc_reg.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT;
+- vdd->vc_reg.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT;
+-
+- vdd->vp_reg.prm_mod = OMAP3430_GR_MOD;
+-
+- /* VPCONFIG bit fields */
+- vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
+- OMAP3430_ERROROFFSET_SHIFT);
+- vdd->vp_reg.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK;
+- vdd->vp_reg.vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT;
+- vdd->vp_reg.vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT;
+- vdd->vp_reg.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK;
+- vdd->vp_reg.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK;
+- vdd->vp_reg.vpconfig_initvdd = OMAP3430_INITVDD_MASK;
+- vdd->vp_reg.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK;
+- vdd->vp_reg.vpconfig_vpenable = OMAP3430_VPENABLE_MASK;
+-
+- /* VSTEPMIN VSTEPMAX bit fields */
+- waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
+- sys_clk_speed) / 1000;
+- vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
+- vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
+- vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
+- vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
+- vdd->vp_reg.vstepmin_smpswaittimemin_shift =
+- OMAP3430_SMPSWAITTIMEMIN_SHIFT;
+- vdd->vp_reg.vstepmax_smpswaittimemax_shift =
+- OMAP3430_SMPSWAITTIMEMAX_SHIFT;
+- vdd->vp_reg.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT;
+- vdd->vp_reg.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT;
+-
+- /* VLIMITTO bit fields */
+- timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
+- vdd->vp_reg.vlimitto_timeout = timeout_val;
+- vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
+- vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
+- vdd->vp_reg.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT;
+- vdd->vp_reg.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT;
+- vdd->vp_reg.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT;
++ /* XXX These are magic numbers and do not belong! */
++ vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
++ vdd->write_reg(vc_val, prm_mod_offs, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+
+- return 0;
++ is_initialized = true;
+ }
+
+-/* OMAP4 specific voltage init functions */
+-static void __init omap4_vc_init(struct omap_vdd_info *vdd)
++static void __init omap_vc_init(struct omap_vdd_info *vdd)
+ {
+ u32 vc_val;
+- u16 mod;
+- static bool is_initialized;
+
+ if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+ pr_err("%s: PMIC info requried to configure vc for"
+@@ -948,173 +613,61 @@ static void __init omap4_vc_init(struct omap_vdd_info *vdd)
+ return;
+ }
+
+- mod = vdd->vc_reg.prm_mod;
+-
+ /* Set up the SMPS_SA(i2c slave address in VC */
+- vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
+- vc_val &= ~vdd->vc_reg.smps_sa_mask;
+- vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
+- vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
++ vc_val = vdd->read_reg(prm_mod_offs,
++ vdd->vc_data->vc_common->smps_sa_reg);
++ vc_val &= ~vdd->vc_data->smps_sa_mask;
++ vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_data->smps_sa_shift;
++ vdd->write_reg(vc_val, prm_mod_offs,
++ vdd->vc_data->vc_common->smps_sa_reg);
+
+ /* Setup the VOLRA(pmic reg addr) in VC */
+- vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
+- vc_val &= ~vdd->vc_reg.smps_volra_mask;
+- vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
+- vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
+-
+- /* TODO: Configure setup times and CMD_VAL values*/
+-
+- if (is_initialized)
+- return;
+-
+- /* Generic VC parameters init */
+- vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+- OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+- OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+- vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+-
+- vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+- vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
++ vc_val = vdd->read_reg(prm_mod_offs,
++ vdd->vc_data->vc_common->smps_volra_reg);
++ vc_val &= ~vdd->vc_data->smps_volra_mask;
++ vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_data->smps_volra_shift;
++ vdd->write_reg(vc_val, prm_mod_offs,
++ vdd->vc_data->vc_common->smps_volra_reg);
++
++ /* Configure the setup times */
++ vc_val = vdd->read_reg(prm_mod_offs, vdd->vfsm->voltsetup_reg);
++ vc_val &= ~vdd->vfsm->voltsetup_mask;
++ vc_val |= vdd->pmic_info->volt_setup_time <<
++ vdd->vfsm->voltsetup_shift;
++ vdd->write_reg(vc_val, prm_mod_offs, vdd->vfsm->voltsetup_reg);
+
+- is_initialized = true;
++ if (cpu_is_omap34xx())
++ omap3_vc_init(vdd);
++ else if (cpu_is_omap44xx())
++ omap4_vc_init(vdd);
+ }
+
+-/* Sets up all the VDD related info for OMAP4 */
+-static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
++static int __init omap_vdd_data_configure(struct omap_vdd_info *vdd)
+ {
+- struct clk *sys_ck;
+- u32 sys_clk_speed, timeout_val, waittime;
++ int ret = -EINVAL;
+
+ if (!vdd->pmic_info) {
+ pr_err("%s: PMIC info requried to configure vdd_%s not"
+ "populated.Hence cannot initialize vdd_%s\n",
+ __func__, vdd->voltdm.name, vdd->voltdm.name);
+- return -EINVAL;
++ goto ovdc_out;
+ }
+
+- if (!strcmp(vdd->voltdm.name, "mpu")) {
+- vdd->volt_data = omap44xx_vdd_mpu_volt_data;
+- vdd->vp_reg.tranxdone_status =
+- OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
+- vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
+- vdd->vc_reg.smps_sa_shift =
+- OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT;
+- vdd->vc_reg.smps_sa_mask =
+- OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK;
+- vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT;
+- vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK;
+- vdd->vc_reg.voltsetup_reg =
+- OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET;
+- vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
+- } else if (!strcmp(vdd->voltdm.name, "core")) {
+- vdd->volt_data = omap44xx_vdd_core_volt_data;
+- vdd->vp_reg.tranxdone_status =
+- OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
+- vdd->vc_reg.cmdval_reg =
+- OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
+- vdd->vc_reg.smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT;
+- vdd->vc_reg.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK;
+- vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT;
+- vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK;
+- vdd->vc_reg.voltsetup_reg =
+- OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET;
+- vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
+- } else if (!strcmp(vdd->voltdm.name, "iva")) {
+- vdd->volt_data = omap44xx_vdd_iva_volt_data;
+- vdd->vp_reg.tranxdone_status =
+- OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
+- vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
+- vdd->vc_reg.smps_sa_shift =
+- OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT;
+- vdd->vc_reg.smps_sa_mask =
+- OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK;
+- vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT;
+- vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK;
+- vdd->vc_reg.voltsetup_reg =
+- OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET;
+- vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
+- } else {
+- pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
+- __func__, vdd->voltdm.name);
+- return -EINVAL;
+- }
++ if (IS_ERR_VALUE(_config_common_vdd_data(vdd)))
++ goto ovdc_out;
+
+- /*
+- * Sys clk rate is require to calculate vp timeout value and
+- * smpswaittimemin and smpswaittimemax.
+- */
+- sys_ck = clk_get(NULL, "sys_clkin_ck");
+- if (IS_ERR(sys_ck)) {
+- pr_warning("%s: Could not get the sys clk to calculate"
+- "various vdd_%s params\n", __func__, vdd->voltdm.name);
+- return -EINVAL;
++ if (cpu_is_omap34xx()) {
++ vdd->read_reg = omap3_voltage_read_reg;
++ vdd->write_reg = omap3_voltage_write_reg;
++ ret = 0;
++ } else if (cpu_is_omap44xx()) {
++ vdd->read_reg = omap4_voltage_read_reg;
++ vdd->write_reg = omap4_voltage_write_reg;
++ ret = 0;
+ }
+- sys_clk_speed = clk_get_rate(sys_ck);
+- clk_put(sys_ck);
+- /* Divide to avoid overflow */
+- sys_clk_speed /= 1000;
+-
+- /* Generic voltage parameters */
+- vdd->curr_volt = 1200000;
+- vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
+- vdd->read_reg = omap4_voltage_read_reg;
+- vdd->write_reg = omap4_voltage_write_reg;
+- vdd->volt_scale = vp_forceupdate_scale_voltage;
+- vdd->vp_enabled = false;
+
+- /* VC parameters */
+- vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
+- vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET;
+- vdd->vc_reg.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET;
+- vdd->vc_reg.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET;
+- vdd->vc_reg.data_shift = OMAP4430_DATA_SHIFT;
+- vdd->vc_reg.slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT;
+- vdd->vc_reg.regaddr_shift = OMAP4430_REGADDR_SHIFT;
+- vdd->vc_reg.valid = OMAP4430_VALID_MASK;
+- vdd->vc_reg.cmd_on_shift = OMAP4430_ON_SHIFT;
+- vdd->vc_reg.cmd_on_mask = OMAP4430_ON_MASK;
+- vdd->vc_reg.cmd_onlp_shift = OMAP4430_ONLP_SHIFT;
+- vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT;
+- vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT;
+-
+- vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
+-
+- /* VPCONFIG bit fields */
+- vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
+- OMAP4430_ERROROFFSET_SHIFT);
+- vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK;
+- vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT;
+- vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT;
+- vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK;
+- vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK;
+- vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK;
+- vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK;
+- vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK;
+-
+- /* VSTEPMIN VSTEPMAX bit fields */
+- waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
+- sys_clk_speed) / 1000;
+- vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
+- vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
+- vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
+- vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
+- vdd->vp_reg.vstepmin_smpswaittimemin_shift =
+- OMAP4430_SMPSWAITTIMEMIN_SHIFT;
+- vdd->vp_reg.vstepmax_smpswaittimemax_shift =
+- OMAP4430_SMPSWAITTIMEMAX_SHIFT;
+- vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT;
+- vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT;
+-
+- /* VLIMITTO bit fields */
+- timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
+- vdd->vp_reg.vlimitto_timeout = timeout_val;
+- vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
+- vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
+- vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT;
+- vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT;
+- vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT;
+-
+- return 0;
++ovdc_out:
++ return ret;
+ }
+
+ /* Public functions */
+@@ -1162,8 +715,7 @@ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+ return 0;
+ }
+
+- curr_vsel = vdd->read_reg(vdd->vp_reg.prm_mod,
+- vdd->vp_offs.voltage);
++ curr_vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
+
+ if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
+ pr_warning("%s: PMIC function to convert vsel to voltage"
+@@ -1185,7 +737,6 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ {
+ struct omap_vdd_info *vdd;
+ u32 vpconfig;
+- u16 mod;
+
+ if (!voltdm || IS_ERR(voltdm)) {
+ pr_warning("%s: VDD specified does not exist!\n", __func__);
+@@ -1199,8 +750,6 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ return;
+ }
+
+- mod = vdd->vp_reg.prm_mod;
+-
+ /* If VP is already enabled, do nothing. Return */
+ if (vdd->vp_enabled)
+ return;
+@@ -1208,9 +757,9 @@ void omap_vp_enable(struct voltagedomain *voltdm)
+ vp_latch_vsel(vdd);
+
+ /* Enable VP */
+- vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+- vpconfig |= vdd->vp_reg.vpconfig_vpenable;
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig |= vdd->vp_data->vp_common->vpconfig_vpenable;
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+ vdd->vp_enabled = true;
+ }
+
+@@ -1225,7 +774,6 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ {
+ struct omap_vdd_info *vdd;
+ u32 vpconfig;
+- u16 mod;
+ int timeout;
+
+ if (!voltdm || IS_ERR(voltdm)) {
+@@ -1240,8 +788,6 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ return;
+ }
+
+- mod = vdd->vp_reg.prm_mod;
+-
+ /* If VP is already disabled, do nothing. Return */
+ if (!vdd->vp_enabled) {
+ pr_warning("%s: Trying to disable VP for vdd_%s when"
+@@ -1250,14 +796,14 @@ void omap_vp_disable(struct voltagedomain *voltdm)
+ }
+
+ /* Disable VP */
+- vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+- vpconfig &= ~vdd->vp_reg.vpconfig_vpenable;
+- vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
++ vpconfig = vdd->read_reg(prm_mod_offs, vdd->vp_data->vpconfig);
++ vpconfig &= ~vdd->vp_data->vp_common->vpconfig_vpenable;
++ vdd->write_reg(vpconfig, prm_mod_offs, vdd->vp_data->vpconfig);
+
+ /*
+ * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
+ */
+- omap_test_timeout((vdd->read_reg(mod, vdd->vp_offs.vstatus)),
++ omap_test_timeout((vdd->read_reg(prm_mod_offs, vdd->vp_data->vstatus)),
+ VP_IDLE_TIMEOUT, timeout);
+
+ if (timeout >= VP_IDLE_TIMEOUT)
+@@ -1510,8 +1056,8 @@ struct voltagedomain *omap_voltage_domain_lookup(char *name)
+ }
+
+ for (i = 0; i < nr_scalable_vdd; i++) {
+- if (!(strcmp(name, vdd_info[i].voltdm.name)))
+- return &vdd_info[i].voltdm;
++ if (!(strcmp(name, vdd_info[i]->voltdm.name)))
++ return &vdd_info[i]->voltdm;
+ }
+
+ return ERR_PTR(-EINVAL);
+@@ -1539,35 +1085,24 @@ int __init omap_voltage_late_init(void)
+ pr_err("%s: Unable to create voltage debugfs main dir\n",
+ __func__);
+ for (i = 0; i < nr_scalable_vdd; i++) {
+- if (vdd_data_configure(&vdd_info[i]))
++ if (omap_vdd_data_configure(vdd_info[i]))
+ continue;
+- vc_init(&vdd_info[i]);
+- vp_init(&vdd_info[i]);
+- vdd_debugfs_init(&vdd_info[i]);
++ omap_vc_init(vdd_info[i]);
++ vp_init(vdd_info[i]);
++ vdd_debugfs_init(vdd_info[i]);
+ }
+
+ return 0;
+ }
+
+-/**
+- * omap_voltage_early_init()- Volatage driver early init
+- */
+-static int __init omap_voltage_early_init(void)
++/* XXX document */
++int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_ocp_mod,
++ struct omap_vdd_info *omap_vdd_array[],
++ u8 omap_vdd_count)
+ {
+- if (cpu_is_omap34xx()) {
+- vdd_info = omap3_vdd_info;
+- nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD;
+- vc_init = omap3_vc_init;
+- vdd_data_configure = omap3_vdd_data_configure;
+- } else if (cpu_is_omap44xx()) {
+- vdd_info = omap4_vdd_info;
+- nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
+- vc_init = omap4_vc_init;
+- vdd_data_configure = omap4_vdd_data_configure;
+- } else {
+- pr_warning("%s: voltage driver support not added\n", __func__);
+- }
+-
++ prm_mod_offs = prm_mod;
++ prm_irqst_ocp_mod_offs = prm_irqst_ocp_mod;
++ vdd_info = omap_vdd_array;
++ nr_scalable_vdd = omap_vdd_count;
+ return 0;
+ }
+-core_initcall(omap_voltage_early_init);
+diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
+index 5bd204e..e9f5408 100644
+--- a/arch/arm/mach-omap2/voltage.h
++++ b/arch/arm/mach-omap2/voltage.h
+@@ -16,6 +16,10 @@
+
+ #include <linux/err.h>
+
++#include "vc.h"
++#include "vp.h"
++
++/* XXX document */
+ #define VOLTSCALE_VPFORCEUPDATE 1
+ #define VOLTSCALE_VCBYPASS 2
+
+@@ -27,36 +31,22 @@
+ #define OMAP3_VOLTOFFSET 0xff
+ #define OMAP3_VOLTSETUP2 0xff
+
+-/* Voltage value defines */
+-#define OMAP3430_VDD_MPU_OPP1_UV 975000
+-#define OMAP3430_VDD_MPU_OPP2_UV 1075000
+-#define OMAP3430_VDD_MPU_OPP3_UV 1200000
+-#define OMAP3430_VDD_MPU_OPP4_UV 1270000
+-#define OMAP3430_VDD_MPU_OPP5_UV 1350000
+-
+-#define OMAP3430_VDD_CORE_OPP1_UV 975000
+-#define OMAP3430_VDD_CORE_OPP2_UV 1050000
+-#define OMAP3430_VDD_CORE_OPP3_UV 1150000
+-
+-#define OMAP3630_VDD_MPU_OPP50_UV 1012500
+-#define OMAP3630_VDD_MPU_OPP100_UV 1200000
+-#define OMAP3630_VDD_MPU_OPP120_UV 1325000
+-#define OMAP3630_VDD_MPU_OPP1G_UV 1375000
+-
+-#define OMAP3630_VDD_CORE_OPP50_UV 1000000
+-#define OMAP3630_VDD_CORE_OPP100_UV 1200000
+-
+-#define OMAP4430_VDD_MPU_OPP50_UV 930000
+-#define OMAP4430_VDD_MPU_OPP100_UV 1100000
+-#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000
+-#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000
+-
+-#define OMAP4430_VDD_IVA_OPP50_UV 930000
+-#define OMAP4430_VDD_IVA_OPP100_UV 1100000
+-#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000
+-
+-#define OMAP4430_VDD_CORE_OPP50_UV 930000
+-#define OMAP4430_VDD_CORE_OPP100_UV 1100000
++/**
++ * struct omap_vfsm_instance_data - per-voltage manager FSM register/bitfield
++ * data
++ * @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
++ * @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
++ * @voltsetup_shift: SETUP_TIME* field shift in the PRM_VOLTSETUP* register
++ *
++ * XXX What about VOLTOFFSET/VOLTCTRL?
++ * XXX It is not necessary to have both a _mask and a _shift for the same
++ * bitfield - remove one!
++ */
++struct omap_vfsm_instance_data {
++ u32 voltsetup_mask;
++ u8 voltsetup_reg;
++ u8 voltsetup_shift;
++};
+
+ /**
+ * struct voltagedomain - omap voltage domain global structure.
+@@ -113,6 +103,42 @@ struct omap_volt_pmic_info {
+ u8 (*uv_to_vsel) (unsigned long uV);
+ };
+
++/**
++ * omap_vdd_info - Per Voltage Domain info
++ *
++ * @volt_data : voltage table having the distinct voltages supported
++ * by the domain and other associated per voltage data.
++ * @pmic_info : pmic specific parameters which should be populted by
++ * the pmic drivers.
++ * @vp_data : the register values, shifts, masks for various
++ * vp registers
++ * @vp_rt_data : VP data derived at runtime, not predefined
++ * @vc_data : structure containing various various vc registers,
++ * shifts, masks etc.
++ * @vfsm : voltage manager FSM data
++ * @voltdm : pointer to the voltage domain structure
++ * @debug_dir : debug directory for this voltage domain.
++ * @curr_volt : current voltage for this vdd.
++ * @vp_enabled : flag to keep track of whether vp is enabled or not
++ * @volt_scale : API to scale the voltage of the vdd.
++ */
++struct omap_vdd_info {
++ struct omap_volt_data *volt_data;
++ struct omap_volt_pmic_info *pmic_info;
++ struct omap_vp_instance_data *vp_data;
++ struct omap_vp_runtime_data vp_rt_data;
++ struct omap_vc_instance_data *vc_data;
++ const struct omap_vfsm_instance_data *vfsm;
++ struct voltagedomain voltdm;
++ struct dentry *debug_dir;
++ u32 curr_volt;
++ bool vp_enabled;
++ u32 (*read_reg) (u16 mod, u8 offset);
++ void (*write_reg) (u32 val, u16 mod, u8 offset);
++ int (*volt_scale) (struct omap_vdd_info *vdd,
++ unsigned long target_volt);
++};
++
+ unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
+ void omap_vp_enable(struct voltagedomain *voltdm);
+ void omap_vp_disable(struct voltagedomain *voltdm);
+@@ -125,6 +151,9 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+ unsigned long volt);
+ unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+ struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
++int __init omap_voltage_early_init(s16 prm_mod, s16 prm_irqst_mod,
++ struct omap_vdd_info *omap_vdd_array[],
++ u8 omap_vdd_count);
+ #ifdef CONFIG_PM
+ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+ struct omap_volt_pmic_info *pmic_info);
+diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+new file mode 100644
+index 0000000..def230f
+--- /dev/null
++++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+@@ -0,0 +1,95 @@
++/*
++ * OMAP3 voltage domain data
++ *
++ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
++ * Rajendra Nayak <rnayak@ti.com>
++ * Lesly A M <x0080970@ti.com>
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2008, 2011 Nokia Corporation
++ * Kalle Jokiniemi
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/kernel.h>
++#include <linux/err.h>
++#include <linux/init.h>
++
++#include <plat/common.h>
++#include <plat/cpu.h>
++
++#include "prm-regbits-34xx.h"
++#include "omap_opp_data.h"
++#include "voltage.h"
++#include "vc.h"
++#include "vp.h"
++
++/*
++ * VDD data
++ */
++
++static const struct omap_vfsm_instance_data omap3_vdd1_vfsm_data = {
++ .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
++ .voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT,
++ .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
++};
++
++static struct omap_vdd_info omap3_vdd1_info = {
++ .vp_data = &omap3_vp1_data,
++ .vc_data = &omap3_vc1_data,
++ .vfsm = &omap3_vdd1_vfsm_data,
++ .voltdm = {
++ .name = "mpu",
++ },
++};
++
++static const struct omap_vfsm_instance_data omap3_vdd2_vfsm_data = {
++ .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
++ .voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT,
++ .voltsetup_mask = OMAP3430_SETUP_TIME2_MASK,
++};
++
++static struct omap_vdd_info omap3_vdd2_info = {
++ .vp_data = &omap3_vp2_data,
++ .vc_data = &omap3_vc2_data,
++ .vfsm = &omap3_vdd2_vfsm_data,
++ .voltdm = {
++ .name = "core",
++ },
++};
++
++/* OMAP3 VDD structures */
++static struct omap_vdd_info *omap3_vdd_info[] = {
++ &omap3_vdd1_info,
++ &omap3_vdd2_info,
++};
++
++/* OMAP3 specific voltage init functions */
++static int __init omap3xxx_voltage_early_init(void)
++{
++ s16 prm_mod = OMAP3430_GR_MOD;
++ s16 prm_irqst_ocp_mod = OCP_MOD;
++
++ if (!cpu_is_omap34xx())
++ return 0;
++
++ /*
++ * XXX Will depend on the process, validation, and binning
++ * for the currently-running IC
++ */
++ if (cpu_is_omap3630()) {
++ omap3_vdd1_info.volt_data = omap36xx_vddmpu_volt_data;
++ omap3_vdd2_info.volt_data = omap36xx_vddcore_volt_data;
++ } else {
++ omap3_vdd1_info.volt_data = omap34xx_vddmpu_volt_data;
++ omap3_vdd2_info.volt_data = omap34xx_vddcore_volt_data;
++ }
++
++ return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
++ omap3_vdd_info,
++ ARRAY_SIZE(omap3_vdd_info));
++};
++core_initcall(omap3xxx_voltage_early_init);
+diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+new file mode 100644
+index 0000000..cb64996
+--- /dev/null
++++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
+@@ -0,0 +1,102 @@
++/*
++ * OMAP3/OMAP4 Voltage Management Routines
++ *
++ * Author: Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2007 Texas Instruments, Inc.
++ * Rajendra Nayak <rnayak@ti.com>
++ * Lesly A M <x0080970@ti.com>
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Kalle Jokiniemi
++ *
++ * Copyright (C) 2010 Texas Instruments, Inc.
++ * Thara Gopinath <thara@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/kernel.h>
++#include <linux/err.h>
++#include <linux/init.h>
++
++#include <plat/common.h>
++
++#include "prm-regbits-44xx.h"
++#include "prm44xx.h"
++#include "prcm44xx.h"
++#include "prminst44xx.h"
++#include "voltage.h"
++#include "omap_opp_data.h"
++#include "vc.h"
++#include "vp.h"
++
++static const struct omap_vfsm_instance_data omap4_vdd_mpu_vfsm_data = {
++ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
++};
++
++static struct omap_vdd_info omap4_vdd_mpu_info = {
++ .vp_data = &omap4_vp_mpu_data,
++ .vc_data = &omap4_vc_mpu_data,
++ .vfsm = &omap4_vdd_mpu_vfsm_data,
++ .voltdm = {
++ .name = "mpu",
++ },
++};
++
++static const struct omap_vfsm_instance_data omap4_vdd_iva_vfsm_data = {
++ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
++};
++
++static struct omap_vdd_info omap4_vdd_iva_info = {
++ .vp_data = &omap4_vp_iva_data,
++ .vc_data = &omap4_vc_iva_data,
++ .vfsm = &omap4_vdd_iva_vfsm_data,
++ .voltdm = {
++ .name = "iva",
++ },
++};
++
++static const struct omap_vfsm_instance_data omap4_vdd_core_vfsm_data = {
++ .voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
++};
++
++static struct omap_vdd_info omap4_vdd_core_info = {
++ .vp_data = &omap4_vp_core_data,
++ .vc_data = &omap4_vc_core_data,
++ .vfsm = &omap4_vdd_core_vfsm_data,
++ .voltdm = {
++ .name = "core",
++ },
++};
++
++/* OMAP4 VDD structures */
++static struct omap_vdd_info *omap4_vdd_info[] = {
++ &omap4_vdd_mpu_info,
++ &omap4_vdd_iva_info,
++ &omap4_vdd_core_info,
++};
++
++/* OMAP4 specific voltage init functions */
++static int __init omap44xx_voltage_early_init(void)
++{
++ s16 prm_mod = OMAP4430_PRM_DEVICE_INST;
++ s16 prm_irqst_ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
++
++ if (!cpu_is_omap44xx())
++ return 0;
++
++ /*
++ * XXX Will depend on the process, validation, and binning
++ * for the currently-running IC
++ */
++ omap4_vdd_mpu_info.volt_data = omap44xx_vdd_mpu_volt_data;
++ omap4_vdd_iva_info.volt_data = omap44xx_vdd_iva_volt_data;
++ omap4_vdd_core_info.volt_data = omap44xx_vdd_core_volt_data;
++
++ return omap_voltage_early_init(prm_mod, prm_irqst_ocp_mod,
++ omap4_vdd_info,
++ ARRAY_SIZE(omap4_vdd_info));
++};
++core_initcall(omap44xx_voltage_early_init);
+diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
+new file mode 100644
+index 0000000..7ce134f
+--- /dev/null
++++ b/arch/arm/mach-omap2/vp.h
+@@ -0,0 +1,143 @@
++/*
++ * OMAP3/4 Voltage Processor (VP) structure and macro definitions
++ *
++ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
++ * Rajendra Nayak <rnayak@ti.com>
++ * Lesly A M <x0080970@ti.com>
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2008, 2011 Nokia Corporation
++ * Kalle Jokiniemi
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License version
++ * 2 as published by the Free Software Foundation.
++ */
++#ifndef __ARCH_ARM_MACH_OMAP2_VP_H
++#define __ARCH_ARM_MACH_OMAP2_VP_H
++
++#include <linux/kernel.h>
++
++/* XXX document */
++#define VP_IDLE_TIMEOUT 200
++#define VP_TRANXDONE_TIMEOUT 300
++
++
++/**
++ * struct omap_vp_common_data - register data common to all VDDs
++ * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
++ * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
++ * @vpconfig_timeouten_mask: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
++ * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
++ * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
++ * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
++ * @vpconfig_erroroffset_shift: ERROROFFSET field shift in PRM_VP*_CONFIG reg
++ * @vpconfig_errorgain_shift: ERRORGAIN field shift in PRM_VP*_CONFIG reg
++ * @vpconfig_initvoltage_shift: INITVOLTAGE field shift in PRM_VP*_CONFIG reg
++ * @vpconfig_stepmin_shift: VSTEPMIN field shift in the PRM_VP*_VSTEPMIN reg
++ * @vpconfig_smpswaittimemin_shift: SMPSWAITTIMEMIN field shift in PRM_VP*_VSTEPMIN reg
++ * @vpconfig_stepmax_shift: VSTEPMAX field shift in the PRM_VP*_VSTEPMAX reg
++ * @vpconfig_smpswaittimemax_shift: SMPSWAITTIMEMAX field shift in PRM_VP*_VSTEPMAX reg
++ * @vpconfig_vlimitto_vddmin_shift: VDDMIN field shift in PRM_VP*_VLIMITTO reg
++ * @vpconfig_vlimitto_vddmax_shift: VDDMAX field shift in PRM_VP*_VLIMITTO reg
++ * @vpconfig_vlimitto_timeout_shift: TIMEOUT field shift in PRM_VP*_VLIMITTO reg
++ *
++ * XXX It it not necessary to have both a mask and a shift for the same
++ * bitfield - remove one
++ * XXX Many of these fields are wrongly named -- e.g., vpconfig_smps* -- fix!
++ */
++struct omap_vp_common_data {
++ u32 vpconfig_errorgain_mask;
++ u32 vpconfig_initvoltage_mask;
++ u32 vpconfig_timeouten;
++ u32 vpconfig_initvdd;
++ u32 vpconfig_forceupdate;
++ u32 vpconfig_vpenable;
++ u8 vpconfig_erroroffset_shift;
++ u8 vpconfig_errorgain_shift;
++ u8 vpconfig_initvoltage_shift;
++ u8 vstepmin_stepmin_shift;
++ u8 vstepmin_smpswaittimemin_shift;
++ u8 vstepmax_stepmax_shift;
++ u8 vstepmax_smpswaittimemax_shift;
++ u8 vlimitto_vddmin_shift;
++ u8 vlimitto_vddmax_shift;
++ u8 vlimitto_timeout_shift;
++};
++
++/**
++ * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data
++ * @prm_irqst_reg: reg offset for PRM_IRQSTATUS_MPU from top of PRM
++ * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
++ *
++ * XXX prm_irqst_reg does not belong here
++ * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a
++ * hardware bug
++ * XXX This structure is probably not needed
++ */
++struct omap_vp_prm_irqst_data {
++ u8 prm_irqst_reg;
++ u32 tranxdone_status;
++};
++
++/**
++ * struct omap_vp_instance_data - VP register offsets (per-VDD)
++ * @vp_common: pointer to struct omap_vp_common_data * for this SoC
++ * @prm_irqst_data: pointer to struct omap_vp_prm_irqst_data for this VDD
++ * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start
++ * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start
++ * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start
++ * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start
++ * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start
++ *
++ * XXX vp_common is probably not needed since it is per-SoC
++ */
++struct omap_vp_instance_data {
++ const struct omap_vp_common_data *vp_common;
++ const struct omap_vp_prm_irqst_data *prm_irqst_data;
++ u8 vpconfig;
++ u8 vstepmin;
++ u8 vstepmax;
++ u8 vlimitto;
++ u8 vstatus;
++ u8 voltage;
++};
++
++/**
++ * struct omap_vp_runtime_data - VP data populated at runtime by code
++ * @vpconfig_erroroffset: value of ERROROFFSET bitfield in PRM_VP*_CONFIG
++ * @vpconfig_errorgain: value of ERRORGAIN bitfield in PRM_VP*_CONFIG
++ * @vstepmin_smpswaittimemin: value of SMPSWAITTIMEMIN bitfield in PRM_VP*_VSTEPMIN
++ * @vstepmax_smpswaittimemax: value of SMPSWAITTIMEMAX bitfield in PRM_VP*_VSTEPMAX
++ * @vlimitto_timeout: value of TIMEOUT bitfield in PRM_VP*_VLIMITTO
++ * @vstepmin_stepmin: value of VSTEPMIN bitfield in PRM_VP*_VSTEPMIN
++ * @vstepmax_stepmax: value of VSTEPMAX bitfield in PRM_VP*_VSTEPMAX
++ * @vlimitto_vddmin: value of VDDMIN bitfield in PRM_VP*_VLIMITTO
++ * @vlimitto_vddmax: value of VDDMAX bitfield in PRM_VP*_VLIMITTO
++ *
++ * XXX Is this structure really needed? Why not just program the
++ * device directly? They are in PRM space, therefore in the WKUP
++ * powerdomain, so register contents should not be lost in off-mode.
++ * XXX Some of these fields are incorrectly named, e.g., vstep*
++ */
++struct omap_vp_runtime_data {
++ u32 vpconfig_erroroffset;
++ u16 vpconfig_errorgain;
++ u16 vstepmin_smpswaittimemin;
++ u16 vstepmax_smpswaittimemax;
++ u16 vlimitto_timeout;
++ u8 vstepmin_stepmin;
++ u8 vstepmax_stepmax;
++ u8 vlimitto_vddmin;
++ u8 vlimitto_vddmax;
++};
++
++extern struct omap_vp_instance_data omap3_vp1_data;
++extern struct omap_vp_instance_data omap3_vp2_data;
++
++extern struct omap_vp_instance_data omap4_vp_mpu_data;
++extern struct omap_vp_instance_data omap4_vp_iva_data;
++extern struct omap_vp_instance_data omap4_vp_core_data;
++
++#endif
+diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
+new file mode 100644
+index 0000000..6452170
+--- /dev/null
++++ b/arch/arm/mach-omap2/vp3xxx_data.c
+@@ -0,0 +1,82 @@
++/*
++ * OMAP3 Voltage Processor (VP) data
++ *
++ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
++ * Rajendra Nayak <rnayak@ti.com>
++ * Lesly A M <x0080970@ti.com>
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2008, 2011 Nokia Corporation
++ * Kalle Jokiniemi
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/init.h>
++
++#include <plat/common.h>
++
++#include "prm-regbits-34xx.h"
++#include "voltage.h"
++
++#include "vp.h"
++
++/*
++ * VP data common to 34xx/36xx chips
++ * XXX This stuff presumably belongs in the vp3xxx.c or vp.c file.
++ */
++static const struct omap_vp_common_data omap3_vp_common = {
++ .vpconfig_erroroffset_shift = OMAP3430_ERROROFFSET_SHIFT,
++ .vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK,
++ .vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT,
++ .vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT,
++ .vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK,
++ .vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK,
++ .vpconfig_initvdd = OMAP3430_INITVDD_MASK,
++ .vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK,
++ .vpconfig_vpenable = OMAP3430_VPENABLE_MASK,
++ .vstepmin_smpswaittimemin_shift = OMAP3430_SMPSWAITTIMEMIN_SHIFT,
++ .vstepmax_smpswaittimemax_shift = OMAP3430_SMPSWAITTIMEMAX_SHIFT,
++ .vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT,
++ .vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT,
++ .vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT,
++ .vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT,
++ .vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT,
++};
++
++static const struct omap_vp_prm_irqst_data omap3_vp1_prm_irqst_data = {
++ .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
++ .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
++};
++
++struct omap_vp_instance_data omap3_vp1_data = {
++ .vp_common = &omap3_vp_common,
++ .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
++ .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
++ .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
++ .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
++ .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
++ .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
++ .prm_irqst_data = &omap3_vp1_prm_irqst_data,
++};
++
++static const struct omap_vp_prm_irqst_data omap3_vp2_prm_irqst_data = {
++ .prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
++ .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
++};
++
++struct omap_vp_instance_data omap3_vp2_data = {
++ .vp_common = &omap3_vp_common,
++ .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
++ .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
++ .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
++ .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
++ .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
++ .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
++ .prm_irqst_data = &omap3_vp2_prm_irqst_data,
++};
+diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
+new file mode 100644
+index 0000000..65d1ad6
+--- /dev/null
++++ b/arch/arm/mach-omap2/vp44xx_data.c
+@@ -0,0 +1,100 @@
++/*
++ * OMAP3 Voltage Processor (VP) data
++ *
++ * Copyright (C) 2007, 2010 Texas Instruments, Inc.
++ * Rajendra Nayak <rnayak@ti.com>
++ * Lesly A M <x0080970@ti.com>
++ * Thara Gopinath <thara@ti.com>
++ *
++ * Copyright (C) 2008, 2011 Nokia Corporation
++ * Kalle Jokiniemi
++ * Paul Walmsley
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/init.h>
++
++#include <plat/common.h>
++
++#include "prm44xx.h"
++#include "prm-regbits-44xx.h"
++#include "voltage.h"
++
++#include "vp.h"
++
++/*
++ * VP data common to 44xx chips
++ * XXX This stuff presumably belongs in the vp44xx.c or vp.c file.
++ */
++static const struct omap_vp_common_data omap4_vp_common = {
++ .vpconfig_erroroffset_shift = OMAP4430_ERROROFFSET_SHIFT,
++ .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK,
++ .vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT,
++ .vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT,
++ .vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK,
++ .vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK,
++ .vpconfig_initvdd = OMAP4430_INITVDD_MASK,
++ .vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK,
++ .vpconfig_vpenable = OMAP4430_VPENABLE_MASK,
++ .vstepmin_smpswaittimemin_shift = OMAP4430_SMPSWAITTIMEMIN_SHIFT,
++ .vstepmax_smpswaittimemax_shift = OMAP4430_SMPSWAITTIMEMAX_SHIFT,
++ .vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT,
++ .vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT,
++ .vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT,
++ .vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT,
++ .vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT,
++};
++
++static const struct omap_vp_prm_irqst_data omap4_vp_mpu_prm_irqst_data = {
++ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
++ .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
++};
++
++struct omap_vp_instance_data omap4_vp_mpu_data = {
++ .vp_common = &omap4_vp_common,
++ .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
++ .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
++ .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
++ .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
++ .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
++ .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
++ .prm_irqst_data = &omap4_vp_mpu_prm_irqst_data,
++};
++
++static const struct omap_vp_prm_irqst_data omap4_vp_iva_prm_irqst_data = {
++ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
++ .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
++};
++
++struct omap_vp_instance_data omap4_vp_iva_data = {
++ .vp_common = &omap4_vp_common,
++ .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
++ .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
++ .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
++ .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
++ .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
++ .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
++ .prm_irqst_data = &omap4_vp_iva_prm_irqst_data,
++};
++
++static const struct omap_vp_prm_irqst_data omap4_vp_core_prm_irqst_data = {
++ .prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
++ .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
++};
++
++struct omap_vp_instance_data omap4_vp_core_data = {
++ .vp_common = &omap4_vp_common,
++ .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
++ .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
++ .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
++ .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
++ .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
++ .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
++ .prm_irqst_data = &omap4_vp_core_prm_irqst_data,
++};
++
+--
+1.7.1
+
diff --git a/patches/for_next/0238-Watchdog-omap_wdt-add-fine-grain-runtime-pm.patch b/patches/for_next/0238-Watchdog-omap_wdt-add-fine-grain-runtime-pm.patch
new file mode 100644
index 0000000000000000000000000000000000000000..a4affb41b550f74157ec291012ea2657bc8b4d78
--- /dev/null
+++ b/patches/for_next/0238-Watchdog-omap_wdt-add-fine-grain-runtime-pm.patch
@@ -0,0 +1,142 @@
+From 4113ebb4bfd8b66db864e8ba7eef5a3077d962cd Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Thu, 10 Mar 2011 22:40:05 -0700
+Subject: [PATCH 238/254] Watchdog: omap_wdt: add fine grain runtime-pm
+
+The omap_wdt should only be in full active state when the
+registers are being accessed. Otherwise the device can be
+on lower power mode.
+
+This patch is based on a patch created by Kalle Jokiniemi:
+https://patchwork.kernel.org/patch/618231/
+which is itself based on a patch created by Atal
+Shargorodsky: http://lkml.org/lkml/2009/3/10/266.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@nokia.com>
+Tested-by: Kalle Jokiniemi <kalle.jokiniemi@nokia.com>
+Cc: Wim Van Sebroeck <wim@iguana.be>
+Acked-by: Wim Van Sebroeck <wim@iguana.be>
+Acked-by: Kevin Hilman <khilman@ti.com>
+---
+ drivers/watchdog/omap_wdt.c | 25 +++++++++++++++++++++++--
+ 1 files changed, 23 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
+index 3dd4971..2b4acb8 100644
+--- a/drivers/watchdog/omap_wdt.c
++++ b/drivers/watchdog/omap_wdt.c
+@@ -124,6 +124,8 @@ static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
+ u32 pre_margin = GET_WLDR_VAL(timer_margin);
+ void __iomem *base = wdev->base;
+
++ pm_runtime_get_sync(wdev->dev);
++
+ /* just count up at 32 KHz */
+ while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
+ cpu_relax();
+@@ -131,6 +133,8 @@ static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
+ __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
+ while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
+ cpu_relax();
++
++ pm_runtime_put_sync(wdev->dev);
+ }
+
+ /*
+@@ -160,6 +164,8 @@ static int omap_wdt_open(struct inode *inode, struct file *file)
+ omap_wdt_ping(wdev); /* trigger loading of new timeout value */
+ omap_wdt_enable(wdev);
+
++ pm_runtime_put_sync(wdev->dev);
++
+ return nonseekable_open(inode, file);
+ }
+
+@@ -171,6 +177,7 @@ static int omap_wdt_release(struct inode *inode, struct file *file)
+ * Shut off the timer unless NOWAYOUT is defined.
+ */
+ #ifndef CONFIG_WATCHDOG_NOWAYOUT
++ pm_runtime_get_sync(wdev->dev);
+
+ omap_wdt_disable(wdev);
+
+@@ -190,9 +197,11 @@ static ssize_t omap_wdt_write(struct file *file, const char __user *data,
+
+ /* Refresh LOAD_TIME. */
+ if (len) {
++ pm_runtime_get_sync(wdev->dev);
+ spin_lock(&wdt_lock);
+ omap_wdt_ping(wdev);
+ spin_unlock(&wdt_lock);
++ pm_runtime_put_sync(wdev->dev);
+ }
+ return len;
+ }
+@@ -224,15 +233,18 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
+ return put_user(omap_prcm_get_reset_sources(),
+ (int __user *)arg);
+ case WDIOC_KEEPALIVE:
++ pm_runtime_get_sync(wdev->dev);
+ spin_lock(&wdt_lock);
+ omap_wdt_ping(wdev);
+ spin_unlock(&wdt_lock);
++ pm_runtime_put_sync(wdev->dev);
+ return 0;
+ case WDIOC_SETTIMEOUT:
+ if (get_user(new_margin, (int __user *)arg))
+ return -EFAULT;
+ omap_wdt_adjust_timeout(new_margin);
+
++ pm_runtime_get_sync(wdev->dev);
+ spin_lock(&wdt_lock);
+ omap_wdt_disable(wdev);
+ omap_wdt_set_timeout(wdev);
+@@ -240,6 +252,7 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
+
+ omap_wdt_ping(wdev);
+ spin_unlock(&wdt_lock);
++ pm_runtime_put_sync(wdev->dev);
+ /* Fall */
+ case WDIOC_GETTIMEOUT:
+ return put_user(timer_margin, (int __user *)arg);
+@@ -345,8 +358,11 @@ static void omap_wdt_shutdown(struct platform_device *pdev)
+ {
+ struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
+
+- if (wdev->omap_wdt_users)
++ if (wdev->omap_wdt_users) {
++ pm_runtime_get_sync(wdev->dev);
+ omap_wdt_disable(wdev);
++ pm_runtime_put_sync(wdev->dev);
++ }
+ }
+
+ static int __devexit omap_wdt_remove(struct platform_device *pdev)
+@@ -381,8 +397,11 @@ static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
+ {
+ struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
+
+- if (wdev->omap_wdt_users)
++ if (wdev->omap_wdt_users) {
++ pm_runtime_get_sync(wdev->dev);
+ omap_wdt_disable(wdev);
++ pm_runtime_put_sync(wdev->dev);
++ }
+
+ return 0;
+ }
+@@ -392,8 +411,10 @@ static int omap_wdt_resume(struct platform_device *pdev)
+ struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
+
+ if (wdev->omap_wdt_users) {
++ pm_runtime_get_sync(wdev->dev);
+ omap_wdt_enable(wdev);
+ omap_wdt_ping(wdev);
++ pm_runtime_put_sync(wdev->dev);
+ }
+
+ return 0;
+--
+1.7.1
+
diff --git a/patches/for_next/0239-OMAP3-wdtimer-Fix-CORE-idle-transition.patch b/patches/for_next/0239-OMAP3-wdtimer-Fix-CORE-idle-transition.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5ba62776b2dc6bd30c0664632f0ad0ab60187fe6
--- /dev/null
+++ b/patches/for_next/0239-OMAP3-wdtimer-Fix-CORE-idle-transition.patch
@@ -0,0 +1,38 @@
+From 988ec1258a6e56b9e229d5d51e0ab3ee0983ee53 Mon Sep 17 00:00:00 2001
+From: Paul Walmsley <paul@pwsan.com>
+Date: Thu, 10 Mar 2011 22:40:06 -0700
+Subject: [PATCH 239/254] OMAP3: wdtimer: Fix CORE idle transition
+
+The HW superwised smart idle for wdtimer in OMAP3 prevents
+CORE power domain idle transitions. Disable it by swithing
+to SW supervised transitions.
+
+This could be a hardware bug in the OMAP3 wdtimer2 block.
+
+Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@nokia.com>
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+Cc: Benoit Cousson <b-cousson@ti.com>
+Acked-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 5 +++++
+ 1 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+index 6a5de99..1d05660 100644
+--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+@@ -1282,6 +1282,11 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
+ .slaves = omap3xxx_wd_timer2_slaves,
+ .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
++ /*
++ * XXX: Use software supervised mode, HW supervised smartidle seems to
++ * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
++ */
++ .flags = HWMOD_SWSUP_SIDLE,
+ };
+
+ /* UART common */
+--
+1.7.1
+
diff --git a/patches/for_next/0240-OMAP3-OPP-Replace-voltage-values-with-Macros.patch b/patches/for_next/0240-OMAP3-OPP-Replace-voltage-values-with-Macros.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f60e1ea2ab101c8b35782b705aaffe54bc062973
--- /dev/null
+++ b/patches/for_next/0240-OMAP3-OPP-Replace-voltage-values-with-Macros.patch
@@ -0,0 +1,140 @@
+From efdaf5697d705411eba3b051914248d406c629b9 Mon Sep 17 00:00:00 2001
+From: Vishwanath BS <vishwanath.bs@ti.com>
+Date: Sat, 5 Mar 2011 15:57:22 +0530
+Subject: [PATCH 240/254] OMAP3+: OPP: Replace voltage values with Macros
+
+Since all voltage data is now centralized in oppxxx_data.c, we can replace
+the values in the opp table with the macros used for voltage values.
+
+This will avoid opp table and voltage layer having conflicting values.
+
+Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/opp3xxx_data.c | 46 ++++++++++++++++++------------------
+ arch/arm/mach-omap2/opp4xxx_data.c | 12 ++++----
+ 2 files changed, 29 insertions(+), 29 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
+index d2bd1bd..d95f3f9 100644
+--- a/arch/arm/mach-omap2/opp3xxx_data.c
++++ b/arch/arm/mach-omap2/opp3xxx_data.c
+@@ -89,15 +89,15 @@ struct omap_volt_data omap36xx_vddcore_volt_data[] = {
+
+ static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
+ /* MPU OPP1 */
+- OPP_INITIALIZER("mpu", true, 125000000, 975000),
++ OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
+ /* MPU OPP2 */
+- OPP_INITIALIZER("mpu", true, 250000000, 1075000),
++ OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
+ /* MPU OPP3 */
+- OPP_INITIALIZER("mpu", true, 500000000, 1200000),
++ OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
+ /* MPU OPP4 */
+- OPP_INITIALIZER("mpu", true, 550000000, 1270000),
++ OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
+ /* MPU OPP5 */
+- OPP_INITIALIZER("mpu", true, 600000000, 1350000),
++ OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
+
+ /*
+ * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
+@@ -107,47 +107,47 @@ static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
+ * impact that frequency will do to the MPU and the whole system in
+ * general.
+ */
+- OPP_INITIALIZER("l3_main", false, 41500000, 975000),
++ OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
+ /* L3 OPP2 */
+- OPP_INITIALIZER("l3_main", true, 83000000, 1050000),
++ OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
+ /* L3 OPP3 */
+- OPP_INITIALIZER("l3_main", true, 166000000, 1150000),
++ OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
+
+ /* DSP OPP1 */
+- OPP_INITIALIZER("iva", true, 90000000, 975000),
++ OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
+ /* DSP OPP2 */
+- OPP_INITIALIZER("iva", true, 180000000, 1075000),
++ OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
+ /* DSP OPP3 */
+- OPP_INITIALIZER("iva", true, 360000000, 1200000),
++ OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
+ /* DSP OPP4 */
+- OPP_INITIALIZER("iva", true, 400000000, 1270000),
++ OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
+ /* DSP OPP5 */
+- OPP_INITIALIZER("iva", true, 430000000, 1350000),
++ OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
+ };
+
+ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
+ /* MPU OPP1 - OPP50 */
+- OPP_INITIALIZER("mpu", true, 300000000, 1012500),
++ OPP_INITIALIZER("mpu", true, 300000000, OMAP3630_VDD_MPU_OPP50_UV),
+ /* MPU OPP2 - OPP100 */
+- OPP_INITIALIZER("mpu", true, 600000000, 1200000),
++ OPP_INITIALIZER("mpu", true, 600000000, OMAP3630_VDD_MPU_OPP100_UV),
+ /* MPU OPP3 - OPP-Turbo */
+- OPP_INITIALIZER("mpu", false, 800000000, 1325000),
++ OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
+ /* MPU OPP4 - OPP-SB */
+- OPP_INITIALIZER("mpu", false, 1000000000, 1375000),
++ OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
+
+ /* L3 OPP1 - OPP50 */
+- OPP_INITIALIZER("l3_main", true, 100000000, 1000000),
++ OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
+ /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+- OPP_INITIALIZER("l3_main", true, 200000000, 1200000),
++ OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
+
+ /* DSP OPP1 - OPP50 */
+- OPP_INITIALIZER("iva", true, 260000000, 1012500),
++ OPP_INITIALIZER("iva", true, 260000000, OMAP3630_VDD_MPU_OPP50_UV),
+ /* DSP OPP2 - OPP100 */
+- OPP_INITIALIZER("iva", true, 520000000, 1200000),
++ OPP_INITIALIZER("iva", true, 520000000, OMAP3630_VDD_MPU_OPP100_UV),
+ /* DSP OPP3 - OPP-Turbo */
+- OPP_INITIALIZER("iva", false, 660000000, 1325000),
++ OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
+ /* DSP OPP4 - OPP-SB */
+- OPP_INITIALIZER("iva", false, 800000000, 1375000),
++ OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
+ };
+
+ /**
+diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
+index 5030794..57f1498 100644
+--- a/arch/arm/mach-omap2/opp4xxx_data.c
++++ b/arch/arm/mach-omap2/opp4xxx_data.c
+@@ -67,17 +67,17 @@ struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+
+ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+ /* MPU OPP1 - OPP50 */
+- OPP_INITIALIZER("mpu", true, 300000000, 1100000),
++ OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
+ /* MPU OPP2 - OPP100 */
+- OPP_INITIALIZER("mpu", true, 600000000, 1200000),
++ OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
+ /* MPU OPP3 - OPP-Turbo */
+- OPP_INITIALIZER("mpu", false, 800000000, 1260000),
++ OPP_INITIALIZER("mpu", false, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV),
+ /* MPU OPP4 - OPP-SB */
+- OPP_INITIALIZER("mpu", false, 1008000000, 1350000),
++ OPP_INITIALIZER("mpu", false, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV),
+ /* L3 OPP1 - OPP50 */
+- OPP_INITIALIZER("l3_main_1", true, 100000000, 930000),
++ OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV),
+ /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+- OPP_INITIALIZER("l3_main_1", true, 200000000, 1100000),
++ OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV),
+ /* TODO: add IVA, DSP, aess, fdif, gpu */
+ };
+
+--
+1.7.1
+
diff --git a/patches/for_next/0241-OMAP4-Enable-800-MHz-and-1-GHz-MPU-OPP.patch b/patches/for_next/0241-OMAP4-Enable-800-MHz-and-1-GHz-MPU-OPP.patch
new file mode 100644
index 0000000000000000000000000000000000000000..45b149e83a854689d295c5734443e56ec9c144c8
--- /dev/null
+++ b/patches/for_next/0241-OMAP4-Enable-800-MHz-and-1-GHz-MPU-OPP.patch
@@ -0,0 +1,36 @@
+From 4640f1bed31b0eadbd759cc5b52eacd09b10df71 Mon Sep 17 00:00:00 2001
+From: Shweta Gulati <shweta.gulati@ti.com>
+Date: Sat, 5 Mar 2011 15:21:21 +0530
+Subject: [PATCH 241/254] OMAP4: Enable 800 MHz and 1 GHz MPU-OPP
+
+Almost all OMAP4 boards support OPP 800 MHz and OPP 1 GHz.
+Enable them in OPP Table. For small minority of boards which use
+OMAP4430-800 MHz device OPP 1GHz is not supported,
+OPP 1GHz should be disabled from board file.
+
+Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
+Acked-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/opp4xxx_data.c | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
+index 57f1498..93b9744 100644
+--- a/arch/arm/mach-omap2/opp4xxx_data.c
++++ b/arch/arm/mach-omap2/opp4xxx_data.c
+@@ -71,9 +71,9 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+ /* MPU OPP2 - OPP100 */
+ OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
+ /* MPU OPP3 - OPP-Turbo */
+- OPP_INITIALIZER("mpu", false, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV),
++ OPP_INITIALIZER("mpu", true, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV),
+ /* MPU OPP4 - OPP-SB */
+- OPP_INITIALIZER("mpu", false, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV),
++ OPP_INITIALIZER("mpu", true, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV),
+ /* L3 OPP1 - OPP50 */
+ OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV),
+ /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+--
+1.7.1
+
diff --git a/patches/for_next/0242-OMAP4-Update-Voltage-Rail-Values-for-MPU-IVA-and-COR.patch b/patches/for_next/0242-OMAP4-Update-Voltage-Rail-Values-for-MPU-IVA-and-COR.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d0b1e61fe3d5d8d3a89eff42f8b0b46f0f98c040
--- /dev/null
+++ b/patches/for_next/0242-OMAP4-Update-Voltage-Rail-Values-for-MPU-IVA-and-COR.patch
@@ -0,0 +1,63 @@
+From 3defba794b33b41d0e8315b676fcc5c93f1275b8 Mon Sep 17 00:00:00 2001
+From: Shweta Gulati <shweta.gulati@ti.com>
+Date: Thu, 10 Mar 2011 10:23:49 +0530
+Subject: [PATCH 242/254] OMAP4: Update Voltage Rail Values for MPU, IVA and CORE
+
+Update MPU, IVA and CORE voltage Rail values obtained from
+OMAP4430 Data Manual Operating Condition Addendum_v0.4.
+
+Tested on OMAP4430 SDP Board.
+
+Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
+Acked-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/opp4xxx_data.c | 18 +++++++++---------
+ 1 files changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
+index 93b9744..b430878 100644
+--- a/arch/arm/mach-omap2/opp4xxx_data.c
++++ b/arch/arm/mach-omap2/opp4xxx_data.c
+@@ -31,10 +31,10 @@
+ * voltage dependent data for each VDD.
+ */
+
+-#define OMAP4430_VDD_MPU_OPP50_UV 930000
+-#define OMAP4430_VDD_MPU_OPP100_UV 1100000
+-#define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000
+-#define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000
++#define OMAP4430_VDD_MPU_OPP50_UV 1025000
++#define OMAP4430_VDD_MPU_OPP100_UV 1200000
++#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
++#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
+
+ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
+@@ -44,9 +44,9 @@ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+ VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
+
+-#define OMAP4430_VDD_IVA_OPP50_UV 930000
+-#define OMAP4430_VDD_IVA_OPP100_UV 1100000
+-#define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000
++#define OMAP4430_VDD_IVA_OPP50_UV 1013000
++#define OMAP4430_VDD_IVA_OPP100_UV 1188000
++#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000
+
+ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+ VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
+@@ -55,8 +55,8 @@ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+ VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
+
+-#define OMAP4430_VDD_CORE_OPP50_UV 930000
+-#define OMAP4430_VDD_CORE_OPP100_UV 1100000
++#define OMAP4430_VDD_CORE_OPP50_UV 1025000
++#define OMAP4430_VDD_CORE_OPP100_UV 1200000
+
+ struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+ VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
+--
+1.7.1
+
diff --git a/patches/for_next/0243-OMAP4-Add-IVA-OPP-enteries.patch b/patches/for_next/0243-OMAP4-Add-IVA-OPP-enteries.patch
new file mode 100644
index 0000000000000000000000000000000000000000..50224ef41b7e266a2f606e4bf1bf5f9a9229a4a8
--- /dev/null
+++ b/patches/for_next/0243-OMAP4-Add-IVA-OPP-enteries.patch
@@ -0,0 +1,38 @@
+From 215393932e1d6a8ab317ca4b3f330607b0d2bb94 Mon Sep 17 00:00:00 2001
+From: Shweta Gulati <shweta.gulati@ti.com>
+Date: Sat, 5 Mar 2011 15:22:26 +0530
+Subject: [PATCH 243/254] OMAP4: Add IVA OPP enteries.
+
+This Patch adds OPP enteries for IVA in OMAP4 OPP Table
+
+Tested on OMAP4430 SDP Board.
+
+Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
+Acked-by: Nishanth Menon <nm@ti.com>
+Signed-off-by: Kevin Hilman <khilman@ti.com>
+---
+ arch/arm/mach-omap2/opp4xxx_data.c | 8 +++++++-
+ 1 files changed, 7 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
+index b430878..2293ba2 100644
+--- a/arch/arm/mach-omap2/opp4xxx_data.c
++++ b/arch/arm/mach-omap2/opp4xxx_data.c
+@@ -78,7 +78,13 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+ OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV),
+ /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+ OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV),
+- /* TODO: add IVA, DSP, aess, fdif, gpu */
++ /* IVA OPP1 - OPP50 */
++ OPP_INITIALIZER("iva", true, 133000000, OMAP4430_VDD_IVA_OPP50_UV),
++ /* IVA OPP2 - OPP100 */
++ OPP_INITIALIZER("iva", true, 266100000, OMAP4430_VDD_IVA_OPP100_UV),
++ /* IVA OPP3 - OPP-Turbo */
++ OPP_INITIALIZER("iva", false, 332000000, OMAP4430_VDD_IVA_OPPTURBO_UV),
++ /* TODO: add DSP, aess, fdif, gpu */
+ };
+
+ /**
+--
+1.7.1
+
diff --git a/patches/dvfs/0015-perf-add-OMAP-support-for-the-new-power-events.patch b/patches/for_next/0244-perf-add-OMAP-support-for-the-new-power-events.patch
similarity index 52%
rename from patches/dvfs/0015-perf-add-OMAP-support-for-the-new-power-events.patch
rename to patches/for_next/0244-perf-add-OMAP-support-for-the-new-power-events.patch
index 1d66623cc695e3a021c3ad1a96df3c68f0671d1c..0a5da765aa014495ef64d2eae678cdead12170b8 100644
--- a/patches/dvfs/0015-perf-add-OMAP-support-for-the-new-power-events.patch
+++ b/patches/for_next/0244-perf-add-OMAP-support-for-the-new-power-events.patch
@@ -1,7 +1,7 @@
-From c4d0b3d66d6a1e9da549fff36d95c7679c209592 Mon Sep 17 00:00:00 2001
-From: Jean Pihet <j-pihet@ti.com>
-Date: Mon, 24 Jan 2011 15:20:57 +0100
-Subject: [PATCH 15/56] perf: add OMAP support for the new power events
+From 0306edd82dd0f9199ad7962762cc2fa1802545b6 Mon Sep 17 00:00:00 2001
+From: Jean Pihet <jean.pihet@newoldbits.com>
+Date: Thu, 3 Mar 2011 11:25:43 +0100
+Subject: [PATCH 244/254] perf: add OMAP support for the new power events
The patch adds the new power management trace points for
the OMAP architecture.
@@ -10,22 +10,25 @@ The trace points are for:
- default idle handler. Since the cpuidle framework is
instrumented in the generic way there is no need to
add trace points in the OMAP specific cpuidle handler;
-- cpufreq (DVFS),
- SoC clocks changes (enable, disable, set_rate),
-- change of power domains next power states.
+- power domain states: the desired target state and -if different-
+ the actually hit state.
-Tested on OMAP3 with suspend/resume, cpuidle, basic DVFS
+Because of the generic nature of the changes, OMAP3 and OMAP4 are supported.
+
+Tested on OMAP3 with suspend/resume, cpuidle, basic DVFS.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
+Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
---
- arch/arm/mach-omap2/clock.c | 8 +++++++-
+ arch/arm/mach-omap2/clock.c | 11 +++++++++--
arch/arm/mach-omap2/pm34xx.c | 7 +++++++
- arch/arm/mach-omap2/powerdomain.c | 8 +++++++-
- 3 files changed, 21 insertions(+), 2 deletions(-)
+ arch/arm/mach-omap2/powerdomain.c | 26 +++++++++++++++++++++++---
+ 3 files changed, 39 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
-index 2a2f152..72af75d 100644
+index 46d03cc..180299e 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -22,7 +22,9 @@
@@ -38,23 +41,27 @@ index 2a2f152..72af75d 100644
#include <plat/clock.h>
#include "clockdomain.h"
#include <plat/cpu.h>
-@@ -261,6 +263,7 @@ void omap2_clk_disable(struct clk *clk)
+@@ -261,8 +263,10 @@ void omap2_clk_disable(struct clk *clk)
pr_debug("clock: %s: disabling in hardware\n", clk->name);
-+ trace_clock_disable(clk->name, 0, smp_processor_id());
- clk->ops->disable(clk);
+- if (clk->ops && clk->ops->disable)
++ if (clk->ops && clk->ops->disable) {
++ trace_clock_disable(clk->name, 0, smp_processor_id());
+ clk->ops->disable(clk);
++ }
if (clk->clkdm)
-@@ -312,6 +315,7 @@ int omap2_clk_enable(struct clk *clk)
- }
+ clkdm_clk_disable(clk->clkdm, clk);
+@@ -314,6 +318,7 @@ int omap2_clk_enable(struct clk *clk)
}
-+ trace_clock_enable(clk->name, 1, smp_processor_id());
- ret = clk->ops->enable(clk);
- if (ret) {
- WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
-@@ -349,8 +353,10 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
+ if (clk->ops && clk->ops->enable) {
++ trace_clock_enable(clk->name, 1, smp_processor_id());
+ ret = clk->ops->enable(clk);
+ if (ret) {
+ WARN(1, "clock: %s: could not enable: %d\n",
+@@ -353,8 +358,10 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
@@ -67,7 +74,7 @@ index 2a2f152..72af75d 100644
return ret;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
-index 6ade4ea..fd60820 100644
+index abc551e..bab0343 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
@@ -78,7 +85,7 @@ index 6ade4ea..fd60820 100644
#include <plat/sram.h>
#include "clockdomain.h"
-@@ -519,8 +520,14 @@ static void omap3_pm_idle(void)
+@@ -514,8 +515,14 @@ static void omap3_pm_idle(void)
if (omap_irq_pending() || need_resched())
goto out;
@@ -94,7 +101,7 @@ index 6ade4ea..fd60820 100644
local_fiq_enable();
local_irq_enable();
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
-index eaed0df..e1feb50 100644
+index a11be81..49c6513 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,12 +19,15 @@
@@ -113,14 +120,53 @@ index eaed0df..e1feb50 100644
#include <plat/cpu.h>
#include "powerdomain.h"
#include "clockdomain.h"
-@@ -406,8 +409,11 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+@@ -32,6 +35,8 @@
+
+ #include "pm.h"
+
++#define PWRDM_TRACE_STATES_FLAG (1<<31)
++
+ enum {
+ PWRDM_STATE_NOW = 0,
+ PWRDM_STATE_PREV,
+@@ -130,8 +135,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
+ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
+ {
+
+- int prev;
+- int state;
++ int prev, state, trace_state = 0;
+
+ if (pwrdm == NULL)
+ return -EINVAL;
+@@ -148,6 +152,17 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
+ pwrdm->state_counter[prev]++;
+ if (prev == PWRDM_POWER_RET)
+ _update_logic_membank_counters(pwrdm);
++ /*
++ * If the power domain did not hit the desired state,
++ * generate a trace event with both the desired and hit states
++ */
++ if (state != prev) {
++ trace_state = (PWRDM_TRACE_STATES_FLAG |
++ ((state & OMAP_POWERSTATE_MASK) << 8) |
++ ((prev & OMAP_POWERSTATE_MASK) << 0));
++ trace_power_domain_target(pwrdm->name, trace_state,
++ smp_processor_id());
++ }
+ break;
+ default:
+ return -EINVAL;
+@@ -406,8 +421,13 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
pwrdm->name, pwrst);
- if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst)
+ if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
++ /* Trace the pwrdm desired target state */
+ trace_power_domain_target(pwrdm->name, pwrst,
+ smp_processor_id());
++ /* Program the pwrdm desired target state */
ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
+ }
diff --git a/patches/for_next/0245-omap2-Add-separate-list-for-dynamic-pads-to-mux.patch b/patches/for_next/0245-omap2-Add-separate-list-for-dynamic-pads-to-mux.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e4994c4087e3c4c13b406fe06666724d61e1f755
--- /dev/null
+++ b/patches/for_next/0245-omap2-Add-separate-list-for-dynamic-pads-to-mux.patch
@@ -0,0 +1,214 @@
+From d414f2ec046e7df60e6a99b08b6ef74180a0e457 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Fri, 11 Mar 2011 11:32:25 -0800
+Subject: [PATCH 245/254] omap2+: Add separate list for dynamic pads to mux
+
+This avoids going through the list unnecessarily when
+idling devices for runtime PM.
+
+Based on an earlier patch by sricharan <r.sricharan@ti.com>.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/mux.c | 88 ++++++++++++++++++++++----
+ arch/arm/mach-omap2/mux.h | 2 +-
+ arch/arm/mach-omap2/omap_hwmod.c | 6 +-
+ arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 +
+ 4 files changed, 83 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
+index 6c84659..8717370 100644
+--- a/arch/arm/mach-omap2/mux.c
++++ b/arch/arm/mach-omap2/mux.c
+@@ -258,7 +258,7 @@ struct omap_hwmod_mux_info * __init
+ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
+ {
+ struct omap_hwmod_mux_info *hmux;
+- int i;
++ int i, nr_pads_dynamic = 0;
+
+ if (!bpads || nr_pads < 1)
+ return NULL;
+@@ -302,9 +302,40 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
+ pad->enable = bpad->enable;
+ pad->idle = bpad->idle;
+ pad->off = bpad->off;
++
++ if (pad->flags & OMAP_DEVICE_PAD_REMUX)
++ nr_pads_dynamic++;
++
+ pr_debug("%s: Initialized %s\n", __func__, pad->name);
+ }
+
++ if (!nr_pads_dynamic)
++ return hmux;
++
++ /*
++ * Add pads that need dynamic muxing into a separate list
++ */
++
++ hmux->nr_pads_dynamic = nr_pads_dynamic;
++ hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
++ nr_pads_dynamic, GFP_KERNEL);
++ if (!hmux->pads_dynamic) {
++ pr_err("%s: Could not allocate dynamic pads\n", __func__);
++ return hmux;
++ }
++
++ nr_pads_dynamic = 0;
++ for (i = 0; i < hmux->nr_pads; i++) {
++ struct omap_device_pad *pad = &hmux->pads[i];
++
++ if (pad->flags & OMAP_DEVICE_PAD_REMUX) {
++ pr_debug("%s: pad %s tagged dynamic\n",
++ __func__, pad->name);
++ hmux->pads_dynamic[nr_pads_dynamic] = pad;
++ nr_pads_dynamic++;
++ }
++ }
++
+ return hmux;
+
+ err3:
+@@ -322,6 +353,44 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ {
+ int i;
+
++ /* Runtime idling of dynamic pads */
++ if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
++ for (i = 0; i < hmux->nr_pads_dynamic; i++) {
++ struct omap_device_pad *pad = hmux->pads_dynamic[i];
++ int val = -EINVAL;
++
++ pad->flags |= OMAP_DEVICE_PAD_IDLE;
++ val = pad->idle;
++ omap_mux_write(pad->partition, val,
++ pad->mux->reg_offset);
++ }
++
++ return;
++ }
++
++ /* Runtime enabling of dynamic pads */
++ if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic) {
++ int idled = 0;
++
++ for (i = 0; i < hmux->nr_pads_dynamic; i++) {
++ struct omap_device_pad *pad = hmux->pads_dynamic[i];
++ int val = -EINVAL;
++
++ if (!(pad->flags & OMAP_DEVICE_PAD_IDLE))
++ continue;
++
++ pad->flags &= ~OMAP_DEVICE_PAD_IDLE;
++ val = pad->enable;
++ omap_mux_write(pad->partition, val,
++ pad->mux->reg_offset);
++ idled++;
++ }
++
++ if (idled)
++ return;
++ }
++
++ /* Enabling or disabling of all pads */
+ for (i = 0; i < hmux->nr_pads; i++) {
+ struct omap_device_pad *pad = &hmux->pads[i];
+ int flags, val = -EINVAL;
+@@ -330,21 +399,10 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+
+ switch (state) {
+ case _HWMOD_STATE_ENABLED:
+- if (flags & OMAP_DEVICE_PAD_ENABLED)
+- break;
+- flags |= OMAP_DEVICE_PAD_ENABLED;
+ val = pad->enable;
+ pr_debug("%s: Enabling %s %x\n", __func__,
+ pad->name, val);
+ break;
+- case _HWMOD_STATE_IDLE:
+- if (!(flags & OMAP_DEVICE_PAD_REMUX))
+- break;
+- flags &= ~OMAP_DEVICE_PAD_ENABLED;
+- val = pad->idle;
+- pr_debug("%s: Idling %s %x\n", __func__,
+- pad->name, val);
+- break;
+ case _HWMOD_STATE_DISABLED:
+ default:
+ /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
+@@ -352,7 +410,6 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ val = pad->off;
+ else
+ val = OMAP_MUX_MODE7;
+- flags &= ~OMAP_DEVICE_PAD_ENABLED;
+ pr_debug("%s: Disabling %s %x\n", __func__,
+ pad->name, val);
+ };
+@@ -363,6 +420,11 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ pad->flags = flags;
+ }
+ }
++
++ if (state == _HWMOD_STATE_ENABLED)
++ hmux->enabled = true;
++ else
++ hmux->enabled = false;
+ }
+
+ #ifdef CONFIG_DEBUG_FS
+diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
+index a4ab17a..1d5bf42 100644
+--- a/arch/arm/mach-omap2/mux.h
++++ b/arch/arm/mach-omap2/mux.h
+@@ -159,7 +159,7 @@ struct omap_board_mux {
+ u16 value;
+ };
+
+-#define OMAP_DEVICE_PAD_ENABLED BIT(7) /* Not needed for board-*.c */
++#define OMAP_DEVICE_PAD_IDLE BIT(7) /* Not needed for board-*.c */
+ #define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad,
+ needs enable, idle and off
+ values */
+diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
+index 4c8329e..e034294 100644
+--- a/arch/arm/mach-omap2/omap_hwmod.c
++++ b/arch/arm/mach-omap2/omap_hwmod.c
+@@ -1244,7 +1244,9 @@ static int _enable(struct omap_hwmod *oh)
+ _deassert_hardreset(oh, oh->rst_lines[0].name);
+
+ /* Mux pins for device runtime if populated */
+- if (oh->mux)
++ if (oh->mux && (!oh->mux->enabled ||
++ ((oh->_state == _HWMOD_STATE_IDLE) &&
++ oh->mux->pads_dynamic)))
+ omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+
+ _add_initiator_dep(oh, mpu_oh);
+@@ -1293,7 +1295,7 @@ static int _idle(struct omap_hwmod *oh)
+ _disable_clocks(oh);
+
+ /* Mux pins for device idle if populated */
+- if (oh->mux)
++ if (oh->mux && oh->mux->pads_dynamic)
+ omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+
+ oh->_state = _HWMOD_STATE_IDLE;
+diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+index d1bc1f3..aef7081 100644
+--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
++++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
+@@ -90,6 +90,9 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+ struct omap_hwmod_mux_info {
+ int nr_pads;
+ struct omap_device_pad *pads;
++ int nr_pads_dynamic;
++ struct omap_device_pad **pads_dynamic;
++ bool enabled;
+ };
+
+ /**
+--
+1.7.1
+
diff --git a/patches/for_next/0246-omap2-mux-Remove-the-use-of-IDLE-flag.patch b/patches/for_next/0246-omap2-mux-Remove-the-use-of-IDLE-flag.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5e36a9aff930665806dee2591a695b4e1706b7ad
--- /dev/null
+++ b/patches/for_next/0246-omap2-mux-Remove-the-use-of-IDLE-flag.patch
@@ -0,0 +1,93 @@
+From 2107252efb69fbd1ad71b074286f602c72642889 Mon Sep 17 00:00:00 2001
+From: R Sricharan <r.sricharan@ti.com>
+Date: Fri, 11 Mar 2011 11:32:25 -0800
+Subject: [PATCH 246/254] omap2+: mux: Remove the use of IDLE flag
+
+Currently OMAP_DEVICE_PAD_IDLE flag is used to mux pins
+dynamically. This can be simplified by using the enabled
+state variable of each pad. This also fixes the issue of
+the static pads not getting muxed after idling and
+disable/enable state transitions.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/mux.c | 19 +++++++------------
+ arch/arm/mach-omap2/mux.h | 1 -
+ 2 files changed, 7 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
+index 8717370..bb043cb 100644
+--- a/arch/arm/mach-omap2/mux.c
++++ b/arch/arm/mach-omap2/mux.c
+@@ -359,7 +359,6 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ struct omap_device_pad *pad = hmux->pads_dynamic[i];
+ int val = -EINVAL;
+
+- pad->flags |= OMAP_DEVICE_PAD_IDLE;
+ val = pad->idle;
+ omap_mux_write(pad->partition, val,
+ pad->mux->reg_offset);
+@@ -369,25 +368,18 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ }
+
+ /* Runtime enabling of dynamic pads */
+- if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic) {
+- int idled = 0;
+-
++ if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
++ && hmux->enabled) {
+ for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+ struct omap_device_pad *pad = hmux->pads_dynamic[i];
+ int val = -EINVAL;
+
+- if (!(pad->flags & OMAP_DEVICE_PAD_IDLE))
+- continue;
+-
+- pad->flags &= ~OMAP_DEVICE_PAD_IDLE;
+ val = pad->enable;
+ omap_mux_write(pad->partition, val,
+ pad->mux->reg_offset);
+- idled++;
+ }
+
+- if (idled)
+- return;
++ return;
+ }
+
+ /* Enabling or disabling of all pads */
+@@ -404,7 +396,6 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ pad->name, val);
+ break;
+ case _HWMOD_STATE_DISABLED:
+- default:
+ /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
+ if (flags & OMAP_DEVICE_PAD_REMUX)
+ val = pad->off;
+@@ -412,6 +403,10 @@ void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+ val = OMAP_MUX_MODE7;
+ pr_debug("%s: Disabling %s %x\n", __func__,
+ pad->name, val);
++ break;
++ default:
++ /* Nothing to be done */
++ break;
+ };
+
+ if (val >= 0) {
+diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
+index 1d5bf42..8920fa4 100644
+--- a/arch/arm/mach-omap2/mux.h
++++ b/arch/arm/mach-omap2/mux.h
+@@ -159,7 +159,6 @@ struct omap_board_mux {
+ u16 value;
+ };
+
+-#define OMAP_DEVICE_PAD_IDLE BIT(7) /* Not needed for board-*.c */
+ #define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad,
+ needs enable, idle and off
+ values */
+--
+1.7.1
+
diff --git a/patches/for_next/0247-omap2-mux-Add-macro-for-configuring-static-with-omap.patch b/patches/for_next/0247-omap2-mux-Add-macro-for-configuring-static-with-omap.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f41d948a9578e6814b93a85d80dc98d57ffe6a17
--- /dev/null
+++ b/patches/for_next/0247-omap2-mux-Add-macro-for-configuring-static-with-omap.patch
@@ -0,0 +1,36 @@
+From 86b3afede3b01eeecbca9978774403a426c2e96e Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Fri, 11 Mar 2011 11:32:26 -0800
+Subject: [PATCH 247/254] omap2+: mux: Add macro for configuring static with omap_hwmod_mux_init
+
+Add macro for defining static pins in the board file.
+
+We can now start implementing pin multiplexing in the platform init
+code for devices that call omap_hwmod_mux_init. Currently that is
+only implemented for serial.c.
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/mux.h | 6 ++++++
+ 1 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
+index 8920fa4..137f321 100644
+--- a/arch/arm/mach-omap2/mux.h
++++ b/arch/arm/mach-omap2/mux.h
+@@ -186,6 +186,12 @@ struct omap_device_pad {
+
+ struct omap_hwmod_mux_info;
+
++#define OMAP_MUX_STATIC(signal, mode) \
++{ \
++ .name = (signal), \
++ .enable = (mode), \
++}
++
+ #if defined(CONFIG_OMAP_MUX)
+
+ /**
+--
+1.7.1
+
diff --git a/patches/for_next/0248-omap4-board-4430sdp-Initialise-the-serial-pads.patch b/patches/for_next/0248-omap4-board-4430sdp-Initialise-the-serial-pads.patch
new file mode 100644
index 0000000000000000000000000000000000000000..eb3b84e8a2a700a4ca882f18d9208b928f0a52d0
--- /dev/null
+++ b/patches/for_next/0248-omap4-board-4430sdp-Initialise-the-serial-pads.patch
@@ -0,0 +1,107 @@
+From f3314d793b0c91202b7c3068af6333643a23ccfc Mon Sep 17 00:00:00 2001
+From: R Sricharan <r.sricharan@ti.com>
+Date: Fri, 11 Mar 2011 06:04:44 +0000
+Subject: [PATCH 248/254] omap4: board-4430sdp: Initialise the serial pads
+
+Use the mux framework to initialise the serial pads.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-4430sdp.c | 71 ++++++++++++++++++++++++++++++++++-
+ 1 files changed, 69 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
+index 85805d4..670cbd5 100644
+--- a/arch/arm/mach-omap2/board-4430sdp.c
++++ b/arch/arm/mach-omap2/board-4430sdp.c
+@@ -625,9 +625,76 @@ static struct omap_board_mux board_mux[] __initdata = {
+ OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
++
++static struct omap_device_pad serial2_pads[] __initdata = {
++ OMAP_MUX_STATIC("uart2_cts.uart2_cts",
++ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_rts.uart2_rts",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_rx.uart2_rx",
++ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_tx.uart2_tx",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++};
++
++static struct omap_device_pad serial3_pads[] __initdata = {
++ OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
++ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
++ OMAP_PIN_INPUT | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++};
++
++static struct omap_device_pad serial4_pads[] __initdata = {
++ OMAP_MUX_STATIC("uart4_rx.uart4_rx",
++ OMAP_PIN_INPUT | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart4_tx.uart4_tx",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++};
++
++static struct omap_board_data serial2_data = {
++ .id = 1,
++ .pads = serial2_pads,
++ .pads_cnt = ARRAY_SIZE(serial2_pads),
++};
++
++static struct omap_board_data serial3_data = {
++ .id = 2,
++ .pads = serial3_pads,
++ .pads_cnt = ARRAY_SIZE(serial3_pads),
++};
++
++static struct omap_board_data serial4_data = {
++ .id = 3,
++ .pads = serial4_pads,
++ .pads_cnt = ARRAY_SIZE(serial4_pads),
++};
++
++static inline void board_serial_init(void)
++{
++ struct omap_board_data bdata;
++ bdata.flags = 0;
++ bdata.pads = NULL;
++ bdata.pads_cnt = 0;
++ bdata.id = 0;
++ /* pass dummy data for UART1 */
++ omap_serial_init_port(&bdata);
++
++ omap_serial_init_port(&serial2_data);
++ omap_serial_init_port(&serial3_data);
++ omap_serial_init_port(&serial4_data);
++}
+ #else
+ #define board_mux NULL
+-#endif
++
++static inline void board_serial_init(void)
++{
++ omap_serial_init();
++}
++ #endif
+
+ static void __init omap_4430sdp_init(void)
+ {
+@@ -644,7 +711,7 @@ static void __init omap_4430sdp_init(void)
+ omap4_i2c_init();
+ omap_sfh7741prox_init();
+ platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
+- omap_serial_init();
++ board_serial_init();
+ omap4_twl6030_hsmmc_init(mmc);
+
+ usb_musb_init(&musb_board_data);
+--
+1.7.1
+
diff --git a/patches/for_next/0249-omap3-board-3430sdp-Initialise-the-serial-pads.patch b/patches/for_next/0249-omap3-board-3430sdp-Initialise-the-serial-pads.patch
new file mode 100644
index 0000000000000000000000000000000000000000..85afee9742b7425439895db06f476d081d0b5c38
--- /dev/null
+++ b/patches/for_next/0249-omap3-board-3430sdp-Initialise-the-serial-pads.patch
@@ -0,0 +1,136 @@
+From e6a939fb71fc0064d0d271e48ea1399806fd7c54 Mon Sep 17 00:00:00 2001
+From: R Sricharan <r.sricharan@ti.com>
+Date: Fri, 11 Mar 2011 06:04:45 +0000
+Subject: [PATCH 249/254] omap3: board-3430sdp: Initialise the serial pads
+
+Use the mux framework to initialise the serial pads.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-3430sdp.c | 102 ++++++++++++++++++++++++++++++++++-
+ 1 files changed, 101 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
+index 85c0b5c..5f33ed4 100644
+--- a/arch/arm/mach-omap2/board-3430sdp.c
++++ b/arch/arm/mach-omap2/board-3430sdp.c
+@@ -657,6 +657,106 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+ static struct omap_board_mux board_mux[] __initdata = {
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
++
++static struct omap_device_pad serial1_pads[] __initdata = {
++ /*
++ * Note that off output enable is an active low
++ * signal. So setting this means pin is a
++ * input enabled in off mode
++ */
++ OMAP_MUX_STATIC("uart1_cts.uart1_cts",
++ OMAP_PIN_INPUT |
++ OMAP_PIN_OFF_INPUT_PULLDOWN |
++ OMAP_OFFOUT_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart1_rts.uart1_rts",
++ OMAP_PIN_OUTPUT |
++ OMAP_OFF_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart1_rx.uart1_rx",
++ OMAP_PIN_INPUT |
++ OMAP_PIN_OFF_INPUT_PULLDOWN |
++ OMAP_OFFOUT_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart1_tx.uart1_tx",
++ OMAP_PIN_OUTPUT |
++ OMAP_OFF_EN |
++ OMAP_MUX_MODE0),
++};
++
++static struct omap_device_pad serial2_pads[] __initdata = {
++ OMAP_MUX_STATIC("uart2_cts.uart2_cts",
++ OMAP_PIN_INPUT_PULLUP |
++ OMAP_PIN_OFF_INPUT_PULLDOWN |
++ OMAP_OFFOUT_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_rts.uart2_rts",
++ OMAP_PIN_OUTPUT |
++ OMAP_OFF_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_rx.uart2_rx",
++ OMAP_PIN_INPUT |
++ OMAP_PIN_OFF_INPUT_PULLDOWN |
++ OMAP_OFFOUT_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_tx.uart2_tx",
++ OMAP_PIN_OUTPUT |
++ OMAP_OFF_EN |
++ OMAP_MUX_MODE0),
++};
++
++static struct omap_device_pad serial3_pads[] __initdata = {
++ OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
++ OMAP_PIN_INPUT_PULLDOWN |
++ OMAP_PIN_OFF_INPUT_PULLDOWN |
++ OMAP_OFFOUT_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
++ OMAP_PIN_OUTPUT |
++ OMAP_OFF_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
++ OMAP_PIN_INPUT |
++ OMAP_PIN_OFF_INPUT_PULLDOWN |
++ OMAP_OFFOUT_EN |
++ OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
++ OMAP_PIN_OUTPUT |
++ OMAP_OFF_EN |
++ OMAP_MUX_MODE0),
++};
++
++static struct omap_board_data serial1_data = {
++ .id = 0,
++ .pads = serial1_pads,
++ .pads_cnt = ARRAY_SIZE(serial1_pads),
++};
++
++static struct omap_board_data serial2_data = {
++ .id = 1,
++ .pads = serial2_pads,
++ .pads_cnt = ARRAY_SIZE(serial2_pads),
++};
++
++static struct omap_board_data serial3_data = {
++ .id = 2,
++ .pads = serial3_pads,
++ .pads_cnt = ARRAY_SIZE(serial3_pads),
++};
++
++static inline void board_serial_init(void)
++{
++ omap_serial_init_port(&serial1_data);
++ omap_serial_init_port(&serial2_data);
++ omap_serial_init_port(&serial3_data);
++}
++#else
++#define board_mux NULL
++
++static inline void board_serial_init(void)
++{
++ omap_serial_init();
++}
+ #endif
+
+ /*
+@@ -801,7 +901,7 @@ static void __init omap_3430sdp_init(void)
+ spi_register_board_info(sdp3430_spi_board_info,
+ ARRAY_SIZE(sdp3430_spi_board_info));
+ ads7846_dev_init();
+- omap_serial_init();
++ board_serial_init();
+ usb_musb_init(&musb_board_data);
+ board_smc91x_init();
+ board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
+--
+1.7.1
+
diff --git a/patches/for_next/0250-omap4-board-omap4panda-Initialise-the-serial-pads.patch b/patches/for_next/0250-omap4-board-omap4panda-Initialise-the-serial-pads.patch
new file mode 100644
index 0000000000000000000000000000000000000000..cc11cf63ad8e259deb43ecaab8de23a6bc9cf324
--- /dev/null
+++ b/patches/for_next/0250-omap4-board-omap4panda-Initialise-the-serial-pads.patch
@@ -0,0 +1,105 @@
+From c215a37dfbdf8a158db20d5e696336246da9485c Mon Sep 17 00:00:00 2001
+From: R Sricharan <r.sricharan@ti.com>
+Date: Fri, 11 Mar 2011 06:04:46 +0000
+Subject: [PATCH 250/254] omap4: board-omap4panda: Initialise the serial pads
+
+Use the mux framework to initialise the serial pads.
+
+Signed-off-by: sricharan <r.sricharan@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-omap4panda.c | 69 +++++++++++++++++++++++++++++++-
+ 1 files changed, 68 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
+index a94ce07..1dd4401 100644
+--- a/arch/arm/mach-omap2/board-omap4panda.c
++++ b/arch/arm/mach-omap2/board-omap4panda.c
+@@ -463,8 +463,75 @@ static struct omap_board_mux board_mux[] __initdata = {
+ OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
++
++static struct omap_device_pad serial2_pads[] __initdata = {
++ OMAP_MUX_STATIC("uart2_cts.uart2_cts",
++ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_rts.uart2_rts",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_rx.uart2_rx",
++ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart2_tx.uart2_tx",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++};
++
++static struct omap_device_pad serial3_pads[] __initdata = {
++ OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
++ OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
++ OMAP_PIN_INPUT | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++};
++
++static struct omap_device_pad serial4_pads[] __initdata = {
++ OMAP_MUX_STATIC("uart4_rx.uart4_rx",
++ OMAP_PIN_INPUT | OMAP_MUX_MODE0),
++ OMAP_MUX_STATIC("uart4_tx.uart4_tx",
++ OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
++};
++
++static struct omap_board_data serial2_data = {
++ .id = 1,
++ .pads = serial2_pads,
++ .pads_cnt = ARRAY_SIZE(serial2_pads),
++};
++
++static struct omap_board_data serial3_data = {
++ .id = 2,
++ .pads = serial3_pads,
++ .pads_cnt = ARRAY_SIZE(serial3_pads),
++};
++
++static struct omap_board_data serial4_data = {
++ .id = 3,
++ .pads = serial4_pads,
++ .pads_cnt = ARRAY_SIZE(serial4_pads),
++};
++
++static inline void board_serial_init(void)
++{
++ struct omap_board_data bdata;
++ bdata.flags = 0;
++ bdata.pads = NULL;
++ bdata.pads_cnt = 0;
++ bdata.id = 0;
++ /* pass dummy data for UART1 */
++ omap_serial_init_port(&bdata);
++
++ omap_serial_init_port(&serial2_data);
++ omap_serial_init_port(&serial3_data);
++ omap_serial_init_port(&serial4_data);
++}
+ #else
+ #define board_mux NULL
++
++static inline void board_serial_init(void)
++{
++ omap_serial_init();
++}
+ #endif
+
+ static void __init omap4_panda_init(void)
+@@ -481,7 +548,7 @@ static void __init omap4_panda_init(void)
+ omap4_panda_i2c_init();
+ platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
+ platform_device_register(&omap_vwlan_device);
+- omap_serial_init();
++ board_serial_init();
+ omap4_twl6030_hsmmc_init(mmc);
+ omap4_ehci_init();
+ usb_musb_init(&musb_board_data);
+--
+1.7.1
+
diff --git a/patches/for_next/0251-omap2-mux-Fix-compile-when-CONFIG_OMAP_MUX-is-not-se.patch b/patches/for_next/0251-omap2-mux-Fix-compile-when-CONFIG_OMAP_MUX-is-not-se.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9e6a7db9a92c3c713ab61f3dd6fb35e68652942b
--- /dev/null
+++ b/patches/for_next/0251-omap2-mux-Fix-compile-when-CONFIG_OMAP_MUX-is-not-se.patch
@@ -0,0 +1,77 @@
+From 8bef3e4aff47b66f100dc4be01a8b4e17e4c1d11 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Fri, 11 Mar 2011 11:39:51 -0800
+Subject: [PATCH 251/254] omap2+: mux: Fix compile when CONFIG_OMAP_MUX is not selected
+
+Fix compile when CONFIG_OMAP_MUX is not selected
+
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/board-cm-t35.c | 2 ++
+ arch/arm/mach-omap2/board-cm-t3517.c | 2 ++
+ arch/arm/mach-omap2/board-devkit8000.c | 2 ++
+ 3 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
+index 27bea54..71545c9 100644
+--- a/arch/arm/mach-omap2/board-cm-t35.c
++++ b/arch/arm/mach-omap2/board-cm-t35.c
+@@ -675,6 +675,7 @@ static void __init cm_t35_init_early(void)
+ mt46h32m32lf6_sdrc_params);
+ }
+
++#ifdef CONFIG_OMAP_MUX
+ static struct omap_board_mux board_mux[] __initdata = {
+ /* nCS and IRQ for CM-T35 ethernet */
+ OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
+@@ -772,6 +773,7 @@ static struct omap_board_mux board_mux[] __initdata = {
+
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
++#endif
+
+ static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
+index 9da6e82..4c737e4 100644
+--- a/arch/arm/mach-omap2/board-cm-t3517.c
++++ b/arch/arm/mach-omap2/board-cm-t3517.c
+@@ -260,6 +260,7 @@ static void __init cm_t3517_init_early(void)
+ omap2_init_common_devices(NULL, NULL);
+ }
+
++#ifdef CONFIG_OMAP_MUX
+ static struct omap_board_mux board_mux[] __initdata = {
+ /* GPIO186 - Green LED */
+ OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+@@ -285,6 +286,7 @@ static struct omap_board_mux board_mux[] __initdata = {
+
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
++#endif
+
+ static void __init cm_t3517_init(void)
+ {
+diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
+index 728f27c..472a25b 100644
+--- a/arch/arm/mach-omap2/board-devkit8000.c
++++ b/arch/arm/mach-omap2/board-devkit8000.c
+@@ -625,6 +625,7 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+ .reset_gpio_port[2] = -EINVAL
+ };
+
++#ifdef CONFIG_OMAP_MUX
+ static struct omap_board_mux board_mux[] __initdata = {
+ /* nCS and IRQ for Devkit8000 ethernet */
+ OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE0),
+@@ -778,6 +779,7 @@ static struct omap_board_mux board_mux[] __initdata = {
+
+ { .reg_offset = OMAP_MUX_TERMINATOR },
+ };
++#endif
+
+ static void __init devkit8000_init(void)
+ {
+--
+1.7.1
+
diff --git a/patches/for_next/0252-omap4-mux-Remove-duplicate-mux-modes.patch b/patches/for_next/0252-omap4-mux-Remove-duplicate-mux-modes.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f0abdf2d8a771f95e543a5295d4498afef57b543
--- /dev/null
+++ b/patches/for_next/0252-omap4-mux-Remove-duplicate-mux-modes.patch
@@ -0,0 +1,397 @@
+From 9c3f69500b304caf39fd17f290f135469b3442b8 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Fri, 11 Mar 2011 11:55:34 -0800
+Subject: [PATCH 252/254] omap4: mux: Remove duplicate mux modes
+
+Remove duplicate mux modes to make the binary smaller:
+
+text data bss dec hex filename
+9378 24472 0 33850 843a mux44xx.o
+9378 19104 0 28482 6f42 mux44xx.o
+
+Cc: Benoit Cousson <b-cousson@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/mach-omap2/mux44xx.c | 282 +----------------------------------------
+ 1 files changed, 6 insertions(+), 276 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
+index c322e7b..9a66445 100644
+--- a/arch/arm/mach-omap2/mux44xx.c
++++ b/arch/arm/mach-omap2/mux44xx.c
+@@ -755,25 +755,9 @@ static struct omap_ball __initdata omap4_core_cbl_ball[] = {
+ #endif
+
+ /*
+- * Superset of all mux modes for omap4 ES2.0
++ * Signals different on ES2.0 compared to superset
+ */
+-static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+- _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
+- NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
+- NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
+- NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
+- NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
+- "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
+- "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
+- "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
+- "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
++static struct omap_mux __initdata omap4_es2_core_subset[] = {
+ _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+ "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+@@ -792,52 +776,15 @@ static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+ "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
+- "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
+- "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
+- "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
+- "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
+- "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
+- "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
+- "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
+ "gpio_48", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
+- "gpio_49", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
+- "sys_ndmareq0", NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
+- "gpio_51", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
+ "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
+ "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
+- "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+- "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
+- "sys_ndmareq1", NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+ "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
+ _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+ "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
+- NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
+- NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
+- "gpio_59", NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
+- "gpio_60", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
+- "gpio_61", NULL, NULL, NULL, NULL),
+- _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
+- "gpio_62", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
+ "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+ NULL, "safe_mode"),
+@@ -851,62 +798,6 @@ static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
+ "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+ "safe_mode"),
+- _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
+- "gpio_65", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
+- "gpio_66", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
+- "gpio_83", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
+- "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
+- NULL, "hw_dbg20", "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
+- "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
+- "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
+- "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
+- "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
+- "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
+- "hsi1_acready", "mcbsp4_fsx", "gpio_87",
+- "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
+- "safe_mode"),
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+ "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+ "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
+@@ -922,84 +813,6 @@ static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+ "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+ "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
+- "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
+- "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
+- "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
+- "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
+- "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
+- "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
+- "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
+- "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
+- "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
+- "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
+- "gpio_96", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
+- NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
+- "gpio_98", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
+- "gpio_99", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
+- "gpio_100", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
+- "gpio_101", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
+- "gpio_102", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
+- "gpio_103", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
+- "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
+- "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
+- "gpio_106", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
+- "gpio_107", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
+- "gpio_108", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
+- "gpio_109", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
+- "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
+- "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
+- NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
+- "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
+- NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
+- "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
+- NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
+- "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+- NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
+- "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+- NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
+- "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
+- "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
+- "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
+- "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
+- "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+- "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
+- "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+- "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
+- NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
+- NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
+- NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+ "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
+ "safe_mode"),
+@@ -1012,58 +825,6 @@ static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+ "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
+ NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
+- "gpio_123", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
+- "gpio_124", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
+- "gpio_125", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
+- "gpio_126", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
+- "gpio_127", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
+- NULL, NULL),
+- _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
+- NULL, NULL),
+- _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
+- "gpio_128", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
+- "gpio_129", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
+- "gpio_135", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
+- "gpio_136", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
+- "gpio_138", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
+- "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
+- "safe_mode"),
+- _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
+- "slimbus2_data", "gpio_140", NULL, NULL, NULL,
+- "safe_mode"),
+- _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
+- NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
+- "gpio_142", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
+- "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+- NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
+- "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+- NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+ "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
+ NULL, "safe_mode"),
+@@ -1096,9 +857,6 @@ static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ "gpio_155", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
+ "gpio_156", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
+- "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
+- "hsi2_cawake", NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+ "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+ "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
+@@ -1140,10 +898,6 @@ static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+ "mcspi3_clk", "dispc2_data11", "rfbi_data11",
+ "safe_mode"),
+- _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
+- "gpio_169", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
+- NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
+ "gpio_171", NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
+@@ -1168,36 +922,10 @@ static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+ NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
+ NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
+- NULL, NULL, NULL, NULL),
+ _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
+ "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
+ _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
+ "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
+- "gpio_181", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
+- "gpio_182", NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
+- NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
+- NULL, NULL, NULL, "safe_mode"),
+- _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
+- NULL, "hw_dbg0", "safe_mode"),
+- _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
+- NULL, "hw_dbg1", "safe_mode"),
+ _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+ "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
+ "safe_mode"),
+@@ -1586,6 +1314,7 @@ int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
+ struct omap_ball *package_balls_core;
+ struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
+ struct omap_mux *core_muxmodes;
++ struct omap_mux *core_subset = NULL;
+ int ret;
+
+ switch (flags & OMAP_PACKAGE_MASK) {
+@@ -1597,7 +1326,8 @@ int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
+ case OMAP_PACKAGE_CBS:
+ pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
+ package_balls_core = omap4_core_cbs_ball;
+- core_muxmodes = omap4_es2_core_muxmodes;
++ core_muxmodes = omap4_core_muxmodes;
++ core_subset = omap4_es2_core_subset;
+ break;
+ default:
+ pr_err("%s: Unknown omap package, mux disabled\n", __func__);
+@@ -1608,7 +1338,7 @@ int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
+ OMAP_MUX_GPIO_IN_MODE3,
+ OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
+ OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
+- core_muxmodes, NULL, board_subset,
++ core_muxmodes, core_subset, board_subset,
+ package_balls_core);
+ if (ret)
+ return ret;
+--
+1.7.1
+
diff --git a/patches/for_next/0253-omap-iovmm-disallow-mapping-NULL-address-when-IOVMF_.patch b/patches/for_next/0253-omap-iovmm-disallow-mapping-NULL-address-when-IOVMF_.patch
new file mode 100644
index 0000000000000000000000000000000000000000..beeb092a5f746d8e52d7536394199393698a8097
--- /dev/null
+++ b/patches/for_next/0253-omap-iovmm-disallow-mapping-NULL-address-when-IOVMF_.patch
@@ -0,0 +1,59 @@
+From ccefeaea254027c33b977a9f94e8e872de829985 Mon Sep 17 00:00:00 2001
+From: Michael Jones <michael.jones@matrix-vision.de>
+Date: Wed, 9 Mar 2011 09:17:32 +0000
+Subject: [PATCH 253/254] omap: iovmm: disallow mapping NULL address when IOVMF_DA_ANON is set
+
+commit c7f4ab26e3bcdaeb3e19ec658e3ad9092f1a6ceb allowed mapping the NULL
+address if da_start==0, which would then not get unmapped. Disallow
+this again if IOVMF_DA_ANON is set. And spell variable 'alignment'
+correctly.
+
+Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/iovmm.c | 13 +++++++------
+ 1 files changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
+index 6dc1296..ea7eab9 100644
+--- a/arch/arm/plat-omap/iovmm.c
++++ b/arch/arm/plat-omap/iovmm.c
+@@ -271,20 +271,21 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
+ size_t bytes, u32 flags)
+ {
+ struct iovm_struct *new, *tmp;
+- u32 start, prev_end, alignement;
++ u32 start, prev_end, alignment;
+
+ if (!obj || !bytes)
+ return ERR_PTR(-EINVAL);
+
+ start = da;
+- alignement = PAGE_SIZE;
++ alignment = PAGE_SIZE;
+
+ if (flags & IOVMF_DA_ANON) {
+- start = obj->da_start;
++ /* Don't map address 0 */
++ start = obj->da_start ? obj->da_start : alignment;
+
+ if (flags & IOVMF_LINEAR)
+- alignement = iopgsz_max(bytes);
+- start = roundup(start, alignement);
++ alignment = iopgsz_max(bytes);
++ start = roundup(start, alignment);
+ } else if (start < obj->da_start || start > obj->da_end ||
+ obj->da_end - start < bytes) {
+ return ERR_PTR(-EINVAL);
+@@ -304,7 +305,7 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
+ goto found;
+
+ if (tmp->da_end >= start && flags & IOVMF_DA_ANON)
+- start = roundup(tmp->da_end + 1, alignement);
++ start = roundup(tmp->da_end + 1, alignment);
+
+ prev_end = tmp->da_end;
+ }
+--
+1.7.1
+
diff --git a/patches/for_next/0254-omap-iovmm-don-t-check-da-to-set-IOVMF_DA_FIXED-flag.patch b/patches/for_next/0254-omap-iovmm-don-t-check-da-to-set-IOVMF_DA_FIXED-flag.patch
new file mode 100644
index 0000000000000000000000000000000000000000..7204e4816baf2ae66d9b942f10b195d4582c5758
--- /dev/null
+++ b/patches/for_next/0254-omap-iovmm-don-t-check-da-to-set-IOVMF_DA_FIXED-flag.patch
@@ -0,0 +1,121 @@
+From 333284b5a4f19779aa5769778133f16b60bf1070 Mon Sep 17 00:00:00 2001
+From: David Cohen <dacohen@gmail.com>
+Date: Wed, 9 Mar 2011 09:17:33 +0000
+Subject: [PATCH 254/254] omap: iovmm: don't check 'da' to set IOVMF_DA_FIXED flag
+
+Currently IOVMM driver sets IOVMF_DA_FIXED/IOVMF_DA_ANON flags according
+to input 'da' address when mapping memory:
+da == 0: IOVMF_DA_ANON
+da != 0: IOVMF_DA_FIXED
+
+It prevents IOMMU to map first page with fixed 'da'. To avoid such
+issue, IOVMM will not automatically set IOVMF_DA_FIXED. It should now
+come from the user throught 'flags' parameter when mapping memory.
+As IOVMF_DA_ANON and IOVMF_DA_FIXED are mutually exclusive, IOVMF_DA_ANON
+can be removed. The driver will now check internally if IOVMF_DA_FIXED
+is set or not.
+
+Signed-off-by: David Cohen <dacohen@gmail.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+---
+ arch/arm/plat-omap/include/plat/iovmm.h | 2 --
+ arch/arm/plat-omap/iovmm.c | 14 +++++---------
+ 2 files changed, 5 insertions(+), 11 deletions(-)
+
+diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
+index bdc7ce5..32a2f6c 100644
+--- a/arch/arm/plat-omap/include/plat/iovmm.h
++++ b/arch/arm/plat-omap/include/plat/iovmm.h
+@@ -71,8 +71,6 @@ struct iovm_struct {
+ #define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
+
+ #define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
+-#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
+-#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
+
+
+ extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
+diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
+index ea7eab9..51ef43e 100644
+--- a/arch/arm/plat-omap/iovmm.c
++++ b/arch/arm/plat-omap/iovmm.c
+@@ -279,7 +279,7 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
+ start = da;
+ alignment = PAGE_SIZE;
+
+- if (flags & IOVMF_DA_ANON) {
++ if (~flags & IOVMF_DA_FIXED) {
+ /* Don't map address 0 */
+ start = obj->da_start ? obj->da_start : alignment;
+
+@@ -304,7 +304,7 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
+ if (tmp->da_start > start && (tmp->da_start - start) >= bytes)
+ goto found;
+
+- if (tmp->da_end >= start && flags & IOVMF_DA_ANON)
++ if (tmp->da_end >= start && ~flags & IOVMF_DA_FIXED)
+ start = roundup(tmp->da_end + 1, alignment);
+
+ prev_end = tmp->da_end;
+@@ -651,7 +651,6 @@ u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
+ flags &= IOVMF_HW_MASK;
+ flags |= IOVMF_DISCONT;
+ flags |= IOVMF_MMIO;
+- flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+
+ da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
+ if (IS_ERR_VALUE(da))
+@@ -691,7 +690,7 @@ EXPORT_SYMBOL_GPL(iommu_vunmap);
+ * @flags: iovma and page property
+ *
+ * Allocate @bytes linearly and creates 1-n-1 mapping and returns
+- * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
++ * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set.
+ */
+ u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
+ {
+@@ -710,7 +709,6 @@ u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
+ flags &= IOVMF_HW_MASK;
+ flags |= IOVMF_DISCONT;
+ flags |= IOVMF_ALLOC;
+- flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+
+ sgt = sgtable_alloc(bytes, flags, da, 0);
+ if (IS_ERR(sgt)) {
+@@ -781,7 +779,7 @@ static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va,
+ * @flags: iovma and page property
+ *
+ * Creates 1-1-1 mapping and returns @da again, which can be
+- * adjusted if 'IOVMF_DA_ANON' is set.
++ * adjusted if 'IOVMF_DA_FIXED' is not set.
+ */
+ u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
+ u32 flags)
+@@ -800,7 +798,6 @@ u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
+ flags &= IOVMF_HW_MASK;
+ flags |= IOVMF_LINEAR;
+ flags |= IOVMF_MMIO;
+- flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+
+ da = __iommu_kmap(obj, da, pa, va, bytes, flags);
+ if (IS_ERR_VALUE(da))
+@@ -839,7 +836,7 @@ EXPORT_SYMBOL_GPL(iommu_kunmap);
+ * @flags: iovma and page property
+ *
+ * Allocate @bytes linearly and creates 1-1-1 mapping and returns
+- * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
++ * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set.
+ */
+ u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
+ {
+@@ -859,7 +856,6 @@ u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
+ flags &= IOVMF_HW_MASK;
+ flags |= IOVMF_LINEAR;
+ flags |= IOVMF_ALLOC;
+- flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+
+ da = __iommu_kmap(obj, da, pa, va, bytes, flags);
+ if (IS_ERR_VALUE(da))
+--
+1.7.1
+
diff --git a/patches/no_devtmps-defconfig b/patches/no_devtmps-defconfig
index 5e8fe477f7228401a3e123388249204e6a952ab3..465084f4312e35090ab56474e9ca9b7792325887 100644
--- a/patches/no_devtmps-defconfig
+++ b/patches/no_devtmps-defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux/arm 2.6.38-rc8 Kernel Configuration
-# Tue Mar 8 18:40:21 2011
+# Sat Mar 12 18:54:49 2011
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -299,8 +299,6 @@ CONFIG_ARCH_OMAP2PLUS=y
#
CONFIG_OMAP_SMARTREFLEX=y
CONFIG_OMAP_SMARTREFLEX_CLASS3=y
-CONFIG_OMAP_SMARTREFLEX_CLASS1P5=y
-CONFIG_OMAP_SR_CLASS1P5_RECALIBRATION_DELAY=86400000
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_OMAP_MUX=y
# CONFIG_OMAP_MUX_DEBUG is not set
@@ -322,7 +320,8 @@ CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
# CONFIG_ARCH_OMAP2 is not set
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y
-CONFIG_ARCH_OMAP3430=y
+CONFIG_SOC_OMAP3430=y
+CONFIG_SOC_OMAPTI816X=y
CONFIG_OMAP_PACKAGE_CBB=y
CONFIG_OMAP_PACKAGE_CUS=y
CONFIG_OMAP_PACKAGE_CBP=y
@@ -354,6 +353,7 @@ CONFIG_MACH_IGEP0020=y
CONFIG_MACH_IGEP0030=y
CONFIG_MACH_SBC3530=y
CONFIG_MACH_OMAP_3630SDP=y
+CONFIG_MACH_TI8168EVM=y
CONFIG_MACH_OMAP_4430SDP=y
CONFIG_MACH_OMAP4_PANDA=y
CONFIG_OMAP3_EMU=y
@@ -1256,8 +1256,6 @@ CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_GPIO is not set
CONFIG_MTD_NAND_OMAP2=y
-CONFIG_MTD_NAND_OMAP_PREFETCH=y
-CONFIG_MTD_NAND_OMAP_PREFETCH_DMA=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_DISKONCHIP=m
# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
@@ -3236,6 +3234,7 @@ CONFIG_MACH_OMAP3_WESTBRIDGE_AST_PNAND_HAL=y
# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
CONFIG_OMAP3_SGX=y
CONFIG_CLKDEV_LOOKUP=y
+# CONFIG_HWSPINLOCK is not set
#
# File systems
diff --git a/patches/panda/0005-OMAP2-3-DSS2-Change-driver-name-to-omap_display.patch b/patches/panda/0005-OMAP2-3-DSS2-Change-driver-name-to-omap_display.patch
index bf9411101c6fce41843326b74e89bac6f42b2836..59b168bc15c258f35fc0b86e658987cdeffe95e6 100644
--- a/patches/panda/0005-OMAP2-3-DSS2-Change-driver-name-to-omap_display.patch
+++ b/patches/panda/0005-OMAP2-3-DSS2-Change-driver-name-to-omap_display.patch
@@ -15,88 +15,34 @@ for: The clkdev changes in clock2420_data.c, clock2430_data.c, clock3xxx_data.c
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/board-3430sdp.c | 2 +-
- arch/arm/mach-omap2/board-am3517evm.c | 2 +-
- arch/arm/mach-omap2/board-cm-t35.c | 2 +-
- arch/arm/mach-omap2/board-devkit8000.c | 6 +++---
- arch/arm/mach-omap2/board-igep0020.c | 2 +-
- arch/arm/mach-omap2/board-omap3beagle.c | 6 +++---
- arch/arm/mach-omap2/board-omap3evm.c | 4 ++--
- arch/arm/mach-omap2/board-omap3pandora.c | 8 ++++----
- arch/arm/mach-omap2/board-omap3stalker.c | 2 +-
+ arch/arm/mach-omap2/board-devkit8000.c | 4 ++--
+ arch/arm/mach-omap2/board-omap3beagle.c | 4 ++--
+ arch/arm/mach-omap2/board-omap3evm.c | 2 +-
+ arch/arm/mach-omap2/board-omap3pandora.c | 6 +++---
arch/arm/mach-omap2/board-rx51-peripherals.c | 4 ++--
- arch/arm/mach-omap2/board-rx51-video.c | 2 +-
- arch/arm/mach-omap2/board-zoom-display.c | 2 +-
arch/arm/mach-omap2/board-zoom-peripherals.c | 4 ++--
arch/arm/mach-omap2/clock2420_data.c | 8 ++++----
arch/arm/mach-omap2/clock2430_data.c | 8 ++++----
arch/arm/mach-omap2/clock3xxx_data.c | 14 +++++++-------
drivers/video/omap2/dss/core.c | 2 +-
- 17 files changed, 39 insertions(+), 39 deletions(-)
+ 10 files changed, 28 insertions(+), 28 deletions(-)
-diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
-index d4e41ef..6f4e7cf 100644
---- a/arch/arm/mach-omap2/board-3430sdp.c
-+++ b/arch/arm/mach-omap2/board-3430sdp.c
-@@ -308,7 +308,7 @@ static struct omap_dss_board_info sdp3430_dss_data = {
- };
-
- static struct platform_device sdp3430_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &sdp3430_dss_data,
-diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
-index 10d60b7..6bb5f53 100644
---- a/arch/arm/mach-omap2/board-am3517evm.c
-+++ b/arch/arm/mach-omap2/board-am3517evm.c
-@@ -379,7 +379,7 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
- };
-
- static struct platform_device am3517_evm_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &am3517_evm_dss_data,
-diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
-index dac1416..79f87ec 100644
---- a/arch/arm/mach-omap2/board-cm-t35.c
-+++ b/arch/arm/mach-omap2/board-cm-t35.c
-@@ -402,7 +402,7 @@ static struct omap_dss_board_info cm_t35_dss_data = {
- };
-
- static struct platform_device cm_t35_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &cm_t35_dss_data,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
-index 9a2a31e..e8cde27 100644
+index 54abdd0..9c08ade 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -196,7 +196,7 @@ static struct omap_dss_board_info devkit8000_dss_data = {
};
- static struct platform_device devkit8000_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &devkit8000_dss_data,
-@@ -204,7 +204,7 @@ static struct platform_device devkit8000_dss_device = {
- };
-
static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss");
+ REGULATOR_SUPPLY("vdda_dac", "omap_display");
static uint32_t board_keymap[] = {
KEY(0, 0, KEY_1),
-@@ -286,7 +286,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
+@@ -278,7 +278,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
};
static struct regulator_consumer_supply devkit8000_vpll1_supply =
@@ -105,33 +51,11 @@ index 9a2a31e..e8cde27 100644
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data devkit8000_vmmc1 = {
-diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
-index 3be85a1..23abfa3 100644
---- a/arch/arm/mach-omap2/board-igep0020.c
-+++ b/arch/arm/mach-omap2/board-igep0020.c
-@@ -486,7 +486,7 @@ static struct omap_dss_board_info igep2_dss_data = {
- };
-
- static struct platform_device igep2_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &igep2_dss_data,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index 46d814a..fd6b4b8 100644
+index f6792f2..de04e07 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
-@@ -229,7 +229,7 @@ static struct omap_dss_board_info beagle_dss_data = {
- };
-
- static struct platform_device beagle_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &beagle_dss_data,
-@@ -237,10 +237,10 @@ static struct platform_device beagle_dss_device = {
+@@ -326,10 +326,10 @@ static struct omap_dss_board_info beagle_dss_data = {
};
static struct regulator_consumer_supply beagle_vdac_supply =
@@ -145,19 +69,10 @@ index 46d814a..fd6b4b8 100644
static void __init beagle_display_init(void)
{
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
-index 323c380..4ad3c4d 100644
+index 3d9b58a..cf0cd1e 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
-@@ -329,7 +329,7 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
- };
-
- static struct platform_device omap3_evm_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &omap3_evm_dss_data,
-@@ -522,7 +522,7 @@ static struct regulator_init_data omap3_evm_vdac = {
+@@ -563,7 +563,7 @@ static struct regulator_init_data omap3_evm_vdac = {
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply omap3_evm_vpll2_supply =
@@ -167,19 +82,10 @@ index 323c380..4ad3c4d 100644
static struct regulator_init_data omap3_evm_vpll2 = {
.constraints = {
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
-index 0b34bed..9e8faf2 100644
+index 17ef547..89e0468 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
-@@ -254,7 +254,7 @@ static struct omap_dss_board_info pandora_dss_data = {
- };
-
- static struct platform_device pandora_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &pandora_dss_data,
-@@ -350,11 +350,11 @@ static struct regulator_consumer_supply pandora_vmmc3_supply =
+@@ -342,11 +342,11 @@ static struct regulator_consumer_supply pandora_vmmc3_supply =
REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2");
static struct regulator_consumer_supply pandora_vdda_dac_supply =
@@ -194,29 +100,18 @@ index 0b34bed..9e8faf2 100644
};
static struct regulator_consumer_supply pandora_vcc_lcd_supply =
-diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
-index 2a2dad4..51c010c 100644
---- a/arch/arm/mach-omap2/board-omap3stalker.c
-+++ b/arch/arm/mach-omap2/board-omap3stalker.c
-@@ -241,7 +241,7 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
- };
-
- static struct platform_device omap3_stalker_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &omap3_stalker_dss_data,
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
-index e75e240..7aedafd 100644
+index d0998f8..5b2bb59 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
-@@ -360,11 +360,11 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
+@@ -366,13 +366,13 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
};
static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
- REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+ REGULATOR_SUPPLY("vdds_sdi", "omap_display"),
+ /* Si4713 supply */
+ REGULATOR_SUPPLY("vdd", "2-0063"),
};
static struct regulator_consumer_supply rx51_vdac_supply[] = {
@@ -225,32 +120,6 @@ index e75e240..7aedafd 100644
};
static struct regulator_init_data rx51_vaux1 = {
-diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
-index acd6700..8140d05 100644
---- a/arch/arm/mach-omap2/board-rx51-video.c
-+++ b/arch/arm/mach-omap2/board-rx51-video.c
-@@ -67,7 +67,7 @@ static struct omap_dss_board_info rx51_dss_board_info = {
- };
-
- struct platform_device rx51_display_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &rx51_dss_board_info,
-diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
-index 6bcd436..d6b949d 100644
---- a/arch/arm/mach-omap2/board-zoom-display.c
-+++ b/arch/arm/mach-omap2/board-zoom-display.c
-@@ -131,7 +131,7 @@ static struct omap_dss_board_info zoom_dss_data = {
- };
-
- static struct platform_device zoom_dss_device = {
-- .name = "omapdss",
-+ .name = "omap_display",
- .id = -1,
- .dev = {
- .platform_data = &zoom_dss_data,
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index e0e040f..d52fc7b 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -307,7 +176,7 @@ index c047dcd..039155e 100644
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
-index 403a4a1..8618262 100644
+index f14d986..84a6c23 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3357,13 +3357,13 @@ static struct omap_clk omap3xxx_clks[] = {
diff --git a/patches/panda/0006-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch b/patches/panda/0006-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch
index 7a5a4f1e5f4b19e1020ff6a7b713aae6ef9137c7..6ce7fa09ce752c6a2a076d68d87c55a997b28744 100644
--- a/patches/panda/0006-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch
+++ b/patches/panda/0006-OMAP2-3-DSS2-Use-Regulator-init-with-driver-name.patch
@@ -10,127 +10,75 @@ Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/board-3430sdp.c | 11 +++--------
- arch/arm/mach-omap2/board-cm-t35.c | 12 ++++--------
- arch/arm/mach-omap2/board-igep0020.c | 6 ++----
- arch/arm/mach-omap2/board-omap3evm.c | 6 ++----
- arch/arm/mach-omap2/board-omap3stalker.c | 12 ++++--------
- 5 files changed, 15 insertions(+), 32 deletions(-)
+ arch/arm/mach-omap2/board-cm-t35.c | 4 ++--
+ arch/arm/mach-omap2/board-igep0020.c | 2 +-
+ arch/arm/mach-omap2/board-omap3evm.c | 2 +-
+ arch/arm/mach-omap2/board-omap3stalker.c | 4 ++--
+ 4 files changed, 6 insertions(+), 6 deletions(-)
-diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
-index 6f4e7cf..d99902c 100644
---- a/arch/arm/mach-omap2/board-3430sdp.c
-+++ b/arch/arm/mach-omap2/board-3430sdp.c
-@@ -315,10 +315,8 @@ static struct platform_device sdp3430_dss_device = {
- },
- };
-
--static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
-- .supply = "vdda_dac",
-- .dev = &sdp3430_dss_device.dev,
--};
-+static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
-+ REGULATOR_SUPPLY("vdda_dac", "omap_display");
-
- static struct platform_device *sdp3430_devices[] __initdata = {
- &sdp3430_dss_device,
-@@ -546,10 +544,7 @@ static struct regulator_init_data sdp3430_vdac = {
-
- /* VPLL2 for digital video outputs */
- static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
-- {
-- .supply = "vdds_dsi",
-- .dev = &sdp3430_dss_device.dev,
-- }
-+ REGULATOR_SUPPLY("vdds_dsi", "omap_display"),
- };
-
- static struct regulator_init_data sdp3430_vpll2 = {
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
-index 79f87ec..22322d1 100644
+index 7311824..19fc4e0 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
-@@ -495,15 +495,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
- .supply = "vmmc_aux",
+@@ -488,10 +488,10 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
};
--static struct regulator_consumer_supply cm_t35_vdac_supply = {
-- .supply = "vdda_dac",
-- .dev = &cm_t35_dss_device.dev,
--};
-+static struct regulator_consumer_supply cm_t35_vdac_supply =
+ static struct regulator_consumer_supply cm_t35_vdac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss");
+ REGULATOR_SUPPLY("vdda_dac", "omap_display");
--static struct regulator_consumer_supply cm_t35_vdvi_supply = {
-- .supply = "vdvi",
-- .dev = &cm_t35_dss_device.dev,
--};
-+static struct regulator_consumer_supply cm_t35_vdvi_supply =
+ static struct regulator_consumer_supply cm_t35_vdvi_supply =
+- REGULATOR_SUPPLY("vdvi", "omapdss");
+ REGULATOR_SUPPLY("vdvi", "omap_display");
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data cm_t35_vmmc1 = {
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
-index 23abfa3..238c69e 100644
+index 54e6318..4fe8575 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
-@@ -493,10 +493,8 @@ static struct platform_device igep2_dss_device = {
- },
+@@ -486,7 +486,7 @@ static struct omap_dss_board_info igep2_dss_data = {
};
--static struct regulator_consumer_supply igep2_vpll2_supply = {
-- .supply = "vdds_dsi",
-- .dev = &igep2_dss_device.dev,
--};
-+static struct regulator_consumer_supply igep2_vpll2_supply =
+ static struct regulator_consumer_supply igep2_vpll2_supply =
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss");
+ REGULATOR_SUPPLY("vdds_dsi", "omap_display");
static struct regulator_init_data igep2_vpll2 = {
.constraints = {
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
-index 4ad3c4d..32ac816 100644
+index 780919e..9e003f8 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
-@@ -500,10 +500,8 @@ static struct twl4030_codec_data omap3evm_codec_data = {
- .audio = &omap3evm_audio_data,
+@@ -544,7 +544,7 @@ static struct twl4030_codec_data omap3evm_codec_data = {
};
--static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = {
-- .supply = "vdda_dac",
-- .dev = &omap3_evm_dss_device.dev,
--};
-+static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
+ static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss");
+ REGULATOR_SUPPLY("vdda_dac", "omap_display");
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_evm_vdac = {
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
-index 51c010c..7b675cb 100644
+index 07006c3..739aa12 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
-@@ -448,10 +448,8 @@ static struct twl4030_codec_data omap3stalker_codec_data = {
- .audio = &omap3stalker_audio_data,
+@@ -441,7 +441,7 @@ static struct twl4030_codec_data omap3stalker_codec_data = {
};
--static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = {
-- .supply = "vdda_dac",
-- .dev = &omap3_stalker_dss_device.dev,
--};
-+static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
+ static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
+- REGULATOR_SUPPLY("vdda_dac", "omapdss");
+ REGULATOR_SUPPLY("vdda_dac", "omap_display");
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_stalker_vdac = {
-@@ -469,10 +467,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
- };
+@@ -460,7 +460,7 @@ static struct regulator_init_data omap3_stalker_vdac = {
/* VPLL2 for digital video outputs */
--static struct regulator_consumer_supply omap3_stalker_vpll2_supply = {
-- .supply = "vdds_dsi",
-- .dev = &omap3_stalker_lcd_device.dev,
--};
-+static struct regulator_consumer_supply omap3_stalker_vpll2_supply =
+ static struct regulator_consumer_supply omap3_stalker_vpll2_supply =
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss");
+ REGULATOR_SUPPLY("vdds_dsi", "omap_display");
static struct regulator_init_data omap3_stalker_vpll2 = {
diff --git a/patches/panda/0007-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch b/patches/panda/0007-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch
index 88153fd7f72d97924af7f98950aac1b93337b589..d2e6e5afc2bd4e777ac3ff43740f2fa7afed92a6 100644
--- a/patches/panda/0007-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch
+++ b/patches/panda/0007-OMAP2-3-DSS2-Create-new-file-display.c-for-central-d.patch
@@ -11,91 +11,34 @@ Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/mach-omap2/Makefile | 3 ++
- arch/arm/mach-omap2/display.c | 46 +++++++++++++++++++++++++++++
- arch/arm/plat-omap/include/plat/display.h | 11 +++++++
- 3 files changed, 60 insertions(+), 0 deletions(-)
- create mode 100644 arch/arm/mach-omap2/display.c
+ arch/arm/mach-omap2/Makefile | 4 ++++
+ arch/arm/plat-omap/include/plat/display.h | 10 ++++++++++
+ 2 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
-index 1c0c2b0..2e81173 100644
+index 1c3635d..c46de95 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
-@@ -242,3 +242,6 @@ obj-y += $(smc91x-m) $(smc91x-y)
+@@ -244,6 +244,10 @@ obj-y += $(smc91x-m) $(smc91x-y)
smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
obj-y += $(smsc911x-m) $(smsc911x-y)
+
+disp-$(CONFIG_OMAP2_DSS) := display.o
+obj-y += $(disp-m) $(disp-y)
-diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
-new file mode 100644
-index 0000000..6e21cb8
---- /dev/null
-+++ b/arch/arm/mach-omap2/display.c
-@@ -0,0 +1,46 @@
-+/*
-+ * OMAP2plus display device setup / initialization.
-+ *
-+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
-+ * Senthilvadivu Guruswamy
-+ * Sumit Semwal
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
-+ * kind, whether express or implied; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+
-+#include <plat/display.h>
-+
-+static struct platform_device omap_display_device = {
-+ .name = "omap_display",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = NULL,
-+ },
-+};
-+
-+int __init omap_display_init(struct omap_dss_board_info
-+ *board_data)
-+{
-+ int r = 0;
-+ omap_display_device.dev.platform_data = board_data;
-+
-+ r = platform_device_register(&omap_display_device);
-+ if (r < 0)
-+ printk(KERN_ERR "Unable to register OMAP-Display device\n");
-+
-+ return r;
-+}
+ obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
+
+ disp-$(CONFIG_OMAP2_DSS) := display.o
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
-index 537f4e4..0f140ec 100644
+index 0f140ec..50a20d0 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
-@@ -23,6 +23,7 @@
- #include <linux/list.h>
- #include <linux/kobject.h>
- #include <linux/device.h>
-+#include <linux/platform_device.h>
- #include <asm/atomic.h>
-
- #define DISPC_IRQ_FRAMEDONE (1 << 0)
-@@ -226,6 +227,16 @@ struct omap_dss_board_info {
- struct omap_dss_device *default_device;
- };
+@@ -237,6 +237,16 @@ static inline int omap_display_init(struct omap_dss_board_info *board_data)
+ }
+ #endif
+#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
+/* Init with the board info */
diff --git a/patches/panda/0009-OMAP2-3-DSS2-Build-omap_device-for-each-DSS-HWIP.patch b/patches/panda/0009-OMAP2-3-DSS2-Build-omap_device-for-each-DSS-HWIP.patch
index c9d32e24237c9f310741f20c3161a24922f0426a..f3c7052dc6f0536071336da640b3794ac409c0d9 100644
--- a/patches/panda/0009-OMAP2-3-DSS2-Build-omap_device-for-each-DSS-HWIP.patch
+++ b/patches/panda/0009-OMAP2-3-DSS2-Build-omap_device-for-each-DSS-HWIP.patch
@@ -10,13 +10,14 @@ Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm/mach-omap2/display.c | 50 +++++++++++++++++++++++++++++
arch/arm/plat-omap/include/plat/display.h | 5 +++
2 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
-index 6e21cb8..5c0a78b 100644
+index b18db84..3494185 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -23,6 +23,8 @@
@@ -27,8 +28,8 @@ index 6e21cb8..5c0a78b 100644
+#include <plat/omap_device.h>
static struct platform_device omap_display_device = {
- .name = "omap_display",
-@@ -32,10 +34,58 @@ static struct platform_device omap_display_device = {
+ .name = "omapdss",
+@@ -32,9 +34,57 @@ static struct platform_device omap_display_device = {
},
};
@@ -40,8 +41,7 @@ index 6e21cb8..5c0a78b 100644
+ },
+};
+
- int __init omap_display_init(struct omap_dss_board_info
- *board_data)
+ int __init omap_display_init(struct omap_dss_board_info *board_data)
{
int r = 0;
+ struct omap_hwmod *oh;
@@ -88,10 +88,10 @@ index 6e21cb8..5c0a78b 100644
r = platform_device_register(&omap_display_device);
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
-index 0f140ec..2fb057e 100644
+index 50a20d0..ff2c6d7 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
-@@ -237,6 +237,11 @@ static inline int omap_display_init(struct omap_dss_board_info *board_data)
+@@ -247,6 +247,11 @@ static inline int omap_display_init(struct omap_dss_board_info *board_data)
}
#endif
diff --git a/patches/panda/0014-OMAP2-3-DSS2-VENC-create-platform_driver-move-init-e.patch b/patches/panda/0014-OMAP2-3-DSS2-VENC-create-platform_driver-move-init-e.patch
index 6f89d98bc813ec1ab89670d4a4da3c685679933e..cf8727cbdffd8eeceb0a7fddec13ed34f016568f 100644
--- a/patches/panda/0014-OMAP2-3-DSS2-VENC-create-platform_driver-move-init-e.patch
+++ b/patches/panda/0014-OMAP2-3-DSS2-VENC-create-platform_driver-move-init-e.patch
@@ -15,6 +15,7 @@ Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm/mach-omap2/board-3430sdp.c | 2 +-
arch/arm/mach-omap2/board-cm-t35.c | 2 +-
@@ -31,20 +32,20 @@ Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
12 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
-index d00f356..e0d13ae 100644
+index 19a36a3..6497868 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
-@@ -308,7 +308,7 @@ static struct omap_dss_board_info sdp3430_dss_data = {
+@@ -398,7 +398,7 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
};
- static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
-- REGULATOR_SUPPLY("vdda_dac", "omap_display");
-+ REGULATOR_SUPPLY("vdda_dac", "omap_venc");
-
- static struct omap_board_config_kernel sdp3430_config[] __initdata = {
+ static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
+- REGULATOR_SUPPLY("vdda_dac", "omapdss"),
++ REGULATOR_SUPPLY("vdda_dac", "omap_venc"),
};
+
+ /* VPLL2 for digital video outputs */
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
-index 1c36ec8..2e9265e 100644
+index 19fc4e0..862fe5f 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -488,7 +488,7 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
@@ -57,7 +58,7 @@ index 1c36ec8..2e9265e 100644
static struct regulator_consumer_supply cm_t35_vdvi_supply =
REGULATOR_SUPPLY("vdvi", "omap_display");
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
-index 84ff6b0..d387c8d 100644
+index 9c08ade..6b2b18f 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -196,7 +196,7 @@ static struct omap_dss_board_info devkit8000_dss_data = {
@@ -70,10 +71,10 @@ index 84ff6b0..d387c8d 100644
static uint32_t board_keymap[] = {
KEY(0, 0, KEY_1),
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index c0a5066..4dd1475 100644
+index de04e07..e29e345 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
-@@ -229,7 +229,7 @@ static struct omap_dss_board_info beagle_dss_data = {
+@@ -326,7 +326,7 @@ static struct omap_dss_board_info beagle_dss_data = {
};
static struct regulator_consumer_supply beagle_vdac_supply =
@@ -83,10 +84,10 @@ index c0a5066..4dd1475 100644
static struct regulator_consumer_supply beagle_vdvi_supply =
REGULATOR_SUPPLY("vdds_dsi", "omap_display");
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
-index 5f156fe..ec45575 100644
+index 9e003f8..8e5b7e2 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
-@@ -493,7 +493,7 @@ static struct twl4030_codec_data omap3evm_codec_data = {
+@@ -544,7 +544,7 @@ static struct twl4030_codec_data omap3evm_codec_data = {
};
static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
@@ -96,7 +97,7 @@ index 5f156fe..ec45575 100644
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_evm_vdac = {
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
-index 613ab58..b44e604 100644
+index 89e0468..58bdf99 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -342,7 +342,7 @@ static struct regulator_consumer_supply pandora_vmmc3_supply =
@@ -109,7 +110,7 @@ index 613ab58..b44e604 100644
static struct regulator_consumer_supply pandora_vdds_supplies[] = {
REGULATOR_SUPPLY("vdds_sdi", "omap_display"),
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
-index 7671218..ab98a64 100644
+index 739aa12..bd12f40 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -441,7 +441,7 @@ static struct twl4030_codec_data omap3stalker_codec_data = {
@@ -256,10 +257,10 @@ index f4835c8..9313851 100644
}
#endif
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
-index eff3505..935ae8e 100644
+index e1f4aab..e15a468 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
-@@ -289,6 +289,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
+@@ -294,6 +294,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
EXPORT_SYMBOL(omap_dss_ntsc_timings);
static struct {
@@ -267,7 +268,7 @@ index eff3505..935ae8e 100644
void __iomem *base;
struct mutex venc_lock;
u32 wss_data;
-@@ -306,6 +307,17 @@ static inline u32 venc_read_reg(int idx)
+@@ -311,6 +312,17 @@ static inline u32 venc_read_reg(int idx)
return l;
}
@@ -285,7 +286,7 @@ index eff3505..935ae8e 100644
static void venc_write_config(const struct venc_config *config)
{
DSSDBG("write venc conf\n");
-@@ -641,46 +653,6 @@ static struct omap_dss_driver venc_driver = {
+@@ -663,46 +675,6 @@ static struct omap_dss_driver venc_driver = {
};
/* driver end */
@@ -332,7 +333,7 @@ index eff3505..935ae8e 100644
int venc_init_display(struct omap_dss_device *dssdev)
{
DSSDBG("init_display\n");
-@@ -740,3 +712,67 @@ void venc_dump_regs(struct seq_file *s)
+@@ -762,3 +734,67 @@ void venc_dump_regs(struct seq_file *s)
#undef DUMPREG
}
diff --git a/patches/panda/0015-OMAP2-3-DSS2-DSI-create-platform_driver-move-init-ex.patch b/patches/panda/0015-OMAP2-3-DSS2-DSI-create-platform_driver-move-init-ex.patch
index 991dd07287c321abf8018dc6c2c95f8db5c97cdc..f997f31c4fae1fc441c21793fd2b73b99386ec8c 100644
--- a/patches/panda/0015-OMAP2-3-DSS2-DSI-create-platform_driver-move-init-ex.patch
+++ b/patches/panda/0015-OMAP2-3-DSS2-DSI-create-platform_driver-move-init-ex.patch
@@ -18,7 +18,7 @@ Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
---
- arch/arm/mach-omap2/board-3430sdp.c | 1 +
+ arch/arm/mach-omap2/board-3430sdp.c | 2 +-
arch/arm/mach-omap2/board-devkit8000.c | 10 ++--
arch/arm/mach-omap2/board-igep0020.c | 10 ++--
arch/arm/mach-omap2/board-omap3beagle.c | 10 ++--
@@ -29,22 +29,23 @@ Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
drivers/video/omap2/dss/core.c | 8 ++--
drivers/video/omap2/dss/dsi.c | 64 ++++++++++++++++++++++++-
drivers/video/omap2/dss/dss.h | 8 ++--
- 11 files changed, 107 insertions(+), 35 deletions(-)
+ 11 files changed, 107 insertions(+), 36 deletions(-)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
-index e0d13ae..33ff4f6 100644
+index 6497868..8a606bb 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
-@@ -533,6 +533,7 @@ static struct regulator_init_data sdp3430_vdac = {
+@@ -403,7 +403,7 @@ static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
+
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omap_display"),
+- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+ REGULATOR_SUPPLY("vdds_dsi", "omap_dsi1"),
};
- static struct regulator_init_data sdp3430_vpll2 = {
+ static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
-index d387c8d..d277143 100644
+index 6b2b18f..a57d698 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -277,8 +277,10 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
@@ -72,7 +73,7 @@ index d387c8d..d277143 100644
/* VAUX4 for ads7846 and nubs */
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
-index d79dcd5..dfbe3a1 100644
+index 4fe8575..d6951bd 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -485,8 +485,10 @@ static struct omap_dss_board_info igep2_dss_data = {
@@ -100,10 +101,10 @@ index d79dcd5..dfbe3a1 100644
static void __init igep2_display_init(void)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
-index 4dd1475..caf6c8a 100644
+index e29e345..bec71a0 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
-@@ -231,8 +231,10 @@ static struct omap_dss_board_info beagle_dss_data = {
+@@ -328,8 +328,10 @@ static struct omap_dss_board_info beagle_dss_data = {
static struct regulator_consumer_supply beagle_vdac_supply =
REGULATOR_SUPPLY("vdda_dac", "omap_venc");
@@ -116,7 +117,7 @@ index 4dd1475..caf6c8a 100644
static void __init beagle_display_init(void)
{
-@@ -419,8 +421,8 @@ static struct regulator_init_data beagle_vpll2 = {
+@@ -530,8 +532,8 @@ static struct regulator_init_data beagle_vpll2 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
@@ -128,10 +129,10 @@ index 4dd1475..caf6c8a 100644
static struct twl4030_usb_data beagle_usb_data = {
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
-index ec45575..0c56b9e 100644
+index 8e5b7e2..8a52dfb 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
-@@ -511,8 +511,10 @@ static struct regulator_init_data omap3_evm_vdac = {
+@@ -562,8 +562,10 @@ static struct regulator_init_data omap3_evm_vdac = {
};
/* VPLL2 for digital video outputs */
@@ -144,7 +145,7 @@ index ec45575..0c56b9e 100644
static struct regulator_init_data omap3_evm_vpll2 = {
.constraints = {
-@@ -524,8 +526,8 @@ static struct regulator_init_data omap3_evm_vpll2 = {
+@@ -575,8 +577,8 @@ static struct regulator_init_data omap3_evm_vpll2 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
@@ -154,9 +155,9 @@ index ec45575..0c56b9e 100644
+ .consumer_supplies = omap3_evm_vpll2_supplies,
};
- static struct twl4030_platform_data omap3evm_twldata = {
+ /* ads7846 on SPI */
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
-index b44e604..b430d2b 100644
+index 58bdf99..12df9cb 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -347,6 +347,7 @@ static struct regulator_consumer_supply pandora_vdda_dac_supply =
@@ -168,7 +169,7 @@ index b44e604..b430d2b 100644
static struct regulator_consumer_supply pandora_vcc_lcd_supply =
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
-index ab98a64..b5e8680 100644
+index bd12f40..2628aa7 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -459,8 +459,10 @@ static struct regulator_init_data omap3_stalker_vdac = {
diff --git a/patches/panda/0035-OMAP4-PandaBoard-Adding-DVI-support.patch b/patches/panda/0035-OMAP4-PandaBoard-Adding-DVI-support.patch
index 8b0be24724a690ae608b99fd729c3a46dce20723..dbb0ed966f2816adb73fbeb9351046fd62e34154 100644
--- a/patches/panda/0035-OMAP4-PandaBoard-Adding-DVI-support.patch
+++ b/patches/panda/0035-OMAP4-PandaBoard-Adding-DVI-support.patch
@@ -23,15 +23,16 @@ for the same is taken from the kernel.org commit e3333f48dd5cb21
(omap: Adding beagle i2c eeprom driver to read EDID)
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
+Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
arch/arm/mach-omap2/board-omap4panda.c | 137 +++++++++++++++++++++++++++++++-
1 files changed, 136 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
-index e944025..b09d239 100644
+index 3dd241b..163cfa5 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
-@@ -37,6 +37,7 @@
+@@ -39,6 +39,7 @@
#include <plat/common.h>
#include <plat/usb.h>
#include <plat/mmc.h>
@@ -39,7 +40,7 @@ index e944025..b09d239 100644
#include "timer-gp.h"
#include "hsmmc.h"
-@@ -76,6 +77,60 @@ static struct platform_device *panda_devices[] __initdata = {
+@@ -80,6 +81,60 @@ static struct platform_device *panda_devices[] __initdata = {
&leds_gpio,
};
@@ -97,10 +98,10 @@ index e944025..b09d239 100644
+ .default_device = &panda_dvi_device,
+};
+
- static void __init omap4_panda_init_irq(void)
+ static void __init omap4_panda_init_early(void)
{
omap2_init_common_infrastructure();
-@@ -375,6 +430,17 @@ static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = {
+@@ -421,6 +476,17 @@ static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = {
.platform_data = &omap4_panda_twldata,
},
};
@@ -118,7 +119,7 @@ index e944025..b09d239 100644
static int __init omap4_panda_i2c_init(void)
{
/*
-@@ -384,13 +450,76 @@ static int __init omap4_panda_i2c_init(void)
+@@ -430,7 +496,12 @@ static int __init omap4_panda_i2c_init(void)
omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo,
ARRAY_SIZE(omap4_panda_i2c_boardinfo));
omap_register_i2c_bus(2, 400, NULL, 0);
@@ -132,9 +133,10 @@ index e944025..b09d239 100644
omap_register_i2c_bus(4, 400, NULL, 0);
return 0;
}
-
- #ifdef CONFIG_OMAP_MUX
- static struct omap_board_mux board_mux[] __initdata = {
+@@ -450,6 +521,64 @@ static struct omap_board_mux board_mux[] __initdata = {
+ OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+ OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+ OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+ /* gpio 0 - TFP410 PD */
+ OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3),
+ /* dispc2_data23 */
@@ -196,7 +198,7 @@ index e944025..b09d239 100644
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
-@@ -400,6 +529,7 @@ static struct omap_board_mux board_mux[] __initdata = {
+@@ -459,6 +588,7 @@ static struct omap_board_mux board_mux[] __initdata = {
static void __init omap4_panda_init(void)
{
int package = OMAP_PACKAGE_CBS;
@@ -204,7 +206,7 @@ index e944025..b09d239 100644
if (omap_rev() == OMAP4430_REV_ES1_0)
package = OMAP_PACKAGE_CBL;
-@@ -411,6 +541,11 @@ static void __init omap4_panda_init(void)
+@@ -474,6 +604,11 @@ static void __init omap4_panda_init(void)
omap4_twl6030_hsmmc_init(mmc);
omap4_ehci_init();
usb_musb_init(&musb_board_data);
diff --git a/version.sh b/version.sh
index 94b07b4057d062f4e74d8bdef6f64f56ccf36a8d..06c7212c869ffc16dd1b00e74217ed8132c02244 100644
--- a/version.sh
+++ b/version.sh
@@ -7,7 +7,7 @@ KERNEL_REL=2.6.37
#PRE_RC=2.6.37-git18
RC_KERNEL=2.6.38
RC_PATCH=-rc8
-ABI=5
+ABI=5.1
if [ "${NO_DEVTMPS}" ] ; then
BUILD=dold${ABI}