diff --git a/patch.sh b/patch.sh
index 976b75d482a632849b41034d1181ffa7cc02f352..71e4fc7bbd1633c7f11b380ce710fa5e663bf71b 100644
--- a/patch.sh
+++ b/patch.sh
@@ -557,30 +557,23 @@ drivers () {
dir 'drivers/ti/tsc'
dir 'drivers/ti/gpio'
dir 'drivers/greybus'
- #dir 'drivers/serdev'
dir 'drivers/fb_ssd1306'
- #dir 'drivers/mikrobus'
}
soc () {
dir 'bootup_hacks'
}
-fixes () {
- dir 'fixes/gcc'
-}
-
###
backports
#reverts
drivers
soc
-fixes
packaging () {
#do_backport="enable"
if [ "x${do_backport}" = "xenable" ] ; then
- backport_tag="v6.0.8"
+ backport_tag="v6.1.1"
subsystem="bindeb-pkg"
#regenerate="enable"
@@ -601,4 +594,4 @@ packaging () {
packaging
echo "patch.sh ran successfully"
-#
\ No newline at end of file
+#
diff --git a/patches/defconfig b/patches/defconfig
index 531492de17fdc0836a23ded009243cb936cf95aa..7eafe5d0c10b2d63592692d4e28d70938dc0cb9d 100644
--- a/patches/defconfig
+++ b/patches/defconfig
@@ -1,15 +1,15 @@
#
# Automatically generated file; DO NOT EDIT.
-# Linux/arm 6.1.0-rc5 Kernel Configuration
+# Linux/arm 6.1.0-rc7 Kernel Configuration
#
-CONFIG_CC_VERSION_TEXT="arm-linux-gnueabi-gcc (GCC) 11.3.0"
+CONFIG_CC_VERSION_TEXT="arm-linux-gnueabi-gcc (GCC) 12.2.0"
CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=110300
+CONFIG_GCC_VERSION=120200
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=23800
+CONFIG_AS_VERSION=23900
CONFIG_LD_IS_BFD=y
-CONFIG_LD_VERSION=23800
+CONFIG_LD_VERSION=23900
CONFIG_LLD_VERSION=0
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
@@ -153,6 +153,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC12_NO_ARRAY_BOUNDS=y
+CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
@@ -461,6 +462,7 @@ CONFIG_ALIGNMENT_TRAP=y
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
# CONFIG_XEN is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features
@@ -663,7 +665,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
-CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK=y
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
@@ -914,6 +915,7 @@ CONFIG_INET_ESP=m
CONFIG_INET_ESP_OFFLOAD=m
# CONFIG_INET_ESPINTCP is not set
CONFIG_INET_IPCOMP=m
+CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_DIAG=m
@@ -7617,10 +7619,12 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo"
#
# Memory initialization
#
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
+# CONFIG_INIT_STACK_ALL_PATTERN is not set
+# CONFIG_INIT_STACK_ALL_ZERO is not set
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
diff --git a/patches/drivers/mikrobus/0001-mikrobus-driver-update-patch.patch b/patches/drivers/mikrobus/0001-mikrobus-driver-update-patch.patch
deleted file mode 100644
index 95336db11bed84a9dab3615b6ba53e65cb79e74d..0000000000000000000000000000000000000000
--- a/patches/drivers/mikrobus/0001-mikrobus-driver-update-patch.patch
+++ /dev/null
@@ -1,2901 +0,0 @@
-From 2fb4b13ddf4e9283069ea392ed71101280cc64e1 Mon Sep 17 00:00:00 2001
-From: vaishnav98 <vaishnav@beagleboard.org>
-Date: Wed, 1 Sep 2021 21:02:29 +0530
-Subject: [PATCH] mikrobus driver update patch
-
-This Patch series is an update to the mikroBUS driver
-with support for mikrobus over greybus and click ID EEPROM.
-
-RFC v1 Patch : https://lkml.org/lkml/2020/7/24/518 .
-The mikrobus driver is updated to add mikrobus ports from device-tree
-overlays, the debug interfaces for adding mikrobus ports through sysFS
-is removed, and the driver considers the extended usage of mikrobus
-port pins from their standard purposes.
-
-change log:
- v2: support for adding mikroBUS ports from DT overlays,
- remove debug sysFS interface for adding mikrobus ports,
- consider extended pin usage/deviations from mikrobus standard
- specifications,
- use greybus CPort protocol enum instead of new protcol enums
- Fix cases of wrong indendation, ignoring return values, freeing
- allocated resources in case of errors and other style suggestions
- in v1 review.
-
-Signed-off-by: vaishnav <vaishnav@beagleboard.org>
-Signed-off-by: vaishnav98 <vaishnav@beagleboard.org>
----
- drivers/greybus/Kconfig | 7 +
- drivers/greybus/Makefile | 2 +
- drivers/greybus/gb_netlink.h | 34 +
- drivers/greybus/manifest.c | 18 +
- drivers/greybus/netlink.c | 257 ++++
- drivers/misc/Kconfig | 1 +
- drivers/misc/Makefile | 1 +
- drivers/misc/mikrobus/Kconfig | 16 +
- drivers/misc/mikrobus/Makefile | 6 +
- drivers/misc/mikrobus/mikrobus_core.c | 1032 +++++++++++++++++
- drivers/misc/mikrobus/mikrobus_id.c | 197 ++++
- drivers/misc/mikrobus/mikrobus_manifest.c | 477 ++++++++
- drivers/misc/mikrobus/mikrobus_manifest.h | 20 +
- drivers/staging/greybus/gbphy.c | 10 +-
- drivers/staging/greybus/gpio.c | 26 +-
- drivers/staging/greybus/i2c.c | 11 +-
- drivers/staging/greybus/pwm.c | 2 +-
- drivers/staging/greybus/sdio.c | 2 +-
- drivers/staging/greybus/spi.c | 2 +-
- drivers/staging/greybus/spilib.c | 19 +-
- drivers/staging/greybus/uart.c | 2 +-
- drivers/staging/greybus/usb.c | 2 +-
- drivers/w1/w1.c | 3 +-
- drivers/w1/w1_int.c | 28 +
- include/linux/greybus/bundle.h | 2 +
- .../staging => include/linux}/greybus/gbphy.h | 61 +-
- include/linux/greybus/greybus_manifest.h | 49 +
- include/linux/greybus/interface.h | 2 +
- include/linux/mikrobus.h | 207 ++++
- include/linux/w1.h | 1 +
- 30 files changed, 2430 insertions(+), 67 deletions(-)
- create mode 100644 drivers/greybus/gb_netlink.h
- create mode 100644 drivers/greybus/netlink.c
- create mode 100644 drivers/misc/mikrobus/Kconfig
- create mode 100644 drivers/misc/mikrobus/Makefile
- create mode 100644 drivers/misc/mikrobus/mikrobus_core.c
- create mode 100644 drivers/misc/mikrobus/mikrobus_id.c
- create mode 100644 drivers/misc/mikrobus/mikrobus_manifest.c
- create mode 100644 drivers/misc/mikrobus/mikrobus_manifest.h
- rename {drivers/staging => include/linux}/greybus/gbphy.h (68%)
- create mode 100644 include/linux/mikrobus.h
-
-diff --git a/drivers/greybus/Kconfig b/drivers/greybus/Kconfig
-index 78ba3c3083d5..f07fb38f4a1a 100644
---- a/drivers/greybus/Kconfig
-+++ b/drivers/greybus/Kconfig
-@@ -28,5 +28,12 @@ config GREYBUS_ES2
- To compile this code as a module, choose M here: the module
- will be called gb-es2.ko
-
-+config GREYBUS_NETLINK
-+ tristate "Greybus netlink host controller"
-+ help
-+ Select this option if you want to implement a Greybus
-+ "host controller" in userspace.
-+ To compile this code as a module, chose M here: the module
-+ will be called gb-netlink.ko
- endif # GREYBUS
-
-diff --git a/drivers/greybus/Makefile b/drivers/greybus/Makefile
-index 9bccdd229aa2..280a35e9971c 100644
---- a/drivers/greybus/Makefile
-+++ b/drivers/greybus/Makefile
-@@ -20,7 +20,9 @@ ccflags-y += -I$(src)
-
- # Greybus Host controller drivers
- gb-es2-y := es2.o
-+gb-netlink-y := netlink.o
-
- obj-$(CONFIG_GREYBUS_ES2) += gb-es2.o
-+obj-$(CONFIG_GREYBUS_NETLINK) += gb-netlink.o
-
-
-diff --git a/drivers/greybus/gb_netlink.h b/drivers/greybus/gb_netlink.h
-new file mode 100644
-index 000000000000..4756491397ec
---- /dev/null
-+++ b/drivers/greybus/gb_netlink.h
-@@ -0,0 +1,34 @@
-+/*
-+ * Greybus TCP/IP driver for Greybus over TCP/IP
-+ *
-+ * Released under the GPLv2 only.
-+ */
-+
-+#ifndef __GB_NETLINK_H
-+#define __GB_NETLINK_H
-+
-+/* Maximum packet size */
-+#define GB_NETLINK_MTU 2048
-+/* Maximum number of Cports */
-+#define GB_NETLINK_NUM_CPORT 32
-+
-+#define GB_NL_NAME "GREYBUS"
-+#define GB_NL_PID 1
-+
-+enum {
-+ GB_NL_A_UNSPEC,
-+ GB_NL_A_DATA,
-+ GB_NL_A_CPORT,
-+ __GB_NL_A_MAX,
-+};
-+#define GB_NL_A_MAX (__GB_NL_A_MAX - 1)
-+
-+enum {
-+ GB_NL_C_UNSPEC,
-+ GB_NL_C_MSG,
-+ GB_NL_C_HD_RESET,
-+ __GB_NL_C_MAX,
-+};
-+#define GB_NL_C_MAX (__GB_NL_C_MAX - 1)
-+
-+#endif /* __GB_NETLINK_H */
-diff --git a/drivers/greybus/manifest.c b/drivers/greybus/manifest.c
-index dd7040697bde..9be09511b4df 100644
---- a/drivers/greybus/manifest.c
-+++ b/drivers/greybus/manifest.c
-@@ -136,6 +136,17 @@ static int identify_descriptor(struct gb_interface *intf,
- case GREYBUS_TYPE_CPORT:
- expected_size += sizeof(struct greybus_descriptor_cport);
- break;
-+ case GREYBUS_TYPE_PROPERTY:
-+ expected_size += sizeof(struct greybus_descriptor_property);
-+ expected_size += desc->property.length;
-+ expected_size = ALIGN(expected_size, 4);
-+ break;
-+ case GREYBUS_TYPE_DEVICE:
-+ expected_size += sizeof(struct greybus_descriptor_device);
-+ break;
-+ case GREYBUS_TYPE_MIKROBUS:
-+ expected_size += sizeof(struct greybus_descriptor_mikrobus);
-+ break;
- case GREYBUS_TYPE_INVALID:
- default:
- dev_err(&intf->dev, "invalid descriptor type (%u)\n",
-@@ -372,6 +383,11 @@ static u32 gb_manifest_parse_bundles(struct gb_interface *intf)
- continue;
- }
-
-+ if (class == GREYBUS_CLASS_BRIDGED_PHY){
-+ bundle->manifest_blob = kmemdup(intf->manifest_blob, intf->manifest_size, GFP_KERNEL);
-+ bundle->manifest_size = intf->manifest_size;
-+ }
-+
- count++;
- }
-
-@@ -489,6 +505,8 @@ bool gb_manifest_parse(struct gb_interface *intf, void *data, size_t size)
- return false;
- }
-
-+ intf->manifest_size = size;
-+ intf->manifest_blob = data;
- /* OK, find all the descriptors */
- desc = manifest->descriptors;
- size -= sizeof(*header);
-diff --git a/drivers/greybus/netlink.c b/drivers/greybus/netlink.c
-new file mode 100644
-index 000000000000..56f507ebdd0b
---- /dev/null
-+++ b/drivers/greybus/netlink.c
-@@ -0,0 +1,257 @@
-+/*
-+ * Greybus Netlink driver for userspace controller
-+ *
-+ * Copyright (c) 2017 BayLibre SAS
-+ *
-+ * Released under the GPLv2 only.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/slab.h>
-+#include <net/genetlink.h>
-+#include <linux/greybus.h>
-+
-+#include "gb_netlink.h"
-+
-+static dev_t major_dev;
-+static struct class *gb_nl_class;
-+static struct genl_family gb_nl_family;
-+static struct gb_host_device *gb_nl_hd;
-+
-+#define VERSION_NR 1
-+
-+#define DEVICE_NAME "gb_netlink"
-+#define CLASS_NAME "gb_netlink"
-+
-+static int _gb_netlink_init(struct device *dev);
-+static void _gb_netlink_exit(void);
-+
-+static int gb_netlink_msg(struct sk_buff *skb, struct genl_info *info)
-+{
-+ struct nlattr *na;
-+ u16 cport_id;
-+ void *data;
-+
-+ if (!info)
-+ return -EPROTO;
-+
-+ na = info->attrs[GB_NL_A_CPORT];
-+ if (!na) {
-+ dev_err(&gb_nl_hd->dev,
-+ "Received message without cport id attribute\n");
-+ return -EPROTO;
-+ }
-+
-+ cport_id = nla_get_u32(na);
-+ if (!cport_id_valid(gb_nl_hd, cport_id)) {
-+ dev_err(&gb_nl_hd->dev, "invalid cport id %u received",
-+ cport_id);
-+ return -EINVAL;
-+ }
-+
-+ na = info->attrs[GB_NL_A_DATA];
-+ if (!na) {
-+ dev_err(&gb_nl_hd->dev,
-+ "Received message without data attribute\n");
-+ return -EPROTO;
-+ }
-+
-+ data = nla_data(na);
-+ if (!data) {
-+ dev_err(&gb_nl_hd->dev,
-+ "Received message without data\n");
-+ return -EINVAL;
-+ }
-+
-+ greybus_data_rcvd(gb_nl_hd, cport_id, data, nla_len(na));
-+
-+ return 0;
-+}
-+
-+static int gb_netlink_hd_reset(struct sk_buff *skb, struct genl_info *info)
-+{
-+ struct device *dev;
-+ struct gb_host_device *hd = gb_nl_hd;
-+
-+ dev = hd->dev.parent;
-+ _gb_netlink_exit();
-+ _gb_netlink_init(dev);
-+
-+ return 0;
-+}
-+
-+static struct nla_policy gb_nl_policy[GB_NL_A_MAX + 1] = {
-+ [GB_NL_A_DATA] = { .type = NLA_BINARY, .len = GB_NETLINK_MTU },
-+ [GB_NL_A_CPORT] = { .type = NLA_U32},
-+};
-+
-+static struct genl_ops gb_nl_ops[] = {
-+ {
-+ .cmd = GB_NL_C_MSG,
-+ .doit = gb_netlink_msg,
-+ },
-+ {
-+ .cmd = GB_NL_C_HD_RESET,
-+ .doit = gb_netlink_hd_reset,
-+ },
-+};
-+
-+static struct genl_family gb_nl_family = {
-+ .hdrsize = 0,
-+ .name = GB_NL_NAME,
-+ .version = VERSION_NR,
-+ .maxattr = GB_NL_A_MAX,
-+ .ops = gb_nl_ops,
-+ .n_ops = ARRAY_SIZE(gb_nl_ops),
-+ .policy = gb_nl_policy,
-+};
-+
-+static int message_send(struct gb_host_device *hd, u16 cport_id,
-+ struct gb_message *message, gfp_t gfp_mask)
-+{
-+ struct nl_msg *nl_msg;
-+ struct sk_buff *skb;
-+ int retval = -ENOMEM;
-+
-+ skb = genlmsg_new(sizeof(*message->header) + sizeof(u32) +
-+ message->payload_size, GFP_KERNEL);
-+ if (!skb)
-+ goto err_out;
-+
-+ nl_msg = genlmsg_put(skb, GB_NL_PID, 0,
-+ &gb_nl_family, 0, GB_NL_C_MSG);
-+ if (!nl_msg)
-+ goto err_free;
-+
-+ retval = nla_put_u32(skb, GB_NL_A_CPORT, cport_id);
-+ if (retval)
-+ goto err_cancel;
-+
-+ retval = nla_put(skb, GB_NL_A_DATA,
-+ sizeof(*message->header) + message->payload_size,
-+ message->header);
-+ if (retval)
-+ goto err_cancel;
-+
-+ genlmsg_end(skb, nl_msg);
-+
-+ retval = genlmsg_unicast(&init_net, skb, GB_NL_PID);
-+ if (retval)
-+ goto err_cancel;
-+
-+ greybus_message_sent(hd, message, 0);
-+
-+ return 0;
-+
-+err_cancel:
-+ genlmsg_cancel(skb, nl_msg);
-+err_free:
-+ nlmsg_free(skb);
-+err_out:
-+ return retval;
-+}
-+
-+static void message_cancel(struct gb_message *message)
-+{
-+}
-+
-+static struct gb_hd_driver tcpip_driver = {
-+ .message_send = message_send,
-+ .message_cancel = message_cancel,
-+};
-+
-+static void _gb_netlink_exit(void)
-+{
-+ if (!gb_nl_hd)
-+ return;
-+
-+ gb_hd_del(gb_nl_hd);
-+ gb_hd_put(gb_nl_hd);
-+
-+ gb_nl_hd = NULL;
-+}
-+
-+static void __exit gb_netlink_exit(void)
-+{
-+ _gb_netlink_exit();
-+
-+ unregister_chrdev_region(major_dev, 1);
-+ device_destroy(gb_nl_class, major_dev);
-+ class_destroy(gb_nl_class);
-+
-+ genl_unregister_family(&gb_nl_family);
-+}
-+
-+static int _gb_netlink_init(struct device *dev)
-+{
-+ int retval;
-+
-+ gb_nl_hd = gb_hd_create(&tcpip_driver, dev, GB_NETLINK_MTU,
-+ GB_NETLINK_NUM_CPORT);
-+ if (IS_ERR(gb_nl_hd))
-+ return PTR_ERR(gb_nl_hd);
-+
-+ retval = gb_hd_add(gb_nl_hd);
-+ if (retval)
-+ goto err_gb_hd_del;
-+
-+ return 0;
-+
-+err_gb_hd_del:
-+ gb_hd_del(gb_nl_hd);
-+ gb_hd_put(gb_nl_hd);
-+
-+ return retval;
-+}
-+
-+static int __init gb_netlink_init(void)
-+{
-+ int retval;
-+ struct device *dev;
-+
-+ retval = genl_register_family(&gb_nl_family);
-+ if (retval)
-+ return retval;
-+
-+ retval = alloc_chrdev_region(&major_dev, 0, 1, DEVICE_NAME);
-+ if (retval)
-+ goto err_genl_unregister;
-+
-+ gb_nl_class = class_create(THIS_MODULE, CLASS_NAME);
-+ if (IS_ERR(gb_nl_class)) {
-+ retval = PTR_ERR(gb_nl_class);
-+ goto err_chrdev_unregister;
-+ }
-+
-+ dev = device_create(gb_nl_class, NULL, major_dev, NULL, DEVICE_NAME);
-+ if (IS_ERR(dev)) {
-+ retval = PTR_ERR(dev);
-+ goto err_class_destroy;
-+ }
-+
-+ retval = _gb_netlink_init(dev);
-+ if (retval)
-+ goto err_device_destroy;
-+
-+ return 0;
-+
-+err_device_destroy:
-+ device_destroy(gb_nl_class, major_dev);
-+err_chrdev_unregister:
-+ unregister_chrdev_region(major_dev, 1);
-+err_class_destroy:
-+ class_destroy(gb_nl_class);
-+err_genl_unregister:
-+ genl_unregister_family(&gb_nl_family);
-+
-+ return retval;
-+}
-+
-+module_init(gb_netlink_init);
-+module_exit(gb_netlink_exit);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Alexandre Bailon <abailon@baylibre.com>");
-diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
-index 8403506a4abf..b9702b3a65ff 100644
---- a/drivers/misc/Kconfig
-+++ b/drivers/misc/Kconfig
-@@ -465,4 +465,5 @@ source "drivers/misc/cardreader/Kconfig"
- source "drivers/misc/habanalabs/Kconfig"
- source "drivers/misc/uacce/Kconfig"
- source "drivers/misc/pvpanic/Kconfig"
-+source "drivers/misc/mikrobus/Kconfig"
- endmenu
-diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
-index 2756a0302d60..b69fc0bad1d0 100644
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -38,6 +38,7 @@ obj-$(CONFIG_VMWARE_BALLOON) += vmw_balloon.o
- obj-$(CONFIG_PCH_PHUB) += pch_phub.o
- obj-y += ti-st/
- obj-y += lis3lv02d/
-+obj-y += mikrobus/
- obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/
- obj-$(CONFIG_INTEL_MEI) += mei/
- obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/
-diff --git a/drivers/misc/mikrobus/Kconfig b/drivers/misc/mikrobus/Kconfig
-new file mode 100644
-index 000000000000..5f42bc4e9410
---- /dev/null
-+++ b/drivers/misc/mikrobus/Kconfig
-@@ -0,0 +1,16 @@
-+menuconfig MIKROBUS
-+ tristate "Module for instantiating devices on mikroBUS ports"
-+ help
-+ This option enables the mikroBUS driver. mikroBUS is an add-on
-+ board socket standard that offers maximum expandability with
-+ the smallest number of pins. The mikroBUS driver instantiates
-+ devices on a mikroBUS port described by identifying data present
-+ in an add-on board resident EEPROM, more details on the mikroBUS
-+ driver support and discussion can be found in this eLinux wiki :
-+ elinux.org/Mikrobus
-+
-+
-+ Say Y here to enable support for this driver.
-+
-+ To compile this code as a module, chose M here: the module
-+ will be called mikrobus.ko
-diff --git a/drivers/misc/mikrobus/Makefile b/drivers/misc/mikrobus/Makefile
-new file mode 100644
-index 000000000000..0dfd04eabaf6
---- /dev/null
-+++ b/drivers/misc/mikrobus/Makefile
-@@ -0,0 +1,6 @@
-+# SPDX-License-Identifier: GPL-2.0
-+# mikroBUS Core
-+
-+obj-$(CONFIG_MIKROBUS) += mikrobus.o
-+mikrobus-y := mikrobus_core.o mikrobus_manifest.o
-+obj-$(CONFIG_MIKROBUS) += mikrobus_id.o
-\ No newline at end of file
-diff --git a/drivers/misc/mikrobus/mikrobus_core.c b/drivers/misc/mikrobus/mikrobus_core.c
-new file mode 100644
-index 000000000000..4e24f980f18a
---- /dev/null
-+++ b/drivers/misc/mikrobus/mikrobus_core.c
-@@ -0,0 +1,1032 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * mikroBUS driver for instantiating add-on
-+ * board devices with an identifier EEPROM
-+ *
-+ * Copyright 2021 Vaishnav M A, BeagleBoard.org Foundation.
-+ * Copyright 2021 Zoran Stojsavljevic, zoran.stojsavljevic@gmail.com
-+ */
-+
-+#define pr_fmt(fmt) "mikrobus:%s: " fmt, __func__
-+
-+#include <linux/err.h>
-+#include <linux/errno.h>
-+#include <linux/idr.h>
-+#include <linux/init.h>
-+#include <linux/jump_label.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/mutex.h>
-+#include <linux/w1.h>
-+#include <linux/w1-gpio.h>
-+#include <linux/device.h>
-+#include <linux/i2c.h>
-+#include <linux/greybus.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio/machine.h>
-+#include <linux/gpio/driver.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/nvmem-provider.h>
-+#include <linux/interrupt.h>
-+#include <linux/spi/spi.h>
-+#include <linux/serdev.h>
-+#include <linux/property.h>
-+#include <linux/platform_device.h>
-+#include <linux/debugfs.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/regulator/fixed.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/clk-provider.h>
-+#include <linux/greybus/greybus_manifest.h>
-+#include <linux/greybus/gbphy.h>
-+#include <linux/mikrobus.h>
-+
-+#include "mikrobus_manifest.h"
-+
-+#define MIKROBUS_ID_USER_EEPROM_ADDR 0x0A0A
-+
-+static DEFINE_MUTEX(core_lock);
-+static DEFINE_IDR(mikrobus_port_idr);
-+static struct class_compat *mikrobus_port_compat_class;
-+int __mikrobus_first_dynamic_bus_num;
-+static bool is_registered;
-+static int mikrobus_port_id_eeprom_probe(struct mikrobus_port *port);
-+
-+const char *MIKROBUS_PINCTRL_STR[] = {"pwm", "uart", "i2c", "spi"};
-+
-+struct bus_type mikrobus_bus_type = {
-+ .name = "mikrobus",
-+};
-+EXPORT_SYMBOL_GPL(mikrobus_bus_type);
-+
-+int mikrobus_port_scan_eeprom(struct mikrobus_port *port)
-+{
-+ struct addon_board_info *board;
-+ int manifest_size;
-+ char header[12];
-+ int retval;
-+ uint16_t manifest_start_addr;
-+ char *buf;
-+
-+ if(port->skip_scan)
-+ return -EINVAL;
-+
-+ retval = nvmem_device_read(port->eeprom, MIKROBUS_ID_USER_EEPROM_ADDR, 1, header);
-+ if (retval != 1) {
-+ dev_err(&port->dev, "failed to fetch manifest start address %d\n",
-+ retval);
-+ return -EINVAL;
-+ }
-+ manifest_start_addr = header[0] << 8;
-+ pr_info("manifest start address is 0x%x \n", manifest_start_addr);
-+
-+ retval = nvmem_device_read(port->eeprom, manifest_start_addr, 12, header);
-+ if (retval != 12) {
-+ dev_err(&port->dev, "failed to fetch manifest header %d\n",
-+ retval);
-+ return -EINVAL;
-+ }
-+ manifest_size = mikrobus_manifest_header_validate(header, 12);
-+ if (manifest_size < 0) {
-+ dev_err(&port->dev, "invalid manifest size %d\n",
-+ manifest_size);
-+ return -EINVAL;
-+ }
-+ buf = kzalloc(manifest_size, GFP_KERNEL);
-+ if (!buf)
-+ return -ENOMEM;
-+ retval = nvmem_device_read(port->eeprom, manifest_start_addr, manifest_size, buf);
-+ if (retval != manifest_size) {
-+ dev_err(&port->dev, "failed to fetch manifest %d\n", retval);
-+ retval = -EINVAL;
-+ goto err_free_buf;
-+ }
-+ board = kzalloc(sizeof(*board), GFP_KERNEL);
-+ if (!board) {
-+ retval = -ENOMEM;
-+ goto err_free_buf;
-+ }
-+ w1_reset_bus(port->w1_master);
-+ /* set RST HIGH */
-+ gpiod_direction_output(port->gpios->desc[MIKROBUS_PIN_RST], 1);
-+ set_bit(W1_ABORT_SEARCH, &port->w1_master->flags);
-+ INIT_LIST_HEAD(&board->manifest_descs);
-+ INIT_LIST_HEAD(&board->devices);
-+ retval = mikrobus_manifest_parse(board, buf, manifest_size);
-+ if (!retval) {
-+ dev_err(&port->dev, "failed to parse manifest, size %d\n",
-+ manifest_size);
-+ retval = -EINVAL;
-+ goto err_free_board;
-+ }
-+ retval = mikrobus_board_register(port, board);
-+ if (retval) {
-+ dev_err(&port->dev, "failed to register board %s\n",
-+ board->name);
-+ goto err_free_board;
-+ }
-+ kfree(buf);
-+ return 0;
-+err_free_board:
-+ kfree(board);
-+err_free_buf:
-+ kfree(buf);
-+ return retval;
-+}
-+EXPORT_SYMBOL_GPL(mikrobus_port_scan_eeprom);
-+
-+static ssize_t name_show(struct device *dev, struct device_attribute *attr,
-+ char *buf)
-+{
-+ return sprintf(buf, "%s\n", to_mikrobus_port(dev)->name);
-+}
-+static DEVICE_ATTR_RO(name);
-+
-+static ssize_t new_device_store(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct mikrobus_port *port = to_mikrobus_port(dev);
-+ struct addon_board_info *board;
-+ int retval;
-+
-+ if (port->board) {
-+ dev_err(dev, "already has board registered\n");
-+ return -EBUSY;
-+ }
-+
-+ board = kzalloc(sizeof(*board), GFP_KERNEL);
-+ if (!board)
-+ return -ENOMEM;
-+ INIT_LIST_HEAD(&board->manifest_descs);
-+ INIT_LIST_HEAD(&board->devices);
-+ retval = mikrobus_manifest_parse(board, (void *)buf, count);
-+ if (!retval) {
-+ dev_err(dev, "failed to parse manifest\n");
-+ retval = -EINVAL;
-+ goto err_free_board;
-+ }
-+ retval = mikrobus_board_register(port, board);
-+ if (retval) {
-+ dev_err(dev, "failed to register board %s\n", board->name);
-+ retval = -EINVAL;
-+ goto err_free_board;
-+ }
-+ return count;
-+err_free_board:
-+ kfree(board);
-+ return retval;
-+}
-+static DEVICE_ATTR_WO(new_device);
-+
-+static ssize_t delete_device_store(struct device *dev, struct device_attribute *attr,
-+ const char *buf, size_t count)
-+{
-+ struct mikrobus_port *port = to_mikrobus_port(dev);
-+ unsigned long id;
-+
-+ if (kstrtoul(buf, 0, &id)) {
-+ dev_err(dev, "cannot parse board id");
-+ return -EINVAL;
-+ }
-+ if (!port->board) {
-+ dev_err(dev, "does not have registered boards");
-+ return -ENODEV;
-+ }
-+ mikrobus_board_unregister(port, port->board);
-+ return count;
-+}
-+static DEVICE_ATTR_IGNORE_LOCKDEP(delete_device, 0200, NULL, delete_device_store);
-+
-+static struct attribute *mikrobus_port_attrs[] = {
-+ &dev_attr_new_device.attr, &dev_attr_delete_device.attr, &dev_attr_name.attr, NULL};
-+ATTRIBUTE_GROUPS(mikrobus_port);
-+
-+static void mikrobus_port_release(struct device *dev)
-+{
-+ struct mikrobus_port *port = to_mikrobus_port(dev);
-+
-+ mutex_lock(&core_lock);
-+ idr_remove(&mikrobus_port_idr, port->id);
-+ mutex_unlock(&core_lock);
-+ kfree(port);
-+}
-+
-+struct device_type mikrobus_port_type = {
-+ .groups = mikrobus_port_groups,
-+ .release = mikrobus_port_release,
-+};
-+EXPORT_SYMBOL_GPL(mikrobus_port_type);
-+
-+static int mikrobus_w1_master_match(struct device *dev, const void *data)
-+{
-+ struct mikrobus_port *port;
-+
-+ if(dev->type != &mikrobus_port_type)
-+ return 0;
-+
-+ port = to_mikrobus_port(dev);
-+
-+ return port->w1_master == data;
-+}
-+
-+struct mikrobus_port *mikrobus_find_port_by_w1_master(struct w1_master *master)
-+{
-+ struct device *dev;
-+
-+ dev = bus_find_device(&mikrobus_bus_type, NULL, master, mikrobus_w1_master_match);
-+ if (!dev)
-+ return NULL;
-+
-+ return (dev->type == &mikrobus_port_type) ? to_mikrobus_port(dev) : NULL;
-+}
-+EXPORT_SYMBOL(mikrobus_find_port_by_w1_master);
-+
-+int mikrobus_port_pinctrl_select(struct mikrobus_port *port)
-+{
-+ struct pinctrl_state *state;
-+ int retval;
-+ int i;
-+
-+ for (i = 0; i < MIKROBUS_NUM_PINCTRL_STATE; i++) {
-+ state = pinctrl_lookup_state(port->pinctrl,
-+ port->pinctrl_selected[i]);
-+ if (!IS_ERR(state)) {
-+ retval = pinctrl_select_state(port->pinctrl, state);
-+ pr_info("setting pinctrl %s\n",
-+ port->pinctrl_selected[i]);
-+ if (retval != 0) {
-+ dev_err(&port->dev, "failed to select state %s\n",
-+ port->pinctrl_selected[i]);
-+ return retval;
-+ }
-+ } else {
-+ dev_err(&port->dev, "failed to find state %s\n",
-+ port->pinctrl_selected[i]);
-+ return PTR_ERR(state);
-+ }
-+ }
-+
-+ return retval;
-+}
-+EXPORT_SYMBOL_GPL(mikrobus_port_pinctrl_select);
-+
-+static int mikrobus_port_pinctrl_setup(struct mikrobus_port *port, struct addon_board_info *board)
-+{
-+ int retval;
-+ int i;
-+
-+ for (i = 0; i < MIKROBUS_NUM_PINCTRL_STATE; i++) {
-+ switch (i) {
-+ case MIKROBUS_PINCTRL_PWM:
-+ if (board->pin_state[MIKROBUS_PIN_PWM] == MIKROBUS_STATE_PWM)
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], PINCTRL_STATE_DEFAULT);
-+ else
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], MIKROBUS_PINCTRL_STATE_GPIO);
-+ break;
-+ case MIKROBUS_PINCTRL_UART:
-+ if (board->pin_state[MIKROBUS_PIN_RX] == MIKROBUS_STATE_UART)
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], PINCTRL_STATE_DEFAULT);
-+ else
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], MIKROBUS_PINCTRL_STATE_GPIO);
-+ break;
-+ case MIKROBUS_PINCTRL_I2C:
-+ if (board->pin_state[MIKROBUS_PIN_SCL] == MIKROBUS_STATE_I2C)
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], PINCTRL_STATE_DEFAULT);
-+ else
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], MIKROBUS_PINCTRL_STATE_GPIO);
-+ break;
-+ case MIKROBUS_PINCTRL_SPI:
-+ if (board->pin_state[MIKROBUS_PIN_MOSI] == MIKROBUS_STATE_SPI)
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], PINCTRL_STATE_DEFAULT);
-+ else
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], MIKROBUS_PINCTRL_STATE_GPIO);
-+ break;
-+ }
-+ }
-+
-+ retval = mikrobus_port_pinctrl_select(port);
-+ if (retval)
-+ dev_err(&port->dev, "failed to select pinctrl states [%d]", retval);
-+ return retval;
-+}
-+
-+static int mikrobus_irq_get(struct mikrobus_port *port, int irqno,
-+ int irq_type)
-+{
-+ int irq;
-+
-+ if (irqno > port->gpios->ndescs - 1) {
-+ dev_err(&port->dev, "GPIO %d does not exist", irqno);
-+ return -ENODEV;
-+ }
-+
-+ irq = gpiod_to_irq(port->gpios->desc[irqno]);
-+ if (irq < 0) {
-+ dev_err(&port->dev, "could not get irq %d", irqno);
-+ return -EINVAL;
-+ }
-+ irq_set_irq_type(irq, irq_type);
-+ return irq;
-+}
-+
-+static int mikrobus_gpio_setup(struct gpio_desc *gpio, int gpio_state)
-+{
-+ int retval;
-+
-+ switch (gpio_state) {
-+ case MIKROBUS_STATE_INPUT:
-+ retval = gpiod_direction_input(gpio);
-+ break;
-+ case MIKROBUS_STATE_OUTPUT_HIGH:
-+ retval = gpiod_direction_output(gpio, 1);
-+ break;
-+ case MIKROBUS_STATE_OUTPUT_LOW:
-+ retval = gpiod_direction_output(gpio, 0);
-+ break;
-+ case MIKROBUS_STATE_PWM:
-+ case MIKROBUS_STATE_SPI:
-+ case MIKROBUS_STATE_I2C:
-+ default:
-+ return 0;
-+ }
-+ return retval;
-+}
-+
-+static char *mikrobus_gpio_chip_name_get(struct mikrobus_port *port, int gpio)
-+{
-+ char *name;
-+ struct gpio_chip *gpiochip;
-+
-+ if (gpio > port->gpios->ndescs - 1)
-+ return NULL;
-+
-+ gpiochip = gpiod_to_chip(port->gpios->desc[gpio]);
-+ name = kmemdup(gpiochip->label, MIKROBUS_NAME_SIZE, GFP_KERNEL);
-+ return name;
-+}
-+
-+static int mikrobus_gpio_hwnum_get(struct mikrobus_port *port, int gpio)
-+{
-+ int hwnum;
-+ struct gpio_chip *gpiochip;
-+
-+ if (gpio > port->gpios->ndescs - 1)
-+ return -ENODEV;
-+
-+ gpiochip = gpiod_to_chip(port->gpios->desc[gpio]);
-+ hwnum = desc_to_gpio(port->gpios->desc[gpio]) - gpiochip->base;
-+ return hwnum;
-+}
-+
-+static void mikrobus_board_device_release_all(struct addon_board_info *info)
-+{
-+ struct board_device_info *dev;
-+ struct board_device_info *next;
-+
-+ list_for_each_entry_safe(dev, next, &info->devices, links) {
-+ list_del(&dev->links);
-+ kfree(dev);
-+ }
-+}
-+
-+static struct software_node *software_node_alloc(const struct property_entry *properties)
-+{
-+ struct property_entry *props;
-+ struct software_node *node;
-+
-+ props = property_entries_dup(properties);
-+ if (IS_ERR(props))
-+ return ERR_CAST(props);
-+
-+ node = kzalloc(sizeof(*node), GFP_KERNEL);
-+ if (!node) {
-+ property_entries_free(props);
-+ return ERR_PTR(-ENOMEM);
-+ }
-+
-+ node->properties = props;
-+
-+ return node;
-+}
-+
-+static int mikrobus_device_register(struct mikrobus_port *port,
-+ struct board_device_info *dev, char *board_name)
-+{
-+ struct i2c_board_info *i2c;
-+ struct spi_device *spi;
-+ struct serdev_device *serdev;
-+ struct platform_device *pdev;
-+ struct gpiod_lookup_table *lookup;
-+ struct regulator_consumer_supply regulator;
-+ char devname[MIKROBUS_NAME_SIZE];
-+ int i;
-+ u64 *val;
-+
-+ dev_info(&port->dev, "registering device : %s", dev->drv_name);
-+
-+ if (dev->gpio_lookup) {
-+ lookup = dev->gpio_lookup;
-+ if (dev->protocol == GREYBUS_PROTOCOL_SPI) {
-+ snprintf(devname, sizeof(devname), "%s.%u",
-+ dev_name(&port->spi_mstr->dev),
-+ port->chip_select[dev->reg]);
-+ lookup->dev_id = kmemdup(devname, MIKROBUS_NAME_SIZE, GFP_KERNEL);
-+ } else if (dev->protocol == GREYBUS_PROTOCOL_RAW) {
-+ snprintf(devname, sizeof(devname), "%s.%u",
-+ dev->drv_name, dev->reg);
-+ lookup->dev_id = kmemdup(devname, MIKROBUS_NAME_SIZE, GFP_KERNEL);
-+ } else
-+ lookup->dev_id = dev->drv_name;
-+ dev_info(&port->dev, " adding lookup table : %s\n",
-+ lookup->dev_id);
-+ for (i = 0; i < dev->num_gpio_resources; i++) {
-+ lookup->table[i].key =
-+ mikrobus_gpio_chip_name_get(port,
-+ lookup->table[i].chip_hwnum);
-+ lookup->table[i].chip_hwnum =
-+ mikrobus_gpio_hwnum_get(port,
-+ lookup->table[i].chip_hwnum);
-+ }
-+ gpiod_add_lookup_table(lookup);
-+ }
-+ if (dev->regulators) {
-+ if (dev->protocol == GREYBUS_PROTOCOL_SPI) {
-+ snprintf(devname, sizeof(devname), "%s.%u",
-+ dev_name(&port->spi_mstr->dev),
-+ port->chip_select[dev->reg]);
-+ regulator.dev_name = kmemdup(devname, MIKROBUS_NAME_SIZE, GFP_KERNEL);
-+ } else if (dev->protocol == GREYBUS_PROTOCOL_RAW) {
-+ snprintf(devname, sizeof(devname), "%s.%u",
-+ dev->drv_name, dev->reg);
-+ regulator.dev_name = kmemdup(devname, MIKROBUS_NAME_SIZE, GFP_KERNEL);
-+ } else
-+ regulator.dev_name = dev->drv_name;
-+
-+ for (i = 0; i < dev->num_regulators; i++) {
-+ val = dev->regulators[i].value.u64_data;
-+ regulator.supply = kmemdup(dev->regulators[i].name, MIKROBUS_NAME_SIZE, GFP_KERNEL);
-+ dev_info(&port->dev, " adding fixed regulator %llu uv, %s for %s\n",
-+ *val, regulator.supply, regulator.dev_name);
-+ regulator_register_always_on(0, dev->regulators[i].name, ®ulator,
-+ 1, *val);
-+ }
-+ }
-+ switch (dev->protocol) {
-+ case GREYBUS_PROTOCOL_SPI:
-+ spi = spi_alloc_device(port->spi_mstr);
-+ if (!spi)
-+ return -ENOMEM;
-+ strncpy(spi->modalias, dev->drv_name, sizeof(spi->modalias) - 1);
-+ if (dev->irq)
-+ spi->irq = mikrobus_irq_get(port, dev->irq, dev->irq_type);
-+ if (dev->properties)
-+ device_add_properties(&spi->dev, dev->properties);
-+ spi->chip_select = port->chip_select[dev->reg];
-+ spi->max_speed_hz = dev->max_speed_hz;
-+ spi->mode = dev->mode;
-+ if (dev->clocks) {
-+ for (i = 0; i < dev->num_clocks; i++) {
-+ val = dev->clocks[i].value.u64_data;
-+ dev_info(&port->dev, " adding fixed clock %s, %llu hz\n",
-+ dev->clocks[i].name, *val);
-+ //failing: under debug
-+ clk_register_fixed_rate(&spi->dev, dev->clocks[i].name, devname, 0, *val);
-+ }
-+ }
-+ spi_add_device(spi);
-+ dev->dev_client = (void *) spi;
-+ break;
-+ case GREYBUS_PROTOCOL_I2C:
-+ i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
-+ if (!i2c)
-+ return -ENOMEM;
-+ strncpy(i2c->type, dev->drv_name, sizeof(i2c->type) - 1);
-+ if (dev->irq)
-+ i2c->irq = mikrobus_irq_get(port, dev->irq, dev->irq_type);
-+ if (dev->properties)
-+ i2c->swnode = software_node_alloc(dev->properties);
-+ i2c->addr = dev->reg;
-+ dev->dev_client = (void *) i2c_new_client_device(port->i2c_adap, i2c);
-+ break;
-+ case GREYBUS_PROTOCOL_RAW:
-+ pdev = platform_device_alloc(dev->drv_name, 0);
-+ if (!pdev)
-+ return -ENOMEM;
-+ if (dev->properties)
-+ platform_device_add_properties(pdev, dev->properties);
-+ dev->dev_client = pdev;
-+ platform_device_add(dev->dev_client);
-+ break;
-+ case GREYBUS_PROTOCOL_UART:
-+ serdev = serdev_device_alloc(port->ser_ctrl);
-+ if (!serdev)
-+ return -ENOMEM;
-+ strncpy(serdev->modalias, dev->drv_name, sizeof(serdev->modalias) - 1);
-+ if (dev->properties)
-+ device_add_properties(&serdev->dev, dev->properties);
-+ dev->dev_client = serdev;
-+ serdev_device_add(serdev);
-+ break;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+static void mikrobus_device_unregister(struct mikrobus_port *port,
-+ struct board_device_info *dev, char *board_name)
-+{
-+ dev_info(&port->dev, "removing device %s\n", dev->drv_name);
-+ if (dev->gpio_lookup) {
-+ gpiod_remove_lookup_table(dev->gpio_lookup);
-+ kfree(dev->gpio_lookup);
-+ }
-+ kfree(dev->properties);
-+ switch (dev->protocol) {
-+ case GREYBUS_PROTOCOL_SPI:
-+ spi_unregister_device((struct spi_device *)dev->dev_client);
-+ break;
-+ case GREYBUS_PROTOCOL_I2C:
-+ i2c_unregister_device((struct i2c_client *)dev->dev_client);
-+ break;
-+ case GREYBUS_PROTOCOL_RAW:
-+ platform_device_unregister((struct platform_device *)dev->dev_client);
-+ break;
-+ case GREYBUS_PROTOCOL_UART:
-+ serdev_device_remove((struct serdev_device *)dev->dev_client);
-+ break;
-+ }
-+}
-+
-+int mikrobus_board_register(struct mikrobus_port *port, struct addon_board_info *board)
-+{
-+ struct board_device_info *devinfo;
-+ struct board_device_info *next;
-+ int retval;
-+ int i;
-+
-+ if (WARN_ON(list_empty(&board->devices)))
-+ return false;
-+ if (port->pinctrl) {
-+ retval = mikrobus_port_pinctrl_setup(port, board);
-+ if (retval)
-+ dev_err(&port->dev, "failed to setup pinctrl state [%d]", retval);
-+
-+ }
-+ if (port->gpios) {
-+ for (i = 0; i < port->gpios->ndescs; i++) {
-+ retval = mikrobus_gpio_setup(port->gpios->desc[i], board->pin_state[i]);
-+ if (retval)
-+ dev_err(&port->dev, "failed to setup gpio %d, state %d",
-+ i, board->pin_state[i]);
-+ }
-+ }
-+ list_for_each_entry_safe(devinfo, next, &board->devices, links)
-+ mikrobus_device_register(port, devinfo, board->name);
-+ port->board = board;
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(mikrobus_board_register);
-+
-+void mikrobus_board_unregister(struct mikrobus_port *port, struct addon_board_info *board)
-+{
-+ struct board_device_info *devinfo;
-+ struct board_device_info *next;
-+
-+ if (WARN_ON(list_empty(&board->devices)))
-+ return;
-+ port->board = NULL;
-+ list_for_each_entry_safe(devinfo, next, &board->devices, links)
-+ mikrobus_device_unregister(port, devinfo, board->name);
-+ mikrobus_board_device_release_all(board);
-+ kfree(board);
-+ port->board = NULL;
-+}
-+EXPORT_SYMBOL_GPL(mikrobus_board_unregister);
-+
-+static int mikrobus_port_id_eeprom_probe(struct mikrobus_port *port)
-+{
-+ struct w1_bus_master *bm;
-+ struct gpiod_lookup_table *lookup;
-+ struct platform_device *mikrobus_id_eeprom_w1_device;
-+ static struct w1_gpio_platform_data *mikrobus_id_eeprom_w1_pdata;
-+ char devname[MIKROBUS_NAME_SIZE];
-+ char drvname[MIKROBUS_NAME_SIZE] = "w1-gpio";
-+ int retval;
-+ int i;
-+
-+ mikrobus_id_eeprom_w1_device = kzalloc(sizeof(*mikrobus_id_eeprom_w1_device), GFP_KERNEL);
-+ if (!mikrobus_id_eeprom_w1_device)
-+ return -ENOMEM;
-+
-+ mikrobus_id_eeprom_w1_pdata = kzalloc(sizeof(*mikrobus_id_eeprom_w1_pdata), GFP_KERNEL);
-+ if (!mikrobus_id_eeprom_w1_pdata)
-+ return -ENOMEM;
-+
-+ mikrobus_id_eeprom_w1_pdata->pullup_gpiod = NULL;
-+ mikrobus_id_eeprom_w1_device->name = kmemdup(drvname, MIKROBUS_NAME_SIZE, GFP_KERNEL);
-+ mikrobus_id_eeprom_w1_device->dev.platform_data = mikrobus_id_eeprom_w1_pdata;
-+
-+ sprintf(port->pinctrl_selected[MIKROBUS_PINCTRL_SPI], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[MIKROBUS_PINCTRL_SPI], MIKROBUS_PINCTRL_STATE_GPIO);
-+
-+ retval = mikrobus_port_pinctrl_select(port);
-+ /* set RST LOW */
-+ gpiod_direction_output(port->gpios->desc[MIKROBUS_PIN_RST], 0);
-+
-+ lookup = kzalloc(struct_size(lookup, table, 1),
-+ GFP_KERNEL);
-+ if (!lookup)
-+ return -ENOMEM;
-+ snprintf(devname, sizeof(devname), "%s.%u",
-+ mikrobus_id_eeprom_w1_device->name,
-+ port->id);
-+ mikrobus_id_eeprom_w1_device->id = port->id;
-+ lookup->dev_id = kmemdup(devname, MIKROBUS_NAME_SIZE, GFP_KERNEL);
-+ lookup->table[0].key = mikrobus_gpio_chip_name_get(port,
-+ MIKROBUS_PIN_CS);
-+ lookup->table[0].flags = GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN;
-+ lookup->table[0].chip_hwnum = mikrobus_gpio_hwnum_get(port,
-+ MIKROBUS_PIN_CS);
-+ gpiod_add_lookup_table(lookup);
-+ platform_device_register(mikrobus_id_eeprom_w1_device);
-+ port->w1_gpio = mikrobus_id_eeprom_w1_device;
-+ bm = (struct w1_bus_master *) platform_get_drvdata(mikrobus_id_eeprom_w1_device);
-+ if(bm) {
-+ port->w1_master = w1_find_master_device(bm);
-+ if(!port->w1_master){
-+ dev_err(&port->dev, "failed to find W1 GPIO master, port [%s]\n",
-+ port->name);
-+ gpiod_remove_lookup_table(lookup);
-+ kfree(lookup);
-+ return -ENODEV;
-+ }
-+ }
-+ return 0;
-+}
-+
-+int mikrobus_port_register(struct mikrobus_port *port)
-+{
-+ struct device *dev = &port->dev;
-+ int retval;
-+ int id;
-+
-+ if (WARN_ON(!is_registered))
-+ return -EAGAIN;
-+
-+ if (dev->of_node) {
-+ id = of_alias_get_id(dev->of_node, "mikrobus");
-+ if (id >= 0) {
-+ port->id = id;
-+ mutex_lock(&core_lock);
-+ id = idr_alloc(&mikrobus_port_idr, port, port->id, port->id + 1,
-+ GFP_KERNEL);
-+ mutex_unlock(&core_lock);
-+ if (WARN(id < 0, "couldn't get idr"))
-+ return id == -ENOSPC ? -EBUSY : id;
-+ }
-+ } else {
-+ mutex_lock(&core_lock);
-+ id = idr_alloc(&mikrobus_port_idr, port, __mikrobus_first_dynamic_bus_num, 0,
-+ GFP_KERNEL);
-+ mutex_unlock(&core_lock);
-+ if (id < 0)
-+ return id;
-+ port->id = id;
-+ }
-+ port->dev.bus = &mikrobus_bus_type;
-+ port->dev.type = &mikrobus_port_type;
-+ strncpy(port->name, "mikrobus-port", sizeof(port->name) - 1);
-+ dev_set_name(&port->dev, "mikrobus-%d", port->id);
-+ pr_info("registering port mikrobus-%d ", port->id);
-+ retval = device_register(&port->dev);
-+ if (retval) {
-+ pr_err("port '%d': can't register device (%d)", port->id, retval);
-+ put_device(&port->dev);
-+ return retval;
-+ }
-+ retval = class_compat_create_link(mikrobus_port_compat_class, &port->dev,
-+ port->dev.parent);
-+ if (retval)
-+ dev_warn(&port->dev, "failed to create compatibility class link\n");
-+ if (!port->w1_master && !port->disable_eeprom) {
-+ dev_info(&port->dev, "mikrobus port %d eeprom empty probing default eeprom\n",
-+ port->id);
-+ mutex_lock(&core_lock);
-+ retval = mikrobus_port_id_eeprom_probe(port);
-+ mutex_unlock(&core_lock);
-+ }
-+ return retval;
-+}
-+EXPORT_SYMBOL_GPL(mikrobus_port_register);
-+
-+void mikrobus_port_delete(struct mikrobus_port *port)
-+{
-+ struct mikrobus_port *found;
-+
-+ mutex_lock(&core_lock);
-+ found = idr_find(&mikrobus_port_idr, port->id);
-+ mutex_unlock(&core_lock);
-+ if (found != port) {
-+ pr_err("port [%s] not registered", port->name);
-+ return;
-+ }
-+ if (port->board) {
-+ dev_err(&port->dev, "attempting to delete port with registered boards, port [%s]\n",
-+ port->name);
-+ return;
-+ }
-+
-+ if (port->eeprom) {
-+ nvmem_device_put(port->eeprom);
-+ platform_device_unregister(port->w1_gpio);
-+ }
-+
-+ class_compat_remove_link(mikrobus_port_compat_class, &port->dev,
-+ port->dev.parent);
-+ device_unregister(&port->dev);
-+ mutex_lock(&core_lock);
-+ idr_remove(&mikrobus_port_idr, port->id);
-+ mutex_unlock(&core_lock);
-+ memset(&port->dev, 0, sizeof(port->dev));
-+}
-+EXPORT_SYMBOL_GPL(mikrobus_port_delete);
-+
-+int mikrobus_port_gb_register(struct gbphy_host *host, void *manifest_blob, size_t manifest_size)
-+{
-+ struct gb_bundle *bundle = host->bundle;
-+ struct addon_board_info *board;
-+ struct gbphy_device *gbphy_dev, *temp;
-+ struct gb_i2c_device *gb_i2c_dev;
-+ struct gb_connection *spi_connection;
-+ struct gb_gpio_controller *ggc;
-+ struct mikrobus_port *port;
-+ struct gpio_desc *desc;
-+ struct gpio_descs *descs;
-+ int retval;
-+
-+ if (bundle->num_cports == 0)
-+ return -ENODEV;
-+
-+ port = kzalloc(sizeof(*port), GFP_KERNEL);
-+ if (!port)
-+ return -ENOMEM;
-+
-+ pr_info("mikrobus gb_probe , num cports= %zu, manifest_size %u \n", bundle->num_cports, manifest_size);
-+ list_for_each_entry_safe(gbphy_dev, temp, &host->devices, list) {
-+ pr_info("protocol added %d", gbphy_dev->cport_desc->protocol_id);
-+ if(gbphy_dev->cport_desc->protocol_id != GREYBUS_PROTOCOL_I2C &&
-+ gbphy_dev->cport_desc->protocol_id != GREYBUS_PROTOCOL_SPI &&
-+ gbphy_dev->cport_desc->protocol_id != GREYBUS_PROTOCOL_GPIO){
-+ pr_info("only I2C , GPIO and SPI Protocol Currently Supported");
-+ kfree(port);
-+ continue;
-+ }
-+ port->dev.parent = &gbphy_dev->dev;
-+ if(gbphy_dev->cport_desc->protocol_id == GREYBUS_PROTOCOL_I2C){
-+ gb_i2c_dev = (struct gb_i2c_device *) gb_gbphy_get_data(gbphy_dev);
-+ port->i2c_adap = &gb_i2c_dev->adapter;
-+
-+ }
-+ else if(gbphy_dev->cport_desc->protocol_id == GREYBUS_PROTOCOL_SPI){
-+ spi_connection = gb_gbphy_get_data(gbphy_dev);
-+ port->spi_mstr = (struct spi_master *)gb_connection_get_data(spi_connection);
-+ }
-+ else if(gbphy_dev->cport_desc->protocol_id == GREYBUS_PROTOCOL_GPIO){
-+ ggc = (struct gb_gpio_controller *) gb_gbphy_get_data(gbphy_dev);
-+ port->gpios = kzalloc(struct_size(descs, desc, 12), GFP_KERNEL);
-+ port->gpios->desc[0] = gpio_to_desc( ggc->chip.base + 7);//PWM GPIO
-+ port->gpios->desc[1] = gpio_to_desc( ggc->chip.base + 20); //INT GPIO
-+ port->gpios->desc[10] = gpio_to_desc( ggc->chip.base + 19); //RST GPIO
-+ }
-+ }
-+ port->disable_eeprom = 1;
-+ retval = mikrobus_port_register(port);
-+ if (retval) {
-+ pr_err("port : can't register port [%d]\n", retval);
-+ }
-+
-+ board = kzalloc(sizeof(*board), GFP_KERNEL);
-+ if (!board) {
-+ retval = -ENOMEM;
-+ goto err_free_buf;
-+ }
-+ INIT_LIST_HEAD(&board->manifest_descs);
-+ INIT_LIST_HEAD(&board->devices);
-+ retval = mikrobus_manifest_parse(board, manifest_blob, manifest_size);
-+ if (!retval) {
-+ dev_err(&port->dev, "failed to parse manifest, size %lu\n",
-+ manifest_size);
-+ retval = -EINVAL;
-+ goto err_free_board;
-+ }
-+ retval = mikrobus_board_register(port, board);
-+ if (retval) {
-+ dev_err(&port->dev, "failed to register board %s\n",
-+ board->name);
-+ goto err_free_board;
-+ }
-+ return 0;
-+err_free_board:
-+ kfree(board);
-+err_free_buf:
-+ kfree(manifest_blob);
-+ return retval;
-+}
-+EXPORT_SYMBOL_GPL(mikrobus_port_gb_register);
-+
-+static int mikrobus_port_probe_pinctrl_setup(struct mikrobus_port *port)
-+{
-+ struct pinctrl_state *state;
-+ struct device *dev = port->dev.parent;
-+ int retval, i;
-+
-+ state = pinctrl_lookup_state(port->pinctrl, PINCTRL_STATE_DEFAULT);
-+ if (!IS_ERR(state)) {
-+ retval = pinctrl_select_state(port->pinctrl, state);
-+ if (retval != 0) {
-+ dev_err(dev, "Failed to select state %s\n",
-+ PINCTRL_STATE_DEFAULT);
-+ return retval;
-+ }
-+ } else {
-+ dev_err(dev, "failed to find state %s\n",
-+ PINCTRL_STATE_DEFAULT);
-+ return PTR_ERR(state);
-+ }
-+
-+ for (i = 0; i < MIKROBUS_NUM_PINCTRL_STATE; i++) {
-+ port->pinctrl_selected[i] =
-+ kmalloc(MIKROBUS_PINCTRL_NAME_SIZE, GFP_KERNEL);
-+ sprintf(port->pinctrl_selected[i], "%s_%s",
-+ MIKROBUS_PINCTRL_STR[i], PINCTRL_STATE_DEFAULT);
-+ }
-+
-+ retval = mikrobus_port_pinctrl_select(port);
-+ if (retval)
-+ dev_err(dev, "failed to select pinctrl states [%d]", retval);
-+ return retval;
-+}
-+
-+static int mikrobus_port_probe(struct platform_device *pdev)
-+{
-+ struct mikrobus_port *port;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *i2c_adap_np;
-+ struct device_node *uart_np;
-+ int retval;
-+ u32 val;
-+
-+ port = kzalloc(sizeof(*port), GFP_KERNEL);
-+ if (!port)
-+ return -ENOMEM;
-+
-+ i2c_adap_np = of_parse_phandle(dev->of_node, "i2c-adapter", 0);
-+ if (!i2c_adap_np) {
-+ dev_err(dev, "cannot parse i2c-adapter\n");
-+ retval = -ENODEV;
-+ goto err_port;
-+ }
-+ port->i2c_adap = of_find_i2c_adapter_by_node(i2c_adap_np);
-+ of_node_put(i2c_adap_np);
-+ retval = device_property_read_u32(dev, "spi-master", &val);
-+ if (retval) {
-+ dev_err(dev, "failed to get spi-master [%d]\n", retval);
-+ goto err_port;
-+ }
-+ port->spi_mstr = spi_busnum_to_master(val);
-+ retval = device_property_read_u32_array(dev, "spi-cs",
-+ port->chip_select, 2);
-+ if (retval) {
-+ dev_err(dev, "failed to get spi-cs [%d]\n", retval);
-+ goto err_port;
-+ }
-+ uart_np = of_parse_phandle(dev->of_node, "uart", 0);
-+ if (!uart_np) {
-+ dev_err(dev, "cannot parse uart\n");
-+ retval = -ENODEV;
-+ goto err_port;
-+ }
-+ port->ser_ctrl = of_find_serdev_controller_by_node(uart_np);
-+ of_node_put(uart_np);
-+ //port->pwm = devm_pwm_get(dev, NULL);
-+ //if (IS_ERR(port->pwm)) {
-+ // retval = PTR_ERR(port->pwm);
-+ // if (retval != -EPROBE_DEFER)
-+ // dev_err(dev, "failed to request PWM device [%d]\n",
-+ // retval);
-+ // goto err_port;
-+ //}
-+ port->gpios = gpiod_get_array(dev, "mikrobus", GPIOD_OUT_LOW);
-+ if (IS_ERR(port->gpios)) {
-+ retval = PTR_ERR(port->gpios);
-+ dev_err(dev, "failed to get gpio array [%d]\n", retval);
-+ goto err_port;
-+ }
-+ port->pinctrl = devm_pinctrl_get(dev);
-+ if (IS_ERR(port->pinctrl)) {
-+ retval = PTR_ERR(port->pinctrl);
-+ dev_err(dev, "failed to get pinctrl [%d]\n", retval);
-+ goto err_port;
-+ }
-+ port->dev.parent = dev;
-+ port->dev.of_node = pdev->dev.of_node;
-+
-+ retval = mikrobus_port_probe_pinctrl_setup(port);
-+ if (retval) {
-+ dev_err(dev, "failed to setup pinctrl [%d]\n", retval);
-+ goto err_port;
-+ }
-+
-+ retval = mikrobus_port_register(port);
-+ if (retval) {
-+ pr_err("port : can't register port [%d]\n", retval);
-+ goto err_port;
-+ }
-+ platform_set_drvdata(pdev, port);
-+ return 0;
-+err_port:
-+ kfree(port);
-+ return retval;
-+}
-+
-+static int mikrobus_port_remove(struct platform_device *pdev)
-+{
-+ struct mikrobus_port *port = platform_get_drvdata(pdev);
-+
-+ mikrobus_port_delete(port);
-+ return 0;
-+}
-+
-+static const struct of_device_id mikrobus_port_of_match[] = {
-+ {.compatible = "linux,mikrobus"},
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mikrobus_port_of_match);
-+
-+static struct platform_driver mikrobus_port_driver = {
-+ .probe = mikrobus_port_probe,
-+ .remove = mikrobus_port_remove,
-+ .driver = {
-+ .name = "mikrobus",
-+ .of_match_table = of_match_ptr(mikrobus_port_of_match),
-+ },
-+};
-+
-+static int __init mikrobus_init(void)
-+{
-+ int retval;
-+
-+ retval = bus_register(&mikrobus_bus_type);
-+ if (retval) {
-+ pr_err("bus_register failed (%d)\n", retval);
-+ return retval;
-+ }
-+ mikrobus_port_compat_class = class_compat_register("mikrobus-port");
-+ if (!mikrobus_port_compat_class) {
-+ pr_err("class_compat register failed (%d)\n", retval);
-+ retval = -ENOMEM;
-+ goto class_err;
-+ }
-+ retval = of_alias_get_highest_id("mikrobus");
-+ if (retval >= __mikrobus_first_dynamic_bus_num)
-+ __mikrobus_first_dynamic_bus_num = retval + 1;
-+
-+ is_registered = true;
-+ retval = platform_driver_register(&mikrobus_port_driver);
-+ if (retval)
-+ pr_err("driver register failed [%d]\n", retval);
-+ return retval;
-+
-+class_err:
-+ bus_unregister(&mikrobus_bus_type);
-+ idr_destroy(&mikrobus_port_idr);
-+ is_registered = false;
-+ return retval;
-+}
-+subsys_initcall(mikrobus_init);
-+
-+static void __exit mikrobus_exit(void)
-+{
-+ platform_driver_unregister(&mikrobus_port_driver);
-+ bus_unregister(&mikrobus_bus_type);
-+ class_compat_unregister(mikrobus_port_compat_class);
-+ idr_destroy(&mikrobus_port_idr);
-+}
-+module_exit(mikrobus_exit);
-+
-+MODULE_AUTHOR("Vaishnav M A <vaishnav@beagleboard.org>");
-+MODULE_DESCRIPTION("mikroBUS main module");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/misc/mikrobus/mikrobus_id.c b/drivers/misc/mikrobus/mikrobus_id.c
-new file mode 100644
-index 000000000000..2b97342327d9
---- /dev/null
-+++ b/drivers/misc/mikrobus/mikrobus_id.c
-@@ -0,0 +1,197 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * mikrobus_id.c - w1 mikroBUS ID family EEPROM driver
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/device.h>
-+#include <linux/types.h>
-+#include <linux/delay.h>
-+
-+#include <linux/w1.h>
-+#include <linux/nvmem-provider.h>
-+
-+#include <linux/mikrobus.h>
-+
-+#define W1_EEPROM_MIKROBUS_ID 0x43
-+
-+#define W1_MIKROBUS_ID_EEPROM_SIZE 0x0A00
-+#define W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE 32
-+#define W1_MIKROBUS_ID_EEPROM_VERIFY_SCRATCH_SIZE 35
-+#define W1_MIKROBUS_ID_READ_EEPROM 0xF0
-+#define W1_MIKROBUS_ID_EEPROM_READ_RETRIES 10
-+#define W1_MIKROBUS_ID_EEPROM_WRITE_RETRIES 5
-+#define W1_MIKROBUS_ID_EEPROM_WRITE_SCRATCH 0x0F
-+#define W1_MIKROBUS_ID_EEPROM_READ_SCRATCH 0xAA
-+#define W1_MIKROBUS_ID_EEPROM_COPY_SCRATCH 0x55
-+#define W1_MIKROBUS_ID_EEPROM_TPROG_MS 20
-+
-+static int w1_mikrobus_id_readblock(struct w1_slave *sl, int off, int count, char *buf)
-+{
-+ u8 wrbuf[3];
-+ u8 *cmp;
-+ int tries = W1_MIKROBUS_ID_EEPROM_READ_RETRIES;
-+
-+ do {
-+ wrbuf[0] = W1_MIKROBUS_ID_READ_EEPROM;
-+ wrbuf[1] = off & 0xFF;
-+ wrbuf[2] = off >> 8;
-+
-+ if (w1_reset_select_slave(sl))
-+ return -1;
-+ w1_write_block(sl->master, wrbuf, 3);
-+ w1_read_block(sl->master, buf, count);
-+
-+ if (w1_reset_select_slave(sl))
-+ return -1;
-+ cmp = kzalloc(count, GFP_KERNEL);
-+ if (!cmp)
-+ return -ENOMEM;
-+ w1_write_block(sl->master, wrbuf, 3);
-+ w1_read_block(sl->master, cmp, count);
-+ if (!memcmp(cmp, buf, count)){
-+ kfree(cmp);
-+ return 0;
-+ }
-+ } while (--tries);
-+
-+ dev_err(&sl->dev, "proof reading failed %d times\n",
-+ W1_MIKROBUS_ID_EEPROM_READ_RETRIES);
-+ kfree(cmp);
-+ return -EIO;
-+}
-+
-+static int w1_mikrobus_id_movescratch(struct w1_slave *sl, int addr, char *buf)
-+{
-+ u8 wrbuf[4];
-+ u8 scratchpad_verify[W1_MIKROBUS_ID_EEPROM_VERIFY_SCRATCH_SIZE];
-+ u8 TA1, TA2, ES;
-+ int verify_status;
-+ int tries;
-+
-+ wrbuf[0] = W1_MIKROBUS_ID_EEPROM_WRITE_SCRATCH;
-+ wrbuf[1] = addr & 0xFF;
-+ wrbuf[2] = addr >> 8;
-+
-+ tries = W1_MIKROBUS_ID_EEPROM_WRITE_RETRIES;
-+ do {
-+ if (w1_reset_select_slave(sl))
-+ return -1;
-+ w1_write_block(sl->master, wrbuf, 3);
-+ w1_write_block(sl->master, buf, W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-+ if (w1_reset_select_slave(sl))
-+ return -1;
-+ w1_write_8(sl->master, W1_MIKROBUS_ID_EEPROM_READ_SCRATCH);
-+ TA1 = w1_read_8(sl->master);
-+ TA2 = w1_read_8(sl->master);
-+ ES = w1_read_8(sl->master);
-+ w1_read_block(sl->master, scratchpad_verify, W1_MIKROBUS_ID_EEPROM_VERIFY_SCRATCH_SIZE);
-+ verify_status = memcmp(buf, scratchpad_verify, W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-+ } while(verify_status && --tries);
-+
-+ if(!tries && verify_status){
-+ dev_err(&sl->dev, "verify scratchpad failed %d times\n",
-+ W1_MIKROBUS_ID_EEPROM_WRITE_RETRIES);
-+ return -EIO;
-+ }
-+
-+ wrbuf[0] = W1_MIKROBUS_ID_EEPROM_COPY_SCRATCH;
-+ wrbuf[1] = addr & 0xFF;
-+ wrbuf[2] = addr >> 8;
-+ wrbuf[3] = ES;
-+ if (w1_reset_select_slave(sl))
-+ return -1;
-+ w1_write_block(sl->master, wrbuf, 4);
-+ msleep(W1_MIKROBUS_ID_EEPROM_TPROG_MS);
-+ return 0;
-+}
-+
-+static int w1_mikrobus_id_writeblock(struct w1_slave *sl, int off, int count, char *buf)
-+{
-+ u16 wraddr = 0;
-+ u16 len = count - (count % W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-+ u8 scratchpad_write[W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE] = {0};
-+
-+ while(len > 0) {
-+ w1_mikrobus_id_movescratch(sl, wraddr + off, buf + wraddr);
-+ wraddr += W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE;
-+ len -= W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE;
-+ }
-+
-+ if(count % W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE){
-+ memcpy(scratchpad_write, buf + wraddr, count % W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-+ w1_mikrobus_id_movescratch(sl, wraddr + off, scratchpad_write);
-+ }
-+
-+ return 0;
-+}
-+
-+static int w1_mikrobus_id_nvmem_read(void *priv, unsigned int off, void *buf, size_t count)
-+{
-+ struct w1_slave *sl = priv;
-+ int ret;
-+
-+ mutex_lock(&sl->master->bus_mutex);
-+ ret = w1_mikrobus_id_readblock(sl, off, count, buf);
-+ mutex_unlock(&sl->master->bus_mutex);
-+
-+ return ret;
-+}
-+
-+static int w1_mikrobus_id_nvmem_write(void *priv, unsigned int off, void *buf, size_t count)
-+{
-+ struct w1_slave *sl = priv;
-+ int ret;
-+
-+ mutex_lock(&sl->master->bus_mutex);
-+ ret = w1_mikrobus_id_writeblock(sl, off, count, buf);
-+ mutex_unlock(&sl->master->bus_mutex);
-+
-+ return ret;
-+}
-+
-+static int w1_mikrobus_id_add_slave(struct w1_slave *sl)
-+{
-+ struct nvmem_device *nvmem;
-+ struct mikrobus_port *port;
-+ struct nvmem_config nvmem_cfg = {
-+ .dev = &sl->dev,
-+ .reg_read = w1_mikrobus_id_nvmem_read,
-+ .reg_write = w1_mikrobus_id_nvmem_write,
-+ .type = NVMEM_TYPE_EEPROM,
-+ .read_only = false,
-+ .word_size = 1,
-+ .stride = 1,
-+ .size = W1_MIKROBUS_ID_EEPROM_SIZE,
-+ .priv = sl,
-+ };
-+
-+ port = mikrobus_find_port_by_w1_master(sl->master);
-+ if(!port)
-+ return -ENODEV;
-+
-+ nvmem_cfg.name = port->name;
-+ nvmem = devm_nvmem_register(&sl->dev, &nvmem_cfg);
-+ port->eeprom = nvmem;
-+ mikrobus_port_scan_eeprom(port);
-+
-+ return PTR_ERR_OR_ZERO(nvmem);
-+}
-+
-+static const struct w1_family_ops w1_family_mikrobus_id_fops = {
-+ .add_slave = w1_mikrobus_id_add_slave,
-+};
-+
-+static struct w1_family w1_family_mikrobus_id = {
-+ .fid = W1_EEPROM_MIKROBUS_ID,
-+ .fops = &w1_family_mikrobus_id_fops,
-+};
-+module_w1_family(w1_family_mikrobus_id);
-+
-+MODULE_AUTHOR("Vaishnav M A <vaishnav@beagleboard.org>");
-+MODULE_DESCRIPTION("w1 family ac driver for mikroBUS ID EEPROM");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("w1-family-" __stringify(W1_EEPROM_MIKROBUS_ID));
-diff --git a/drivers/misc/mikrobus/mikrobus_manifest.c b/drivers/misc/mikrobus/mikrobus_manifest.c
-new file mode 100644
-index 000000000000..bd945110ba8c
---- /dev/null
-+++ b/drivers/misc/mikrobus/mikrobus_manifest.c
-@@ -0,0 +1,477 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * mikroBUS manifest parsing, an
-+ * extension to Greybus Manifest Parsing
-+ * under drivers/greybus/manifest.c
-+ *
-+ * Copyright 2014-2015 Google Inc.
-+ * Copyright 2014-2015 Linaro Ltd.
-+ */
-+
-+#define pr_fmt(fmt) "mikrobus_manifest:%s: " fmt, __func__
-+
-+#include <linux/bits.h>
-+#include <linux/types.h>
-+#include <linux/property.h>
-+#include <linux/greybus/greybus_manifest.h>
-+
-+#include "mikrobus_manifest.h"
-+
-+struct manifest_desc {
-+ struct list_head links;
-+ size_t size;
-+ void *data;
-+ enum greybus_descriptor_type type;
-+};
-+
-+static void manifest_descriptor_release_all(struct addon_board_info *board)
-+{
-+ struct manifest_desc *descriptor;
-+ struct manifest_desc *next;
-+
-+ list_for_each_entry_safe(descriptor, next, &board->manifest_descs, links) {
-+ list_del(&descriptor->links);
-+ kfree(descriptor);
-+ }
-+}
-+
-+static int board_descriptor_add(struct addon_board_info *board, struct greybus_descriptor *desc,
-+ size_t size)
-+{
-+ struct greybus_descriptor_header *desc_header = &desc->header;
-+ struct manifest_desc *descriptor;
-+ size_t desc_size;
-+ size_t expected_size;
-+
-+ if (size < sizeof(*desc_header)) {
-+ pr_err("short descriptor (%zu < %zu)", size, sizeof(*desc_header));
-+ return -EINVAL;
-+ }
-+ desc_size = le16_to_cpu(desc_header->size);
-+ if (desc_size > size) {
-+ pr_err("incorrect descriptor size (%zu != %zu)", size, desc_size);
-+ return -EINVAL;
-+ }
-+ expected_size = sizeof(*desc_header);
-+ switch (desc_header->type) {
-+ case GREYBUS_TYPE_STRING:
-+ expected_size += sizeof(struct greybus_descriptor_string);
-+ expected_size += desc->string.length;
-+ expected_size = ALIGN(expected_size, 4);
-+ break;
-+ case GREYBUS_TYPE_PROPERTY:
-+ expected_size += sizeof(struct greybus_descriptor_property);
-+ expected_size += desc->property.length;
-+ expected_size = ALIGN(expected_size, 4);
-+ break;
-+ case GREYBUS_TYPE_DEVICE:
-+ expected_size += sizeof(struct greybus_descriptor_device);
-+ break;
-+ case GREYBUS_TYPE_MIKROBUS:
-+ expected_size += sizeof(struct greybus_descriptor_mikrobus);
-+ break;
-+ case GREYBUS_TYPE_INTERFACE:
-+ expected_size += sizeof(struct greybus_descriptor_interface);
-+ break;
-+ case GREYBUS_TYPE_CPORT:
-+ expected_size += sizeof(struct greybus_descriptor_cport);
-+ break;
-+ case GREYBUS_TYPE_BUNDLE:
-+ expected_size += sizeof(struct greybus_descriptor_bundle);
-+ break;
-+ case GREYBUS_TYPE_INVALID:
-+ default:
-+ pr_err("invalid descriptor type %d", desc_header->type);
-+ return -EINVAL;
-+ }
-+
-+ descriptor = kzalloc(sizeof(*descriptor), GFP_KERNEL);
-+ if (!descriptor)
-+ return -ENOMEM;
-+ descriptor->size = desc_size;
-+ descriptor->data = (char *)desc + sizeof(*desc_header);
-+ descriptor->type = desc_header->type;
-+ list_add_tail(&descriptor->links, &board->manifest_descs);
-+ return desc_size;
-+}
-+
-+static char *mikrobus_string_get(struct addon_board_info *board, u8 string_id)
-+{
-+ struct greybus_descriptor_string *desc_string;
-+ struct manifest_desc *descriptor;
-+ bool found = false;
-+ char *string;
-+
-+ if (!string_id)
-+ return NULL;
-+
-+ list_for_each_entry(descriptor, &board->manifest_descs, links) {
-+ if (descriptor->type != GREYBUS_TYPE_STRING)
-+ continue;
-+ desc_string = descriptor->data;
-+ if (desc_string->id == string_id) {
-+ found = true;
-+ break;
-+ }
-+ }
-+ if (!found)
-+ return ERR_PTR(-ENOENT);
-+ string = kmemdup(&desc_string->string, desc_string->length + 1, GFP_KERNEL);
-+ if (!string)
-+ return ERR_PTR(-ENOMEM);
-+ string[desc_string->length] = '\0';
-+ return string;
-+}
-+
-+static void mikrobus_state_get(struct addon_board_info *board)
-+{
-+ struct greybus_descriptor_mikrobus *mikrobus;
-+ struct greybus_descriptor_interface *interface;
-+ struct manifest_desc *descriptor;
-+ bool found = false;
-+ int i;
-+
-+ list_for_each_entry(descriptor, &board->manifest_descs, links) {
-+ if (descriptor->type == GREYBUS_TYPE_MIKROBUS) {
-+ mikrobus = descriptor->data;
-+ found = true;
-+ break;
-+ }
-+ }
-+ if (!found) {
-+ pr_err("mikrobus descriptor not found");
-+ return;
-+ }
-+ for (i = 0; i < MIKROBUS_PORT_PIN_COUNT; i++)
-+ board->pin_state[i] = mikrobus->pin_state[i];
-+
-+ found = false;
-+ list_for_each_entry(descriptor, &board->manifest_descs, links) {
-+ if (descriptor->type == GREYBUS_TYPE_INTERFACE) {
-+ interface = descriptor->data;
-+ found = true;
-+ break;
-+ }
-+ }
-+ if (!found) {
-+ pr_err("interface descriptor not found");
-+ return;
-+ }
-+ board->name = mikrobus_string_get(board, interface->product_stringid);
-+}
-+
-+static struct property_entry *
-+mikrobus_property_entry_get(struct addon_board_info *board, u8 *prop_link,
-+ int num_properties)
-+{
-+ struct greybus_descriptor_property *desc_property;
-+ struct manifest_desc *descriptor;
-+ struct property_entry *properties;
-+ bool found = false;
-+ char *prop_name;
-+ u64 *val_u64;
-+ u32 *val_u32;
-+ u16 *val_u16;
-+ u8 *val_u8;
-+ int i;
-+
-+ properties = kcalloc(num_properties, sizeof(*properties), GFP_KERNEL);
-+ if (!properties)
-+ return ERR_PTR(-ENOMEM);
-+ for (i = 0; i < num_properties; i++) {
-+ list_for_each_entry(descriptor, &board->manifest_descs, links) {
-+ if (descriptor->type != GREYBUS_TYPE_PROPERTY)
-+ continue;
-+ desc_property = descriptor->data;
-+ if (desc_property->id == prop_link[i]) {
-+ found = true;
-+ break;
-+ }
-+ }
-+ if (!found) {
-+ kfree(properties);
-+ return ERR_PTR(-ENOENT);
-+ }
-+ prop_name = mikrobus_string_get(board, desc_property->propname_stringid);
-+ if (!prop_name) {
-+ kfree(properties);
-+ return ERR_PTR(-ENOENT);
-+ }
-+ switch (desc_property->type) {
-+ case MIKROBUS_PROPERTY_TYPE_U8:
-+ val_u8 = kmemdup(&desc_property->value,
-+ (desc_property->length) * sizeof(u8),
-+ GFP_KERNEL);
-+ if (desc_property->length == 1)
-+ properties[i] = PROPERTY_ENTRY_U8(prop_name, *val_u8);
-+ else
-+ properties[i] = PROPERTY_ENTRY_U8_ARRAY_LEN(prop_name,
-+ (void *)desc_property->value, desc_property->length);
-+ break;
-+ case MIKROBUS_PROPERTY_TYPE_U16:
-+ val_u16 = kmemdup(&desc_property->value,
-+ (desc_property->length) * sizeof(u16), GFP_KERNEL);
-+ if (desc_property->length == 1)
-+ properties[i] = PROPERTY_ENTRY_U16(prop_name, *val_u16);
-+ else
-+ properties[i] = PROPERTY_ENTRY_U16_ARRAY_LEN(prop_name,
-+ (void *)desc_property->value, desc_property->length);
-+ break;
-+ case MIKROBUS_PROPERTY_TYPE_U32:
-+ val_u32 = kmemdup(&desc_property->value,
-+ (desc_property->length) * sizeof(u32), GFP_KERNEL);
-+ if (desc_property->length == 1)
-+ properties[i] = PROPERTY_ENTRY_U32(prop_name, *val_u32);
-+ else
-+ properties[i] = PROPERTY_ENTRY_U32_ARRAY_LEN(prop_name,
-+ (void *)desc_property->value, desc_property->length);
-+ break;
-+ case MIKROBUS_PROPERTY_TYPE_U64:
-+ val_u64 = kmemdup(&desc_property->value,
-+ (desc_property->length) * sizeof(u64), GFP_KERNEL);
-+ if (desc_property->length == 1)
-+ properties[i] = PROPERTY_ENTRY_U64(prop_name, *val_u64);
-+ else
-+ properties[i] = PROPERTY_ENTRY_U64_ARRAY_LEN(prop_name,
-+ (void *)desc_property->value, desc_property->length);
-+ break;
-+ default:
-+ kfree(properties);
-+ return ERR_PTR(-EINVAL);
-+ }
-+ }
-+ return properties;
-+}
-+
-+static u8 *mikrobus_property_link_get(struct addon_board_info *board, u8 prop_id,
-+ struct board_device_info *board_dev, u8 prop_type)
-+{
-+ struct greybus_descriptor_property *desc_property;
-+ struct manifest_desc *descriptor;
-+ bool found = false;
-+ u8 *val_u8;
-+
-+ if (!prop_id)
-+ return NULL;
-+ list_for_each_entry(descriptor, &board->manifest_descs, links) {
-+ if (descriptor->type != GREYBUS_TYPE_PROPERTY)
-+ continue;
-+ desc_property = descriptor->data;
-+ if (desc_property->id == prop_id && desc_property->type == prop_type) {
-+ found = true;
-+ break;
-+ }
-+ }
-+ if (!found)
-+ return ERR_PTR(-ENOENT);
-+ val_u8 = kmemdup(&desc_property->value, desc_property->length, GFP_KERNEL);
-+ if (prop_type == MIKROBUS_PROPERTY_TYPE_GPIO)
-+ board_dev->num_gpio_resources = desc_property->length;
-+ else if (prop_type == MIKROBUS_PROPERTY_TYPE_PROPERTY)
-+ board_dev->num_properties = desc_property->length;
-+ else if (prop_type == MIKROBUS_PROPERTY_TYPE_REGULATOR)
-+ board_dev->num_regulators = desc_property->length;
-+ else if (prop_type == MIKROBUS_PROPERTY_TYPE_CLOCK)
-+ board_dev->num_clocks = desc_property->length;
-+ return val_u8;
-+}
-+
-+static int mikrobus_manifest_attach_device(struct addon_board_info *board,
-+ struct greybus_descriptor_device *dev_desc)
-+{
-+ struct board_device_info *board_dev;
-+ struct gpiod_lookup_table *lookup;
-+ struct greybus_descriptor_property *desc_property;
-+ struct manifest_desc *descriptor;
-+ u8 *gpio_desc_link;
-+ u8 *prop_link;
-+ u8 *reg_link;
-+ u8 *clock_link;
-+ u8 *gpioval;
-+ int retval;
-+ int i;
-+
-+ board_dev = kzalloc(sizeof(*board_dev), GFP_KERNEL);
-+ if (!board_dev)
-+ return -ENOMEM;
-+ board_dev->id = dev_desc->id;
-+ board_dev->drv_name = mikrobus_string_get(board, dev_desc->driver_stringid);
-+ if (!board_dev->drv_name) {
-+ retval = -ENOENT;
-+ goto err_free_board_dev;
-+ }
-+ board_dev->protocol = dev_desc->protocol;
-+ board_dev->reg = dev_desc->reg;
-+ board_dev->irq = dev_desc->irq;
-+ board_dev->irq_type = dev_desc->irq_type;
-+ board_dev->max_speed_hz = le32_to_cpu(dev_desc->max_speed_hz);
-+ board_dev->mode = dev_desc->mode;
-+ pr_info("parsed device %d, driver=%s, protocol=%d, reg=%x", board_dev->id, board_dev->drv_name, board_dev->protocol, board_dev->reg);
-+
-+ if (dev_desc->prop_link > 0) {
-+ prop_link = mikrobus_property_link_get(board, dev_desc->prop_link,
-+ board_dev, MIKROBUS_PROPERTY_TYPE_PROPERTY);
-+ if (!prop_link) {
-+ retval = -ENOENT;
-+ goto err_free_board_dev;
-+ }
-+ pr_info("device %d, number of properties=%d", board_dev->id,
-+ board_dev->num_properties);
-+ board_dev->properties = mikrobus_property_entry_get(board, prop_link,
-+ board_dev->num_properties);
-+ }
-+
-+ if (dev_desc->gpio_link > 0) {
-+ gpio_desc_link = mikrobus_property_link_get(board, dev_desc->gpio_link, board_dev,
-+ MIKROBUS_PROPERTY_TYPE_GPIO);
-+ if (!gpio_desc_link) {
-+ retval = -ENOENT;
-+ goto err_free_board_dev;
-+ }
-+ pr_info("device %d, number of gpio resource=%d", board_dev->id,
-+ board_dev->num_gpio_resources);
-+ lookup = kzalloc(struct_size(lookup, table, board_dev->num_gpio_resources),
-+ GFP_KERNEL);
-+ if (!lookup) {
-+ retval = -ENOMEM;
-+ goto err_free_board_dev;
-+ }
-+ for (i = 0; i < board_dev->num_gpio_resources; i++) {
-+ list_for_each_entry(descriptor, &board->manifest_descs, links) {
-+ if (descriptor->type != GREYBUS_TYPE_PROPERTY)
-+ continue;
-+ desc_property = descriptor->data;
-+ if (desc_property->id == gpio_desc_link[i]) {
-+ gpioval = desc_property->value;
-+ lookup->table[i].chip_hwnum = gpioval[0];
-+ lookup->table[i].flags = gpioval[1];
-+ lookup->table[i].con_id =
-+ mikrobus_string_get(board,
-+ desc_property->propname_stringid);
-+ break;
-+ }
-+ }
-+ }
-+ board_dev->gpio_lookup = lookup;
-+ }
-+
-+ if (dev_desc->reg_link > 0) {
-+ reg_link = mikrobus_property_link_get(board, dev_desc->reg_link,
-+ board_dev, MIKROBUS_PROPERTY_TYPE_REGULATOR);
-+ if (!reg_link) {
-+ retval = -ENOENT;
-+ goto err_free_board_dev;
-+ }
-+ pr_info("device %d, number of regulators=%d", board_dev->id,
-+ board_dev->num_regulators);
-+ board_dev->regulators = mikrobus_property_entry_get(board, reg_link,
-+ board_dev->num_regulators);
-+ }
-+
-+ if (dev_desc->clock_link > 0) {
-+ clock_link = mikrobus_property_link_get(board, dev_desc->clock_link,
-+ board_dev, MIKROBUS_PROPERTY_TYPE_CLOCK);
-+ if (!clock_link) {
-+ retval = -ENOENT;
-+ goto err_free_board_dev;
-+ }
-+ pr_info("device %d, number of clocks=%d", board_dev->id,
-+ board_dev->num_clocks);
-+ board_dev->clocks = mikrobus_property_entry_get(board, clock_link,
-+ board_dev->num_clocks);
-+ }
-+ list_add_tail(&board_dev->links, &board->devices);
-+ return 0;
-+err_free_board_dev:
-+ kfree(board_dev);
-+ return retval;
-+}
-+
-+static int mikrobus_manifest_parse_devices(struct addon_board_info *board)
-+{
-+ struct greybus_descriptor_device *desc_device;
-+ struct manifest_desc *desc, *next;
-+ int retval;
-+ int devcount = 0;
-+
-+ list_for_each_entry_safe(desc, next, &board->manifest_descs, links) {
-+ if (desc->type != GREYBUS_TYPE_DEVICE)
-+ continue;
-+ desc_device = desc->data;
-+ retval = mikrobus_manifest_attach_device(board, desc_device);
-+ devcount++;
-+ }
-+ return devcount;
-+}
-+
-+int mikrobus_manifest_parse(struct addon_board_info *board, void *data,
-+ size_t size)
-+{
-+ struct greybus_manifest_header *header;
-+ struct greybus_manifest *manifest;
-+ struct greybus_descriptor *desc;
-+ u16 manifest_size;
-+ int dev_count;
-+ int desc_size;
-+
-+ if (size < sizeof(*header)) {
-+ pr_err("short manifest (%zu < %zu)", size, sizeof(*header));
-+ return -EINVAL;
-+ }
-+
-+ manifest = data;
-+ header = &manifest->header;
-+ manifest_size = le16_to_cpu(header->size);
-+
-+ if (manifest_size != size) {
-+ pr_err("invalid manifest size(%zu < %u)", size, manifest_size);
-+ return -EINVAL;
-+ }
-+
-+ if (header->version_major > MIKROBUS_VERSION_MAJOR) {
-+ pr_err("manifest version too new (%u.%u > %u.%u)",
-+ header->version_major, header->version_minor,
-+ MIKROBUS_VERSION_MAJOR, MIKROBUS_VERSION_MINOR);
-+ return -EINVAL;
-+ }
-+
-+ desc = manifest->descriptors;
-+ size -= sizeof(*header);
-+ while (size) {
-+ desc_size = board_descriptor_add(board, desc, size);
-+ if (desc_size < 0) {
-+ pr_err("invalid manifest descriptor, size: %u", desc_size);
-+ return -EINVAL;
-+ }
-+ desc = (void *)desc + desc_size;
-+ size -= desc_size;
-+ }
-+ mikrobus_state_get(board);
-+ dev_count = mikrobus_manifest_parse_devices(board);
-+ pr_info(" %s manifest parsed with %d devices", board->name, dev_count);
-+ manifest_descriptor_release_all(board);
-+ return true;
-+}
-+
-+size_t mikrobus_manifest_header_validate(void *data, size_t size)
-+{
-+ struct greybus_manifest_header *header;
-+ u16 manifest_size;
-+
-+ header = data;
-+ manifest_size = le16_to_cpu(header->size);
-+
-+ if (manifest_size < sizeof(*header)) {
-+ pr_err("short manifest (%zu < %zu)", size, sizeof(*header));
-+ return -EINVAL;
-+ }
-+
-+ if (header->version_major > MIKROBUS_VERSION_MAJOR) {
-+ pr_err("manifest version too new (%u.%u > %u.%u)",
-+ header->version_major, header->version_minor,
-+ MIKROBUS_VERSION_MAJOR, MIKROBUS_VERSION_MINOR);
-+ return -EINVAL;
-+ }
-+ return manifest_size;
-+}
-+
-diff --git a/drivers/misc/mikrobus/mikrobus_manifest.h b/drivers/misc/mikrobus/mikrobus_manifest.h
-new file mode 100644
-index 000000000000..4c8b4346575e
---- /dev/null
-+++ b/drivers/misc/mikrobus/mikrobus_manifest.h
-@@ -0,0 +1,20 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mikroBUS manifest definition
-+ * extension to Greybus Manifest Definition
-+ *
-+ * Copyright 2014-2015 Google Inc.
-+ * Copyright 2014-2015 Linaro Ltd.
-+ *
-+ * Released under the GPLv2 and BSD licenses.
-+ */
-+
-+#ifndef __MIKROBUS_MANIFEST_H
-+#define __MIKROBUS_MANIFEST_H
-+
-+#include <linux/mikrobus.h>
-+
-+int mikrobus_manifest_parse(struct addon_board_info *info, void *data, size_t size);
-+size_t mikrobus_manifest_header_validate(void *data, size_t size);
-+
-+#endif /* __MIKROBUS_MANIFEST_H */
-diff --git a/drivers/staging/greybus/gbphy.c b/drivers/staging/greybus/gbphy.c
-index 13d319860da5..738421ccf4b2 100644
---- a/drivers/staging/greybus/gbphy.c
-+++ b/drivers/staging/greybus/gbphy.c
-@@ -14,16 +14,12 @@
- #include <linux/slab.h>
- #include <linux/device.h>
- #include <linux/greybus.h>
-+#include <linux/mikrobus.h>
-
--#include "gbphy.h"
-+#include <linux/greybus/gbphy.h>
-
- #define GB_GBPHY_AUTOSUSPEND_MS 3000
-
--struct gbphy_host {
-- struct gb_bundle *bundle;
-- struct list_head devices;
--};
--
- static DEFINE_IDA(gbphy_id);
-
- static ssize_t protocol_id_show(struct device *dev,
-@@ -305,6 +301,8 @@ static int gb_gbphy_probe(struct gb_bundle *bundle,
- list_add(&gbphy_dev->list, &gbphy_host->devices);
- }
-
-+ mikrobus_port_gb_register(gbphy_host, bundle->manifest_blob, bundle->manifest_size);
-+
- gb_pm_runtime_put_autosuspend(bundle);
-
- return 0;
-diff --git a/drivers/staging/greybus/gpio.c b/drivers/staging/greybus/gpio.c
-index 7e6347fe93f9..218f4ae1c562 100644
---- a/drivers/staging/greybus/gpio.c
-+++ b/drivers/staging/greybus/gpio.c
-@@ -15,32 +15,8 @@
- #include <linux/mutex.h>
- #include <linux/greybus.h>
-
--#include "gbphy.h"
--
--struct gb_gpio_line {
-- /* The following has to be an array of line_max entries */
-- /* --> make them just a flags field */
-- u8 active: 1,
-- direction: 1, /* 0 = output, 1 = input */
-- value: 1; /* 0 = low, 1 = high */
-- u16 debounce_usec;
--
-- u8 irq_type;
-- bool irq_type_pending;
-- bool masked;
-- bool masked_pending;
--};
--
--struct gb_gpio_controller {
-- struct gbphy_device *gbphy_dev;
-- struct gb_connection *connection;
-- u8 line_max; /* max line number */
-- struct gb_gpio_line *lines;
-+#include <linux/greybus/gbphy.h>
-
-- struct gpio_chip chip;
-- struct irq_chip irqc;
-- struct mutex irq_lock;
--};
- #define gpio_chip_to_gb_gpio_controller(chip) \
- container_of(chip, struct gb_gpio_controller, chip)
- #define irq_data_to_gpio_chip(d) (d->domain->host_data)
-diff --git a/drivers/staging/greybus/i2c.c b/drivers/staging/greybus/i2c.c
-index de2f6516da09..4fff1c6d88b7 100644
---- a/drivers/staging/greybus/i2c.c
-+++ b/drivers/staging/greybus/i2c.c
-@@ -12,16 +12,7 @@
- #include <linux/i2c.h>
- #include <linux/greybus.h>
-
--#include "gbphy.h"
--
--struct gb_i2c_device {
-- struct gb_connection *connection;
-- struct gbphy_device *gbphy_dev;
--
-- u32 functionality;
--
-- struct i2c_adapter adapter;
--};
-+#include <linux/greybus/gbphy.h>
-
- /*
- * Map Greybus i2c functionality bits into Linux ones
-diff --git a/drivers/staging/greybus/pwm.c b/drivers/staging/greybus/pwm.c
-index 891a6a672378..2808882e2ad3 100644
---- a/drivers/staging/greybus/pwm.c
-+++ b/drivers/staging/greybus/pwm.c
-@@ -12,7 +12,7 @@
- #include <linux/pwm.h>
- #include <linux/greybus.h>
-
--#include "gbphy.h"
-+#include <linux/greybus/gbphy.h>
-
- struct gb_pwm_chip {
- struct gb_connection *connection;
-diff --git a/drivers/staging/greybus/sdio.c b/drivers/staging/greybus/sdio.c
-index 37bf04c22dbc..29f82d95e8b2 100644
---- a/drivers/staging/greybus/sdio.c
-+++ b/drivers/staging/greybus/sdio.c
-@@ -14,7 +14,7 @@
- #include <linux/workqueue.h>
- #include <linux/greybus.h>
-
--#include "gbphy.h"
-+#include <linux/greybus/gbphy.h>
-
- struct gb_sdio_host {
- struct gb_connection *connection;
-diff --git a/drivers/staging/greybus/spi.c b/drivers/staging/greybus/spi.c
-index 68e8d272db6d..2ab5fa2e6cfa 100644
---- a/drivers/staging/greybus/spi.c
-+++ b/drivers/staging/greybus/spi.c
-@@ -9,7 +9,7 @@
- #include <linux/module.h>
- #include <linux/greybus.h>
-
--#include "gbphy.h"
-+#include <linux/greybus/gbphy.h>
- #include "spilib.h"
-
- static struct spilib_ops *spilib_ops;
-diff --git a/drivers/staging/greybus/spilib.c b/drivers/staging/greybus/spilib.c
-index ad0700a0bb81..5c94b7639969 100644
---- a/drivers/staging/greybus/spilib.c
-+++ b/drivers/staging/greybus/spilib.c
-@@ -14,24 +14,7 @@
- #include <linux/spi/spi.h>
-
- #include "spilib.h"
--
--struct gb_spilib {
-- struct gb_connection *connection;
-- struct device *parent;
-- struct spi_transfer *first_xfer;
-- struct spi_transfer *last_xfer;
-- struct spilib_ops *ops;
-- u32 rx_xfer_offset;
-- u32 tx_xfer_offset;
-- u32 last_xfer_size;
-- unsigned int op_timeout;
-- u16 mode;
-- u16 flags;
-- u32 bits_per_word_mask;
-- u8 num_chipselect;
-- u32 min_speed_hz;
-- u32 max_speed_hz;
--};
-+#include <linux/greybus/gbphy.h>
-
- #define GB_SPI_STATE_MSG_DONE ((void *)0)
- #define GB_SPI_STATE_MSG_IDLE ((void *)1)
-diff --git a/drivers/staging/greybus/uart.c b/drivers/staging/greybus/uart.c
-index 73f01ed1e5b7..6722565b1fd7 100644
---- a/drivers/staging/greybus/uart.c
-+++ b/drivers/staging/greybus/uart.c
-@@ -30,7 +30,7 @@
- #include <linux/completion.h>
- #include <linux/greybus.h>
-
--#include "gbphy.h"
-+#include <linux/greybus/gbphy.h>
-
- #define GB_NUM_MINORS 16 /* 16 is more than enough */
- #define GB_NAME "ttyGB"
-diff --git a/drivers/staging/greybus/usb.c b/drivers/staging/greybus/usb.c
-index 8e9d9d59a357..df4b84f022a5 100644
---- a/drivers/staging/greybus/usb.c
-+++ b/drivers/staging/greybus/usb.c
-@@ -12,7 +12,7 @@
- #include <linux/usb/hcd.h>
- #include <linux/greybus.h>
-
--#include "gbphy.h"
-+#include <linux/greybus/gbphy.h>
-
- /* Greybus USB request types */
- #define GB_USB_TYPE_HCD_START 0x02
-diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c
-index f2ae2e563dc5..c59ecb60f358 100644
---- a/drivers/w1/w1.c
-+++ b/drivers/w1/w1.c
-@@ -683,7 +683,8 @@ static int __w1_attach_slave_device(struct w1_slave *sl)
- sl->dev.of_node = of_find_matching_node(sl->master->dev.of_node,
- sl->family->of_match_table);
-
-- dev_set_name(&sl->dev, "%02x-%012llx",
-+ dev_set_name(&sl->dev, "%s-%02x-%012llx",
-+ sl->master->name,
- (unsigned int) sl->reg_num.family,
- (unsigned long long) sl->reg_num.id);
- snprintf(&sl->name[0], sizeof(sl->name),
-diff --git a/drivers/w1/w1_int.c b/drivers/w1/w1_int.c
-index b3e1792d9c49..5b16717c8415 100644
---- a/drivers/w1/w1_int.c
-+++ b/drivers/w1/w1_int.c
-@@ -243,3 +243,31 @@ void w1_remove_master_device(struct w1_bus_master *bm)
- __w1_remove_master_device(found);
- }
- EXPORT_SYMBOL(w1_remove_master_device);
-+
-+/**
-+ * w1_find_master_device() - find a master device
-+ * @bm: master bus device to search
-+ */
-+struct w1_master *w1_find_master_device(struct w1_bus_master *bm)
-+{
-+ struct w1_master *dev, *found = NULL;
-+
-+ list_for_each_entry(dev, &w1_masters, w1_master_entry) {
-+ if (!dev->initialized)
-+ continue;
-+
-+ if (dev->bus_master->data == bm->data) {
-+ found = dev;
-+ break;
-+ }
-+ }
-+
-+ if (!found) {
-+ pr_err("device doesn't exist.\n");
-+ return ERR_PTR(-ENODEV);
-+ }
-+
-+ return found;
-+}
-+EXPORT_SYMBOL(w1_find_master_device);
-+
-diff --git a/include/linux/greybus/bundle.h b/include/linux/greybus/bundle.h
-index df8d88424cb7..f54ceecf2be8 100644
---- a/include/linux/greybus/bundle.h
-+++ b/include/linux/greybus/bundle.h
-@@ -33,6 +33,8 @@ struct gb_bundle {
- u8 *state;
-
- struct list_head links; /* interface->bundles */
-+ void *manifest_blob;
-+ size_t manifest_size;
- };
- #define to_gb_bundle(d) container_of(d, struct gb_bundle, dev)
-
-diff --git a/drivers/staging/greybus/gbphy.h b/include/linux/greybus/gbphy.h
-similarity index 68%
-rename from drivers/staging/greybus/gbphy.h
-rename to include/linux/greybus/gbphy.h
-index d4a225b76338..cfc23589b2e2 100644
---- a/drivers/staging/greybus/gbphy.h
-+++ b/include/linux/greybus/gbphy.h
-@@ -8,6 +8,63 @@
- #ifndef __GBPHY_H
- #define __GBPHY_H
-
-+#include <linux/i2c.h>
-+#include <linux/gpio/driver.h>
-+
-+struct gbphy_host {
-+ struct gb_bundle *bundle;
-+ struct list_head devices;
-+};
-+
-+
-+struct gb_i2c_device {
-+ struct gb_connection *connection;
-+ struct gbphy_device *gbphy_dev;
-+ u32 functionality;
-+ struct i2c_adapter adapter;
-+};
-+
-+struct gb_spilib {
-+ struct gb_connection *connection;
-+ struct device *parent;
-+ struct spi_transfer *first_xfer;
-+ struct spi_transfer *last_xfer;
-+ struct spilib_ops *ops;
-+ u32 rx_xfer_offset;
-+ u32 tx_xfer_offset;
-+ u32 last_xfer_size;
-+ unsigned int op_timeout;
-+ u16 mode;
-+ u16 flags;
-+ u32 bits_per_word_mask;
-+ u8 num_chipselect;
-+ u32 min_speed_hz;
-+ u32 max_speed_hz;
-+};
-+struct gb_gpio_line {
-+ /* The following has to be an array of line_max entries */
-+ /* --> make them just a flags field */
-+ u8 active: 1,
-+ direction: 1, /* 0 = output, 1 = input */
-+ value: 1; /* 0 = low, 1 = high */
-+ u16 debounce_usec;
-+
-+ u8 irq_type;
-+ bool irq_type_pending;
-+ bool masked;
-+ bool masked_pending;
-+};
-+
-+struct gb_gpio_controller {
-+ struct gbphy_device *gbphy_dev;
-+ struct gb_connection *connection;
-+ u8 line_max; /* max line number */
-+ struct gb_gpio_line *lines;
-+ struct gpio_chip chip;
-+ struct irq_chip irqc;
-+ struct mutex irq_lock;
-+};
-+
- struct gbphy_device {
- u32 id;
- struct greybus_descriptor_cport *cport_desc;
-@@ -36,9 +93,9 @@ struct gbphy_device_id {
-
- struct gbphy_driver {
- const char *name;
-- int (*probe)(struct gbphy_device *device,
-+ int (*probe)(struct gbphy_device *,
- const struct gbphy_device_id *id);
-- void (*remove)(struct gbphy_device *device);
-+ void (*remove)(struct gbphy_device *);
- const struct gbphy_device_id *id_table;
-
- struct device_driver driver;
-diff --git a/include/linux/greybus/greybus_manifest.h b/include/linux/greybus/greybus_manifest.h
-index 6e62fe478712..50d5a5fd3d51 100644
---- a/include/linux/greybus/greybus_manifest.h
-+++ b/include/linux/greybus/greybus_manifest.h
-@@ -23,6 +23,9 @@ enum greybus_descriptor_type {
- GREYBUS_TYPE_STRING = 0x02,
- GREYBUS_TYPE_BUNDLE = 0x03,
- GREYBUS_TYPE_CPORT = 0x04,
-+ GREYBUS_TYPE_MIKROBUS = 0x05,
-+ GREYBUS_TYPE_PROPERTY = 0x06,
-+ GREYBUS_TYPE_DEVICE = 0x07,
- };
-
- enum greybus_protocol {
-@@ -151,6 +154,49 @@ struct greybus_descriptor_cport {
- __u8 protocol_id; /* enum greybus_protocol */
- } __packed;
-
-+/*
-+ * A mikrobus descriptor is used to describe the details
-+ * about the bus ocnfiguration for the add-on board
-+ * connected to the mikrobus port.
-+ */
-+struct greybus_descriptor_mikrobus {
-+ __u8 pin_state[12];
-+} __packed;
-+
-+/*
-+ * A property descriptor is used to pass named properties
-+ * to device drivers through the unified device properties
-+ * interface under linux/property.h
-+ */
-+struct greybus_descriptor_property {
-+ __u8 length;
-+ __u8 id;
-+ __u8 propname_stringid;
-+ __u8 type;
-+ __u8 value[0];
-+} __packed;
-+
-+/*
-+ * A device descriptor is used to describe the
-+ * details required by a add-on board device
-+ * driver.
-+ */
-+struct greybus_descriptor_device {
-+ __u8 id;
-+ __u8 driver_stringid;
-+ __u8 protocol;
-+ __u8 reg;
-+ __le32 max_speed_hz;
-+ __u8 irq;
-+ __u8 irq_type;
-+ __u8 mode;
-+ __u8 prop_link;
-+ __u8 gpio_link;
-+ __u8 reg_link;
-+ __u8 clock_link;
-+ __u8 pad[1];
-+} __packed;
-+
- struct greybus_descriptor_header {
- __le16 size;
- __u8 type; /* enum greybus_descriptor_type */
-@@ -164,6 +210,9 @@ struct greybus_descriptor {
- struct greybus_descriptor_interface interface;
- struct greybus_descriptor_bundle bundle;
- struct greybus_descriptor_cport cport;
-+ struct greybus_descriptor_mikrobus mikrobus;
-+ struct greybus_descriptor_property property;
-+ struct greybus_descriptor_device device;
- };
- } __packed;
-
-diff --git a/include/linux/greybus/interface.h b/include/linux/greybus/interface.h
-index ce4def881e6f..a7d8d40fa300 100644
---- a/include/linux/greybus/interface.h
-+++ b/include/linux/greybus/interface.h
-@@ -65,6 +65,8 @@ struct gb_interface {
-
- struct work_struct mode_switch_work;
- struct completion mode_switch_completion;
-+ void *manifest_blob;
-+ size_t manifest_size;
- };
- #define to_gb_interface(d) container_of(d, struct gb_interface, dev)
-
-diff --git a/include/linux/mikrobus.h b/include/linux/mikrobus.h
-new file mode 100644
-index 000000000000..4999ac70e566
---- /dev/null
-+++ b/include/linux/mikrobus.h
-@@ -0,0 +1,207 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mikroBUS Driver for instantiating add-on
-+ * board devices with an identifier EEPROM
-+ *
-+ * Copyright 2020 Vaishnav M A, BeagleBoard.org Foundation.
-+ */
-+
-+#ifndef __MIKROBUS_H
-+#define __MIKROBUS_H
-+
-+#include <linux/kernel.h>
-+#include <linux/device.h>
-+#include <linux/i2c.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/gpio/machine.h>
-+#include <linux/spi/spi.h>
-+#include <linux/serdev.h>
-+#include <linux/property.h>
-+#include <linux/greybus.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/nvmem-provider.h>
-+#include <linux/greybus/gbphy.h>
-+
-+#define MIKROBUS_VERSION_MAJOR 0x00
-+#define MIKROBUS_VERSION_MINOR 0x03
-+
-+#define MIKROBUS_NAME_SIZE 40
-+#define MIKROBUS_PINCTRL_NAME_SIZE 20
-+
-+#define MIKROBUS_NUM_PINCTRL_STATE 4
-+#define MIKROBUS_NUM_CS 2
-+
-+#define MIKROBUS_PINCTRL_PWM 0
-+#define MIKROBUS_PINCTRL_UART 1
-+#define MIKROBUS_PINCTRL_I2C 2
-+#define MIKROBUS_PINCTRL_SPI 3
-+
-+#define MIKROBUS_PINCTRL_STATE_GPIO "gpio"
-+
-+#define MIKROBUS_EEPROM_EXIT_ID_CMD 0xD2
-+
-+extern struct bus_type mikrobus_bus_type;
-+extern struct device_type mikrobus_port_type;
-+extern const char *MIKROBUS_PINCTRL_STR[];
-+
-+enum mikrobus_property_type {
-+ MIKROBUS_PROPERTY_TYPE_MIKROBUS = 0x00,
-+ MIKROBUS_PROPERTY_TYPE_PROPERTY = 0x01,
-+ MIKROBUS_PROPERTY_TYPE_GPIO = 0x02,
-+ MIKROBUS_PROPERTY_TYPE_U8 = 0x03,
-+ MIKROBUS_PROPERTY_TYPE_U16 = 0x04,
-+ MIKROBUS_PROPERTY_TYPE_U32 = 0x05,
-+ MIKROBUS_PROPERTY_TYPE_U64 = 0x06,
-+ MIKROBUS_PROPERTY_TYPE_REGULATOR = 0x07,
-+ MIKROBUS_PROPERTY_TYPE_CLOCK = 0x08,
-+};
-+
-+enum mikrobus_pin {
-+ MIKROBUS_PIN_PWM = 0x00,
-+ MIKROBUS_PIN_INT = 0x01,
-+ MIKROBUS_PIN_RX = 0x02,
-+ MIKROBUS_PIN_TX = 0x03,
-+ MIKROBUS_PIN_SCL = 0x04,
-+ MIKROBUS_PIN_SDA = 0x05,
-+ MIKROBUS_PIN_MOSI = 0x06,
-+ MIKROBUS_PIN_MISO = 0x07,
-+ MIKROBUS_PIN_SCK = 0x08,
-+ MIKROBUS_PIN_CS = 0x09,
-+ MIKROBUS_PIN_RST = 0x0A,
-+ MIKROBUS_PIN_AN = 0x0B,
-+ MIKROBUS_PORT_PIN_COUNT = 0x0C,
-+};
-+
-+enum mikrobus_pin_state {
-+ MIKROBUS_STATE_INPUT = 0x01,
-+ MIKROBUS_STATE_OUTPUT_HIGH = 0x02,
-+ MIKROBUS_STATE_OUTPUT_LOW = 0x03,
-+ MIKROBUS_STATE_PWM = 0x04,
-+ MIKROBUS_STATE_SPI = 0x05,
-+ MIKROBUS_STATE_I2C = 0x06,
-+ MIKROBUS_STATE_UART = 0x07,
-+};
-+
-+/*
-+ * board_device_info describes a single device on a mikrobus add-on
-+ * board, an add-on board can present one or more device to the host
-+ *
-+ * @gpio_lookup: used to provide the GPIO lookup table for
-+ * passing the named GPIOs to device drivers.
-+ * @properties: used to provide the property_entry to pass named
-+ * properties to device drivers, applicable only when driver uses
-+ * device_property_read_* calls to fetch the properties.
-+ * @num_gpio_resources: number of named gpio resources for the device,
-+ * used mainly for gpiod_lookup_table memory allocation.
-+ * @num_properties: number of custom properties for the device,
-+ * used mainly for property_entry memory allocation.
-+ * @protocol: used to know the type of the device and it should
-+ * contain one of the values defined under 'enum greybus_class_type'
-+ * under linux/greybus/greybus_manifest.h
-+ * @reg: I2C address for the device, for devices on the SPI bus
-+ * this field is the chip select address relative to the mikrobus
-+ * port:0->device chip select connected to CS pin on mikroBUS port
-+ * 1->device chip select connected to RST Pin on mikroBUS port
-+ * @mode: SPI mode
-+ * @max_speed_hz: SPI max speed(Hz)
-+ * @drv_name: device_id to match with the driver
-+ * @irq_type: type of IRQ trigger , match with defines in linux/interrupt.h
-+ * @irq: irq number relative to the mikrobus port should contain one of the
-+ * values defined under 'enum mikrobus_pin'
-+ * @id: device id starting from 1
-+ */
-+struct board_device_info {
-+ struct gpiod_lookup_table *gpio_lookup;
-+ struct property_entry *properties;
-+ struct property_entry *regulators;
-+ struct property_entry *clocks;
-+ struct list_head links;
-+ unsigned short num_gpio_resources;
-+ unsigned short num_properties;
-+ unsigned short num_regulators;
-+ unsigned short num_clocks;
-+ unsigned short protocol;
-+ unsigned short reg;
-+ unsigned int mode;
-+ void *dev_client;
-+ u32 max_speed_hz;
-+ char *drv_name;
-+ int irq_type;
-+ int irq;
-+ int id;
-+};
-+
-+/*
-+ * addon_board_info describes a mikrobus add-on device the add-on
-+ * board, an add-on board can present one or more device to the host
-+ *
-+ * @manifest_descs: list of manifest descriptors
-+ * @devices: list of devices on the board
-+ * @pin_state: the state of each pin on the mikrobus port required
-+ * for the add-on board should contain one of the values defined under
-+ * 'enum mikrobus_pin_state' restrictions are as per mikrobus standard
-+ * specifications.
-+ * @name: add-on board name
-+ */
-+struct addon_board_info {
-+ struct list_head manifest_descs;
-+ struct list_head devices;
-+ u8 pin_state[MIKROBUS_PORT_PIN_COUNT];
-+ char *name;
-+};
-+
-+/*
-+ * mikrobus_port describes the peripherals mapped to a
-+ * mikrobus port.
-+ *
-+ * @eeprom_client: i2c_client corresponding to the eeprom
-+ * on the add-on board.
-+ * @board: pointer to the attached add-on board.
-+ * @i2c_adap: I2C adapter attached to the mikrobus port.
-+ * @spi_mstr: SPI master attached to the mikrobus port.
-+ * @eeprom: nvmem_device for the eeprom on the add-on board.
-+ * @pwm: pwm_device attached to the mikrobus port PWM pin.
-+ * @pinctrl_selected: current pinctrl_selected state.
-+ * @chip_select: chip select number mapped to the SPI
-+ * CS pin on the mikrobus port and the RST pin on the mikrobus
-+ * port
-+ * @id: port id starting from 1
-+ */
-+struct mikrobus_port {
-+ struct addon_board_info *board;
-+ struct nvmem_device *eeprom;
-+ struct i2c_adapter *i2c_adap;
-+ struct spi_master *spi_mstr;
-+ struct w1_master *w1_master;
-+ struct platform_device *w1_gpio;
-+ struct serdev_controller *ser_ctrl;
-+ struct gpio_descs *gpios;
-+ struct pwm_device *pwm;
-+ struct pinctrl *pinctrl;
-+ struct module *owner;
-+ struct device dev;
-+ char name[MIKROBUS_NAME_SIZE];
-+ char *pinctrl_selected[MIKROBUS_NUM_PINCTRL_STATE];
-+ unsigned int chip_select[MIKROBUS_NUM_CS];
-+ int skip_scan;
-+ int disable_eeprom;
-+ int id;
-+};
-+#define to_mikrobus_port(d) container_of(d, struct mikrobus_port, dev)
-+
-+void mikrobus_board_unregister(struct mikrobus_port *port,
-+ struct addon_board_info *board);
-+int mikrobus_board_register(struct mikrobus_port *port,
-+ struct addon_board_info *board);
-+
-+int mikrobus_port_gb_register(struct gbphy_host *host, void *manifest_blob, size_t manifest_size);
-+int mikrobus_port_register(struct mikrobus_port *port);
-+int mikrobus_port_pinctrl_select(struct mikrobus_port *port);
-+void mikrobus_port_delete(struct mikrobus_port *port);
-+int mikrobus_port_scan_eeprom(struct mikrobus_port *port);
-+struct mikrobus_port *mikrobus_find_port_by_w1_master(struct w1_master *master);
-+#endif /* __MIKROBUS_H */
-diff --git a/include/linux/w1.h b/include/linux/w1.h
-index 9a2a0ef39018..24269d0dd5d1 100644
---- a/include/linux/w1.h
-+++ b/include/linux/w1.h
-@@ -242,6 +242,7 @@ struct w1_master {
-
- int w1_add_master_device(struct w1_bus_master *master);
- void w1_remove_master_device(struct w1_bus_master *master);
-+struct w1_master *w1_find_master_device(struct w1_bus_master *master);
-
- /**
- * struct w1_family_ops - operations for a family type
---
-2.25.1
-
diff --git a/patches/drivers/mikrobus/0002-v5.15.x-mikrobus-Use-software-node-API-with-the-prop.patch b/patches/drivers/mikrobus/0002-v5.15.x-mikrobus-Use-software-node-API-with-the-prop.patch
deleted file mode 100644
index 5d2cbb63e0a333287bba07c58a37c5b7e92284f4..0000000000000000000000000000000000000000
--- a/patches/drivers/mikrobus/0002-v5.15.x-mikrobus-Use-software-node-API-with-the-prop.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From a05f98ae5794c56d341d612c794e949f8ecc6a86 Mon Sep 17 00:00:00 2001
-From: Robert Nelson <robertcnelson@gmail.com>
-Date: Mon, 1 Nov 2021 11:39:04 -0500
-Subject: [PATCH 2/2] v5.15.x: mikrobus: Use software node API with the
- properties
-
-Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
----
- drivers/misc/mikrobus/mikrobus_core.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/misc/mikrobus/mikrobus_core.c b/drivers/misc/mikrobus/mikrobus_core.c
-index 4e24f980f18a..5700396b83e4 100644
---- a/drivers/misc/mikrobus/mikrobus_core.c
-+++ b/drivers/misc/mikrobus/mikrobus_core.c
-@@ -524,7 +524,7 @@ static int mikrobus_device_register(struct mikrobus_port *port,
- if (!pdev)
- return -ENOMEM;
- if (dev->properties)
-- platform_device_add_properties(pdev, dev->properties);
-+ device_create_managed_software_node(&pdev->dev, dev->properties, NULL);
- dev->dev_client = pdev;
- platform_device_add(dev->dev_client);
- break;
---
-2.30.2
-
diff --git a/patches/drivers/mikrobus/0003-drivers-misc-mikrobus-add-support-alternate-Click-ID.patch b/patches/drivers/mikrobus/0003-drivers-misc-mikrobus-add-support-alternate-Click-ID.patch
deleted file mode 100644
index 2df996702d4869162fec14cabcb54a0212f41bd5..0000000000000000000000000000000000000000
--- a/patches/drivers/mikrobus/0003-drivers-misc-mikrobus-add-support-alternate-Click-ID.patch
+++ /dev/null
@@ -1,343 +0,0 @@
-From 3363f1da1dc7fb5c3926051ab9dc6d05d7c83334 Mon Sep 17 00:00:00 2001
-From: vaishnav98 <vaishnav@beagleboard.org>
-Date: Tue, 23 Nov 2021 12:24:04 +0530
-Subject: [PATCH] drivers: misc: mikrobus add support alternate Click ID EEPROM
-
-Add support for Alternate Click ID EEPROM Part No. DS28E36
-
-Signed-off-by: vaishnav <vaishnav@beagleboard.org>
----
- drivers/misc/mikrobus/mikrobus_core.c | 31 +----
- drivers/misc/mikrobus/mikrobus_id.c | 171 +++++++++++++++-----------
- 2 files changed, 103 insertions(+), 99 deletions(-)
-
-diff --git a/drivers/misc/mikrobus/mikrobus_core.c b/drivers/misc/mikrobus/mikrobus_core.c
-index 5700396b83e4..c4511bc2846c 100644
---- a/drivers/misc/mikrobus/mikrobus_core.c
-+++ b/drivers/misc/mikrobus/mikrobus_core.c
-@@ -78,7 +78,7 @@ int mikrobus_port_scan_eeprom(struct mikrobus_port *port)
- if (retval != 1) {
- dev_err(&port->dev, "failed to fetch manifest start address %d\n",
- retval);
-- return -EINVAL;
-+ header[0] = 0;
- }
- manifest_start_addr = header[0] << 8;
- pr_info("manifest start address is 0x%x \n", manifest_start_addr);
-@@ -255,7 +255,7 @@ int mikrobus_port_pinctrl_select(struct mikrobus_port *port)
- port->pinctrl_selected[i]);
- if (!IS_ERR(state)) {
- retval = pinctrl_select_state(port->pinctrl, state);
-- pr_info("setting pinctrl %s\n",
-+ pr_debug("setting pinctrl %s\n",
- port->pinctrl_selected[i]);
- if (retval != 0) {
- dev_err(&port->dev, "failed to select state %s\n",
-@@ -400,26 +400,6 @@ static void mikrobus_board_device_release_all(struct addon_board_info *info)
- }
- }
-
--static struct software_node *software_node_alloc(const struct property_entry *properties)
--{
-- struct property_entry *props;
-- struct software_node *node;
--
-- props = property_entries_dup(properties);
-- if (IS_ERR(props))
-- return ERR_CAST(props);
--
-- node = kzalloc(sizeof(*node), GFP_KERNEL);
-- if (!node) {
-- property_entries_free(props);
-- return ERR_PTR(-ENOMEM);
-- }
--
-- node->properties = props;
--
-- return node;
--}
--
- static int mikrobus_device_register(struct mikrobus_port *port,
- struct board_device_info *dev, char *board_name)
- {
-@@ -515,7 +495,7 @@ static int mikrobus_device_register(struct mikrobus_port *port,
- if (dev->irq)
- i2c->irq = mikrobus_irq_get(port, dev->irq, dev->irq_type);
- if (dev->properties)
-- i2c->swnode = software_node_alloc(dev->properties);
-+ i2c->fwnode = fwnode_create_software_node(dev->properties, NULL);
- i2c->addr = dev->reg;
- dev->dev_client = (void *) i2c_new_client_device(port->i2c_adap, i2c);
- break;
-@@ -625,7 +605,6 @@ static int mikrobus_port_id_eeprom_probe(struct mikrobus_port *port)
- char devname[MIKROBUS_NAME_SIZE];
- char drvname[MIKROBUS_NAME_SIZE] = "w1-gpio";
- int retval;
-- int i;
-
- mikrobus_id_eeprom_w1_device = kzalloc(sizeof(*mikrobus_id_eeprom_w1_device), GFP_KERNEL);
- if (!mikrobus_id_eeprom_w1_device)
-@@ -773,7 +752,7 @@ int mikrobus_port_gb_register(struct gbphy_host *host, void *manifest_blob, size
- struct gb_connection *spi_connection;
- struct gb_gpio_controller *ggc;
- struct mikrobus_port *port;
-- struct gpio_desc *desc;
-+ // struct gpio_desc *desc;
- struct gpio_descs *descs;
- int retval;
-
-@@ -827,7 +806,7 @@ int mikrobus_port_gb_register(struct gbphy_host *host, void *manifest_blob, size
- INIT_LIST_HEAD(&board->devices);
- retval = mikrobus_manifest_parse(board, manifest_blob, manifest_size);
- if (!retval) {
-- dev_err(&port->dev, "failed to parse manifest, size %lu\n",
-+ dev_err(&port->dev, "failed to parse manifest, size %u\n",
- manifest_size);
- retval = -EINVAL;
- goto err_free_board;
-diff --git a/drivers/misc/mikrobus/mikrobus_id.c b/drivers/misc/mikrobus/mikrobus_id.c
-index 2b97342327d9..d8e9b3660b6b 100644
---- a/drivers/misc/mikrobus/mikrobus_id.c
-+++ b/drivers/misc/mikrobus/mikrobus_id.c
-@@ -16,18 +16,19 @@
-
- #include <linux/mikrobus.h>
-
-+#define W1_EEPROM_MIKROBUS_SECONDARY_ID 0x4C
- #define W1_EEPROM_MIKROBUS_ID 0x43
--
--#define W1_MIKROBUS_ID_EEPROM_SIZE 0x0A00
-+#define W1_MIKROBUS_ID_EEPROM_SIZE 0x0A00
-+#define W1_MIKROBUS_ID_EEPROM_SECONDARY_SIZE 0x0200
-+#define W1_MIKROBUS_ID_EEPROM_SECONDARY_PAGE_SIZE 32
- #define W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE 32
- #define W1_MIKROBUS_ID_EEPROM_VERIFY_SCRATCH_SIZE 35
- #define W1_MIKROBUS_ID_READ_EEPROM 0xF0
-+#define W1_MIKROBUS_ID_READ_SECONDARY_EEPROM 0x69
-+#define W1_MIKROBUS_ID_RELEASE_SECONDARY_EEPROM 0xAA
- #define W1_MIKROBUS_ID_EEPROM_READ_RETRIES 10
--#define W1_MIKROBUS_ID_EEPROM_WRITE_RETRIES 5
--#define W1_MIKROBUS_ID_EEPROM_WRITE_SCRATCH 0x0F
--#define W1_MIKROBUS_ID_EEPROM_READ_SCRATCH 0xAA
--#define W1_MIKROBUS_ID_EEPROM_COPY_SCRATCH 0x55
- #define W1_MIKROBUS_ID_EEPROM_TPROG_MS 20
-+#define MIKROBUS_ID_USER_EEPROM_ADDR 0x0A0A
-
- static int w1_mikrobus_id_readblock(struct w1_slave *sl, int off, int count, char *buf)
- {
-@@ -64,90 +65,80 @@ static int w1_mikrobus_id_readblock(struct w1_slave *sl, int off, int count, cha
- return -EIO;
- }
-
--static int w1_mikrobus_id_movescratch(struct w1_slave *sl, int addr, char *buf)
-+static int w1_mikrobus_id_readpage_secondary(struct w1_slave *sl, int pageaddr, char *buf)
- {
-- u8 wrbuf[4];
-- u8 scratchpad_verify[W1_MIKROBUS_ID_EEPROM_VERIFY_SCRATCH_SIZE];
-- u8 TA1, TA2, ES;
-- int verify_status;
-- int tries;
--
-- wrbuf[0] = W1_MIKROBUS_ID_EEPROM_WRITE_SCRATCH;
-- wrbuf[1] = addr & 0xFF;
-- wrbuf[2] = addr >> 8;
-+ u8 crc_rdbuf[2];
-
-- tries = W1_MIKROBUS_ID_EEPROM_WRITE_RETRIES;
-- do {
-- if (w1_reset_select_slave(sl))
-- return -1;
-- w1_write_block(sl->master, wrbuf, 3);
-- w1_write_block(sl->master, buf, W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-- if (w1_reset_select_slave(sl))
-- return -1;
-- w1_write_8(sl->master, W1_MIKROBUS_ID_EEPROM_READ_SCRATCH);
-- TA1 = w1_read_8(sl->master);
-- TA2 = w1_read_8(sl->master);
-- ES = w1_read_8(sl->master);
-- w1_read_block(sl->master, scratchpad_verify, W1_MIKROBUS_ID_EEPROM_VERIFY_SCRATCH_SIZE);
-- verify_status = memcmp(buf, scratchpad_verify, W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-- } while(verify_status && --tries);
--
-- if(!tries && verify_status){
-- dev_err(&sl->dev, "verify scratchpad failed %d times\n",
-- W1_MIKROBUS_ID_EEPROM_WRITE_RETRIES);
-- return -EIO;
-- }
--
-- wrbuf[0] = W1_MIKROBUS_ID_EEPROM_COPY_SCRATCH;
-- wrbuf[1] = addr & 0xFF;
-- wrbuf[2] = addr >> 8;
-- wrbuf[3] = ES;
- if (w1_reset_select_slave(sl))
-- return -1;
-- w1_write_block(sl->master, wrbuf, 4);
-- msleep(W1_MIKROBUS_ID_EEPROM_TPROG_MS);
-+ return -1;
-+ w1_write_8(sl->master, W1_MIKROBUS_ID_READ_SECONDARY_EEPROM);
-+ w1_write_8(sl->master, pageaddr);
-+ w1_read_block(sl->master, crc_rdbuf, 2);
-+ w1_write_8(sl->master, W1_MIKROBUS_ID_RELEASE_SECONDARY_EEPROM);
-+ msleep(10);
-+ w1_read_block(sl->master, crc_rdbuf, 1);
-+ w1_read_block(sl->master, buf, W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-+ w1_read_block(sl->master, crc_rdbuf, 2);
- return 0;
- }
-
--static int w1_mikrobus_id_writeblock(struct w1_slave *sl, int off, int count, char *buf)
-+static int w1_mikrobus_id_readbuf_secondary(struct w1_slave *sl, int count, char *buf)
- {
-- u16 wraddr = 0;
-- u16 len = count - (count % W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-- u8 scratchpad_write[W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE] = {0};
--
-- while(len > 0) {
-- w1_mikrobus_id_movescratch(sl, wraddr + off, buf + wraddr);
-- wraddr += W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE;
-- len -= W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE;
-+ u8 pageaddr = 0;
-+ int iter, index, ret;
-+ int len = count - (count % W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-+ u8 temp_rdbuf[W1_MIKROBUS_ID_EEPROM_SECONDARY_PAGE_SIZE];
-+
-+ while(len > 0) {
-+ ret = w1_mikrobus_id_readpage_secondary(sl, pageaddr, buf + (W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE*pageaddr));
-+ pageaddr += 1;
-+ len -= W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE;
- }
-
- if(count % W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE){
-- memcpy(scratchpad_write, buf + wraddr, count % W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE);
-- w1_mikrobus_id_movescratch(sl, wraddr + off, scratchpad_write);
-+ ret = w1_mikrobus_id_readpage_secondary(sl, pageaddr, temp_rdbuf);
-+ for(iter = W1_MIKROBUS_ID_EEPROM_SCRATCH_SIZE*pageaddr, index=0; iter < count; iter++, index++)
-+ buf[iter] = temp_rdbuf[index];
- }
--
-- return 0;
-+ return ret;
- }
-
--static int w1_mikrobus_id_nvmem_read(void *priv, unsigned int off, void *buf, size_t count)
-+static int w1_mikrobus_id_readblock_secondary(struct w1_slave *sl, int off, int count, char *buf)
- {
-- struct w1_slave *sl = priv;
-- int ret;
-+ u8 *cmp;
-+ int tries = W1_MIKROBUS_ID_EEPROM_READ_RETRIES;
-
-- mutex_lock(&sl->master->bus_mutex);
-- ret = w1_mikrobus_id_readblock(sl, off, count, buf);
-- mutex_unlock(&sl->master->bus_mutex);
--
-- return ret;
-+ if(off == MIKROBUS_ID_USER_EEPROM_ADDR && count == 1) {
-+ buf[0] = 0;
-+ return 0;
-+ }
-+
-+ do {
-+ w1_mikrobus_id_readbuf_secondary(sl, count, buf);
-+ cmp = kzalloc(count, GFP_KERNEL);
-+ if (!cmp)
-+ return -ENOMEM;
-+ w1_mikrobus_id_readbuf_secondary(sl, count, cmp);
-+ if (!memcmp(cmp, buf, count)){
-+ kfree(cmp);
-+ return 0;
-+ }
-+ } while (--tries);
-+
-+ kfree(cmp);
-+ return -EINVAL;
- }
-
--static int w1_mikrobus_id_nvmem_write(void *priv, unsigned int off, void *buf, size_t count)
-+static int w1_mikrobus_id_nvmem_read(void *priv, unsigned int off, void *buf, size_t count)
- {
- struct w1_slave *sl = priv;
- int ret;
-
- mutex_lock(&sl->master->bus_mutex);
-- ret = w1_mikrobus_id_writeblock(sl, off, count, buf);
-+ if (sl->family->fid == W1_EEPROM_MIKROBUS_SECONDARY_ID)
-+ ret = w1_mikrobus_id_readblock_secondary(sl, off, count, buf);
-+ else
-+ ret = w1_mikrobus_id_readblock(sl, off, count, buf);
- mutex_unlock(&sl->master->bus_mutex);
-
- return ret;
-@@ -160,12 +151,12 @@ static int w1_mikrobus_id_add_slave(struct w1_slave *sl)
- struct nvmem_config nvmem_cfg = {
- .dev = &sl->dev,
- .reg_read = w1_mikrobus_id_nvmem_read,
-- .reg_write = w1_mikrobus_id_nvmem_write,
- .type = NVMEM_TYPE_EEPROM,
-- .read_only = false,
-+ .read_only = true,
- .word_size = 1,
- .stride = 1,
-- .size = W1_MIKROBUS_ID_EEPROM_SIZE,
-+ .size = (sl->family->fid == W1_EEPROM_MIKROBUS_SECONDARY_ID) ?
-+ W1_MIKROBUS_ID_EEPROM_SECONDARY_SIZE: W1_MIKROBUS_ID_EEPROM_SIZE,
- .priv = sl,
- };
-
-@@ -181,7 +172,7 @@ static int w1_mikrobus_id_add_slave(struct w1_slave *sl)
- return PTR_ERR_OR_ZERO(nvmem);
- }
-
--static const struct w1_family_ops w1_family_mikrobus_id_fops = {
-+static struct w1_family_ops w1_family_mikrobus_id_fops = {
- .add_slave = w1_mikrobus_id_add_slave,
- };
-
-@@ -189,9 +180,43 @@ static struct w1_family w1_family_mikrobus_id = {
- .fid = W1_EEPROM_MIKROBUS_ID,
- .fops = &w1_family_mikrobus_id_fops,
- };
--module_w1_family(w1_family_mikrobus_id);
-+
-+static struct w1_family w1_family_mikrobus_id_alternate = {
-+ .fid = W1_EEPROM_MIKROBUS_SECONDARY_ID,
-+ .fops = &w1_family_mikrobus_id_fops,
-+};
-+
-+static int __init w1_mikrobusid_init(void)
-+{
-+ int err;
-+
-+ err = w1_register_family(&w1_family_mikrobus_id);
-+ if (err)
-+ return err;
-+
-+ err = w1_register_family(&w1_family_mikrobus_id_alternate);
-+ if (err)
-+ goto err_mikrobusidinit;
-+
-+
-+ return 0;
-+
-+err_mikrobusidinit:
-+ w1_unregister_family(&w1_family_mikrobus_id);
-+ return err;
-+}
-+
-+static void __exit w1_mikrobusid_exit(void)
-+{
-+ w1_unregister_family(&w1_family_mikrobus_id);
-+ w1_unregister_family(&w1_family_mikrobus_id_alternate);
-+}
-+
-+module_init(w1_mikrobusid_init);
-+module_exit(w1_mikrobusid_exit);
-
- MODULE_AUTHOR("Vaishnav M A <vaishnav@beagleboard.org>");
- MODULE_DESCRIPTION("w1 family ac driver for mikroBUS ID EEPROM");
- MODULE_LICENSE("GPL");
- MODULE_ALIAS("w1-family-" __stringify(W1_EEPROM_MIKROBUS_ID));
-+MODULE_ALIAS("w1-family-" __stringify(W1_EEPROM_MIKROBUS_SECONDARY_ID));
---
-2.25.1
-
diff --git a/patches/drivers/powervr/0001-sizes.h-Add-entries-between-32G-and-64T.patch b/patches/drivers/powervr/0001-sizes.h-Add-entries-between-32G-and-64T.patch
deleted file mode 100644
index a8d80388b4e521a3a63e155465b99d49ef4890fb..0000000000000000000000000000000000000000
--- a/patches/drivers/powervr/0001-sizes.h-Add-entries-between-32G-and-64T.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From b0719e1872b919c3ef1f99972406c20e4d588f00 Mon Sep 17 00:00:00 2001
-From: Matt Coster <matt.coster@imgtec.com>
-Date: Wed, 1 Sep 2021 15:36:33 +0100
-Subject: [PATCH 1/3] sizes.h: Add entries between 32G and 64T
-
-Signed-off-by: Matt Coster <matt.coster@imgtec.com>
----
- include/linux/sizes.h | 19 +++++++++++++++----
- 1 file changed, 15 insertions(+), 4 deletions(-)
-
-diff --git a/include/linux/sizes.h b/include/linux/sizes.h
-index 1ac79bcee2bb..e19e41ac45e0 100644
---- a/include/linux/sizes.h
-+++ b/include/linux/sizes.h
-@@ -43,10 +43,21 @@
- #define SZ_1G 0x40000000
- #define SZ_2G 0x80000000
-
--#define SZ_4G _AC(0x100000000, ULL)
--#define SZ_8G _AC(0x200000000, ULL)
--#define SZ_16G _AC(0x400000000, ULL)
--#define SZ_32G _AC(0x800000000, ULL)
-+#define SZ_4G _AC(0x000100000000, ULL)
-+#define SZ_8G _AC(0x000200000000, ULL)
-+#define SZ_16G _AC(0x000400000000, ULL)
-+#define SZ_32G _AC(0x000800000000, ULL)
-+#define SZ_64G _AC(0x001000000000, ULL)
-+#define SZ_128G _AC(0x002000000000, ULL)
-+#define SZ_256G _AC(0x004000000000, ULL)
-+#define SZ_512G _AC(0x008000000000, ULL)
-+
-+#define SZ_1T _AC(0x010000000000, ULL)
-+#define SZ_2T _AC(0x020000000000, ULL)
-+#define SZ_4T _AC(0x040000000000, ULL)
-+#define SZ_8T _AC(0x080000000000, ULL)
-+#define SZ_16T _AC(0x100000000000, ULL)
-+#define SZ_32T _AC(0x200000000000, ULL)
- #define SZ_64T _AC(0x400000000000, ULL)
-
- #endif /* __LINUX_SIZES_H__ */
---
-2.30.2
-
diff --git a/patches/drivers/powervr/0002-dt-bindings-gpu-add-bindings-for-Imagination-Technol.patch b/patches/drivers/powervr/0002-dt-bindings-gpu-add-bindings-for-Imagination-Technol.patch
deleted file mode 100644
index bd2ddf7b97053a6e1d55126d544a7167006bb2b0..0000000000000000000000000000000000000000
--- a/patches/drivers/powervr/0002-dt-bindings-gpu-add-bindings-for-Imagination-Technol.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From 1de9dfaf563c1fb86268358d188c189afe4a10e0 Mon Sep 17 00:00:00 2001
-From: Sarah Walker <sarah.walker@imgtec.com>
-Date: Thu, 12 Aug 2021 08:50:45 +0100
-Subject: [PATCH 2/3] dt-bindings: gpu: add bindings for Imagination
- Technologies PowerVR Rogue GPUs
-
-Co-authored-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
-Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
-Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
----
- .../devicetree/bindings/gpu/img,powervr.yaml | 101 ++++++++++++++++++
- 1 file changed, 101 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/gpu/img,powervr.yaml
-
-diff --git a/Documentation/devicetree/bindings/gpu/img,powervr.yaml b/Documentation/devicetree/bindings/gpu/img,powervr.yaml
-new file mode 100644
-index 000000000000..9440a01434e5
---- /dev/null
-+++ b/Documentation/devicetree/bindings/gpu/img,powervr.yaml
-@@ -0,0 +1,101 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR MIT)
-+# Copyright (c) 2022 Imagination Technologies Ltd.
-+%YAML 1.2
-+---
-+$id: "http://devicetree.org/schemas/gpu/img-powervr.yaml#"
-+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-+
-+title: Imagination Technologies PowerVR GPU
-+
-+maintainers:
-+ - Sarah Walker <sarah.walker@imgtec.com>
-+
-+properties:
-+ compatible:
-+ oneOf:
-+ - items:
-+ - enum:
-+ - mediatek,mt8173-gpu
-+ - const: img,powervr-series6xt
-+
-+ reg:
-+ minItems: 1
-+ maxItems: 1
-+
-+ clocks:
-+ minItems: 1
-+ maxItems: 3
-+
-+ clock-names:
-+ items:
-+ - const: core_clk
-+ - const: mem_clk
-+ - const: sys_clk
-+
-+ interrupts:
-+ items:
-+ - description: GPU interrupt
-+
-+ interrupt-names:
-+ items:
-+ - const: gpu
-+
-+ power-domains:
-+ maxItems: 1
-+
-+ operating-points-v2: true
-+ power-supply: true
-+
-+ "#cooling-cells":
-+ const: 2
-+
-+required:
-+ - compatible
-+ - reg
-+ - clocks
-+ - clock-names
-+ - interrupts
-+ - interrupt-names
-+
-+allOf:
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ const: mediatek,mt8173-gpu
-+ then:
-+ properties:
-+ reg:
-+ minItems: 2
-+ maxItems: 2
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ const: img,powervr-series6xt
-+ then:
-+ properties:
-+ clocks:
-+ minItems: 3
-+
-+examples:
-+ - |
-+ #include <dt-bindings/interrupt-controller/irq.h>
-+ #include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+ gpu@13000000 {
-+ compatible = "mediatek,mt8173-gpu", "img,powervr-series6xt";
-+ reg = <0 0x13000000 0 0xffff>, <0 0x13fff000 0 0x1000>;
-+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MFG>;
-+ power-supply = <&da9211_vgpu_reg>;
-+ operating-points-v2 = <&gpu_opp_table>;
-+ clocks = <&gpu_ckgen 0>,
-+ <&gpu_ckgen 1>,
-+ <&gpu_ckgen 2>;
-+ clock-names = "core_clk",
-+ "mem_clk",
-+ "sys_clk";
-+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "gpu";
-+ };
-+
---
-2.30.2
-
diff --git a/patches/drivers/powervr/0003-drm-imagination-Add-initial-Imagination-Technologies.patch b/patches/drivers/powervr/0003-drm-imagination-Add-initial-Imagination-Technologies.patch
deleted file mode 100644
index 315035496bc1dadf693c125e712e7d20c60741d4..0000000000000000000000000000000000000000
--- a/patches/drivers/powervr/0003-drm-imagination-Add-initial-Imagination-Technologies.patch
+++ /dev/null
@@ -1,28872 +0,0 @@
-From 03d958cbedb0fedd7e5c4aaa77e9dd41990dc3f9 Mon Sep 17 00:00:00 2001
-From: Frank Binns <frank.binns@imgtec.com>
-Date: Fri, 23 Apr 2021 16:41:22 +0100
-Subject: [PATCH 3/3] drm/imagination: Add initial Imagination Technologies
- PowerVR driver
-
-Co-authored-by: Sarah Walker <sarah.walker@imgtec.com>
-Co-authored-by: Matt Coster <matt.coster@imgtec.com>
-Co-authored-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
-Signed-off-by: Frank Binns <frank.binns@imgtec.com>
-Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
-Signed-off-by: Matt Coster <matt.coster@imgtec.com>
-Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
----
- drivers/gpu/drm/Kconfig | 2 +
- drivers/gpu/drm/Makefile | 1 +
- drivers/gpu/drm/imagination/Kconfig | 11 +
- drivers/gpu/drm/imagination/Makefile | 29 +
- drivers/gpu/drm/imagination/pvr_ccb.c | 282 +
- drivers/gpu/drm/imagination/pvr_ccb.h | 48 +
- drivers/gpu/drm/imagination/pvr_cccb.c | 328 +
- drivers/gpu/drm/imagination/pvr_cccb.h | 103 +
- drivers/gpu/drm/imagination/pvr_context.c | 727 ++
- drivers/gpu/drm/imagination/pvr_context.h | 181 +
- drivers/gpu/drm/imagination/pvr_device.c | 613 ++
- drivers/gpu/drm/imagination/pvr_device.h | 776 +++
- drivers/gpu/drm/imagination/pvr_device_info.c | 108 +
- drivers/gpu/drm/imagination/pvr_device_info.h | 54 +
- drivers/gpu/drm/imagination/pvr_drv.c | 885 +++
- drivers/gpu/drm/imagination/pvr_drv.h | 19 +
- drivers/gpu/drm/imagination/pvr_fence.c | 250 +
- drivers/gpu/drm/imagination/pvr_fence.h | 148 +
- drivers/gpu/drm/imagination/pvr_free_list.c | 377 +
- drivers/gpu/drm/imagination/pvr_free_list.h | 139 +
- drivers/gpu/drm/imagination/pvr_fw.c | 900 +++
- drivers/gpu/drm/imagination/pvr_fw.h | 163 +
- drivers/gpu/drm/imagination/pvr_fw_info.h | 106 +
- drivers/gpu/drm/imagination/pvr_fw_meta.c | 834 +++
- drivers/gpu/drm/imagination/pvr_fw_mips.c | 185 +
- drivers/gpu/drm/imagination/pvr_fw_mips.h | 29 +
- drivers/gpu/drm/imagination/pvr_fw_trace.c | 487 ++
- drivers/gpu/drm/imagination/pvr_fw_trace.h | 70 +
- drivers/gpu/drm/imagination/pvr_gem.c | 1082 +++
- drivers/gpu/drm/imagination/pvr_gem.h | 383 +
- drivers/gpu/drm/imagination/pvr_hwrt.c | 379 +
- drivers/gpu/drm/imagination/pvr_hwrt.h | 171 +
- drivers/gpu/drm/imagination/pvr_job.c | 969 +++
- drivers/gpu/drm/imagination/pvr_job.h | 32 +
- drivers/gpu/drm/imagination/pvr_object.c | 223 +
- drivers/gpu/drm/imagination/pvr_object.h | 60 +
- .../gpu/drm/imagination/pvr_rogue_cr_defs.h | 6191 +++++++++++++++++
- drivers/gpu/drm/imagination/pvr_rogue_defs.h | 162 +
- drivers/gpu/drm/imagination/pvr_rogue_fwif.h | 2314 ++++++
- .../drm/imagination/pvr_rogue_fwif_client.h | 158 +
- .../drm/imagination/pvr_rogue_fwif_common.h | 55 +
- .../pvr_rogue_fwif_resetframework.h | 28 +
- .../gpu/drm/imagination/pvr_rogue_fwif_sf.h | 846 +++
- .../drm/imagination/pvr_rogue_fwif_shared.h | 235 +
- .../drm/imagination/pvr_rogue_heap_config.h | 103 +
- drivers/gpu/drm/imagination/pvr_rogue_meta.h | 357 +
- drivers/gpu/drm/imagination/pvr_rogue_mips.h | 336 +
- .../gpu/drm/imagination/pvr_rogue_mmu_defs.h | 136 +
- drivers/gpu/drm/imagination/pvr_vendor.h | 77 +
- drivers/gpu/drm/imagination/pvr_vm.c | 4177 +++++++++++
- drivers/gpu/drm/imagination/pvr_vm.h | 192 +
- drivers/gpu/drm/imagination/pvr_vm_mips.c | 220 +
- drivers/gpu/drm/imagination/pvr_vm_mips.h | 22 +
- .../gpu/drm/imagination/vendor/pvr_mt8173.c | 121 +
- include/uapi/drm/pvr_drm.h | 1524 ++++
- 55 files changed, 28408 insertions(+)
- create mode 100644 drivers/gpu/drm/imagination/Kconfig
- create mode 100644 drivers/gpu/drm/imagination/Makefile
- create mode 100644 drivers/gpu/drm/imagination/pvr_ccb.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_ccb.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_cccb.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_cccb.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_context.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_context.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_device.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_device.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_device_info.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_device_info.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_drv.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_drv.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_fence.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_fence.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_free_list.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_free_list.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_fw.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_fw.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_fw_info.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_fw_meta.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_fw_mips.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_fw_mips.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_fw_trace.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_fw_trace.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_gem.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_gem.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_hwrt.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_hwrt.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_job.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_job.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_object.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_object.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_defs.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_fwif.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_fwif_client.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_fwif_common.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_fwif_resetframework.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_fwif_sf.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_meta.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_mips.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_rogue_mmu_defs.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_vendor.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_vm.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_vm.h
- create mode 100644 drivers/gpu/drm/imagination/pvr_vm_mips.c
- create mode 100644 drivers/gpu/drm/imagination/pvr_vm_mips.h
- create mode 100644 drivers/gpu/drm/imagination/vendor/pvr_mt8173.c
- create mode 100644 include/uapi/drm/pvr_drm.h
-
-diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
-index b1f22e457fd0..ff6c83027177 100644
---- a/drivers/gpu/drm/Kconfig
-+++ b/drivers/gpu/drm/Kconfig
-@@ -390,6 +390,8 @@ source "drivers/gpu/drm/gud/Kconfig"
-
- source "drivers/gpu/drm/sprd/Kconfig"
-
-+source "drivers/gpu/drm/imagination/Kconfig"
-+
- config DRM_HYPERV
- tristate "DRM Support for Hyper-V synthetic video device"
- depends on DRM && PCI && MMU && HYPERV
-diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
-index 301a44dc18e3..6e063a24c1c5 100644
---- a/drivers/gpu/drm/Makefile
-+++ b/drivers/gpu/drm/Makefile
-@@ -135,3 +135,4 @@ obj-y += xlnx/
- obj-y += gud/
- obj-$(CONFIG_DRM_HYPERV) += hyperv/
- obj-$(CONFIG_DRM_SPRD) += sprd/
-+obj-$(CONFIG_DRM_POWERVR) += imagination/
-diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imagination/Kconfig
-new file mode 100644
-index 000000000000..83248822d0ed
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/Kconfig
-@@ -0,0 +1,11 @@
-+# SPDX-License-Identifier: GPL-2.0 OR MIT
-+# Copyright (c) 2022 Imagination Technologies Ltd.
-+
-+config DRM_POWERVR
-+ tristate "Imagination Technologies PowerVR Graphics"
-+ depends on ARM64
-+ depends on DRM
-+ select FW_LOADER
-+ help
-+ Choose this option if you have a system that has an Imagination
-+ Technologies PowerVR Rogue GPU.
-diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagination/Makefile
-new file mode 100644
-index 000000000000..74725a03e5a0
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/Makefile
-@@ -0,0 +1,29 @@
-+# SPDX-License-Identifier: GPL-2.0 OR MIT
-+# Copyright (c) 2022 Imagination Technologies Ltd.
-+
-+subdir-cc-flags-y := -I$(srctree)/$(src)
-+
-+powervr-y := \
-+ pvr_ccb.o \
-+ pvr_cccb.o \
-+ pvr_context.o \
-+ pvr_device.o \
-+ pvr_device_info.o \
-+ pvr_drv.o \
-+ pvr_fence.o \
-+ pvr_free_list.o \
-+ pvr_fw.o \
-+ pvr_fw_meta.o \
-+ pvr_fw_mips.o \
-+ pvr_fw_trace.o \
-+ pvr_gem.o \
-+ pvr_hwrt.o \
-+ pvr_job.o \
-+ pvr_object.o \
-+ pvr_vm.o \
-+ pvr_vm_mips.o
-+
-+powervr-y += \
-+ vendor/pvr_mt8173.o
-+
-+obj-$(CONFIG_DRM_POWERVR) += powervr.o
-diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c
-new file mode 100644
-index 000000000000..41d65061f4b2
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_ccb.c
-@@ -0,0 +1,282 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_ccb.h"
-+#include "pvr_device.h"
-+#include "pvr_fw.h"
-+#include "pvr_gem.h"
-+
-+#include <linux/compiler.h>
-+#include <linux/delay.h>
-+#include <linux/jiffies.h>
-+#include <linux/kernel.h>
-+#include <linux/mutex.h>
-+#include <linux/types.h>
-+#include <linux/workqueue.h>
-+
-+#define ACQUIRE_SLOT_TIMEOUT (1 * HZ) /* 1s */
-+
-+/**
-+ * pvr_ccb_init() - Initialise a CCB
-+ * @pvr_dev: Device pointer.
-+ * @pvr_ccb: Pointer to CCB structure to initialise.
-+ * @num_cmds_log2: Log2 of number of commands in this CCB.
-+ * @cmd_size: Command size for this CCB.
-+ *
-+ * Return:
-+ * * Zero on success, or
-+ * * Any error code returned by pvr_gem_create_and_map_fw_object().
-+ */
-+static int
-+pvr_ccb_init(struct pvr_device *pvr_dev, struct pvr_ccb *pvr_ccb,
-+ u32 num_cmds_log2, size_t cmd_size)
-+{
-+ u32 num_cmds = 1 << num_cmds_log2;
-+ u32 ccb_size = num_cmds * cmd_size;
-+ int err;
-+
-+ mutex_init(&pvr_ccb->lock);
-+
-+ /*
-+ * Map CCB and control structure as uncached, so we don't have to flush
-+ * CPU cache repeatedly when polling for space.
-+ */
-+ pvr_ccb->ctrl = pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*pvr_ccb->ctrl),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED,
-+ &pvr_ccb->ctrl_obj);
-+ if (IS_ERR(pvr_ccb->ctrl)) {
-+ err = PTR_ERR(pvr_ccb->ctrl);
-+ goto err_out;
-+ }
-+
-+ pvr_ccb->ccb = pvr_gem_create_and_map_fw_object(pvr_dev, ccb_size,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_ccb->ccb_obj);
-+ if (IS_ERR(pvr_ccb->ccb)) {
-+ err = PTR_ERR(pvr_ccb->ccb);
-+ goto err_free_ctrl;
-+ }
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_ccb->ctrl_obj,
-+ &pvr_ccb->ctrl_fw_addr));
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_ccb->ccb_obj,
-+ &pvr_ccb->ccb_fw_addr));
-+
-+ pvr_ccb->ctrl->write_offset = 0;
-+ pvr_ccb->ctrl->read_offset = 0;
-+ pvr_ccb->ctrl->wrap_mask = num_cmds - 1;
-+ pvr_ccb->ctrl->cmd_size = cmd_size;
-+
-+ return 0;
-+
-+err_free_ctrl:
-+ pvr_fw_object_vunmap(pvr_ccb->ctrl_obj, pvr_ccb->ctrl, false);
-+ pvr_fw_object_release(pvr_ccb->ctrl_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_ccb_fini() - Release CCB structure
-+ * @pvr_ccb: CCB to release.
-+ */
-+void
-+pvr_ccb_fini(struct pvr_ccb *pvr_ccb)
-+{
-+ pvr_fw_object_vunmap(pvr_ccb->ccb_obj, pvr_ccb->ccb, false);
-+ pvr_fw_object_release(pvr_ccb->ccb_obj);
-+
-+ pvr_fw_object_vunmap(pvr_ccb->ctrl_obj, pvr_ccb->ctrl, false);
-+ pvr_fw_object_release(pvr_ccb->ctrl_obj);
-+}
-+
-+/**
-+ * pvr_ccb_slot_available_locked() - Test whether any slots are available in CCB
-+ * @pvr_ccb: CCB to test.
-+ * @write_offset: Address to store number of next available slot. May be %NULL.
-+ *
-+ * Caller must hold @pvr_ccb->lock.
-+ *
-+ * Return:
-+ * * %true if a slot is available, or
-+ * * %false if no slot is available.
-+ */
-+static __always_inline bool
-+pvr_ccb_slot_available_locked(struct pvr_ccb *pvr_ccb, u32 *write_offset)
-+{
-+ struct rogue_fwif_ccb_ctl *ctrl = pvr_ccb->ctrl;
-+ u32 next_write_offset = (ctrl->write_offset + 1) & ctrl->wrap_mask;
-+
-+ lockdep_assert_held(&pvr_ccb->lock);
-+
-+ if (ctrl->read_offset != next_write_offset) {
-+ if (write_offset)
-+ *write_offset = next_write_offset;
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+/**
-+ * pvr_ccb_acquire_slot_locked() - Acquire slot in CCB
-+ * @pvr_ccb: CCB to acquire slot in.
-+ * @write_offset: Address to store acquired slot number.
-+ *
-+ * Caller must hold @pvr_ccb->lock.
-+ *
-+ * Return:
-+ * * Zero on success, or
-+ * * -EBUSY if function times out waiting for a slot.
-+ */
-+static int
-+pvr_ccb_acquire_slot_locked(struct pvr_ccb *pvr_ccb, u32 *write_offset)
-+{
-+ unsigned long start_timestamp = jiffies;
-+
-+ lockdep_assert_held(&pvr_ccb->lock);
-+
-+ while ((jiffies - start_timestamp) < ACQUIRE_SLOT_TIMEOUT) {
-+ if (pvr_ccb_slot_available_locked(pvr_ccb, write_offset))
-+ return 0;
-+ usleep_range(1, 50);
-+ }
-+
-+ return -EBUSY;
-+}
-+
-+/**
-+ * pvr_fwccb_process_worker() - Process any pending FWCCB commands
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * For this initial implementation, FWCCB commands will be printed to the console but otherwise not
-+ * processed.
-+ */
-+static void
-+pvr_fwccb_process_worker(struct work_struct *work)
-+{
-+ struct pvr_device *pvr_dev = container_of(work, struct pvr_device, fwccb_work);
-+ volatile struct rogue_fwif_fwccb_cmd *fwccb = pvr_dev->fwccb.ccb;
-+ struct rogue_fwif_ccb_ctl *ctrl = pvr_dev->fwccb.ctrl;
-+
-+ mutex_lock(&pvr_dev->fwccb.lock);
-+
-+ while (ctrl->read_offset != ctrl->write_offset) {
-+ drm_info(from_pvr_device(pvr_dev), "Received FWCCB command %x\n",
-+ fwccb[ctrl->read_offset].cmd_type);
-+
-+ ctrl->read_offset = (ctrl->read_offset + 1) & ctrl->wrap_mask;
-+ }
-+
-+ mutex_unlock(&pvr_dev->fwccb.lock);
-+}
-+
-+/**
-+ * pvr_kccb_send_cmd() - Send command to the KCCB
-+ * @pvr_dev: Device pointer.
-+ * @cmd: Command to sent.
-+ * @kccb_slot: Address to store the KCCB slot for this command. May be %NULL.
-+ *
-+ * Returns:
-+ * * Zero on success, or
-+ * * -EBUSY if timeout while waiting for a free KCCB slot.
-+ */
-+int
-+pvr_kccb_send_cmd(struct pvr_device *pvr_dev, struct rogue_fwif_kccb_cmd *cmd,
-+ u32 *kccb_slot)
-+{
-+ struct pvr_ccb *pvr_ccb = &pvr_dev->kccb;
-+ struct rogue_fwif_kccb_cmd *kccb = pvr_ccb->ccb;
-+ struct rogue_fwif_ccb_ctl *ctrl = pvr_ccb->ctrl;
-+ u32 old_write_offset;
-+ u32 new_write_offset;
-+ int err;
-+
-+ mutex_lock(&pvr_ccb->lock);
-+
-+ old_write_offset = ctrl->write_offset;
-+
-+ err = pvr_ccb_acquire_slot_locked(pvr_ccb, &new_write_offset);
-+ if (err)
-+ goto err_unlock;
-+
-+ memcpy(&kccb[old_write_offset], cmd,
-+ sizeof(struct rogue_fwif_kccb_cmd));
-+ if (kccb_slot) {
-+ *kccb_slot = old_write_offset;
-+ /* Clear return status for this slot. */
-+ WRITE_ONCE(pvr_dev->kccb_rtn[old_write_offset],
-+ ROGUE_FWIF_KCCB_RTN_SLOT_NO_RESPONSE);
-+ }
-+ mb(); /* memory barrier */
-+ ctrl->write_offset = new_write_offset;
-+
-+ mutex_unlock(&pvr_ccb->lock);
-+
-+ /* Kick MTS */
-+ pvr_fw_mts_schedule(pvr_dev,
-+ PVR_FWIF_DM_GP & ~ROGUE_CR_MTS_SCHEDULE_DM_CLRMSK);
-+
-+ return 0;
-+
-+err_unlock:
-+ mutex_unlock(&pvr_ccb->lock);
-+
-+ return err;
-+}
-+
-+/**
-+ * pvr_kccb_wait_for_completion() - Wait for a KCCB command to complete
-+ * @pvr_dev: Device pointer.
-+ * @slot_nr: KCCB slot to wait on.
-+ * @timeout: Timeout length (in jiffies).
-+ *
-+ * Returns:
-+ * * Zero on success, or
-+ * * -EBUSY on timeout.
-+ */
-+int
-+pvr_kccb_wait_for_completion(struct pvr_device *pvr_dev, u32 slot_nr,
-+ u32 timeout)
-+{
-+ int ret = wait_event_timeout(pvr_dev->kccb_rtn_q, READ_ONCE(pvr_dev->kccb_rtn[slot_nr]) &
-+ ROGUE_FWIF_KCCB_RTN_SLOT_CMD_EXECUTED, timeout);
-+
-+ return ret ? 0 : -EBUSY;
-+}
-+
-+/**
-+ * pvr_kccb_init() - Initialise device KCCB
-+ * @pvr_dev: Target PowerVR device
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_ccb_init().
-+ */
-+int
-+pvr_kccb_init(struct pvr_device *pvr_dev)
-+{
-+ return pvr_ccb_init(pvr_dev, &pvr_dev->kccb,
-+ ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT,
-+ sizeof(struct rogue_fwif_kccb_cmd));
-+}
-+
-+/**
-+ * pvr_fwccb_init() - Initialise device FWCCB
-+ * @pvr_dev: Target PowerVR device
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_ccb_init().
-+ */
-+int
-+pvr_fwccb_init(struct pvr_device *pvr_dev)
-+{
-+ INIT_WORK(&pvr_dev->fwccb_work, pvr_fwccb_process_worker);
-+
-+ return pvr_ccb_init(pvr_dev, &pvr_dev->fwccb,
-+ ROGUE_FWIF_FWCCB_NUMCMDS_LOG2,
-+ sizeof(struct rogue_fwif_fwccb_cmd));
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_ccb.h b/drivers/gpu/drm/imagination/pvr_ccb.h
-new file mode 100644
-index 000000000000..cae5f61d74fc
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_ccb.h
-@@ -0,0 +1,48 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_CCB_H__
-+#define __PVR_CCB_H__
-+
-+#include "pvr_rogue_fwif.h"
-+
-+#include <linux/mutex.h>
-+#include <linux/types.h>
-+
-+/* Forward declaration from pvr_device.h. */
-+struct pvr_device;
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_fw_object;
-+
-+struct pvr_ccb {
-+ /** @ctrl_obj: FW object representing CCB control structure. */
-+ struct pvr_fw_object *ctrl_obj;
-+ /** @ccb_obj: FW object representing CCB. */
-+ struct pvr_fw_object *ccb_obj;
-+
-+ /** @ctrl_fw_addr: FW virtual address of CCB control structure. */
-+ u32 ctrl_fw_addr;
-+ /** @ccb_fw_addr: FW virtual address of CCB. */
-+ u32 ccb_fw_addr;
-+
-+ /** @lock: Mutex protecting @ctrl and @ccb. */
-+ struct mutex lock;
-+ /**
-+ * @ctrl: Kernel mapping of CCB control structure. @lock must be held
-+ * when accessing.
-+ */
-+ struct rogue_fwif_ccb_ctl *ctrl;
-+ /** @ccb: Kernel mapping of CCB. @lock must be held when accessing. */
-+ void *ccb;
-+};
-+
-+int pvr_kccb_init(struct pvr_device *pvr_dev);
-+int pvr_fwccb_init(struct pvr_device *pvr_dev);
-+void pvr_ccb_fini(struct pvr_ccb *ccb);
-+
-+int pvr_kccb_send_cmd(struct pvr_device *pvr_dev,
-+ struct rogue_fwif_kccb_cmd *cmd, u32 *kccb_slot);
-+int pvr_kccb_wait_for_completion(struct pvr_device *pvr_dev, u32 slot_nr, u32 timeout);
-+
-+#endif /* __PVR_CCB_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_cccb.c b/drivers/gpu/drm/imagination/pvr_cccb.c
-new file mode 100644
-index 000000000000..451cea704c23
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_cccb.c
-@@ -0,0 +1,328 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_ccb.h"
-+#include "pvr_cccb.h"
-+#include "pvr_device.h"
-+#include "pvr_gem.h"
-+#include "pvr_hwrt.h"
-+
-+#include <linux/compiler.h>
-+#include <linux/delay.h>
-+#include <linux/jiffies.h>
-+#include <linux/mutex.h>
-+#include <linux/types.h>
-+
-+#define PADDING_COMMAND_SIZE sizeof(struct rogue_fwif_ccb_cmd_header)
-+
-+static __always_inline u32
-+get_ccb_space(u32 w_off, u32 r_off, u32 ccb_size)
-+{
-+ return (((r_off) - (w_off)) + ((ccb_size)-1)) & ((ccb_size)-1);
-+}
-+
-+/**
-+ * pvr_cccb_init() - Initialise a Client CCB
-+ * @pvr_dev: Device pointer.
-+ * @pvr_cccb: Pointer to Client CCB structure to initialise.
-+ * @size_log2: Log2 size of Client CCB in bytes.
-+ * @name: Name of owner of Client CCB. Used for fence context.
-+ *
-+ * Return:
-+ * * Zero on success, or
-+ * * Any error code returned by pvr_gem_create_and_map_fw_object().
-+ */
-+int
-+pvr_cccb_init(struct pvr_device *pvr_dev, struct pvr_cccb *pvr_cccb,
-+ u32 size_log2, const char *name)
-+{
-+ size_t size = 1 << size_log2;
-+ int err;
-+
-+ mutex_init(&pvr_cccb->lock);
-+
-+ /*
-+ * Map CCCB and control structure as uncached, so we don't have to flush
-+ * CPU cache repeatedly when polling for space.
-+ */
-+ pvr_cccb->ctrl = pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*pvr_cccb->ctrl),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED,
-+ &pvr_cccb->ctrl_obj);
-+ if (IS_ERR(pvr_cccb->ctrl)) {
-+ err = PTR_ERR(pvr_cccb->ctrl);
-+ goto err_out;
-+ }
-+
-+ pvr_cccb->cccb = pvr_gem_create_and_map_fw_object(pvr_dev, size,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_cccb->cccb_obj);
-+ if (IS_ERR(pvr_cccb->cccb)) {
-+ err = PTR_ERR(pvr_cccb->cccb);
-+ goto err_free_ctrl;
-+ }
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_cccb->ctrl_obj,
-+ &pvr_cccb->ctrl_fw_addr));
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_cccb->cccb_obj,
-+ &pvr_cccb->cccb_fw_addr));
-+
-+ WRITE_ONCE(pvr_cccb->ctrl->write_offset, 0);
-+ WRITE_ONCE(pvr_cccb->ctrl->read_offset, 0);
-+ WRITE_ONCE(pvr_cccb->ctrl->dep_offset, 0);
-+ WRITE_ONCE(pvr_cccb->ctrl->wrap_mask, size - 1);
-+ pvr_cccb->size = size;
-+ pvr_cccb->write_offset = 0;
-+ pvr_cccb->wrap_mask = size - 1;
-+
-+ pvr_fence_context_init(pvr_dev, &pvr_cccb->pvr_fence_context, name);
-+
-+ return 0;
-+
-+err_free_ctrl:
-+ pvr_fw_object_vunmap(pvr_cccb->ctrl_obj, pvr_cccb->ctrl, false);
-+ pvr_fw_object_release(pvr_cccb->ctrl_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_cccb_fini() - Release Client CCB structure
-+ * @pvr_cccb: Client CCB to release.
-+ */
-+void
-+pvr_cccb_fini(struct pvr_cccb *pvr_cccb)
-+{
-+ pvr_fw_object_vunmap(pvr_cccb->cccb_obj, pvr_cccb->cccb, false);
-+ pvr_fw_object_release(pvr_cccb->cccb_obj);
-+
-+ pvr_fw_object_vunmap(pvr_cccb->ctrl_obj, pvr_cccb->ctrl, false);
-+ pvr_fw_object_release(pvr_cccb->ctrl_obj);
-+}
-+
-+static void
-+build_padding_command(void *cmd_ptr, u32 remaining)
-+{
-+ struct rogue_fwif_ccb_cmd_header *cmd = cmd_ptr;
-+
-+ WRITE_ONCE(cmd->cmd_type, ROGUE_FWIF_CCB_CMD_TYPE_PADDING);
-+ WRITE_ONCE(cmd->cmd_size, remaining - sizeof(*cmd));
-+}
-+
-+/**
-+ * pvr_cccb_acquire_command_space_locked() - Acquire space in a Client CCB
-+ * @pvr_cccb: Target Client CCB.
-+ * @size: Size of allocation, in bytes.
-+ * @out_ptr: Pointer to location to store CPU pointer to acquired space.
-+ * @new_write_offset: Pointer to location to store new CCB write offset.
-+ *
-+ * Caller must hold @pvr_cccb->lock, and if this function succeeds then it must
-+ * be held until after pvr_release_cccb_space() is called.
-+ *
-+ * Returns:
-+ * * Zero on success, or
-+ * * -EAGAIN if insufficient space is currently available in the CCCB.
-+ */
-+static int
-+pvr_cccb_acquire_command_space_locked(struct pvr_cccb *pvr_cccb, size_t size,
-+ void **out_ptr, u32 *new_write_offset)
-+{
-+ struct rogue_fwif_cccb_ctl *ctrl = pvr_cccb->ctrl;
-+ u32 read_offset = READ_ONCE(ctrl->read_offset);
-+ u32 remaining = pvr_cccb->size - pvr_cccb->write_offset;
-+ u32 required_size = size;
-+ bool padding_required = false;
-+
-+ lockdep_assert_held(&pvr_cccb->lock);
-+
-+ /*
-+ * Always ensure we have enough room for a padding command at the end of
-+ * the CCCB.
-+ */
-+ required_size += PADDING_COMMAND_SIZE;
-+
-+ if (remaining < required_size) {
-+ /*
-+ * Command would need to wrap, so we need to pad the remainder
-+ * of the CCCB.
-+ */
-+ required_size += remaining;
-+ padding_required = true;
-+ }
-+
-+ if (get_ccb_space(pvr_cccb->write_offset, read_offset, pvr_cccb->size) <
-+ required_size)
-+ return -EAGAIN;
-+
-+ if (padding_required) {
-+ /* Add padding command */
-+ build_padding_command(&pvr_cccb->cccb[pvr_cccb->write_offset], remaining);
-+ pvr_cccb->write_offset = 0;
-+ }
-+
-+ *out_ptr = &pvr_cccb->cccb[pvr_cccb->write_offset];
-+ *new_write_offset = pvr_cccb->write_offset + size;
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_cccb_write_command() - Write a command to a Client CCB
-+ * @pvr_cccb: Target Client CCB.
-+ * @cmd_data: Pointer to command to write.
-+ * @size: Size of command in bytes.
-+ *
-+ * Caller must have locked the Client CCB with pvr_cccb_lock().
-+ *
-+ * Returns:
-+ * * Zero on success, or
-+ * * -EAGAIN if insufficient space is currently available in the CCCB.
-+ */
-+int
-+pvr_cccb_write_command(struct pvr_cccb *pvr_cccb, void *cmd_data, size_t size)
-+{
-+ void *cccb_ptr;
-+ u32 new_write_offset;
-+ int err;
-+
-+ lockdep_assert_held(&pvr_cccb->lock);
-+
-+ err = pvr_cccb_acquire_command_space_locked(pvr_cccb, size, &cccb_ptr,
-+ &new_write_offset);
-+ if (err)
-+ return err;
-+
-+ memcpy(cccb_ptr, cmd_data, size);
-+ pvr_cccb->write_offset = new_write_offset;
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_cccb_write_command_with_header() - Write a command + command header to a
-+ * Client CCB
-+ * @pvr_cccb: Target Client CCB.
-+ * @cmd_type: Client CCB command type. Must be one of %ROGUE_FWIF_CCB_CMD_TYPE_*.
-+ * @cmd_size: Size of command in bytes.
-+ * @cmd_data: Pointer to command to write.
-+ * @ext_job_ref: External job reference.
-+ * @int_job_ref: Internal job reference.
-+ *
-+ * Caller must have locked the Client CCB with pvr_cccb_lock().
-+ *
-+ * Returns:
-+ * * Zero on success, or
-+ * * -EAGAIN if insufficient space is currently available in the CCCB.
-+ */
-+int
-+pvr_cccb_write_command_with_header(struct pvr_cccb *pvr_cccb, u32 cmd_type, u32 cmd_size,
-+ void *cmd_data, u32 ext_job_ref, u32 int_job_ref)
-+{
-+ struct rogue_fwif_ccb_cmd_header cmd_header;
-+ u8 *cccb_ptr;
-+ u32 new_write_offset;
-+ const size_t size = sizeof(cmd_header) + cmd_size;
-+ int err;
-+
-+ lockdep_assert_held(&pvr_cccb->lock);
-+
-+ cmd_header.cmd_type = cmd_type;
-+ cmd_header.cmd_size = cmd_size;
-+ cmd_header.ext_job_ref = ext_job_ref;
-+ cmd_header.int_job_ref = int_job_ref;
-+
-+ err = pvr_cccb_acquire_command_space_locked(pvr_cccb, size, (void **)&cccb_ptr,
-+ &new_write_offset);
-+ if (err)
-+ return err;
-+
-+ memcpy(cccb_ptr, &cmd_header, sizeof(cmd_header));
-+ memcpy(cccb_ptr + sizeof(cmd_header), cmd_data, cmd_size);
-+ pvr_cccb->write_offset = new_write_offset;
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_cccb_wait_for_idle: Wait for Client CCB to go idle
-+ * @pvr_cccb: Client CCB to wait on.
-+ * @timeout: Timeout length (in jiffies).
-+ *
-+ * Returns:
-+ * * Zero on success, or
-+ * * -EBUSY on timeout.
-+ */
-+int
-+pvr_cccb_wait_for_idle(struct pvr_cccb *pvr_cccb, u32 timeout)
-+{
-+ struct rogue_fwif_cccb_ctl *ctrl = pvr_cccb->ctrl;
-+ unsigned long end_jiffies = jiffies + timeout;
-+
-+ while (!time_after(jiffies, end_jiffies)) {
-+ if (READ_ONCE(ctrl->read_offset) == READ_ONCE(ctrl->write_offset))
-+ return 0;
-+ usleep_range(100, 1000);
-+ }
-+
-+ return -EBUSY;
-+}
-+
-+/**
-+ * pvr_cccb_unlock_send_kccb_kick: Unlock Client CCB and send KCCB kick to
-+ * trigger command processing
-+ * @pvr_dev: Device pointer.
-+ * @pvr_cccb: Pointer to CCCB to process.
-+ * @cctx_fw_addr: FW virtual address for context owning this Client CCB.
-+ * @hwrt: HWRT data set associated with this kick. May be %NULL.
-+ *
-+ * Caller must have locked the Client CCB with pvr_cccb_lock().
-+ *
-+ * If this function is successful, then the Client CCB will be unlocked. On
-+ * error, the Client CCB will still be locked, and it is the callers
-+ * responsibility to unlock it with pvr_cccb_unlock_rollback().
-+ *
-+ * Return :
-+ * * Zero on success, or
-+ * * Any error returned by pvr_kccb_send_cmd().
-+ */
-+int
-+pvr_cccb_unlock_send_kccb_kick(struct pvr_device *pvr_dev,
-+ struct pvr_cccb *pvr_cccb, u32 cctx_fw_addr,
-+ struct pvr_hwrt_data *hwrt)
-+{
-+ struct rogue_fwif_kccb_cmd cmd_kick;
-+ struct rogue_fwif_kccb_cmd_kick_data *cmd_kick_data =
-+ &cmd_kick.cmd_data.cmd_kick_data;
-+ u32 *cleanup_ctl;
-+ int err;
-+
-+ lockdep_assert_held(&pvr_cccb->lock);
-+
-+ cmd_kick.cmd_type = ROGUE_FWIF_KCCB_CMD_KICK;
-+ cmd_kick_data->context_fw_addr = cctx_fw_addr;
-+ cmd_kick_data->client_woff_update = pvr_cccb->write_offset;
-+ cmd_kick_data->client_wrap_mask_update = pvr_cccb->wrap_mask;
-+
-+ cmd_kick_data->num_cleanup_ctl = 0;
-+ cleanup_ctl = cmd_kick_data->cleanup_ctl_fw_addr;
-+ if (hwrt) {
-+ WARN_ON(!pvr_gem_get_fw_addr_offset(hwrt->fw_obj,
-+ offsetof(struct rogue_fwif_hwrtdata, cleanup_state),
-+ cleanup_ctl));
-+ cmd_kick_data->num_cleanup_ctl++;
-+ cleanup_ctl++;
-+ }
-+ cmd_kick_data->work_est_cmd_header_offset = 0;
-+
-+ err = pvr_kccb_send_cmd(pvr_dev, &cmd_kick, NULL);
-+ if (err)
-+ goto err_out;
-+
-+ mutex_unlock(&pvr_cccb->lock);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_cccb.h b/drivers/gpu/drm/imagination/pvr_cccb.h
-new file mode 100644
-index 000000000000..7cf479ee75cb
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_cccb.h
-@@ -0,0 +1,103 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_CCCB_H__
-+#define __PVR_CCCB_H__
-+
-+#include "pvr_fence.h"
-+#include "pvr_rogue_fwif.h"
-+#include "pvr_rogue_fwif_shared.h"
-+
-+#include <linux/mutex.h>
-+#include <linux/types.h>
-+
-+/* Forward declaration from pvr_device.h. */
-+struct pvr_device;
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_fw_object;
-+
-+/* Forward declaration from pvr_hwrt.h. */
-+struct pvr_hwrt_data;
-+
-+struct pvr_cccb {
-+ /** @ctrl_obj: FW object representing CCCB control structure. */
-+ struct pvr_fw_object *ctrl_obj;
-+
-+ /** @ccb_obj: FW object representing CCCB. */
-+ struct pvr_fw_object *cccb_obj;
-+
-+ /** @lock: Mutex protecting @ctrl and @cccb. */
-+ struct mutex lock;
-+
-+ /**
-+ * @ctrl: Kernel mapping of CCCB control structure. @lock must be held
-+ * when accessing.
-+ */
-+ struct rogue_fwif_cccb_ctl *ctrl;
-+
-+ /** @cccb: Kernel mapping of CCCB. @lock must be held when accessing.*/
-+ u8 *cccb;
-+
-+ /** @ctrl_fw_addr: FW virtual address of CCCB control structure. */
-+ u32 ctrl_fw_addr;
-+ /** @ccb_fw_addr: FW virtual address of CCCB. */
-+ u32 cccb_fw_addr;
-+
-+ /** @size: Size of CCCB in bytes. */
-+ size_t size;
-+
-+ /** @write_offset: CCCB write offset. */
-+ u32 write_offset;
-+
-+ /** @wrap_mask: CCCB wrap mask. */
-+ u32 wrap_mask;
-+
-+ /** @old_write_offset: CCCB write offset, sampled at CCCB lock time. */
-+ u32 old_write_offset;
-+
-+ /** @pvr_fence_context: Fence context for data master represented by this CCCB. */
-+ struct pvr_fence_context pvr_fence_context;
-+};
-+
-+int pvr_cccb_init(struct pvr_device *pvr_dev, struct pvr_cccb *cccb,
-+ u32 size_log2, const char *name);
-+void pvr_cccb_fini(struct pvr_cccb *cccb);
-+
-+int pvr_cccb_write_command(struct pvr_cccb *pvr_cccb, void *cmd_data,
-+ size_t size);
-+int
-+pvr_cccb_write_command_with_header(struct pvr_cccb *pvr_cccb, u32 cmd_type, u32 cmd_size,
-+ void *cmd_data, u32 ext_job_ref, u32 int_job_ref);
-+int pvr_cccb_wait_for_idle(struct pvr_cccb *pvr_cccb, u32 timeout);
-+int pvr_cccb_unlock_send_kccb_kick(struct pvr_device *pvr_dev,
-+ struct pvr_cccb *pvr_cccb, u32 cctx_fw_addr,
-+ struct pvr_hwrt_data *hwrt);
-+
-+/**
-+ * pvr_cccb_lock() - Lock a client CCB for writing
-+ * @pvr_cccb: Target client CCB.
-+ */
-+static __always_inline void
-+pvr_cccb_lock(struct pvr_cccb *pvr_cccb)
-+{
-+ mutex_lock(&pvr_cccb->lock);
-+
-+ pvr_cccb->old_write_offset = pvr_cccb->write_offset;
-+}
-+
-+/**
-+ * pvr_cccb_unlock_rollback() - Unlock a client CCB and rollback any written
-+ * commands
-+ * @pvr_cccb: Target client CCB.
-+ */
-+static __always_inline void
-+pvr_cccb_unlock_rollback(struct pvr_cccb *pvr_cccb)
-+{
-+ lockdep_assert_held(&pvr_cccb->lock);
-+
-+ pvr_cccb->write_offset = pvr_cccb->old_write_offset;
-+ mutex_unlock(&pvr_cccb->lock);
-+}
-+
-+#endif /* __PVR_CCCB_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_context.c b/drivers/gpu/drm/imagination/pvr_context.c
-new file mode 100644
-index 000000000000..b316a05e551b
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_context.c
-@@ -0,0 +1,727 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_cccb.h"
-+#include "pvr_context.h"
-+#include "pvr_device.h"
-+#include "pvr_gem.h"
-+#include "pvr_object.h"
-+#include "pvr_rogue_fwif.h"
-+#include "pvr_rogue_fwif_common.h"
-+#include "pvr_rogue_fwif_resetframework.h"
-+
-+#include <drm/drm_auth.h>
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/types.h>
-+#include <linux/xarray.h>
-+
-+/* TODO: placeholder */
-+#define MAX_DEADLINE_MS 30000
-+
-+#define CTX_COMPUTE_CCCB_SIZE_LOG2 15
-+#define CTX_FRAG_CCCB_SIZE_LOG2 15
-+#define CTX_GEOM_CCCB_SIZE_LOG2 15
-+
-+static int
-+pvr_init_context_common(struct pvr_device *pvr_dev, struct pvr_file *pvr_file,
-+ struct pvr_context *ctx, int type,
-+ enum pvr_context_priority priority,
-+ struct drm_pvr_ioctl_create_context_args *args)
-+{
-+ struct rogue_fwif_rf_cmd *reset_framework;
-+ int err;
-+
-+ ctx->type = type;
-+ ctx->pvr_dev = pvr_dev;
-+ ctx->pvr_file = pvr_file;
-+
-+ ctx->flags = args->flags;
-+ ctx->priority = priority;
-+
-+ kref_init(&ctx->ref_count);
-+
-+ reset_framework = pvr_gem_create_and_map_fw_object(pvr_dev, ROGUE_FWIF_RF_CMD_SIZE,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &ctx->reset_framework_obj);
-+ if (IS_ERR(reset_framework)) {
-+ err = PTR_ERR(reset_framework);
-+ goto err_out;
-+ }
-+
-+ if (args->reset_framework_registers) {
-+ struct drm_pvr_reset_framework rf_args;
-+
-+ if (copy_from_user(&rf_args,
-+ u64_to_user_ptr(
-+ args->reset_framework_registers),
-+ sizeof(rf_args))) {
-+ err = -EFAULT;
-+ goto err_rf_free;
-+ }
-+
-+ if (rf_args.flags || rf_args.format != DRM_PVR_RF_FORMAT_CDM_1) {
-+ err = -EINVAL;
-+ goto err_rf_free;
-+ }
-+
-+ if (!PVR_IOCTL_UNION_PADDING_CHECK(&rf_args, data,
-+ cdm_format_1) ||
-+ !rf_args.data.cdm_format_1.cdm_ctrl_stream_base) {
-+ err = -EINVAL;
-+ goto err_rf_free;
-+ }
-+
-+ reset_framework->flags = ROGUE_FWIF_RF_FLAG_ENABLE;
-+ reset_framework->fw_registers.cdmreg_cdm_ctrl_stream_base =
-+ rf_args.data.cdm_format_1.cdm_ctrl_stream_base;
-+
-+ } else {
-+ reset_framework->flags = 0;
-+ }
-+
-+ pvr_fw_object_vunmap(ctx->reset_framework_obj, reset_framework, true);
-+
-+ return 0;
-+
-+err_rf_free:
-+ pvr_fw_object_release(ctx->reset_framework_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+pvr_fini_context_common(struct pvr_device *pvr_dev, struct pvr_context *ctx)
-+{
-+ pvr_fw_object_release(ctx->reset_framework_obj);
-+}
-+
-+/**
-+ * pvr_init_geom_context() - Initialise a geometry context
-+ * @ctx_render: Pointer to parent render context.
-+ * @render_ctx_args: Arguments from userspace.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_gem_create_and_map_fw_object().
-+ */
-+static int
-+pvr_init_geom_context(
-+ struct pvr_context_render *ctx_render,
-+ struct drm_pvr_ioctl_create_render_context_args *render_ctx_args)
-+{
-+ struct pvr_device *pvr_dev = ctx_render->base.pvr_dev;
-+ struct pvr_context_geom *ctx_geom = &ctx_render->ctx_geom;
-+ struct rogue_fwif_geom_ctx_state *geom_ctx_state_fw;
-+ int err;
-+
-+ ctx_geom->ctx_id = atomic_inc_return(&ctx_render->base.pvr_file->ctx_id);
-+
-+ err = pvr_cccb_init(pvr_dev, &ctx_geom->cccb, CTX_GEOM_CCCB_SIZE_LOG2, "geometry");
-+ if (err)
-+ goto err_out;
-+
-+ geom_ctx_state_fw = pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*geom_ctx_state_fw),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &ctx_geom->ctx_state_obj);
-+ if (IS_ERR(geom_ctx_state_fw)) {
-+ err = PTR_ERR(geom_ctx_state_fw);
-+ goto err_cccb_fini;
-+ }
-+
-+ geom_ctx_state_fw->geom_reg_vdm_call_stack_pointer =
-+ render_ctx_args->vdm_callstack_addr;
-+
-+ pvr_fw_object_vunmap(ctx_geom->ctx_state_obj, geom_ctx_state_fw, true);
-+
-+ return 0;
-+
-+err_cccb_fini:
-+ pvr_cccb_fini(&ctx_geom->cccb);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_fini_geom_context() - Clean up a geometry context
-+ * @ctx_render: Pointer to parent render context.
-+ */
-+static void
-+pvr_fini_geom_context(struct pvr_context_render *ctx_render)
-+{
-+ struct pvr_context_geom *ctx_geom = &ctx_render->ctx_geom;
-+
-+ pvr_fw_object_release(ctx_geom->ctx_state_obj);
-+
-+ pvr_cccb_fini(&ctx_geom->cccb);
-+}
-+
-+/**
-+ * pvr_init_frag_context() - Initialise a fragment context
-+ * @ctx_render: Pointer to parent render context.
-+ * @render_ctx_args: Arguments from userspace.
-+ *
-+ * Return:
-+ * * 0 on success.
-+ */
-+static int
-+pvr_init_frag_context(struct pvr_context_render *ctx_render,
-+ struct drm_pvr_ioctl_create_render_context_args *render_ctx_args)
-+{
-+ struct pvr_device *pvr_dev = ctx_render->base.pvr_dev;
-+ struct pvr_file *pvr_file = ctx_render->base.pvr_file;
-+ struct pvr_context_frag *ctx_frag = &ctx_render->ctx_frag;
-+ int err;
-+
-+ ctx_frag->ctx_id = atomic_inc_return(&pvr_file->ctx_id);
-+
-+ err = pvr_cccb_init(pvr_dev, &ctx_frag->cccb, CTX_FRAG_CCCB_SIZE_LOG2, "fragment");
-+ if (err)
-+ goto err_out;
-+
-+ err = pvr_gem_create_fw_object(pvr_dev, sizeof(struct rogue_fwif_frag_ctx_state),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED, &ctx_frag->ctx_state_obj);
-+ if (err)
-+ goto err_cccb_fini;
-+
-+ return 0;
-+
-+err_cccb_fini:
-+ pvr_cccb_fini(&ctx_frag->cccb);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_fini_frag_context() - Clean up a fragment context
-+ * @ctx_render: Pointer to parent render context.
-+ */
-+static void
-+pvr_fini_frag_context(struct pvr_context_render *ctx_render)
-+{
-+ struct pvr_context_frag *ctx_frag = &ctx_render->ctx_frag;
-+
-+ pvr_fw_object_release(ctx_frag->ctx_state_obj);
-+
-+ pvr_cccb_fini(&ctx_frag->cccb);
-+}
-+
-+static int
-+remap_priority(struct pvr_file *pvr_file, s32 uapi_priority, enum pvr_context_priority *priority_out)
-+{
-+ switch (uapi_priority) {
-+ case DRM_PVR_CTX_PRIORITY_LOW:
-+ *priority_out = PVR_CTX_PRIORITY_LOW;
-+ break;
-+ case DRM_PVR_CTX_PRIORITY_NORMAL:
-+ *priority_out = PVR_CTX_PRIORITY_MEDIUM;
-+ break;
-+ case DRM_PVR_CTX_PRIORITY_HIGH:
-+ if (!capable(CAP_SYS_NICE) && !drm_is_current_master(from_pvr_file(pvr_file)))
-+ return -EACCES;
-+ *priority_out = PVR_CTX_PRIORITY_HIGH;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_init_fw_common_context() - Initialise an FW-side common context structure
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @ctx: Pointer to context.
-+ * @cctx_fw: Pointer to FW common context structure.
-+ * @dm_type: Data master type.
-+ * @priority: Context priority.
-+ * @max_deadline_ms: Maximum deadline for work on this context.
-+ * @cctx_id: Common context ID.
-+ * @ctx_state_obj: FW object representing context state.
-+ * @cccb: Client CCB for this context.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_gem_get_fw_addr().
-+ */
-+static int
-+pvr_init_fw_common_context(struct pvr_file *pvr_file, struct pvr_context *ctx,
-+ struct rogue_fwif_fwcommoncontext *cctx_fw,
-+ u32 dm_type, u32 priority, u32 max_deadline_ms,
-+ u32 cctx_id, struct pvr_fw_object *ctx_state_obj,
-+ struct pvr_cccb *cccb)
-+{
-+ int err = 0;
-+
-+ cctx_fw->ccbctl_fw_addr = cccb->ctrl_fw_addr;
-+ cctx_fw->ccb_fw_addr = cccb->cccb_fw_addr;
-+
-+ cctx_fw->dm = dm_type;
-+ cctx_fw->priority = ctx->priority;
-+ cctx_fw->priority_seq_num = 0;
-+ cctx_fw->max_deadline_ms = max_deadline_ms;
-+ cctx_fw->pid = task_tgid_nr(current);
-+ cctx_fw->server_common_context_id = cctx_id;
-+
-+ if (ctx->reset_framework_obj) {
-+ if (!pvr_gem_get_fw_addr(ctx->reset_framework_obj,
-+ &cctx_fw->rf_cmd_addr)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+ }
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_file->fw_mem_ctx_obj, &cctx_fw->fw_mem_context_fw_addr));
-+
-+ if (!pvr_gem_get_fw_addr(ctx_state_obj, &cctx_fw->context_state_addr)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_init_fw_render_context() - Initialise an FW-side render context structure
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @ctx_render: Pointer to parent render context.
-+ * @args: Context creation arguments from userspace.
-+ * @render_ctx_args: Render context specific arguments from userspace.
-+ *
-+ * Return:
-+ * * 0 on success.
-+ */
-+static int
-+pvr_init_fw_render_context(
-+ struct pvr_file *pvr_file,
-+ struct pvr_context_render *ctx_render,
-+ struct drm_pvr_ioctl_create_context_args *args,
-+ struct drm_pvr_ioctl_create_render_context_args *render_ctx_args)
-+{
-+ struct rogue_fwif_geom_registers_caswitch *ctxswitch_regs;
-+ struct rogue_fwif_fwrendercontext *fw_render_context;
-+ struct drm_pvr_static_render_context_state srcs_args;
-+ int err;
-+
-+ fw_render_context = pvr_gem_create_and_map_fw_object(ctx_render->base.pvr_dev,
-+ sizeof(*fw_render_context), PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED, &ctx_render->fw_obj);
-+ if (IS_ERR(fw_render_context)) {
-+ err = PTR_ERR(fw_render_context);
-+ goto err_out;
-+ }
-+
-+ /* Copy static render context state from userspace. */
-+ if (copy_from_user(&srcs_args,
-+ u64_to_user_ptr(
-+ render_ctx_args->static_render_context_state),
-+ sizeof(srcs_args))) {
-+ err = -EFAULT;
-+ goto err_destroy_gem_object;
-+ }
-+
-+ if (srcs_args.format != DRM_PVR_SRCS_FORMAT_1 ||
-+ srcs_args._padding_4) {
-+ err = -EINVAL;
-+ goto err_destroy_gem_object;
-+ }
-+
-+ if (!PVR_IOCTL_UNION_PADDING_CHECK(&srcs_args, data, format_1)) {
-+ err = -EINVAL;
-+ goto err_destroy_gem_object;
-+ }
-+
-+ ctxswitch_regs =
-+ &fw_render_context->static_render_context_state.ctxswitch_regs;
-+
-+ BUILD_BUG_ON(sizeof(*ctxswitch_regs) != sizeof(srcs_args.data));
-+ memcpy(ctxswitch_regs, &srcs_args.data, sizeof(srcs_args.data));
-+
-+ err = pvr_init_fw_common_context(pvr_file, &ctx_render->base,
-+ &fw_render_context->geom_context,
-+ PVR_FWIF_DM_GEOM, args->priority,
-+ MAX_DEADLINE_MS,
-+ ctx_render->ctx_geom.ctx_id,
-+ ctx_render->ctx_geom.ctx_state_obj,
-+ &ctx_render->ctx_geom.cccb);
-+ if (err)
-+ goto err_destroy_gem_object;
-+
-+ err = pvr_init_fw_common_context(pvr_file, &ctx_render->base,
-+ &fw_render_context->frag_context,
-+ PVR_FWIF_DM_FRAG, args->priority,
-+ MAX_DEADLINE_MS,
-+ ctx_render->ctx_frag.ctx_id,
-+ ctx_render->ctx_frag.ctx_state_obj,
-+ &ctx_render->ctx_frag.cccb);
-+ if (err)
-+ goto err_destroy_gem_object;
-+
-+ pvr_fw_object_vunmap(ctx_render->fw_obj, fw_render_context, true);
-+ return 0;
-+
-+err_destroy_gem_object:
-+ pvr_fw_object_vunmap(ctx_render->fw_obj, fw_render_context, true);
-+ pvr_fw_object_release(ctx_render->fw_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_fini_fw_render_context() - Clean up an FW-side render context structure
-+ * @ctx_render: Pointer to parent render context.
-+ */
-+static void
-+pvr_fini_fw_render_context(struct pvr_context_render *ctx_render)
-+{
-+ pvr_fw_object_release(ctx_render->fw_obj);
-+}
-+
-+/**
-+ * pvr_init_compute_context() - Initialise a compute context structure
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @ctx_compute: Pointer to parent compute context.
-+ * @args: Context creation arguments from userspace.
-+ * @compute_ctx_args: Compute context specific arguments from userspace.
-+ *
-+ * Return:
-+ * * 0 on success.
-+ */
-+static int
-+pvr_init_compute_context(
-+ struct pvr_file *pvr_file,
-+ struct pvr_context_compute *ctx_compute,
-+ struct drm_pvr_ioctl_create_context_args *args,
-+ struct drm_pvr_ioctl_create_compute_context_args *compute_ctx_args)
-+{
-+ struct pvr_device *pvr_dev = pvr_file->pvr_dev;
-+ struct rogue_fwif_cdm_registers_cswitch *ctxswitch_regs;
-+ struct rogue_fwif_fwcomputecontext *fw_compute_context;
-+ struct drm_pvr_static_compute_context_state sccs_args;
-+ int err;
-+
-+ ctx_compute->ctx_id = atomic_inc_return(&pvr_file->ctx_id);
-+
-+ err = pvr_cccb_init(pvr_dev, &ctx_compute->cccb, CTX_COMPUTE_CCCB_SIZE_LOG2, "compute");
-+ if (err)
-+ goto err_out;
-+
-+ err = pvr_gem_create_fw_object(pvr_dev, sizeof(struct rogue_fwif_compute_ctx_state),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED, &ctx_compute->ctx_state_obj);
-+ if (err)
-+ goto err_cccb_fini;
-+
-+ fw_compute_context = pvr_gem_create_and_map_fw_object(ctx_compute->base.pvr_dev,
-+ sizeof(*fw_compute_context), PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED, &ctx_compute->fw_obj);
-+ if (IS_ERR(fw_compute_context)) {
-+ err = PTR_ERR(fw_compute_context);
-+ goto err_destroy_ctx_state_obj;
-+ }
-+
-+ /* Copy static render context state from userspace. */
-+ if (copy_from_user(&sccs_args,
-+ u64_to_user_ptr(compute_ctx_args->static_compute_context_state),
-+ sizeof(sccs_args))) {
-+ err = -EFAULT;
-+ goto err_destroy_gem_object;
-+ }
-+
-+ if (sccs_args.format != DRM_PVR_SCCS_FORMAT_1 || sccs_args._padding_4) {
-+ err = -EINVAL;
-+ goto err_destroy_gem_object;
-+ }
-+
-+ if (!PVR_IOCTL_UNION_PADDING_CHECK(&sccs_args, data, format_1)) {
-+ err = -EINVAL;
-+ goto err_destroy_gem_object;
-+ }
-+
-+ ctxswitch_regs =
-+ &fw_compute_context->static_compute_context_state.ctxswitch_regs;
-+
-+ BUILD_BUG_ON(sizeof(*ctxswitch_regs) != sizeof(sccs_args.data));
-+ memcpy(ctxswitch_regs, &sccs_args.data, sizeof(sccs_args.data));
-+
-+ err = pvr_init_fw_common_context(pvr_file, &ctx_compute->base,
-+ &fw_compute_context->cdm_context, PVR_FWIF_DM_CDM,
-+ args->priority, MAX_DEADLINE_MS,
-+ ctx_compute->ctx_id,
-+ ctx_compute->ctx_state_obj,
-+ &ctx_compute->cccb);
-+ if (err)
-+ goto err_destroy_gem_object;
-+
-+ pvr_fw_object_vunmap(ctx_compute->fw_obj, fw_compute_context, true);
-+ return 0;
-+
-+err_destroy_gem_object:
-+ pvr_fw_object_vunmap(ctx_compute->fw_obj, fw_compute_context, true);
-+ pvr_fw_object_release(ctx_compute->fw_obj);
-+
-+err_destroy_ctx_state_obj:
-+ pvr_fw_object_release(ctx_compute->ctx_state_obj);
-+
-+err_cccb_fini:
-+ pvr_cccb_fini(&ctx_compute->cccb);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_fini_compute_context() - Clean up a compute context structure
-+ * @ctx_compute: Pointer to compute context.
-+ */
-+static void
-+pvr_fini_compute_context(struct pvr_context_compute *ctx_compute)
-+{
-+ pvr_fw_object_release(ctx_compute->fw_obj);
-+ pvr_fw_object_release(ctx_compute->ctx_state_obj);
-+ pvr_cccb_fini(&ctx_compute->cccb);
-+}
-+
-+/**
-+ * pvr_create_render_context() - Create a combination geometry/fragment render
-+ * context and return a handle
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @args: Creation arguments from userspace.
-+ * @render_ctx_args: Render context creation args from userspace.
-+ * @handle_out: Output handle pointer.
-+ *
-+ * The context is initialised with refcount of 1.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%ENOMEM on out-of-memory, or
-+ * * Any error returned by xa_alloc().
-+ */
-+int
-+pvr_create_render_context(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_context_args *args,
-+ struct drm_pvr_ioctl_create_render_context_args *render_ctx_args,
-+ u32 *handle_out)
-+{
-+ struct pvr_device *pvr_dev = pvr_file->pvr_dev;
-+ struct pvr_context_render *ctx_render;
-+ enum pvr_context_priority priority;
-+ u32 handle;
-+ int err;
-+
-+ if (!render_ctx_args->static_render_context_state) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ err = remap_priority(pvr_file, args->priority, &priority);
-+ if (err)
-+ goto err_out;
-+
-+ ctx_render = kzalloc(sizeof(*ctx_render), GFP_KERNEL);
-+ if (!ctx_render) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ err = pvr_init_context_common(pvr_dev, pvr_file,
-+ from_pvr_context_render(ctx_render),
-+ DRM_PVR_CTX_TYPE_RENDER, priority, args);
-+ if (err < 0)
-+ goto err_free;
-+
-+ err = pvr_init_geom_context(ctx_render, render_ctx_args);
-+ if (err < 0)
-+ goto err_destroy_common_context;
-+
-+ err = pvr_init_frag_context(ctx_render, render_ctx_args);
-+ if (err < 0)
-+ goto err_destroy_geom_context;
-+
-+ err = pvr_init_fw_render_context(pvr_file, ctx_render, args, render_ctx_args);
-+ if (err < 0)
-+ goto err_destroy_frag_context;
-+
-+ /* Add to context list, and get handle */
-+ err = xa_alloc(&pvr_file->contexts, &handle,
-+ from_pvr_context_render(ctx_render), xa_limit_1_32b,
-+ GFP_KERNEL);
-+ if (err < 0)
-+ goto err_destroy_fw_render_context;
-+
-+ *handle_out = handle;
-+
-+ return 0;
-+
-+err_destroy_fw_render_context:
-+ pvr_fini_fw_render_context(ctx_render);
-+
-+err_destroy_frag_context:
-+ pvr_fini_frag_context(ctx_render);
-+
-+err_destroy_geom_context:
-+ pvr_fini_geom_context(ctx_render);
-+
-+err_destroy_common_context:
-+ pvr_fini_context_common(pvr_dev, from_pvr_context_render(ctx_render));
-+
-+err_free:
-+ kfree(ctx_render);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_create_compute_context() - Create a compute context and return a handle
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @args: Creation arguments from userspace.
-+ * @compute_ctx_args: Compute context creation args from userspace.
-+ * @handle_out: Output handle pointer.
-+ *
-+ * The context is initialised with refcount of 1.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%ENOMEM on out-of-memory, or
-+ * * Any error returned by xa_alloc().
-+ */
-+int
-+pvr_create_compute_context(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_context_args *args,
-+ struct drm_pvr_ioctl_create_compute_context_args *compute_ctx_args,
-+ u32 *handle_out)
-+{
-+ struct pvr_device *pvr_dev = pvr_file->pvr_dev;
-+ struct pvr_context_compute *ctx_compute;
-+ enum pvr_context_priority priority;
-+ u32 handle;
-+ int err;
-+
-+ if (!compute_ctx_args->static_compute_context_state) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ err = remap_priority(pvr_file, args->priority, &priority);
-+ if (err)
-+ goto err_out;
-+
-+ ctx_compute = kzalloc(sizeof(*ctx_compute), GFP_KERNEL);
-+ if (!ctx_compute) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ err = pvr_init_context_common(pvr_dev, pvr_file,
-+ from_pvr_context_compute(ctx_compute),
-+ DRM_PVR_CTX_TYPE_COMPUTE, priority, args);
-+ if (err < 0)
-+ goto err_free;
-+
-+ err = pvr_init_compute_context(pvr_file, ctx_compute, args, compute_ctx_args);
-+ if (err < 0)
-+ goto err_destroy_common_context;
-+
-+ /* Add to context list, and get handle */
-+ err = xa_alloc(&pvr_file->contexts, &handle,
-+ from_pvr_context_compute(ctx_compute), xa_limit_1_32b,
-+ GFP_KERNEL);
-+ if (err < 0)
-+ goto err_destroy_compute_context;
-+
-+ *handle_out = handle;
-+
-+ return 0;
-+
-+err_destroy_compute_context:
-+ pvr_fini_compute_context(ctx_compute);
-+
-+err_destroy_common_context:
-+ pvr_fini_context_common(pvr_dev, from_pvr_context_compute(ctx_compute));
-+
-+err_free:
-+ kfree(ctx_compute);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+pvr_release_context(struct kref *ref_count)
-+{
-+ struct pvr_context *ctx =
-+ container_of(ref_count, struct pvr_context, ref_count);
-+ struct pvr_device *pvr_dev = ctx->pvr_dev;
-+
-+ if (ctx->type == DRM_PVR_CTX_TYPE_RENDER) {
-+ struct pvr_context_render *ctx_render =
-+ to_pvr_context_render(ctx);
-+
-+ WARN_ON(pvr_object_cleanup(pvr_dev, ROGUE_FWIF_CLEANUP_FWCOMMONCONTEXT,
-+ ctx_render->fw_obj,
-+ offsetof(struct rogue_fwif_fwrendercontext,
-+ geom_context)));
-+ WARN_ON(pvr_object_cleanup(pvr_dev, ROGUE_FWIF_CLEANUP_FWCOMMONCONTEXT,
-+ ctx_render->fw_obj,
-+ offsetof(struct rogue_fwif_fwrendercontext,
-+ frag_context)));
-+
-+ pvr_fini_fw_render_context(ctx_render);
-+
-+ /* Destroy owned geometry & fragment contexts. */
-+ pvr_fini_frag_context(ctx_render);
-+ pvr_fini_geom_context(ctx_render);
-+ } else if (ctx->type == DRM_PVR_CTX_TYPE_COMPUTE) {
-+ struct pvr_context_compute *ctx_compute =
-+ to_pvr_context_compute(ctx);
-+
-+ pvr_fini_compute_context(ctx_compute);
-+ }
-+
-+ pvr_fini_context_common(ctx->pvr_dev, ctx);
-+
-+ kfree(ctx);
-+}
-+
-+/**
-+ * pvr_context_put() - Release reference on context
-+ * @ctx: Target context.
-+ */
-+void
-+pvr_context_put(struct pvr_context *ctx)
-+{
-+ kref_put(&ctx->ref_count, pvr_release_context);
-+}
-+
-+/**
-+ * pvr_context_destroy() - Destroy context
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @handle: Context handle.
-+ *
-+ * Removes context from context list and drops initial reference. Context will
-+ * then be destroyed once all outstanding references are dropped.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EINVAL if context not in context list.
-+ */
-+int
-+pvr_context_destroy(struct pvr_file *pvr_file, u32 handle)
-+{
-+ struct pvr_context *ctx = xa_erase(&pvr_file->contexts, handle);
-+
-+ if (!ctx)
-+ return -EINVAL;
-+
-+ pvr_context_put(ctx);
-+
-+ return 0;
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_context.h b/drivers/gpu/drm/imagination/pvr_context.h
-new file mode 100644
-index 000000000000..e94f2e8f655e
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_context.h
-@@ -0,0 +1,181 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_CONTEXT_H__
-+#define __PVR_CONTEXT_H__
-+
-+#include <linux/compiler_attributes.h>
-+#include <linux/kref.h>
-+#include <linux/types.h>
-+#include <linux/xarray.h>
-+#include <uapi/drm/pvr_drm.h>
-+
-+#include "pvr_cccb.h"
-+#include "pvr_device.h"
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_fw_object;
-+
-+/**
-+ * struct pvr_context_geom - Geometry render context data
-+ */
-+struct pvr_context_geom {
-+ /** @ctx_id: FW context ID. */
-+ u32 ctx_id;
-+
-+ /**
-+ * @ctx_state_obj: FW object representing context register state.
-+ */
-+ struct pvr_fw_object *ctx_state_obj;
-+
-+ /** @cccb: Client Circular Command Buffer. */
-+ struct pvr_cccb cccb;
-+};
-+
-+/**
-+ * struct pvr_context_frag - Fragment render context data
-+ */
-+struct pvr_context_frag {
-+ /** @ctx_id: FW context ID. */
-+ u32 ctx_id;
-+
-+ /**
-+ * @ctx_state_obj: FW object representing context register state.
-+ */
-+ struct pvr_fw_object *ctx_state_obj;
-+
-+ /** @cccb: Client Circular Command Buffer. */
-+ struct pvr_cccb cccb;
-+};
-+
-+enum pvr_context_priority {
-+ PVR_CTX_PRIORITY_LOW = 0,
-+ PVR_CTX_PRIORITY_MEDIUM,
-+ PVR_CTX_PRIORITY_HIGH,
-+};
-+
-+/**
-+ * struct pvr_context - Context data
-+ */
-+struct pvr_context {
-+ /** @ref_count: Refcount for context. */
-+ struct kref ref_count;
-+
-+ /** @pvr_dev: Pointer to owning device. */
-+ struct pvr_device *pvr_dev;
-+
-+ /** @pvr_file: Pointer to owning file. */
-+ struct pvr_file *pvr_file;
-+
-+ /** @type: Type of context. */
-+ enum drm_pvr_ctx_type type;
-+
-+ /** @flags: Context flags. */
-+ u32 flags;
-+
-+ /** @priority: Context priority*/
-+ enum pvr_context_priority priority;
-+
-+ /** @reset_framework_obj: FW object representing reset framework. */
-+ struct pvr_fw_object *reset_framework_obj;
-+};
-+
-+/**
-+ * struct pvr_context_render - Render context data
-+ */
-+struct pvr_context_render {
-+ /** @base: Base context structure. */
-+ struct pvr_context base;
-+
-+ /** @ctx_geom: Geometry context data. */
-+ struct pvr_context_geom ctx_geom;
-+
-+ /** @ctx_frag: Fragment context data. */
-+ struct pvr_context_frag ctx_frag;
-+
-+ /** @fw_obj: FW object representing FW-side context data. */
-+ struct pvr_fw_object *fw_obj;
-+};
-+
-+/**
-+ * struct pvr_context_compute - Compute context data
-+ */
-+struct pvr_context_compute {
-+ /** @base: Base context structure. */
-+ struct pvr_context base;
-+
-+ /** @fw_obj: FW object representing FW-side context data. */
-+ struct pvr_fw_object *fw_obj;
-+
-+ /** @ctx_id: Compute context ID. */
-+ u32 ctx_id;
-+
-+ /**
-+ * @ctx_state_obj: FW object representing context register state.
-+ */
-+ struct pvr_fw_object *ctx_state_obj;
-+
-+ /** @cccb: Client Circular Command Buffer. */
-+ struct pvr_cccb cccb;
-+};
-+
-+int pvr_create_render_context(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_context_args *args,
-+ struct drm_pvr_ioctl_create_render_context_args *render_ctx_args,
-+ u32 *handle_out);
-+int pvr_create_compute_context(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_context_args *args,
-+ struct drm_pvr_ioctl_create_compute_context_args *compute_ctx_args,
-+ u32 *handle_out);
-+
-+static __always_inline struct pvr_context *
-+from_pvr_context_render(struct pvr_context_render *ctx_render)
-+{
-+ return &ctx_render->base;
-+};
-+
-+static __always_inline struct pvr_context_render *
-+to_pvr_context_render(struct pvr_context *ctx)
-+{
-+ return container_of(ctx, struct pvr_context_render, base);
-+}
-+
-+static __always_inline struct pvr_context *
-+from_pvr_context_compute(struct pvr_context_compute *ctx_context)
-+{
-+ return &ctx_context->base;
-+};
-+
-+static __always_inline struct pvr_context_compute *
-+to_pvr_context_compute(struct pvr_context *ctx)
-+{
-+ return container_of(ctx, struct pvr_context_compute, base);
-+}
-+
-+/**
-+ * pvr_context_get() - Get context pointer from handle.
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @handle: Context handle.
-+ *
-+ * Takes reference on context. Call pvr_context_put() to release.
-+ *
-+ * Return:
-+ * * The requested context on success, or
-+ * * %NULL on failure.
-+ */
-+static __always_inline struct pvr_context *
-+pvr_context_get(struct pvr_file *pvr_file, u32 handle)
-+{
-+ struct pvr_context *ctx = xa_load(&pvr_file->contexts, handle);
-+
-+ if (ctx)
-+ kref_get(&ctx->ref_count);
-+
-+ return ctx;
-+}
-+
-+void pvr_context_put(struct pvr_context *ctx);
-+
-+int pvr_context_destroy(struct pvr_file *pvr_file, u32 handle);
-+
-+#endif /* __PVR_CONTEXT_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/imagination/pvr_device.c
-new file mode 100644
-index 000000000000..d0d63584b2aa
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_device.c
-@@ -0,0 +1,613 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_fw.h"
-+
-+#include "pvr_rogue_cr_defs.h"
-+
-+#include <drm/drm_print.h>
-+
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/compiler_attributes.h>
-+#include <linux/compiler_types.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/err.h>
-+#include <linux/firmware.h>
-+#include <linux/gfp.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/stddef.h>
-+#include <linux/types.h>
-+#include <linux/workqueue.h>
-+
-+/* Major and minor numbers for the supported version of the firmware. */
-+#define PVR_FW_VERSION_MAJOR 1
-+#define PVR_FW_VERSION_MINOR 14
-+
-+/**
-+ * pvr_device_reg_init() - Initialize kernel access to a PowerVR device's
-+ * control registers.
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Sets struct pvr_device->regs.
-+ *
-+ * This method of mapping the device control registers into memory ensures that
-+ * they are unmapped when the driver is detached (i.e. no explicit cleanup is
-+ * required).
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error returned by devm_platform_ioremap_resource().
-+ */
-+static int
-+pvr_device_reg_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct platform_device *plat_dev = to_platform_device(drm_dev->dev);
-+ struct resource *regs_resource;
-+ void __iomem *regs;
-+ int err;
-+
-+ pvr_dev->regs_resource = NULL;
-+ pvr_dev->regs = NULL;
-+
-+ regs = devm_platform_get_and_ioremap_resource(plat_dev, 0, ®s_resource);
-+ if (IS_ERR(regs)) {
-+ err = PTR_ERR(regs);
-+ drm_err(drm_dev, "failed to ioremap gpu registers (err=%d)\n",
-+ err);
-+ return err;
-+ }
-+
-+ pvr_dev->regs = regs;
-+ pvr_dev->regs_resource = regs_resource;
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_device_reg_fini() - Deinitialize kernel access to a PowerVR device's
-+ * control registers.
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This is essentially a no-op, since pvr_device_reg_init() already ensures that
-+ * struct pvr_device->regs is unmapped when the device is detached. This
-+ * function just sets struct pvr_device->regs to %NULL.
-+ */
-+static __always_inline void
-+pvr_device_reg_fini(struct pvr_device *pvr_dev)
-+{
-+ pvr_dev->regs = NULL;
-+}
-+
-+/**
-+ * pvr_device_clk_init() - Initialize clocks required by a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Sets struct pvr_device->core_clk, struct pvr_device->sys_clk and
-+ * struct pvr_device->mem_clk.
-+ *
-+ * Three clocks are required by the PowerVR device: core, sys and mem. On
-+ * return, this function guarantees that the clocks are in one of the following
-+ * states:
-+ *
-+ * * All successfully initialized,
-+ * * Core errored, sys and mem uninitialized,
-+ * * Core deinitialized, sys errored, mem uninitialized, or
-+ * * Core and sys deinitialized, mem errored.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * Any error returned by devm_clk_get(), or
-+ * * Any error returned by clk_prepare_enable().
-+ */
-+static int pvr_device_clk_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct clk *core_clk;
-+ struct clk *sys_clk;
-+ struct clk *mem_clk;
-+ int err;
-+
-+ pvr_dev->core_clk = NULL;
-+ pvr_dev->sys_clk = NULL;
-+ pvr_dev->mem_clk = NULL;
-+
-+ core_clk = devm_clk_get(drm_dev->dev, "core_clk");
-+ if (IS_ERR(core_clk)) {
-+ err = PTR_ERR(core_clk);
-+ drm_err(drm_dev, "failed to get core_clk (err=%d)\n", err);
-+ goto err_out;
-+ }
-+
-+ sys_clk = devm_clk_get(drm_dev->dev, "sys_clk");
-+ if (IS_ERR(sys_clk)) {
-+ err = PTR_ERR(sys_clk);
-+ drm_err(drm_dev, "failed to get sys_clk (err=%d)\n", err);
-+ goto err_out;
-+ }
-+
-+ mem_clk = devm_clk_get(drm_dev->dev, "mem_clk");
-+ if (IS_ERR(mem_clk)) {
-+ err = PTR_ERR(mem_clk);
-+ drm_err(drm_dev, "failed to get mem_clk (err=%d)\n", err);
-+ goto err_out;
-+ }
-+
-+ err = clk_prepare_enable(core_clk);
-+ if (err)
-+ goto err_out;
-+
-+ err = clk_prepare_enable(sys_clk);
-+ if (err)
-+ goto err_deinit_core_clk;
-+
-+ err = clk_prepare_enable(mem_clk);
-+ if (err)
-+ goto err_deinit_sys_clk;
-+
-+ pvr_dev->core_clk = core_clk;
-+ pvr_dev->sys_clk = sys_clk;
-+ pvr_dev->mem_clk = mem_clk;
-+
-+ return 0;
-+
-+err_deinit_sys_clk:
-+ clk_disable_unprepare(sys_clk);
-+err_deinit_core_clk:
-+ clk_disable_unprepare(core_clk);
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_device_clk_fini() - Deinitialize clocks required by a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+static void
-+pvr_device_clk_fini(struct pvr_device *pvr_dev)
-+{
-+ clk_disable_unprepare(pvr_dev->mem_clk);
-+ clk_disable_unprepare(pvr_dev->sys_clk);
-+ clk_disable_unprepare(pvr_dev->core_clk);
-+
-+ pvr_dev->core_clk = NULL;
-+ pvr_dev->sys_clk = NULL;
-+ pvr_dev->mem_clk = NULL;
-+}
-+
-+/**
-+ * pvr_device_clk_core_get_freq - Get current PowerVR device core clock frequency
-+ * @pvr_dev: Target PowerVR device.
-+ * @freq_out: Pointer to location to store core clock frequency in Hz.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%EINVAL if frequency can not be determined.
-+ */
-+int
-+pvr_device_clk_core_get_freq(struct pvr_device *pvr_dev, u32 *freq_out)
-+{
-+ u32 freq = clk_get_rate(pvr_dev->core_clk);
-+
-+ if (!freq)
-+ return -EINVAL;
-+
-+ *freq_out = freq;
-+ return 0;
-+}
-+
-+static irqreturn_t pvr_meta_irq_handler(int irq, void *data)
-+{
-+ struct pvr_device *pvr_dev = data;
-+ u32 irq_status;
-+
-+ irq_status = PVR_CR_READ32(pvr_dev, META_SP_MSLVIRQSTATUS);
-+
-+ if (!(irq_status & ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN))
-+ return IRQ_NONE; /* Spurious IRQ - ignore. */
-+
-+ /* Acknowledge IRQ. */
-+ PVR_CR_WRITE32(pvr_dev, META_SP_MSLVIRQSTATUS,
-+ ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK);
-+
-+ /* Only process IRQ work if FW is currently running. */
-+ if (pvr_dev->fw_booted) {
-+ queue_work(pvr_dev->irq_wq, &pvr_dev->fwccb_work);
-+ wake_up(&pvr_dev->kccb_rtn_q);
-+ queue_work(pvr_dev->irq_wq, &pvr_dev->fence_work);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+/**
-+ * pvr_device_irq_init() - Initialise IRQ required by a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Returns:
-+ * * 0 on success,
-+ * * Any error returned by platform_get_irq_byname(), or
-+ * * Any error returned by request_irq().
-+ */
-+static int
-+pvr_device_irq_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct platform_device *plat_dev = to_platform_device(drm_dev->dev);
-+ int err;
-+
-+ init_waitqueue_head(&pvr_dev->kccb_rtn_q);
-+
-+ pvr_dev->irq_wq = alloc_workqueue("powervr-irq", WQ_UNBOUND, 0);
-+ if (!pvr_dev->irq_wq) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ pvr_dev->irq = platform_get_irq_byname(plat_dev, "gpu");
-+ if (pvr_dev->irq < 0) {
-+ err = pvr_dev->irq;
-+ goto err_destroy_wq;
-+ }
-+
-+ err = request_irq(pvr_dev->irq, pvr_meta_irq_handler, IRQF_SHARED, NULL, pvr_dev);
-+ if (err)
-+ goto err_destroy_wq;
-+
-+ return 0;
-+
-+err_destroy_wq:
-+ destroy_workqueue(pvr_dev->irq_wq);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_device_irq_fini() - Deinitialise IRQ required by a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+static void
-+pvr_device_irq_fini(struct pvr_device *pvr_dev)
-+{
-+ free_irq(pvr_dev->irq, pvr_dev);
-+ destroy_workqueue(pvr_dev->irq_wq);
-+}
-+
-+/**
-+ * pvr_build_firmware_filename() - Construct a PowerVR firmware filename
-+ * @pvr_dev: Target PowerVR device.
-+ * @base: First part of the filename.
-+ * @major: Major version number.
-+ * @minor: Minor version number.
-+ *
-+ * A PowerVR firmware filename consists of three parts separated by underscores
-+ * (``'_'``) along with a '.fw' file suffix. The first part is the exact value
-+ * of @base, the second part is the hardware version string derived from @pvr_fw
-+ * and the final part is the firmware version number constructed from @major and
-+ * @minor with a 'v' prefix, e.g. powervr/rogue_4.40.2.51_v1.14.fw.
-+ *
-+ * The returned string will have been slab allocated and must be freed with
-+ * kfree().
-+ *
-+ * Return:
-+ * * The constructed filename on success, or
-+ * * Any error returned by kasprintf().
-+ */
-+static char *
-+pvr_build_firmware_filename(struct pvr_device *pvr_dev, const char *base,
-+ u8 major, u8 minor)
-+{
-+ struct pvr_version *version = &pvr_dev->version;
-+
-+ return kasprintf(GFP_KERNEL, "%s_%d.%d.%d.%d_v%d.%d.fw", base, version->b,
-+ version->v, version->n, version->c, major, minor);
-+}
-+
-+/**
-+ * pvr_request_firmware() - Load firmware for a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * See pvr_build_firmware_filename() for details on firmware file naming.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * Any error returned by pvr_build_firmware_filename(), or
-+ * * Any error returned by request_firmware().
-+ */
-+static int
-+pvr_request_firmware(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = &pvr_dev->base;
-+ char *filename;
-+ const struct firmware *fw;
-+ int err;
-+
-+ filename = pvr_build_firmware_filename(pvr_dev, "powervr/rogue",
-+ PVR_FW_VERSION_MAJOR,
-+ PVR_FW_VERSION_MINOR);
-+ if (IS_ERR(filename))
-+ return PTR_ERR(filename);
-+
-+ /*
-+ * This function takes a copy of &filename, meaning we can free our
-+ * instance before returning.
-+ */
-+ err = request_firmware(&fw, filename, pvr_dev->base.dev);
-+ if (err) {
-+ drm_err(drm_dev, "failed to load firmware %s (err=%d)\n",
-+ filename, err);
-+ goto err_free_filename;
-+ }
-+
-+ drm_info(drm_dev, "loaded firmware %s\n", filename);
-+ kfree(filename);
-+
-+ pvr_dev->fw = fw;
-+
-+ return 0;
-+
-+err_free_filename:
-+ kfree(filename);
-+
-+ return err;
-+}
-+
-+/**
-+ * pvr_load_hw_version() - Load a PowerVR device's hardware version (BVNC) from
-+ * control registers.
-+ *
-+ * Sets struct pvr_dev.version.
-+ *
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+static void
-+pvr_load_hw_version(struct pvr_device *pvr_dev)
-+{
-+ struct pvr_version *version = &pvr_dev->version;
-+ u64 bvnc;
-+
-+ /*
-+ * Try reading the BVNC using the newer (cleaner) method first. If the
-+ * B value is zero, fall back to the older method.
-+ */
-+ bvnc = PVR_CR_READ64(pvr_dev, CORE_ID__PBVNC);
-+
-+ version->b = PVR_CR_FIELD_GET(bvnc, CORE_ID__PBVNC__BRANCH_ID);
-+ if (version->b != 0) {
-+ version->v = PVR_CR_FIELD_GET(bvnc, CORE_ID__PBVNC__VERSION_ID);
-+ version->n = PVR_CR_FIELD_GET(
-+ bvnc, CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS);
-+ version->c = PVR_CR_FIELD_GET(bvnc, CORE_ID__PBVNC__CONFIG_ID);
-+ } else {
-+ u32 core_rev = PVR_CR_READ32(pvr_dev, CORE_REVISION);
-+ u32 core_id = PVR_CR_READ32(pvr_dev, CORE_ID);
-+ u16 core_id_config = PVR_CR_FIELD_GET(core_id, CORE_ID_CONFIG);
-+
-+ version->b = PVR_CR_FIELD_GET(core_rev, CORE_REVISION_MAJOR);
-+ version->v = PVR_CR_FIELD_GET(core_rev, CORE_REVISION_MINOR);
-+ version->n = FIELD_GET(0xFF00, core_id_config);
-+ version->c = FIELD_GET(0x00FF, core_id_config);
-+ }
-+}
-+
-+/**
-+ * pvr_set_dma_info() - Set PowerVR device DMA information
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Sets the DMA mask and max segment size for the PowerVR device.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * Any error returned by PVR_FEATURE_VALUE(), or
-+ * * Any error returned by dma_set_mask().
-+ */
-+
-+static int
-+pvr_set_dma_info(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ u16 phys_bus_width;
-+ int err;
-+
-+ err = PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width);
-+ if (err) {
-+ drm_err(drm_dev, "Failed to get device physical bus width\n");
-+ return err;
-+ }
-+
-+ /*
-+ * See the comment on &pvr_drm_driver.prime_fd_to_handle for an
-+ * explanation of the dma_set_mask function and dma_set_max_seg_size
-+ * calls below.
-+ */
-+ err = dma_set_mask(drm_dev->dev, DMA_BIT_MASK(phys_bus_width));
-+ if (err) {
-+ drm_err(drm_dev, "Failed to set DMA mask (err=%d)\n", err);
-+ return err;
-+ }
-+
-+ dma_set_max_seg_size(drm_dev->dev, UINT_MAX);
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_device_gpu_init() - GPU-specific initialization for a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * The following steps are taken to ensure the device is ready:
-+ *
-+ * 1. Read the hardware version information from control registers,
-+ * 2. Initialise the hardware feature information,
-+ * 3. Setup the device DMA information,
-+ * 4. Setup the device-scoped memory context, and
-+ * 5. Load firmware into the device.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%ENODEV if the GPU is not supported,
-+ * * Any error returned by pvr_set_dma_info(),
-+ * * Any error returned by pvr_memory_context_init(), or
-+ * * Any error returned by pvr_request_firmware().
-+ */
-+static int
-+pvr_device_gpu_init(struct pvr_device *pvr_dev)
-+{
-+ int err;
-+
-+ pvr_load_hw_version(pvr_dev);
-+
-+ err = pvr_device_info_init(pvr_dev);
-+ if (err)
-+ goto err_out;
-+
-+ if (PVR_HAS_FEATURE(pvr_dev, meta)) {
-+ pvr_dev->fw_processor_type = PVR_FW_PROCESSOR_TYPE_META;
-+ } else if (PVR_HAS_FEATURE(pvr_dev, mips)) {
-+ pvr_dev->fw_processor_type = PVR_FW_PROCESSOR_TYPE_MIPS;
-+ } else if (PVR_HAS_FEATURE(pvr_dev, riscv_fw_processor)) {
-+ pvr_dev->fw_processor_type = PVR_FW_PROCESSOR_TYPE_RISCV;
-+ } else {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ err = pvr_set_dma_info(pvr_dev);
-+ if (err)
-+ goto err_out;
-+
-+ pvr_dev->kernel_vm_ctx = pvr_vm_create_context(pvr_dev);
-+ if (IS_ERR(pvr_dev->kernel_vm_ctx)) {
-+ err = PTR_ERR(pvr_dev->kernel_vm_ctx);
-+ goto err_out;
-+ }
-+
-+ err = pvr_request_firmware(pvr_dev);
-+ if (err)
-+ goto err_vm_ctx_destroy;
-+
-+ err = pvr_fw_init(pvr_dev);
-+ if (err)
-+ goto err_release_firmware;
-+
-+ return 0;
-+
-+err_release_firmware:
-+ release_firmware(pvr_dev->fw);
-+
-+err_vm_ctx_destroy:
-+ pvr_vm_destroy_context(pvr_dev->kernel_vm_ctx, true);
-+ pvr_dev->kernel_vm_ctx = NULL;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_device_gpu_fini() - GPU-specific deinitialization for a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+static void
-+pvr_device_gpu_fini(struct pvr_device *pvr_dev)
-+{
-+ pvr_fw_fini(pvr_dev);
-+ release_firmware(pvr_dev->fw);
-+
-+ pvr_vm_destroy_context(pvr_dev->kernel_vm_ctx, true);
-+}
-+
-+/**
-+ * pvr_device_init() - Initialize a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * If this function returns successfully, the device will have been fully
-+ * initialized. Otherwise, any parts of the device initialized before an error
-+ * occurs will be de-initialized before returning.
-+ *
-+ * NOTE: The initialization steps currently taken are the bare minimum required
-+ * to read from the control registers. The device is unlikely to function
-+ * until further initialization steps are added. [This note should be
-+ * removed when that happens.]
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * Any error returned by pvr_device_reg_init(),
-+ * * Any error returned by pvr_device_clk_init(), or
-+ * * Any error returned by pvr_device_gpu_init().
-+ */
-+int
-+pvr_device_init(struct pvr_device *pvr_dev)
-+{
-+ int err;
-+
-+ /* Map the control registers into memory. */
-+ err = pvr_device_reg_init(pvr_dev);
-+ if (err)
-+ return err;
-+
-+ /* Enable and initialize clocks required for the device to operate. */
-+ err = pvr_device_clk_init(pvr_dev);
-+ if (err)
-+ goto err_device_reg_fini;
-+
-+ if (pvr_dev->vendor.callbacks &&
-+ pvr_dev->vendor.callbacks->power_enable) {
-+ err = pvr_dev->vendor.callbacks->power_enable(pvr_dev);
-+ if (err)
-+ goto err_device_clk_fini;
-+ }
-+
-+ err = pvr_device_irq_init(pvr_dev);
-+ if (err)
-+ goto err_vendor_power_disable;
-+
-+ /* Perform GPU-specific initialization steps. */
-+ err = pvr_device_gpu_init(pvr_dev);
-+ if (err)
-+ goto err_device_irq_fini;
-+
-+ return 0;
-+
-+err_device_irq_fini:
-+ pvr_device_irq_fini(pvr_dev);
-+
-+err_vendor_power_disable:
-+ if (pvr_dev->vendor.callbacks &&
-+ pvr_dev->vendor.callbacks->power_disable)
-+ pvr_dev->vendor.callbacks->power_disable(pvr_dev);
-+
-+err_device_clk_fini:
-+ pvr_device_clk_fini(pvr_dev);
-+
-+err_device_reg_fini:
-+ pvr_device_reg_fini(pvr_dev);
-+
-+ return err;
-+}
-+
-+/**
-+ * pvr_device_fini() - Deinitialize a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+void
-+pvr_device_fini(struct pvr_device *pvr_dev)
-+{
-+ /*
-+ * Deinitialization stages are performed in reverse order compared to
-+ * the initialization stages in pvr_device_init().
-+ */
-+ pvr_device_gpu_fini(pvr_dev);
-+ pvr_device_irq_fini(pvr_dev);
-+ if (pvr_dev->vendor.callbacks &&
-+ pvr_dev->vendor.callbacks->power_disable)
-+ pvr_dev->vendor.callbacks->power_disable(pvr_dev);
-+ pvr_device_clk_fini(pvr_dev);
-+ pvr_device_reg_fini(pvr_dev);
-+
-+ /* TODO: Remaining deinitialization steps */
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h
-new file mode 100644
-index 000000000000..216ff9ae6fcb
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_device.h
-@@ -0,0 +1,776 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_DEVICE_H__
-+#define __PVR_DEVICE_H__
-+
-+#include "pvr_ccb.h"
-+#include "pvr_device_info.h"
-+#include "pvr_fw_trace.h"
-+#include "pvr_vendor.h"
-+#include "pvr_vm.h"
-+
-+#include <drm/drm_device.h>
-+#include <drm/drm_file.h>
-+#include <drm/drm_mm.h>
-+
-+#include <linux/bits.h>
-+#include <linux/compiler_attributes.h>
-+#include <linux/compiler_types.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/math.h>
-+#include <linux/types.h>
-+#include <linux/wait.h>
-+#include <linux/workqueue.h>
-+#include <linux/xarray.h>
-+
-+/* Forward declaration from <linux/clk.h>. */
-+struct clk;
-+
-+/* Forward declaration from <linux/firmware.h>. */
-+struct firmware;
-+
-+/* Forward declaration from "pvr_fw.h". */
-+struct pvr_fw_funcs;
-+
-+/**
-+ * struct pvr_version - Hardware version information for a PowerVR device
-+ * @b: Branch ID.
-+ * @v: Version ID.
-+ * @n: Number of scalable units.
-+ * @c: Config ID.
-+ */
-+struct pvr_version {
-+ u16 b, v, n, c;
-+};
-+
-+/**
-+ * struct pvr_fw_version - Firmware version information
-+ * @major: Major version number.
-+ * @minor: Minor version number.
-+ */
-+struct pvr_fw_version {
-+ u16 major, minor;
-+};
-+
-+/**
-+ * struct pvr_vendor - Vendor specific data for @pvr_device.
-+ */
-+struct pvr_vendor {
-+ /**
-+ * @callbacks: Callback functions for vendor specific functionality.
-+ *
-+ * May be %NULL.
-+ */
-+ const struct pvr_vendor_callbacks *callbacks;
-+
-+ /** @data: Vendor specific data. */
-+ void *data;
-+};
-+
-+/**
-+ * struct pvr_device - powervr-specific wrapper for &struct drm_device
-+ */
-+struct pvr_device {
-+ /**
-+ * @base: The underlying &struct drm_device.
-+ *
-+ * Do not access this member directly, instead call
-+ * from_pvr_device().
-+ */
-+ struct drm_device base;
-+
-+ /** @version: Hardware version detected at runtime. */
-+ struct pvr_version version;
-+
-+ /**
-+ * @features: Hardware feature information.
-+ *
-+ * Do not access this member directly, instead use PVR_HAS_FEATURE()
-+ * or PVR_FEATURE_VALUE() macros.
-+ */
-+ struct pvr_device_features features;
-+
-+ /**
-+ * @quirks: Hardware quirk information.
-+ *
-+ * Do not access this member directly, instead use PVR_HAS_QUIRK().
-+ */
-+ struct pvr_device_quirks quirks;
-+
-+ /** @fw_version: Firmware version detected at runtime. */
-+ struct pvr_fw_version fw_version;
-+
-+ /** @regs_resource: Resource representing device control registers. */
-+ struct resource *regs_resource;
-+
-+ /**
-+ * @regs: Device control registers.
-+ *
-+ * These are mapped into memory when the device is initialized; that
-+ * location is where this pointer points.
-+ */
-+ void __iomem *regs;
-+
-+ /** @core_clk: General core clock. */
-+ struct clk *core_clk;
-+
-+ /** @sys_clk: System bus clock. */
-+ struct clk *sys_clk;
-+
-+ /** @mem_clk: Memory clock. */
-+ struct clk *mem_clk;
-+
-+ /** @irq: IRQ number. */
-+ int irq;
-+
-+ /** @irq_wq: Workqueue for actions triggered off the IRQ handler. */
-+ struct workqueue_struct *irq_wq;
-+
-+ /** @kccb_rtn_q: Waitqueue for KCCB command return waiters. */
-+ wait_queue_head_t kccb_rtn_q;
-+
-+ /** @fw: Handle to the firmware loaded into the device. */
-+ const struct firmware *fw;
-+
-+ /** @vendor: Vendor specific device data. */
-+ struct pvr_vendor vendor;
-+
-+ /** @kccb: Kernel CCB. */
-+ struct pvr_ccb kccb;
-+
-+ /** @fwccb: Firmware CCB. */
-+ struct pvr_ccb fwccb;
-+
-+ /** @fwccb_work: Work item for FWCCB processing. */
-+ struct work_struct fwccb_work;
-+
-+ /** @fence_work: Work item for fence processing. */
-+ struct work_struct fence_work;
-+
-+ /** @kccb_rtn_obj: Object representing KCCB return slots. */
-+ struct pvr_fw_object *kccb_rtn_obj;
-+
-+ /**
-+ * @kccb_rtn: Pointer to CPU mapping of KCCB return slots. Must be
-+ * accessed by READ_ONCE()/WRITE_ONCE().
-+ */
-+ u32 *kccb_rtn;
-+
-+ /** @kernel_vm_ctx: TODO */
-+ struct pvr_vm_context *kernel_vm_ctx;
-+
-+ /** @fw_mm: Firmware address space allocator. */
-+ struct drm_mm fw_mm;
-+
-+ /** @fw_mm_lock: Lock protecting access to &fw_mm. */
-+ spinlock_t fw_mm_lock;
-+
-+ /** @fw_mm_base: Base address of address space managed by @fw_mm. */
-+ u64 fw_mm_base;
-+
-+ /** @fw_code_obj: Object representing firmware code. */
-+ struct pvr_fw_object *fw_code_obj;
-+
-+ /** @fw_data_obj: Object representing firmware data. */
-+ struct pvr_fw_object *fw_data_obj;
-+
-+ /**
-+ * @fw_core_code_obj: Object representing firmware core code. May be
-+ * %NULL if firmware does not contain this section.
-+ */
-+ struct pvr_fw_object *fw_core_code_obj;
-+
-+ /**
-+ * @fw_core_data_obj: Object representing firmware core data. May be
-+ * %NULL if firmware does not contain this section.
-+ */
-+ struct pvr_fw_object *fw_core_data_obj;
-+
-+ /**
-+ * @fwif_connection_ctl_obj: Object representing FWIF connection control
-+ * structure.
-+ */
-+ struct pvr_fw_object *fwif_connection_ctl_obj;
-+
-+ /**
-+ * @fwif_connection_ctl: Pointer to CPU mapping of FWIF connection
-+ * control structure.
-+ */
-+ struct rogue_fwif_connection_ctl *fwif_connection_ctl;
-+
-+ /** @fw_osinit_obj: Object representing FW OSINIT structure. */
-+ struct pvr_fw_object *fw_osinit_obj;
-+
-+ /** @fw_osinit: Pointer to CPU mapping of FW OSINIT structure. */
-+ struct rogue_fwif_osinit *fw_osinit;
-+
-+ /** @fw_sysinit_obj: Object representing FW SYSINIT structure. */
-+ struct pvr_fw_object *fw_sysinit_obj;
-+
-+ /** @fw_sysinit: Pointer to CPU mapping of FW SYSINIT structure. */
-+ struct rogue_fwif_sysinit *fw_sysinit;
-+
-+ /** @fw_osdata_obj: Object representing FW OSDATA structure. */
-+ struct pvr_fw_object *fw_osdata_obj;
-+
-+ /** @fw_osdata: Pointer to CPU mapping of FW OSDATA structure. */
-+ struct rogue_fwif_osdata *fw_osdata;
-+
-+ /** @fw_hwrinfobuf_obj: Object representing FW hwrinfobuf structure. */
-+ struct pvr_fw_object *fw_hwrinfobuf_obj;
-+
-+ /** @fw_sysdata_obj: Object representing FW SYSDATA structure. */
-+ struct pvr_fw_object *fw_sysdata_obj;
-+
-+ /** @fw_fault_page_obj: Object representing FW fault page. */
-+ struct pvr_fw_object *fw_fault_page_obj;
-+
-+ /**
-+ * @fw_gpu_util_fwcb_obj: Object representing FW GPU utilisation control
-+ * structure.
-+ */
-+ struct pvr_fw_object *fw_gpu_util_fwcb_obj;
-+
-+ /**
-+ * @fw_runtime_cfg_obj: Object representing FW runtime config
-+ * structure.
-+ */
-+ struct pvr_fw_object *fw_runtime_cfg_obj;
-+
-+ /** @fw_mmucache_sync_obj: Object used as the sync parameter in an MMU cache operation. */
-+ struct pvr_fw_object *fw_mmucache_sync_obj;
-+
-+ /** @fw_booted: %true if the firmware has been booted, %false otherwise. */
-+ bool fw_booted;
-+
-+ /** @fw_trace: Device firmware trace buffer state. */
-+ struct pvr_fw_trace fw_trace;
-+
-+ /** @fence_list_spinlock: Lock protecting accesses to @fence_list. */
-+ spinlock_t fence_list_spinlock;
-+
-+ /** @fence_list: List of active fences. */
-+ struct list_head fence_list;
-+
-+ /**
-+ * @fw_processor_type: FW processor type for this device. Must be one of
-+ * %PVR_FW_PROCESSOR_TYPE_*.
-+ */
-+ u16 fw_processor_type;
-+
-+ /** @fw_funcs: Function table for the FW processor used by this device. */
-+ const struct pvr_fw_funcs *fw_funcs;
-+
-+ /** @fw_data: Pointer to data specific to FW processor. */
-+ union {
-+ /** @mips_data: Pointer to MIPS-specific data. */
-+ struct pvr_fw_mips_data *mips_data;
-+ } fw_data;
-+
-+ /** @fw_heap: Firmware heap information. */
-+ struct {
-+ /** @gpu_addr: Base address of firmware heap in GPU address space. */
-+ u64 gpu_addr;
-+
-+ /** @size: Size of main area of heap. */
-+ u32 size;
-+
-+ /** @offset_mask: Mask for offsets within FW heap. */
-+ u32 offset_mask;
-+
-+ /** @raw_size: Raw size of heap, including reserved areas. */
-+ u32 raw_size;
-+
-+ /** @log2_size: Log2 of raw size of heap. */
-+ u32 log2_size;
-+
-+ /** @config_offset: Offset of config area within heap. */
-+ u32 config_offset;
-+
-+ /** @reserved_size: Size of reserved area in heap. */
-+ u32 reserved_size;
-+ } fw_heap_info;
-+};
-+
-+/**
-+ * struct pvr_file - powervr-specific data to be assigned to &struct
-+ * drm_file.driver_priv
-+ */
-+struct pvr_file {
-+ /**
-+ * @file: A reference to the parent &struct drm_file.
-+ *
-+ * Do not access this member directly, instead call from_pvr_file().
-+ */
-+ struct drm_file *file;
-+
-+ /**
-+ * @pvr_dev: A reference to the powervr-specific wrapper for the
-+ * associated device. Saves on repeated calls to
-+ * to_pvr_device().
-+ */
-+ struct pvr_device *pvr_dev;
-+
-+ /**
-+ * @contexts: Array of contexts belonging to this file. Array members
-+ * are of type "struct pvr_context *".
-+ */
-+ struct xarray contexts;
-+
-+ /**
-+ * @objects: Array of objects belonging to this file. Array members
-+ * are of type "struct pvr_object *".
-+ */
-+ struct xarray objects;
-+
-+ /** @free_list_id: Next ID to be assigned when creating a free list. */
-+ atomic_t free_list_id;
-+
-+ /** @ctx_id: Next ID to be assigned when creating a context. */
-+ atomic_t ctx_id;
-+
-+ /** @user_vm_ctx: TODO */
-+ struct pvr_vm_context *user_vm_ctx;
-+
-+ /** @fw_mem_ctx_obj: Firmware object representing firmware memory context. */
-+ struct pvr_fw_object *fw_mem_ctx_obj;
-+};
-+
-+/**
-+ * PVR_HAS_FEATURE() - Tests whether a PowerVR device has a given feature
-+ * @pvr_dev: [IN] Target PowerVR device.
-+ * @feature: [IN] Hardware feature name.
-+ *
-+ * Feature names are derived from those found in &struct pvr_device_features by
-+ * dropping the 'has_' prefix, which is applied by this macro.
-+ *
-+ * Return:
-+ * * true if the named feature is present in the hardware
-+ * * false if the named feature is not present in the hardware
-+ */
-+#define PVR_HAS_FEATURE(pvr_dev, feature) ((pvr_dev)->features.has_##feature)
-+
-+/**
-+ * PVR_FEATURE_VALUE() - Gets a PowerVR device feature value
-+ * @pvr_dev: [IN] Target PowerVR device.
-+ * @feature: [IN] Feature name.
-+ * @value_out: [OUT] Feature value.
-+ *
-+ * This macro will get a feature value for those features that have values.
-+ *
-+ * Feature names are derived from those found in &struct pvr_device_features by
-+ * dropping the 'has_' prefix.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EINVAL if the named feature is not present in the hardware
-+ */
-+#define PVR_FEATURE_VALUE(pvr_dev, feature, value_out) \
-+ ({ \
-+ struct pvr_device *__pvr_dev = pvr_dev; \
-+ int __ret = -EINVAL; \
-+ if (__pvr_dev->features.has_##feature) { \
-+ *(value_out) = __pvr_dev->features.feature; \
-+ __ret = 0; \
-+ } \
-+ __ret; \
-+ })
-+
-+/**
-+ * PVR_HAS_QUIRK() - Tests whether a physical device has a given quirk
-+ * @pvr_dev: [IN] Target PowerVR device.
-+ * @quirk: [IN] Hardware quirk name.
-+ *
-+ * Quirk numbers are derived from those found in #pvr_device_quirks by
-+ * dropping the 'has_brn' prefix, which is applied by this macro.
-+ *
-+ * Returns
-+ * * true if the quirk is present in the hardware, or
-+ * * false if the quirk is not present in the hardware.
-+ */
-+#define PVR_HAS_QUIRK(pvr_dev, quirk) ((pvr_dev)->quirks.has_brn##quirk)
-+
-+static __always_inline struct drm_device *
-+from_pvr_device(struct pvr_device *pvr_dev)
-+{
-+ return &pvr_dev->base;
-+}
-+
-+static __always_inline struct pvr_device *
-+to_pvr_device(struct drm_device *drm_dev)
-+{
-+ return container_of(drm_dev, struct pvr_device, base);
-+}
-+
-+static __always_inline struct drm_file *
-+from_pvr_file(struct pvr_file *pvr_file)
-+{
-+ return pvr_file->file;
-+}
-+
-+static __always_inline struct pvr_file *
-+to_pvr_file(struct drm_file *file)
-+{
-+ return file->driver_priv;
-+}
-+
-+/**
-+ * PVR_PACKED_BVNC() - Packs B, V, N and C values into a 64-bit unsigned integer
-+ * @b: Branch ID.
-+ * @v: Version ID.
-+ * @n: Number of scalable units.
-+ * @c: Config ID.
-+ *
-+ * The packed layout is as follows:
-+ *
-+ * +--------+--------+--------+-------+
-+ * | 63..48 | 47..32 | 31..16 | 15..0 |
-+ * +========+========+========+=======+
-+ * | B | V | N | C |
-+ * +--------+--------+--------+-------+
-+ *
-+ * pvr_version_to_packed_bvnc() should be used instead of this macro when a
-+ * &struct pvr_version is available in order to ensure proper type checking.
-+ *
-+ * Return: Packed BVNC.
-+ */
-+/* clang-format off */
-+#define PVR_PACKED_BVNC(b, v, n, c) \
-+ ((((u64)(b) & GENMASK_ULL(15, 0)) << 48) | \
-+ (((u64)(v) & GENMASK_ULL(15, 0)) << 32) | \
-+ (((u64)(n) & GENMASK_ULL(15, 0)) << 16) | \
-+ (((u64)(c) & GENMASK_ULL(15, 0)) << 0))
-+/* clang-format on */
-+
-+/**
-+ * pvr_version_to_packed_bvnc() - Packs B, V, N and C values into a 64-bit
-+ * unsigned integer
-+ * @version: Version information.
-+ *
-+ * The packed layout is as follows:
-+ *
-+ * +--------+--------+--------+-------+
-+ * | 63..48 | 47..32 | 31..16 | 15..0 |
-+ * +========+========+========+=======+
-+ * | B | V | N | C |
-+ * +--------+--------+--------+-------+
-+ *
-+ * This should be used in preference to PVR_PACKED_BVNC() when a &struct
-+ * pvr_version is available in order to ensure proper type checking.
-+ *
-+ * Return: Packed BVNC.
-+ */
-+static __always_inline u64
-+pvr_version_to_packed_bvnc(struct pvr_version *version)
-+{
-+ return PVR_PACKED_BVNC(version->b, version->v, version->n, version->c);
-+}
-+
-+static __always_inline void
-+packed_bvnc_to_pvr_version(u64 bvnc, struct pvr_version *version)
-+{
-+ version->b = (bvnc & GENMASK_ULL(63, 48)) >> 48;
-+ version->v = (bvnc & GENMASK_ULL(47, 32)) >> 32;
-+ version->n = (bvnc & GENMASK_ULL(31, 16)) >> 16;
-+ version->c = bvnc & GENMASK_ULL(15, 0);
-+}
-+
-+int pvr_device_init(struct pvr_device *pvr_dev);
-+void pvr_device_fini(struct pvr_device *pvr_dev);
-+
-+int
-+pvr_device_clk_core_get_freq(struct pvr_device *pvr_dev, u32 *freq_out);
-+
-+/**
-+ * PVR_CR_READ32() - Read a 32-bit register from a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg: Target register.
-+ *
-+ * This macro is a wrapper around __pvr_cr_read32(). It applies ROGUE_CR_ prefix
-+ * to the provided @reg name, making it behave comparably to the
-+ * PVR_CR_FIELD_GET() macro.
-+ *
-+ * Return: The value of the requested register.
-+ */
-+#define PVR_CR_READ32(pvr_dev, reg) __pvr_cr_read32(pvr_dev, ROGUE_CR_##reg)
-+
-+/**
-+ * PVR_CR_READ64() - Read a 64-bit register from a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg: Target register.
-+ *
-+ * This macro is a wrapper around __pvr_cr_read64(). It applies ROGUE_CR_ prefix
-+ * to the provided @reg name, making it behave comparably to the
-+ * PVR_CR_FIELD_GET() macro.
-+ *
-+ * Return: The value of the requested register.
-+ */
-+#define PVR_CR_READ64(pvr_dev, reg) __pvr_cr_read64(pvr_dev, ROGUE_CR_##reg)
-+
-+/**
-+ * PVR_CR_WRITE32() - Write to a 32-bit register in a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg: Target register.
-+ * @val: Value to write.
-+ *
-+ * This macro is a wrapper around __pvr_cr_write32(). It applies ROGUE_CR_
-+ * prefix to the provided @reg name, making it behave comparably to the
-+ * PVR_CR_FIELD_GET() macro.
-+ */
-+#define PVR_CR_WRITE32(pvr_dev, reg, val) \
-+ __pvr_cr_write32(pvr_dev, ROGUE_CR_##reg, val)
-+
-+/**
-+ * PVR_CR_WRITE64() - Write to a 64-bit register in a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg: Target register.
-+ * @val: Value to write.
-+ *
-+ * This macro is a wrapper around __pvr_cr_write64(). It applies ROGUE_CR_
-+ * prefix to the provided @reg name, making it behave comparably to the
-+ * PVR_CR_FIELD_GET() macro.
-+ */
-+#define PVR_CR_WRITE64(pvr_dev, reg, val) \
-+ __pvr_cr_write64(pvr_dev, ROGUE_CR_##reg, val)
-+
-+/**
-+ * PVR_CR_FIELD_GET() - Extract a single field from a PowerVR control register
-+ * @val: Value of the target register.
-+ * @field: Field specifier, as defined in "pvr_rogue_cr_defs.h".
-+ *
-+ * Return: The extracted field.
-+ */
-+#define PVR_CR_FIELD_GET(val, field) FIELD_GET(~ROGUE_CR_##field##_CLRMSK, val)
-+
-+/**
-+ * __pvr_cr_read32() - Read a 32-bit register from a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg: Target register.
-+ *
-+ * Do not call this function directly; use the PVR_CR_READ32() macro instead.
-+ *
-+ * Return: The value of the requested register.
-+ */
-+static __always_inline u32
-+__pvr_cr_read32(struct pvr_device *pvr_dev, u32 reg)
-+{
-+ return ioread32(pvr_dev->regs + reg);
-+}
-+
-+/**
-+ * __pvr_cr_read64() - Read a 64-bit register from a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg: Target register.
-+ *
-+ * Do not call this function directly; use the PVR_CR_READ64() macro instead.
-+ *
-+ * Return: The value of the requested register.
-+ */
-+static __always_inline u64
-+__pvr_cr_read64(struct pvr_device *pvr_dev, u32 reg)
-+{
-+ return ioread64(pvr_dev->regs + reg);
-+}
-+
-+/**
-+ * __pvr_cr_write32() - Write to a 32-bit register in a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg: Target register.
-+ * @val: Value to write.
-+ *
-+ * Do not call this function directly; use the PVR_CR_WRITE32() macro instead.
-+ */
-+static __always_inline void
-+__pvr_cr_write32(struct pvr_device *pvr_dev, u32 reg, u32 val)
-+{
-+ iowrite32(val, pvr_dev->regs + reg);
-+}
-+
-+/**
-+ * __pvr_cr_write64() - Write to a 64-bit register in a PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg: Target register.
-+ * @val: Value to write.
-+ *
-+ * Do not call this function directly; use the PVR_CR_WRITE64() macro instead.
-+ */
-+static __always_inline void
-+__pvr_cr_write64(struct pvr_device *pvr_dev, u32 reg, u64 val)
-+{
-+ iowrite64(val, pvr_dev->regs + reg);
-+}
-+
-+/**
-+ * pvr_cr_poll_reg32() - Wait for a 32-bit register to match a given value by
-+ * polling
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg_addr: Address of register.
-+ * @reg_value: Expected register value (after masking).
-+ * @reg_mask: Mask of bits valid for comparison with @reg_value.
-+ * @timeout_usec: Timeout length, in us.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%ETIMEDOUT on timeout.
-+ */
-+static __always_inline int
-+pvr_cr_poll_reg32(struct pvr_device *pvr_dev, u32 reg_addr, u32 reg_value,
-+ u32 reg_mask, u64 timeout_usec)
-+{
-+ u32 value;
-+
-+ return readl_poll_timeout(pvr_dev->regs + reg_addr, value,
-+ (value & reg_mask) == reg_value, 0, timeout_usec);
-+}
-+
-+/**
-+ * pvr_cr_poll_reg64() - Wait for a 64-bit register to match a given value by
-+ * polling
-+ * @pvr_dev: Target PowerVR device.
-+ * @reg_addr: Address of register.
-+ * @reg_value: Expected register value (after masking).
-+ * @reg_mask: Mask of bits valid for comparison with @reg_value.
-+ * @timeout_usec: Timeout length, in us.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%ETIMEDOUT on timeout.
-+ */
-+static __always_inline int
-+pvr_cr_poll_reg64(struct pvr_device *pvr_dev, u32 reg_addr, u64 reg_value,
-+ u64 reg_mask, u64 timeout_usec)
-+{
-+ u64 value;
-+
-+ return readq_poll_timeout(pvr_dev->regs + reg_addr, value,
-+ (value & reg_mask) == reg_value, 0, timeout_usec);
-+}
-+
-+/**
-+ * pvr_round_up_to_cacheline_size() - Round up a provided size to be cacheline
-+ * aligned
-+ * @pvr_dev: Target PowerVR device.
-+ * @size: Initial size, in bytes.
-+ *
-+ * Returns:
-+ * * Size aligned to cacheline size.
-+ */
-+static __always_inline size_t
-+pvr_round_up_to_cacheline_size(struct pvr_device *pvr_dev, size_t size)
-+{
-+ u16 slc_cacheline_size_in_bits = 0;
-+ u16 slc_cacheline_size_in_bytes;
-+
-+ WARN_ON(!PVR_HAS_FEATURE(pvr_dev, slc_cache_line_size_in_bits));
-+ PVR_FEATURE_VALUE(pvr_dev, slc_cache_line_size_in_bits,
-+ &slc_cacheline_size_in_bits);
-+ slc_cacheline_size_in_bytes = slc_cacheline_size_in_bits / 8;
-+
-+ return round_up(size, slc_cacheline_size_in_bytes);
-+}
-+
-+/**
-+ * DOC: IOCTL validation helpers
-+ *
-+ * To validate the constraints imposed on IOCTL argument structs, a collection
-+ * of macros and helper functions exist in ``pvr_device.h``.
-+ *
-+ * Of the current helpers, it should only be necessary to call
-+ * PVR_IOCTL_UNION_PADDING_CHECK() directly. This macro should be used once in
-+ * every code path which extracts a union member from a struct passed from
-+ * userspace.
-+ */
-+
-+/**
-+ * pvr_ioctl_union_padding_check() - Validate that the implicit padding between
-+ * the end of a union member and the end of the union itself is zeroed.
-+ * @instance: Pointer to the instance of the struct to validate.
-+ * @union_offset: Offset into the type of @instance of the target union. Must
-+ * be 64-bit aligned.
-+ * @union_size: Size of the target union in the type of @instance. Must be
-+ * 64-bit aligned.
-+ * @member_size: Size of the target member in the target union specified by
-+ * @union_offset and @union_size. It is assumed that the offset of the target
-+ * member is zero relative to @union_offset. Must be 64-bit aligned.
-+ *
-+ * You probably want to use PVR_IOCTL_UNION_PADDING_CHECK() instead of calling
-+ * this function directly, since that macro abstracts away much of the setup,
-+ * and also provides some static validation. See its docs for details.
-+ *
-+ * Return:
-+ * * %true if every byte between the end of the used member of the union and
-+ * the end of that union is zeroed, or
-+ * * %false otherwise.
-+ */
-+static __always_inline bool
-+pvr_ioctl_union_padding_check(void *instance, size_t union_offset,
-+ size_t union_size, size_t member_size)
-+{
-+ /*
-+ * void pointer arithmetic is technically illegal - cast to a byte
-+ * pointer so this addition works safely.
-+ */
-+ void *padding_start = ((u8 *)instance) + union_offset + member_size;
-+ size_t padding_size = union_size - member_size;
-+
-+ return !memchr_inv(padding_start, 0, padding_size);
-+}
-+
-+/**
-+ * PVR_STATIC_ASSERT_64BIT_ALIGNED() - Inline assertion for 64-bit alignment.
-+ * @static_expr_: Target expression to evaluate.
-+ *
-+ * If @static_expr_ does not evaluate to a constant integer which would be a
-+ * 64-bit aligned address (i.e. a multiple of 8), compilation will fail.
-+ *
-+ * Return:
-+ * The value of @static_expr_.
-+ */
-+#define PVR_STATIC_ASSERT_64BIT_ALIGNED(static_expr_) \
-+ ({ \
-+ static_assert(((static_expr_) & (sizeof(u64) - 1)) == 0); \
-+ (static_expr_); \
-+ })
-+
-+/**
-+ * PVR_IOCTL_UNION_PADDING_CHECK() - Validate that the implicit padding between
-+ * the end of a union member and the end of the union itself is zeroed.
-+ * @struct_instance_: An expression which evaluates to a pointer to a UAPI data
-+ * struct.
-+ * @union_: The name of the union member of @struct_instance_ to check. If the
-+ * union member is nested within the type of @struct_instance_, this may
-+ * contain the member access operator (".").
-+ * @member_: The name of the member of @union_ to assess.
-+ *
-+ * This is a wrapper around pvr_ioctl_union_padding_check() which performs
-+ * alignment checks and simplifies things for the caller.
-+ *
-+ * Return:
-+ * * %true if every byte in @struct_instance_ between the end of @member_ and
-+ * the end of @union_ is zeroed, or
-+ * * %false otherwise.
-+ */
-+#define PVR_IOCTL_UNION_PADDING_CHECK(struct_instance_, union_, member_) \
-+ ({ \
-+ typeof(struct_instance_) __instance = (struct_instance_); \
-+ size_t __union_offset = PVR_STATIC_ASSERT_64BIT_ALIGNED( \
-+ offsetof(typeof(*__instance), union_)); \
-+ size_t __union_size = PVR_STATIC_ASSERT_64BIT_ALIGNED( \
-+ sizeof(__instance->union_)); \
-+ size_t __member_size = PVR_STATIC_ASSERT_64BIT_ALIGNED( \
-+ sizeof(__instance->union_.member_)); \
-+ pvr_ioctl_union_padding_check(__instance, __union_offset, \
-+ __union_size, __member_size); \
-+ })
-+
-+/** Reserve handle 0 as invalid for xarrays. */
-+#define xa_limit_1_32b XA_LIMIT(1, UINT_MAX)
-+
-+#define PVR_FW_PROCESSOR_TYPE_META 0
-+#define PVR_FW_PROCESSOR_TYPE_MIPS 1
-+#define PVR_FW_PROCESSOR_TYPE_RISCV 2
-+
-+#endif /* __PVR_DEVICE_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_device_info.c b/drivers/gpu/drm/imagination/pvr_device_info.c
-new file mode 100644
-index 000000000000..eb437dc7d346
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_device_info.c
-@@ -0,0 +1,108 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_device_info.h"
-+
-+#include <drm/drm_print.h>
-+
-+#include <linux/types.h>
-+
-+const struct pvr_device_features pvr_device_4_V_2_51 = {
-+ .has_meta = true,
-+ .has_meta_coremem_size = true,
-+ .has_num_clusters = true,
-+ .has_phys_bus_width = true,
-+ .has_slc_cache_line_size_in_bits = true,
-+ .has_virtual_address_space_bits = true,
-+
-+ .meta = true,
-+ .meta_coremem_size = 32,
-+ .num_clusters = 2,
-+ .phys_bus_width = 40,
-+ .slc_cache_line_size_in_bits = 512,
-+ .virtual_address_space_bits = 40,
-+};
-+
-+const struct pvr_device_quirks pvr_device_quirks_4_40_2_51 = {
-+ .has_brn63142 = true,
-+};
-+
-+const struct pvr_device_features pvr_device_33_V_11_3 = {
-+ .has_mips = true,
-+ .has_num_clusters = true,
-+ .has_phys_bus_width = true,
-+ .has_slc_cache_line_size_in_bits = true,
-+ .has_virtual_address_space_bits = true,
-+
-+ .mips = true,
-+ .num_clusters = 1,
-+ .phys_bus_width = 36,
-+ .slc_cache_line_size_in_bits = 512,
-+ .virtual_address_space_bits = 40,
-+};
-+
-+const struct pvr_device_quirks pvr_device_quirks_33_15_11_3 = {
-+};
-+
-+const struct pvr_device_features pvr_device_36_V_104_796 = {
-+ .has_num_clusters = true,
-+ .has_phys_bus_width = true,
-+ .has_riscv_fw_processor = true,
-+ .has_slc_cache_line_size_in_bits = true,
-+ .has_virtual_address_space_bits = true,
-+
-+ .num_clusters = 1,
-+ .phys_bus_width = 36,
-+ .riscv_fw_processor = true,
-+ .slc_cache_line_size_in_bits = 512,
-+ .virtual_address_space_bits = 40,
-+};
-+
-+const struct pvr_device_quirks pvr_device_quirks_36_53_104_796 = {
-+};
-+
-+/**
-+ * pvr_device_info_init() - Initialize a PowerVR device's hardware features and quirks
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This function relies on &pvr_dev.version having already been initialized. If
-+ * PowerVR device version is supported then sets &pvr_dev.features and &pvr_dev.quirks.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%ENODEV if the device is not supported.
-+ */
-+int
-+pvr_device_info_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct pvr_version *version = &pvr_dev->version;
-+ const u64 bvnc = pvr_version_to_packed_bvnc(version);
-+
-+ /*
-+ * This macro results in a "Macros with multiple statements should be
-+ * enclosed in a do - while loop" checkpatch error. However, following
-+ * this advice would make the macro look a bit odd and isn't necessary
-+ * in this particular case, as the macro has a very specific use and a
-+ * very limited lifetime. The error can therefore be ignored.
-+ */
-+#define CASE_PACKED_BVNC_DEVICE_INFO(b, v, n, c) \
-+ case PVR_PACKED_BVNC(b, v, n, c): \
-+ pvr_dev->features = pvr_device_##b##_V_##n##_##c; \
-+ pvr_dev->quirks = pvr_device_quirks_##b##_##v##_##n##_##c; \
-+ return 0
-+
-+ switch (bvnc) {
-+ CASE_PACKED_BVNC_DEVICE_INFO(4, 40, 2, 51);
-+ CASE_PACKED_BVNC_DEVICE_INFO(33, 15, 11, 3);
-+ CASE_PACKED_BVNC_DEVICE_INFO(36, 53, 104, 796);
-+ }
-+
-+#undef CASE_PACKED_BVNC_DEVICE_INFO
-+
-+ drm_warn(drm_dev, "Unsupported BVNC: %u.%u.%u.%u\n", version->b,
-+ version->v, version->n, version->c);
-+
-+ return -ENODEV;
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_device_info.h b/drivers/gpu/drm/imagination/pvr_device_info.h
-new file mode 100644
-index 000000000000..2bb571bd03c5
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_device_info.h
-@@ -0,0 +1,54 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_DEVICE_INFO_H__
-+#define __PVR_DEVICE_INFO_H__
-+
-+#include <linux/types.h>
-+
-+struct pvr_device;
-+
-+/**
-+ * struct pvr_device_features - Hardware feature information
-+ */
-+struct pvr_device_features {
-+ bool has_meta : 1;
-+ bool has_meta_coremem_size : 1;
-+ bool has_mips : 1;
-+ bool has_num_clusters : 1;
-+ bool has_phys_bus_width : 1;
-+ bool has_riscv_fw_processor : 1;
-+ bool has_slc_cache_line_size_in_bits : 1;
-+ bool has_virtual_address_space_bits : 1;
-+
-+ bool meta;
-+ u32 meta_coremem_size;
-+ bool mips;
-+ u16 num_clusters;
-+ u16 phys_bus_width;
-+ bool riscv_fw_processor;
-+ u16 slc_cache_line_size_in_bits;
-+ u16 virtual_address_space_bits;
-+};
-+
-+/**
-+ * struct pvr_device_quirks - Hardware quirk information
-+ */
-+struct pvr_device_quirks {
-+ bool has_brn63142 : 1;
-+};
-+
-+int pvr_device_info_init(struct pvr_device *pvr_dev);
-+
-+/*
-+ * Meta cores
-+ *
-+ * These are the values for the 'meta' feature when the feature is present
-+ * (as per @pvr_device_features)/
-+ */
-+#define PVR_META_MTP218 (1)
-+#define PVR_META_MTP219 (2)
-+#define PVR_META_LTP218 (3)
-+#define PVR_META_LTP217 (4)
-+
-+#endif /* __PVR_DEVICE_INFO_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c
-new file mode 100644
-index 000000000000..cca639fc1aa6
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_drv.c
-@@ -0,0 +1,885 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_context.h"
-+#include "pvr_device.h"
-+#include "pvr_drv.h"
-+#include "pvr_gem.h"
-+#include "pvr_job.h"
-+#include "pvr_object.h"
-+#include "pvr_rogue_fwif_shared.h"
-+#include "pvr_fw_trace.h"
-+
-+#include <uapi/drm/pvr_drm.h>
-+
-+#include <drm/drm_device.h>
-+#include <drm/drm_drv.h>
-+#include <drm/drm_file.h>
-+#include <drm/drm_ioctl.h>
-+
-+#include <linux/err.h>
-+#include <linux/export.h>
-+#include <linux/fs.h>
-+#include <linux/limits.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/of_device.h>
-+#include <linux/of_platform.h>
-+#include <linux/overflow.h>
-+#include <linux/platform_device.h>
-+#include <linux/xarray.h>
-+
-+/**
-+ * DOC: PowerVR Graphics Driver
-+ *
-+ * This driver supports the following PowerVR graphics cores from Imagination
-+ * Technologies:
-+ *
-+ * * GX6250 (found in MediaTek MT8173)
-+ */
-+
-+bool pvr_fw_trace_enable;
-+module_param(pvr_fw_trace_enable, bool, 0);
-+MODULE_PARM_DESC(pvr_fw_trace_enable, "Enable FW trace at module startup");
-+
-+/**
-+ * pvr_ioctl_create_bo() - IOCTL to create a GEM buffer object.
-+ * @drm_dev: [IN] Target DRM device.
-+ * @raw_args: [IN/OUT] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_create_bo_args.
-+ * @file: [IN] DRM file-private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_CREATE_BO.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if the value of &drm_pvr_ioctl_create_bo_args.size is zero
-+ * or wider than &typedef size_t,
-+ * * -%EINVAL if any bits in &drm_pvr_ioctl_create_bo_args.flags that are
-+ * reserved or undefined are set,
-+ * * -%EINVAL if any padding fields in &drm_pvr_ioctl_create_bo_args are not
-+ * zero,
-+ * * Any error encountered while creating the object (see
-+ * pvr_gem_object_create()), or
-+ * * Any error encountered while transferring ownership of the object into a
-+ * userspace-accessible handle (see pvr_gem_object_into_handle()).
-+ */
-+int
-+pvr_ioctl_create_bo(struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_create_bo_args *args = raw_args;
-+ struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
-+ struct pvr_file *pvr_file = to_pvr_file(file);
-+
-+ struct pvr_gem_object *pvr_obj;
-+ size_t sanitized_size;
-+ size_t real_size;
-+
-+ int err;
-+
-+ /* All padding fields must be zeroed. */
-+ if (args->_padding_c != 0)
-+ return -EINVAL;
-+
-+ /*
-+ * On 64-bit platforms (our primary target), size_t is a u64. However,
-+ * on other architectures we have to check for overflow when casting
-+ * down to size_t from u64.
-+ *
-+ * We also disallow zero-sized allocations, and reserved (kernel-only)
-+ * flags.
-+ */
-+ if (args->size > SIZE_MAX || args->size == 0 ||
-+ args->flags & PVR_BO_RESERVED_MASK) {
-+ return -EINVAL;
-+ }
-+
-+ sanitized_size = (size_t)args->size;
-+
-+ /*
-+ * Create a buffer object and transfer ownership to a userspace-
-+ * accessible handle.
-+ */
-+ pvr_obj = pvr_gem_object_create(pvr_dev, sanitized_size, args->flags);
-+ if (IS_ERR(pvr_obj)) {
-+ err = PTR_ERR(pvr_obj);
-+ goto err_out;
-+ }
-+
-+ /*
-+ * Store the actual size of the created buffer object. We can't fetch
-+ * this after this point because we will no longer have a reference to
-+ * &pvr_obj.
-+ */
-+ real_size = pvr_gem_object_size(pvr_obj);
-+
-+ /* This function will not modify &args->handle unless it succeeds. */
-+ err = pvr_gem_object_into_handle(pvr_obj, pvr_file, &args->handle);
-+ if (err)
-+ goto err_destroy_obj;
-+
-+ /*
-+ * Now write the real size back to the args struct, after no further
-+ * errors can occur.
-+ */
-+ args->size = real_size;
-+
-+ return 0;
-+
-+err_destroy_obj:
-+ /*
-+ * GEM objects are refcounted, so there is no explicit destructor
-+ * function. Instead, we release the singular reference we currently
-+ * hold on the object and let GEM take care of the rest.
-+ */
-+ pvr_gem_object_put(pvr_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_ioctl_get_bo_mmap_offset() - IOCTL to generate a "fake" offset to be
-+ * used when calling mmap() from userspace to map the given GEM buffer object
-+ * @drm_dev: [IN] DRM device (unused).
-+ * @raw_args: [IN/OUT] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_get_bo_mmap_offset_args.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_GET_BO_MMAP_OFFSET.
-+ *
-+ * This IOCTL does *not* perform an mmap. See the docs on
-+ * &struct drm_pvr_ioctl_get_bo_mmap_offset_args for details.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%ENOENT if the handle does not reference a valid GEM buffer object,
-+ * * -%EINVAL if any padding fields in &struct
-+ * drm_pvr_ioctl_get_bo_mmap_offset_args are not zero, or
-+ * * Any error returned by drm_gem_create_mmap_offset().
-+ */
-+int
-+pvr_ioctl_get_bo_mmap_offset(__always_unused struct drm_device *drm_dev,
-+ void *raw_args, struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_get_bo_mmap_offset_args *args = raw_args;
-+ struct pvr_file *pvr_file = to_pvr_file(file);
-+
-+ struct pvr_gem_object *pvr_obj;
-+ struct drm_gem_object *gem_obj;
-+ int ret;
-+
-+ /* All padding fields must be zeroed. */
-+ if (args->_padding_4 != 0)
-+ return -EINVAL;
-+
-+ /*
-+ * Obtain a kernel reference to the buffer object. This reference is
-+ * counted and must be manually dropped before returning. If a buffer
-+ * object cannot be found for the specified handle, return -%ENOENT (No
-+ * such file or directory).
-+ */
-+ pvr_obj = pvr_gem_object_from_handle(pvr_file, args->handle);
-+ if (!pvr_obj)
-+ return -ENOENT;
-+
-+ gem_obj = from_pvr_gem_object(pvr_obj);
-+
-+ /*
-+ * Allocate a fake offset which can be used in userspace calls to mmap
-+ * on the DRM device file. If this fails, return the error code. This
-+ * operation is idempotent.
-+ */
-+ ret = drm_gem_create_mmap_offset(gem_obj);
-+ if (ret != 0) {
-+ /* Drop our reference to the buffer object. */
-+ drm_gem_object_put(gem_obj);
-+ return ret;
-+ }
-+
-+ /*
-+ * Read out the fake offset allocated by the earlier call to
-+ * drm_gem_create_mmap_offset.
-+ */
-+ args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node);
-+
-+ /* Drop our reference to the buffer object. */
-+ pvr_gem_object_put(pvr_obj);
-+
-+ return 0;
-+}
-+
-+static __always_inline u64
-+pvr_fw_version_packed(u32 major, u32 minor)
-+{
-+ return ((u64)major << 32) | minor;
-+}
-+
-+/**
-+ * pvr_ioctl_get_param() - IOCTL to get information about a device
-+ * @drm_dev: [IN] DRM device.
-+ * @raw_args: [IN/OUT] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_get_param_args.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_GET_PARAM.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if the value of &struct drm_pvr_ioctl_get_param_args.param is
-+ * not one of those in &enum drm_pvr_param or is %DRM_PVR_PARAM_INVALID, or
-+ * * -%EINVAL if any padding fields in &struct drm_pvr_ioctl_get_param_args
-+ * are not zero.
-+ */
-+int
-+pvr_ioctl_get_param(struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
-+ struct drm_pvr_ioctl_get_param_args *args = raw_args;
-+ u64 value;
-+
-+ /* All padding fields must be zeroed. */
-+ if (args->_padding_4 != 0)
-+ return -EINVAL;
-+
-+ switch (args->param) {
-+ case DRM_PVR_PARAM_GPU_ID:
-+ value = pvr_version_to_packed_bvnc(&pvr_dev->version);
-+ break;
-+ case DRM_PVR_PARAM_HWRT_NUM_GEOMDATAS:
-+ value = ROGUE_FWIF_NUM_GEOMDATAS;
-+ break;
-+ case DRM_PVR_PARAM_HWRT_NUM_RTDATAS:
-+ value = ROGUE_FWIF_NUM_RTDATAS;
-+ break;
-+ case DRM_PVR_PARAM_HWRT_NUM_FREELISTS:
-+ value = ROGUE_FWIF_NUM_RTDATA_FREELISTS;
-+ break;
-+ case DRM_PVR_PARAM_FW_VERSION:
-+ value = pvr_fw_version_packed(pvr_dev->fw_version.major, pvr_dev->fw_version.minor);
-+ break;
-+ case DRM_PVR_PARAM_INVALID:
-+ case DRM_PVR_PARAM_MAX:
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ args->value = value;
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_ioctl_create_context() - IOCTL to create a context
-+ * @drm_dev: [IN] DRM device.
-+ * @raw_args: [IN/OUT] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_create_context_args.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_CREATE_CONTEXT.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EINVAL if provided arguments are invalid, or
-+ * * -%EFAULT if arguments can't be copied from userspace, or
-+ * * Any error returned by pvr_create_render_context().
-+ */
-+int
-+pvr_ioctl_create_context(struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_create_context_args *args = raw_args;
-+ struct pvr_file *pvr_file = file->driver_priv;
-+ u32 handle;
-+ int err;
-+
-+ if (args->flags || !args->data) {
-+ /* Context creation flags are currently unused and must be zero. */
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ switch (args->type) {
-+ case DRM_PVR_CTX_TYPE_RENDER: {
-+ struct drm_pvr_ioctl_create_render_context_args render_ctx_args;
-+
-+ if (copy_from_user(&render_ctx_args, u64_to_user_ptr(args->data),
-+ sizeof(render_ctx_args))) {
-+ err = -EFAULT;
-+ goto err_out;
-+ }
-+
-+ err = pvr_create_render_context(pvr_file, args, &render_ctx_args, &handle);
-+ break;
-+ }
-+
-+ case DRM_PVR_CTX_TYPE_COMPUTE: {
-+ struct drm_pvr_ioctl_create_compute_context_args compute_ctx_args;
-+
-+ if (copy_from_user(&compute_ctx_args, u64_to_user_ptr(args->data),
-+ sizeof(compute_ctx_args))) {
-+ err = -EFAULT;
-+ goto err_out;
-+ }
-+
-+ err = pvr_create_compute_context(pvr_file, args, &compute_ctx_args, &handle);
-+ break;
-+ }
-+
-+
-+ default:
-+ err = -EINVAL;
-+ break;
-+ }
-+
-+ if (err < 0)
-+ goto err_out;
-+
-+ args->handle = handle;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_ioctl_destroy_context() - IOCTL to destroy a context
-+ * @drm_dev: [IN] DRM device.
-+ * @raw_args: [IN/OUT] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_destroy_context_args.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_DESTROY_CONTEXT.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EINVAL if context not in context list.
-+ */
-+int
-+pvr_ioctl_destroy_context(struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_destroy_context_args *args = raw_args;
-+ struct pvr_file *pvr_file = file->driver_priv;
-+
-+ return pvr_context_destroy(pvr_file, args->handle);
-+}
-+
-+/**
-+ * pvr_ioctl_create_object() - IOCTL to create an object
-+ * @drm_dev: [IN] DRM device.
-+ * @raw_args: [IN/OUT] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_create_object_args.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_CREATE_OBJECT.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_object_create().
-+ */
-+int
-+pvr_ioctl_create_object(struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_create_object_args *args = raw_args;
-+ struct pvr_file *pvr_file = to_pvr_file(file);
-+ u32 handle;
-+ int err;
-+
-+ err = pvr_object_create(pvr_file, args, &handle);
-+ if (!err)
-+ args->handle = handle;
-+
-+ return err;
-+}
-+
-+/**
-+ * pvr_ioctl_destroy_object() - IOCTL to destroy an object
-+ * @drm_dev: [IN] DRM device.
-+ * @raw_args: [IN] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_destroy_object_args.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_DESTROY_OBJECT.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EINVAL if object not in object list.
-+ */
-+int
-+pvr_ioctl_destroy_object(struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_destroy_object_args *args = raw_args;
-+ struct pvr_file *pvr_file = to_pvr_file(file);
-+
-+ return pvr_object_destroy(pvr_file, args->handle);
-+}
-+
-+/**
-+ * pvr_ioctl_get_heap_info() - IOCTL to get information on device heaps
-+ * @drm_dev: [IN] DRM device.
-+ * @raw_args: [IN] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_get_heap_info.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_GET_HEAP_INFO.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EFAULT on failure to write to user buffer.
-+ */
-+int
-+pvr_ioctl_get_heap_info(struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_get_heap_info_args *args = raw_args;
-+
-+ return pvr_get_heap_info(to_pvr_device(drm_dev), args);
-+}
-+
-+/**
-+ * pvr_ioctl_vm_op_map() - Sub-operation of pvr_ioctl_vm_op().
-+ * @pvr_file: PowerVR file private data.
-+ * @args: The operation-specific part of the calling ioctl args.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_VM_OP when the
-+ * &drm_pvr_ioctl_vm_op_args.operation field is set to %DRM_PVR_VM_OP_MAP.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if &drm_pvr_ioctl_vm_op_map_args.flags is not zero,
-+ * * -%EINVAL if the bounds specified by &drm_pvr_ioctl_vm_op_map_args.offset
-+ * and &drm_pvr_ioctl_vm_op_map_args.size are not valid or do not fall
-+ * within the buffer object specified by
-+ * &drm_pvr_ioctl_vm_op_map_args.handle,
-+ * * -%EINVAL if the bounds specified by
-+ * &drm_pvr_ioctl_vm_op_map_args.device_addr and
-+ * &drm_pvr_ioctl_vm_op_map_args.size do not form a valid device-virtual
-+ * address range which falls entirely within a single heap, or
-+ * * -%ENOENT if &drm_pvr_ioctl_vm_op_map_args.handle does not refer to a
-+ * valid PowerVR buffer object.
-+ */
-+static int
-+pvr_ioctl_vm_op_map(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_vm_op_map_args *args)
-+{
-+ struct pvr_device *pvr_dev = pvr_file->pvr_dev;
-+ struct pvr_vm_context *vm_ctx = pvr_file->user_vm_ctx;
-+
-+ struct pvr_gem_object *pvr_obj;
-+ size_t pvr_obj_size;
-+
-+ u64 offset_plus_size;
-+ int err;
-+
-+ /* Initial validation of args. */
-+ if (args->flags != 0 ||
-+ check_add_overflow(args->offset, args->size, &offset_plus_size) ||
-+ !pvr_find_heap_containing(pvr_dev, args->device_addr, args->size)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ pvr_obj = pvr_gem_object_from_handle(pvr_file, args->handle);
-+ if (!pvr_obj) {
-+ err = -ENOENT;
-+ goto err_out;
-+ }
-+
-+ pvr_obj_size = pvr_gem_object_size(pvr_obj);
-+
-+ /*
-+ * Validate offset and size args. The alignment of these will be
-+ * checked when mapping; for now just check that they're within valid
-+ * bounds
-+ */
-+ if (args->offset >= pvr_obj_size || offset_plus_size > pvr_obj_size) {
-+ err = -EINVAL;
-+ goto err_put_pvr_object;
-+ }
-+
-+ /*
-+ * If the caller has specified that the entire object should be mapped,
-+ * use the more efficient pvr_vm_map().
-+ */
-+ if (args->offset == 0 && args->size == pvr_obj_size) {
-+ err = pvr_vm_map(vm_ctx, pvr_obj, args->device_addr);
-+ } else {
-+ err = pvr_vm_map_partial(vm_ctx, pvr_obj, args->offset,
-+ args->device_addr, args->size);
-+ }
-+ if (err)
-+ goto err_put_pvr_object;
-+
-+ /*
-+ * In order to set up the mapping, we needed a reference to &pvr_obj.
-+ * However, pvr_vm_map() obtains and stores its own reference, so we
-+ * must release ours before returning.
-+ */
-+ err = 0;
-+ goto err_put_pvr_object;
-+
-+err_put_pvr_object:
-+ pvr_gem_object_put(pvr_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_ioctl_vm_op_unmap() - Sub-operation of pvr_ioctl_vm_op().
-+ * @pvr_file: PowerVR file private data.
-+ * @args: The operation-specific part of the calling ioctl args.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_VM_OP when the
-+ * &drm_pvr_ioctl_vm_op_args.operation field is set to %DRM_PVR_VM_OP_UNMAP.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if &drm_pvr_ioctl_vm_op_unmap_args.device_addr is not a valid
-+ * device page-aligned device-virtual address, or
-+ * * -%ENOENT if there is currently no PowerVR buffer object mapped at
-+ * &drm_pvr_ioctl_vm_op_unmap_args.device_addr.
-+ */
-+static int
-+pvr_ioctl_vm_op_unmap(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_vm_op_unmap_args *args)
-+{
-+ return pvr_vm_unmap(pvr_file->user_vm_ctx, args->device_addr);
-+}
-+
-+/**
-+ * pvr_ioctl_vm_op() - IOCTL to perform a virtual memory operation.
-+ * @drm_dev: [IN] Target DRM device.
-+ * @raw_args: [IN] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_vm_op_args.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_VM_OP.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if any padding fields in &drm_pvr_ioctl_vm_op_args are not zero
-+ * (including implicit padding in unions), or
-+ * * Any error encountered while processing the selected pvr_ioctl_vm_op_*()
-+ * function corresponding to &drm_pvr_ioctl_vm_op_args.operation.
-+ */
-+int
-+pvr_ioctl_vm_op(__always_unused struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_vm_op_args *args = raw_args;
-+ struct pvr_file *pvr_file = to_pvr_file(file);
-+
-+ /* All padding fields must be zeroed. */
-+ if (args->_padding_4 != 0)
-+ return -EINVAL;
-+
-+ /*
-+ * We delegate most of the data.* member validation to individual
-+ * operation handlers. However, since the implicit union padding
-+ * falls outside these members, we must check that ourselves.
-+ */
-+ switch (args->operation) {
-+ case DRM_PVR_VM_OP_MAP:
-+ if (!PVR_IOCTL_UNION_PADDING_CHECK(args, data, map))
-+ return -EINVAL;
-+
-+ return pvr_ioctl_vm_op_map(pvr_file, &args->data.map);
-+
-+ case DRM_PVR_VM_OP_UNMAP:
-+ if (!PVR_IOCTL_UNION_PADDING_CHECK(args, data, unmap))
-+ return -EINVAL;
-+
-+ return pvr_ioctl_vm_op_unmap(pvr_file, &args->data.unmap);
-+
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+/*
-+ * pvr_ioctl_submit_job() - IOCTL to submit a job to the GPU
-+ * @drm_dev: [IN] DRM device.
-+ * @raw_args: [IN] Arguments passed to this IOCTL. This must be of type
-+ * &struct drm_pvr_ioctl_submit_job_args.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Called from userspace with %DRM_IOCTL_PVR_SUBMIT_JOB.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EINVAL if arguments are invalid.
-+ */
-+int
-+pvr_ioctl_submit_job(struct drm_device *drm_dev, void *raw_args,
-+ struct drm_file *file)
-+{
-+ struct drm_pvr_ioctl_submit_job_args *args = raw_args;
-+ struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
-+ struct pvr_file *pvr_file = to_pvr_file(file);
-+
-+ return pvr_submit_job(pvr_dev, pvr_file, args);
-+}
-+
-+#define DRM_PVR_IOCTL(_name, _func, _flags) \
-+ DRM_IOCTL_DEF_DRV(PVR_##_name, pvr_ioctl_##_func, _flags)
-+
-+/* clang-format off */
-+
-+static const struct drm_ioctl_desc pvr_drm_driver_ioctls[] = {
-+ DRM_PVR_IOCTL(CREATE_BO, create_bo, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(GET_BO_MMAP_OFFSET, get_bo_mmap_offset, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(GET_PARAM, get_param, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(CREATE_CONTEXT, create_context, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(DESTROY_CONTEXT, destroy_context, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(CREATE_OBJECT, create_object, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(DESTROY_OBJECT, destroy_object, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(GET_HEAP_INFO, get_heap_info, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(VM_OP, vm_op, DRM_RENDER_ALLOW),
-+ DRM_PVR_IOCTL(SUBMIT_JOB, submit_job, DRM_RENDER_ALLOW),
-+};
-+
-+/* clang-format on */
-+
-+#undef DRM_PVR_IOCTL
-+
-+/**
-+ * pvr_drm_driver_open() - Driver callback when a new &struct drm_file is opened
-+ * @drm_dev: [IN] DRM device.
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Allocates powervr-specific file private data (&struct pvr_file).
-+ *
-+ * Registered in &pvr_drm_driver.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%ENOMEM if the allocation of a &struct ipvr_file fails, or
-+ * * Any error returned by pvr_memory_context_init().
-+ */
-+static int
-+pvr_drm_driver_open(struct drm_device *drm_dev, struct drm_file *file)
-+{
-+ struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
-+ struct pvr_file *pvr_file;
-+
-+ int err;
-+
-+ pvr_file = kzalloc(sizeof(*pvr_file), GFP_KERNEL);
-+ if (!pvr_file) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ /*
-+ * Store reference to base DRM file private data for use by
-+ * from_pvr_file.
-+ */
-+ pvr_file->file = file;
-+
-+ /*
-+ * Store reference to powervr-specific outer device struct in file
-+ * private data for convenient access.
-+ */
-+ pvr_file->pvr_dev = pvr_dev;
-+
-+ xa_init_flags(&pvr_file->contexts, XA_FLAGS_ALLOC);
-+ xa_init_flags(&pvr_file->objects, XA_FLAGS_ALLOC);
-+
-+ /* Initialize the file-scoped memory context. */
-+ pvr_file->user_vm_ctx = pvr_vm_create_context(pvr_dev);
-+ if (IS_ERR(pvr_file->user_vm_ctx)) {
-+ err = PTR_ERR(pvr_file->user_vm_ctx);
-+ goto err_xa_destroy;
-+ }
-+
-+ err = pvr_vm_fw_mem_context_create(pvr_file);
-+ if (err)
-+ goto err_vm_ctx_destroy;
-+
-+ /*
-+ * Store reference to powervr-specific file private data in DRM file
-+ * private data.
-+ */
-+ file->driver_priv = pvr_file;
-+
-+ return 0;
-+
-+err_vm_ctx_destroy:
-+ pvr_vm_destroy_context(pvr_file->user_vm_ctx, false);
-+
-+err_xa_destroy:
-+ xa_destroy(&pvr_file->contexts);
-+ xa_destroy(&pvr_file->objects);
-+
-+ kfree(pvr_file);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_drm_driver_postclose() - One of the driver callbacks when a &struct
-+ * drm_file is closed.
-+ * @drm_dev: [IN] DRM device (unused).
-+ * @file: [IN] DRM file private data.
-+ *
-+ * Frees powervr-specific file private data (&struct pvr_file).
-+ *
-+ * Registered in &pvr_drm_driver.
-+ */
-+static void
-+pvr_drm_driver_postclose(__always_unused struct drm_device *drm_dev,
-+ struct drm_file *file)
-+{
-+ struct pvr_file *pvr_file = to_pvr_file(file);
-+ struct pvr_context *ctx;
-+ struct pvr_object *obj;
-+ unsigned long id;
-+
-+ pvr_vm_fw_mem_context_destroy(pvr_file);
-+ pvr_vm_destroy_context(pvr_file->user_vm_ctx, false);
-+
-+ /* clang-format off */
-+ /* Drop references on any remaining objects. */
-+ xa_for_each(&pvr_file->objects, id, obj) {
-+ pvr_object_put(obj);
-+ }
-+
-+ /* Drop references on any remaining contexts. */
-+ xa_for_each(&pvr_file->contexts, id, ctx) {
-+ pvr_context_put(ctx);
-+ }
-+ /* clang-format on */
-+
-+ xa_destroy(&pvr_file->contexts);
-+
-+ kfree(pvr_file);
-+ file->driver_priv = NULL;
-+}
-+
-+DEFINE_DRM_GEM_FOPS(pvr_drm_driver_fops);
-+
-+static struct drm_driver pvr_drm_driver = {
-+ .driver_features = DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ,
-+ .open = pvr_drm_driver_open,
-+ .postclose = pvr_drm_driver_postclose,
-+ .ioctls = pvr_drm_driver_ioctls,
-+ .num_ioctls = ARRAY_SIZE(pvr_drm_driver_ioctls),
-+ .fops = &pvr_drm_driver_fops,
-+#if defined(CONFIG_DEBUG_FS)
-+ .debugfs_init = pvr_fw_trace_debugfs_init,
-+#endif
-+
-+ .name = PVR_DRIVER_NAME,
-+ .desc = PVR_DRIVER_DESC,
-+ .date = PVR_DRIVER_DATE,
-+ .major = PVR_DRIVER_MAJOR,
-+ .minor = PVR_DRIVER_MINOR,
-+ .patchlevel = PVR_DRIVER_PATCHLEVEL,
-+
-+ /*
-+ * These three (four) helper functions implement PRIME buffer sharing
-+ * for us. The last is set implicitly when not assigned here. The only
-+ * additional requirement to make PRIME work is to call dma_set_mask()
-+ * in pvr_probe() to tell DMA that we can read from more than the first
-+ * 4GB (32 bits) of memory address space. The subsequent call to
-+ * dma_set_max_seg_size() is not strictly required, but prevents some
-+ * warnings from appearing when CONFIG_DMA_API_DEBUG_SG is enabled.
-+ */
-+ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
-+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
-+ .gem_prime_import_sg_table = __pvr_gem_prime_import_sg_table,
-+ /* .gem_prime_import = drm_gem_prime_import, */
-+};
-+
-+static int
-+pvr_probe(struct platform_device *plat_dev)
-+{
-+ struct pvr_device *pvr_dev;
-+ struct drm_device *drm_dev;
-+ int err;
-+
-+ pvr_dev = devm_drm_dev_alloc(&plat_dev->dev, &pvr_drm_driver,
-+ struct pvr_device, base);
-+ if (IS_ERR(pvr_dev)) {
-+ err = IS_ERR(pvr_dev);
-+ goto err_out;
-+ }
-+ drm_dev = &pvr_dev->base;
-+
-+ platform_set_drvdata(plat_dev, drm_dev);
-+
-+ pvr_fence_device_init(pvr_dev);
-+
-+ pvr_dev->vendor.callbacks = of_device_get_match_data(&plat_dev->dev);
-+
-+ if (pvr_dev->vendor.callbacks && pvr_dev->vendor.callbacks->init) {
-+ err = pvr_dev->vendor.callbacks->init(pvr_dev);
-+ if (err)
-+ goto err_out;
-+ }
-+
-+ err = pvr_device_init(pvr_dev);
-+ if (err)
-+ goto err_vendor_fini;
-+
-+ err = drm_dev_register(drm_dev, 0);
-+ if (err)
-+ goto err_device_fini;
-+
-+ return 0;
-+
-+err_device_fini:
-+ pvr_device_fini(pvr_dev);
-+
-+err_vendor_fini:
-+ if (pvr_dev->vendor.callbacks && pvr_dev->vendor.callbacks->fini)
-+ pvr_dev->vendor.callbacks->fini(pvr_dev);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_remove(struct platform_device *plat_dev)
-+{
-+ struct drm_device *drm_dev = platform_get_drvdata(plat_dev);
-+ struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
-+
-+ drm_dev_unregister(drm_dev);
-+ pvr_device_fini(pvr_dev);
-+ if (pvr_dev->vendor.callbacks && pvr_dev->vendor.callbacks->fini)
-+ pvr_dev->vendor.callbacks->fini(pvr_dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id dt_match[] = {
-+ { .compatible = "mediatek,mt8173-gpu", .data = &pvr_mt8173_callbacks },
-+ { .compatible = "img,powervr-series6xt", .data = NULL },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, dt_match);
-+
-+static struct platform_driver pvr_driver = {
-+ .probe = pvr_probe,
-+ .remove = pvr_remove,
-+ .driver = {
-+ .name = PVR_DRIVER_NAME,
-+ .of_match_table = dt_match,
-+ },
-+};
-+module_platform_driver(pvr_driver);
-+
-+MODULE_AUTHOR("Imagination Technologies Ltd.");
-+MODULE_DESCRIPTION(PVR_DRIVER_DESC);
-+MODULE_LICENSE("Dual MIT/GPL");
-+MODULE_IMPORT_NS(DMA_BUF);
-diff --git a/drivers/gpu/drm/imagination/pvr_drv.h b/drivers/gpu/drm/imagination/pvr_drv.h
-new file mode 100644
-index 000000000000..89630b82aaca
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_drv.h
-@@ -0,0 +1,19 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_DRV_H__
-+#define __PVR_DRV_H__
-+
-+#define PVR_DRIVER_NAME "powervr"
-+#define PVR_DRIVER_DESC "Imagination PowerVR Graphics"
-+#define PVR_DRIVER_DATE "20220211"
-+
-+/*
-+ * Driver interface version:
-+ * - 1.0: Initial interface
-+ */
-+#define PVR_DRIVER_MAJOR 1
-+#define PVR_DRIVER_MINOR 0
-+#define PVR_DRIVER_PATCHLEVEL 0
-+
-+#endif /* __PVR_DRV_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_fence.c b/drivers/gpu/drm/imagination/pvr_fence.c
-new file mode 100644
-index 000000000000..d1f5acaa70d1
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fence.c
-@@ -0,0 +1,250 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_drv.h"
-+#include "pvr_fence.h"
-+#include "pvr_gem.h"
-+#include "pvr_rogue_fwif.h"
-+
-+#include <linux/errno.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+
-+/**
-+ * pvr_fence_create() - Create a PowerVR fence
-+ * @context: Target PowerVR fence context
-+ *
-+ * The fence will be created with two references; one for the caller, one for the fence worker. The
-+ * callers reference (and any other references subsequently taken) should be released with
-+ * dma_fence_put(). If the fence will not be signaled (e.g. on an error path) then the fence worker
-+ * reference should also be manually dropped.
-+ *
-+ * Returns:
-+ * * 0 on success,
-+ * * -%ENOMEM on out of memory, or
-+ * * Any error returned by pvr_gem_create_and_map_fw_object().
-+ */
-+struct dma_fence *
-+pvr_fence_create(struct pvr_fence_context *context)
-+{
-+ struct pvr_device *pvr_dev = context->pvr_dev;
-+ struct pvr_fence *pvr_fence;
-+ unsigned long flags;
-+ int err;
-+
-+ pvr_fence = kmalloc(sizeof(*pvr_fence), GFP_KERNEL);
-+ if (!pvr_fence) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ pvr_fence->context = context;
-+ pvr_fence->sync_checkpoint =
-+ pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*pvr_fence->sync_checkpoint),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_fence->sync_checkpoint_fw_obj);
-+ if (IS_ERR(pvr_fence->sync_checkpoint)) {
-+ err = PTR_ERR(pvr_fence->sync_checkpoint);
-+ goto err_free;
-+ }
-+
-+ INIT_LIST_HEAD(&pvr_fence->dep_list);
-+ INIT_LIST_HEAD(&pvr_fence->dep_head);
-+
-+ dma_fence_init(&pvr_fence->base, &pvr_fence_ops, &context->fence_spinlock,
-+ context->fence_context, atomic_inc_return(&context->fence_id));
-+
-+ /*
-+ * The initial reference on this fence will be passed to the fence list as soon as the
-+ * fence is added to that list. Take another reference before then to hand back to the
-+ * caller.
-+ */
-+ dma_fence_get(&pvr_fence->base);
-+
-+ spin_lock_irqsave(&pvr_dev->fence_list_spinlock, flags);
-+ list_add_tail(&pvr_fence->head, &pvr_dev->fence_list);
-+ spin_unlock_irqrestore(&pvr_dev->fence_list_spinlock, flags);
-+
-+ return from_pvr_fence(pvr_fence);
-+
-+err_free:
-+ kfree(pvr_fence);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+static void
-+pvr_fence_release_dep_fences(struct pvr_fence *pvr_fence)
-+{
-+ struct pvr_device *pvr_dev = pvr_fence->context->pvr_dev;
-+ struct pvr_fence *dep_fence;
-+ struct pvr_fence *tmp;
-+ unsigned long flags;
-+
-+ LIST_HEAD(dep_fence_list);
-+
-+ spin_lock_irqsave(&pvr_dev->fence_list_spinlock, flags);
-+
-+ list_for_each_entry_safe(dep_fence, tmp, &pvr_fence->dep_list, dep_head)
-+ list_move_tail(&dep_fence->dep_head, &dep_fence_list);
-+
-+ spin_unlock_irqrestore(&pvr_dev->fence_list_spinlock, flags);
-+
-+ list_for_each_entry_safe(dep_fence, tmp, &dep_fence_list, dep_head) {
-+ list_del_init(&dep_fence->dep_head);
-+ dma_fence_put(&dep_fence->base);
-+ }
-+}
-+
-+static void
-+pvr_fence_destroy(struct pvr_fence *pvr_fence)
-+{
-+ struct pvr_device *pvr_dev = pvr_fence->context->pvr_dev;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&pvr_dev->fence_list_spinlock, flags);
-+ list_del(&pvr_fence->head);
-+ spin_unlock_irqrestore(&pvr_dev->fence_list_spinlock, flags);
-+
-+ pvr_fence_release_dep_fences(pvr_fence);
-+
-+ pvr_fw_object_vunmap(pvr_fence->sync_checkpoint_fw_obj, pvr_fence->sync_checkpoint, false);
-+ pvr_fw_object_release(pvr_fence->sync_checkpoint_fw_obj);
-+
-+ BUILD_BUG_ON(offsetof(typeof(*pvr_fence), base));
-+ dma_fence_free(&pvr_fence->base);
-+}
-+
-+static const char *
-+pvr_fence_get_driver_name(struct dma_fence *fence)
-+{
-+ return PVR_DRIVER_NAME;
-+}
-+
-+static const char *
-+pvr_fence_get_timeline_name(struct dma_fence *fence)
-+{
-+ struct pvr_fence *pvr_fence = to_pvr_fence(fence);
-+
-+ return (const char *)pvr_fence->context->timeline_name;
-+}
-+
-+static bool
-+pvr_fence_is_signaled(struct dma_fence *fence)
-+{
-+ struct pvr_fence *pvr_fence = to_pvr_fence(fence);
-+
-+ return (pvr_fence->sync_checkpoint->state == PVR_SYNC_CHECKPOINT_ERRORED) ||
-+ (pvr_fence->sync_checkpoint->state == PVR_SYNC_CHECKPOINT_SIGNALED);
-+}
-+
-+static void
-+pvr_fence_release(struct dma_fence *fence)
-+{
-+ struct pvr_fence *pvr_fence = to_pvr_fence(fence);
-+
-+ pvr_fence_destroy(pvr_fence);
-+}
-+
-+const struct dma_fence_ops pvr_fence_ops = {
-+ .get_driver_name = pvr_fence_get_driver_name,
-+ .get_timeline_name = pvr_fence_get_timeline_name,
-+ .release = pvr_fence_release,
-+ .signaled = pvr_fence_is_signaled,
-+};
-+
-+/**
-+ * pvr_fence_process_worker() - Process any completed fences
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+static void
-+pvr_fence_process_worker(struct work_struct *work)
-+{
-+ struct pvr_device *pvr_dev = container_of(work, struct pvr_device, fence_work);
-+ struct pvr_fence *pvr_fence;
-+ struct pvr_fence *tmp;
-+ unsigned long flags;
-+
-+ LIST_HEAD(signaled_list);
-+
-+ spin_lock_irqsave(&pvr_dev->fence_list_spinlock, flags);
-+
-+ /* Move any signaled fences to the signaled list for further processing. */
-+ list_for_each_entry_safe(pvr_fence, tmp, &pvr_dev->fence_list, head) {
-+ if (pvr_fence_is_signaled(&pvr_fence->base))
-+ list_move_tail(&pvr_fence->head, &signaled_list);
-+ }
-+
-+ /* Finished with device fence list, can now drop lock. */
-+ spin_unlock_irqrestore(&pvr_dev->fence_list_spinlock, flags);
-+
-+ list_for_each_entry_safe(pvr_fence, tmp, &signaled_list, head) {
-+ list_del_init(&pvr_fence->head);
-+
-+ /* Signal fence and drop our reference. */
-+ dma_fence_signal(&pvr_fence->base);
-+ pvr_fence_release_dep_fences(pvr_fence);
-+ dma_fence_put(&pvr_fence->base);
-+ }
-+}
-+
-+/**
-+ * pvr_fence_device_init() - Initialise fence handling for PowerVR device
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+void
-+pvr_fence_device_init(struct pvr_device *pvr_dev)
-+{
-+ spin_lock_init(&pvr_dev->fence_list_spinlock);
-+ INIT_LIST_HEAD(&pvr_dev->fence_list);
-+ INIT_WORK(&pvr_dev->fence_work, pvr_fence_process_worker);
-+}
-+
-+/**
-+ * pvr_fence_context_init() - Initialise fence context
-+ * @pvr_dev: Target PowerVR device.
-+ * @context: Pointer to fence context to initialise.
-+ * @name: Name of timeline this fence context represents.
-+ */
-+void
-+pvr_fence_context_init(struct pvr_device *pvr_dev, struct pvr_fence_context *context,
-+ const char *name)
-+{
-+ context->pvr_dev = pvr_dev;
-+ spin_lock_init(&context->fence_spinlock);
-+ atomic_set(&context->fence_id, 0);
-+ context->fence_context = dma_fence_context_alloc(1);
-+ strncpy(context->timeline_name, name, sizeof(context->timeline_name) - 1);
-+}
-+
-+/**
-+ * pvr_fence_to_ufo() - Create a UFO representation of a pvr_fence, for use by firmware
-+ * @fence: Pointer to fence to convert.
-+ * @ufo: Location to write UFO representation.
-+ *
-+ * Returns:
-+ * * 0 on success,
-+ * * -%EINVAL if provided fence is not a &struct pvr_fence, or
-+ * * -%ENOMEM if provided fence is not mapped to firmware.
-+ */
-+int
-+pvr_fence_to_ufo(struct dma_fence *fence, struct rogue_fwif_ufo *ufo)
-+{
-+ struct pvr_fence *pvr_fence = to_pvr_fence(fence);
-+
-+ if (unlikely(!pvr_fence))
-+ return -EINVAL;
-+
-+ if (!pvr_gem_get_fw_addr(pvr_fence->sync_checkpoint_fw_obj, &ufo->addr))
-+ return -ENOMEM;
-+
-+ ufo->addr |= ROGUE_FWIF_UFO_ADDR_IS_SYNC_CHECKPOINT;
-+ ufo->value = PVR_SYNC_CHECKPOINT_ACTIVE;
-+
-+ return 0;
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_fence.h b/drivers/gpu/drm/imagination/pvr_fence.h
-new file mode 100644
-index 000000000000..789a8768c911
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fence.h
-@@ -0,0 +1,148 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_FENCE_H__
-+#define __PVR_FENCE_H__
-+
-+#include "pvr_device.h"
-+
-+#include <linux/bits.h>
-+#include <linux/dma-fence.h>
-+#include <linux/list.h>
-+#include <linux/spinlock.h>
-+#include <linux/types.h>
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_fw_object;
-+
-+/* Forward declarations from pvr_rogue_fwif_shared.h. */
-+struct rogue_fwif_sync_checkpoint;
-+struct rogue_fwif_ufo;
-+
-+/**
-+ * &struct pvr_fence_context - PowerVR fence context
-+ */
-+struct pvr_fence_context {
-+ /** @pvr_dev: Owning PowerVR device. */
-+ struct pvr_device *pvr_dev;
-+
-+ /** @fence_spinlock: Lock used by pvr_fence. */
-+ spinlock_t fence_spinlock;
-+
-+ /** @fence_id: Next ID to be assigned when creating fences. */
-+ atomic_t fence_id;
-+
-+ /** @fence_context: Device fence context. */
-+ u64 fence_context;
-+
-+ /** @timeline_name: Name of timeline this fence context represents. */
-+ char timeline_name[32];
-+};
-+
-+/**
-+ * &struct pvr_fence - PowerVR fence structure
-+ */
-+struct pvr_fence {
-+ /** @base: Base DMA fence backing this pvr_fence. */
-+ struct dma_fence base;
-+
-+ /** @fence_context: Owning fence context. */
-+ struct pvr_fence_context *context;
-+
-+ /** @head: List head for this fence. */
-+ struct list_head head;
-+
-+ /**
-+ * @sync_checkpoint_fw_obj: FW object representing the sync checkpoint structure for this
-+ * fence.
-+ */
-+ struct pvr_fw_object *sync_checkpoint_fw_obj;
-+
-+ /** @sync_checkpoint: CPU mapping of sync checkpoint structure for this fence. */
-+ struct rogue_fwif_sync_checkpoint *sync_checkpoint;
-+
-+ /**
-+ * @dep_list: List of fences this fence depends on. All fences in this list will be
-+ * released when this fence is signalled or destroyed.
-+ */
-+ struct list_head dep_list;
-+
-+ /** @dep_head: Dependency list head for this fence. */
-+ struct list_head dep_head;
-+};
-+
-+extern const struct dma_fence_ops pvr_fence_ops;
-+
-+void
-+pvr_fence_device_init(struct pvr_device *pvr_dev);
-+void
-+pvr_fence_context_init(struct pvr_device *pvr_dev, struct pvr_fence_context *context,
-+ const char *name);
-+struct dma_fence *
-+pvr_fence_create(struct pvr_fence_context *context);
-+int
-+pvr_fence_to_ufo(struct dma_fence *fence, struct rogue_fwif_ufo *ufo);
-+
-+static __always_inline struct dma_fence *
-+from_pvr_fence(struct pvr_fence *pvr_fence)
-+{
-+ return &pvr_fence->base;
-+}
-+
-+static __always_inline struct pvr_fence *
-+to_pvr_fence(struct dma_fence *fence)
-+{
-+ if (fence->ops == &pvr_fence_ops)
-+ return container_of(fence, struct pvr_fence, base);
-+
-+ return NULL;
-+}
-+
-+/**
-+ * pvr_fence_add_fence_dependency() - Add dependency to pvr_fence
-+ * @fence: Target fence.
-+ * @dep_fence: Dependency to add.
-+ *
-+ * Dependency will be released when target fence is signalled or destroyed.
-+ *
-+ * Returns:
-+ * * 0 on success,
-+ * * -%EINVAL if provided fences are not pvr_fences, or
-+ * * -%EINVAL if dependency is already attached to a &struct pvr_fence.
-+ */
-+static __always_inline int
-+pvr_fence_add_fence_dependency(struct dma_fence *fence, struct dma_fence *dep_fence)
-+{
-+ struct pvr_fence *pvr_dep_fence = to_pvr_fence(dep_fence);
-+ struct pvr_fence *pvr_fence = to_pvr_fence(fence);
-+ struct pvr_device *pvr_dev;
-+ unsigned long flags;
-+ int err;
-+
-+ if (!pvr_fence || !pvr_dep_fence) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ pvr_dev = pvr_fence->context->pvr_dev;
-+ spin_lock_irqsave(&pvr_dev->fence_list_spinlock, flags);
-+
-+ if (!list_empty(&pvr_dep_fence->dep_head)) {
-+ err = -EINVAL;
-+ goto err_unlock;
-+ }
-+
-+ list_add_tail(&pvr_dep_fence->dep_head, &pvr_fence->dep_list);
-+
-+ spin_unlock_irqrestore(&pvr_dev->fence_list_spinlock, flags);
-+
-+ return 0;
-+
-+err_unlock:
-+ spin_unlock_irqrestore(&pvr_dev->fence_list_spinlock, flags);
-+
-+err_out:
-+ return err;
-+}
-+
-+#endif /* __PVR_FENCE_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_free_list.c b/drivers/gpu/drm/imagination/pvr_free_list.c
-new file mode 100644
-index 000000000000..869d9302f7b5
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_free_list.c
-@@ -0,0 +1,377 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_free_list.h"
-+#include "pvr_gem.h"
-+#include "pvr_object.h"
-+#include "pvr_rogue_fwif.h"
-+#include "pvr_vm.h"
-+
-+#include <drm/drm_gem.h>
-+#include <linux/slab.h>
-+#include <linux/xarray.h>
-+#include <uapi/drm/pvr_drm.h>
-+
-+#define FREE_LIST_ENTRY_SIZE sizeof(u32)
-+
-+#define FREE_LIST_ALIGNMENT \
-+ ((ROGUE_BIF_PM_FREELIST_BASE_ADDR_ALIGNSIZE / FREE_LIST_ENTRY_SIZE) - 1)
-+
-+static int
-+free_list_create_kernel_structure(
-+ struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_free_list_args *args,
-+ struct pvr_free_list *free_list)
-+{
-+ struct pvr_gem_object *free_list_obj;
-+ u64 free_list_size;
-+ int err;
-+
-+ if (args->grow_threshold < 0 || args->grow_threshold > 100 ||
-+ args->initial_num_pages > args->max_num_pages ||
-+ args->grow_num_pages > args->max_num_pages ||
-+ args->max_num_pages == 0 ||
-+ (args->initial_num_pages < args->max_num_pages && !args->grow_num_pages) ||
-+ (args->initial_num_pages == args->max_num_pages && args->grow_num_pages)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+ if ((args->initial_num_pages & FREE_LIST_ALIGNMENT) ||
-+ (args->max_num_pages & FREE_LIST_ALIGNMENT) ||
-+ (args->grow_num_pages & FREE_LIST_ALIGNMENT)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ free_list_obj = pvr_vm_find_gem_object(pvr_file->user_vm_ctx, args->free_list_gpu_addr,
-+ NULL, &free_list_size);
-+ if (IS_ERR(free_list_obj)) {
-+ err = PTR_ERR(free_list_obj);
-+ goto err_out;
-+ }
-+
-+ if ((free_list_obj->flags & DRM_PVR_BO_CPU_ALLOW_USERSPACE_ACCESS) ||
-+ !(free_list_obj->flags & DRM_PVR_BO_DEVICE_PM_FW_PROTECT) ||
-+ free_list_size < (args->max_num_pages * FREE_LIST_ENTRY_SIZE)) {
-+ err = -EINVAL;
-+ goto err_put_free_list_obj;
-+ }
-+
-+ free_list->base.type = DRM_PVR_OBJECT_TYPE_FREE_LIST;
-+ free_list->pvr_dev = pvr_file->pvr_dev;
-+ free_list->current_pages = 0;
-+ free_list->max_pages = args->max_num_pages;
-+ free_list->grow_pages = args->grow_num_pages;
-+ free_list->grow_threshold = args->grow_threshold;
-+ free_list->id = atomic_inc_return(&pvr_file->free_list_id);
-+ INIT_LIST_HEAD(&free_list->mem_block_list);
-+ free_list->obj = free_list_obj;
-+
-+ err = pvr_gem_object_get_pages(free_list->obj);
-+ if (err < 0)
-+ goto err_put_free_list_obj;
-+
-+ return 0;
-+
-+err_put_free_list_obj:
-+ pvr_gem_object_put(free_list_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+free_list_destroy_kernel_structure(struct pvr_free_list *free_list)
-+{
-+ pvr_gem_object_put_pages(free_list->obj);
-+ pvr_gem_object_put(free_list->obj);
-+}
-+
-+/**
-+ * calculate_free_list_ready_pages() - Function to work out the number of free
-+ * list pages to reserve for growing within
-+ * the FW without having to wait for the
-+ * host to progress a grow request
-+ * @free_list: Pointer to free list.
-+ * @pages: Total pages currently in free list.
-+ *
-+ * If the threshold or grow size means less than the alignment size (4 pages on
-+ * Rogue), then the feature is not used.
-+ *
-+ * Return: number of pages to reserve.
-+ */
-+static u32
-+calculate_free_list_ready_pages(struct pvr_free_list *free_list, u32 pages)
-+{
-+ u32 ready_pages = ((pages * free_list->grow_threshold) / 100);
-+
-+ /* The number of pages must be less than the grow size. */
-+ ready_pages = min(ready_pages, free_list->grow_pages);
-+
-+ /*
-+ * The number of pages must be a multiple of the free list align size.
-+ */
-+ ready_pages &= ~FREE_LIST_ALIGNMENT;
-+
-+ return ready_pages;
-+}
-+
-+static int
-+free_list_create_fw_structure(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_free_list_args *args,
-+ struct pvr_free_list *free_list)
-+{
-+ struct pvr_device *pvr_dev = pvr_file->pvr_dev;
-+ struct rogue_fwif_freelist *free_list_fw;
-+ u32 ready_pages;
-+ int err;
-+
-+ /*
-+ * Create and map the FW structure so we can initialise it. This is not
-+ * accessed on the CPU side post-initialisation so the mapping lifetime
-+ * is only for this function.
-+ */
-+ free_list_fw = pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*free_list_fw),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED, &free_list->fw_obj);
-+ if (IS_ERR(free_list_fw)) {
-+ err = PTR_ERR(free_list_fw);
-+ goto err_out;
-+ }
-+
-+ /* Fill out FW structure */
-+ ready_pages = calculate_free_list_ready_pages(free_list,
-+ args->initial_num_pages);
-+
-+ free_list_fw->max_pages = free_list->max_pages;
-+ free_list_fw->current_pages = args->initial_num_pages - ready_pages;
-+ free_list_fw->grow_pages = free_list->grow_pages;
-+ free_list_fw->ready_pages = ready_pages;
-+ free_list_fw->freelist_id = free_list->id;
-+ free_list_fw->grow_pending = false;
-+ free_list_fw->current_stack_top = free_list_fw->current_pages - 1;
-+ free_list_fw->freelist_dev_addr = args->free_list_gpu_addr;
-+ free_list_fw->current_dev_addr =
-+ (free_list_fw->freelist_dev_addr +
-+ ((free_list_fw->max_pages - free_list_fw->current_pages) *
-+ FREE_LIST_ENTRY_SIZE)) &
-+ ~((u64)ROGUE_BIF_PM_FREELIST_BASE_ADDR_ALIGNSIZE - 1);
-+
-+ pvr_fw_object_vunmap(free_list->fw_obj, free_list_fw, false);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+free_list_destroy_fw_structure(struct pvr_free_list *free_list)
-+{
-+ pvr_fw_object_release(free_list->fw_obj);
-+}
-+
-+static int
-+pvr_free_list_insert_pages(struct pvr_free_list *free_list,
-+ struct sg_table *sgt, u32 offset, u32 num_pages)
-+{
-+ struct sg_dma_page_iter dma_iter;
-+ u32 *page_list;
-+ int err;
-+
-+ page_list = pvr_gem_object_vmap(free_list->obj, false);
-+ if (IS_ERR(page_list)) {
-+ err = PTR_ERR(page_list);
-+ goto err_out;
-+ }
-+
-+ offset /= FREE_LIST_ENTRY_SIZE;
-+ /* clang-format off */
-+ for_each_sgtable_dma_page(sgt, &dma_iter, 0) {
-+ dma_addr_t dma_addr = sg_page_iter_dma_address(&dma_iter);
-+ u64 dma_pfn = dma_addr >>
-+ ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT;
-+ u32 dma_addr_offset;
-+
-+ BUILD_BUG_ON(ROGUE_BIF_PM_PHYSICAL_PAGE_SIZE > PAGE_SIZE);
-+
-+ for (dma_addr_offset = 0; dma_addr_offset < PAGE_SIZE;
-+ dma_addr_offset += ROGUE_BIF_PM_PHYSICAL_PAGE_SIZE) {
-+ WARN_ON_ONCE(dma_pfn >> 32);
-+
-+ page_list[offset++] = (u32)dma_pfn;
-+ dma_pfn++;
-+
-+ num_pages--;
-+ if (!num_pages)
-+ break;
-+ }
-+
-+ if (!num_pages)
-+ break;
-+ };
-+ /* clang-format on */
-+
-+ pvr_gem_object_vunmap(free_list->obj, page_list, true);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_free_list_grow(struct pvr_free_list *free_list, u32 num_pages)
-+{
-+ struct pvr_device *pvr_dev = free_list->pvr_dev;
-+ struct pvr_free_list_node *free_list_node;
-+ u32 start_page;
-+ u32 offset;
-+ int err;
-+
-+ if (num_pages & FREE_LIST_ALIGNMENT) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ free_list_node = kzalloc(sizeof(*free_list_node), GFP_KERNEL);
-+ if (!free_list_node) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ free_list_node->num_pages = num_pages;
-+ free_list_node->free_list = free_list;
-+
-+ free_list_node->mem_obj = pvr_gem_object_create(pvr_dev,
-+ num_pages << ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT,
-+ PVR_BO_FW_FLAGS_DEVICE_CACHED);
-+ if (IS_ERR(free_list_node->mem_obj)) {
-+ err = PTR_ERR(free_list_node->mem_obj);
-+ goto err_free;
-+ }
-+
-+ err = pvr_gem_object_get_pages(free_list_node->mem_obj);
-+ if (err < 0)
-+ goto err_destroy_gem_object;
-+
-+ start_page = free_list->max_pages - free_list->current_pages -
-+ free_list_node->num_pages;
-+ offset = ((start_page * FREE_LIST_ENTRY_SIZE) &
-+ ~((u64)ROGUE_BIF_PM_FREELIST_BASE_ADDR_ALIGNSIZE - 1));
-+
-+ pvr_free_list_insert_pages(free_list, free_list_node->mem_obj->sgt,
-+ offset, num_pages);
-+
-+ list_add_tail(&free_list_node->node, &free_list->mem_block_list);
-+
-+ free_list->current_pages += num_pages;
-+
-+ /*
-+ * Reserve a number ready pages to allow the FW to process OOM quickly
-+ * and asynchronously request a grow.
-+ */
-+ free_list->ready_pages =
-+ calculate_free_list_ready_pages(free_list,
-+ free_list->current_pages);
-+ free_list->current_pages -= free_list->ready_pages;
-+
-+ return 0;
-+
-+err_destroy_gem_object:
-+ pvr_gem_object_put(free_list_node->mem_obj);
-+
-+err_free:
-+ kfree(free_list_node);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+pvr_free_list_free_node(struct pvr_free_list_node *free_list_node)
-+{
-+ pvr_gem_object_put_pages(free_list_node->mem_obj);
-+ pvr_gem_object_put(free_list_node->mem_obj);
-+
-+ kfree(free_list_node);
-+}
-+
-+/**
-+ * pvr_free_list_create() - Create a new free list and return an object pointer
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @args: Creation arguments from userspace.
-+ *
-+ * Return:
-+ * * Free list pointer on success, or
-+ * * -%ENOMEM on out of memory.
-+ */
-+struct pvr_free_list *
-+pvr_free_list_create(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_free_list_args *args)
-+{
-+ struct pvr_free_list *free_list;
-+ int err;
-+
-+ /* Create and fill out the kernel structure */
-+ free_list = kzalloc(sizeof(*free_list), GFP_KERNEL);
-+ if (!free_list) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ err = free_list_create_kernel_structure(pvr_file, args, free_list);
-+ if (err < 0)
-+ goto err_free;
-+
-+ err = free_list_create_fw_structure(pvr_file, args, free_list);
-+ if (err < 0)
-+ goto err_destroy_kernel_structure;
-+
-+ err = pvr_free_list_grow(free_list, args->initial_num_pages);
-+ if (err < 0)
-+ goto err_destroy_fw_structure;
-+
-+ return free_list;
-+
-+err_destroy_fw_structure:
-+ free_list_destroy_fw_structure(free_list);
-+
-+err_destroy_kernel_structure:
-+ free_list_destroy_kernel_structure(free_list);
-+
-+err_free:
-+ kfree(free_list);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * pvr_free_list_destroy() - Destroy a free list
-+ * @free_list: Free list to be destroyed.
-+ *
-+ * This should not be called directly. Free list references should be dropped via
-+ * pvr_free_list_put().
-+ */
-+void
-+pvr_free_list_destroy(struct pvr_free_list *free_list)
-+{
-+ struct list_head *pos, *n;
-+
-+ WARN_ON(pvr_object_cleanup(free_list->pvr_dev, ROGUE_FWIF_CLEANUP_FREELIST,
-+ free_list->fw_obj, 0));
-+
-+ /* clang-format off */
-+ list_for_each_safe(pos, n, &free_list->mem_block_list) {
-+ struct pvr_free_list_node *free_list_node =
-+ container_of(pos, struct pvr_free_list_node, node);
-+
-+ list_del(pos);
-+ pvr_free_list_free_node(free_list_node);
-+ }
-+ /* clang-format on */
-+
-+ free_list_destroy_kernel_structure(free_list);
-+ free_list_destroy_fw_structure(free_list);
-+ kfree(free_list);
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_free_list.h b/drivers/gpu/drm/imagination/pvr_free_list.h
-new file mode 100644
-index 000000000000..f7eef2c10d61
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_free_list.h
-@@ -0,0 +1,139 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_FREE_LIST_H__
-+#define __PVR_FREE_LIST_H__
-+
-+#include <linux/compiler_attributes.h>
-+#include <linux/kref.h>
-+#include <linux/list.h>
-+#include <linux/types.h>
-+#include <linux/xarray.h>
-+#include <uapi/drm/pvr_drm.h>
-+
-+#include "pvr_device.h"
-+#include "pvr_object.h"
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_fw_object;
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_gem_object;
-+
-+/**
-+ * struct pvr_free_list_node - structure representing an allocation in the free
-+ * list
-+ */
-+struct pvr_free_list_node {
-+ /** @node: List node for &pvr_free_list.mem_block_list. */
-+ struct list_head node;
-+
-+ /** @free_list: Pointer to owning free list. */
-+ struct pvr_free_list *free_list;
-+
-+ /** @num_pages: Number of pages in this node. */
-+ u32 num_pages;
-+
-+ /** @mem_obj: GEM object representing the pages in this node. */
-+ struct pvr_gem_object *mem_obj;
-+};
-+
-+/**
-+ * struct pvr_free_list - structure representing a free list
-+ */
-+struct pvr_free_list {
-+ /** @base: Object base structure. */
-+ struct pvr_object base;
-+
-+ /** @pvr_dev: Pointer to owning device. */
-+ struct pvr_device *pvr_dev;
-+
-+ /** @obj: GEM object representing the free list. */
-+ struct pvr_gem_object *obj;
-+
-+ /** @fw_obj: FW object representing the FW-side structure. */
-+ struct pvr_fw_object *fw_obj;
-+
-+ /** @current_pages: Current number of pages in free list. */
-+ u32 current_pages;
-+
-+ /** @max_pages: Maximum number of pages in free list. */
-+ u32 max_pages;
-+
-+ /** @grow_pages: Pages to grow free list by per request. */
-+ u32 grow_pages;
-+
-+ /**
-+ * @grow_threshold: Percentage of FL memory used that should trigger a
-+ * new grow request.
-+ */
-+ u32 grow_threshold;
-+
-+ /**
-+ * @ready_pages: Number of pages reserved for FW to use while a grow
-+ * request is being processed.
-+ */
-+ u32 ready_pages;
-+
-+ /** @id: FW-side ID for the free list. */
-+ u32 id;
-+
-+ /** @mem_block_list: List of memory blocks in this free list. */
-+ struct list_head mem_block_list;
-+};
-+
-+static __always_inline struct pvr_object *
-+from_pvr_free_list(struct pvr_free_list *free_list)
-+{
-+ return &free_list->base;
-+};
-+
-+static __always_inline struct pvr_free_list *
-+to_pvr_free_list(struct pvr_object *obj)
-+{
-+ return container_of(obj, struct pvr_free_list, base);
-+}
-+
-+struct pvr_free_list *
-+pvr_free_list_create(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_free_list_args *args);
-+
-+void pvr_free_list_destroy(struct pvr_free_list *free_list);
-+
-+/**
-+ * pvr_free_list_get() - Get free list pointer from handle
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @handle: Object handle.
-+ *
-+ * Takes reference on object. Call pvr_object_put() to release.
-+ *
-+ * Returns:
-+ * * The requested object on success, or
-+ * * %NULL on failure (object does not exist in list, or is not a free list)
-+ */
-+static __always_inline struct pvr_free_list *
-+pvr_free_list_get(struct pvr_file *pvr_file, u32 handle)
-+{
-+ struct pvr_object *obj = pvr_object_get(pvr_file, handle);
-+
-+ if (obj) {
-+ if (obj->type == DRM_PVR_OBJECT_TYPE_FREE_LIST)
-+ return to_pvr_free_list(obj);
-+
-+ pvr_object_put(obj);
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * pvr_free_list_put() - Release reference on free list
-+ * @free_list: Pointer to list to release reference on
-+ */
-+static __always_inline void
-+pvr_free_list_put(struct pvr_free_list *free_list)
-+{
-+ pvr_object_put(&free_list->base);
-+}
-+
-+#endif /* __PVR_FREE_LIST_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c
-new file mode 100644
-index 000000000000..6d185c24f1ab
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fw.c
-@@ -0,0 +1,900 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_ccb.h"
-+#include "pvr_device.h"
-+#include "pvr_fw.h"
-+#include "pvr_fw_info.h"
-+#include "pvr_fw_trace.h"
-+#include "pvr_gem.h"
-+#include "pvr_rogue_heap_config.h"
-+
-+#include <drm/drm_mm.h>
-+#include <linux/firmware.h>
-+#include <linux/minmax.h>
-+#include <linux/sizes.h>
-+
-+#define FW_BOOT_TIMEOUT_USEC 5000000
-+
-+/* Config heap occupies top 192k of the firmware heap. */
-+#define PVR_ROGUE_FW_CONFIG_HEAP_GRANULARITY SZ_64K
-+#define PVR_ROGUE_FW_CONFIG_HEAP_SIZE (3 * PVR_ROGUE_FW_CONFIG_HEAP_GRANULARITY)
-+
-+/* Main firmware allocations should come from the remainder of the heap. */
-+#define PVR_ROGUE_FW_MAIN_HEAP_BASE ROGUE_FW_HEAP_BASE
-+
-+/* Offsets from start of configuration area of FW heap. */
-+#define PVR_ROGUE_FWIF_CONNECTION_CTL_OFFSET 0
-+#define PVR_ROGUE_FWIF_OSINIT_OFFSET \
-+ (PVR_ROGUE_FWIF_CONNECTION_CTL_OFFSET + PVR_ROGUE_FW_CONFIG_HEAP_GRANULARITY)
-+#define PVR_ROGUE_FWIF_SYSINIT_OFFSET \
-+ (PVR_ROGUE_FWIF_OSINIT_OFFSET + PVR_ROGUE_FW_CONFIG_HEAP_GRANULARITY)
-+
-+#define PVR_ROGUE_FAULT_PAGE_SIZE SZ_4K
-+
-+#define PVR_SYNC_OBJ_SIZE sizeof(u32)
-+
-+const struct pvr_fw_layout_entry *
-+pvr_fw_find_layout_entry(const struct pvr_fw_layout_entry *layout_entries, u32 num_layout_entries,
-+ enum pvr_fw_section_id id)
-+{
-+ u32 entry;
-+
-+ for (entry = 0; entry < num_layout_entries; entry++) {
-+ if (layout_entries[entry].id == id)
-+ return &layout_entries[entry];
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * pvr_fw_validate() - Parse firmware header and check compatibility
-+ * @pvr_dev: Device pointer.
-+ * @header_out: Pointer to location to write firmware header pointer.
-+ * @layout_entries_out: Pointer to location to write layout table pointer.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -EINVAL if firmware is incompatible.
-+ */
-+static int
-+pvr_fw_validate(struct pvr_device *pvr_dev,
-+ const struct pvr_fw_info_header **header_out,
-+ const struct pvr_fw_layout_entry **layout_entries_out)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ const u8 *fw = pvr_dev->fw->data;
-+ u32 fw_offset = pvr_dev->fw->size - SZ_4K;
-+ const struct pvr_fw_layout_entry *layout_entries;
-+ const struct pvr_fw_info_header *header;
-+ u32 layout_table_size;
-+ u32 entry;
-+ int err;
-+
-+ if ((pvr_dev->fw->size < SZ_4K) ||
-+ (pvr_dev->fw->size % FW_BLOCK_SIZE)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ header = (const struct pvr_fw_info_header *)&fw[fw_offset];
-+
-+ if (header->info_version != PVR_FW_INFO_VERSION) {
-+ drm_err(drm_dev, "Unsupported fw info version %u\n",
-+ header->info_version);
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if (header->header_len != sizeof(struct pvr_fw_info_header) ||
-+ header->layout_entry_size != sizeof(struct pvr_fw_layout_entry) ||
-+ header->layout_entry_num > PVR_FW_INFO_MAX_NUM_ENTRIES) {
-+ drm_err(drm_dev, "FW info format mismatch\n");
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if (pvr_version_to_packed_bvnc(&pvr_dev->version) != header->bvnc) {
-+ struct pvr_version fw_version;
-+
-+ packed_bvnc_to_pvr_version(header->bvnc, &fw_version);
-+ drm_err(drm_dev, "Unsupported fw version %i.%i.%i.%i\n",
-+ fw_version.b, fw_version.v, fw_version.n, fw_version.c);
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ fw_offset += header->header_len;
-+ layout_table_size =
-+ header->layout_entry_size * header->layout_entry_num;
-+ if ((fw_offset + layout_table_size) > pvr_dev->fw->size) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ layout_entries = (const struct pvr_fw_layout_entry *)&fw[fw_offset];
-+ for (entry = 0; entry < header->layout_entry_num; entry++) {
-+ u32 start_addr = layout_entries[entry].base_addr;
-+ u32 end_addr = start_addr + layout_entries[entry].alloc_size;
-+
-+ if (start_addr >= end_addr) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+ }
-+
-+ *header_out = header;
-+ *layout_entries_out = layout_entries;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+layout_get_sizes(const struct pvr_fw_layout_entry *layout_entries,
-+ u32 num_layout_entries, u32 *code_alloc_size,
-+ u32 *data_alloc_size, u32 *core_code_alloc_size,
-+ u32 *core_data_alloc_size)
-+{
-+ u32 entry;
-+
-+ *code_alloc_size = 0;
-+ *data_alloc_size = 0;
-+ *core_code_alloc_size = 0;
-+ *core_data_alloc_size = 0;
-+
-+ /* Extract section sizes from FW layout table. */
-+ for (entry = 0; entry < num_layout_entries; entry++) {
-+ switch (layout_entries[entry].type) {
-+ case FW_CODE:
-+ (*code_alloc_size) += layout_entries[entry].alloc_size;
-+ break;
-+ case FW_DATA:
-+ (*data_alloc_size) += layout_entries[entry].alloc_size;
-+ break;
-+ case FW_COREMEM_CODE:
-+ (*core_code_alloc_size) +=
-+ layout_entries[entry].alloc_size;
-+ break;
-+ case FW_COREMEM_DATA:
-+ (*core_data_alloc_size) +=
-+ layout_entries[entry].alloc_size;
-+ break;
-+ case NONE:
-+ break;
-+ }
-+ }
-+}
-+
-+int
-+pvr_fw_find_mmu_segment(u32 addr, u32 size, const struct pvr_fw_layout_entry *layout_entries,
-+ u32 num_layout_entries, void *fw_code_ptr, void *fw_data_ptr,
-+ void *fw_core_code_ptr, void *fw_core_data_ptr,
-+ void **host_addr_out)
-+{
-+ u32 end_addr = addr + size;
-+ int entry = 0;
-+ int err;
-+
-+ /* Ensure requested range is not zero, and size is not causing addr to overflow. */
-+ if (end_addr <= addr) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ for (entry = 0; entry < num_layout_entries; entry++) {
-+ u32 entry_start_addr = layout_entries[entry].base_addr;
-+ u32 entry_end_addr = entry_start_addr + layout_entries[entry].alloc_size;
-+
-+ if (addr >= entry_start_addr && addr < entry_end_addr &&
-+ end_addr > entry_start_addr && end_addr <= entry_end_addr) {
-+ switch (layout_entries[entry].type) {
-+ case FW_CODE:
-+ *host_addr_out = fw_code_ptr;
-+ break;
-+
-+ case FW_DATA:
-+ *host_addr_out = fw_data_ptr;
-+ break;
-+
-+ case FW_COREMEM_CODE:
-+ *host_addr_out = fw_core_code_ptr;
-+ break;
-+
-+ case FW_COREMEM_DATA:
-+ *host_addr_out = fw_core_data_ptr;
-+ break;
-+
-+ default:
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+ /* Direct Mem write to mapped memory */
-+ addr -= layout_entries[entry].base_addr;
-+ addr += layout_entries[entry].alloc_offset;
-+
-+ /*
-+ * Add offset to pointer to FW allocation only if that
-+ * allocation is available
-+ */
-+ *(u8 **)host_addr_out += addr;
-+ return 0;
-+ }
-+ }
-+
-+ err = -EINVAL;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_fw_create_fwif_connection_ctl(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ int err;
-+
-+ pvr_dev->fwif_connection_ctl = pvr_gem_create_and_map_fw_object_offset(pvr_dev,
-+ pvr_dev->fw_heap_info.config_offset + PVR_ROGUE_FWIF_CONNECTION_CTL_OFFSET,
-+ sizeof(*pvr_dev->fwif_connection_ctl),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fwif_connection_ctl_obj);
-+ if (IS_ERR(pvr_dev->fwif_connection_ctl)) {
-+ drm_err(drm_dev,
-+ "Unable to allocate FWIF connection control memory\n");
-+ err = PTR_ERR(pvr_dev->fwif_connection_ctl);
-+ goto err_out;
-+ }
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+pvr_fw_fini_fwif_connection_ctl(struct pvr_device *pvr_dev)
-+{
-+ pvr_fw_object_vunmap(pvr_dev->fwif_connection_ctl_obj,
-+ pvr_dev->fwif_connection_ctl, false);
-+ pvr_fw_object_release(pvr_dev->fwif_connection_ctl_obj);
-+}
-+
-+static int
-+pvr_fw_create_os_structures(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct rogue_fwif_hwrinfobuf *hwrinfobuf;
-+ int err;
-+
-+ pvr_dev->fw_osinit = pvr_gem_create_and_map_fw_object_offset(pvr_dev,
-+ pvr_dev->fw_heap_info.config_offset + PVR_ROGUE_FWIF_OSINIT_OFFSET,
-+ sizeof(*pvr_dev->fw_osinit), PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_osinit_obj);
-+ if (IS_ERR(pvr_dev->fw_osinit)) {
-+ drm_err(drm_dev, "Unable to allocate FW OSINIT structure\n");
-+ err = PTR_ERR(pvr_dev->fw_osinit);
-+ goto err_out;
-+ }
-+
-+ pvr_dev->fw_osdata = pvr_gem_create_and_map_fw_object(
-+ pvr_dev, sizeof(*pvr_dev->fw_osdata),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_osdata_obj);
-+ if (IS_ERR(pvr_dev->fw_osdata)) {
-+ drm_err(drm_dev, "Unable to allocate FW OSDATA structure\n");
-+ err = PTR_ERR(pvr_dev->fw_osdata);
-+ goto err_release_osinit;
-+ }
-+
-+ hwrinfobuf = pvr_gem_create_and_map_fw_object(
-+ pvr_dev, sizeof(*hwrinfobuf),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_hwrinfobuf_obj);
-+ if (IS_ERR(hwrinfobuf)) {
-+ drm_err(drm_dev,
-+ "Unable to allocate FW hwrinfobuf structure\n");
-+ err = PTR_ERR(hwrinfobuf);
-+ goto err_release_osdata;
-+ }
-+
-+ err = pvr_gem_create_fw_object(pvr_dev, PVR_SYNC_OBJ_SIZE,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_mmucache_sync_obj);
-+ if (err) {
-+ drm_err(drm_dev,
-+ "Unable to allocate MMU cache sync object\n");
-+ goto err_release_hwrinfobuf;
-+ }
-+
-+ pvr_dev->fw_osinit->kernel_ccbctl_fw_addr =
-+ pvr_dev->kccb.ctrl_fw_addr;
-+ pvr_dev->fw_osinit->kernel_ccb_fw_addr = pvr_dev->kccb.ccb_fw_addr;
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_dev->kccb_rtn_obj,
-+ &pvr_dev->fw_osinit->kernel_ccb_rtn_slots_fw_addr));
-+
-+ pvr_dev->fw_osinit->firmware_ccbctl_fw_addr =
-+ pvr_dev->fwccb.ctrl_fw_addr;
-+ pvr_dev->fw_osinit->firmware_ccb_fw_addr = pvr_dev->fwccb.ccb_fw_addr;
-+
-+ pvr_dev->fw_osinit->work_est_firmware_ccbctl_fw_addr = 0;
-+ pvr_dev->fw_osinit->work_est_firmware_ccb_fw_addr = 0;
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ pvr_dev->fw_hwrinfobuf_obj,
-+ &pvr_dev->fw_osinit->rogue_fwif_hwr_info_buf_ctl_fw_addr));
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_dev->fw_osdata_obj,
-+ &pvr_dev->fw_osinit->fw_os_data_fw_addr));
-+
-+ pvr_dev->fw_osinit->hwr_debug_dump_limit = 0;
-+
-+ ROGUE_FWIF_COMPCHECKS_BVNC_INIT(
-+ pvr_dev->fw_osinit->rogue_comp_checks.hw_bvnc);
-+ ROGUE_FWIF_COMPCHECKS_BVNC_INIT(
-+ pvr_dev->fw_osinit->rogue_comp_checks.fw_bvnc);
-+
-+ pvr_fw_object_vunmap(pvr_dev->fw_hwrinfobuf_obj, hwrinfobuf, false);
-+ /* fw_osinit_obj and fw_osdata_obj remain mapped on the CPU. */
-+ return 0;
-+
-+err_release_hwrinfobuf:
-+ pvr_fw_object_vunmap(pvr_dev->fw_hwrinfobuf_obj, hwrinfobuf, false);
-+ pvr_fw_object_release(pvr_dev->fw_hwrinfobuf_obj);
-+
-+err_release_osdata:
-+ pvr_fw_object_vunmap(pvr_dev->fw_osdata_obj, pvr_dev->fw_osdata, false);
-+ pvr_fw_object_release(pvr_dev->fw_osdata_obj);
-+
-+err_release_osinit:
-+ pvr_fw_object_vunmap(pvr_dev->fw_osinit_obj, pvr_dev->fw_osinit, false);
-+ pvr_fw_object_release(pvr_dev->fw_osinit_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+pvr_fw_destroy_os_structures(struct pvr_device *pvr_dev)
-+{
-+ pvr_fw_object_release(pvr_dev->fw_mmucache_sync_obj);
-+ pvr_fw_object_release(pvr_dev->fw_hwrinfobuf_obj);
-+ pvr_fw_object_vunmap(pvr_dev->fw_osdata_obj, pvr_dev->fw_osdata, false);
-+ pvr_fw_object_release(pvr_dev->fw_osdata_obj);
-+ pvr_fw_object_vunmap(pvr_dev->fw_osinit_obj, pvr_dev->fw_osinit, false);
-+ pvr_fw_object_release(pvr_dev->fw_osinit_obj);
-+}
-+
-+static int
-+pvr_fw_create_dev_structures(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct rogue_fwif_sysdata *sysdata;
-+ struct rogue_fwif_gpu_util_fwcb *gpu_util_fwcb;
-+ struct rogue_fwif_runtime_cfg *runtime_cfg;
-+ u32 clock_speed_hz;
-+ u32 *fault_page;
-+ dma_addr_t fault_dma_addr;
-+ int i;
-+ int err;
-+
-+ pvr_dev->fw_sysinit = pvr_gem_create_and_map_fw_object_offset(pvr_dev,
-+ pvr_dev->fw_heap_info.config_offset + PVR_ROGUE_FWIF_SYSINIT_OFFSET,
-+ sizeof(*pvr_dev->fw_sysinit),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_sysinit_obj);
-+ if (IS_ERR(pvr_dev->fw_sysinit)) {
-+ drm_err(drm_dev, "Unable to allocate FW SYSINIT structure\n");
-+ err = PTR_ERR(pvr_dev->fw_sysinit);
-+ goto err_out;
-+ }
-+
-+ sysdata = pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*sysdata),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_sysdata_obj);
-+ if (IS_ERR(sysdata)) {
-+ drm_err(drm_dev, "Unable to allocate FW SYSDATA structure\n");
-+ err = PTR_ERR(sysdata);
-+ goto err_release_sysinit;
-+ }
-+ sysdata->config_flags = 0;
-+ sysdata->config_flags_ext = 0;
-+ pvr_fw_object_vunmap(pvr_dev->fw_sysdata_obj, sysdata, false);
-+
-+ fault_page = pvr_gem_create_and_map_fw_object(pvr_dev, PVR_ROGUE_FAULT_PAGE_SIZE,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED,
-+ &pvr_dev->fw_fault_page_obj);
-+ if (IS_ERR(fault_page)) {
-+ drm_err(drm_dev, "Unable to allocate FW fault page\n");
-+ err = PTR_ERR(fault_page);
-+ goto err_release_sysdata;
-+ }
-+ for (i = 0; i < PVR_ROGUE_FAULT_PAGE_SIZE / sizeof(*fault_page); i++)
-+ fault_page[i] = 0xdeadbee0;
-+ pvr_fw_object_vunmap(pvr_dev->fw_fault_page_obj, fault_page, false);
-+
-+ gpu_util_fwcb = pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*gpu_util_fwcb),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_gpu_util_fwcb_obj);
-+ if (IS_ERR(gpu_util_fwcb)) {
-+ drm_err(drm_dev, "Unable to allocate GPU util FWCB\n");
-+ err = PTR_ERR(gpu_util_fwcb);
-+ goto err_release_fault_page;
-+ }
-+ /* TODO : add timestamp. */
-+ gpu_util_fwcb->last_word = PVR_FWIF_GPU_UTIL_STATE_IDLE;
-+ pvr_fw_object_vunmap(pvr_dev->fw_gpu_util_fwcb_obj, gpu_util_fwcb, false);
-+
-+ err = pvr_device_clk_core_get_freq(pvr_dev, &clock_speed_hz);
-+ if (err) {
-+ drm_err(drm_dev, "Unable to determine core clock frequency\n");
-+ goto err_release_gpu_util_fwcb;
-+ }
-+
-+ runtime_cfg = pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*runtime_cfg),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_runtime_cfg_obj);
-+ if (IS_ERR(runtime_cfg)) {
-+ drm_err(drm_dev, "Unable to allocate FW runtime config\n");
-+ err = PTR_ERR(runtime_cfg);
-+ goto err_release_gpu_util_fwcb;
-+ }
-+ runtime_cfg->core_clock_speed = clock_speed_hz;
-+ runtime_cfg->active_pm_latency_ms = 0;
-+ runtime_cfg->active_pm_latency_persistant = true;
-+ WARN_ON(PVR_FEATURE_VALUE(pvr_dev, num_clusters,
-+ &runtime_cfg->default_dusts_num_init) != 0);
-+ pvr_fw_object_vunmap(pvr_dev->fw_runtime_cfg_obj, runtime_cfg, false);
-+
-+ err = pvr_fw_trace_init(pvr_dev);
-+ if (err)
-+ goto err_release_runtime_cfg;
-+
-+ err = pvr_fw_get_dma_addr(pvr_dev->fw_fault_page_obj, 0, &fault_dma_addr);
-+ if (err) {
-+ drm_err(drm_dev,
-+ "Unable to get FW fault page physical address\n");
-+ goto err_trace_fini;
-+ }
-+ pvr_dev->fw_sysinit->fault_phys_addr = (u64)fault_dma_addr;
-+
-+ pvr_dev->fw_sysinit->pds_exec_base = ROGUE_PDSCODEDATA_HEAP_BASE;
-+ pvr_dev->fw_sysinit->usc_exec_base = ROGUE_USCCODE_HEAP_BASE;
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ pvr_dev->fw_runtime_cfg_obj,
-+ &pvr_dev->fw_sysinit->runtime_cfg_fw_addr));
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ pvr_dev->fw_trace.tracebuf_ctrl_obj,
-+ &pvr_dev->fw_sysinit->trace_buf_ctl_fw_addr));
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ pvr_dev->fw_sysdata_obj,
-+ &pvr_dev->fw_sysinit->fw_sys_data_fw_addr));
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ pvr_dev->fw_gpu_util_fwcb_obj,
-+ &pvr_dev->fw_sysinit->gpu_util_fw_cb_ctl_fw_addr));
-+ if (pvr_dev->fw_core_data_obj) {
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ pvr_dev->fw_core_data_obj,
-+ &pvr_dev->fw_sysinit->coremem_data_store.fw_addr));
-+ }
-+
-+ /* Currently unsupported. */
-+ pvr_dev->fw_sysinit->counter_dump_ctl.buffer_fw_addr = 0;
-+ pvr_dev->fw_sysinit->counter_dump_ctl.size_in_dwords = 0;
-+
-+ /* Skip alignment checks. */
-+ pvr_dev->fw_sysinit->align_checks = 0;
-+
-+ pvr_dev->fw_sysinit->filter_flags = 0;
-+ pvr_dev->fw_sysinit->hw_perf_filter = 0;
-+ pvr_dev->fw_sysinit->firmware_perf = FW_PERF_CONF_NONE;
-+ pvr_dev->fw_sysinit->initial_core_clock_speed = clock_speed_hz;
-+ pvr_dev->fw_sysinit->active_pm_latency_ms = 0;
-+ pvr_dev->fw_sysinit->gpio_validation_mode = ROGUE_FWIF_GPIO_VAL_OFF;
-+ pvr_dev->fw_sysinit->firmware_started = false;
-+ pvr_dev->fw_sysinit->marker_val = 1;
-+
-+ memset(&pvr_dev->fw_sysinit->bvnc_km_feature_flags, 0,
-+ sizeof(pvr_dev->fw_sysinit->bvnc_km_feature_flags));
-+
-+ return 0;
-+
-+err_trace_fini:
-+ pvr_fw_trace_fini(pvr_dev);
-+
-+err_release_runtime_cfg:
-+ pvr_fw_object_release(pvr_dev->fw_runtime_cfg_obj);
-+
-+err_release_gpu_util_fwcb:
-+ pvr_fw_object_release(pvr_dev->fw_gpu_util_fwcb_obj);
-+
-+err_release_fault_page:
-+ pvr_fw_object_release(pvr_dev->fw_fault_page_obj);
-+
-+err_release_sysdata:
-+ pvr_fw_object_release(pvr_dev->fw_sysdata_obj);
-+
-+err_release_sysinit:
-+ pvr_fw_object_vunmap(pvr_dev->fw_sysinit_obj, pvr_dev->fw_sysinit, false);
-+ pvr_fw_object_release(pvr_dev->fw_sysinit_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+pvr_fw_destroy_dev_structures(struct pvr_device *pvr_dev)
-+{
-+ pvr_fw_trace_fini(pvr_dev);
-+ pvr_fw_object_release(pvr_dev->fw_runtime_cfg_obj);
-+ pvr_fw_object_release(pvr_dev->fw_gpu_util_fwcb_obj);
-+ pvr_fw_object_release(pvr_dev->fw_fault_page_obj);
-+ pvr_fw_object_release(pvr_dev->fw_sysdata_obj);
-+ pvr_fw_object_vunmap(pvr_dev->fw_sysinit_obj, pvr_dev->fw_sysinit, false);
-+ pvr_fw_object_release(pvr_dev->fw_sysinit_obj);
-+}
-+
-+/**
-+ * pvr_fw_process() - Process firmware image, allocate FW memory and create boot
-+ * arguments
-+ * @pvr_dev: Device pointer.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_gem_create_and_map_fw_object_offset(), or
-+ * * Any error returned by pvr_gem_create_and_map_fw_object().
-+ */
-+static int
-+pvr_fw_process(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ const u8 *fw = pvr_dev->fw->data;
-+ const struct pvr_fw_info_header *header;
-+ const struct pvr_fw_layout_entry *layout_entries;
-+ u32 code_alloc_size;
-+ u32 data_alloc_size;
-+ u32 core_code_alloc_size;
-+ u32 core_data_alloc_size;
-+ u8 *fw_code_ptr;
-+ u8 *fw_data_ptr;
-+ u8 *fw_core_code_ptr;
-+ u8 *fw_core_data_ptr;
-+ int err;
-+
-+ err = pvr_fw_validate(pvr_dev, &header, &layout_entries);
-+ if (err)
-+ goto err_out;
-+
-+ layout_get_sizes(layout_entries, header->layout_entry_num,
-+ &code_alloc_size, &data_alloc_size,
-+ &core_code_alloc_size, &core_data_alloc_size);
-+
-+ /* Allocate and map memory for firmware sections. */
-+
-+ /*
-+ * Code allocation must be at the start of the firmware heap, otherwise
-+ * firmware processor will be unable to boot.
-+ *
-+ * This has the useful side-effect that for every other object in the
-+ * driver, a firmware address of 0 is invalid.
-+ */
-+ fw_code_ptr = pvr_gem_create_and_map_fw_object_offset(pvr_dev, 0, code_alloc_size,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED, &pvr_dev->fw_code_obj);
-+ if (IS_ERR(fw_code_ptr)) {
-+ drm_err(drm_dev, "Unable to allocate FW code memory\n");
-+ err = PTR_ERR(fw_code_ptr);
-+ goto err_out;
-+ }
-+
-+ fw_data_ptr = pvr_gem_create_and_map_fw_object(pvr_dev, data_alloc_size,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED, &pvr_dev->fw_data_obj);
-+ if (IS_ERR(fw_data_ptr)) {
-+ drm_err(drm_dev, "Unable to allocate FW data memory\n");
-+ err = PTR_ERR(fw_data_ptr);
-+ goto err_free_fw_code_obj;
-+ }
-+
-+ /* Core code and data sections are optional. */
-+ if (core_code_alloc_size) {
-+ fw_core_code_ptr = pvr_gem_create_and_map_fw_object(pvr_dev, core_code_alloc_size,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_core_code_obj);
-+ if (IS_ERR(fw_core_code_ptr)) {
-+ drm_err(drm_dev,
-+ "Unable to allocate FW core code memory\n");
-+ err = PTR_ERR(fw_core_code_ptr);
-+ goto err_free_fw_data_obj;
-+ }
-+ } else {
-+ fw_core_code_ptr = NULL;
-+ }
-+
-+ if (core_data_alloc_size) {
-+ fw_core_data_ptr = pvr_gem_create_and_map_fw_object(pvr_dev, core_data_alloc_size,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->fw_core_data_obj);
-+ if (IS_ERR(fw_core_data_ptr)) {
-+ drm_err(drm_dev,
-+ "Unable to allocate FW core data memory\n");
-+ err = PTR_ERR(fw_core_data_ptr);
-+ goto err_free_fw_core_code_obj;
-+ }
-+ } else {
-+ fw_core_data_ptr = NULL;
-+ }
-+
-+ err = pvr_dev->fw_funcs->fw_process(pvr_dev, fw, layout_entries, header->layout_entry_num,
-+ fw_code_ptr, fw_data_ptr, fw_core_code_ptr,
-+ fw_core_data_ptr, core_code_alloc_size);
-+
-+ if (err)
-+ goto err_free_fw_core_data_obj;
-+
-+ /* We're finished with the firmware section memory on the CPU, unmap. */
-+ if (fw_core_data_ptr)
-+ pvr_fw_object_vunmap(pvr_dev->fw_core_data_obj, fw_core_data_ptr, false);
-+ if (fw_core_code_ptr)
-+ pvr_fw_object_vunmap(pvr_dev->fw_core_code_obj, fw_core_code_ptr, false);
-+ pvr_fw_object_vunmap(pvr_dev->fw_data_obj, fw_data_ptr, false);
-+ fw_data_ptr = NULL;
-+ pvr_fw_object_vunmap(pvr_dev->fw_code_obj, fw_code_ptr, false);
-+ fw_code_ptr = NULL;
-+
-+ err = pvr_fw_create_fwif_connection_ctl(pvr_dev);
-+ if (err)
-+ goto err_free_fw_core_data_obj;
-+
-+ return 0;
-+
-+err_free_fw_core_data_obj:
-+ if (fw_core_data_ptr) {
-+ pvr_fw_object_vunmap(pvr_dev->fw_core_data_obj, fw_core_data_ptr, false);
-+ pvr_fw_object_release(pvr_dev->fw_core_data_obj);
-+ }
-+
-+err_free_fw_core_code_obj:
-+ if (fw_core_code_ptr) {
-+ pvr_fw_object_vunmap(pvr_dev->fw_core_code_obj, fw_core_code_ptr, false);
-+ pvr_fw_object_release(pvr_dev->fw_core_code_obj);
-+ }
-+
-+err_free_fw_data_obj:
-+ if (fw_data_ptr)
-+ pvr_fw_object_vunmap(pvr_dev->fw_data_obj, fw_data_ptr, false);
-+ pvr_fw_object_release(pvr_dev->fw_data_obj);
-+
-+err_free_fw_code_obj:
-+ if (fw_code_ptr)
-+ pvr_fw_object_vunmap(pvr_dev->fw_code_obj, fw_code_ptr, false);
-+ pvr_fw_object_release(pvr_dev->fw_code_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+pvr_fw_cleanup(struct pvr_device *pvr_dev)
-+{
-+ pvr_fw_fini_fwif_connection_ctl(pvr_dev);
-+
-+ if (pvr_dev->fw_core_code_obj)
-+ pvr_fw_object_release(pvr_dev->fw_core_code_obj);
-+ if (pvr_dev->fw_core_data_obj)
-+ pvr_fw_object_release(pvr_dev->fw_core_data_obj);
-+ pvr_fw_object_release(pvr_dev->fw_code_obj);
-+ pvr_fw_object_release(pvr_dev->fw_data_obj);
-+}
-+
-+/**
-+ * pvr_wait_for_fw_boot() - Wait for firmware to finish booting
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%ETIMEDOUT if firmware fails to boot within timeout.
-+ */
-+int
-+pvr_wait_for_fw_boot(struct pvr_device *pvr_dev)
-+{
-+ ktime_t deadline = ktime_add_us(ktime_get(), FW_BOOT_TIMEOUT_USEC);
-+
-+ while (ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0) {
-+ if (READ_ONCE(pvr_dev->fw_sysinit->firmware_started))
-+ return 0;
-+ }
-+
-+ return -ETIMEDOUT;
-+}
-+
-+/*
-+ * pvr_fw_heap_info_init() - Calculate size and masks for FW heap
-+ * @pvr_dev: Target PowerVR device.
-+ * @log2_size: Log2 of raw heap size.
-+ * @reserved_size: Size of reserved area of heap, in bytes. May be zero.
-+ */
-+void
-+pvr_fw_heap_info_init(struct pvr_device *pvr_dev, u32 log2_size, u32 reserved_size)
-+{
-+ pvr_dev->fw_heap_info.gpu_addr = PVR_ROGUE_FW_MAIN_HEAP_BASE;
-+ pvr_dev->fw_heap_info.log2_size = log2_size;
-+ pvr_dev->fw_heap_info.reserved_size = reserved_size;
-+ pvr_dev->fw_heap_info.raw_size = 1 << pvr_dev->fw_heap_info.log2_size;
-+ pvr_dev->fw_heap_info.offset_mask = pvr_dev->fw_heap_info.raw_size - 1;
-+ pvr_dev->fw_heap_info.config_offset = pvr_dev->fw_heap_info.raw_size -
-+ PVR_ROGUE_FW_CONFIG_HEAP_SIZE;
-+ pvr_dev->fw_heap_info.size = pvr_dev->fw_heap_info.raw_size -
-+ (PVR_ROGUE_FW_CONFIG_HEAP_SIZE + reserved_size);
-+}
-+
-+/**
-+ * pvr_fw_init() - Initialise and boot firmware
-+ * @pvr_dev: Target PowerVR device
-+ *
-+ * On successful completion of the function the PowerVR device will be
-+ * initialised and ready to use.
-+ *
-+ * Returns:
-+ * * 0 on success,
-+ * * -%EINVAL on invalid firmware image,
-+ * * -%ENOMEM on out of memory, or
-+ * * -%ETIMEDOUT if firmware processor fails to boot or on register poll timeout.
-+ */
-+int
-+pvr_fw_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ u32 kccb_size_log2 = ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT;
-+ u32 kccb_rtn_size = (1 << kccb_size_log2) * sizeof(*pvr_dev->kccb_rtn);
-+ u32 ddk_version;
-+ int err;
-+
-+ if (pvr_dev->fw_processor_type == PVR_FW_PROCESSOR_TYPE_META) {
-+ pvr_dev->fw_funcs = &pvr_fw_funcs_meta;
-+ } else if (pvr_dev->fw_processor_type == PVR_FW_PROCESSOR_TYPE_MIPS) {
-+ pvr_dev->fw_funcs = &pvr_fw_funcs_mips;
-+ } else {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ err = pvr_dev->fw_funcs->init(pvr_dev);
-+ if (err)
-+ goto err_out;
-+
-+ drm_mm_init(&pvr_dev->fw_mm, ROGUE_FW_HEAP_BASE, pvr_dev->fw_heap_info.raw_size);
-+ pvr_dev->fw_mm_base = ROGUE_FW_HEAP_BASE;
-+ spin_lock_init(&pvr_dev->fw_mm_lock);
-+
-+ err = pvr_fw_process(pvr_dev);
-+ if (err)
-+ goto err_mm_takedown;
-+
-+ /* Initialise KCCB and FWCCB. */
-+ err = pvr_kccb_init(pvr_dev);
-+ if (err)
-+ goto err_fw_cleanup;
-+
-+ err = pvr_fwccb_init(pvr_dev);
-+ if (err)
-+ goto err_kccb_fini;
-+
-+ /* Allocate memory for KCCB return slots. */
-+ pvr_dev->kccb_rtn = pvr_gem_create_and_map_fw_object(pvr_dev, kccb_rtn_size,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_dev->kccb_rtn_obj);
-+ if (IS_ERR(pvr_dev->kccb_rtn)) {
-+ err = PTR_ERR(pvr_dev->kccb_rtn);
-+ goto err_fwccb_fini;
-+ }
-+
-+ err = pvr_fw_create_os_structures(pvr_dev);
-+ if (err)
-+ goto err_kccb_rtn_release;
-+
-+ err = pvr_fw_create_dev_structures(pvr_dev);
-+ if (err)
-+ goto err_destroy_os_structures;
-+
-+ err = pvr_dev->fw_funcs->start(pvr_dev);
-+ if (err)
-+ goto err_destroy_dev_structures;
-+
-+ err = pvr_wait_for_fw_boot(pvr_dev);
-+ if (err) {
-+ drm_err(drm_dev, "Firmware failed to boot\n");
-+ goto err_fw_stop;
-+ }
-+
-+ pvr_dev->fw_booted = true;
-+
-+ /* Now that firmware has booted, we can get the firmware version. */
-+ ddk_version = pvr_dev->fw_osinit->rogue_comp_checks.ddk_version;
-+ pvr_dev->fw_version.major = ddk_version >> 16;
-+ pvr_dev->fw_version.minor = ddk_version & 0xffff;
-+
-+ return 0;
-+
-+err_fw_stop:
-+ pvr_dev->fw_funcs->stop(pvr_dev);
-+
-+err_destroy_dev_structures:
-+ pvr_fw_destroy_dev_structures(pvr_dev);
-+
-+err_destroy_os_structures:
-+ pvr_fw_destroy_os_structures(pvr_dev);
-+
-+err_kccb_rtn_release:
-+ pvr_fw_object_vunmap(pvr_dev->kccb_rtn_obj, pvr_dev->kccb_rtn, false);
-+ pvr_fw_object_release(pvr_dev->kccb_rtn_obj);
-+
-+err_fwccb_fini:
-+ pvr_ccb_fini(&pvr_dev->fwccb);
-+
-+err_kccb_fini:
-+ pvr_ccb_fini(&pvr_dev->kccb);
-+
-+err_fw_cleanup:
-+ pvr_fw_cleanup(pvr_dev);
-+
-+err_mm_takedown:
-+ drm_mm_takedown(&pvr_dev->fw_mm);
-+
-+ if (pvr_dev->fw_funcs->fini)
-+ pvr_dev->fw_funcs->fini(pvr_dev);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_fw_fini() - Shutdown firmware processor and free associated memory
-+ * @pvr_dev: Target PowerVR device
-+ */
-+void
-+pvr_fw_fini(struct pvr_device *pvr_dev)
-+{
-+ pvr_dev->fw_funcs->stop(pvr_dev);
-+ pvr_dev->fw_booted = false;
-+ pvr_fw_destroy_dev_structures(pvr_dev);
-+ pvr_fw_destroy_os_structures(pvr_dev);
-+ pvr_fw_object_vunmap(pvr_dev->kccb_rtn_obj, (void *)pvr_dev->kccb_rtn, false);
-+ pvr_fw_object_release(pvr_dev->kccb_rtn_obj);
-+ /*
-+ * Ensure FWCCB worker has finished executing before destroying FWCCB. The IRQ handler has
-+ * been unregistered at this point so no new work should be being submitted.
-+ */
-+ flush_work(&pvr_dev->fwccb_work);
-+ pvr_ccb_fini(&pvr_dev->fwccb);
-+ pvr_ccb_fini(&pvr_dev->kccb);
-+ pvr_fw_cleanup(pvr_dev);
-+
-+ drm_mm_takedown(&pvr_dev->fw_mm);
-+
-+ if (pvr_dev->fw_funcs->fini)
-+ pvr_dev->fw_funcs->fini(pvr_dev);
-+}
-+
-+/**
-+ * pvr_fw_mts_schedule() - Schedule work via an MTS kick
-+ * @pvr_dev: Target PowerVR device
-+ * @val: Kick mask. Should be a combination of %ROGUE_CR_MTS_SCHEDULE_*
-+ */
-+void
-+pvr_fw_mts_schedule(struct pvr_device *pvr_dev, u32 val)
-+{
-+ /* Ensure memory is flushed before kicking MTS. */
-+ wmb();
-+
-+ PVR_CR_WRITE32(pvr_dev, MTS_SCHEDULE, val);
-+
-+ /* Ensure the MTS kick goes through before continuing. */
-+ mb();
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h
-new file mode 100644
-index 000000000000..1ee11a8b1d20
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fw.h
-@@ -0,0 +1,163 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_FW_H__
-+#define __PVR_FW_H__
-+
-+#include "pvr_fw_info.h"
-+
-+#include <linux/types.h>
-+
-+/* Forward declaration from pvr_device.h. */
-+struct pvr_device;
-+
-+#define ROGUE_FWIF_FWCCB_NUMCMDS_LOG2 5
-+
-+#define ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT 7
-+
-+/**
-+ * struct pvr_fw_funcs - FW processor function table
-+ */
-+struct pvr_fw_funcs {
-+ /**
-+ * @init:
-+ *
-+ * FW processor specific initialisation.
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This function must call pvr_fw_heap_calculate() to initialise the firmware heap for this
-+ * FW processor.
-+ *
-+ * This function is mandatory.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any appropriate error on failure.
-+ */
-+ int (*init)(struct pvr_device *pvr_dev);
-+
-+ /**
-+ * @fini:
-+ *
-+ * FW processor specific finalisation.
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This function is optional.
-+ */
-+ void (*fini)(struct pvr_device *pvr_dev);
-+
-+ /**
-+ * @fw_process:
-+ *
-+ * Load and process firmware image.
-+ * @pvr_dev: Target PowerVR device.
-+ * @fw: Pointer to firmware image.
-+ * @layout_entries: Layout of firmware memory.
-+ * @num_layout_entries: Number of entries in @layout_entries.
-+ * @fw_code_ptr: Pointer to firmware code section.
-+ * @fw_data_ptr: Pointer to firmware data section.
-+ * @fw_core_code_ptr: Pointer to firmware core code section. May be %NULL.
-+ * @fw_core_data_ptr: Pointer to firmware core data section. May be %NULL.
-+ * @core_code_alloc_size: Total allocation size of core code section.
-+ *
-+ * This function is mandatory.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any appropriate error on failure.
-+ */
-+ int (*fw_process)(struct pvr_device *pvr_dev, const u8 *fw,
-+ const struct pvr_fw_layout_entry *layout_entries, u32 num_layout_entries,
-+ u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr,
-+ u8 *fw_core_data_ptr, u32 core_code_alloc_size);
-+
-+ /**
-+ * @vm_map:
-+ *
-+ * Map FW object into FW processor address space.
-+ * @pvr_dev: Target PowerVR device.
-+ * @fw_obj: FW object to map.
-+ *
-+ * This function is mandatory.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any appropriate error on failure.
-+ */
-+ int (*vm_map)(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj);
-+
-+ /**
-+ * @vm_unmap:
-+ *
-+ * Unmap FW object from FW processor address space.
-+ * @pvr_dev: Target PowerVR device.
-+ * @fw_obj: FW object to map.
-+ *
-+ * This function is mandatory.
-+ */
-+ void (*vm_unmap)(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj);
-+
-+ /**
-+ * @get_fw_addr_with_offset:
-+ *
-+ * Called to get address of object in firmware address space, with offset.
-+ * @fw_obj: Pointer to object.
-+ * @offset: Desired offset from start of object.
-+ *
-+ * This function is mandatory.
-+ *
-+ * Returns:
-+ * * Address in firmware address space.
-+ */
-+ u32 (*get_fw_addr_with_offset)(struct pvr_fw_object *fw_obj, u32 offset);
-+
-+ /**
-+ * @start:
-+ *
-+ * Called to start FW processor and boot firmware.
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This function is mandatory.
-+ *
-+ * Returns:
-+ * * 0 on success.
-+ * * Any appropriate error on failure.
-+ */
-+ int (*start)(struct pvr_device *pvr_dev);
-+
-+ /**
-+ * @stop:
-+ *
-+ * Called to stop FW processor execution.
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This function is mandatory.
-+ *
-+ * Returns:
-+ * * 0 on success.
-+ * * Any appropriate error on failure.
-+ */
-+ int (*stop)(struct pvr_device *pvr_dev);
-+};
-+
-+extern const struct pvr_fw_funcs pvr_fw_funcs_meta;
-+extern const struct pvr_fw_funcs pvr_fw_funcs_mips;
-+
-+int pvr_fw_init(struct pvr_device *pvr_dev);
-+void pvr_fw_fini(struct pvr_device *pvr_dev);
-+
-+void pvr_fw_mts_schedule(struct pvr_device *pvr_dev, u32 val);
-+
-+void
-+pvr_fw_heap_info_init(struct pvr_device *pvr_dev, u32 log2_size, u32 reserved_size);
-+
-+const struct pvr_fw_layout_entry *
-+pvr_fw_find_layout_entry(const struct pvr_fw_layout_entry *layout_entries, u32 num_layout_entries,
-+ enum pvr_fw_section_id id);
-+int
-+pvr_fw_find_mmu_segment(u32 addr, u32 size, const struct pvr_fw_layout_entry *layout_entries,
-+ u32 num_layout_entries, void *fw_code_ptr, void *fw_data_ptr,
-+ void *fw_core_code_ptr, void *fw_core_data_ptr,
-+ void **host_addr_out);
-+
-+#endif /* __PVR_FW_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_fw_info.h b/drivers/gpu/drm/imagination/pvr_fw_info.h
-new file mode 100644
-index 000000000000..2f2a6ffe61b9
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fw_info.h
-@@ -0,0 +1,106 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_FW_INFO_H__
-+#define __PVR_FW_INFO_H__
-+
-+#include <linux/sizes.h>
-+#include <linux/types.h>
-+
-+/*
-+ * Firmware binary block unit in bytes.
-+ * Raw data stored in FW binary will be aligned to this size.
-+ */
-+#define FW_BLOCK_SIZE SZ_4K
-+
-+/* Maximum number of entries in firmware layout table. */
-+#define PVR_FW_INFO_MAX_NUM_ENTRIES 8
-+
-+enum pvr_fw_section_id {
-+ META_CODE = 0,
-+ META_PRIVATE_DATA,
-+ META_COREMEM_CODE,
-+ META_COREMEM_DATA,
-+ MIPS_CODE,
-+ MIPS_EXCEPTIONS_CODE,
-+ MIPS_BOOT_CODE,
-+ MIPS_PRIVATE_DATA,
-+ MIPS_BOOT_DATA,
-+ MIPS_STACK,
-+ RISCV_UNCACHED_CODE,
-+ RISCV_CACHED_CODE,
-+ RISCV_PRIVATE_DATA,
-+ RISCV_COREMEM_CODE,
-+ RISCV_COREMEM_DATA,
-+};
-+
-+enum pvr_fw_section_type {
-+ NONE = 0,
-+ FW_CODE,
-+ FW_DATA,
-+ FW_COREMEM_CODE,
-+ FW_COREMEM_DATA,
-+};
-+
-+/*
-+ * FW binary format with FW info attached:
-+ *
-+ * Contents Offset
-+ * +-----------------+
-+ * | | 0
-+ * | |
-+ * | Original binary |
-+ * | file |
-+ * | (.ldr/.elf) |
-+ * | |
-+ * | |
-+ * +-----------------+
-+ * | FW info header | FILE_SIZE - 4K
-+ * +-----------------+
-+ * | |
-+ * | FW layout table |
-+ * | |
-+ * +-----------------+
-+ * FILE_SIZE
-+ */
-+
-+#define PVR_FW_INFO_VERSION 1
-+
-+/** struct pvr_fw_info_header - Firmware header */
-+struct pvr_fw_info_header {
-+ /** @info_version: FW info header version. */
-+ u32 info_version;
-+ /** @header_len: Header length. */
-+ u32 header_len;
-+ /** @layout_entry_num: Number of entries in the layout table. */
-+ u32 layout_entry_num;
-+ /** @layout_entry_size: Size of an entry in the layout table. */
-+ u32 layout_entry_size;
-+ /** @bvnc: FW version number. */
-+ aligned_u64 bvnc;
-+ /** @fw_page_size: Page size of processor on which firmware executes. */
-+ u32 fw_page_size;
-+ /** @flags: Compatibility flags. */
-+ u32 flags;
-+};
-+
-+/**
-+ * struct pvr_fw_layout_entry - Entry in firmware layout table, describing a
-+ * section of the firmware image
-+ */
-+struct pvr_fw_layout_entry {
-+ /** @id: Section ID. */
-+ enum pvr_fw_section_id id;
-+ /** @type: Section type. */
-+ enum pvr_fw_section_type type;
-+ /** @base_addr: Base address of section in FW address space. */
-+ u32 base_addr;
-+ /** @max_size: Maximum size of section, in bytes. */
-+ u32 max_size;
-+ /** @alloc_size: Allocation size of section, in bytes. */
-+ u32 alloc_size;
-+ /** @alloc_offset: Allocation offset of section. */
-+ u32 alloc_offset;
-+};
-+
-+#endif /* __PVR_FW_INFO_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c
-new file mode 100644
-index 000000000000..63a29b0cb686
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c
-@@ -0,0 +1,834 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_fw.h"
-+#include "pvr_fw_info.h"
-+#include "pvr_gem.h"
-+#include "pvr_rogue_cr_defs.h"
-+#include "pvr_rogue_meta.h"
-+
-+#include <linux/compiler.h>
-+#include <linux/delay.h>
-+#include <linux/firmware.h>
-+#include <linux/ktime.h>
-+#include <linux/types.h>
-+
-+#define ROGUE_FW_HEAP_META_SHIFT 25 /* 32 MB */
-+
-+#define POLL_TIMEOUT_USEC 1000000
-+
-+/**
-+ * pvr_meta_cr_read32() - Read a META register via the Slave Port
-+ * @pvr_dev: Device pointer.
-+ * @reg_addr: Address of register to read.
-+ * @reg_value_out: Pointer to location to store register value.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_cr_poll_reg32().
-+ */
-+static int
-+pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out)
-+{
-+ int err;
-+
-+ /* Wait for Slave Port to be Ready. */
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1,
-+ ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
-+ ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
-+ ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
-+ ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ /* Issue a Read. */
-+ PVR_CR_WRITE32(pvr_dev, META_SP_MSLVCTRL0,
-+ reg_addr | ROGUE_CR_META_SP_MSLVCTRL0_RD_EN);
-+ (void)PVR_CR_READ32(pvr_dev, META_SP_MSLVCTRL0); /* Fence write. */
-+
-+ /* Wait for Slave Port to be Ready. */
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1,
-+ ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
-+ ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
-+ ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
-+ ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ *reg_value_out = PVR_CR_READ32(pvr_dev, META_SP_MSLVDATAX);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+rogue_meta_proc_wrapper_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ u64 garten_config;
-+
-+ /* Set Garten IDLE to META idle and Set the Garten Wrapper BIF Fence address. */
-+
-+ /* Garten IDLE bit controlled by META. */
-+ garten_config = ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META;
-+
-+ /* The fence addr is set during the fw init sequence. */
-+
-+ /* Set PC = 0 for fences. */
-+ garten_config &=
-+ ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_CLRMSK;
-+ garten_config |=
-+ (u64)MMU_CONTEXT_MAPPING_FWPRIV
-+ << ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT;
-+
-+ /* Set SLC DM=META. */
-+ garten_config |= ((u64)ROGUE_FW_SEGMMU_META_BIFDM_ID)
-+ << ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT;
-+
-+ drm_info(drm_dev, "Configure META wrapper");
-+ PVR_CR_WRITE64(pvr_dev, MTS_GARTEN_WRAPPER_CONFIG, garten_config);
-+}
-+
-+static void
-+rogue_axi_ace_list_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+
-+ /* Setup AXI-ACE config. Set everything to outer cache. */
-+ u64 reg_val =
-+ (3U
-+ << ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_SHIFT) |
-+ (3U
-+ << ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_SHIFT) |
-+ (2U
-+ << ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_SHIFT) |
-+ (2U
-+ << ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_SHIFT) |
-+ (2U
-+ << ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_SHIFT) |
-+ (2U
-+ << ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_SHIFT) |
-+ (2U
-+ << ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_SHIFT) |
-+ (2U
-+ << ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_SHIFT);
-+
-+ drm_info(drm_dev, "Init AXI-ACE interface");
-+ PVR_CR_WRITE64(pvr_dev, AXI_ACE_LITE_CONFIGURATION, reg_val);
-+}
-+
-+static void
-+rogue_bif_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ dma_addr_t pc_dma_addr;
-+ u64 pc_addr;
-+
-+ /* Acquire the address of the Kernel Page Catalogue. */
-+ pc_dma_addr = pvr_vm_get_page_catalogue_addr(pvr_dev->kernel_vm_ctx);
-+
-+ /* Write the kernel catalogue base. */
-+ drm_info(drm_dev, "Rogue firmware MMU Page Catalogue");
-+
-+ pc_addr = ((((u64)pc_dma_addr >> ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSHIFT)
-+ << ROGUE_CR_BIF_CAT_BASE0_ADDR_SHIFT) &
-+ ~ROGUE_CR_BIF_CAT_BASE0_ADDR_CLRMSK);
-+
-+ __pvr_cr_write64(pvr_dev, BIF_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV),
-+ pc_addr);
-+}
-+
-+static int
-+rogue_slc_init(struct pvr_device *pvr_dev)
-+{
-+ u16 slc_cache_line_size_in_bits;
-+ u32 reg_val;
-+ int err;
-+
-+ /*
-+ * SLC Misc control.
-+ *
-+ * Note: This is a 64bit register and we set only the lower 32bits
-+ * leaving the top 32bits (ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS)
-+ * unchanged from the HW default.
-+ */
-+ reg_val = (PVR_CR_READ32(pvr_dev, SLC_CTRL_MISC) &
-+ ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_EN) |
-+ ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH1;
-+
-+ err = PVR_FEATURE_VALUE(pvr_dev, slc_cache_line_size_in_bits,
-+ &slc_cache_line_size_in_bits);
-+ if (err)
-+ return err;
-+
-+ /* Bypass burst combiner if SLC line size is smaller than 1024 bits. */
-+ if (slc_cache_line_size_in_bits < 1024)
-+ reg_val |= ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_EN;
-+
-+ PVR_CR_WRITE32(pvr_dev, SLC_CTRL_MISC, reg_val);
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_meta_start() - Start META processor and boot firmware
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Returns:
-+ * * 0 on success.
-+ */
-+static int
-+pvr_meta_start(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ int err;
-+
-+ /* Set Rogue in soft-reset. */
-+ drm_info(drm_dev, "%s: soft reset everything", __func__);
-+ PVR_CR_WRITE64(pvr_dev, SOFT_RESET, ROGUE_CR_SOFT_RESET_MASKFULL);
-+
-+ /* Read soft-reset to fence previous write in order to clear the SOCIF pipeline. */
-+ (void)PVR_CR_READ64(pvr_dev, SOFT_RESET);
-+
-+ /* Take Rascal and Dust out of reset. */
-+ drm_info(drm_dev, "%s: Rascal and Dust out of reset", __func__);
-+ PVR_CR_WRITE64(pvr_dev, SOFT_RESET,
-+ ROGUE_CR_SOFT_RESET_MASKFULL ^
-+ ROGUE_CR_SOFT_RESET_RASCALDUSTS_EN);
-+
-+ (void)PVR_CR_READ64(pvr_dev, SOFT_RESET);
-+
-+ /* Take everything out of reset but the FW processor. */
-+ drm_info(drm_dev, "%s: Take everything out of reset but META", __func__);
-+ PVR_CR_WRITE64(pvr_dev, SOFT_RESET, ROGUE_CR_SOFT_RESET_GARTEN_EN);
-+
-+ (void)PVR_CR_READ64(pvr_dev, SOFT_RESET);
-+
-+ err = rogue_slc_init(pvr_dev);
-+ if (err)
-+ goto err_reset;
-+
-+ /* Configure META to Master boot */
-+ drm_info(drm_dev, "%s: META Master boot", __func__);
-+ PVR_CR_WRITE64(pvr_dev, META_BOOT, ROGUE_CR_META_BOOT_MODE_EN);
-+
-+ /* Initialise Firmware wrapper. */
-+ rogue_meta_proc_wrapper_init(pvr_dev);
-+
-+ /* We must init the AXI-ACE interface before first BIF transaction. */
-+ rogue_axi_ace_list_init(pvr_dev);
-+
-+ /* Initialise BIF. */
-+ rogue_bif_init(pvr_dev);
-+
-+ drm_info(drm_dev, "%s: Take META out of reset", __func__);
-+
-+ /* Need to wait for at least 16 cycles before taking the FW processor out of reset ... */
-+ udelay(3);
-+
-+ PVR_CR_WRITE64(pvr_dev, SOFT_RESET, 0x0);
-+ (void)PVR_CR_READ64(pvr_dev, SOFT_RESET);
-+
-+ /* ... and afterwards. */
-+ udelay(3);
-+
-+ return 0;
-+
-+err_reset:
-+ /* Put everything back into soft-reset. */
-+ PVR_CR_WRITE64(pvr_dev, SOFT_RESET, ROGUE_CR_SOFT_RESET_MASKFULL);
-+
-+ return err;
-+}
-+
-+/**
-+ * pvr_meta_stop() - Stop META processor
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_cr_poll_reg32().
-+ */
-+static int
-+pvr_meta_stop(struct pvr_device *pvr_dev)
-+{
-+ const u32 jones_sidekick_idle_mask = ROGUE_CR_JONES_IDLE_MASKFULL &
-+ ~(ROGUE_CR_JONES_IDLE_GARTEN_EN |
-+ ROGUE_CR_JONES_IDLE_SOCIF_EN |
-+ ROGUE_CR_JONES_IDLE_HOSTIF_EN);
-+ u32 reg_value;
-+ int err;
-+
-+ /*
-+ * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.
-+ * For LAYOUT_MARS = 1, SIDEKICK would have been powered down by FW.
-+ */
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_JONES_IDLE,
-+ jones_sidekick_idle_mask,
-+ jones_sidekick_idle_mask,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ /* Unset MTS DM association with threads. */
-+ PVR_CR_WRITE32(pvr_dev, MTS_INTCTX_THREAD0_DM_ASSOC,
-+ ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_MASKFULL &
-+ ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK);
-+ PVR_CR_WRITE32(pvr_dev, MTS_BGCTX_THREAD0_DM_ASSOC,
-+ ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL &
-+ ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK);
-+ PVR_CR_WRITE32(pvr_dev, MTS_INTCTX_THREAD1_DM_ASSOC,
-+ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL &
-+ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
-+ PVR_CR_WRITE32(pvr_dev, MTS_BGCTX_THREAD1_DM_ASSOC,
-+ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL &
-+ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
-+
-+ /* Extra Idle checks. */
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0,
-+ ROGUE_CR_BIF_STATUS_MMU_MASKFULL,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIFPM_STATUS_MMU, 0,
-+ ROGUE_CR_BIFPM_STATUS_MMU_MASKFULL,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIFPM_READS_EXT_STATUS, 0,
-+ ROGUE_CR_BIFPM_READS_EXT_STATUS_MASKFULL,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ err = pvr_cr_poll_reg64(pvr_dev, ROGUE_CR_SLC_STATUS1, 0,
-+ ROGUE_CR_SLC_STATUS1_MASKFULL,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ /*
-+ * Wait for SLC to signal IDLE.
-+ * For LAYOUT_MARS = 1, SLC would have been powered down by FW.
-+ */
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE,
-+ ROGUE_CR_SLC_IDLE_MASKFULL,
-+ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ /*
-+ * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.
-+ * For LAYOUT_MARS = 1, SIDEKICK would have been powered down by FW.
-+ */
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
-+ jones_sidekick_idle_mask,
-+ jones_sidekick_idle_mask,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+
-+ err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value);
-+ if (err)
-+ goto err_out;
-+
-+ if (!reg_value) {
-+ /*
-+ * Wait for Sidekick/Jones to signal IDLE including the Garten
-+ * Wrapper if there is no debugger attached (TxVECINT_BHALT =
-+ * 0x0).
-+ */
-+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
-+ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
-+ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
-+ POLL_TIMEOUT_USEC);
-+ if (err)
-+ goto err_out;
-+ }
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static __always_inline void
-+add_boot_arg(u32 **boot_conf, u32 param, u32 data)
-+{
-+ *(*boot_conf)++ = param;
-+ *(*boot_conf)++ = data;
-+}
-+
-+static int
-+meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
-+ struct rogue_meta_ldr_l1_data_blk *l1_data,
-+ u32 coremem_size,
-+ const struct pvr_fw_layout_entry *layout_entries,
-+ u32 num_layout_entries, u8 *fw_code_ptr, u8 *fw_data_ptr,
-+ u8 *fw_core_code_ptr, u8 *fw_core_data_ptr,
-+ const u32 fw_size)
-+{
-+ struct rogue_meta_ldr_l2_data_blk *l2_block =
-+ (struct rogue_meta_ldr_l2_data_blk *)(fw +
-+ l1_data->cmd_data[1]);
-+ u32 offset = l1_data->cmd_data[0];
-+ u32 data_size;
-+ void *write_addr;
-+ int err;
-+
-+ /* Verify header is within bounds. */
-+ if (((u8 *)l2_block - fw) >= fw_size || ((u8 *)(l2_block + 1) - fw) >= fw_size) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ data_size = l2_block->length - 6 /* L2 Tag length and checksum */;
-+
-+ /* Verify data is within bounds. */
-+ if (((u8 *)l2_block->block_data - fw) >= fw_size ||
-+ ((((u8 *)l2_block->block_data) + data_size) - fw) >= fw_size) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if (!ROGUE_META_IS_COREMEM_CODE(offset, coremem_size) &&
-+ !ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
-+ /* Global range is aliased to local range */
-+ offset &= ~META_MEM_GLOBAL_RANGE_BIT;
-+ }
-+
-+ err = pvr_fw_find_mmu_segment(offset, data_size, layout_entries,
-+ num_layout_entries, fw_code_ptr, fw_data_ptr,
-+ fw_core_code_ptr, fw_core_data_ptr, &write_addr);
-+ if (err) {
-+ drm_err(drm_dev,
-+ "Addr 0x%x (size: %d) not found in any firmware segment",
-+ offset, data_size);
-+ goto err_out;
-+ }
-+
-+ memcpy(write_addr, l2_block->block_data, data_size);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
-+ struct rogue_meta_ldr_l1_data_blk *l1_data,
-+ u32 coremem_size,
-+ const struct pvr_fw_layout_entry *layout_entries,
-+ u32 num_layout_entries, u8 *fw_code_ptr, u8 *fw_data_ptr,
-+ u8 *fw_core_code_ptr, u8 *fw_core_data_ptr)
-+{
-+ u32 offset = l1_data->cmd_data[0];
-+ u32 byte_count = l1_data->cmd_data[1];
-+ void *write_addr;
-+ int err;
-+
-+ if (ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
-+ /* cannot zero coremem directly */
-+ return 0;
-+ }
-+
-+ /* Global range is aliased to local range */
-+ offset &= ~META_MEM_GLOBAL_RANGE_BIT;
-+
-+ err = pvr_fw_find_mmu_segment(offset, byte_count, layout_entries,
-+ num_layout_entries, fw_code_ptr, fw_data_ptr,
-+ fw_core_code_ptr, fw_core_data_ptr, &write_addr);
-+ if (err) {
-+ drm_err(drm_dev,
-+ "Addr 0x%x (size: %d) not found in any firmware segment",
-+ offset, byte_count);
-+ goto err_out;
-+ }
-+
-+ memset(write_addr, 0, byte_count);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
-+ struct rogue_meta_ldr_l1_data_blk *l1_data,
-+ const u32 fw_size, u32 **boot_conf_ptr)
-+{
-+ struct rogue_meta_ldr_l2_data_blk *l2_block =
-+ (struct rogue_meta_ldr_l2_data_blk *)(fw +
-+ l1_data->cmd_data[0]);
-+ struct rogue_meta_ldr_cfg_blk *config_command;
-+ u32 l2_block_size;
-+ u32 curr_block_size = 0;
-+ u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL;
-+ int err;
-+
-+ /* Verify block header is within bounds. */
-+ if (((u8 *)l2_block - fw) >= fw_size || ((u8 *)(l2_block + 1) - fw) >= fw_size) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ l2_block_size = l2_block->length - 6 /* L2 Tag length and checksum */;
-+ config_command = (struct rogue_meta_ldr_cfg_blk *)l2_block->block_data;
-+
-+ if (((u8 *)config_command - fw) >= fw_size ||
-+ ((((u8 *)config_command) + l2_block_size) - fw) >= fw_size) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ while (l2_block_size >= 12) {
-+ if (config_command->type != ROGUE_META_LDR_CFG_WRITE) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ /*
-+ * Only write to bootloader if we got a valid pointer to the FW
-+ * code allocation.
-+ */
-+ if (boot_conf) {
-+ u32 register_offset = config_command->block_data[0];
-+ u32 register_value = config_command->block_data[1];
-+
-+ /* Do register write */
-+ add_boot_arg(&boot_conf, register_offset,
-+ register_value);
-+ }
-+
-+ curr_block_size = 12;
-+ l2_block_size -= curr_block_size;
-+ config_command = (struct rogue_meta_ldr_cfg_blk
-+ *)((uintptr_t)config_command +
-+ curr_block_size);
-+ }
-+
-+ if (boot_conf_ptr)
-+ *boot_conf_ptr = boot_conf;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * process_ldr_command_stream() - Process LDR firmware image and populate
-+ * firmware sections
-+ * @pvr_dev: Device pointer.
-+ * @fw: Pointer to firmware image.
-+ * @layout_entries: Pointer to layout table.
-+ * @num_layout_entries: Number of entries in layout table.
-+ * @fw_code_ptr: Pointer to FW code section.
-+ * @fw_data_ptr: Pointer to FW data section.
-+ * @fw_core_code_ptr: Pointer to FW coremem code section.
-+ * @fw_core_data_ptr: Pointer to FW coremem data section.
-+ * @boot_conf_ptr: Pointer to boot config argument pointer.
-+ *
-+ * Returns :
-+ * * 0 on success, or
-+ * * -EINVAL on any error in LDR command stream.
-+ */
-+static int
-+process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw,
-+ const struct pvr_fw_layout_entry *layout_entries,
-+ u32 num_layout_entries, u8 *fw_code_ptr,
-+ u8 *fw_data_ptr, u8 *fw_core_code_ptr,
-+ u8 *fw_core_data_ptr, u32 **boot_conf_ptr)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct rogue_meta_ldr_block_hdr *ldr_header =
-+ (struct rogue_meta_ldr_block_hdr *)fw;
-+ struct rogue_meta_ldr_l1_data_blk *l1_data =
-+ (struct rogue_meta_ldr_l1_data_blk *)(fw + ldr_header->sl_data);
-+ const u32 fw_size = pvr_dev->fw->size;
-+ int err;
-+
-+ u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL;
-+ u32 coremem_size;
-+
-+ err = PVR_FEATURE_VALUE(pvr_dev, meta_coremem_size, &coremem_size);
-+ if (err)
-+ goto err_out;
-+
-+ coremem_size *= SZ_1K;
-+
-+ while (l1_data) {
-+ /* Verify block header is within bounds. */
-+ if (((u8 *)l1_data - fw) >= fw_size || ((u8 *)(l1_data + 1) - fw) >= fw_size) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if (ROGUE_META_LDR_BLK_IS_COMMENT(l1_data->cmd)) {
-+ /* Don't process comment blocks */
-+ goto next_block;
-+ }
-+
-+ switch (l1_data->cmd & ROGUE_META_LDR_CMD_MASK)
-+ case ROGUE_META_LDR_CMD_LOADMEM: {
-+ err = meta_ldr_cmd_loadmem(drm_dev, fw, l1_data,
-+ coremem_size, layout_entries,
-+ num_layout_entries,
-+ fw_code_ptr, fw_data_ptr,
-+ fw_core_code_ptr,
-+ fw_core_data_ptr, fw_size);
-+ if (err)
-+ goto err_out;
-+ break;
-+
-+ case ROGUE_META_LDR_CMD_START_THREADS:
-+ /* Don't process this block */
-+ break;
-+
-+ case ROGUE_META_LDR_CMD_ZEROMEM:
-+ err = meta_ldr_cmd_zeromem(drm_dev, l1_data,
-+ coremem_size, layout_entries,
-+ num_layout_entries,
-+ fw_code_ptr, fw_data_ptr,
-+ fw_core_code_ptr,
-+ fw_core_data_ptr);
-+ break;
-+
-+ case ROGUE_META_LDR_CMD_CONFIG:
-+ err = meta_ldr_cmd_config(drm_dev, fw, l1_data, fw_size,
-+ &boot_conf);
-+ break;
-+
-+ default:
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+next_block:
-+ if (l1_data->next == 0xFFFFFFFF)
-+ break;
-+
-+ l1_data = (struct rogue_meta_ldr_l1_data_blk *)(fw +
-+ l1_data->next);
-+ }
-+
-+ if (boot_conf_ptr)
-+ *boot_conf_ptr = boot_conf;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+configure_seg_id(u64 seg_out_addr, u32 seg_base, u32 seg_limit, u32 seg_id,
-+ u32 **boot_conf_ptr)
-+{
-+ u32 seg_out_addr0 = seg_out_addr & 0x00000000FFFFFFFFUL;
-+ u32 seg_out_addr1 = (seg_out_addr >> 32) & 0x00000000FFFFFFFFUL;
-+ u32 *boot_conf = *boot_conf_ptr;
-+
-+ /* META segments have a minimum size. */
-+ u32 limit_off = max(seg_limit, ROGUE_FW_SEGMMU_ALIGN);
-+
-+ /* The limit is an offset, therefore off = size - 1. */
-+ limit_off -= 1;
-+
-+ seg_base |= ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE;
-+
-+ add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENTn_BASE(seg_id), seg_base);
-+ add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENTn_LIMIT(seg_id),
-+ limit_off);
-+ add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENTn_OUTA0(seg_id),
-+ seg_out_addr0);
-+ add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENTn_OUTA1(seg_id),
-+ seg_out_addr1);
-+
-+ *boot_conf_ptr = boot_conf;
-+}
-+
-+static void
-+configure_seg_mmu(struct pvr_device *pvr_dev,
-+ const struct pvr_fw_layout_entry *layout_entries,
-+ u32 num_layout_entries, u32 **boot_conf_ptr)
-+{
-+ u64 seg_out_addr_top;
-+ u32 i;
-+
-+ seg_out_addr_top =
-+ ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWPRIV,
-+ ROGUE_FW_SEGMMU_META_BIFDM_ID);
-+
-+ for (i = 0; i < num_layout_entries; i++) {
-+ /*
-+ * FW code is using the bootloader segment which is already
-+ * configured on boot. FW coremem code and data don't use the
-+ * segment MMU. Only the FW data segment needs to be configured.
-+ */
-+ if (layout_entries[i].type == FW_DATA) {
-+ u32 seg_id = ROGUE_FW_SEGMMU_DATA_ID;
-+ u64 seg_out_addr;
-+
-+ WARN_ON(!pvr_gem_get_fw_gpu_addr(pvr_dev->fw_data_obj,
-+ &seg_out_addr));
-+ seg_out_addr += layout_entries[i].alloc_offset;
-+ seg_out_addr |= seg_out_addr_top;
-+
-+ /* Write the sequence to the bootldr. */
-+ configure_seg_id(seg_out_addr,
-+ layout_entries[i].base_addr,
-+ layout_entries[i].alloc_size, seg_id,
-+ boot_conf_ptr);
-+
-+ break;
-+ }
-+ }
-+}
-+
-+static void
-+configure_meta_caches(u32 **boot_conf_ptr)
-+{
-+ u32 *boot_conf = *boot_conf_ptr;
-+ u32 d_cache_t0, i_cache_t0;
-+ u32 d_cache_t1, i_cache_t1;
-+ u32 d_cache_t2, i_cache_t2;
-+ u32 d_cache_t3, i_cache_t3;
-+
-+ /* Initialise I/Dcache settings */
-+ d_cache_t0 = d_cache_t1 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
-+ d_cache_t2 = d_cache_t3 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
-+ i_cache_t0 = i_cache_t1 = i_cache_t2 = i_cache_t3 = 0;
-+
-+ d_cache_t0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
-+ i_cache_t0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
-+
-+ /* Local region MMU enhanced bypass: WIN-3 mode for code and data caches */
-+ add_boot_arg(&boot_conf, META_CR_MMCU_LOCAL_EBCTRL,
-+ META_CR_MMCU_LOCAL_EBCTRL_ICWIN |
-+ META_CR_MMCU_LOCAL_EBCTRL_DCWIN);
-+
-+ /* Data cache partitioning thread 0 to 3 */
-+ add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(0), d_cache_t0);
-+ add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(1), d_cache_t1);
-+ add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(2), d_cache_t2);
-+ add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(3), d_cache_t3);
-+
-+ /* Enable data cache hits */
-+ add_boot_arg(&boot_conf, META_CR_MMCU_DCACHE_CTRL,
-+ META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN);
-+
-+ /* Instruction cache partitioning thread 0 to 3 */
-+ add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(0), i_cache_t0);
-+ add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(1), i_cache_t1);
-+ add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(2), i_cache_t2);
-+ add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(3), i_cache_t3);
-+
-+ /* Enable instruction cache hits */
-+ add_boot_arg(&boot_conf, META_CR_MMCU_ICACHE_CTRL,
-+ META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN);
-+
-+ add_boot_arg(&boot_conf, 0x040000C0, 0);
-+
-+ *boot_conf_ptr = boot_conf;
-+}
-+
-+static int
-+pvr_meta_fw_process(struct pvr_device *pvr_dev, const u8 *fw,
-+ const struct pvr_fw_layout_entry *layout_entries, u32 num_layout_entries,
-+ u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr,
-+ u32 core_code_alloc_size)
-+{
-+ u32 *boot_conf;
-+ int err;
-+
-+ boot_conf = ((u32 *)fw_code_ptr) + ROGUE_FW_BOOTLDR_CONF_OFFSET;
-+
-+ /* Slave port and JTAG accesses are privileged. */
-+ add_boot_arg(&boot_conf, META_CR_SYSC_JTAG_THREAD,
-+ META_CR_SYSC_JTAG_THREAD_PRIV_EN);
-+
-+ configure_seg_mmu(pvr_dev, layout_entries, num_layout_entries, &boot_conf);
-+
-+ /* Populate FW sections from LDR image. */
-+ err = process_ldr_command_stream(pvr_dev, fw, layout_entries, num_layout_entries,
-+ fw_code_ptr, fw_data_ptr, fw_core_code_ptr,
-+ fw_core_data_ptr, &boot_conf);
-+ if (err)
-+ goto err_out;
-+
-+ configure_meta_caches(&boot_conf);
-+
-+ /* End argument list. */
-+ add_boot_arg(&boot_conf, 0, 0);
-+
-+ if (pvr_dev->fw_core_code_obj) {
-+ u32 core_code_fw_addr;
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_dev->fw_core_code_obj, &core_code_fw_addr));
-+ add_boot_arg(&boot_conf, core_code_fw_addr, core_code_alloc_size);
-+ } else {
-+ add_boot_arg(&boot_conf, 0, 0);
-+ }
-+ /* None of the cores supported by this driver have META DMA. */
-+ add_boot_arg(&boot_conf, 0, 0);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_meta_init(struct pvr_device *pvr_dev)
-+{
-+ pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_META_SHIFT, 0);
-+
-+ return 0;
-+}
-+
-+static u32
-+pvr_meta_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
-+{
-+ u32 fw_addr = fw_obj->fw_addr_offset + offset + ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS;
-+
-+ /* META cacheability is determined by address. */
-+ if (fw_obj->base.flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
-+ fw_addr |= ROGUE_FW_SEGMMU_DATA_META_UNCACHED |
-+ ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED;
-+
-+ return fw_addr;
-+}
-+
-+static int
-+pvr_meta_vm_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
-+{
-+ struct pvr_gem_object *pvr_obj = from_pvr_fw_object(fw_obj);
-+
-+ return pvr_vm_map(pvr_dev->kernel_vm_ctx, pvr_obj, fw_obj->fw_mm_node.start);
-+}
-+
-+static void
-+pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
-+{
-+ pvr_vm_unmap(pvr_dev->kernel_vm_ctx, fw_obj->fw_mm_node.start);
-+}
-+
-+const struct pvr_fw_funcs pvr_fw_funcs_meta = {
-+ .init = pvr_meta_init,
-+ .fw_process = pvr_meta_fw_process,
-+ .vm_map = pvr_meta_vm_map,
-+ .vm_unmap = pvr_meta_vm_unmap,
-+ .get_fw_addr_with_offset = pvr_meta_get_fw_addr_with_offset,
-+ .start = pvr_meta_start,
-+ .stop = pvr_meta_stop,
-+};
-diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/imagination/pvr_fw_mips.c
-new file mode 100644
-index 000000000000..2aca0d6ab09f
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c
-@@ -0,0 +1,185 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_fw.h"
-+#include "pvr_fw_mips.h"
-+#include "pvr_gem.h"
-+#include "pvr_rogue_mips.h"
-+#include "pvr_vm_mips.h"
-+
-+#include <linux/elf.h>
-+#include <linux/err.h>
-+#include <linux/types.h>
-+
-+#define ROGUE_FW_HEAP_MIPS_BASE 0xC0000000
-+#define ROGUE_FW_HEAP_MIPS_SHIFT 24 /* 16 MB */
-+#define ROGUE_FW_HEAP_MIPS_RESERVED_SIZE SZ_1M
-+
-+/**
-+ * process_elf_command_stream() - Process ELF firmware image and populate
-+ * firmware sections
-+ * @pvr_dev: Device pointer.
-+ * @fw: Pointer to firmware image.
-+ * @layout_entries: Pointer to layout table.
-+ * @num_layout_entries: Number of entries in layout table.
-+ * @fw_code_ptr: Pointer to FW code section.
-+ * @fw_data_ptr: Pointer to FW data section.
-+ * @fw_core_code_ptr: Pointer to FW coremem code section.
-+ * @fw_core_data_ptr: Pointer to FW coremem data section.
-+ *
-+ * Returns :
-+ * * 0 on success, or
-+ * * -EINVAL on any error in ELF command stream.
-+ */
-+static int
-+process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw,
-+ const struct pvr_fw_layout_entry *layout_entries,
-+ u32 num_layout_entries, u8 *fw_code_ptr,
-+ u8 *fw_data_ptr, u8 *fw_core_code_ptr,
-+ u8 *fw_core_data_ptr)
-+{
-+ struct elf32_hdr *header = (struct elf32_hdr *)fw;
-+ struct elf32_phdr *program_header = (struct elf32_phdr *)(fw + header->e_phoff);
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ u32 entry;
-+ int err;
-+
-+ for (entry = 0; entry < header->e_phnum; entry++, program_header++) {
-+ void *write_addr;
-+
-+ /* Only consider loadable entries in the ELF segment table */
-+ if (program_header->p_type != PT_LOAD)
-+ continue;
-+
-+ err = pvr_fw_find_mmu_segment(program_header->p_vaddr, program_header->p_memsz,
-+ layout_entries, num_layout_entries, fw_code_ptr, fw_data_ptr,
-+ fw_core_code_ptr, fw_core_data_ptr, &write_addr);
-+ if (err) {
-+ drm_err(drm_dev,
-+ "Addr 0x%x (size: %d) not found in any firmware segment",
-+ program_header->p_vaddr, program_header->p_memsz);
-+ goto err_out;
-+ }
-+
-+ /* Write to FW allocation only if available */
-+ if (write_addr) {
-+ memcpy(write_addr, fw + program_header->p_offset,
-+ program_header->p_filesz);
-+
-+ memset((u8 *)write_addr + program_header->p_filesz, 0,
-+ program_header->p_memsz - program_header->p_filesz);
-+ }
-+ }
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_mips_init(struct pvr_device *pvr_dev)
-+{
-+ pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_MIPS_SHIFT, ROGUE_FW_HEAP_MIPS_RESERVED_SIZE);
-+
-+ return pvr_vm_mips_init(pvr_dev);
-+}
-+
-+static void
-+pvr_mips_fini(struct pvr_device *pvr_dev)
-+{
-+ pvr_vm_mips_fini(pvr_dev);
-+}
-+
-+static int
-+pvr_mips_fw_process(struct pvr_device *pvr_dev, const u8 *fw,
-+ const struct pvr_fw_layout_entry *layout_entries, u32 num_layout_entries,
-+ u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr,
-+ u32 core_code_alloc_size)
-+{
-+ struct pvr_fw_mips_data *mips_data = pvr_dev->fw_data.mips_data;
-+ const struct pvr_fw_layout_entry *boot_data_entry;
-+ const struct pvr_fw_layout_entry *stack_entry;
-+ struct rogue_mipsfw_boot_data *boot_data;
-+ dma_addr_t dma_addr;
-+ u32 page_nr;
-+ int err;
-+
-+ err = process_elf_command_stream(pvr_dev, fw, layout_entries, num_layout_entries,
-+ fw_code_ptr, fw_data_ptr, fw_core_code_ptr,
-+ fw_core_data_ptr);
-+ if (err)
-+ goto err_out;
-+
-+ boot_data_entry = pvr_fw_find_layout_entry(layout_entries, num_layout_entries,
-+ MIPS_BOOT_DATA);
-+ if (!boot_data_entry) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ stack_entry = pvr_fw_find_layout_entry(layout_entries, num_layout_entries, MIPS_STACK);
-+ if (!stack_entry) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ boot_data = (struct rogue_mipsfw_boot_data *)(fw_data_ptr + boot_data_entry->alloc_offset +
-+ ROGUE_MIPSFW_BOOTLDR_CONF_OFFSET);
-+
-+ WARN_ON(pvr_fw_get_dma_addr(pvr_dev->fw_data_obj, stack_entry->alloc_offset, &dma_addr));
-+ boot_data->stack_phys_addr = dma_addr;
-+
-+ boot_data->reg_base = pvr_dev->regs_resource->start;
-+
-+ for (page_nr = 0; page_nr < ARRAY_SIZE(boot_data->pt_phys_addr); page_nr++) {
-+ WARN_ON(pvr_gem_get_dma_addr(mips_data->pt_obj,
-+ page_nr << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K, &dma_addr));
-+
-+ boot_data->pt_phys_addr[page_nr] = dma_addr;
-+ }
-+
-+ boot_data->pt_log2_page_size = ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
-+ boot_data->pt_num_pages = ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES;
-+ boot_data->reserved1 = 0;
-+ boot_data->reserved2 = 0;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_mips_start(struct pvr_device *pvr_dev)
-+{
-+ return -ENODEV;
-+}
-+
-+static int
-+pvr_mips_stop(struct pvr_device *pvr_dev)
-+{
-+ return -ENODEV;
-+}
-+
-+static u32
-+pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
-+{
-+ struct pvr_device *pvr_dev = fw_obj->base.pvr_dev;
-+
-+ /* MIPS cacheability is determined by page table. */
-+ return ((fw_obj->fw_addr_offset + offset) & pvr_dev->fw_heap_info.offset_mask) |
-+ ROGUE_FW_HEAP_MIPS_BASE;
-+}
-+
-+const struct pvr_fw_funcs pvr_fw_funcs_mips = {
-+ .init = pvr_mips_init,
-+ .fini = pvr_mips_fini,
-+ .fw_process = pvr_mips_fw_process,
-+ .vm_map = pvr_vm_mips_map,
-+ .vm_unmap = pvr_vm_mips_unmap,
-+ .get_fw_addr_with_offset = pvr_mips_get_fw_addr_with_offset,
-+ .start = pvr_mips_start,
-+ .stop = pvr_mips_stop,
-+};
-diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.h b/drivers/gpu/drm/imagination/pvr_fw_mips.h
-new file mode 100644
-index 000000000000..2a2ca7618b18
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fw_mips.h
-@@ -0,0 +1,29 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_FW_MIPS_H__
-+#define __PVR_FW_MIPS_H__
-+
-+#include <linux/types.h>
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_gem_object;
-+
-+/**
-+ * struct pvr_fw_mips_data - MIPS-specific data
-+ */
-+struct pvr_fw_mips_data {
-+ /** @pt_obj: Object representing MIPS pagetable. */
-+ struct pvr_gem_object *pt_obj;
-+
-+ /** @pt: Pointer to CPU mapping of MIPS pagetable. */
-+ u32 *pt;
-+
-+ /** @cache_policy: Cache policy for this processor. */
-+ u32 cache_policy;
-+
-+ /** @pfn_mask: PFN mask for MIPS pagetable. */
-+ u32 pfn_mask;
-+};
-+
-+#endif /* __PVR_FW_MIPS_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_fw_trace.c b/drivers/gpu/drm/imagination/pvr_fw_trace.c
-new file mode 100644
-index 000000000000..21b1f242aa03
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fw_trace.c
-@@ -0,0 +1,487 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_gem.h"
-+#include "pvr_rogue_fwif.h"
-+#include "pvr_rogue_fwif_sf.h"
-+#include "pvr_fw_trace.h"
-+
-+#include <drm/drm_file.h>
-+#include <linux/sysfs.h>
-+#include <linux/types.h>
-+
-+/*
-+ * The tuple pairs that will be generated using XMacros will be stored here.
-+ * This macro definition must match the definition of rogue_fw_log_sfids in
-+ * pvr_rogue_fwif_sf.h.
-+ */
-+static const struct rogue_km_stid_fmt stid_fmts[] = {
-+#define X(a, b, c, d, e) { ROGUE_FW_LOG_CREATESFID(a, b, e), d },
-+ ROGUE_FW_LOG_SFIDLIST
-+#undef X
-+};
-+
-+int pvr_fw_trace_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct pvr_fw_trace *fw_trace = &pvr_dev->fw_trace;
-+ u32 thread_nr;
-+ int err;
-+
-+ fw_trace->tracebuf_ctrl = pvr_gem_create_and_map_fw_object(pvr_dev,
-+ sizeof(*fw_trace->tracebuf_ctrl), PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED, &fw_trace->tracebuf_ctrl_obj);
-+ if (IS_ERR(fw_trace->tracebuf_ctrl)) {
-+ drm_err(drm_dev, "Unable to allocate trace buffer control structure\n");
-+ err = PTR_ERR(fw_trace->tracebuf_ctrl);
-+ goto err_out;
-+ }
-+
-+ BUILD_BUG_ON(ARRAY_SIZE(fw_trace->tracebuf_ctrl->tracebuf) !=
-+ ARRAY_SIZE(fw_trace->buffers));
-+
-+ for (thread_nr = 0; thread_nr < ARRAY_SIZE(fw_trace->buffers); thread_nr++) {
-+ struct rogue_fwif_tracebuf_space *tracebuf_space =
-+ &fw_trace->tracebuf_ctrl->tracebuf[thread_nr];
-+ struct pvr_fw_trace_buffer *trace_buffer = &fw_trace->buffers[thread_nr];
-+
-+ trace_buffer->buf = pvr_gem_create_and_map_fw_object(pvr_dev,
-+ ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS * sizeof(*trace_buffer->buf),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &trace_buffer->buf_obj);
-+ if (IS_ERR(trace_buffer->buf)) {
-+ drm_err(drm_dev, "Unable to allocate trace buffer\n");
-+ err = PTR_ERR(trace_buffer->buf);
-+ trace_buffer->buf = NULL;
-+ goto err_free_buf;
-+ }
-+ trace_buffer->tracebuf_space = tracebuf_space;
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(trace_buffer->buf_obj,
-+ &tracebuf_space->trace_buffer_fw_addr));
-+
-+ tracebuf_space->trace_buffer = trace_buffer->buf;
-+ tracebuf_space->trace_pointer = 0;
-+ }
-+
-+ fw_trace->tracebuf_ctrl->tracebuf_size_in_dwords =
-+ ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS;
-+ fw_trace->tracebuf_ctrl->tracebuf_flags = 0;
-+
-+ if (pvr_fw_trace_enable) {
-+ fw_trace->group_mask = ROGUE_FWIF_LOG_TYPE_GROUP_MASK;
-+ fw_trace->tracebuf_ctrl->log_type = ROGUE_FWIF_LOG_TYPE_TRACE |
-+ fw_trace->group_mask;
-+ } else {
-+ fw_trace->group_mask = 0;
-+ fw_trace->tracebuf_ctrl->log_type = ROGUE_FWIF_LOG_TYPE_NONE;
-+ }
-+
-+ return 0;
-+
-+err_free_buf:
-+ for (thread_nr = 0; thread_nr < ARRAY_SIZE(fw_trace->buffers); thread_nr++) {
-+ struct pvr_fw_trace_buffer *trace_buffer = &fw_trace->buffers[thread_nr];
-+
-+ if (trace_buffer->buf) {
-+ pvr_fw_object_vunmap(trace_buffer->buf_obj, trace_buffer->buf, false);
-+ pvr_fw_object_release(trace_buffer->buf_obj);
-+ }
-+ }
-+
-+ pvr_fw_object_vunmap(fw_trace->tracebuf_ctrl_obj, fw_trace->tracebuf_ctrl, false);
-+ pvr_fw_object_release(fw_trace->tracebuf_ctrl_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+void pvr_fw_trace_fini(struct pvr_device *pvr_dev)
-+{
-+ struct pvr_fw_trace *fw_trace = &pvr_dev->fw_trace;
-+ u32 thread_nr;
-+
-+ for (thread_nr = 0; thread_nr < ARRAY_SIZE(fw_trace->buffers); thread_nr++) {
-+ struct pvr_fw_trace_buffer *trace_buffer = &fw_trace->buffers[thread_nr];
-+
-+ pvr_fw_object_vunmap(trace_buffer->buf_obj, trace_buffer->buf, false);
-+ pvr_fw_object_release(trace_buffer->buf_obj);
-+ }
-+ pvr_fw_object_vunmap(fw_trace->tracebuf_ctrl_obj, fw_trace->tracebuf_ctrl, false);
-+ pvr_fw_object_release(fw_trace->tracebuf_ctrl_obj);
-+}
-+
-+/**
-+ * update_logtype() - Send KCCB command to trigger FW to update logtype
-+ * @pvr_dev: Target PowerVR device
-+ * @group_mask: New log group mask.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_kccb_send_cmd().
-+ */
-+static int
-+update_logtype(struct pvr_device *pvr_dev, u32 group_mask)
-+{
-+ struct pvr_fw_trace *fw_trace = &pvr_dev->fw_trace;
-+ struct rogue_fwif_kccb_cmd cmd;
-+
-+ if (group_mask)
-+ fw_trace->tracebuf_ctrl->log_type = ROGUE_FWIF_LOG_TYPE_TRACE | group_mask;
-+ else
-+ fw_trace->tracebuf_ctrl->log_type = ROGUE_FWIF_LOG_TYPE_NONE;
-+
-+ cmd.cmd_type = ROGUE_FWIF_KCCB_CMD_LOGTYPE_UPDATE;
-+ cmd.kccb_flags = 0;
-+
-+ return pvr_kccb_send_cmd(pvr_dev, &cmd, NULL);
-+}
-+
-+static int fw_trace_group_mask_show(struct seq_file *m, void *data)
-+{
-+ struct pvr_device *pvr_dev = m->private;
-+
-+ seq_printf(m, "%08x\n", pvr_dev->fw_trace.group_mask);
-+
-+ return 0;
-+}
-+
-+static int fw_trace_group_mask_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, fw_trace_group_mask_show, inode->i_private);
-+}
-+
-+static ssize_t fw_trace_group_mask_write(struct file *file, const char __user *ubuf, size_t len,
-+ loff_t *offp)
-+{
-+ struct seq_file *m = file->private_data;
-+ struct pvr_device *pvr_dev = m->private;
-+ u32 new_group_mask;
-+ int err;
-+
-+ err = kstrtouint_from_user(ubuf, len, 0, &new_group_mask);
-+ if (err)
-+ goto err_out;
-+
-+ err = update_logtype(pvr_dev, new_group_mask);
-+ if (err)
-+ goto err_out;
-+
-+ pvr_dev->fw_trace.group_mask = new_group_mask;
-+
-+err_out:
-+ return err ? err : len;
-+}
-+
-+
-+static const struct file_operations pvr_fw_trace_group_mask_fops = {
-+ .owner = THIS_MODULE,
-+ .open = fw_trace_group_mask_open,
-+ .read = seq_read,
-+ .write = fw_trace_group_mask_write,
-+ .llseek = default_llseek,
-+ .release = single_release,
-+};
-+
-+struct pvr_fw_trace_seq_data {
-+ /** @buffer: Pointer to copy of trace data. */
-+ u32 *buffer;
-+
-+ /** @start_offset: Starting offset in trace data, as reported by FW. */
-+ u32 start_offset;
-+
-+ /** @idx: Current index into trace data. */
-+ u32 idx;
-+
-+ /** @assert_buf: Trace assert buffer, as reported by FW. */
-+ struct rogue_fwif_file_info_buf assert_buf;
-+};
-+
-+static u32 find_sfid(u32 id)
-+{
-+ u32 i;
-+
-+ for (i = 0; i < ARRAY_SIZE(stid_fmts); i++) {
-+ if (stid_fmts[i].id == id)
-+ return i;
-+ }
-+
-+ return ROGUE_FW_SF_LAST;
-+}
-+
-+static u32 read_fw_trace(struct pvr_fw_trace_seq_data *trace_seq_data, u32 offset)
-+{
-+ u32 idx;
-+
-+ idx = trace_seq_data->idx + offset;
-+ if (idx >= ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS)
-+ return 0;
-+
-+ idx = (idx + trace_seq_data->start_offset) % ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS;
-+ return trace_seq_data->buffer[idx];
-+}
-+
-+/**
-+ * fw_trace_get_next() - Advance trace index to next entry
-+ * @trace_seq_data: Trace sequence data.
-+ *
-+ * Returns:
-+ * * %true if trace index is now pointing to a valid entry, or
-+ * * %false if trace index is pointing to an invalid entry, or has hit the end
-+ * of the trace.
-+ */
-+static bool fw_trace_get_next(struct pvr_fw_trace_seq_data *trace_seq_data)
-+{
-+ u32 id, sf_id;
-+
-+ while (trace_seq_data->idx < ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS) {
-+ id = read_fw_trace(trace_seq_data, 0);
-+ trace_seq_data->idx++;
-+ if (!ROGUE_FW_LOG_VALIDID(id))
-+ continue;
-+ if (id == ROGUE_FW_SF_MAIN_ASSERT_FAILED) {
-+ /* Assertion failure marks the end of the trace. */
-+ return false;
-+ }
-+
-+ sf_id = find_sfid(id);
-+ if (sf_id == ROGUE_FW_SF_FIRST)
-+ continue;
-+ if (sf_id == ROGUE_FW_SF_LAST) {
-+ /*
-+ * Could not match with an ID in the SF table, trace is
-+ * most likely corrupt from this point.
-+ */
-+ return false;
-+ }
-+
-+ /* Skip over the timestamp, and any parameters. */
-+ trace_seq_data->idx += 2 + ROGUE_FW_SF_PARAMNUM(id);
-+
-+ /* Ensure index is now pointing to a valid trace entry. */
-+ id = read_fw_trace(trace_seq_data, 0);
-+ if (!ROGUE_FW_LOG_VALIDID(id))
-+ continue;
-+
-+ return true;
-+ };
-+
-+ /* Hit end of trace data. */
-+ return false;
-+}
-+
-+/**
-+ * fw_trace_get_first() - Find first valid entry in trace
-+ * @trace_seq_data: Trace sequence data.
-+ *
-+ * Skips over invalid (usually zero) and ROGUE_FW_SF_FIRST entries.
-+ *
-+ * If the trace has no valid entries, this function will exit with the trace
-+ * index pointing to the end of the trace. trace_seq_show() will return an error
-+ * in this state.
-+ */
-+static void fw_trace_get_first(struct pvr_fw_trace_seq_data *trace_seq_data)
-+{
-+ trace_seq_data->idx = 0;
-+
-+ while (trace_seq_data->idx < ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS) {
-+ u32 id = read_fw_trace(trace_seq_data, 0);
-+
-+ if (ROGUE_FW_LOG_VALIDID(id)) {
-+ u32 sf_id = find_sfid(id);
-+
-+ if (sf_id != ROGUE_FW_SF_FIRST)
-+ break;
-+ }
-+ trace_seq_data->idx++;
-+ }
-+}
-+
-+static void *fw_trace_seq_start(struct seq_file *s, loff_t *pos)
-+{
-+ struct pvr_fw_trace_seq_data *trace_seq_data = s->private;
-+ u32 i;
-+
-+ /* Reset trace index, then advance to *pos. */
-+ fw_trace_get_first(trace_seq_data);
-+
-+ for (i = 0; i < *pos; i++) {
-+ if (!fw_trace_get_next(trace_seq_data))
-+ return NULL;
-+ }
-+
-+ return (trace_seq_data->idx < ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS) ? pos : NULL;
-+}
-+
-+static void *fw_trace_seq_next(struct seq_file *s, void *v, loff_t *pos)
-+{
-+ struct pvr_fw_trace_seq_data *trace_seq_data = s->private;
-+
-+ (*pos)++;
-+ if (!fw_trace_get_next(trace_seq_data))
-+ return NULL;
-+
-+ return (trace_seq_data->idx < ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS) ? pos : NULL;
-+}
-+
-+static void fw_trace_seq_stop(struct seq_file *s, void *v)
-+{
-+}
-+
-+static int fw_trace_seq_show(struct seq_file *s, void *v)
-+{
-+ struct pvr_fw_trace_seq_data *trace_seq_data = s->private;
-+ u64 timestamp;
-+ u32 id;
-+ u32 sf_id;
-+ int err;
-+
-+ if (trace_seq_data->idx >= ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ id = read_fw_trace(trace_seq_data, 0);
-+ if (!ROGUE_FW_LOG_VALIDID(id)) {
-+ /* Index is not pointing at a valid entry. */
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ sf_id = find_sfid(id);
-+ if (sf_id == ROGUE_FW_SF_LAST) {
-+ /* Index is not pointing at a valid entry. */
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ timestamp = read_fw_trace(trace_seq_data, 1) |
-+ ((u64)read_fw_trace(trace_seq_data, 2) << 32);
-+ timestamp = (timestamp & ~ROGUE_FWT_TIMESTAMP_TIME_CLRMSK) >>
-+ ROGUE_FWT_TIMESTAMP_TIME_SHIFT;
-+
-+ seq_printf(s, "[%llu] : ", timestamp);
-+ if (id == ROGUE_FW_SF_MAIN_ASSERT_FAILED) {
-+ seq_printf(s, "ASSERTION %s failed at %s:%u",
-+ trace_seq_data->assert_buf.info,
-+ trace_seq_data->assert_buf.path,
-+ trace_seq_data->assert_buf.line_num);
-+ } else {
-+ seq_printf(s, stid_fmts[sf_id].name,
-+ read_fw_trace(trace_seq_data, 3),
-+ read_fw_trace(trace_seq_data, 4),
-+ read_fw_trace(trace_seq_data, 5),
-+ read_fw_trace(trace_seq_data, 6),
-+ read_fw_trace(trace_seq_data, 7),
-+ read_fw_trace(trace_seq_data, 8),
-+ read_fw_trace(trace_seq_data, 9),
-+ read_fw_trace(trace_seq_data, 10),
-+ read_fw_trace(trace_seq_data, 11),
-+ read_fw_trace(trace_seq_data, 12),
-+ read_fw_trace(trace_seq_data, 13),
-+ read_fw_trace(trace_seq_data, 14),
-+ read_fw_trace(trace_seq_data, 15),
-+ read_fw_trace(trace_seq_data, 16),
-+ read_fw_trace(trace_seq_data, 17),
-+ read_fw_trace(trace_seq_data, 18),
-+ read_fw_trace(trace_seq_data, 19),
-+ read_fw_trace(trace_seq_data, 20),
-+ read_fw_trace(trace_seq_data, 21),
-+ read_fw_trace(trace_seq_data, 22));
-+ }
-+ seq_puts(s, "\n");
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static const struct seq_operations pvr_fw_trace_seq_ops = {
-+ .start = fw_trace_seq_start,
-+ .next = fw_trace_seq_next,
-+ .stop = fw_trace_seq_stop,
-+ .show = fw_trace_seq_show
-+};
-+
-+static int fw_trace_open(struct inode *inode, struct file *file)
-+{
-+ struct pvr_fw_trace_buffer *trace_buffer = inode->i_private;
-+ struct rogue_fwif_tracebuf_space *tracebuf_space =
-+ trace_buffer->tracebuf_space;
-+ struct pvr_fw_trace_seq_data *trace_seq_data;
-+ int err;
-+
-+ trace_seq_data = kzalloc(sizeof(*trace_seq_data), GFP_KERNEL);
-+ if (!trace_seq_data)
-+ goto err_out;
-+
-+ trace_seq_data->buffer = kcalloc(ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS,
-+ sizeof(*trace_seq_data->buffer), GFP_KERNEL);
-+ if (!trace_seq_data->buffer)
-+ goto err_free_data;
-+
-+ /*
-+ * Take a local copy of the trace buffer, as firmware may still be
-+ * writing to it. This will exist as long as this file is open.
-+ */
-+ memcpy(trace_seq_data->buffer, trace_buffer->buf,
-+ ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS * sizeof(u32));
-+ trace_seq_data->start_offset = READ_ONCE(tracebuf_space->trace_pointer);
-+ trace_seq_data->assert_buf = tracebuf_space->assert_buf;
-+ fw_trace_get_first(trace_seq_data);
-+
-+ err = seq_open(file, &pvr_fw_trace_seq_ops);
-+ if (err)
-+ goto err_free_buffer;
-+
-+ ((struct seq_file *)file->private_data)->private = trace_seq_data;
-+
-+ return 0;
-+
-+err_free_buffer:
-+ kfree(trace_seq_data->buffer);
-+
-+err_free_data:
-+ kfree(trace_seq_data);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int fw_trace_release(struct inode *inode, struct file *file)
-+{
-+ struct pvr_fw_trace_seq_data *trace_seq_data =
-+ ((struct seq_file *)file->private_data)->private;
-+
-+ seq_release(inode, file);
-+ kfree(trace_seq_data->buffer);
-+ kfree(trace_seq_data);
-+
-+ return 0;
-+}
-+
-+static const struct file_operations pvr_fw_trace_fops = {
-+ .owner = THIS_MODULE,
-+ .open = fw_trace_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = fw_trace_release,
-+};
-+
-+void pvr_fw_trace_debugfs_init(struct drm_minor *minor)
-+{
-+ struct pvr_device *pvr_dev = to_pvr_device(minor->dev);
-+ u32 thread_nr;
-+
-+ for (thread_nr = 0; thread_nr < ARRAY_SIZE(pvr_dev->fw_trace.buffers); thread_nr++) {
-+ char fn[14];
-+
-+ sprintf(fn, "pvr_fw_trace%u", thread_nr);
-+ debugfs_create_file(fn, 0444, minor->debugfs_root,
-+ &pvr_dev->fw_trace.buffers[thread_nr], &pvr_fw_trace_fops);
-+ }
-+
-+ debugfs_create_file("pvr_fw_trace_group_mask", 0644, minor->debugfs_root, pvr_dev,
-+ &pvr_fw_trace_group_mask_fops);
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_fw_trace.h b/drivers/gpu/drm/imagination/pvr_fw_trace.h
-new file mode 100644
-index 000000000000..d9c79ff27f4e
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_fw_trace.h
-@@ -0,0 +1,70 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_FW_TRACE_H__
-+#define __PVR_FW_TRACE_H__
-+
-+#include <drm/drm_file.h>
-+#include <linux/types.h>
-+
-+/* Forward declaration from pvr_device.h. */
-+struct pvr_device;
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_fw_object;
-+
-+/* Forward declarations from pvr_rogue_fwif.h */
-+struct rogue_fwif_tracebuf;
-+struct rogue_fwif_tracebuf_space;
-+
-+/**
-+ * struct pvr_fw_trace_buffer - Structure representing a trace buffer
-+ */
-+struct pvr_fw_trace_buffer {
-+ /** @buf_obj: FW buffer object representing trace buffer. */
-+ struct pvr_fw_object *buf_obj;
-+
-+ /** @buf: Pointer to CPU mapping of trace buffer. */
-+ u32 *buf;
-+
-+ /**
-+ * @tracebuf_space: Pointer to FW tracebuf_space structure for this
-+ * trace buffer.
-+ */
-+ struct rogue_fwif_tracebuf_space *tracebuf_space;
-+};
-+
-+/**
-+ * struct pvr_fw_trace - Device firmware trace data
-+ */
-+struct pvr_fw_trace {
-+ /**
-+ * @tracebuf_ctrl_obj: Object representing FW trace buffer control
-+ * structure.
-+ */
-+ struct pvr_fw_object *tracebuf_ctrl_obj;
-+
-+ /**
-+ * @tracebuf_ctrl: Pointer to CPU mapping of FW trace buffer control
-+ * structure.
-+ */
-+ struct rogue_fwif_tracebuf *tracebuf_ctrl;
-+
-+ /**
-+ * @buffers: Array representing the actual trace buffers owned by this
-+ * device.
-+ */
-+ struct pvr_fw_trace_buffer buffers[ROGUE_FW_THREAD_NUM];
-+
-+ /** @group_mask: Mask of enabled trace groups. */
-+ u32 group_mask;
-+};
-+
-+extern bool pvr_fw_trace_enable;
-+
-+int pvr_fw_trace_init(struct pvr_device *pvr_dev);
-+void pvr_fw_trace_fini(struct pvr_device *pvr_dev);
-+
-+void pvr_fw_trace_debugfs_init(struct drm_minor *minor);
-+
-+#endif /* __PVR_FW_TRACE_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_gem.c b/drivers/gpu/drm/imagination/pvr_gem.c
-new file mode 100644
-index 000000000000..5a6b3d31f33d
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_gem.c
-@@ -0,0 +1,1082 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_gem.h"
-+#include "pvr_rogue_meta.h"
-+#include "pvr_vm.h"
-+#include "pvr_vm_mips.h"
-+
-+#include <drm/drm_gem.h>
-+#include <drm/drm_prime.h>
-+
-+#include <linux/compiler.h>
-+#include <linux/compiler_attributes.h>
-+#include <linux/dma-buf.h>
-+#include <linux/dma-direction.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/err.h>
-+#include <linux/gfp.h>
-+#include <linux/log2.h>
-+#include <linux/mutex.h>
-+#include <linux/pagemap.h>
-+#include <linux/refcount.h>
-+#include <linux/scatterlist.h>
-+
-+static vm_fault_t pvr_gem_vm_fault(struct vm_fault *vmf)
-+{
-+ struct vm_area_struct *vma = vmf->vma;
-+ struct drm_gem_object *gem_obj = vma->vm_private_data;
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+ loff_t num_pages = gem_obj->size >> PAGE_SHIFT;
-+ pgoff_t page_offset;
-+ struct page *page;
-+ vm_fault_t ret;
-+
-+ /* We don't use vmf->pgoff since that has the fake offset */
-+ page_offset = (vmf->address - vma->vm_start) >> PAGE_SHIFT;
-+
-+ if (page_offset >= num_pages || WARN_ON_ONCE(!pvr_obj->pages)) {
-+ ret = VM_FAULT_SIGBUS;
-+ } else {
-+ page = pvr_obj->pages[page_offset];
-+
-+ ret = vmf_insert_page(vma, vmf->address, page);
-+ }
-+
-+ return ret;
-+}
-+
-+static void pvr_gem_vm_open(struct vm_area_struct *vma)
-+{
-+ struct drm_gem_object *gem_obj = vma->vm_private_data;
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+ int err;
-+
-+ WARN_ON(gem_obj->import_attach);
-+
-+ err = pvr_gem_object_get_pages(pvr_obj);
-+ WARN_ON(err);
-+
-+ drm_gem_vm_open(vma);
-+}
-+
-+static void pvr_gem_vm_close(struct vm_area_struct *vma)
-+{
-+ struct drm_gem_object *gem_obj = vma->vm_private_data;
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+
-+ pvr_gem_object_put_pages(pvr_obj);
-+ drm_gem_vm_close(vma);
-+}
-+
-+static const struct vm_operations_struct pvr_gem_vm_ops = {
-+ .fault = pvr_gem_vm_fault,
-+ .open = pvr_gem_vm_open,
-+ .close = pvr_gem_vm_close,
-+};
-+
-+static void pvr_gem_free_object(struct drm_gem_object *gem_obj)
-+{
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+
-+ if (gem_obj->import_attach)
-+ drm_prime_gem_destroy(gem_obj, pvr_obj->sgt);
-+ drm_gem_object_release(gem_obj);
-+ kfree(pvr_obj);
-+}
-+
-+static struct sg_table *pvr_gem_get_sg_table(struct drm_gem_object *gem_obj)
-+{
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+
-+ if (gem_obj->import_attach)
-+ return ERR_PTR(-EINVAL);
-+
-+ return drm_prime_pages_to_sg(gem_obj->dev, pvr_obj->pages, gem_obj->size >> PAGE_SHIFT);
-+}
-+
-+static int pvr_gem_mmap(struct drm_gem_object *gem_obj, struct vm_area_struct *vma)
-+{
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+ int err;
-+
-+ if (gem_obj->import_attach) {
-+ /* Drop the reference drm_gem_mmap_obj() acquired.*/
-+ drm_gem_object_put(gem_obj);
-+ vma->vm_private_data = NULL;
-+
-+ return dma_buf_mmap(gem_obj->dma_buf, vma, 0);
-+ }
-+
-+ if (!(pvr_obj->flags & DRM_PVR_BO_CPU_ALLOW_USERSPACE_ACCESS)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ err = pvr_gem_object_get_pages(pvr_obj);
-+ if (err)
-+ goto err_out;
-+
-+ vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
-+ vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
-+ if (!(pvr_obj->flags & PVR_BO_CPU_CACHED))
-+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int pvr_gem_pin(struct drm_gem_object *gem_obj)
-+{
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+
-+ WARN_ON(gem_obj->import_attach);
-+
-+ return pvr_gem_object_get_pages(pvr_obj);
-+}
-+
-+static void pvr_gem_unpin(struct drm_gem_object *gem_obj)
-+{
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+
-+ WARN_ON(gem_obj->import_attach);
-+
-+ pvr_gem_object_put_pages(pvr_obj);
-+}
-+
-+static const struct drm_gem_object_funcs pvr_gem_object_funcs = {
-+ .free = pvr_gem_free_object,
-+ .get_sg_table = pvr_gem_get_sg_table,
-+ .mmap = pvr_gem_mmap,
-+ .pin = pvr_gem_pin,
-+ .unpin = pvr_gem_unpin,
-+ .vm_ops = &pvr_gem_vm_ops,
-+};
-+
-+static void pvr_free_fw_object(struct drm_gem_object *gem_obj)
-+{
-+ struct pvr_gem_object *pvr_obj = to_pvr_gem_object(gem_obj);
-+ struct pvr_fw_object *fw_obj = to_pvr_fw_object(pvr_obj);
-+
-+ WARN_ON(gem_obj->import_attach);
-+ drm_gem_object_release(gem_obj);
-+ kfree(fw_obj);
-+}
-+
-+/* FW objects may not be mmap'ed or exported. */
-+static const struct drm_gem_object_funcs pvr_gem_fw_object_funcs = {
-+ .free = pvr_free_fw_object,
-+};
-+
-+/**
-+ * pvr_gem_object_flags_validate() - Verify that a collection of PowerVR GEM
-+ * mapping and/or creation flags form a valid combination.
-+ * @flags: PowerVR GEM mapping/creation flags to validate.
-+ *
-+ * This function explicitly allows kernel-only flags. All ioctl entrypoints
-+ * should do their own validation as well as relying on this function.
-+ *
-+ * Return:
-+ * * %true if @flags contains valid mapping and/or creation flags, or
-+ * * %false otherwise.
-+ */
-+static bool
-+pvr_gem_object_flags_validate(u64 flags)
-+{
-+ static const u64 invalid_combinations[] = {
-+ /*
-+ * Memory flagged as PM/FW-protected cannot be mapped to
-+ * userspace. To make this explicit, we require that the two
-+ * flags allowing each of these respective features are never
-+ * specified together.
-+ */
-+ (DRM_PVR_BO_DEVICE_PM_FW_PROTECT |
-+ DRM_PVR_BO_CPU_ALLOW_USERSPACE_ACCESS),
-+ };
-+
-+ int i;
-+
-+ /*
-+ * Check for bits set in undefined regions. Reserved regions refer to
-+ * options that can only be set by the kernel. These are explicitly
-+ * allowed in most cases, and must be checked specifically in IOCTL
-+ * callback code.
-+ */
-+ if ((flags & PVR_BO_UNDEFINED_MASK) != 0)
-+ return false;
-+
-+ /*
-+ * Check for all combinations of flags marked as invalid in the array
-+ * above.
-+ */
-+ for (i = 0; i < ARRAY_SIZE(invalid_combinations); ++i) {
-+ u64 combo = invalid_combinations[i];
-+
-+ if ((flags & combo) == combo)
-+ return false;
-+ }
-+
-+ return true;
-+}
-+
-+/**
-+ * pvr_gem_object_into_handle() - Convert a reference to an object into a
-+ * userspace-accessible handle.
-+ * @pvr_obj: [IN] Target PowerVR-specific object.
-+ * @pvr_file: [IN] File to associate the handle with.
-+ * @handle: [OUT] Pointer to store the created handle in. Remains unmodified if
-+ * an error is encountered.
-+ *
-+ * If an error is encountered, ownership of @pvr_obj will not have been
-+ * transferred. If this function succeeds, however, further use of @pvr_obj is
-+ * considered undefined behaviour unless another reference to it is explicitly
-+ * held.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error encountered while attempting to allocate a handle on @pvr_file.
-+ */
-+int
-+pvr_gem_object_into_handle(struct pvr_gem_object *pvr_obj,
-+ struct pvr_file *pvr_file, u32 *handle)
-+{
-+ struct drm_gem_object *gem_obj = from_pvr_gem_object(pvr_obj);
-+ struct drm_file *file = from_pvr_file(pvr_file);
-+
-+ u32 new_handle;
-+ int err;
-+
-+ err = drm_gem_handle_create(file, gem_obj, &new_handle);
-+ if (err)
-+ goto err_out;
-+
-+ /*
-+ * Release our reference to @pvr_obj, effectively transferring
-+ * ownership to the handle.
-+ */
-+ pvr_gem_object_put(pvr_obj);
-+
-+ /*
-+ * Do not store the new handle in @handle until no more errors can
-+ * occur.
-+ */
-+ *handle = new_handle;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_gem_object_from_handle() - Obtain a reference to an object from a
-+ * userspace handle.
-+ * @pvr_file: PowerVR-specific file to which @handle is associated.
-+ * @handle: Userspace handle referencing the target object.
-+ *
-+ * On return, @handle always maintains its reference to the requested object
-+ * (if it had one in the first place). If this function succeeds, the returned
-+ * object will hold an additional reference. When the caller is finished with
-+ * the returned object, they should call pvr_gem_object_put() on it to release
-+ * this reference.
-+ *
-+ * Return:
-+ * * A pointer to the requested PowerVR-specific object on success, or
-+ * * %NULL otherwise.
-+ */
-+struct pvr_gem_object *
-+pvr_gem_object_from_handle(struct pvr_file *pvr_file, u32 handle)
-+{
-+ struct drm_file *file = from_pvr_file(pvr_file);
-+ struct drm_gem_object *gem_obj;
-+
-+ gem_obj = drm_gem_object_lookup(file, handle);
-+ if (!gem_obj)
-+ return NULL;
-+
-+ return to_pvr_gem_object(gem_obj);
-+}
-+
-+static int
-+pvr_gem_object_get_pages_locked(struct pvr_gem_object *pvr_obj)
-+{
-+ struct drm_gem_object *obj = from_pvr_gem_object(pvr_obj);
-+ struct page **pages;
-+ struct sg_table *sgt;
-+ int err;
-+
-+ lockdep_assert_held(&pvr_obj->lock);
-+
-+ if (obj->import_attach) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if ((++pvr_obj->pages_ref_count) == 1) {
-+ WARN_ON(pvr_obj->pages);
-+
-+ pages = drm_gem_get_pages(obj);
-+ if (IS_ERR(pages)) {
-+ err = PTR_ERR(pages);
-+ goto err_dec_ref_count;
-+ }
-+
-+ sgt = drm_prime_pages_to_sg(obj->dev, pages,
-+ obj->size >> PAGE_SHIFT);
-+ if (IS_ERR(sgt)) {
-+ err = PTR_ERR(sgt);
-+ goto err_put_pages;
-+ }
-+
-+ err = dma_map_sgtable(obj->dev->dev, sgt, DMA_BIDIRECTIONAL, 0);
-+ if (err)
-+ goto err_free_sgt;
-+
-+ pvr_obj->pages = pages;
-+ pvr_obj->sgt = sgt;
-+ } else {
-+ WARN_ON(!pvr_obj->pages);
-+ }
-+
-+ return 0;
-+
-+err_free_sgt:
-+ sg_free_table(sgt);
-+ kfree(sgt);
-+
-+err_put_pages:
-+ drm_gem_put_pages(obj, pages, false, false);
-+
-+err_dec_ref_count:
-+ pvr_obj->pages_ref_count--;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_gem_object_get_pages: Get pages associated with a &struct pvr_gem_object
-+ * @pvr_obj: Target object
-+ *
-+ * This will fill out the pages array of the object. This must be called before
-+ * the object is mapped to userspace.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error returned by drm_gem_get_pages(), or
-+ * * Any error returned by drm_prime_pages_to_sg(), or
-+ * * Any error returned by dma_map_sgtable().
-+ */
-+int
-+pvr_gem_object_get_pages(struct pvr_gem_object *pvr_obj)
-+{
-+ int err;
-+
-+ mutex_lock(&pvr_obj->lock);
-+ err = pvr_gem_object_get_pages_locked(pvr_obj);
-+ mutex_unlock(&pvr_obj->lock);
-+
-+ return err;
-+}
-+
-+static void
-+pvr_gem_object_put_pages_locked(struct pvr_gem_object *pvr_obj)
-+{
-+ struct drm_gem_object *gem_obj = from_pvr_gem_object(pvr_obj);
-+
-+ lockdep_assert_held(&pvr_obj->lock);
-+
-+ if (gem_obj->import_attach)
-+ return;
-+
-+ if (pvr_obj->pages && (--pvr_obj->pages_ref_count) == 0) {
-+ sg_free_table(pvr_obj->sgt);
-+ kfree(pvr_obj->sgt);
-+ drm_gem_put_pages(gem_obj, pvr_obj->pages, true, true);
-+ pvr_obj->sgt = NULL;
-+ pvr_obj->pages = NULL;
-+ }
-+}
-+
-+/**
-+ * pvr_gem_object_put_pages: Release pages associated with a &struct
-+ * pvr_gem_object
-+ * @pvr_obj: Target object
-+ */
-+void
-+pvr_gem_object_put_pages(struct pvr_gem_object *pvr_obj)
-+{
-+ mutex_lock(&pvr_obj->lock);
-+ pvr_gem_object_put_pages_locked(pvr_obj);
-+ mutex_unlock(&pvr_obj->lock);
-+}
-+
-+/**
-+ * pvr_gem_object_vmap_prot() - Map a PowerVR GEM object into CPU virtual
-+ * address space without using information from the object's flags.
-+ * @pvr_obj: Target PowerVR GEM object.
-+ * @sync_to_cpu: Specifies whether the buffer should be synced to the CPU
-+ * immediately after mapping.
-+ * @prot: Page protection options for the mapping.
-+ *
-+ * Once the caller is finished with the CPU mapping, they must call
-+ * pvr_gem_object_vunmap() on @pvr_obj.
-+ *
-+ * Unlike pvr_gem_object_vmap(), this function does NOT use information from
-+ * the flags on @pvr_obj to determine page protection options. You probably
-+ * want to use pvr_gem_object_vmap() instead. If you really need to use this
-+ * function, be absolutely sure that @prot is compatible with the flags on
-+ * @pvr_obj. There are no safeguards!
-+ *
-+ * Return:
-+ * * A pointer to the CPU mapping on success,
-+ * * -%ENOMEM if the mapping fails, or
-+ * * Any error encountered while attempting to acquire a reference to the
-+ * backing pages for @pvr_obj.
-+ */
-+static void *
-+pvr_gem_object_vmap_prot(struct pvr_gem_object *pvr_obj, bool sync_to_cpu,
-+ pgprot_t prot)
-+{
-+ struct drm_gem_object *gem_obj = from_pvr_gem_object(pvr_obj);
-+ /* The size of @pvr_obj is always CPU page-aligned. */
-+ size_t nr_pages = pvr_gem_object_size(pvr_obj) >> PAGE_SHIFT;
-+
-+ void *cpu_ptr;
-+
-+ int err;
-+
-+ if (gem_obj->import_attach) {
-+ struct dma_buf_map map;
-+
-+ err = dma_buf_vmap(gem_obj->import_attach->dmabuf, &map);
-+ if (err)
-+ goto err_out;
-+
-+ cpu_ptr = map.vaddr;
-+ } else {
-+ err = pvr_gem_object_get_pages(pvr_obj);
-+ if (err)
-+ goto err_out;
-+
-+ cpu_ptr = vmap(pvr_obj->pages, nr_pages, VM_MAP, prot);
-+ if (!cpu_ptr) {
-+ err = -ENOMEM;
-+ goto err_put_pages;
-+ }
-+ }
-+
-+ /*
-+ * There's no need for sync operations on the CPU cache if we're not
-+ * using the CPU cache.
-+ */
-+ if ((pvr_obj->flags & PVR_BO_CPU_CACHED) && sync_to_cpu) {
-+ struct device *dev = gem_obj->dev->dev;
-+
-+ dma_sync_sgtable_for_cpu(dev, pvr_obj->sgt, DMA_BIDIRECTIONAL);
-+ }
-+
-+ return cpu_ptr;
-+
-+err_put_pages:
-+ pvr_gem_object_put_pages(pvr_obj);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * pvr_gem_object_vmap() - Map a PowerVR GEM object into CPU virtual address
-+ * space.
-+ * @pvr_obj: Target PowerVR GEM object.
-+ * @sync_to_cpu: Specifies whether the buffer should be synced to the CPU
-+ * immediately after mapping.
-+ *
-+ * Once the caller is finished with the CPU mapping, they must call
-+ * pvr_gem_object_vunmap() on @pvr_obj.
-+ *
-+ * If @pvr_obj is not using the CPU cache, @sync_to_cpu is ignored.
-+ *
-+ * Return:
-+ * * A pointer to the CPU mapping on success,
-+ * * -%ENOMEM if the mapping fails, or
-+ * * Any error encountered while attempting to acquire a reference to the
-+ * backing pages for @pvr_obj.
-+ */
-+void *
-+pvr_gem_object_vmap(struct pvr_gem_object *pvr_obj, bool sync_to_cpu)
-+{
-+ pgprot_t prot;
-+
-+ /* Determine parameters from @pvr_obj CPU caching strategy. */
-+ if (pvr_obj->flags & PVR_BO_CPU_CACHED) {
-+ prot = PAGE_KERNEL;
-+ } else {
-+ /* The default caching strategy is write-combined. */
-+ prot = pgprot_writecombine(PAGE_KERNEL);
-+ }
-+
-+ return pvr_gem_object_vmap_prot(pvr_obj, sync_to_cpu, prot);
-+}
-+
-+/**
-+ * pvr_gem_object_vunmap() - Unmap a PowerVR memory object from CPU virtual
-+ * address space.
-+ * @pvr_obj: Target PowerVR GEM object.
-+ * @cpu_ptr: CPU pointer to be unmapped from.
-+ * @sync_to_device: Specifies whether the buffer should be synced to the device
-+ * immediately before unmapping from the CPU.
-+ *
-+ * If @pvr_obj is not using the CPU cache, @sync_to_device is ignored.
-+ */
-+void
-+pvr_gem_object_vunmap(struct pvr_gem_object *pvr_obj, void *cpu_ptr,
-+ bool sync_to_device)
-+{
-+ struct drm_gem_object *gem_obj = from_pvr_gem_object(pvr_obj);
-+
-+ /*
-+ * There's no need for sync operations on the CPU cache if we're not
-+ * using the CPU cache.
-+ */
-+ if ((pvr_obj->flags & PVR_BO_CPU_CACHED) && sync_to_device) {
-+ struct device *dev = gem_obj->dev->dev;
-+
-+ dma_sync_sgtable_for_device(dev, pvr_obj->sgt,
-+ DMA_BIDIRECTIONAL);
-+ }
-+
-+ if (gem_obj->import_attach) {
-+ struct dma_buf_map map = DMA_BUF_MAP_INIT_VADDR(cpu_ptr);
-+
-+ dma_buf_vunmap(gem_obj->import_attach->dmabuf, &map);
-+ } else {
-+ vunmap(cpu_ptr);
-+
-+ pvr_gem_object_put_pages(pvr_obj);
-+ }
-+}
-+
-+/**
-+ * pvr_gem_object_zero() - Zeroes the physical memory behind an object.
-+ * @pvr_obj: Target PowerVR GEM object.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error encountered while attempting to map @pvr_obj to the CPU (see
-+ * pvr_gem_object_vmap_unchecked()).
-+ */
-+static int
-+pvr_gem_object_zero(struct pvr_gem_object *pvr_obj)
-+{
-+ void *cpu_ptr;
-+ int err;
-+
-+ /*
-+ * We always map writecombined here so there's no need to flush the
-+ * CPU cache afterwards.
-+ */
-+ cpu_ptr = pvr_gem_object_vmap_prot(pvr_obj, false,
-+ pgprot_writecombine(PAGE_KERNEL));
-+ if (IS_ERR(cpu_ptr)) {
-+ err = PTR_ERR(cpu_ptr);
-+ goto err_out;
-+ }
-+
-+ memset(cpu_ptr, 0, pvr_gem_object_size(pvr_obj));
-+
-+ pvr_gem_object_vunmap(pvr_obj, cpu_ptr, false);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_gem_object_init() - Initialises a PowerVR-specific buffer object.
-+ * @pvr_dev: Target PowerVR device.
-+ * @pvr_obj: PowerVR buffer object to initialise
-+ * @size: Size of the object to allocate in bytes. Must be greater than zero.
-+ * Any value which is not an exact multiple of the system page size will be
-+ * rounded up to satisfy this condition.
-+ * @flags: Options which affect both this operation and future mapping
-+ * operations performed on the returned object. Must be a combination of
-+ * DRM_PVR_BO_* and/or PVR_BO_* flags.
-+ * @funcs: Pointer to &struct drm_gem_object_funcs to assign to this object.
-+ * @is_imported: True if buffer object represents an imported buffer.
-+ *
-+ * The created object may be larger than @size, but can never be smaller. To
-+ * get the exact size, call pvr_gem_object_size() on the returned pointer.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if @size is zero or @flags is not valid,
-+ * * -%ENOMEM if sufficient physical memory cannot be allocated,
-+ * * Any other error returned by drm_gem_object_init(), or
-+ * * Any other error returned by drm_gem_create_mmap_offset().
-+ */
-+static int
-+pvr_gem_object_init(struct pvr_device *pvr_dev, struct pvr_gem_object *pvr_obj, size_t size,
-+ u64 flags, const struct drm_gem_object_funcs *funcs, bool is_imported)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct drm_gem_object *gem_obj;
-+ int err;
-+
-+ /* Verify @size and @flags before continuing. */
-+ if (size == 0 || !pvr_gem_object_flags_validate(flags)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ size = PAGE_ALIGN(size);
-+
-+ /* FIXME: Compute any kernel-only options and apply them to @flags. */
-+
-+ gem_obj = from_pvr_gem_object(pvr_obj);
-+
-+ if (is_imported) {
-+ drm_gem_private_object_init(drm_dev, gem_obj, size);
-+ } else {
-+ err = drm_gem_object_init(drm_dev, gem_obj, size);
-+ if (err)
-+ goto err_out;
-+
-+ /*
-+ * Our buffers are kept pinned, so allocating them from the MOVABLE zone is a
-+ * really bad idea, and conflicts with CMA. See comments above new_inode() why this
-+ * is required _and_ expected if you're going to pin these pages.
-+ */
-+ mapping_set_gfp_mask(gem_obj->filp->f_mapping, GFP_HIGHUSER |
-+ __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
-+ }
-+
-+ err = drm_gem_create_mmap_offset(gem_obj);
-+ if (err)
-+ goto err_release;
-+
-+ pvr_obj->pvr_dev = pvr_dev;
-+ mutex_init(&pvr_obj->lock);
-+
-+ /* Safe to cast away the const-qualifier during initialization. */
-+ *(u64 *)&pvr_obj->flags = flags;
-+
-+ gem_obj->funcs = funcs;
-+
-+ /*
-+ * Do this last because pvr_gem_object_zero() requires a fully
-+ * configured instance of struct pvr_gem_object.
-+ */
-+ if (flags & DRM_PVR_BO_CREATE_ZEROED)
-+ pvr_gem_object_zero(pvr_obj);
-+
-+ return 0;
-+
-+err_release:
-+ drm_gem_object_release(gem_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static struct pvr_gem_object *
-+pvr_gem_object_create_internal(struct pvr_device *pvr_dev, size_t size, u64 flags, bool is_imported)
-+{
-+ struct pvr_gem_object *pvr_obj;
-+ int err;
-+
-+ /* Allocate a powervr-specific buffer object, which includes a &struct drm_gem_object. */
-+ pvr_obj = kzalloc(sizeof(*pvr_obj), GFP_KERNEL);
-+ if (!pvr_obj) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ err = pvr_gem_object_init(pvr_dev, pvr_obj, size, flags, &pvr_gem_object_funcs,
-+ is_imported);
-+ if (err)
-+ goto err_kfree_pvr_obj;
-+
-+ return pvr_obj;
-+
-+err_kfree_pvr_obj:
-+ kfree(pvr_obj);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * pvr_gem_object_create() - Creates a PowerVR-specific buffer object.
-+ * @pvr_dev: Target PowerVR device.
-+ * @size: Size of the object to allocate in bytes. Must be greater than zero.
-+ * Any value which is not an exact multiple of the system page size will be
-+ * rounded up to satisfy this condition.
-+ * @flags: Options which affect both this operation and future mapping
-+ * operations performed on the returned object. Must be a combination of
-+ * DRM_PVR_BO_* and/or PVR_BO_* flags.
-+ *
-+ * The created object may be larger than @size, but can never be smaller. To
-+ * get the exact size, call pvr_gem_object_size() on the returned pointer.
-+ *
-+ * Return:
-+ * * The newly-minted PowerVR-specific buffer object on success,
-+ * * -%EINVAL if @size is zero or @flags is not valid,
-+ * * -%ENOMEM if sufficient physical memory cannot be allocated, or
-+ * * Any other error returned by drm_gem_create_mmap_offset().
-+ */
-+struct pvr_gem_object *
-+pvr_gem_object_create(struct pvr_device *pvr_dev, size_t size, u64 flags)
-+{
-+ return pvr_gem_object_create_internal(pvr_dev, size, flags, false);
-+}
-+
-+/**
-+ * pvr_gem_fw_vmap() - Map a FW object in firmware address space
-+ * @pvr_dev: Device pointer.
-+ * @fw_obj: FW object to map.
-+ * @dev_addr: Desired address in device space, if a specific address is
-+ * required. 0 otherwise.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%EINVAL if @fw_obj is already mapped but has no references, or
-+ * * Any error returned by DRM.
-+ */
-+static int
-+pvr_gem_fw_vmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj,
-+ u64 dev_addr)
-+{
-+ struct pvr_gem_object *pvr_obj = from_pvr_fw_object(fw_obj);
-+ struct drm_gem_object *gem_obj = from_pvr_gem_object(pvr_obj);
-+
-+ int err;
-+
-+ err = pvr_gem_object_get_pages(pvr_obj);
-+ if (err)
-+ goto err_out;
-+
-+ spin_lock(&pvr_dev->fw_mm_lock);
-+
-+ if (drm_mm_node_allocated(&fw_obj->fw_mm_node)) {
-+ err = -EINVAL;
-+ goto err_unlock;
-+ }
-+
-+ if (!dev_addr) {
-+ /*
-+ * Allocate from the main heap only (firmware heap minus
-+ * config space).
-+ */
-+ err = drm_mm_insert_node_in_range(&pvr_dev->fw_mm, &fw_obj->fw_mm_node,
-+ gem_obj->size, 0, 0,
-+ pvr_dev->fw_heap_info.gpu_addr,
-+ pvr_dev->fw_heap_info.gpu_addr +
-+ pvr_dev->fw_heap_info.size, 0);
-+ if (err)
-+ goto err_unlock;
-+ } else {
-+ fw_obj->fw_mm_node.start = dev_addr;
-+ fw_obj->fw_mm_node.size = gem_obj->size;
-+ err = drm_mm_reserve_node(&pvr_dev->fw_mm,
-+ &fw_obj->fw_mm_node);
-+ if (err)
-+ goto err_unlock;
-+ }
-+
-+ spin_unlock(&pvr_dev->fw_mm_lock);
-+
-+ /* Map object on GPU. */
-+ err = pvr_dev->fw_funcs->vm_map(pvr_dev, fw_obj);
-+ if (err)
-+ goto err_remove_node;
-+
-+ fw_obj->fw_addr_offset =
-+ (u32)(fw_obj->fw_mm_node.start - pvr_dev->fw_mm_base);
-+
-+ return 0;
-+
-+err_remove_node:
-+ spin_lock(&pvr_dev->fw_mm_lock);
-+ drm_mm_remove_node(&fw_obj->fw_mm_node);
-+
-+err_unlock:
-+ spin_unlock(&pvr_dev->fw_mm_lock);
-+
-+ pvr_gem_object_put_pages(pvr_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_gem_fw_vunmap() - Unmap a previously mapped FW object
-+ * @fw_obj: FW object to unmap.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%EINVAL if object is not currently mapped.
-+ */
-+static int
-+pvr_gem_fw_vunmap(struct pvr_fw_object *fw_obj)
-+{
-+ struct pvr_gem_object *pvr_obj = from_pvr_fw_object(fw_obj);
-+ struct drm_gem_object *gem_obj = from_pvr_gem_object(pvr_obj);
-+ struct pvr_device *pvr_dev = to_pvr_device(gem_obj->dev);
-+ int err;
-+
-+ pvr_dev->fw_funcs->vm_unmap(pvr_dev, fw_obj);
-+
-+ spin_lock(&pvr_dev->fw_mm_lock);
-+
-+ if (!drm_mm_node_allocated(&fw_obj->fw_mm_node)) {
-+ spin_unlock(&pvr_dev->fw_mm_lock);
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ drm_mm_remove_node(&fw_obj->fw_mm_node);
-+
-+ spin_unlock(&pvr_dev->fw_mm_lock);
-+
-+ pvr_gem_object_put_pages(pvr_obj);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_gem_create_fw_object_common(struct pvr_device *pvr_dev, size_t size,
-+ u64 flags, u64 dev_addr,
-+ struct pvr_fw_object **fw_obj_out)
-+{
-+ struct pvr_fw_object *fw_obj;
-+ int err;
-+
-+ /* %DRM_PVR_BO_DEVICE_PM_FW_PROTECT is implicit for FW objects. */
-+ flags |= DRM_PVR_BO_DEVICE_PM_FW_PROTECT;
-+
-+ fw_obj = kzalloc(sizeof(*fw_obj), GFP_KERNEL);
-+ if (!fw_obj) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ /*
-+ * All firmware objects use the same mapping flags. See
-+ * %PVR_BO_FW_FLAGS_* for details.
-+ */
-+ err = pvr_gem_object_init(pvr_dev, &fw_obj->base, size, flags, &pvr_gem_fw_object_funcs,
-+ false);
-+ if (err)
-+ goto err_fw_obj_free;
-+
-+ err = pvr_gem_fw_vmap(pvr_dev, fw_obj, dev_addr);
-+ if (err)
-+ goto err_release_object;
-+
-+ *fw_obj_out = fw_obj;
-+
-+ return 0;
-+
-+err_release_object:
-+ pvr_gem_object_put(&fw_obj->base);
-+
-+err_fw_obj_free:
-+ kfree(fw_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_gem_create_fw_object() - Create a FW object and map to firmware
-+ * @pvr_dev: PowerVR device pointer.
-+ * @size: Size of object, in bytes.
-+ * @flags: Options which affect both this operation and future mapping
-+ * operations performed on the returned object. Must be a combination of
-+ * DRM_PVR_BO_* and/or PVR_BO_* flags.
-+ * @fw_obj_out: Pointer to location to store created object pointer.
-+ *
-+ * %DRM_PVR_BO_DEVICE_PM_FW_PROTECT is implied for all FW objects. Consequently,
-+ * this function will fail if @flags has %DRM_PVR_BO_CPU_ALLOW_USERSPACE_ACCESS
-+ * set.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_gem_create_fw_object_common().
-+ */
-+int
-+pvr_gem_create_fw_object(struct pvr_device *pvr_dev, size_t size, u64 flags,
-+ struct pvr_fw_object **fw_obj_out)
-+{
-+ return pvr_gem_create_fw_object_common(pvr_dev, size, flags, 0,
-+ fw_obj_out);
-+}
-+
-+static void *
-+pvr_gem_create_and_map_fw_common(struct pvr_device *pvr_dev, size_t size,
-+ u64 flags, u64 dev_addr,
-+ struct pvr_fw_object **fw_obj_out)
-+{
-+ struct pvr_fw_object *fw_obj;
-+ void *cpu_ptr;
-+ int err;
-+
-+ err = pvr_gem_create_fw_object_common(pvr_dev, size, flags, dev_addr,
-+ &fw_obj);
-+ if (err)
-+ goto err_out;
-+
-+ cpu_ptr = pvr_fw_object_vmap(fw_obj, true);
-+ if (IS_ERR(cpu_ptr)) {
-+ err = PTR_ERR(cpu_ptr);
-+ goto err_put_object;
-+ }
-+
-+ *fw_obj_out = fw_obj;
-+
-+ return cpu_ptr;
-+
-+err_put_object:
-+ pvr_fw_object_release(fw_obj);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * pvr_gem_create_and_map_fw_object() - Create a FW object and map to firmware
-+ * and CPU
-+ * @pvr_dev: PowerVR device pointer.
-+ * @size: Size of object, in bytes.
-+ * @flags: Options which affect both this operation and future mapping
-+ * operations performed on the returned object. Must be a combination of
-+ * DRM_PVR_BO_* and/or PVR_BO_* flags.
-+ * @fw_obj_out: Pointer to location to store created object pointer.
-+ *
-+ * %DRM_PVR_BO_DEVICE_PM_FW_PROTECT is implied for all FW objects. Consequently,
-+ * this function will fail if @flags has %DRM_PVR_BO_CPU_ALLOW_USERSPACE_ACCESS
-+ * set.
-+ *
-+ * Caller is responsible for calling pvr_gem_object_vunmap() to release the CPU
-+ * mapping.
-+ *
-+ * Returns:
-+ * * Pointer to CPU mapping of newly created object, or
-+ * * Any error returned by pvr_gem_create_fw_object(), or
-+ * * Any error returned by pvr_gem_object_vmap().
-+ */
-+void *
-+pvr_gem_create_and_map_fw_object(struct pvr_device *pvr_dev, size_t size,
-+ u64 flags, struct pvr_fw_object **fw_obj_out)
-+{
-+ return pvr_gem_create_and_map_fw_common(pvr_dev, size, flags, 0,
-+ fw_obj_out);
-+}
-+
-+/**
-+ * pvr_gem_create_and_map_fw_object_offset() - Create a FW object and map to
-+ * firmware at the provided offset
-+ * and to the CPU.
-+ * @pvr_dev: PowerVR device pointer.
-+ * @dev_offset: Base address of desired FW mapping, offset from start of FW heap.
-+ * @size: Size of object, in bytes.
-+ * @flags: Options which affect both this operation and future mapping
-+ * operations performed on the returned object. Must be a combination of
-+ * DRM_PVR_BO_* and/or PVR_BO_* flags.
-+ * @fw_obj_out: Pointer to location to store created object pointer.
-+ *
-+ * %DRM_PVR_BO_DEVICE_PM_FW_PROTECT is implied for all FW objects. Consequently,
-+ * this function will fail if @flags has %DRM_PVR_BO_CPU_ALLOW_USERSPACE_ACCESS
-+ * set.
-+ *
-+ * Caller is responsible for calling pvr_gem_object_vunmap() to release the CPU
-+ * mapping.
-+ *
-+ * Returns:
-+ * * Pointer to CPU mapping of newly created object, or
-+ * * Any error returned by pvr_gem_create_fw_object(), or
-+ * * Any error returned by pvr_gem_object_vmap().
-+ */
-+void *
-+pvr_gem_create_and_map_fw_object_offset(struct pvr_device *pvr_dev,
-+ u32 dev_offset, size_t size, u64 flags,
-+ struct pvr_fw_object **fw_obj_out)
-+{
-+ u64 dev_addr = pvr_dev->fw_mm_base + dev_offset;
-+
-+ return pvr_gem_create_and_map_fw_common(pvr_dev, size, flags, dev_addr,
-+ fw_obj_out);
-+}
-+
-+/**
-+ * pvr_gem_get_dma_addr() - Get DMA address for given offset in object
-+ * @pvr_obj: Pointer to object to lookup address in.
-+ * @offset: Offset within object to lookup address at.
-+ * @dma_addr_out: Pointer to location to store DMA address.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%EINVAL if object is not currently backed, or if @offset is out of valid
-+ * range for this object.
-+ */
-+int
-+pvr_gem_get_dma_addr(struct pvr_gem_object *pvr_obj, u32 offset,
-+ dma_addr_t *dma_addr_out)
-+{
-+ u32 accumulated_offset = 0;
-+ struct scatterlist *sgl;
-+ unsigned int sgt_idx;
-+
-+ if (!pvr_obj->sgt)
-+ return -EINVAL;
-+
-+ for_each_sgtable_dma_sg(pvr_obj->sgt, sgl, sgt_idx) {
-+ u32 new_offset = accumulated_offset + sg_dma_len(sgl);
-+
-+ if (offset >= accumulated_offset && offset < new_offset) {
-+ *dma_addr_out = sg_dma_address(sgl) +
-+ (offset - accumulated_offset);
-+ return 0;
-+ }
-+
-+ accumulated_offset = new_offset;
-+ }
-+
-+ return -EINVAL;
-+}
-+
-+/**
-+ * pvr_fw_object_release() - Release FW object and unmap from FW space
-+ * @fw_obj: Object to release.
-+ */
-+void pvr_fw_object_release(struct pvr_fw_object *fw_obj)
-+{
-+ WARN_ON(pvr_gem_fw_vunmap(fw_obj));
-+ pvr_fw_object_put(fw_obj);
-+}
-+
-+struct drm_gem_object *
-+__pvr_gem_prime_import_sg_table(struct drm_device *drm_dev,
-+ struct dma_buf_attachment *attach,
-+ struct sg_table *sgt)
-+{
-+ struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
-+ size_t size = attach->dmabuf->size;
-+ struct pvr_gem_object *pvr_obj;
-+
-+ pvr_obj = pvr_gem_object_create_internal(pvr_dev, size, 0, true);
-+ if (IS_ERR(pvr_obj))
-+ return ERR_CAST(pvr_obj);
-+
-+ pvr_obj->sgt = sgt;
-+
-+ return from_pvr_gem_object(pvr_obj);
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagination/pvr_gem.h
-new file mode 100644
-index 000000000000..d65e1ae490eb
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_gem.h
-@@ -0,0 +1,383 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_GEM_H__
-+#define __PVR_GEM_H__
-+
-+#include "pvr_fw.h"
-+#include "pvr_rogue_heap_config.h"
-+#include "pvr_rogue_meta.h"
-+
-+#include <uapi/drm/pvr_drm.h>
-+
-+#include <drm/drm_gem.h>
-+#include <drm/drm_mm.h>
-+
-+#include <linux/bitfield.h>
-+#include <linux/bits.h>
-+#include <linux/const.h>
-+#include <linux/compiler_attributes.h>
-+#include <linux/kernel.h>
-+#include <linux/mutex.h>
-+#include <linux/refcount.h>
-+#include <linux/scatterlist.h>
-+#include <linux/sizes.h>
-+#include <linux/types.h>
-+
-+/* Forward declaration from "pvr_device.h". */
-+struct pvr_device;
-+struct pvr_file;
-+
-+/**
-+ * DOC: Flags for DRM_IOCTL_PVR_CREATE_BO (kernel-only)
-+ *
-+ * Kernel-only values allowed in &pvr_gem_object->flags. The majority of options
-+ * for this field are specified in the UAPI header "pvr_drm.h" with a
-+ * DRM_PVR_BO_ prefix. To distinguish these internal options (which must exist
-+ * in ranges marked as "reserved" in the UAPI header), we drop the DRM prefix.
-+ * The public options should be used directly, DRM prefix and all.
-+ *
-+ * To avoid potentially confusing gaps in the UAPI options, these kernel-only
-+ * options are specified "in reverse", starting at bit 63.
-+ *
-+ * We use "reserved" to refer to bits defined here and not exposed in the UAPI.
-+ * Bits not defined anywhere are "undefined".
-+ *
-+ * Creation options
-+ * These use the prefix PVR_BO_CREATE_.
-+ *
-+ * *There are currently no kernel-only flags in this group.*
-+ *
-+ * Device mapping options
-+ * These use the prefix PVR_BO_DEVICE_.
-+ *
-+ * *There are currently no kernel-only flags in this group.*
-+ *
-+ * CPU mapping options
-+ * These use the prefix PVR_BO_CPU_.
-+ *
-+ * :CACHED: By default, all GEM objects are mapped write-combined on the
-+ * CPU. Set this flag to override this behaviour and map the object
-+ * cached.
-+ */
-+#define PVR_BO_CPU_CACHED BIT_ULL(63)
-+
-+/* Bits 62..4 are undefined. */
-+/* Bits 3..0 are defined in the UAPI. */
-+
-+/* Other utilities. */
-+#define PVR_BO_UNDEFINED_MASK GENMASK_ULL(62, 4)
-+#define PVR_BO_RESERVED_MASK (PVR_BO_UNDEFINED_MASK | GENMASK_ULL(63, 63))
-+
-+/*
-+ * All firmware-mapped memory uses (mostly) the same flags. Specifically,
-+ * firmware-mapped memory should be:
-+ * * Read/write on the device,
-+ * * Read/write on the CPU, and
-+ * * Write-combined on the CPU.
-+ *
-+ * The only variation is in caching on the device.
-+ */
-+#define PVR_BO_FW_FLAGS_DEVICE_CACHED (ULL(0))
-+#define PVR_BO_FW_FLAGS_DEVICE_UNCACHED DRM_PVR_BO_DEVICE_BYPASS_CACHE
-+
-+/**
-+ * struct pvr_gem_object - powervr-specific wrapper for &struct drm_gem_object
-+ */
-+struct pvr_gem_object {
-+ /**
-+ * @base: The underlying &struct drm_gem_object.
-+ *
-+ * Do not access this member directly, instead call
-+ * from_pvr_gem_object().
-+ */
-+ struct drm_gem_object base;
-+
-+ /** @pvr_dev: Owning PowerVR device. */
-+ struct pvr_device *pvr_dev;
-+
-+ /**
-+ * @lock: Mutex protecting @pages_ref_count and @fw_mm_ref_count, and
-+ * writes to @pages, @sgt and @mm_node.
-+ */
-+ struct mutex lock;
-+
-+ /**
-+ * @pages_ref_count: Reference count for @pages. @lock must be held when
-+ * accessing.
-+ */
-+ int pages_ref_count;
-+
-+ /**
-+ * @pages: Array of page structures representing the memory backing
-+ * this object. @lock must be held when writing.
-+ * pvr_gem_get_pages() must be called before reading.
-+ */
-+ struct page **pages;
-+
-+ /**
-+ * @sgt: Scatter-gather table representing the memory backing this
-+ * object. @lock must be held when writing. pvr_gem_get_pages()
-+ * must be called before reading.
-+ */
-+ struct sg_table *sgt;
-+
-+ /**
-+ * @flags: Options set at creation-time. Some of these options apply to
-+ * the creation operation itself (which are stored here for reference)
-+ * with the remainder used for mapping options to both the device and
-+ * CPU. These are used every time this object is mapped, but may be
-+ * changed after creation.
-+ *
-+ * Must be a combination of DRM_PVR_BO_* and/or PVR_BO_* flags.
-+ *
-+ * .. note::
-+ *
-+ * This member is declared const to indicate that none of these
-+ * options may change or be changed throughout the object's
-+ * lifetime.
-+ */
-+ const u64 flags;
-+};
-+
-+/**
-+ * struct pvr_fw_object - container for firmware memory allocations
-+ */
-+struct pvr_fw_object {
-+ /** @base: The underlying PVR GEM object backing this allocation. */
-+ struct pvr_gem_object base;
-+
-+ /**
-+ * @fw_mm_node: Node representing mapping in FW address space. @pvr_obj->lock must
-+ * be held when writing.
-+ */
-+ struct drm_mm_node fw_mm_node;
-+
-+ /**
-+ * @fw_addr_offset: Virtual address offset of firmware mapping. Only
-+ * valid if @flags has %PVR_GEM_OBJECT_FLAGS_FW_MAPPED
-+ * set.
-+ */
-+ u32 fw_addr_offset;
-+};
-+
-+static __always_inline struct drm_gem_object *
-+from_pvr_gem_object(struct pvr_gem_object *pvr_obj)
-+{
-+ return &pvr_obj->base;
-+}
-+
-+static __always_inline struct pvr_gem_object *
-+to_pvr_gem_object(struct drm_gem_object *gem_obj)
-+{
-+ return container_of(gem_obj, struct pvr_gem_object, base);
-+}
-+
-+static __always_inline struct pvr_gem_object *
-+from_pvr_fw_object(struct pvr_fw_object *fw_obj)
-+{
-+ return &fw_obj->base;
-+}
-+
-+static __always_inline struct pvr_fw_object *
-+to_pvr_fw_object(struct pvr_gem_object *pvr_obj)
-+{
-+ return container_of(pvr_obj, struct pvr_fw_object, base);
-+}
-+
-+/* Functions defined in pvr_gem.c */
-+
-+struct drm_gem_object *
-+__pvr_gem_prime_import_sg_table(struct drm_device *drm_dev,
-+ struct dma_buf_attachment *attach,
-+ struct sg_table *sgt);
-+
-+struct pvr_gem_object *pvr_gem_object_create(struct pvr_device *pvr_dev,
-+ size_t size, u64 flags);
-+
-+int pvr_gem_object_into_handle(struct pvr_gem_object *pvr_obj,
-+ struct pvr_file *pvr_file, u32 *handle);
-+struct pvr_gem_object *pvr_gem_object_from_handle(struct pvr_file *pvr_file,
-+ u32 handle);
-+
-+int pvr_gem_object_get_pages(struct pvr_gem_object *pvr_obj);
-+void pvr_gem_object_put_pages(struct pvr_gem_object *pvr_obj);
-+
-+void *pvr_gem_object_vmap(struct pvr_gem_object *pvr_obj, bool sync_to_cpu);
-+void pvr_gem_object_vunmap(struct pvr_gem_object *pvr_obj, void *cpu_ptr,
-+ bool sync_to_device);
-+
-+int pvr_gem_create_fw_object(struct pvr_device *pvr_dev, size_t size, u64 flags,
-+ struct pvr_fw_object **pvr_obj_out);
-+
-+void *pvr_gem_create_and_map_fw_object(struct pvr_device *pvr_dev, size_t size,
-+ u64 flags,
-+ struct pvr_fw_object **pvr_obj_out);
-+
-+void *
-+pvr_gem_create_and_map_fw_object_offset(struct pvr_device *pvr_dev,
-+ u32 dev_offset, size_t size, u64 flags,
-+ struct pvr_fw_object **pvr_obj_out);
-+
-+int pvr_gem_get_dma_addr(struct pvr_gem_object *pvr_obj, u32 offset,
-+ dma_addr_t *dma_addr_out);
-+
-+/**
-+ * pvr_gem_object_get() - Acquire reference on pvr_gem_object
-+ * @pvr_obj: Pointer to object to acquire reference on.
-+ */
-+static __always_inline void
-+pvr_gem_object_get(struct pvr_gem_object *pvr_obj)
-+{
-+ drm_gem_object_get(from_pvr_gem_object(pvr_obj));
-+}
-+
-+/**
-+ * pvr_gem_object_put() - Release reference on pvr_gem_object
-+ * @pvr_obj: Pointer to object to release reference on.
-+ */
-+static __always_inline void
-+pvr_gem_object_put(struct pvr_gem_object *pvr_obj)
-+{
-+ drm_gem_object_put(from_pvr_gem_object(pvr_obj));
-+}
-+
-+static __always_inline size_t
-+pvr_gem_object_size(struct pvr_gem_object *pvr_obj)
-+{
-+ return from_pvr_gem_object(pvr_obj)->size;
-+}
-+
-+/**
-+ * pvr_gem_object_is_imported() - Return whether an object is imported
-+ * @pvr_obj: Pointer to object to test.
-+ *
-+ * Returns:
-+ * * %true if object is imported, or
-+ * * %false if object is not imported.
-+ */
-+static __always_inline bool
-+pvr_gem_object_is_imported(struct pvr_gem_object *pvr_obj)
-+{
-+ return pvr_obj->base.import_attach != NULL;
-+}
-+
-+void pvr_fw_object_release(struct pvr_fw_object *fw_obj);
-+
-+static __always_inline void *
-+pvr_fw_object_vmap(struct pvr_fw_object *fw_obj, bool sync_to_cpu)
-+{
-+ return pvr_gem_object_vmap(from_pvr_fw_object(fw_obj), sync_to_cpu);
-+}
-+
-+static __always_inline void
-+pvr_fw_object_vunmap(struct pvr_fw_object *fw_obj, void *cpu_ptr, bool sync_to_device)
-+{
-+ pvr_gem_object_vunmap(from_pvr_fw_object(fw_obj), cpu_ptr, sync_to_device);
-+}
-+
-+/**
-+ * pvr_fw_object_get() - Acquire reference on pvr_fw_object
-+ * @fw_obj: Pointer to object to acquire reference on.
-+ */
-+static __always_inline void
-+pvr_fw_object_get(struct pvr_fw_object *fw_obj)
-+{
-+ pvr_gem_object_get(from_pvr_fw_object(fw_obj));
-+}
-+
-+/**
-+ * pvr_fw_object_put() - Release reference on pvr_fw_object
-+ * @fw_obj: Pointer to object to release reference on.
-+ *
-+ * Note: This function must _not_ be used to release the reference obtained at
-+ * creation time via pvr_gem_create_fw_object(). Use pvr_fw_object_release()
-+ * instead.
-+ */
-+static __always_inline void
-+pvr_fw_object_put(struct pvr_fw_object *fw_obj)
-+{
-+ pvr_gem_object_put(from_pvr_fw_object(fw_obj));
-+}
-+
-+/**
-+ * pvr_fw_get_dma_addr() - Get DMA address for given offset in firmware object
-+ * @fw_obj: Pointer to object to lookup address in.
-+ * @offset: Offset within object to lookup address at.
-+ * @dma_addr_out: Pointer to location to store DMA address.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%EINVAL if object is not currently backed, or if @offset is out of valid
-+ * range for this object.
-+ */
-+static __always_inline int
-+pvr_fw_get_dma_addr(struct pvr_fw_object *fw_obj, u32 offset, dma_addr_t *dma_addr_out)
-+{
-+ return pvr_gem_get_dma_addr(from_pvr_fw_object(fw_obj), offset, dma_addr_out);
-+}
-+
-+/**
-+ * pvr_gem_get_fw_addr_offset() - Return address of object in firmware address space, with given
-+ * offset.
-+ * @fw_obj: Pointer to object.
-+ * @offset: Desired offset from start of object.
-+ * @fw_addr_out: Location to store address to.
-+ *
-+ * Returns :
-+ * * %true on success, or
-+ * * %false if object is not mapped to firmware address space, or if @offset is outside object.
-+ */
-+static __always_inline bool
-+pvr_gem_get_fw_addr_offset(struct pvr_fw_object *fw_obj, u32 offset, u32 *fw_addr_out)
-+{
-+ struct pvr_gem_object *pvr_obj = from_pvr_fw_object(fw_obj);
-+ struct pvr_device *pvr_dev = pvr_obj->pvr_dev;
-+
-+ *fw_addr_out = pvr_dev->fw_funcs->get_fw_addr_with_offset(fw_obj, offset);
-+
-+ return true;
-+}
-+
-+/**
-+ * pvr_gem_get_fw_addr() - Return address of object in firmware address space
-+ * @fw_obj: Pointer to object.
-+ * @fw_addr_out: Location to store address to.
-+ *
-+ * Returns :
-+ * * %true on success, or
-+ * * %false if object is not mapped to firmware address space.
-+ */
-+static __always_inline bool
-+pvr_gem_get_fw_addr(struct pvr_fw_object *fw_obj, u32 *fw_addr_out)
-+{
-+ return pvr_gem_get_fw_addr_offset(fw_obj, 0, fw_addr_out);
-+}
-+
-+/**
-+ * pvr_gem_get_fw_gpu_addr() - Return address of object in GPU address space
-+ * @fw_obj: Pointer to object.
-+ * @gpu_addr_out: Location to store address to.
-+ *
-+ * Note that this function is not valid if firmware processor is MIPS.
-+ *
-+ * Returns :
-+ * * %true on success, or
-+ * * %false if object is not mapped to firmware address space.
-+ */
-+static __always_inline bool
-+pvr_gem_get_fw_gpu_addr(struct pvr_fw_object *fw_obj, u64 *gpu_addr_out)
-+{
-+ /* FIXME: Move to META-specific file */
-+ struct pvr_gem_object *pvr_obj = from_pvr_fw_object(fw_obj);
-+ struct pvr_device *pvr_dev = pvr_obj->pvr_dev;
-+
-+ if (pvr_dev->fw_processor_type != PVR_FW_PROCESSOR_TYPE_MIPS) {
-+ *gpu_addr_out = fw_obj->fw_addr_offset + pvr_dev->fw_heap_info.gpu_addr;
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+#endif /* __PVR_GEM_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_hwrt.c b/drivers/gpu/drm/imagination/pvr_hwrt.c
-new file mode 100644
-index 000000000000..49ae5a2e30d4
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_hwrt.c
-@@ -0,0 +1,379 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_free_list.h"
-+#include "pvr_hwrt.h"
-+#include "pvr_gem.h"
-+#include "pvr_object.h"
-+#include "pvr_rogue_fwif.h"
-+
-+#include <drm/drm_gem.h>
-+#include <linux/slab.h>
-+#include <linux/xarray.h>
-+#include <uapi/drm/pvr_drm.h>
-+
-+/* Size of Shadow Render Target Cache entry */
-+#define SRTC_ENTRY_SIZE sizeof(u32)
-+/* Size of Renders Accumulation Array entry */
-+#define RAA_ENTRY_SIZE sizeof(u32)
-+
-+static int
-+hwrt_init_kernel_structure(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_hwrt_dataset_args *args,
-+ struct create_hwrt_free_list_args *free_list_args,
-+ struct pvr_hwrt_dataset *hwrt)
-+{
-+ int err;
-+ int i;
-+
-+ hwrt->base.type = DRM_PVR_OBJECT_TYPE_HWRT_DATASET;
-+ hwrt->pvr_dev = pvr_file->pvr_dev;
-+ hwrt->max_rts = args->max_rts;
-+ hwrt->num_free_lists = args->num_free_lists;
-+ hwrt->num_rt_datas = args->num_rt_datas;
-+
-+ /* Get pointers to the free lists */
-+ for (i = 0; i < hwrt->num_free_lists; i++) {
-+ hwrt->free_lists[i] =
-+ pvr_free_list_get(pvr_file,
-+ free_list_args[i].free_list_handle);
-+ if (!hwrt->free_lists[i]) {
-+ err = -EINVAL;
-+ goto err_put_free_lists;
-+ }
-+ }
-+
-+ return 0;
-+
-+err_put_free_lists:
-+ for (i = 0; i < hwrt->num_free_lists; i++) {
-+ if (hwrt->free_lists[i]) {
-+ pvr_free_list_put(hwrt->free_lists[i]);
-+ hwrt->free_lists[i] = NULL;
-+ }
-+ }
-+
-+ return err;
-+}
-+
-+static void
-+hwrt_fini_kernel_structure(struct pvr_hwrt_dataset *hwrt)
-+{
-+ int i;
-+
-+ for (i = 0; i < hwrt->num_free_lists; i++) {
-+ if (hwrt->free_lists[i]) {
-+ pvr_free_list_put(hwrt->free_lists[i]);
-+ hwrt->free_lists[i] = NULL;
-+ }
-+ }
-+}
-+
-+static int
-+hwrt_init_common_fw_structure(
-+ struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_hwrt_dataset_args *args,
-+ struct pvr_hwrt_dataset *hwrt)
-+{
-+ struct pvr_device *pvr_dev = pvr_file->pvr_dev;
-+ struct rogue_fwif_hwrtdata_common *hwrt_data_common_fw;
-+ int err;
-+
-+ /*
-+ * Create and map the FW structure so we can initialise it. This is not
-+ * accessed on the CPU side post-initialisation so the mapping lifetime
-+ * is only for this function.
-+ */
-+ hwrt_data_common_fw = pvr_gem_create_and_map_fw_object(pvr_dev,
-+ sizeof(*hwrt_data_common_fw), PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED, &hwrt->common_fw_obj);
-+ if (IS_ERR(hwrt_data_common_fw)) {
-+ err = PTR_ERR(hwrt_data_common_fw);
-+ goto err_out;
-+ }
-+
-+ hwrt_data_common_fw->geom_caches_need_zeroing = false;
-+
-+ pvr_fw_object_vunmap(hwrt->common_fw_obj, hwrt_data_common_fw, false);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+hwrt_fini_common_fw_structure(struct pvr_hwrt_dataset *hwrt)
-+{
-+ pvr_fw_object_release(hwrt->common_fw_obj);
-+}
-+
-+static int
-+hwrt_data_init_fw_structure(struct pvr_file *pvr_file,
-+ struct pvr_hwrt_dataset *hwrt,
-+ struct drm_pvr_ioctl_create_hwrt_dataset_args *args,
-+ struct create_hwrt_geom_data_args *geom_data_args,
-+ struct create_hwrt_rt_data_args *rt_data_args,
-+ struct pvr_hwrt_data *hwrt_data)
-+{
-+ struct pvr_device *pvr_dev = pvr_file->pvr_dev;
-+ struct rogue_fwif_hwrtdata *hwrt_data_fw;
-+ struct rogue_fwif_rta_ctl *rta_ctl;
-+ int free_list_i;
-+ int err;
-+
-+ /*
-+ * Create and map the FW structure so we can initialise it. This is not
-+ * accessed on the CPU side post-initialisation so the mapping lifetime
-+ * is only for this function.
-+ */
-+ hwrt_data_fw = pvr_gem_create_and_map_fw_object(pvr_dev, sizeof(*hwrt_data_fw),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED, &hwrt_data->fw_obj);
-+ if (IS_ERR(hwrt_data_fw)) {
-+ err = PTR_ERR(hwrt_data_fw);
-+ goto err_out;
-+ }
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ hwrt->common_fw_obj, &hwrt_data_fw->hwrt_data_common_fw_addr));
-+
-+ /* MList Data Store */
-+ hwrt_data_fw->pm_mlist_dev_addr = rt_data_args->pm_mlist_dev_addr;
-+
-+ for (free_list_i = 0; free_list_i < hwrt->num_free_lists;
-+ free_list_i++) {
-+ if (!pvr_gem_get_fw_addr(
-+ hwrt->free_lists[free_list_i]->fw_obj,
-+ &hwrt_data_fw->freelists_fw_addr[free_list_i])) {
-+ err = -EINVAL;
-+ goto err_put_fw_obj;
-+ }
-+ }
-+
-+ hwrt_data_fw->vheap_table_dev_addr = geom_data_args->vheap_table_dev_addr;
-+ hwrt_data_fw->screen_pixel_max = args->screen_pixel_max;
-+ hwrt_data_fw->multi_sample_ctl = args->multi_sample_control;
-+ hwrt_data_fw->flipped_multi_sample_ctl =
-+ args->flipped_multi_sample_control;
-+ hwrt_data_fw->tpc_stride = args->tpc_stride;
-+ hwrt_data_fw->tail_ptrs_dev_addr = geom_data_args->tail_ptrs_dev_addr;
-+ hwrt_data_fw->tpc_size = args->tpc_stride;
-+ hwrt_data_fw->te_screen = args->te_screen_size;
-+ hwrt_data_fw->mtile_stride = args->mtile_stride;
-+ hwrt_data_fw->teaa = args->te_aa;
-+ hwrt_data_fw->te_mtile1 = args->te_mtile[0];
-+ hwrt_data_fw->te_mtile2 = args->te_mtile[1];
-+ hwrt_data_fw->isp_merge_lower_x = args->isp_merge_lower_x;
-+ hwrt_data_fw->isp_merge_lower_y = args->isp_merge_lower_y;
-+ hwrt_data_fw->isp_merge_upper_x = args->isp_merge_upper_x;
-+ hwrt_data_fw->isp_mergy_upper_y = args->isp_merge_upper_y;
-+ hwrt_data_fw->isp_merge_scale_x = args->isp_merge_scale_x;
-+ hwrt_data_fw->isp_merge_scale_y = args->isp_merge_scale_y;
-+ hwrt_data_fw->macrotile_array_dev_addr =
-+ rt_data_args->macrotile_array_dev_addr;
-+ hwrt_data_fw->rgn_header_dev_addr = rt_data_args->region_header_dev_addr;
-+ hwrt_data_fw->rtc_dev_addr = geom_data_args->rtc_dev_addr;
-+ hwrt_data_fw->rgn_header_size = args->region_header_size;
-+ hwrt_data_fw->isp_mtile_size = args->isp_mtile_size;
-+
-+ rta_ctl = &hwrt_data_fw->rta_ctl;
-+
-+ rta_ctl->render_target_index = 0;
-+ rta_ctl->active_render_targets = 0;
-+ rta_ctl->valid_render_targets_fw_addr = 0;
-+ rta_ctl->rta_num_partial_renders_fw_addr = 0;
-+ rta_ctl->max_rts = args->max_rts;
-+
-+ if (args->max_rts > 1) {
-+ err = pvr_gem_create_fw_object(pvr_dev, args->max_rts * SRTC_ENTRY_SIZE,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &hwrt_data->srtc_obj);
-+ if (err)
-+ goto err_put_fw_obj;
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ hwrt_data->srtc_obj,
-+ &rta_ctl->valid_render_targets_fw_addr));
-+
-+ err = pvr_gem_create_fw_object(pvr_dev, args->max_rts * RAA_ENTRY_SIZE,
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED |
-+ DRM_PVR_BO_CREATE_ZEROED,
-+ &hwrt_data->raa_obj);
-+ if (err)
-+ goto err_put_shadow_rt_cache;
-+ WARN_ON(!pvr_gem_get_fw_addr(
-+ hwrt_data->raa_obj,
-+ &rta_ctl->rta_num_partial_renders_fw_addr));
-+ }
-+
-+ pvr_fw_object_vunmap(hwrt_data->fw_obj, hwrt_data_fw, false);
-+
-+ return 0;
-+
-+err_put_shadow_rt_cache:
-+ pvr_fw_object_release(hwrt_data->srtc_obj);
-+
-+err_put_fw_obj:
-+ pvr_fw_object_vunmap(hwrt_data->fw_obj, hwrt_data_fw, false);
-+ pvr_fw_object_release(hwrt_data->fw_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+hwrt_data_fini_fw_structure(struct pvr_hwrt_dataset *hwrt, int hwrt_nr)
-+{
-+ struct pvr_hwrt_data *hwrt_data = &hwrt->data[hwrt_nr];
-+
-+ if (hwrt->max_rts > 1) {
-+ pvr_fw_object_release(hwrt_data->raa_obj);
-+ pvr_fw_object_release(hwrt_data->srtc_obj);
-+ }
-+
-+ pvr_fw_object_release(hwrt_data->fw_obj);
-+}
-+
-+/**
-+ * pvr_hwrt_dataset_create() - Create a new HWRT dataset
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @args: Creation arguments from userspace.
-+ *
-+ * Return:
-+ * * HWRT pointer on success, or
-+ * * -%ENOMEM on out of memory.
-+ */
-+struct pvr_hwrt_dataset *
-+pvr_hwrt_dataset_create(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_hwrt_dataset_args *args)
-+{
-+ struct create_hwrt_geom_data_args *geom_data_args;
-+ struct create_hwrt_rt_data_args *rt_data_args;
-+ struct create_hwrt_free_list_args *free_list_args;
-+ struct pvr_hwrt_dataset *hwrt;
-+ int err;
-+ int i;
-+
-+ if (args->num_geom_datas != ROGUE_FWIF_NUM_GEOMDATAS ||
-+ args->num_rt_datas != ROGUE_FWIF_NUM_RTDATAS ||
-+ args->num_free_lists != ROGUE_FWIF_NUM_RTDATA_FREELISTS) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if (args->_padding_7a || args->_padding_7c) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ /* TODO: support multiple geom datas */
-+ BUILD_BUG_ON(ROGUE_FWIF_NUM_GEOMDATAS != 1);
-+
-+ /* Copy geom / RT / free list structures from user space. */
-+ geom_data_args = kcalloc(args->num_geom_datas, sizeof(*geom_data_args),
-+ GFP_KERNEL);
-+ rt_data_args =
-+ kcalloc(args->num_rt_datas, sizeof(*rt_data_args), GFP_KERNEL);
-+ free_list_args = kcalloc(args->num_free_lists, sizeof(*free_list_args),
-+ GFP_KERNEL);
-+ if (!geom_data_args || !rt_data_args || !free_list_args) {
-+ err = -ENOMEM;
-+ goto err_free_args;
-+ }
-+
-+ if (copy_from_user(geom_data_args,
-+ u64_to_user_ptr(args->geom_data_args),
-+ sizeof(*geom_data_args) * args->num_geom_datas)) {
-+ err = -EFAULT;
-+ goto err_free_args;
-+ }
-+ if (copy_from_user(rt_data_args, u64_to_user_ptr(args->rt_data_args),
-+ sizeof(*rt_data_args) * args->num_rt_datas)) {
-+ err = -EFAULT;
-+ goto err_free_args;
-+ }
-+ if (copy_from_user(free_list_args,
-+ u64_to_user_ptr(args->free_list_args),
-+ sizeof(*free_list_args) * args->num_free_lists)) {
-+ err = -EFAULT;
-+ goto err_free_args;
-+ }
-+
-+ /* Create and fill out the kernel structure */
-+ hwrt = kzalloc(sizeof(*hwrt), GFP_KERNEL);
-+ if (!hwrt) {
-+ err = -ENOMEM;
-+ goto err_free_args;
-+ }
-+
-+ err = hwrt_init_kernel_structure(pvr_file, args, free_list_args, hwrt);
-+ if (err < 0)
-+ goto err_free_hwrt;
-+
-+ err = hwrt_init_common_fw_structure(pvr_file, args, hwrt);
-+ if (err < 0)
-+ goto err_destroy_kernel_structure;
-+
-+ for (i = 0; i < args->num_rt_datas; i++) {
-+ err = hwrt_data_init_fw_structure(pvr_file, hwrt, args,
-+ geom_data_args,
-+ &rt_data_args[i],
-+ &hwrt->data[i]);
-+ if (err < 0) {
-+ i--;
-+ /* Destroy already created structures. */
-+ for (; i >= 0; i--)
-+ hwrt_data_fini_fw_structure(hwrt, i);
-+ goto err_destroy_common_fw_structure;
-+ }
-+
-+ hwrt->data[i].hwrt_dataset = hwrt;
-+ }
-+
-+ kfree(geom_data_args);
-+ kfree(rt_data_args);
-+ kfree(free_list_args);
-+
-+ return hwrt;
-+
-+err_destroy_common_fw_structure:
-+ hwrt_fini_common_fw_structure(hwrt);
-+
-+err_destroy_kernel_structure:
-+ hwrt_fini_kernel_structure(hwrt);
-+
-+err_free_hwrt:
-+ kfree(hwrt);
-+
-+err_free_args:
-+ kfree(geom_data_args);
-+ kfree(rt_data_args);
-+ kfree(free_list_args);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * pvr_hwrt_dataset_destroy() - Destroy a HWRT data set
-+ * @hwrt: HWRT pointer
-+ *
-+ * This should not be called directly. HWRT references should be dropped via pvr_hwrt_dataset_put().
-+ */
-+void
-+pvr_hwrt_dataset_destroy(struct pvr_hwrt_dataset *hwrt)
-+{
-+ struct pvr_device *pvr_dev = hwrt->pvr_dev;
-+ int i;
-+
-+ for (i = hwrt->num_rt_datas - 1; i >= 0; i--) {
-+ WARN_ON(pvr_object_cleanup(pvr_dev, ROGUE_FWIF_CLEANUP_HWRTDATA,
-+ hwrt->data[i].fw_obj, 0));
-+ hwrt_data_fini_fw_structure(hwrt, i);
-+ }
-+
-+ hwrt_fini_common_fw_structure(hwrt);
-+ hwrt_fini_kernel_structure(hwrt);
-+
-+ kfree(hwrt);
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_hwrt.h b/drivers/gpu/drm/imagination/pvr_hwrt.h
-new file mode 100644
-index 000000000000..edfa3945e055
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_hwrt.h
-@@ -0,0 +1,171 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_HWRT_H__
-+#define __PVR_HWRT_H__
-+
-+#include <linux/compiler_attributes.h>
-+#include <linux/kref.h>
-+#include <linux/list.h>
-+#include <linux/types.h>
-+#include <linux/xarray.h>
-+#include <uapi/drm/pvr_drm.h>
-+
-+#include "pvr_device.h"
-+#include "pvr_object.h"
-+#include "pvr_rogue_fwif_shared.h"
-+
-+/* Forward declaration from pvr_free_list.h. */
-+struct pvr_free_list;
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_fw_object;
-+
-+/**
-+ * struct pvr_hwrt_data - structure representing HWRT data
-+ */
-+struct pvr_hwrt_data {
-+ /** @fw_obj: FW object representing the FW-side structure. */
-+ struct pvr_fw_object *fw_obj;
-+
-+ /**
-+ * @srtc_obj: FW object representing shadow render target cache.
-+ *
-+ * Only valid if @max_rts > 1.
-+ */
-+ struct pvr_fw_object *srtc_obj;
-+
-+ /**
-+ * @raa_obj: FW object representing renders accumulation array.
-+ *
-+ * Only valid if @max_rts > 1.
-+ */
-+ struct pvr_fw_object *raa_obj;
-+
-+ /** @hwrt_dataset: Back pointer to owning HWRT dataset. */
-+ struct pvr_hwrt_dataset *hwrt_dataset;
-+};
-+
-+/**
-+ * struct pvr_hwrt_dataset - structure representing a HWRT data set.
-+ */
-+struct pvr_hwrt_dataset {
-+ /** @base: Object base structure. */
-+ struct pvr_object base;
-+
-+ /** @pvr_dev: Pointer to owning device. */
-+ struct pvr_device *pvr_dev;
-+
-+ /** @common_fw_obj: FW object representing common FW-side structure. */
-+ struct pvr_fw_object *common_fw_obj;
-+
-+ /** @data: HWRT data structures belonging to this set. */
-+ struct pvr_hwrt_data data[ROGUE_FWIF_NUM_RTDATAS];
-+
-+ /** @free_lists: Free lists used by HWRT data set. */
-+ struct pvr_free_list *free_lists[ROGUE_FWIF_NUM_RTDATA_FREELISTS];
-+
-+ /** @max_rts: Maximum render targets for this HWRT data set. */
-+ u16 max_rts;
-+
-+ /** @num_rt_datas: Number of rt data arguments. */
-+ u32 num_rt_datas;
-+
-+ /** @num_free_lists: Number of free list arguments. */
-+ u32 num_free_lists;
-+};
-+
-+struct pvr_hwrt_dataset *
-+pvr_hwrt_dataset_create(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_hwrt_dataset_args *args);
-+
-+void pvr_hwrt_dataset_destroy(struct pvr_hwrt_dataset *hwrt);
-+
-+static __always_inline struct pvr_object *
-+from_pvr_hwrt_dataset(struct pvr_hwrt_dataset *hwrt)
-+{
-+ return &hwrt->base;
-+};
-+
-+static __always_inline struct pvr_hwrt_dataset *
-+to_pvr_hwrt_dataset(struct pvr_object *obj)
-+{
-+ return container_of(obj, struct pvr_hwrt_dataset, base);
-+}
-+
-+/**
-+ * pvr_hwrt_dataset_get() - Get HWRT dataset pointer from handle
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @handle: Object handle.
-+ *
-+ * Takes reference on object. Call pvr_hwrt_dataset_put() to release.
-+ *
-+ * Returns:
-+ * * The requested object on success, or
-+ * * %NULL on failure (object does not exist in list, or is not a HWRT
-+ * dataset)
-+ */
-+static __always_inline struct pvr_hwrt_dataset *
-+pvr_hwrt_dataset_get(struct pvr_file *pvr_file, u32 handle)
-+{
-+ struct pvr_object *obj = pvr_object_get(pvr_file, handle);
-+
-+ if (obj) {
-+ if (obj->type == DRM_PVR_OBJECT_TYPE_HWRT_DATASET)
-+ return to_pvr_hwrt_dataset(obj);
-+
-+ pvr_object_put(obj);
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * pvr_hwrt_dataset_put() - Release reference on HWRT dataset
-+ * @hwrt: Pointer to HWRT dataset to release reference on
-+ */
-+static __always_inline void
-+pvr_hwrt_dataset_put(struct pvr_hwrt_dataset *hwrt)
-+{
-+ pvr_object_put(&hwrt->base);
-+}
-+
-+/**
-+ * pvr_hwrt_data_get() - Get HWRT data pointer from handle and index
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @handle: Object handle.
-+ * @index: Index of RT data within dataset.
-+ *
-+ * Takes reference on dataset object. Call pvr_hwrt_data_put() to release.
-+ *
-+ * Returns:
-+ * * The requested object on success, or
-+ * * %NULL on failure (object does not exist in list, or is not a HWRT
-+ * dataset, or index is out of range)
-+ */
-+static __always_inline struct pvr_hwrt_data *
-+pvr_hwrt_data_get(struct pvr_file *pvr_file, u32 handle, u32 index)
-+{
-+ struct pvr_hwrt_dataset *hwrt_dataset = pvr_hwrt_dataset_get(pvr_file, handle);
-+
-+ if (hwrt_dataset) {
-+ if (index < hwrt_dataset->num_rt_datas)
-+ return &hwrt_dataset->data[index];
-+
-+ pvr_hwrt_dataset_put(hwrt_dataset);
-+ }
-+
-+ return NULL;
-+}
-+
-+/**
-+ * pvr_hwrt_data_put() - Release reference on HWRT data
-+ * @hwrt: Pointer to HWRT data to release reference on
-+ */
-+static __always_inline void
-+pvr_hwrt_data_put(struct pvr_hwrt_data *hwrt)
-+{
-+ pvr_hwrt_dataset_put(hwrt->hwrt_dataset);
-+}
-+
-+#endif /* __PVR_HWRT_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_job.c b/drivers/gpu/drm/imagination/pvr_job.c
-new file mode 100644
-index 000000000000..27c28eb2ff08
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_job.c
-@@ -0,0 +1,969 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_context.h"
-+#include "pvr_device.h"
-+#include "pvr_fence.h"
-+#include "pvr_gem.h"
-+#include "pvr_hwrt.h"
-+#include "pvr_job.h"
-+#include "pvr_rogue_fwif.h"
-+#include "pvr_rogue_fwif_client.h"
-+
-+#include <drm/drm_gem.h>
-+#include <drm/drm_syncobj.h>
-+#include <linux/slab.h>
-+#include <linux/types.h>
-+#include <linux/xarray.h>
-+#include <uapi/drm/pvr_drm.h>
-+
-+static int
-+import_fences(struct pvr_file *pvr_file, u32 num_in_syncobj_handles,
-+ u64 in_syncobj_handles_p, struct xarray *in_fences)
-+{
-+ const void __user *uptr = u64_to_user_ptr(in_syncobj_handles_p);
-+ u32 *in_syncobj_handles;
-+ struct dma_fence *fence;
-+ unsigned long id;
-+ int err;
-+ int i;
-+
-+ in_syncobj_handles = kcalloc(num_in_syncobj_handles, sizeof(*in_syncobj_handles),
-+ GFP_KERNEL);
-+ if (!in_syncobj_handles) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ if (copy_from_user(in_syncobj_handles, uptr,
-+ sizeof(*in_syncobj_handles) * num_in_syncobj_handles)) {
-+ err = -EFAULT;
-+ goto err_free_memory;
-+ }
-+
-+ for (i = 0; i < num_in_syncobj_handles; i++) {
-+ err = drm_syncobj_find_fence(from_pvr_file(pvr_file),
-+ in_syncobj_handles[i], 0, 0, &fence);
-+ if (err)
-+ goto err_release_fences;
-+
-+ err = drm_gem_fence_array_add(in_fences, fence);
-+ if (err)
-+ goto err_release_fences;
-+ }
-+
-+ return 0;
-+
-+err_release_fences:
-+ xa_for_each(in_fences, id, fence) {
-+ dma_fence_put(fence);
-+ }
-+ xa_destroy(in_fences);
-+
-+err_free_memory:
-+ kfree(in_syncobj_handles);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void release_fences(struct xarray *in_fences)
-+{
-+ struct dma_fence *fence;
-+ unsigned long id;
-+
-+ xa_for_each(in_fences, id, fence) {
-+ dma_fence_put(fence);
-+ }
-+ xa_destroy(in_fences);
-+}
-+
-+static int
-+import_implicit_fences(struct pvr_file *pvr_file, struct pvr_job *job,
-+ u32 num_in_bo_handles, u64 in_bo_handles_p,
-+ struct xarray *in_fences)
-+{
-+ struct drm_file *drm_file = from_pvr_file(pvr_file);
-+ struct drm_pvr_bo_ref *bo_refs;
-+ struct dma_fence *fence;
-+ unsigned long id;
-+ int err;
-+ int i;
-+
-+ bo_refs = kvmalloc_array(num_in_bo_handles, sizeof(*bo_refs), GFP_KERNEL);
-+ if (!bo_refs) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ if (copy_from_user(bo_refs, u64_to_user_ptr(in_bo_handles_p),
-+ num_in_bo_handles * sizeof(*bo_refs))) {
-+ err = -EFAULT;
-+ goto err_free_bo_refs;
-+ }
-+
-+ job->bos = kvmalloc_array(num_in_bo_handles, sizeof(*job->bos), GFP_KERNEL | __GFP_ZERO);
-+ if (!job->bos) {
-+ err = -ENOMEM;
-+ goto err_free_bo_refs;
-+ }
-+
-+ job->num_bos = num_in_bo_handles;
-+
-+ for (i = 0; i < job->num_bos; i++) {
-+ job->bos[i] = drm_gem_object_lookup(drm_file, bo_refs[i].handle);
-+ if (job->bos[i])
-+ goto err_release_fences;
-+
-+ err = drm_gem_fence_array_add_implicit(in_fences, job->bos[i],
-+ bo_refs[i].flags & DRM_PVR_BO_REF_WRITE);
-+ if (err)
-+ goto err_release_fences;
-+ }
-+
-+ return 0;
-+
-+err_release_fences:
-+ xa_for_each(in_fences, id, fence) {
-+ dma_fence_put(fence);
-+ }
-+ xa_destroy(in_fences);
-+
-+ for (i = 0; i < num_in_bo_handles; i++)
-+ drm_gem_object_put(job->bos[i]);
-+ kfree(job->bos);
-+
-+err_free_bo_refs:
-+ kfree(bo_refs);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void release_implicit_fences(struct pvr_job *job, struct xarray *in_fences)
-+{
-+ struct dma_fence *fence;
-+ unsigned long id;
-+ int i;
-+
-+ xa_for_each(in_fences, id, fence) {
-+ dma_fence_put(fence);
-+ }
-+ xa_destroy(in_fences);
-+
-+ for (i = 0; i < job->num_bos; i++)
-+ drm_gem_object_put(job->bos[i]);
-+ kfree(job->bos);
-+}
-+
-+static void wait_fences(struct xarray *fence_array)
-+{
-+ struct dma_fence *fence;
-+ unsigned long id;
-+
-+ xa_for_each(fence_array, id, fence) {
-+ dma_fence_wait(fence, false);
-+ }
-+}
-+
-+static int
-+submit_cmd_geometry(struct pvr_device *pvr_dev, struct pvr_file *pvr_file,
-+ struct pvr_context_render *ctx_render,
-+ struct drm_pvr_ioctl_submit_job_args *args,
-+ struct drm_pvr_job_render_args *render_args, struct pvr_hwrt_data *hwrt,
-+ struct rogue_fwif_cmd_geom *cmd_geom, struct dma_fence **out_fence_out)
-+{
-+ struct rogue_fwif_cmd_geom_frag_shared *cmd_shared = &cmd_geom->cmd_shared;
-+ struct pvr_context_geom *ctx_geom = &ctx_render->ctx_geom;
-+ struct drm_syncobj *out_syncobj;
-+ struct rogue_fwif_ufo out_ufo;
-+ struct dma_fence *out_fence;
-+ struct xarray in_fences;
-+ u32 ctx_fw_addr;
-+ int err;
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(hwrt->fw_obj, &cmd_shared->hwrt_data_fw_addr));
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(ctx_render->fw_obj, &ctx_fw_addr));
-+
-+ out_fence = pvr_fence_create(&ctx_geom->cccb.pvr_fence_context);
-+ if (IS_ERR(out_fence)) {
-+ err = PTR_ERR(out_fence);
-+ goto err_out;
-+ }
-+
-+ err = pvr_fence_to_ufo(out_fence, &out_ufo);
-+ if (err)
-+ goto err_put_out_fence;
-+
-+ if (render_args->out_syncobj_geom) {
-+ out_syncobj = drm_syncobj_find(from_pvr_file(pvr_file),
-+ render_args->out_syncobj_geom);
-+ if (!out_syncobj) {
-+ err = -ENOENT;
-+ goto err_put_out_fence;
-+ }
-+ }
-+
-+ xa_init_flags(&in_fences, XA_FLAGS_ALLOC);
-+
-+ err = import_fences(pvr_file, render_args->num_in_syncobj_handles_geom,
-+ render_args->in_syncobj_handles_geom, &in_fences);
-+ if (err)
-+ goto err_put_out_syncobj;
-+
-+ /* Wait on fences */
-+ wait_fences(&in_fences);
-+
-+ pvr_cccb_lock(&ctx_geom->cccb);
-+
-+ /* Submit job to FW */
-+ err = pvr_cccb_write_command_with_header(&ctx_geom->cccb, ROGUE_FWIF_CCB_CMD_TYPE_GEOM,
-+ sizeof(*cmd_geom), cmd_geom, args->ext_job_ref, 0);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ err = pvr_cccb_write_command_with_header(&ctx_geom->cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE,
-+ sizeof(out_ufo), &out_ufo, args->ext_job_ref, 0);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ err = pvr_cccb_unlock_send_kccb_kick(pvr_dev, &ctx_geom->cccb, ctx_fw_addr, hwrt);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ /* Signal completion of geometry job */
-+ if (render_args->out_syncobj_geom) {
-+ drm_syncobj_replace_fence(out_syncobj, out_fence);
-+ drm_syncobj_put(out_syncobj);
-+ }
-+
-+ /* Write out fence to be used as input by fragment job. */
-+ *out_fence_out = out_fence;
-+ release_fences(&in_fences);
-+
-+ return 0;
-+
-+err_cccb_unlock_rollback:
-+ pvr_cccb_unlock_rollback(&ctx_geom->cccb);
-+
-+ release_fences(&in_fences);
-+
-+err_put_out_syncobj:
-+ if (render_args->out_syncobj_geom)
-+ drm_syncobj_put(out_syncobj);
-+
-+err_put_out_fence:
-+ /* As out_fence will now never be signaled, we need to drop two references here. */
-+ dma_fence_put(out_fence);
-+ dma_fence_put(out_fence);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+submit_cmd_fragment(struct pvr_device *pvr_dev, struct pvr_file *pvr_file,
-+ struct pvr_context_render *ctx_render,
-+ struct drm_pvr_ioctl_submit_job_args *args,
-+ struct drm_pvr_job_render_args *render_args, struct pvr_hwrt_data *hwrt,
-+ struct rogue_fwif_cmd_frag *cmd_frag, struct dma_fence *geom_in_fence)
-+{
-+ struct rogue_fwif_cmd_geom_frag_shared *cmd_shared = &cmd_frag->cmd_shared;
-+ struct pvr_context_frag *ctx_frag = &ctx_render->ctx_frag;
-+ struct drm_syncobj *out_syncobj;
-+ struct rogue_fwif_ufo out_ufo;
-+ struct dma_fence *out_fence;
-+ struct xarray in_fences;
-+ u32 ctx_fw_addr;
-+ int err;
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(hwrt->fw_obj, &cmd_shared->hwrt_data_fw_addr));
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(ctx_render->fw_obj, &ctx_fw_addr));
-+ ctx_fw_addr += offsetof(struct rogue_fwif_fwrendercontext, frag_context);
-+
-+ out_fence = pvr_fence_create(&ctx_frag->cccb.pvr_fence_context);
-+ if (IS_ERR(out_fence)) {
-+ err = PTR_ERR(out_fence);
-+ goto err_out;
-+ }
-+
-+ err = pvr_fence_to_ufo(out_fence, &out_ufo);
-+ if (err)
-+ goto err_put_out_fence;
-+
-+ if (geom_in_fence) {
-+ /*
-+ * Add dependency on geometry fence to the out fence, to ensure the former doesn't
-+ * get freed while it's still being waited on.
-+ */
-+ dma_fence_get(geom_in_fence);
-+ pvr_fence_add_fence_dependency(out_fence, geom_in_fence);
-+ }
-+
-+ if (render_args->out_syncobj_frag) {
-+ out_syncobj = drm_syncobj_find(from_pvr_file(pvr_file),
-+ render_args->out_syncobj_frag);
-+ if (!out_syncobj) {
-+ err = -ENOENT;
-+ goto err_put_out_fence;
-+ }
-+ }
-+
-+ xa_init_flags(&in_fences, XA_FLAGS_ALLOC);
-+
-+ err = import_fences(pvr_file, render_args->num_in_syncobj_handles_frag,
-+ render_args->in_syncobj_handles_frag, &in_fences);
-+ if (err)
-+ goto err_put_out_syncobj;
-+
-+ /* Wait on fences */
-+ wait_fences(&in_fences);
-+
-+ pvr_cccb_lock(&ctx_frag->cccb);
-+
-+ if (geom_in_fence) {
-+ struct rogue_fwif_ufo geom_in_ufo;
-+
-+ err = pvr_fence_to_ufo(geom_in_fence, &geom_in_ufo);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ err = pvr_cccb_write_command_with_header(&ctx_frag->cccb,
-+ ROGUE_FWIF_CCB_CMD_TYPE_FENCE,
-+ sizeof(geom_in_ufo), &geom_in_ufo,
-+ args->ext_job_ref, 0);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+ }
-+
-+ /* Submit job to FW */
-+ err = pvr_cccb_write_command_with_header(&ctx_frag->cccb, ROGUE_FWIF_CCB_CMD_TYPE_FRAG,
-+ sizeof(*cmd_frag), cmd_frag, args->ext_job_ref, 0);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ err = pvr_cccb_write_command_with_header(&ctx_frag->cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE,
-+ sizeof(out_ufo), &out_ufo, args->ext_job_ref, 0);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ err = pvr_cccb_unlock_send_kccb_kick(pvr_dev, &ctx_frag->cccb, ctx_fw_addr, hwrt);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ /* Signal completion of fragment job */
-+ if (render_args->out_syncobj_frag) {
-+ drm_syncobj_replace_fence(out_syncobj, out_fence);
-+ drm_syncobj_put(out_syncobj);
-+ }
-+
-+ dma_fence_put(out_fence);
-+ release_fences(&in_fences);
-+
-+ return 0;
-+
-+err_cccb_unlock_rollback:
-+ pvr_cccb_unlock_rollback(&ctx_frag->cccb);
-+
-+ release_fences(&in_fences);
-+
-+err_put_out_syncobj:
-+ if (render_args->out_syncobj_frag)
-+ drm_syncobj_put(out_syncobj);
-+
-+err_put_out_fence:
-+ /* As out_fence will now never be signaled, we need to drop two references here. */
-+ dma_fence_put(out_fence);
-+ dma_fence_put(out_fence);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+submit_cmd_compute(struct pvr_device *pvr_dev, struct pvr_file *pvr_file,
-+ struct pvr_context_compute *ctx_compute,
-+ struct drm_pvr_ioctl_submit_job_args *args,
-+ struct drm_pvr_job_compute_args *compute_args,
-+ struct rogue_fwif_cmd_compute *cmd_compute)
-+{
-+ struct drm_syncobj *out_syncobj;
-+ struct rogue_fwif_ufo out_ufo;
-+ struct dma_fence *out_fence;
-+ struct xarray in_fences;
-+ u32 ctx_fw_addr;
-+ int err;
-+
-+ WARN_ON(!pvr_gem_get_fw_addr(ctx_compute->fw_obj, &ctx_fw_addr));
-+
-+ out_fence = pvr_fence_create(&ctx_compute->cccb.pvr_fence_context);
-+ if (IS_ERR(out_fence)) {
-+ err = PTR_ERR(out_fence);
-+ goto err_out;
-+ }
-+
-+ err = pvr_fence_to_ufo(out_fence, &out_ufo);
-+ if (err)
-+ goto err_put_out_fence;
-+
-+ if (compute_args->out_syncobj) {
-+ out_syncobj = drm_syncobj_find(from_pvr_file(pvr_file),
-+ compute_args->out_syncobj);
-+ if (!out_syncobj) {
-+ err = -ENOENT;
-+ goto err_put_out_fence;
-+ }
-+ }
-+
-+ xa_init_flags(&in_fences, XA_FLAGS_ALLOC);
-+
-+ err = import_fences(pvr_file, compute_args->num_in_syncobj_handles,
-+ compute_args->in_syncobj_handles, &in_fences);
-+ if (err)
-+ goto err_put_out_syncobj;
-+
-+ /* Wait on fences */
-+ wait_fences(&in_fences);
-+
-+ pvr_cccb_lock(&ctx_compute->cccb);
-+
-+ /* Submit job to FW */
-+ err = pvr_cccb_write_command_with_header(&ctx_compute->cccb, ROGUE_FWIF_CCB_CMD_TYPE_CDM,
-+ sizeof(*cmd_compute), cmd_compute,
-+ args->ext_job_ref, 0);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ err = pvr_cccb_write_command_with_header(&ctx_compute->cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE,
-+ sizeof(out_ufo), &out_ufo, args->ext_job_ref, 0);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ err = pvr_cccb_unlock_send_kccb_kick(pvr_dev, &ctx_compute->cccb, ctx_fw_addr, NULL);
-+ if (err)
-+ goto err_cccb_unlock_rollback;
-+
-+ /* Signal completion of compute job */
-+ if (compute_args->out_syncobj) {
-+ drm_syncobj_replace_fence(out_syncobj, out_fence);
-+ drm_syncobj_put(out_syncobj);
-+ }
-+
-+ dma_fence_put(out_fence);
-+ release_fences(&in_fences);
-+
-+ return 0;
-+
-+err_cccb_unlock_rollback:
-+ pvr_cccb_unlock_rollback(&ctx_compute->cccb);
-+
-+ release_fences(&in_fences);
-+
-+err_put_out_syncobj:
-+ if (compute_args->out_syncobj)
-+ drm_syncobj_put(out_syncobj);
-+
-+err_put_out_fence:
-+ /* As out_fence will now never be signaled, we need to drop two references here. */
-+ dma_fence_put(out_fence);
-+ dma_fence_put(out_fence);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+convert_cmd_geom(struct rogue_fwif_cmd_geom *cmd_geom, struct drm_pvr_cmd_geom *cmd_geom_user)
-+{
-+ struct drm_pvr_cmd_geom_format_1 *cmd_geom_format_1 =
-+ &cmd_geom_user->data.cmd_geom_format_1;
-+
-+ if (cmd_geom_user->format != DRM_PVR_CMD_GEOM_FORMAT_1 || cmd_geom_user->_padding_4)
-+ return -EINVAL;
-+
-+ if (cmd_geom_format_1->flags & ~DRM_PVR_SUBMIT_JOB_GEOM_CMD_FLAGS_MASK)
-+ return -EINVAL;
-+
-+ cmd_geom->cmd_shared.cmn.frame_num = cmd_geom_format_1->frame_num;
-+ /* HWRT and PR buffers filled out later. */
-+ cmd_geom->flags = cmd_geom_format_1->flags;
-+ /* PR fence filled out later. */
-+
-+ cmd_geom->geom_regs.vdm_ctrl_stream_base =
-+ cmd_geom_format_1->geom_regs.vdm_ctrl_stream_base;
-+ cmd_geom->geom_regs.tpu_border_colour_table =
-+ cmd_geom_format_1->geom_regs.tpu_border_colour_table;
-+ cmd_geom->geom_regs.ppp_ctrl = cmd_geom_format_1->geom_regs.ppp_ctrl;
-+ cmd_geom->geom_regs.te_psg = cmd_geom_format_1->geom_regs.te_psg;
-+ cmd_geom->geom_regs.tpu = cmd_geom_format_1->geom_regs.tpu;
-+ cmd_geom->geom_regs.vdm_context_resume_task0_size =
-+ cmd_geom_format_1->geom_regs.vdm_context_resume_task0_size;
-+ cmd_geom->geom_regs.pds_ctrl = cmd_geom_format_1->geom_regs.pds_ctrl;
-+ cmd_geom->geom_regs.view_idx = cmd_geom_format_1->geom_regs.view_idx;
-+
-+ return 0;
-+}
-+
-+static int
-+convert_cmd_frag(struct rogue_fwif_cmd_frag *cmd_frag, struct drm_pvr_cmd_frag *cmd_frag_user)
-+{
-+ struct drm_pvr_cmd_frag_format_1 *cmd_frag_format_1 =
-+ &cmd_frag_user->data.cmd_frag_format_1;
-+
-+ if (cmd_frag_user->format != DRM_PVR_CMD_FRAG_FORMAT_1 || cmd_frag_user->_padding_4)
-+ return -EINVAL;
-+
-+ if (cmd_frag_format_1->flags & ~DRM_PVR_SUBMIT_JOB_FRAG_CMD_FLAGS_MASK)
-+ return -EINVAL;
-+
-+ cmd_frag->cmd_shared.cmn.frame_num = cmd_frag_format_1->frame_num;
-+ /* HWRT and PR buffers filled out later. */
-+ cmd_frag->flags = cmd_frag_format_1->flags;
-+ cmd_frag->zls_stride = cmd_frag_format_1->zls_stride;
-+ cmd_frag->sls_stride = cmd_frag_format_1->sls_stride;
-+
-+ memcpy(cmd_frag->regs.usc_clear_register, cmd_frag_format_1->regs.usc_clear_register,
-+ sizeof(cmd_frag->regs.usc_clear_register));
-+ cmd_frag->regs.usc_pixel_output_ctrl = cmd_frag_format_1->regs.usc_pixel_output_ctrl;
-+ cmd_frag->regs.isp_bgobjdepth = cmd_frag_format_1->regs.isp_bgobjdepth;
-+ cmd_frag->regs.isp_bgobjvals = cmd_frag_format_1->regs.isp_bgobjvals;
-+ cmd_frag->regs.isp_aa = cmd_frag_format_1->regs.isp_aa;
-+ cmd_frag->regs.isp_ctl = cmd_frag_format_1->regs.isp_ctl;
-+ cmd_frag->regs.tpu = cmd_frag_format_1->regs.tpu;
-+ cmd_frag->regs.event_pixel_pds_info = cmd_frag_format_1->regs.event_pixel_pds_info;
-+ cmd_frag->regs.pixel_phantom = cmd_frag_format_1->regs.pixel_phantom;
-+ cmd_frag->regs.view_idx = cmd_frag_format_1->regs.view_idx;
-+ cmd_frag->regs.event_pixel_pds_data = cmd_frag_format_1->regs.event_pixel_pds_data;
-+ cmd_frag->regs.isp_scissor_base = cmd_frag_format_1->regs.isp_scissor_base;
-+ cmd_frag->regs.isp_dbias_base = cmd_frag_format_1->regs.isp_dbias_base;
-+ cmd_frag->regs.isp_oclqry_base = cmd_frag_format_1->regs.isp_oclqry_base;
-+ cmd_frag->regs.isp_zlsctl = cmd_frag_format_1->regs.isp_zlsctl;
-+ cmd_frag->regs.isp_zload_store_base = cmd_frag_format_1->regs.isp_zload_store_base;
-+ cmd_frag->regs.isp_stencil_load_store_base =
-+ cmd_frag_format_1->regs.isp_stencil_load_store_base;
-+ cmd_frag->regs.isp_zls_pixels = cmd_frag_format_1->regs.isp_zls_pixels;
-+ memcpy(cmd_frag->regs.pbe_word, cmd_frag_format_1->regs.pbe_word,
-+ sizeof(cmd_frag->regs.pbe_word));
-+ cmd_frag->regs.tpu_border_colour_table = cmd_frag_format_1->regs.tpu_border_colour_table;
-+ memcpy(cmd_frag->regs.pds_bgnd, cmd_frag_format_1->regs.pds_bgnd,
-+ sizeof(cmd_frag->regs.pds_bgnd));
-+ memcpy(cmd_frag->regs.pds_pr_bgnd, cmd_frag_format_1->regs.pds_pr_bgnd,
-+ sizeof(cmd_frag->regs.pds_pr_bgnd));
-+
-+ return 0;
-+}
-+
-+static int
-+convert_cmd_compute(struct rogue_fwif_cmd_compute *cmd_compute,
-+ struct drm_pvr_cmd_compute *cmd_compute_user)
-+{
-+ struct drm_pvr_cmd_compute_format_1 *cmd_compute_format_1 =
-+ &cmd_compute_user->data.cmd_compute_format_1;
-+
-+ if (cmd_compute_user->format != DRM_PVR_CMD_COMPUTE_FORMAT_1 ||
-+ cmd_compute_user->_padding_4)
-+ return -EINVAL;
-+
-+ if (cmd_compute_format_1->flags & ~DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_FLAGS_MASK)
-+ return -EINVAL;
-+
-+ cmd_compute->common.frame_num = cmd_compute_format_1->frame_num;
-+ cmd_compute->flags = cmd_compute_format_1->flags;
-+
-+ cmd_compute->cmd_regs.tpu_border_colour_table =
-+ cmd_compute_format_1->regs.tpu_border_colour_table;
-+ cmd_compute->cmd_regs.cdm_item = cmd_compute_format_1->regs.cdm_item;
-+ cmd_compute->cmd_regs.compute_cluster = cmd_compute_format_1->regs.compute_cluster;
-+ cmd_compute->cmd_regs.cdm_ctrl_stream_base =
-+ cmd_compute_format_1->regs.cdm_ctrl_stream_base;
-+ cmd_compute->cmd_regs.tpu = cmd_compute_format_1->regs.tpu;
-+ cmd_compute->cmd_regs.cdm_resume_pds1 = cmd_compute_format_1->regs.cdm_resume_pds1;
-+
-+ return 0;
-+}
-+
-+static int
-+pvr_fw_cmd_geom_init(struct drm_pvr_job_render_args *render_args,
-+ struct rogue_fwif_cmd_geom **cmd_geom_out)
-+{
-+ struct drm_pvr_cmd_geom *cmd_geom_user;
-+ struct rogue_fwif_cmd_geom *cmd_geom;
-+ int err;
-+
-+ cmd_geom_user = kzalloc(sizeof(*cmd_geom_user), GFP_KERNEL);
-+ if (!cmd_geom_user) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ cmd_geom = kzalloc(sizeof(*cmd_geom), GFP_KERNEL);
-+ if (!cmd_geom) {
-+ err = -ENOMEM;
-+ goto err_free_cmd_geom_user;
-+ }
-+
-+ if (copy_from_user(cmd_geom_user, u64_to_user_ptr(render_args->cmd_geom),
-+ sizeof(*cmd_geom_user))) {
-+ err = -EFAULT;
-+ goto err_free_cmd_geom;
-+ }
-+
-+ err = convert_cmd_geom(cmd_geom, cmd_geom_user);
-+ if (err)
-+ goto err_free_cmd_geom;
-+
-+ kfree(cmd_geom_user);
-+
-+ *cmd_geom_out = cmd_geom;
-+
-+ return 0;
-+
-+err_free_cmd_geom:
-+ kfree(cmd_geom);
-+
-+err_free_cmd_geom_user:
-+ kfree(cmd_geom_user);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_fw_cmd_frag_init(struct drm_pvr_job_render_args *render_args,
-+ struct rogue_fwif_cmd_frag **cmd_frag_out)
-+{
-+ struct drm_pvr_cmd_frag *cmd_frag_user;
-+ struct rogue_fwif_cmd_frag *cmd_frag;
-+ int err;
-+
-+ cmd_frag_user = kzalloc(sizeof(*cmd_frag_user), GFP_KERNEL);
-+ if (!cmd_frag_user) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ cmd_frag = kzalloc(sizeof(*cmd_frag), GFP_KERNEL);
-+ if (!cmd_frag) {
-+ err = -ENOMEM;
-+ goto err_free_cmd_frag_user;
-+ }
-+
-+ if (copy_from_user(cmd_frag_user, u64_to_user_ptr(render_args->cmd_frag),
-+ sizeof(*cmd_frag_user))) {
-+ err = -EFAULT;
-+ goto err_free_cmd_frag;
-+ }
-+
-+ err = convert_cmd_frag(cmd_frag, cmd_frag_user);
-+ if (err)
-+ goto err_free_cmd_frag;
-+
-+ kfree(cmd_frag_user);
-+
-+ *cmd_frag_out = cmd_frag;
-+
-+ return 0;
-+
-+err_free_cmd_frag:
-+ kfree(cmd_frag);
-+
-+err_free_cmd_frag_user:
-+ kfree(cmd_frag_user);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_fw_cmd_compute_init(struct drm_pvr_job_compute_args *compute_args,
-+ struct rogue_fwif_cmd_compute **cmd_compute_out)
-+{
-+ struct drm_pvr_cmd_compute *cmd_compute_user;
-+ struct rogue_fwif_cmd_compute *cmd_compute;
-+ int err;
-+
-+ cmd_compute_user = kzalloc(sizeof(*cmd_compute_user), GFP_KERNEL);
-+ if (!cmd_compute_user) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ cmd_compute = kzalloc(sizeof(*cmd_compute), GFP_KERNEL);
-+ if (!cmd_compute) {
-+ err = -ENOMEM;
-+ goto err_free_cmd_compute_user;
-+ }
-+
-+ if (copy_from_user(cmd_compute_user, u64_to_user_ptr(compute_args->cmd),
-+ sizeof(*cmd_compute_user))) {
-+ err = -EFAULT;
-+ goto err_free_cmd_compute;
-+ }
-+
-+ err = convert_cmd_compute(cmd_compute, cmd_compute_user);
-+ if (err)
-+ goto err_free_cmd_compute;
-+
-+ kfree(cmd_compute_user);
-+
-+ *cmd_compute_out = cmd_compute;
-+
-+ return 0;
-+
-+err_free_cmd_compute:
-+ kfree(cmd_compute);
-+
-+err_free_cmd_compute_user:
-+ kfree(cmd_compute_user);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_process_job_render(struct pvr_device *pvr_dev,
-+ struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_submit_job_args *args,
-+ struct drm_pvr_job_render_args *render_args,
-+ struct pvr_job *job)
-+{
-+ struct pvr_context_render *ctx_render;
-+ struct rogue_fwif_cmd_geom *cmd_geom;
-+ struct rogue_fwif_cmd_frag *cmd_frag;
-+ struct xarray implicit_fences;
-+ struct dma_fence *geom_fence = NULL;
-+ struct pvr_hwrt_data *hwrt;
-+ int err;
-+
-+ /* Copy commands from userspace. */
-+ if (render_args->cmd_geom) {
-+ err = pvr_fw_cmd_geom_init(render_args, &cmd_geom);
-+ if (err)
-+ goto err_out;
-+ }
-+ if (render_args->cmd_frag) {
-+ err = pvr_fw_cmd_frag_init(render_args, &cmd_frag);
-+ if (err)
-+ goto err_free_cmd_geom;
-+ }
-+
-+ hwrt = pvr_hwrt_data_get(pvr_file, render_args->hwrt_data_set_handle,
-+ render_args->hwrt_data_index);
-+ if (!hwrt) {
-+ err = -EINVAL;
-+ goto err_free_cmd_frag;
-+ }
-+
-+ job->ctx = pvr_context_get(pvr_file, args->context_handle);
-+ if (!job->ctx) {
-+ err = -EINVAL;
-+ goto err_put_hwrt;
-+ }
-+ ctx_render = to_pvr_context_render(job->ctx);
-+
-+ xa_init_flags(&implicit_fences, XA_FLAGS_ALLOC);
-+
-+ err = import_implicit_fences(pvr_file, job, render_args->num_bo_handles,
-+ render_args->bo_handles, &implicit_fences);
-+ if (err)
-+ goto err_put_context;
-+
-+ /* Wait on implicit fences */
-+ wait_fences(&implicit_fences);
-+
-+ if (render_args->cmd_geom) {
-+ err = submit_cmd_geometry(pvr_dev, pvr_file, ctx_render, args, render_args, hwrt,
-+ cmd_geom, &geom_fence);
-+ if (err)
-+ goto err_release_implicit_fences;
-+ }
-+
-+ if (render_args->cmd_frag) {
-+ err = submit_cmd_fragment(pvr_dev, pvr_file, ctx_render, args, render_args, hwrt,
-+ cmd_frag, geom_fence);
-+ if (err)
-+ goto err_put_geom_fence;
-+ }
-+
-+ dma_fence_put(geom_fence);
-+ release_implicit_fences(job, &implicit_fences);
-+ pvr_context_put(job->ctx);
-+ pvr_hwrt_data_put(hwrt);
-+
-+ kfree(cmd_frag);
-+ kfree(cmd_geom);
-+
-+ return 0;
-+
-+err_put_geom_fence:
-+ dma_fence_put(geom_fence);
-+
-+err_release_implicit_fences:
-+ release_implicit_fences(job, &implicit_fences);
-+
-+err_put_context:
-+ pvr_context_put(job->ctx);
-+
-+err_put_hwrt:
-+ pvr_hwrt_data_put(hwrt);
-+
-+err_free_cmd_frag:
-+ if (render_args->cmd_frag)
-+ kfree(cmd_frag);
-+
-+err_free_cmd_geom:
-+ if (render_args->cmd_geom)
-+ kfree(cmd_geom);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_process_job_compute(struct pvr_device *pvr_dev,
-+ struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_submit_job_args *args,
-+ struct drm_pvr_job_compute_args *compute_args,
-+ struct pvr_job *job)
-+{
-+ struct rogue_fwif_cmd_compute *cmd_compute;
-+ struct pvr_context_compute *ctx_compute;
-+ struct xarray implicit_fences;
-+ int err;
-+
-+ /* Copy commands from userspace. */
-+ if (!compute_args->cmd || compute_args->_padding_24) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ err = pvr_fw_cmd_compute_init(compute_args, &cmd_compute);
-+ if (err)
-+ goto err_out;
-+
-+ job->ctx = pvr_context_get(pvr_file, args->context_handle);
-+ if (!job->ctx) {
-+ err = -EINVAL;
-+ goto err_free_cmd_compute;
-+ }
-+ ctx_compute = to_pvr_context_compute(job->ctx);
-+
-+ xa_init_flags(&implicit_fences, XA_FLAGS_ALLOC);
-+
-+ err = import_implicit_fences(pvr_file, job, compute_args->num_bo_handles,
-+ compute_args->bo_handles, &implicit_fences);
-+ if (err)
-+ goto err_put_context;
-+
-+ /* Wait on implicit fences */
-+ wait_fences(&implicit_fences);
-+
-+ err = submit_cmd_compute(pvr_dev, pvr_file, ctx_compute, args, compute_args, cmd_compute);
-+ if (err)
-+ goto err_release_implicit_fences;
-+
-+ release_implicit_fences(job, &implicit_fences);
-+ pvr_context_put(job->ctx);
-+
-+ kfree(cmd_compute);
-+
-+ return 0;
-+
-+err_release_implicit_fences:
-+ release_implicit_fences(job, &implicit_fences);
-+
-+err_put_context:
-+ pvr_context_put(job->ctx);
-+
-+err_free_cmd_compute:
-+ kfree(cmd_compute);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_submit_job() - Submit a job to the GPU
-+ * @pvr_dev: Target PowerVR device.
-+ * @pvr_file: Pointer to PowerVR file structure.
-+ * @args: IOCTL arguments.
-+ *
-+ * This initial implementation is entirely synchronous; on return the GPU will
-+ * be idle. This will not be the case for future implementations.
-+ *
-+ * Returns:
-+ * * 0 on success,
-+ * * -%EFAULT if arguments can not be copied from user space,
-+ * * -%EINVAL on invalid arguments, or
-+ * * Any other error.
-+ */
-+int
-+pvr_submit_job(struct pvr_device *pvr_dev,
-+ struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_submit_job_args *args)
-+{
-+ struct pvr_job *job;
-+ int err;
-+
-+ if (args->_padding_c) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ job = kzalloc(sizeof(*job), GFP_KERNEL);
-+ if (!job) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ job->type = args->job_type;
-+
-+ /* Process arguments based on job type */
-+ switch (job->type) {
-+ case DRM_PVR_JOB_TYPE_RENDER: {
-+ struct drm_pvr_job_render_args render_args;
-+
-+ if (copy_from_user(&render_args, u64_to_user_ptr(args->data),
-+ sizeof(render_args))) {
-+ err = -EFAULT;
-+ goto err_free;
-+ }
-+
-+ err = pvr_process_job_render(pvr_dev, pvr_file, args, &render_args, job);
-+ if (err)
-+ goto err_free;
-+ break;
-+ }
-+
-+ case DRM_PVR_JOB_TYPE_COMPUTE: {
-+ struct drm_pvr_job_compute_args compute_args;
-+
-+ if (copy_from_user(&compute_args, u64_to_user_ptr(args->data),
-+ sizeof(compute_args))) {
-+ err = -EFAULT;
-+ goto err_free;
-+ }
-+
-+ err = pvr_process_job_compute(pvr_dev, pvr_file, args, &compute_args, job);
-+ if (err)
-+ goto err_free;
-+ break;
-+ }
-+
-+ default:
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ kfree(job);
-+
-+ return 0;
-+
-+err_free:
-+ kfree(job);
-+
-+err_out:
-+ return err;
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_job.h b/drivers/gpu/drm/imagination/pvr_job.h
-new file mode 100644
-index 000000000000..c65d800627f1
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_job.h
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_JOB_H__
-+#define __PVR_JOB_H__
-+
-+#include <uapi/drm/pvr_drm.h>
-+
-+#include <linux/types.h>
-+
-+#include <drm/drm_gem.h>
-+
-+/* Forward declaration from "pvr_context.h". */
-+struct pvr_context;
-+
-+/* Forward declarations from "pvr_device.h". */
-+struct pvr_device;
-+struct pvr_file;
-+
-+struct pvr_job {
-+ enum drm_pvr_job_type type;
-+
-+ struct pvr_context *ctx;
-+
-+ u32 num_bos;
-+ struct drm_gem_object **bos;
-+};
-+
-+int pvr_submit_job(struct pvr_device *pvr_dev, struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_submit_job_args *args);
-+
-+#endif /* __PVR_JOB_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_object.c b/drivers/gpu/drm/imagination/pvr_object.c
-new file mode 100644
-index 000000000000..54318ffe7887
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_object.c
-@@ -0,0 +1,223 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_free_list.h"
-+#include "pvr_gem.h"
-+#include "pvr_hwrt.h"
-+#include "pvr_object.h"
-+
-+#include <linux/xarray.h>
-+#include <uapi/drm/pvr_drm.h>
-+
-+static void
-+destroy_object(struct pvr_object *obj)
-+{
-+ switch (obj->type) {
-+ case DRM_PVR_OBJECT_TYPE_FREE_LIST: {
-+ struct pvr_free_list *free_list = to_pvr_free_list(obj);
-+
-+ pvr_free_list_destroy(free_list);
-+ break;
-+ }
-+ case DRM_PVR_OBJECT_TYPE_HWRT_DATASET: {
-+ struct pvr_hwrt_dataset *hwrt = to_pvr_hwrt_dataset(obj);
-+
-+ pvr_hwrt_dataset_destroy(hwrt);
-+ break;
-+ }
-+ case DRM_PVR_OBJECT_TYPE_MAX:
-+ default:
-+ WARN_ON(1);
-+ break;
-+ }
-+}
-+
-+/**
-+ * pvr_object_create() - Create an object from parameters from userspace
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @args: Creation arguments from userspace.
-+ * @handle_out: Output handle pointer.
-+ *
-+ * The context is initialised with refcount of 1.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EINVAL on invalid arguments, or
-+ * * -%ENOMEM on out-of-memory, or
-+ * * -%EFAULT if arguments can't be copied from userspace, or
-+ * * Any error returned by pvr_free_list_create().
-+ */
-+int
-+pvr_object_create(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_object_args *args,
-+ u32 *handle_out)
-+{
-+ struct pvr_object *obj;
-+ u32 handle;
-+ int err;
-+
-+ switch (args->type) {
-+ case DRM_PVR_OBJECT_TYPE_FREE_LIST: {
-+ struct drm_pvr_ioctl_create_free_list_args free_list_args;
-+ struct pvr_free_list *free_list;
-+
-+ if (copy_from_user(&free_list_args, u64_to_user_ptr(args->data),
-+ sizeof(free_list_args))) {
-+ err = -EFAULT;
-+ goto err_out;
-+ }
-+
-+ free_list = pvr_free_list_create(pvr_file, &free_list_args);
-+ if (IS_ERR(free_list)) {
-+ err = PTR_ERR(free_list);
-+ goto err_out;
-+ }
-+ obj = from_pvr_free_list(free_list);
-+ break;
-+ }
-+
-+ case DRM_PVR_OBJECT_TYPE_HWRT_DATASET: {
-+ struct drm_pvr_ioctl_create_hwrt_dataset_args hwrt_args;
-+ struct pvr_hwrt_dataset *hwrt;
-+
-+ if (copy_from_user(&hwrt_args, u64_to_user_ptr(args->data),
-+ sizeof(hwrt_args))) {
-+ err = -EFAULT;
-+ goto err_out;
-+ }
-+
-+ hwrt = pvr_hwrt_dataset_create(pvr_file, &hwrt_args);
-+ if (IS_ERR(hwrt)) {
-+ err = PTR_ERR(hwrt);
-+ goto err_out;
-+ }
-+ obj = from_pvr_hwrt_dataset(hwrt);
-+ break;
-+ }
-+
-+ case DRM_PVR_OBJECT_TYPE_MAX:
-+ default:
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+ if (IS_ERR(obj)) {
-+ err = PTR_ERR(obj);
-+ goto err_out;
-+ }
-+
-+ kref_init(&obj->ref_count);
-+
-+ /* Add to object list, and get handle */
-+ err = xa_alloc(&pvr_file->objects, &handle, obj, xa_limit_1_32b,
-+ GFP_KERNEL);
-+ if (err < 0)
-+ goto err_destroy_object;
-+
-+ *handle_out = handle;
-+ return 0;
-+
-+err_destroy_object:
-+ destroy_object(obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+pvr_object_release(struct kref *ref_count)
-+{
-+ struct pvr_object *obj =
-+ container_of(ref_count, struct pvr_object, ref_count);
-+
-+ destroy_object(obj);
-+}
-+
-+/**
-+ * pvr_object_put() - Release reference on object
-+ * @obj: Target object.
-+ */
-+void
-+pvr_object_put(struct pvr_object *obj)
-+{
-+ kref_put(&obj->ref_count, pvr_object_release);
-+}
-+
-+/**
-+ * pvr_object_destroy() - Destroy object
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @handle: Object handle.
-+ *
-+ * Removes object from list and drops initial reference. Object will then be
-+ * destroyed once all outstanding references are dropped.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%EINVAL if object not in object list.
-+ */
-+int
-+pvr_object_destroy(struct pvr_file *pvr_file, u32 handle)
-+{
-+ struct pvr_object *obj = xa_erase(&pvr_file->objects, handle);
-+
-+ if (!obj)
-+ return -EINVAL;
-+
-+ pvr_object_put(obj);
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_object_cleanup() - Send FW cleanup request for an object
-+ * @pvr_dev: Target PowerVR device.
-+ * @type: Type of object to cleanup. Must be one of &enum rogue_fwif_cleanup_type.
-+ * @fw_obj: Pointer to FW object containing object to cleanup.
-+ * @offset: Offset within FW object of object to cleanup.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -EBUSY on timeout.
-+ */
-+int
-+pvr_object_cleanup(struct pvr_device *pvr_dev, u32 type, struct pvr_fw_object *fw_obj, u32 offset)
-+{
-+ struct rogue_fwif_kccb_cmd cmd;
-+ int slot_nr;
-+ int err;
-+
-+ struct rogue_fwif_cleanup_request *cleanup_req = &cmd.cmd_data.cleanup_data;
-+
-+ cmd.cmd_type = ROGUE_FWIF_KCCB_CMD_CLEANUP;
-+ cmd.kccb_flags = 0;
-+ cleanup_req->cleanup_type = type;
-+
-+ switch (type) {
-+ case ROGUE_FWIF_CLEANUP_FWCOMMONCONTEXT:
-+ WARN_ON(!pvr_gem_get_fw_addr_offset(fw_obj, offset,
-+ &cleanup_req->cleanup_data.context_fw_addr));
-+ break;
-+ case ROGUE_FWIF_CLEANUP_HWRTDATA:
-+ WARN_ON(!pvr_gem_get_fw_addr_offset(fw_obj, offset,
-+ &cleanup_req->cleanup_data.hwrt_data_fw_addr));
-+ break;
-+ case ROGUE_FWIF_CLEANUP_FREELIST:
-+ WARN_ON(!pvr_gem_get_fw_addr_offset(fw_obj, offset,
-+ &cleanup_req->cleanup_data.freelist_fw_addr));
-+ break;
-+ default:
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ err = pvr_kccb_send_cmd(pvr_dev, &cmd, &slot_nr);
-+ if (err)
-+ goto err_out;
-+
-+ err = pvr_kccb_wait_for_completion(pvr_dev, slot_nr, HZ);
-+ if (err)
-+ goto err_out;
-+
-+err_out:
-+ return err;
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_object.h b/drivers/gpu/drm/imagination/pvr_object.h
-new file mode 100644
-index 000000000000..f1973632f718
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_object.h
-@@ -0,0 +1,60 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_OBJECT_H__
-+#define __PVR_OBJECT_H__
-+
-+#include <linux/compiler_attributes.h>
-+#include <linux/kref.h>
-+#include <linux/list.h>
-+#include <linux/types.h>
-+#include <linux/xarray.h>
-+#include <uapi/drm/pvr_drm.h>
-+
-+#include "pvr_device.h"
-+
-+/**
-+ * struct pvr_object - Common object structure
-+ */
-+struct pvr_object {
-+ /** @type: Type of object. Must be one of &enum drm_pvr_object_type. */
-+ enum drm_pvr_object_type type;
-+
-+ /** @ref_count: Reference count of object. */
-+ struct kref ref_count;
-+};
-+
-+int pvr_object_create(struct pvr_file *pvr_file,
-+ struct drm_pvr_ioctl_create_object_args *args,
-+ u32 *handle_out);
-+
-+/**
-+ * pvr_object_get() - Get object pointer from handle
-+ * @pvr_file: Pointer to pvr_file structure.
-+ * @handle: Object handle.
-+ *
-+ * Takes reference on object. Call pvr_object_put() to release.
-+ *
-+ * Returns:
-+ * * The requested object on success, or
-+ * * %NULL on failure (object is not in object list)
-+ */
-+static __always_inline struct pvr_object *
-+pvr_object_get(struct pvr_file *pvr_file, u32 handle)
-+{
-+ struct pvr_object *obj = xa_load(&pvr_file->objects, handle);
-+
-+ if (obj)
-+ kref_get(&obj->ref_count);
-+
-+ return obj;
-+}
-+
-+void pvr_object_put(struct pvr_object *obj);
-+
-+int pvr_object_destroy(struct pvr_file *pvr_file, u32 handle);
-+
-+int
-+pvr_object_cleanup(struct pvr_device *pvr_dev, u32 type, struct pvr_fw_object *fw_obj, u32 offset);
-+
-+#endif /* __PVR_OBJECT_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
-new file mode 100644
-index 000000000000..4ffa3df14325
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
-@@ -0,0 +1,6191 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+/* *** Autogenerated C -- do not edit *** */
-+
-+#ifndef __PVR_ROGUE_CR_DEFS_H__
-+#define __PVR_ROGUE_CR_DEFS_H__
-+
-+/* clang-format off */
-+
-+#define ROGUE_CR_DEFS_REVISION 1
-+
-+/* Register ROGUE_CR_RASTERISATION_INDIRECT */
-+#define ROGUE_CR_RASTERISATION_INDIRECT 0x8238U
-+#define ROGUE_CR_RASTERISATION_INDIRECT_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
-+
-+/* Register ROGUE_CR_PBE_INDIRECT */
-+#define ROGUE_CR_PBE_INDIRECT 0x83E0U
-+#define ROGUE_CR_PBE_INDIRECT_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_PBE_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_PBE_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
-+
-+/* Register ROGUE_CR_PBE_PERF_INDIRECT */
-+#define ROGUE_CR_PBE_PERF_INDIRECT 0x83D8U
-+#define ROGUE_CR_PBE_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
-+
-+/* Register ROGUE_CR_TPU_PERF_INDIRECT */
-+#define ROGUE_CR_TPU_PERF_INDIRECT 0x83F0U
-+#define ROGUE_CR_TPU_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
-+#define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U
-+
-+/* Register ROGUE_CR_RASTERISATION_PERF_INDIRECT */
-+#define ROGUE_CR_RASTERISATION_PERF_INDIRECT 0x8318U
-+#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
-+
-+/* Register ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT */
-+#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT 0x8028U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U
-+
-+/* Register ROGUE_CR_USC_PERF_INDIRECT */
-+#define ROGUE_CR_USC_PERF_INDIRECT 0x8030U
-+#define ROGUE_CR_USC_PERF_INDIRECT_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U
-+
-+/* Register ROGUE_CR_BLACKPEARL_INDIRECT */
-+#define ROGUE_CR_BLACKPEARL_INDIRECT 0x8388U
-+#define ROGUE_CR_BLACKPEARL_INDIRECT_MASKFULL 0x0000000000000003ULL
-+#define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU
-+
-+/* Register ROGUE_CR_BLACKPEARL_PERF_INDIRECT */
-+#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT 0x83F8U
-+#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
-+#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU
-+
-+/* Register ROGUE_CR_TEXAS3_PERF_INDIRECT */
-+#define ROGUE_CR_TEXAS3_PERF_INDIRECT 0x83D0U
-+#define ROGUE_CR_TEXAS3_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL
-+#define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U
-+
-+/* Register ROGUE_CR_TEXAS_PERF_INDIRECT */
-+#define ROGUE_CR_TEXAS_PERF_INDIRECT 0x8288U
-+#define ROGUE_CR_TEXAS_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
-+#define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU
-+
-+/* Register ROGUE_CR_BX_TU_PERF_INDIRECT */
-+#define ROGUE_CR_BX_TU_PERF_INDIRECT 0xC900U
-+#define ROGUE_CR_BX_TU_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL
-+#define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU
-+
-+/* Register ROGUE_CR_CLK_CTRL */
-+#define ROGUE_CR_CLK_CTRL 0x0000U
-+#define ROGUE_CR_CLK_CTRL__PBE2_XE__MASKFULL 0xFFFFFF003F3FFFFFULL
-+#define ROGUE_CR_CLK_CTRL__S7_TOP__MASKFULL 0xCFCF03000F3F3F0FULL
-+#define ROGUE_CR_CLK_CTRL_MASKFULL 0xFFFFFF003F3FFFFFULL
-+#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_SHIFT 62U
-+#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_CLRMSK 0x3FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_ON 0x4000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_BIF_TEXAS_AUTO 0x8000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_IPP_SHIFT 60U
-+#define ROGUE_CR_CLK_CTRL_IPP_CLRMSK 0xCFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_IPP_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_IPP_ON 0x1000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_IPP_AUTO 0x2000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FBC_SHIFT 58U
-+#define ROGUE_CR_CLK_CTRL_FBC_CLRMSK 0xF3FFFFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_FBC_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FBC_ON 0x0400000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FBC_AUTO 0x0800000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FBDC_SHIFT 56U
-+#define ROGUE_CR_CLK_CTRL_FBDC_CLRMSK 0xFCFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_FBDC_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FBDC_ON 0x0100000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FBDC_AUTO 0x0200000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_SHIFT 54U
-+#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_CLRMSK 0xFF3FFFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_ON 0x0040000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_FB_TLCACHE_AUTO 0x0080000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_USCS_SHIFT 52U
-+#define ROGUE_CR_CLK_CTRL_USCS_CLRMSK 0xFFCFFFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_USCS_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_USCS_ON 0x0010000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_USCS_AUTO 0x0020000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_PBE_SHIFT 50U
-+#define ROGUE_CR_CLK_CTRL_PBE_CLRMSK 0xFFF3FFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_PBE_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_PBE_ON 0x0004000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_PBE_AUTO 0x0008000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_MCU_L1_SHIFT 48U
-+#define ROGUE_CR_CLK_CTRL_MCU_L1_CLRMSK 0xFFFCFFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_MCU_L1_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_MCU_L1_ON 0x0001000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_MCU_L1_AUTO 0x0002000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_CDM_SHIFT 46U
-+#define ROGUE_CR_CLK_CTRL_CDM_CLRMSK 0xFFFF3FFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_CDM_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_CDM_ON 0x0000400000000000ULL
-+#define ROGUE_CR_CLK_CTRL_CDM_AUTO 0x0000800000000000ULL
-+#define ROGUE_CR_CLK_CTRL_SIDEKICK_SHIFT 44U
-+#define ROGUE_CR_CLK_CTRL_SIDEKICK_CLRMSK 0xFFFFCFFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_SIDEKICK_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_SIDEKICK_ON 0x0000100000000000ULL
-+#define ROGUE_CR_CLK_CTRL_SIDEKICK_AUTO 0x0000200000000000ULL
-+#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_SHIFT 42U
-+#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_CLRMSK 0xFFFFF3FFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_ON 0x0000040000000000ULL
-+#define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_AUTO 0x0000080000000000ULL
-+#define ROGUE_CR_CLK_CTRL_BIF_SHIFT 40U
-+#define ROGUE_CR_CLK_CTRL_BIF_CLRMSK 0xFFFFFCFFFFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_BIF_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_BIF_ON 0x0000010000000000ULL
-+#define ROGUE_CR_CLK_CTRL_BIF_AUTO 0x0000020000000000ULL
-+#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_SHIFT 28U
-+#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFCFFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_ON 0x0000000010000000ULL
-+#define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_AUTO 0x0000000020000000ULL
-+#define ROGUE_CR_CLK_CTRL_MCU_L0_SHIFT 26U
-+#define ROGUE_CR_CLK_CTRL_MCU_L0_CLRMSK 0xFFFFFFFFF3FFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_MCU_L0_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_MCU_L0_ON 0x0000000004000000ULL
-+#define ROGUE_CR_CLK_CTRL_MCU_L0_AUTO 0x0000000008000000ULL
-+#define ROGUE_CR_CLK_CTRL_TPU_SHIFT 24U
-+#define ROGUE_CR_CLK_CTRL_TPU_CLRMSK 0xFFFFFFFFFCFFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_TPU_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_TPU_ON 0x0000000001000000ULL
-+#define ROGUE_CR_CLK_CTRL_TPU_AUTO 0x0000000002000000ULL
-+#define ROGUE_CR_CLK_CTRL_USC_SHIFT 20U
-+#define ROGUE_CR_CLK_CTRL_USC_CLRMSK 0xFFFFFFFFFFCFFFFFULL
-+#define ROGUE_CR_CLK_CTRL_USC_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_USC_ON 0x0000000000100000ULL
-+#define ROGUE_CR_CLK_CTRL_USC_AUTO 0x0000000000200000ULL
-+#define ROGUE_CR_CLK_CTRL_TLA_SHIFT 18U
-+#define ROGUE_CR_CLK_CTRL_TLA_CLRMSK 0xFFFFFFFFFFF3FFFFULL
-+#define ROGUE_CR_CLK_CTRL_TLA_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_TLA_ON 0x0000000000040000ULL
-+#define ROGUE_CR_CLK_CTRL_TLA_AUTO 0x0000000000080000ULL
-+#define ROGUE_CR_CLK_CTRL_SLC_SHIFT 16U
-+#define ROGUE_CR_CLK_CTRL_SLC_CLRMSK 0xFFFFFFFFFFFCFFFFULL
-+#define ROGUE_CR_CLK_CTRL_SLC_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_SLC_ON 0x0000000000010000ULL
-+#define ROGUE_CR_CLK_CTRL_SLC_AUTO 0x0000000000020000ULL
-+#define ROGUE_CR_CLK_CTRL_UVS_SHIFT 14U
-+#define ROGUE_CR_CLK_CTRL_UVS_CLRMSK 0xFFFFFFFFFFFF3FFFULL
-+#define ROGUE_CR_CLK_CTRL_UVS_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_UVS_ON 0x0000000000004000ULL
-+#define ROGUE_CR_CLK_CTRL_UVS_AUTO 0x0000000000008000ULL
-+#define ROGUE_CR_CLK_CTRL_PDS_SHIFT 12U
-+#define ROGUE_CR_CLK_CTRL_PDS_CLRMSK 0xFFFFFFFFFFFFCFFFULL
-+#define ROGUE_CR_CLK_CTRL_PDS_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_PDS_ON 0x0000000000001000ULL
-+#define ROGUE_CR_CLK_CTRL_PDS_AUTO 0x0000000000002000ULL
-+#define ROGUE_CR_CLK_CTRL_VDM_SHIFT 10U
-+#define ROGUE_CR_CLK_CTRL_VDM_CLRMSK 0xFFFFFFFFFFFFF3FFULL
-+#define ROGUE_CR_CLK_CTRL_VDM_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_VDM_ON 0x0000000000000400ULL
-+#define ROGUE_CR_CLK_CTRL_VDM_AUTO 0x0000000000000800ULL
-+#define ROGUE_CR_CLK_CTRL_PM_SHIFT 8U
-+#define ROGUE_CR_CLK_CTRL_PM_CLRMSK 0xFFFFFFFFFFFFFCFFULL
-+#define ROGUE_CR_CLK_CTRL_PM_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_PM_ON 0x0000000000000100ULL
-+#define ROGUE_CR_CLK_CTRL_PM_AUTO 0x0000000000000200ULL
-+#define ROGUE_CR_CLK_CTRL_GPP_SHIFT 6U
-+#define ROGUE_CR_CLK_CTRL_GPP_CLRMSK 0xFFFFFFFFFFFFFF3FULL
-+#define ROGUE_CR_CLK_CTRL_GPP_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_GPP_ON 0x0000000000000040ULL
-+#define ROGUE_CR_CLK_CTRL_GPP_AUTO 0x0000000000000080ULL
-+#define ROGUE_CR_CLK_CTRL_TE_SHIFT 4U
-+#define ROGUE_CR_CLK_CTRL_TE_CLRMSK 0xFFFFFFFFFFFFFFCFULL
-+#define ROGUE_CR_CLK_CTRL_TE_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_TE_ON 0x0000000000000010ULL
-+#define ROGUE_CR_CLK_CTRL_TE_AUTO 0x0000000000000020ULL
-+#define ROGUE_CR_CLK_CTRL_TSP_SHIFT 2U
-+#define ROGUE_CR_CLK_CTRL_TSP_CLRMSK 0xFFFFFFFFFFFFFFF3ULL
-+#define ROGUE_CR_CLK_CTRL_TSP_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_TSP_ON 0x0000000000000004ULL
-+#define ROGUE_CR_CLK_CTRL_TSP_AUTO 0x0000000000000008ULL
-+#define ROGUE_CR_CLK_CTRL_ISP_SHIFT 0U
-+#define ROGUE_CR_CLK_CTRL_ISP_CLRMSK 0xFFFFFFFFFFFFFFFCULL
-+#define ROGUE_CR_CLK_CTRL_ISP_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL_ISP_ON 0x0000000000000001ULL
-+#define ROGUE_CR_CLK_CTRL_ISP_AUTO 0x0000000000000002ULL
-+
-+/* Register ROGUE_CR_CLK_STATUS */
-+#define ROGUE_CR_CLK_STATUS 0x0008U
-+#define ROGUE_CR_CLK_STATUS__PBE2_XE__MASKFULL 0x00000001FFF077FFULL
-+#define ROGUE_CR_CLK_STATUS__S7_TOP__MASKFULL 0x00000001B3101773ULL
-+#define ROGUE_CR_CLK_STATUS_MASKFULL 0x00000001FFF077FFULL
-+#define ROGUE_CR_CLK_STATUS_MCU_FBTC_SHIFT 32U
-+#define ROGUE_CR_CLK_STATUS_MCU_FBTC_CLRMSK 0xFFFFFFFEFFFFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_MCU_FBTC_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_MCU_FBTC_RUNNING 0x0000000100000000ULL
-+#define ROGUE_CR_CLK_STATUS_BIF_TEXAS_SHIFT 31U
-+#define ROGUE_CR_CLK_STATUS_BIF_TEXAS_CLRMSK 0xFFFFFFFF7FFFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_BIF_TEXAS_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_BIF_TEXAS_RUNNING 0x0000000080000000ULL
-+#define ROGUE_CR_CLK_STATUS_IPP_SHIFT 30U
-+#define ROGUE_CR_CLK_STATUS_IPP_CLRMSK 0xFFFFFFFFBFFFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_IPP_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_IPP_RUNNING 0x0000000040000000ULL
-+#define ROGUE_CR_CLK_STATUS_FBC_SHIFT 29U
-+#define ROGUE_CR_CLK_STATUS_FBC_CLRMSK 0xFFFFFFFFDFFFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_FBC_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_FBC_RUNNING 0x0000000020000000ULL
-+#define ROGUE_CR_CLK_STATUS_FBDC_SHIFT 28U
-+#define ROGUE_CR_CLK_STATUS_FBDC_CLRMSK 0xFFFFFFFFEFFFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_FBDC_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_FBDC_RUNNING 0x0000000010000000ULL
-+#define ROGUE_CR_CLK_STATUS_FB_TLCACHE_SHIFT 27U
-+#define ROGUE_CR_CLK_STATUS_FB_TLCACHE_CLRMSK 0xFFFFFFFFF7FFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_FB_TLCACHE_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_FB_TLCACHE_RUNNING 0x0000000008000000ULL
-+#define ROGUE_CR_CLK_STATUS_USCS_SHIFT 26U
-+#define ROGUE_CR_CLK_STATUS_USCS_CLRMSK 0xFFFFFFFFFBFFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_USCS_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_USCS_RUNNING 0x0000000004000000ULL
-+#define ROGUE_CR_CLK_STATUS_PBE_SHIFT 25U
-+#define ROGUE_CR_CLK_STATUS_PBE_CLRMSK 0xFFFFFFFFFDFFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_PBE_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_PBE_RUNNING 0x0000000002000000ULL
-+#define ROGUE_CR_CLK_STATUS_MCU_L1_SHIFT 24U
-+#define ROGUE_CR_CLK_STATUS_MCU_L1_CLRMSK 0xFFFFFFFFFEFFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_MCU_L1_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_MCU_L1_RUNNING 0x0000000001000000ULL
-+#define ROGUE_CR_CLK_STATUS_CDM_SHIFT 23U
-+#define ROGUE_CR_CLK_STATUS_CDM_CLRMSK 0xFFFFFFFFFF7FFFFFULL
-+#define ROGUE_CR_CLK_STATUS_CDM_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_CDM_RUNNING 0x0000000000800000ULL
-+#define ROGUE_CR_CLK_STATUS_SIDEKICK_SHIFT 22U
-+#define ROGUE_CR_CLK_STATUS_SIDEKICK_CLRMSK 0xFFFFFFFFFFBFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_SIDEKICK_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_SIDEKICK_RUNNING 0x0000000000400000ULL
-+#define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_SHIFT 21U
-+#define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_RUNNING 0x0000000000200000ULL
-+#define ROGUE_CR_CLK_STATUS_BIF_SHIFT 20U
-+#define ROGUE_CR_CLK_STATUS_BIF_CLRMSK 0xFFFFFFFFFFEFFFFFULL
-+#define ROGUE_CR_CLK_STATUS_BIF_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_BIF_RUNNING 0x0000000000100000ULL
-+#define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_SHIFT 14U
-+#define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFFFFFBFFFULL
-+#define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_RUNNING 0x0000000000004000ULL
-+#define ROGUE_CR_CLK_STATUS_MCU_L0_SHIFT 13U
-+#define ROGUE_CR_CLK_STATUS_MCU_L0_CLRMSK 0xFFFFFFFFFFFFDFFFULL
-+#define ROGUE_CR_CLK_STATUS_MCU_L0_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_MCU_L0_RUNNING 0x0000000000002000ULL
-+#define ROGUE_CR_CLK_STATUS_TPU_SHIFT 12U
-+#define ROGUE_CR_CLK_STATUS_TPU_CLRMSK 0xFFFFFFFFFFFFEFFFULL
-+#define ROGUE_CR_CLK_STATUS_TPU_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_TPU_RUNNING 0x0000000000001000ULL
-+#define ROGUE_CR_CLK_STATUS_USC_SHIFT 10U
-+#define ROGUE_CR_CLK_STATUS_USC_CLRMSK 0xFFFFFFFFFFFFFBFFULL
-+#define ROGUE_CR_CLK_STATUS_USC_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_USC_RUNNING 0x0000000000000400ULL
-+#define ROGUE_CR_CLK_STATUS_TLA_SHIFT 9U
-+#define ROGUE_CR_CLK_STATUS_TLA_CLRMSK 0xFFFFFFFFFFFFFDFFULL
-+#define ROGUE_CR_CLK_STATUS_TLA_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_TLA_RUNNING 0x0000000000000200ULL
-+#define ROGUE_CR_CLK_STATUS_SLC_SHIFT 8U
-+#define ROGUE_CR_CLK_STATUS_SLC_CLRMSK 0xFFFFFFFFFFFFFEFFULL
-+#define ROGUE_CR_CLK_STATUS_SLC_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_SLC_RUNNING 0x0000000000000100ULL
-+#define ROGUE_CR_CLK_STATUS_UVS_SHIFT 7U
-+#define ROGUE_CR_CLK_STATUS_UVS_CLRMSK 0xFFFFFFFFFFFFFF7FULL
-+#define ROGUE_CR_CLK_STATUS_UVS_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_UVS_RUNNING 0x0000000000000080ULL
-+#define ROGUE_CR_CLK_STATUS_PDS_SHIFT 6U
-+#define ROGUE_CR_CLK_STATUS_PDS_CLRMSK 0xFFFFFFFFFFFFFFBFULL
-+#define ROGUE_CR_CLK_STATUS_PDS_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_PDS_RUNNING 0x0000000000000040ULL
-+#define ROGUE_CR_CLK_STATUS_VDM_SHIFT 5U
-+#define ROGUE_CR_CLK_STATUS_VDM_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_CLK_STATUS_VDM_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_VDM_RUNNING 0x0000000000000020ULL
-+#define ROGUE_CR_CLK_STATUS_PM_SHIFT 4U
-+#define ROGUE_CR_CLK_STATUS_PM_CLRMSK 0xFFFFFFFFFFFFFFEFULL
-+#define ROGUE_CR_CLK_STATUS_PM_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_PM_RUNNING 0x0000000000000010ULL
-+#define ROGUE_CR_CLK_STATUS_GPP_SHIFT 3U
-+#define ROGUE_CR_CLK_STATUS_GPP_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
-+#define ROGUE_CR_CLK_STATUS_GPP_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_GPP_RUNNING 0x0000000000000008ULL
-+#define ROGUE_CR_CLK_STATUS_TE_SHIFT 2U
-+#define ROGUE_CR_CLK_STATUS_TE_CLRMSK 0xFFFFFFFFFFFFFFFBULL
-+#define ROGUE_CR_CLK_STATUS_TE_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_TE_RUNNING 0x0000000000000004ULL
-+#define ROGUE_CR_CLK_STATUS_TSP_SHIFT 1U
-+#define ROGUE_CR_CLK_STATUS_TSP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_CLK_STATUS_TSP_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_TSP_RUNNING 0x0000000000000002ULL
-+#define ROGUE_CR_CLK_STATUS_ISP_SHIFT 0U
-+#define ROGUE_CR_CLK_STATUS_ISP_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_CLK_STATUS_ISP_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS_ISP_RUNNING 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_CORE_ID */
-+#define ROGUE_CR_CORE_ID__PBVNC 0x0020U
-+#define ROGUE_CR_CORE_ID__PBVNC__MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_SHIFT 48U
-+#define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_CLRMSK 0x0000FFFFFFFFFFFFULL
-+#define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_SHIFT 32U
-+#define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_CLRMSK 0xFFFF0000FFFFFFFFULL
-+#define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_SHIFT 16U
-+#define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_CLRMSK 0xFFFFFFFF0000FFFFULL
-+#define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_SHIFT 0U
-+#define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_CORE_ID */
-+#define ROGUE_CR_CORE_ID 0x0018U
-+#define ROGUE_CR_CORE_ID_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_CORE_ID_ID_SHIFT 16U
-+#define ROGUE_CR_CORE_ID_ID_CLRMSK 0x0000FFFFU
-+#define ROGUE_CR_CORE_ID_CONFIG_SHIFT 0U
-+#define ROGUE_CR_CORE_ID_CONFIG_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_CORE_REVISION */
-+#define ROGUE_CR_CORE_REVISION 0x0020U
-+#define ROGUE_CR_CORE_REVISION_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_CORE_REVISION_DESIGNER_SHIFT 24U
-+#define ROGUE_CR_CORE_REVISION_DESIGNER_CLRMSK 0x00FFFFFFU
-+#define ROGUE_CR_CORE_REVISION_MAJOR_SHIFT 16U
-+#define ROGUE_CR_CORE_REVISION_MAJOR_CLRMSK 0xFF00FFFFU
-+#define ROGUE_CR_CORE_REVISION_MINOR_SHIFT 8U
-+#define ROGUE_CR_CORE_REVISION_MINOR_CLRMSK 0xFFFF00FFU
-+#define ROGUE_CR_CORE_REVISION_MAINTENANCE_SHIFT 0U
-+#define ROGUE_CR_CORE_REVISION_MAINTENANCE_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_DESIGNER_REV_FIELD1 */
-+#define ROGUE_CR_DESIGNER_REV_FIELD1 0x0028U
-+#define ROGUE_CR_DESIGNER_REV_FIELD1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0U
-+#define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_DESIGNER_REV_FIELD2 */
-+#define ROGUE_CR_DESIGNER_REV_FIELD2 0x0030U
-+#define ROGUE_CR_DESIGNER_REV_FIELD2_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0U
-+#define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_CHANGESET_NUMBER */
-+#define ROGUE_CR_CHANGESET_NUMBER 0x0040U
-+#define ROGUE_CR_CHANGESET_NUMBER_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_SHIFT 0U
-+#define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_CLRMSK 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_CLK_XTPLUS_CTRL */
-+#define ROGUE_CR_CLK_XTPLUS_CTRL 0x0080U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_MASKFULL 0x0000003FFFFF0000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_SHIFT 36U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_CLRMSK 0xFFFFFFCFFFFFFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_ON 0x0000001000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_AUTO 0x0000002000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_SHIFT 34U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_CLRMSK 0xFFFFFFF3FFFFFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_ON 0x0000000400000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_AUTO 0x0000000800000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_SHIFT 32U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_CLRMSK 0xFFFFFFFCFFFFFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_ON 0x0000000100000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_AUTO 0x0000000200000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_SHIFT 30U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_CLRMSK 0xFFFFFFFF3FFFFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_ON 0x0000000040000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_AUTO 0x0000000080000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_SHIFT 28U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_CLRMSK 0xFFFFFFFFCFFFFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_ON 0x0000000010000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_AUTO 0x0000000020000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_SHIFT 26U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_CLRMSK 0xFFFFFFFFF3FFFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_ON 0x0000000004000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_AUTO 0x0000000008000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_SHIFT 24U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_CLRMSK 0xFFFFFFFFFCFFFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_ON 0x0000000001000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_AUTO 0x0000000002000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_SHIFT 22U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_CLRMSK 0xFFFFFFFFFF3FFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_ON 0x0000000000400000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_AUTO 0x0000000000800000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_SHIFT 20U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_CLRMSK 0xFFFFFFFFFFCFFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_ON 0x0000000000100000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_AUTO 0x0000000000200000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_SHIFT 18U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_CLRMSK 0xFFFFFFFFFFF3FFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_ON 0x0000000000040000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_AUTO 0x0000000000080000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_SHIFT 16U
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_CLRMSK 0xFFFFFFFFFFFCFFFFULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_ON 0x0000000000010000ULL
-+#define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_AUTO 0x0000000000020000ULL
-+
-+/* Register ROGUE_CR_CLK_XTPLUS_STATUS */
-+#define ROGUE_CR_CLK_XTPLUS_STATUS 0x0088U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_MASKFULL 0x00000000000007FFULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_SHIFT 10U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_CLRMSK 0xFFFFFFFFFFFFFBFFULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_RUNNING 0x0000000000000400ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_SHIFT 9U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_CLRMSK 0xFFFFFFFFFFFFFDFFULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_RUNNING 0x0000000000000200ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_SHIFT 8U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_CLRMSK 0xFFFFFFFFFFFFFEFFULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_RUNNING 0x0000000000000100ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_SHIFT 7U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_CLRMSK 0xFFFFFFFFFFFFFF7FULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_RUNNING 0x0000000000000080ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_SHIFT 6U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_CLRMSK 0xFFFFFFFFFFFFFFBFULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_RUNNING 0x0000000000000040ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_SHIFT 5U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_RUNNING 0x0000000000000020ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_SHIFT 4U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_CLRMSK 0xFFFFFFFFFFFFFFEFULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_RUNNING 0x0000000000000010ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_SHIFT 3U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_RUNNING 0x0000000000000008ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_SHIFT 2U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_CLRMSK 0xFFFFFFFFFFFFFFFBULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_RUNNING 0x0000000000000004ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_SHIFT 1U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_RUNNING 0x0000000000000002ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_SHIFT 0U
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_RUNNING 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_SOFT_RESET */
-+#define ROGUE_CR_SOFT_RESET 0x0100U
-+#define ROGUE_CR_SOFT_RESET__PBE2_XE__MASKFULL 0xFFEFFFFFFFFFFC3DULL
-+#define ROGUE_CR_SOFT_RESET_MASKFULL 0x00E7FFFFFFFFFC3DULL
-+#define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_SHIFT 63U
-+#define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_CLRMSK 0x7FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_EN 0x8000000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_SHIFT 62U
-+#define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_EN 0x4000000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_SHIFT 61U
-+#define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_EN 0x2000000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_JONES_CORE_SHIFT 60U
-+#define ROGUE_CR_SOFT_RESET_JONES_CORE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_JONES_CORE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_TILING_CORE_SHIFT 59U
-+#define ROGUE_CR_SOFT_RESET_TILING_CORE_CLRMSK 0xF7FFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_TILING_CORE_EN 0x0800000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_TE3_SHIFT 58U
-+#define ROGUE_CR_SOFT_RESET_TE3_CLRMSK 0xFBFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_TE3_EN 0x0400000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_VCE_SHIFT 57U
-+#define ROGUE_CR_SOFT_RESET_VCE_CLRMSK 0xFDFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_VCE_EN 0x0200000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_VBS_SHIFT 56U
-+#define ROGUE_CR_SOFT_RESET_VBS_CLRMSK 0xFEFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_VBS_EN 0x0100000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_DPX1_CORE_SHIFT 55U
-+#define ROGUE_CR_SOFT_RESET_DPX1_CORE_CLRMSK 0xFF7FFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DPX1_CORE_EN 0x0080000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_DPX0_CORE_SHIFT 54U
-+#define ROGUE_CR_SOFT_RESET_DPX0_CORE_CLRMSK 0xFFBFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DPX0_CORE_EN 0x0040000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_FBA_SHIFT 53U
-+#define ROGUE_CR_SOFT_RESET_FBA_CLRMSK 0xFFDFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_FBA_EN 0x0020000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_FB_CDC_SHIFT 51U
-+#define ROGUE_CR_SOFT_RESET_FB_CDC_CLRMSK 0xFFF7FFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_FB_CDC_EN 0x0008000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_SH_SHIFT 50U
-+#define ROGUE_CR_SOFT_RESET_SH_CLRMSK 0xFFFBFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_SH_EN 0x0004000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_VRDM_SHIFT 49U
-+#define ROGUE_CR_SOFT_RESET_VRDM_CLRMSK 0xFFFDFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_VRDM_EN 0x0002000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_MCU_FBTC_SHIFT 48U
-+#define ROGUE_CR_SOFT_RESET_MCU_FBTC_CLRMSK 0xFFFEFFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_MCU_FBTC_EN 0x0001000000000000ULL
-+#define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_SHIFT 47U
-+#define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_CLRMSK 0xFFFF7FFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_EN 0x0000800000000000ULL
-+#define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_SHIFT 46U
-+#define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_CLRMSK 0xFFFFBFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_EN 0x0000400000000000ULL
-+#define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_SHIFT 45U
-+#define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_CLRMSK 0xFFFFDFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_EN 0x0000200000000000ULL
-+#define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_SHIFT 44U
-+#define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_CLRMSK 0xFFFFEFFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_EN 0x0000100000000000ULL
-+#define ROGUE_CR_SOFT_RESET_IPP_SHIFT 43U
-+#define ROGUE_CR_SOFT_RESET_IPP_CLRMSK 0xFFFFF7FFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_IPP_EN 0x0000080000000000ULL
-+#define ROGUE_CR_SOFT_RESET_BIF_TEXAS_SHIFT 42U
-+#define ROGUE_CR_SOFT_RESET_BIF_TEXAS_CLRMSK 0xFFFFFBFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_BIF_TEXAS_EN 0x0000040000000000ULL
-+#define ROGUE_CR_SOFT_RESET_TORNADO_CORE_SHIFT 41U
-+#define ROGUE_CR_SOFT_RESET_TORNADO_CORE_CLRMSK 0xFFFFFDFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_TORNADO_CORE_EN 0x0000020000000000ULL
-+#define ROGUE_CR_SOFT_RESET_DUST_H_CORE_SHIFT 40U
-+#define ROGUE_CR_SOFT_RESET_DUST_H_CORE_CLRMSK 0xFFFFFEFFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DUST_H_CORE_EN 0x0000010000000000ULL
-+#define ROGUE_CR_SOFT_RESET_DUST_G_CORE_SHIFT 39U
-+#define ROGUE_CR_SOFT_RESET_DUST_G_CORE_CLRMSK 0xFFFFFF7FFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DUST_G_CORE_EN 0x0000008000000000ULL
-+#define ROGUE_CR_SOFT_RESET_DUST_F_CORE_SHIFT 38U
-+#define ROGUE_CR_SOFT_RESET_DUST_F_CORE_CLRMSK 0xFFFFFFBFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DUST_F_CORE_EN 0x0000004000000000ULL
-+#define ROGUE_CR_SOFT_RESET_DUST_E_CORE_SHIFT 37U
-+#define ROGUE_CR_SOFT_RESET_DUST_E_CORE_CLRMSK 0xFFFFFFDFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DUST_E_CORE_EN 0x0000002000000000ULL
-+#define ROGUE_CR_SOFT_RESET_DUST_D_CORE_SHIFT 36U
-+#define ROGUE_CR_SOFT_RESET_DUST_D_CORE_CLRMSK 0xFFFFFFEFFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DUST_D_CORE_EN 0x0000001000000000ULL
-+#define ROGUE_CR_SOFT_RESET_DUST_C_CORE_SHIFT 35U
-+#define ROGUE_CR_SOFT_RESET_DUST_C_CORE_CLRMSK 0xFFFFFFF7FFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DUST_C_CORE_EN 0x0000000800000000ULL
-+#define ROGUE_CR_SOFT_RESET_MMU_SHIFT 34U
-+#define ROGUE_CR_SOFT_RESET_MMU_CLRMSK 0xFFFFFFFBFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_MMU_EN 0x0000000400000000ULL
-+#define ROGUE_CR_SOFT_RESET_BIF1_SHIFT 33U
-+#define ROGUE_CR_SOFT_RESET_BIF1_CLRMSK 0xFFFFFFFDFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_BIF1_EN 0x0000000200000000ULL
-+#define ROGUE_CR_SOFT_RESET_GARTEN_SHIFT 32U
-+#define ROGUE_CR_SOFT_RESET_GARTEN_CLRMSK 0xFFFFFFFEFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_GARTEN_EN 0x0000000100000000ULL
-+#define ROGUE_CR_SOFT_RESET_CPU_SHIFT 32U
-+#define ROGUE_CR_SOFT_RESET_CPU_CLRMSK 0xFFFFFFFEFFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_CPU_EN 0x0000000100000000ULL
-+#define ROGUE_CR_SOFT_RESET_RASCAL_CORE_SHIFT 31U
-+#define ROGUE_CR_SOFT_RESET_RASCAL_CORE_CLRMSK 0xFFFFFFFF7FFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_RASCAL_CORE_EN 0x0000000080000000ULL
-+#define ROGUE_CR_SOFT_RESET_DUST_B_CORE_SHIFT 30U
-+#define ROGUE_CR_SOFT_RESET_DUST_B_CORE_CLRMSK 0xFFFFFFFFBFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DUST_B_CORE_EN 0x0000000040000000ULL
-+#define ROGUE_CR_SOFT_RESET_DUST_A_CORE_SHIFT 29U
-+#define ROGUE_CR_SOFT_RESET_DUST_A_CORE_CLRMSK 0xFFFFFFFFDFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_DUST_A_CORE_EN 0x0000000020000000ULL
-+#define ROGUE_CR_SOFT_RESET_FB_TLCACHE_SHIFT 28U
-+#define ROGUE_CR_SOFT_RESET_FB_TLCACHE_CLRMSK 0xFFFFFFFFEFFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_FB_TLCACHE_EN 0x0000000010000000ULL
-+#define ROGUE_CR_SOFT_RESET_SLC_SHIFT 27U
-+#define ROGUE_CR_SOFT_RESET_SLC_CLRMSK 0xFFFFFFFFF7FFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_SLC_EN 0x0000000008000000ULL
-+#define ROGUE_CR_SOFT_RESET_TLA_SHIFT 26U
-+#define ROGUE_CR_SOFT_RESET_TLA_CLRMSK 0xFFFFFFFFFBFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_TLA_EN 0x0000000004000000ULL
-+#define ROGUE_CR_SOFT_RESET_UVS_SHIFT 25U
-+#define ROGUE_CR_SOFT_RESET_UVS_CLRMSK 0xFFFFFFFFFDFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_UVS_EN 0x0000000002000000ULL
-+#define ROGUE_CR_SOFT_RESET_TE_SHIFT 24U
-+#define ROGUE_CR_SOFT_RESET_TE_CLRMSK 0xFFFFFFFFFEFFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_TE_EN 0x0000000001000000ULL
-+#define ROGUE_CR_SOFT_RESET_GPP_SHIFT 23U
-+#define ROGUE_CR_SOFT_RESET_GPP_CLRMSK 0xFFFFFFFFFF7FFFFFULL
-+#define ROGUE_CR_SOFT_RESET_GPP_EN 0x0000000000800000ULL
-+#define ROGUE_CR_SOFT_RESET_FBDC_SHIFT 22U
-+#define ROGUE_CR_SOFT_RESET_FBDC_CLRMSK 0xFFFFFFFFFFBFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_FBDC_EN 0x0000000000400000ULL
-+#define ROGUE_CR_SOFT_RESET_FBC_SHIFT 21U
-+#define ROGUE_CR_SOFT_RESET_FBC_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_FBC_EN 0x0000000000200000ULL
-+#define ROGUE_CR_SOFT_RESET_PM_SHIFT 20U
-+#define ROGUE_CR_SOFT_RESET_PM_CLRMSK 0xFFFFFFFFFFEFFFFFULL
-+#define ROGUE_CR_SOFT_RESET_PM_EN 0x0000000000100000ULL
-+#define ROGUE_CR_SOFT_RESET_PBE_SHIFT 19U
-+#define ROGUE_CR_SOFT_RESET_PBE_CLRMSK 0xFFFFFFFFFFF7FFFFULL
-+#define ROGUE_CR_SOFT_RESET_PBE_EN 0x0000000000080000ULL
-+#define ROGUE_CR_SOFT_RESET_USC_SHARED_SHIFT 18U
-+#define ROGUE_CR_SOFT_RESET_USC_SHARED_CLRMSK 0xFFFFFFFFFFFBFFFFULL
-+#define ROGUE_CR_SOFT_RESET_USC_SHARED_EN 0x0000000000040000ULL
-+#define ROGUE_CR_SOFT_RESET_MCU_L1_SHIFT 17U
-+#define ROGUE_CR_SOFT_RESET_MCU_L1_CLRMSK 0xFFFFFFFFFFFDFFFFULL
-+#define ROGUE_CR_SOFT_RESET_MCU_L1_EN 0x0000000000020000ULL
-+#define ROGUE_CR_SOFT_RESET_BIF_SHIFT 16U
-+#define ROGUE_CR_SOFT_RESET_BIF_CLRMSK 0xFFFFFFFFFFFEFFFFULL
-+#define ROGUE_CR_SOFT_RESET_BIF_EN 0x0000000000010000ULL
-+#define ROGUE_CR_SOFT_RESET_CDM_SHIFT 15U
-+#define ROGUE_CR_SOFT_RESET_CDM_CLRMSK 0xFFFFFFFFFFFF7FFFULL
-+#define ROGUE_CR_SOFT_RESET_CDM_EN 0x0000000000008000ULL
-+#define ROGUE_CR_SOFT_RESET_VDM_SHIFT 14U
-+#define ROGUE_CR_SOFT_RESET_VDM_CLRMSK 0xFFFFFFFFFFFFBFFFULL
-+#define ROGUE_CR_SOFT_RESET_VDM_EN 0x0000000000004000ULL
-+#define ROGUE_CR_SOFT_RESET_TESS_SHIFT 13U
-+#define ROGUE_CR_SOFT_RESET_TESS_CLRMSK 0xFFFFFFFFFFFFDFFFULL
-+#define ROGUE_CR_SOFT_RESET_TESS_EN 0x0000000000002000ULL
-+#define ROGUE_CR_SOFT_RESET_PDS_SHIFT 12U
-+#define ROGUE_CR_SOFT_RESET_PDS_CLRMSK 0xFFFFFFFFFFFFEFFFULL
-+#define ROGUE_CR_SOFT_RESET_PDS_EN 0x0000000000001000ULL
-+#define ROGUE_CR_SOFT_RESET_ISP_SHIFT 11U
-+#define ROGUE_CR_SOFT_RESET_ISP_CLRMSK 0xFFFFFFFFFFFFF7FFULL
-+#define ROGUE_CR_SOFT_RESET_ISP_EN 0x0000000000000800ULL
-+#define ROGUE_CR_SOFT_RESET_TSP_SHIFT 10U
-+#define ROGUE_CR_SOFT_RESET_TSP_CLRMSK 0xFFFFFFFFFFFFFBFFULL
-+#define ROGUE_CR_SOFT_RESET_TSP_EN 0x0000000000000400ULL
-+#define ROGUE_CR_SOFT_RESET_SYSARB_SHIFT 5U
-+#define ROGUE_CR_SOFT_RESET_SYSARB_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_SOFT_RESET_SYSARB_EN 0x0000000000000020ULL
-+#define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_SHIFT 4U
-+#define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFFFFFFFEFULL
-+#define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_EN 0x0000000000000010ULL
-+#define ROGUE_CR_SOFT_RESET_MCU_L0_SHIFT 3U
-+#define ROGUE_CR_SOFT_RESET_MCU_L0_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
-+#define ROGUE_CR_SOFT_RESET_MCU_L0_EN 0x0000000000000008ULL
-+#define ROGUE_CR_SOFT_RESET_TPU_SHIFT 2U
-+#define ROGUE_CR_SOFT_RESET_TPU_CLRMSK 0xFFFFFFFFFFFFFFFBULL
-+#define ROGUE_CR_SOFT_RESET_TPU_EN 0x0000000000000004ULL
-+#define ROGUE_CR_SOFT_RESET_USC_SHIFT 0U
-+#define ROGUE_CR_SOFT_RESET_USC_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_SOFT_RESET_USC_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_SOFT_RESET2 */
-+#define ROGUE_CR_SOFT_RESET2 0x0108U
-+#define ROGUE_CR_SOFT_RESET2_MASKFULL 0x00000000001FFFFFULL
-+#define ROGUE_CR_SOFT_RESET2_SPFILTER_SHIFT 12U
-+#define ROGUE_CR_SOFT_RESET2_SPFILTER_CLRMSK 0xFFE00FFFU
-+#define ROGUE_CR_SOFT_RESET2_TDM_SHIFT 11U
-+#define ROGUE_CR_SOFT_RESET2_TDM_CLRMSK 0xFFFFF7FFU
-+#define ROGUE_CR_SOFT_RESET2_TDM_EN 0x00000800U
-+#define ROGUE_CR_SOFT_RESET2_ASTC_SHIFT 10U
-+#define ROGUE_CR_SOFT_RESET2_ASTC_CLRMSK 0xFFFFFBFFU
-+#define ROGUE_CR_SOFT_RESET2_ASTC_EN 0x00000400U
-+#define ROGUE_CR_SOFT_RESET2_BLACKPEARL_SHIFT 9U
-+#define ROGUE_CR_SOFT_RESET2_BLACKPEARL_CLRMSK 0xFFFFFDFFU
-+#define ROGUE_CR_SOFT_RESET2_BLACKPEARL_EN 0x00000200U
-+#define ROGUE_CR_SOFT_RESET2_USCPS_SHIFT 8U
-+#define ROGUE_CR_SOFT_RESET2_USCPS_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_SOFT_RESET2_USCPS_EN 0x00000100U
-+#define ROGUE_CR_SOFT_RESET2_IPF_SHIFT 7U
-+#define ROGUE_CR_SOFT_RESET2_IPF_CLRMSK 0xFFFFFF7FU
-+#define ROGUE_CR_SOFT_RESET2_IPF_EN 0x00000080U
-+#define ROGUE_CR_SOFT_RESET2_GEOMETRY_SHIFT 6U
-+#define ROGUE_CR_SOFT_RESET2_GEOMETRY_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_SOFT_RESET2_GEOMETRY_EN 0x00000040U
-+#define ROGUE_CR_SOFT_RESET2_USC_SHARED_SHIFT 5U
-+#define ROGUE_CR_SOFT_RESET2_USC_SHARED_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_SOFT_RESET2_USC_SHARED_EN 0x00000020U
-+#define ROGUE_CR_SOFT_RESET2_PDS_SHARED_SHIFT 4U
-+#define ROGUE_CR_SOFT_RESET2_PDS_SHARED_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_SOFT_RESET2_PDS_SHARED_EN 0x00000010U
-+#define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_SHIFT 3U
-+#define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_EN 0x00000008U
-+#define ROGUE_CR_SOFT_RESET2_PIXEL_SHIFT 2U
-+#define ROGUE_CR_SOFT_RESET2_PIXEL_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SOFT_RESET2_PIXEL_EN 0x00000004U
-+#define ROGUE_CR_SOFT_RESET2_CDM_SHIFT 1U
-+#define ROGUE_CR_SOFT_RESET2_CDM_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SOFT_RESET2_CDM_EN 0x00000002U
-+#define ROGUE_CR_SOFT_RESET2_VERTEX_SHIFT 0U
-+#define ROGUE_CR_SOFT_RESET2_VERTEX_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SOFT_RESET2_VERTEX_EN 0x00000001U
-+
-+/* Register ROGUE_CR_EVENT_STATUS */
-+#define ROGUE_CR_EVENT_STATUS 0x0130U
-+#define ROGUE_CR_EVENT_STATUS__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL
-+#define ROGUE_CR_EVENT_STATUS__SIGNALS__MASKFULL 0x00000000E007FFFFULL
-+#define ROGUE_CR_EVENT_STATUS_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_SHIFT 31U
-+#define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_EN 0x80000000U
-+#define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_SHIFT 30U
-+#define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_EN 0x40000000U
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_SHIFT 29U
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U
-+#define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_SHIFT 28U
-+#define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_EN 0x10000000U
-+#define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_SHIFT 27U
-+#define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_EN 0x08000000U
-+#define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_SHIFT 26U
-+#define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_EN 0x04000000U
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_SHIFT 25U
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_EN 0x02000000U
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_SHIFT 24U
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_EN 0x01000000U
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_SHIFT 23U
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_EN 0x00800000U
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_SHIFT 22U
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_EN 0x00400000U
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_SHIFT 21U
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_EN 0x00200000U
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_SHIFT 20U
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_EN 0x00100000U
-+#define ROGUE_CR_EVENT_STATUS_SAFETY_SHIFT 20U
-+#define ROGUE_CR_EVENT_STATUS_SAFETY_CLRMSK 0xFFEFFFFFU
-+#define ROGUE_CR_EVENT_STATUS_SAFETY_EN 0x00100000U
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_SHIFT 19U
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_EN 0x00080000U
-+#define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_SHIFT 19U
-+#define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_CLRMSK 0xFFF7FFFFU
-+#define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_EN 0x00080000U
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_SHIFT 18U
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU
-+#define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_EN 0x00040000U
-+#define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U
-+#define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU
-+#define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U
-+#define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_SHIFT 17U
-+#define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_CLRMSK 0xFFFDFFFFU
-+#define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_EN 0x00020000U
-+#define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_SHIFT 17U
-+#define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU
-+#define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_SHIFT 16U
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_EN 0x00010000U
-+#define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_SHIFT 15U
-+#define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_CLRMSK 0xFFFF7FFFU
-+#define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_EN 0x00008000U
-+#define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_SHIFT 14U
-+#define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU
-+#define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_EN 0x00004000U
-+#define ROGUE_CR_EVENT_STATUS_GPIO_ACK_SHIFT 13U
-+#define ROGUE_CR_EVENT_STATUS_GPIO_ACK_CLRMSK 0xFFFFDFFFU
-+#define ROGUE_CR_EVENT_STATUS_GPIO_ACK_EN 0x00002000U
-+#define ROGUE_CR_EVENT_STATUS_GPIO_REQ_SHIFT 12U
-+#define ROGUE_CR_EVENT_STATUS_GPIO_REQ_CLRMSK 0xFFFFEFFFU
-+#define ROGUE_CR_EVENT_STATUS_GPIO_REQ_EN 0x00001000U
-+#define ROGUE_CR_EVENT_STATUS_POWER_ABORT_SHIFT 11U
-+#define ROGUE_CR_EVENT_STATUS_POWER_ABORT_CLRMSK 0xFFFFF7FFU
-+#define ROGUE_CR_EVENT_STATUS_POWER_ABORT_EN 0x00000800U
-+#define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_SHIFT 10U
-+#define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU
-+#define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_EN 0x00000400U
-+#define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_SHIFT 9U
-+#define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU
-+#define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_EN 0x00000200U
-+#define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_SHIFT 8U
-+#define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_EN 0x00000100U
-+#define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_SHIFT 7U
-+#define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU
-+#define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_EN 0x00000080U
-+#define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 6U
-+#define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_EN 0x00000040U
-+#define ROGUE_CR_EVENT_STATUS_TA_FINISHED_SHIFT 5U
-+#define ROGUE_CR_EVENT_STATUS_TA_FINISHED_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_EVENT_STATUS_TA_FINISHED_EN 0x00000020U
-+#define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_SHIFT 4U
-+#define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_EN 0x00000010U
-+#define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 3U
-+#define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_EN 0x00000008U
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_SHIFT 2U
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_EN 0x00000004U
-+#define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_SHIFT 1U
-+#define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_EN 0x00000002U
-+#define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_SHIFT 0U
-+#define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_TIMER */
-+#define ROGUE_CR_TIMER 0x0160U
-+#define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TIMER_BIT31_SHIFT 63U
-+#define ROGUE_CR_TIMER_BIT31_CLRMSK 0x7FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_TIMER_BIT31_EN 0x8000000000000000ULL
-+#define ROGUE_CR_TIMER_VALUE_SHIFT 0U
-+#define ROGUE_CR_TIMER_VALUE_CLRMSK 0xFFFF000000000000ULL
-+
-+/* Register ROGUE_CR_TLA_STATUS */
-+#define ROGUE_CR_TLA_STATUS 0x0178U
-+#define ROGUE_CR_TLA_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_TLA_STATUS_BLIT_COUNT_SHIFT 39U
-+#define ROGUE_CR_TLA_STATUS_BLIT_COUNT_CLRMSK 0x0000007FFFFFFFFFULL
-+#define ROGUE_CR_TLA_STATUS_REQUEST_SHIFT 7U
-+#define ROGUE_CR_TLA_STATUS_REQUEST_CLRMSK 0xFFFFFF800000007FULL
-+#define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_SHIFT 1U
-+#define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_CLRMSK 0xFFFFFFFFFFFFFF81ULL
-+#define ROGUE_CR_TLA_STATUS_BUSY_SHIFT 0U
-+#define ROGUE_CR_TLA_STATUS_BUSY_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_TLA_STATUS_BUSY_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_PM_PARTIAL_RENDER_ENABLE */
-+#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE 0x0338U
-+#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_SHIFT 0U
-+#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SIDEKICK_IDLE */
-+#define ROGUE_CR_SIDEKICK_IDLE 0x03C8U
-+#define ROGUE_CR_SIDEKICK_IDLE_MASKFULL 0x000000000000007FULL
-+#define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_SHIFT 6U
-+#define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_EN 0x00000040U
-+#define ROGUE_CR_SIDEKICK_IDLE_MMU_SHIFT 5U
-+#define ROGUE_CR_SIDEKICK_IDLE_MMU_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_SIDEKICK_IDLE_MMU_EN 0x00000020U
-+#define ROGUE_CR_SIDEKICK_IDLE_BIF128_SHIFT 4U
-+#define ROGUE_CR_SIDEKICK_IDLE_BIF128_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_SIDEKICK_IDLE_BIF128_EN 0x00000010U
-+#define ROGUE_CR_SIDEKICK_IDLE_TLA_SHIFT 3U
-+#define ROGUE_CR_SIDEKICK_IDLE_TLA_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_SIDEKICK_IDLE_TLA_EN 0x00000008U
-+#define ROGUE_CR_SIDEKICK_IDLE_GARTEN_SHIFT 2U
-+#define ROGUE_CR_SIDEKICK_IDLE_GARTEN_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN 0x00000004U
-+#define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_SHIFT 1U
-+#define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN 0x00000002U
-+#define ROGUE_CR_SIDEKICK_IDLE_SOCIF_SHIFT 0U
-+#define ROGUE_CR_SIDEKICK_IDLE_SOCIF_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MARS_IDLE */
-+#define ROGUE_CR_MARS_IDLE 0x08F8U
-+#define ROGUE_CR_MARS_IDLE_MASKFULL 0x0000000000000007ULL
-+#define ROGUE_CR_MARS_IDLE_MH_SYSARB0_SHIFT 2U
-+#define ROGUE_CR_MARS_IDLE_MH_SYSARB0_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN 0x00000004U
-+#define ROGUE_CR_MARS_IDLE_CPU_SHIFT 1U
-+#define ROGUE_CR_MARS_IDLE_CPU_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_MARS_IDLE_CPU_EN 0x00000002U
-+#define ROGUE_CR_MARS_IDLE_SOCIF_SHIFT 0U
-+#define ROGUE_CR_MARS_IDLE_SOCIF_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MARS_IDLE_SOCIF_EN 0x00000001U
-+
-+/* Register ROGUE_CR_VDM_CONTEXT_STORE_STATUS */
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS 0x0430U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_MASKFULL 0x00000000000000F3ULL
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_SHIFT 4U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_CLRMSK 0xFFFFFF0FU
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN 0x00000002U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK0 */
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0 0x0438U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_SHIFT 32U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_CLRMSK 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_SHIFT 0U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_CLRMSK 0xFFFFFFFF00000000ULL
-+
-+/* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK1 */
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK1 0x0440U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_SHIFT 0U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK2 */
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2 0x0448U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_SHIFT 32U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_CLRMSK 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_SHIFT 0U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_CLRMSK 0xFFFFFFFF00000000ULL
-+
-+/* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK0 */
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0 0x0450U
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_SHIFT 32U
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_CLRMSK 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_SHIFT 0U
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_CLRMSK 0xFFFFFFFF00000000ULL
-+
-+/* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK1 */
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1 0x0458U
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_SHIFT 0U
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK2 */
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2 0x0460U
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_SHIFT 32U
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_CLRMSK 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_SHIFT 0U
-+#define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_CLRMSK 0xFFFFFFFF00000000ULL
-+
-+/* Register ROGUE_CR_CDM_CONTEXT_STORE_STATUS */
-+#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS 0x04A0U
-+#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_MASKFULL 0x0000000000000003ULL
-+#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U
-+#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN 0x00000002U
-+#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U
-+#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_CDM_CONTEXT_PDS0 */
-+#define ROGUE_CR_CDM_CONTEXT_PDS0 0x04A8U
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_MASKFULL 0xFFFFFFF0FFFFFFF0ULL
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_SHIFT 36U
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSHIFT 4U
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSIZE 16U
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_SHIFT 4U
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSHIFT 4U
-+#define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_CDM_CONTEXT_PDS1 */
-+#define ROGUE_CR_CDM_CONTEXT_PDS1 0x04B0U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_MASKFULL 0x000000003FFFFFFFULL
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_SHIFT 29U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_EN 0x20000000U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_SHIFT 28U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_EN 0x10000000U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_SHIFT 27U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_CLRMSK 0xF7FFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_EN 0x08000000U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_SHIFT 21U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_SHIFT 20U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_EN 0x00100000U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_SHIFT 11U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_SHIFT 7U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_SHIFT 1U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_SHIFT 0U
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_CDM_TERMINATE_PDS */
-+#define ROGUE_CR_CDM_TERMINATE_PDS 0x04B8U
-+#define ROGUE_CR_CDM_TERMINATE_PDS_MASKFULL 0xFFFFFFF0FFFFFFF0ULL
-+#define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_SHIFT 36U
-+#define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL
-+#define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSHIFT 4U
-+#define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSIZE 16U
-+#define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_SHIFT 4U
-+#define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL
-+#define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSHIFT 4U
-+#define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_CDM_TERMINATE_PDS1 */
-+#define ROGUE_CR_CDM_TERMINATE_PDS1 0x04C0U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_MASKFULL 0x000000003FFFFFFFULL
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_SHIFT 29U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_EN 0x20000000U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_SHIFT 28U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_EN 0x10000000U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_SHIFT 27U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_CLRMSK 0xF7FFFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_EN 0x08000000U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_SHIFT 21U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_SHIFT 20U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_EN 0x00100000U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_SHIFT 11U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_SHIFT 7U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_SHIFT 1U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_SHIFT 0U
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_CDM_CONTEXT_LOAD_PDS0 */
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0 0x04D8U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_MASKFULL 0xFFFFFFF0FFFFFFF0ULL
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_SHIFT 36U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSHIFT 4U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSIZE 16U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_SHIFT 4U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSHIFT 4U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_CDM_CONTEXT_LOAD_PDS1 */
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1 0x04E0U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_MASKFULL 0x000000003FFFFFFFULL
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_SHIFT 29U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_EN 0x20000000U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_SHIFT 28U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_EN 0x10000000U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_SHIFT 28U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_SHIFT 27U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_CLRMSK 0xF7FFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_EN 0x08000000U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_SHIFT 21U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_SHIFT 20U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_EN 0x00100000U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_SHIFT 11U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_SHIFT 7U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_SHIFT 1U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_SHIFT 0U
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_WRAPPER_CONFIG */
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG 0x0810U
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_MASKFULL 0x000001030F01FFFFULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_SHIFT 40U
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_CLRMSK 0xFFFFFEFFFFFFFFFFULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_EN 0x0000010000000000ULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_SHIFT 33U
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_CLRMSK 0xFFFFFFFDFFFFFFFFULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_EN 0x0000000200000000ULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_SHIFT 32U
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_CLRMSK 0xFFFFFFFEFFFFFFFFULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_EN 0x0000000100000000ULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_SHIFT 25U
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_CLRMSK 0xFFFFFFFFF1FFFFFFULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_SHIFT 24U
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_CLRMSK 0xFFFFFFFFFEFFFFFFULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_EN 0x0000000001000000ULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_SHIFT 16U
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_CLRMSK 0xFFFFFFFFFFFEFFFFULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MIPS32 0x0000000000000000ULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MICROMIPS 0x0000000000010000ULL
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_SHIFT 0U
-+#define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1 0x0818U
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2 0x0820U
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_SHIFT 6U
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_SHIFT 5U
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1 0x0828U
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2 0x0830U
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_SHIFT 6U
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_SHIFT 5U
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1 0x0838U
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2 0x0840U
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_SHIFT 6U
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_SHIFT 5U
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1 0x0848U
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2 0x0850U
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_SHIFT 6U
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_SHIFT 5U
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1 0x0858U
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MASKFULL 0x00000000FFFFF001ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2 */
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2 0x0860U
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_SHIFT 6U
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_SHIFT 5U
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_EN 0x0000000000000020ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS */
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS 0x0868U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_MASKFULL 0x00000001FFFFFFFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_SHIFT 32U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_CLRMSK 0xFFFFFFFEFFFFFFFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_EN 0x0000000100000000ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_CLRMSK 0xFFFFFFFF00000000ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR */
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR 0x0870U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG */
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG 0x0878U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MASKFULL 0xFFFFFFF7FFFFFFBFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_SHIFT 36U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_CLRMSK 0x0000000FFFFFFFFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_SHIFT 32U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_CLRMSK 0xFFFFFFF8FFFFFFFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_SHIFT 11U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_CLRMSK 0xFFFFFFFFFFFFF7FFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_EN 0x0000000000000800ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_SHIFT 7U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_CLRMSK 0xFFFFFFFFFFFFF87FULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_4KB 0x0000000000000000ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_16KB 0x0000000000000080ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_64KB 0x0000000000000100ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_256KB 0x0000000000000180ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_1MB 0x0000000000000200ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_4MB 0x0000000000000280ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_16MB 0x0000000000000300ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_64MB 0x0000000000000380ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_256MB 0x0000000000000400ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_SHIFT 1U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_CLRMSK 0xFFFFFFFFFFFFFFC1ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ */
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ 0x0880U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_MASKFULL 0x000000000000003FULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_SHIFT 1U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_CLRMSK 0xFFFFFFC1U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA */
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA 0x0888U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MASKFULL 0xFFFFFFF7FFFFFF81ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_SHIFT 36U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_CLRMSK 0x0000000FFFFFFFFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_SHIFT 32U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_CLRMSK 0xFFFFFFF8FFFFFFFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_SHIFT 12U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_SHIFT 11U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_CLRMSK 0xFFFFFFFFFFFFF7FFULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_EN 0x0000000000000800ULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_SHIFT 7U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_CLRMSK 0xFFFFFFFFFFFFF87FULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE */
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE 0x08A0U
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_SHIFT 0U
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS */
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS 0x08A8U
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_SHIFT 0U
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR */
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR 0x08B0U
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_SHIFT 0U
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE */
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE 0x08B8U
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_SHIFT 0U
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_WRAPPER_NMI_EVENT */
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT 0x08C0U
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_SHIFT 0U
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_DEBUG_CONFIG */
-+#define ROGUE_CR_MIPS_DEBUG_CONFIG 0x08C8U
-+#define ROGUE_CR_MIPS_DEBUG_CONFIG_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_SHIFT 0U
-+#define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_EXCEPTION_STATUS */
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS 0x08D0U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_MASKFULL 0x000000000000003FULL
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_SHIFT 5U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_EN 0x00000020U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_SHIFT 4U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_EN 0x00000010U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_SHIFT 3U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_EN 0x00000008U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_SHIFT 2U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_EN 0x00000004U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_SHIFT 1U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_EN 0x00000002U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_SHIFT 0U
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MIPS_WRAPPER_STATUS */
-+#define ROGUE_CR_MIPS_WRAPPER_STATUS 0x08E8U
-+#define ROGUE_CR_MIPS_WRAPPER_STATUS_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_SHIFT 0U
-+#define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_XPU_BROADCAST */
-+#define ROGUE_CR_XPU_BROADCAST 0x0890U
-+#define ROGUE_CR_XPU_BROADCAST_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_XPU_BROADCAST_MASK_SHIFT 0U
-+#define ROGUE_CR_XPU_BROADCAST_MASK_CLRMSK 0xFFFFFE00U
-+
-+/* Register ROGUE_CR_META_SP_MSLVDATAX */
-+#define ROGUE_CR_META_SP_MSLVDATAX 0x0A00U
-+#define ROGUE_CR_META_SP_MSLVDATAX_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVDATAT */
-+#define ROGUE_CR_META_SP_MSLVDATAT 0x0A08U
-+#define ROGUE_CR_META_SP_MSLVDATAT_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVCTRL0 */
-+#define ROGUE_CR_META_SP_MSLVCTRL0 0x0A10U
-+#define ROGUE_CR_META_SP_MSLVCTRL0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_SHIFT 2U
-+#define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_CLRMSK 0x00000003U
-+#define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_SHIFT 1U
-+#define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_EN 0x00000002U
-+#define ROGUE_CR_META_SP_MSLVCTRL0_RD_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVCTRL0_RD_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_META_SP_MSLVCTRL0_RD_EN 0x00000001U
-+
-+/* Register ROGUE_CR_META_SP_MSLVCTRL1 */
-+#define ROGUE_CR_META_SP_MSLVCTRL1 0x0A18U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_MASKFULL 0x00000000F7F4003FULL
-+#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_SHIFT 30U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_CLRMSK 0x3FFFFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_SHIFT 29U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_EN 0x20000000U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_SHIFT 28U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_EN 0x10000000U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_SHIFT 26U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_CLRMSK 0xFBFFFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN 0x04000000U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_SHIFT 25U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_CLRMSK 0xFDFFFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_EN 0x02000000U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_READY_SHIFT 24U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_READY_CLRMSK 0xFEFFFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_READY_EN 0x01000000U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_SHIFT 21U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_CLRMSK 0xFF1FFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_SHIFT 20U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_CLRMSK 0xFFEFFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_EN 0x00100000U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_SHIFT 18U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_CLRMSK 0xFFFBFFFFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_EN 0x00040000U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_SHIFT 4U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_CLRMSK 0xFFFFFFCFU
-+#define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_SHIFT 2U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_CLRMSK 0xFFFFFFF3U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_CLRMSK 0xFFFFFFFCU
-+
-+/* Register ROGUE_CR_META_SP_MSLVHANDSHKE */
-+#define ROGUE_CR_META_SP_MSLVHANDSHKE 0x0A50U
-+#define ROGUE_CR_META_SP_MSLVHANDSHKE_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_SHIFT 2U
-+#define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_CLRMSK 0xFFFFFFF3U
-+#define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_CLRMSK 0xFFFFFFFCU
-+
-+/* Register ROGUE_CR_META_SP_MSLVT0KICK */
-+#define ROGUE_CR_META_SP_MSLVT0KICK 0x0A80U
-+#define ROGUE_CR_META_SP_MSLVT0KICK_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVT0KICKI */
-+#define ROGUE_CR_META_SP_MSLVT0KICKI 0x0A88U
-+#define ROGUE_CR_META_SP_MSLVT0KICKI_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVT1KICK */
-+#define ROGUE_CR_META_SP_MSLVT1KICK 0x0A90U
-+#define ROGUE_CR_META_SP_MSLVT1KICK_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVT1KICKI */
-+#define ROGUE_CR_META_SP_MSLVT1KICKI 0x0A98U
-+#define ROGUE_CR_META_SP_MSLVT1KICKI_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVT2KICK */
-+#define ROGUE_CR_META_SP_MSLVT2KICK 0x0AA0U
-+#define ROGUE_CR_META_SP_MSLVT2KICK_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVT2KICKI */
-+#define ROGUE_CR_META_SP_MSLVT2KICKI 0x0AA8U
-+#define ROGUE_CR_META_SP_MSLVT2KICKI_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVT3KICK */
-+#define ROGUE_CR_META_SP_MSLVT3KICK 0x0AB0U
-+#define ROGUE_CR_META_SP_MSLVT3KICK_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVT3KICKI */
-+#define ROGUE_CR_META_SP_MSLVT3KICKI 0x0AB8U
-+#define ROGUE_CR_META_SP_MSLVT3KICKI_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_META_SP_MSLVRST */
-+#define ROGUE_CR_META_SP_MSLVRST 0x0AC0U
-+#define ROGUE_CR_META_SP_MSLVRST_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_EN 0x00000001U
-+
-+/* Register ROGUE_CR_META_SP_MSLVIRQSTATUS */
-+#define ROGUE_CR_META_SP_MSLVIRQSTATUS 0x0AC8U
-+#define ROGUE_CR_META_SP_MSLVIRQSTATUS_MASKFULL 0x000000000000000CULL
-+#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_SHIFT 3U
-+#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_EN 0x00000008U
-+#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_SHIFT 2U
-+#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN 0x00000004U
-+
-+/* Register ROGUE_CR_META_SP_MSLVIRQENABLE */
-+#define ROGUE_CR_META_SP_MSLVIRQENABLE 0x0AD0U
-+#define ROGUE_CR_META_SP_MSLVIRQENABLE_MASKFULL 0x000000000000000CULL
-+#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_SHIFT 3U
-+#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_EN 0x00000008U
-+#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_SHIFT 2U
-+#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_EN 0x00000004U
-+
-+/* Register ROGUE_CR_META_SP_MSLVIRQLEVEL */
-+#define ROGUE_CR_META_SP_MSLVIRQLEVEL 0x0AD8U
-+#define ROGUE_CR_META_SP_MSLVIRQLEVEL_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_SHIFT 0U
-+#define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE */
-+#define ROGUE_CR_MTS_SCHEDULE 0x0B00U
-+#define ROGUE_CR_MTS_SCHEDULE_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_MTS_SCHEDULE_HOST_SHIFT 8U
-+#define ROGUE_CR_MTS_SCHEDULE_HOST_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_MTS_SCHEDULE_HOST_BG_TIMER 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE_HOST_HOST 0x00000100U
-+#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_SHIFT 6U
-+#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT1 0x00000040U
-+#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT2 0x00000080U
-+#define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT3 0x000000C0U
-+#define ROGUE_CR_MTS_SCHEDULE_CONTEXT_SHIFT 5U
-+#define ROGUE_CR_MTS_SCHEDULE_CONTEXT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SCHEDULE_CONTEXT_BGCTX 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE_CONTEXT_INTCTX 0x00000020U
-+#define ROGUE_CR_MTS_SCHEDULE_TASK_SHIFT 4U
-+#define ROGUE_CR_MTS_SCHEDULE_TASK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SCHEDULE_TASK_NON_COUNTED 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE_TASK_COUNTED 0x00000010U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_CLRMSK 0xFFFFFFF0U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM1 0x00000001U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM2 0x00000002U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM3 0x00000003U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM4 0x00000004U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM5 0x00000005U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM6 0x00000006U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM7 0x00000007U
-+#define ROGUE_CR_MTS_SCHEDULE_DM_DM_ALL 0x0000000FU
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE1 */
-+#define ROGUE_CR_MTS_SCHEDULE1 0x10B00U
-+#define ROGUE_CR_MTS_SCHEDULE1_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_MTS_SCHEDULE1_HOST_SHIFT 8U
-+#define ROGUE_CR_MTS_SCHEDULE1_HOST_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_MTS_SCHEDULE1_HOST_BG_TIMER 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE1_HOST_HOST 0x00000100U
-+#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_SHIFT 6U
-+#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT1 0x00000040U
-+#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT2 0x00000080U
-+#define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT3 0x000000C0U
-+#define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_SHIFT 5U
-+#define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_BGCTX 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_INTCTX 0x00000020U
-+#define ROGUE_CR_MTS_SCHEDULE1_TASK_SHIFT 4U
-+#define ROGUE_CR_MTS_SCHEDULE1_TASK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SCHEDULE1_TASK_NON_COUNTED 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE1_TASK_COUNTED 0x00000010U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_CLRMSK 0xFFFFFFF0U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM1 0x00000001U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM2 0x00000002U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM3 0x00000003U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM4 0x00000004U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM5 0x00000005U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM6 0x00000006U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM7 0x00000007U
-+#define ROGUE_CR_MTS_SCHEDULE1_DM_DM_ALL 0x0000000FU
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE2 */
-+#define ROGUE_CR_MTS_SCHEDULE2 0x20B00U
-+#define ROGUE_CR_MTS_SCHEDULE2_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_MTS_SCHEDULE2_HOST_SHIFT 8U
-+#define ROGUE_CR_MTS_SCHEDULE2_HOST_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_MTS_SCHEDULE2_HOST_BG_TIMER 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE2_HOST_HOST 0x00000100U
-+#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_SHIFT 6U
-+#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT1 0x00000040U
-+#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT2 0x00000080U
-+#define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT3 0x000000C0U
-+#define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_SHIFT 5U
-+#define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_BGCTX 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_INTCTX 0x00000020U
-+#define ROGUE_CR_MTS_SCHEDULE2_TASK_SHIFT 4U
-+#define ROGUE_CR_MTS_SCHEDULE2_TASK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SCHEDULE2_TASK_NON_COUNTED 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE2_TASK_COUNTED 0x00000010U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_CLRMSK 0xFFFFFFF0U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM1 0x00000001U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM2 0x00000002U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM3 0x00000003U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM4 0x00000004U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM5 0x00000005U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM6 0x00000006U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM7 0x00000007U
-+#define ROGUE_CR_MTS_SCHEDULE2_DM_DM_ALL 0x0000000FU
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE3 */
-+#define ROGUE_CR_MTS_SCHEDULE3 0x30B00U
-+#define ROGUE_CR_MTS_SCHEDULE3_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_MTS_SCHEDULE3_HOST_SHIFT 8U
-+#define ROGUE_CR_MTS_SCHEDULE3_HOST_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_MTS_SCHEDULE3_HOST_BG_TIMER 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE3_HOST_HOST 0x00000100U
-+#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_SHIFT 6U
-+#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT1 0x00000040U
-+#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT2 0x00000080U
-+#define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT3 0x000000C0U
-+#define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_SHIFT 5U
-+#define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_BGCTX 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_INTCTX 0x00000020U
-+#define ROGUE_CR_MTS_SCHEDULE3_TASK_SHIFT 4U
-+#define ROGUE_CR_MTS_SCHEDULE3_TASK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SCHEDULE3_TASK_NON_COUNTED 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE3_TASK_COUNTED 0x00000010U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_CLRMSK 0xFFFFFFF0U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM1 0x00000001U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM2 0x00000002U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM3 0x00000003U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM4 0x00000004U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM5 0x00000005U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM6 0x00000006U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM7 0x00000007U
-+#define ROGUE_CR_MTS_SCHEDULE3_DM_DM_ALL 0x0000000FU
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE4 */
-+#define ROGUE_CR_MTS_SCHEDULE4 0x40B00U
-+#define ROGUE_CR_MTS_SCHEDULE4_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_MTS_SCHEDULE4_HOST_SHIFT 8U
-+#define ROGUE_CR_MTS_SCHEDULE4_HOST_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_MTS_SCHEDULE4_HOST_BG_TIMER 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE4_HOST_HOST 0x00000100U
-+#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_SHIFT 6U
-+#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT1 0x00000040U
-+#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT2 0x00000080U
-+#define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT3 0x000000C0U
-+#define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_SHIFT 5U
-+#define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_BGCTX 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_INTCTX 0x00000020U
-+#define ROGUE_CR_MTS_SCHEDULE4_TASK_SHIFT 4U
-+#define ROGUE_CR_MTS_SCHEDULE4_TASK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SCHEDULE4_TASK_NON_COUNTED 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE4_TASK_COUNTED 0x00000010U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_CLRMSK 0xFFFFFFF0U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM1 0x00000001U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM2 0x00000002U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM3 0x00000003U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM4 0x00000004U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM5 0x00000005U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM6 0x00000006U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM7 0x00000007U
-+#define ROGUE_CR_MTS_SCHEDULE4_DM_DM_ALL 0x0000000FU
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE5 */
-+#define ROGUE_CR_MTS_SCHEDULE5 0x50B00U
-+#define ROGUE_CR_MTS_SCHEDULE5_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_MTS_SCHEDULE5_HOST_SHIFT 8U
-+#define ROGUE_CR_MTS_SCHEDULE5_HOST_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_MTS_SCHEDULE5_HOST_BG_TIMER 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE5_HOST_HOST 0x00000100U
-+#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_SHIFT 6U
-+#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT1 0x00000040U
-+#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT2 0x00000080U
-+#define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT3 0x000000C0U
-+#define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_SHIFT 5U
-+#define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_BGCTX 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_INTCTX 0x00000020U
-+#define ROGUE_CR_MTS_SCHEDULE5_TASK_SHIFT 4U
-+#define ROGUE_CR_MTS_SCHEDULE5_TASK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SCHEDULE5_TASK_NON_COUNTED 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE5_TASK_COUNTED 0x00000010U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_CLRMSK 0xFFFFFFF0U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM1 0x00000001U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM2 0x00000002U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM3 0x00000003U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM4 0x00000004U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM5 0x00000005U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM6 0x00000006U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM7 0x00000007U
-+#define ROGUE_CR_MTS_SCHEDULE5_DM_DM_ALL 0x0000000FU
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE6 */
-+#define ROGUE_CR_MTS_SCHEDULE6 0x60B00U
-+#define ROGUE_CR_MTS_SCHEDULE6_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_MTS_SCHEDULE6_HOST_SHIFT 8U
-+#define ROGUE_CR_MTS_SCHEDULE6_HOST_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_MTS_SCHEDULE6_HOST_BG_TIMER 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE6_HOST_HOST 0x00000100U
-+#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_SHIFT 6U
-+#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT1 0x00000040U
-+#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT2 0x00000080U
-+#define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT3 0x000000C0U
-+#define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_SHIFT 5U
-+#define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_BGCTX 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_INTCTX 0x00000020U
-+#define ROGUE_CR_MTS_SCHEDULE6_TASK_SHIFT 4U
-+#define ROGUE_CR_MTS_SCHEDULE6_TASK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SCHEDULE6_TASK_NON_COUNTED 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE6_TASK_COUNTED 0x00000010U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_CLRMSK 0xFFFFFFF0U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM1 0x00000001U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM2 0x00000002U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM3 0x00000003U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM4 0x00000004U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM5 0x00000005U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM6 0x00000006U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM7 0x00000007U
-+#define ROGUE_CR_MTS_SCHEDULE6_DM_DM_ALL 0x0000000FU
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE7 */
-+#define ROGUE_CR_MTS_SCHEDULE7 0x70B00U
-+#define ROGUE_CR_MTS_SCHEDULE7_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_MTS_SCHEDULE7_HOST_SHIFT 8U
-+#define ROGUE_CR_MTS_SCHEDULE7_HOST_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_MTS_SCHEDULE7_HOST_BG_TIMER 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE7_HOST_HOST 0x00000100U
-+#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_SHIFT 6U
-+#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT1 0x00000040U
-+#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT2 0x00000080U
-+#define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT3 0x000000C0U
-+#define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_SHIFT 5U
-+#define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_BGCTX 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_INTCTX 0x00000020U
-+#define ROGUE_CR_MTS_SCHEDULE7_TASK_SHIFT 4U
-+#define ROGUE_CR_MTS_SCHEDULE7_TASK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SCHEDULE7_TASK_NON_COUNTED 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE7_TASK_COUNTED 0x00000010U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_CLRMSK 0xFFFFFFF0U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM0 0x00000000U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM1 0x00000001U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM2 0x00000002U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM3 0x00000003U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM4 0x00000004U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM5 0x00000005U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM6 0x00000006U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM7 0x00000007U
-+#define ROGUE_CR_MTS_SCHEDULE7_DM_DM_ALL 0x0000000FU
-+
-+/* Register ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC */
-+#define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC 0x0B30U
-+#define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U
-+#define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC */
-+#define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC 0x0B38U
-+#define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U
-+#define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC */
-+#define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC 0x0B40U
-+#define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U
-+#define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC */
-+#define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC 0x0B48U
-+#define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U
-+#define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG */
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG 0x0B50U
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__MASKFULL 0x000FF0FFFFFFF701ULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_MASKFULL 0x0000FFFFFFFFF001ULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT 44U
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_CLRMSK 0xFFFF0FFFFFFFFFFFULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_SHIFT 44U
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_CLRMSK 0xFFF00FFFFFFFFFFFULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT 40U
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_CLRMSK 0xFFFFF0FFFFFFFFFFULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_SHIFT 12U
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_SHIFT 9U
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_CLRMSK 0xFFFFFFFFFFFFF9FFULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_SHIFT 8U
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_CLRMSK 0xFFFFFFFFFFFFFEFFULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_EN 0x0000000000000100ULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_SHIFT 0U
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META 0x0000000000000000ULL
-+#define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_MTS 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE */
-+#define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE 0x0B58U
-+#define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE */
-+#define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE 0x0B60U
-+#define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE */
-+#define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE 0x0B68U
-+#define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE */
-+#define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE 0x0B70U
-+#define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE */
-+#define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE 0x0B78U
-+#define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE */
-+#define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE 0x0B80U
-+#define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_MTS_INTCTX */
-+#define ROGUE_CR_MTS_INTCTX 0x0B98U
-+#define ROGUE_CR_MTS_INTCTX_MASKFULL 0x000000003FFFFFFFULL
-+#define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_SHIFT 22U
-+#define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_CLRMSK 0xC03FFFFFU
-+#define ROGUE_CR_MTS_INTCTX_DM_PTR_SHIFT 18U
-+#define ROGUE_CR_MTS_INTCTX_DM_PTR_CLRMSK 0xFFC3FFFFU
-+#define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_SHIFT 16U
-+#define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_CLRMSK 0xFFFCFFFFU
-+#define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_SHIFT 8U
-+#define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_CLRMSK 0xFFFF00FFU
-+#define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_SHIFT 0U
-+#define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_MTS_BGCTX */
-+#define ROGUE_CR_MTS_BGCTX 0x0BA0U
-+#define ROGUE_CR_MTS_BGCTX_MASKFULL 0x0000000000003FFFULL
-+#define ROGUE_CR_MTS_BGCTX_DM_PTR_SHIFT 10U
-+#define ROGUE_CR_MTS_BGCTX_DM_PTR_CLRMSK 0xFFFFC3FFU
-+#define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_SHIFT 8U
-+#define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_CLRMSK 0xFFFFFCFFU
-+#define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_SHIFT 0U
-+#define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE */
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE 0x0BA8U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_SHIFT 56U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_CLRMSK 0x00FFFFFFFFFFFFFFULL
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_SHIFT 48U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_CLRMSK 0xFF00FFFFFFFFFFFFULL
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_SHIFT 40U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_CLRMSK 0xFFFF00FFFFFFFFFFULL
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_SHIFT 32U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_CLRMSK 0xFFFFFF00FFFFFFFFULL
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_SHIFT 24U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_CLRMSK 0xFFFFFFFF00FFFFFFULL
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_SHIFT 16U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_CLRMSK 0xFFFFFFFFFF00FFFFULL
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_SHIFT 8U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_CLRMSK 0xFFFFFFFFFFFF00FFULL
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_SHIFT 0U
-+#define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_CLRMSK 0xFFFFFFFFFFFFFF00ULL
-+
-+/* Register ROGUE_CR_MTS_GPU_INT_STATUS */
-+#define ROGUE_CR_MTS_GPU_INT_STATUS 0x0BB0U
-+#define ROGUE_CR_MTS_GPU_INT_STATUS_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_SHIFT 0U
-+#define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_MTS_SCHEDULE_ENABLE */
-+#define ROGUE_CR_MTS_SCHEDULE_ENABLE 0x0BC8U
-+#define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_SHIFT 0U
-+#define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_IRQ_OS0_EVENT_STATUS */
-+#define ROGUE_CR_IRQ_OS0_EVENT_STATUS 0x0BD8U
-+#define ROGUE_CR_IRQ_OS0_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS0_EVENT_CLEAR */
-+#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR 0x0BE8U
-+#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS1_EVENT_STATUS */
-+#define ROGUE_CR_IRQ_OS1_EVENT_STATUS 0x10BD8U
-+#define ROGUE_CR_IRQ_OS1_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS1_EVENT_CLEAR */
-+#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR 0x10BE8U
-+#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS2_EVENT_STATUS */
-+#define ROGUE_CR_IRQ_OS2_EVENT_STATUS 0x20BD8U
-+#define ROGUE_CR_IRQ_OS2_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS2_EVENT_CLEAR */
-+#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR 0x20BE8U
-+#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS3_EVENT_STATUS */
-+#define ROGUE_CR_IRQ_OS3_EVENT_STATUS 0x30BD8U
-+#define ROGUE_CR_IRQ_OS3_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS3_EVENT_CLEAR */
-+#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR 0x30BE8U
-+#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS4_EVENT_STATUS */
-+#define ROGUE_CR_IRQ_OS4_EVENT_STATUS 0x40BD8U
-+#define ROGUE_CR_IRQ_OS4_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS4_EVENT_CLEAR */
-+#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR 0x40BE8U
-+#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS5_EVENT_STATUS */
-+#define ROGUE_CR_IRQ_OS5_EVENT_STATUS 0x50BD8U
-+#define ROGUE_CR_IRQ_OS5_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS5_EVENT_CLEAR */
-+#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR 0x50BE8U
-+#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS6_EVENT_STATUS */
-+#define ROGUE_CR_IRQ_OS6_EVENT_STATUS 0x60BD8U
-+#define ROGUE_CR_IRQ_OS6_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS6_EVENT_CLEAR */
-+#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR 0x60BE8U
-+#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS7_EVENT_STATUS */
-+#define ROGUE_CR_IRQ_OS7_EVENT_STATUS 0x70BD8U
-+#define ROGUE_CR_IRQ_OS7_EVENT_STATUS_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_IRQ_OS7_EVENT_CLEAR */
-+#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR 0x70BE8U
-+#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_SHIFT 0U
-+#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_META_BOOT */
-+#define ROGUE_CR_META_BOOT 0x0BF8U
-+#define ROGUE_CR_META_BOOT_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_META_BOOT_MODE_SHIFT 0U
-+#define ROGUE_CR_META_BOOT_MODE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_META_BOOT_MODE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_GARTEN_SLC */
-+#define ROGUE_CR_GARTEN_SLC 0x0BB8U
-+#define ROGUE_CR_GARTEN_SLC_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_SHIFT 0U
-+#define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_EN 0x00000001U
-+
-+/* Register ROGUE_CR_PPP */
-+#define ROGUE_CR_PPP 0x0CD0U
-+#define ROGUE_CR_PPP_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PPP_CHECKSUM_SHIFT 0U
-+#define ROGUE_CR_PPP_CHECKSUM_CLRMSK 0x00000000U
-+
-+#define ROGUE_CR_ISP_RENDER_DIR_TYPE_MASK 0x00000003U
-+/* Top-left to bottom-right */
-+#define ROGUE_CR_ISP_RENDER_DIR_TYPE_TL2BR 0x00000000U
-+/* Top-right to bottom-left */
-+#define ROGUE_CR_ISP_RENDER_DIR_TYPE_TR2BL 0x00000001U
-+/* Bottom-left to top-right */
-+#define ROGUE_CR_ISP_RENDER_DIR_TYPE_BL2TR 0x00000002U
-+/* Bottom-right to top-left */
-+#define ROGUE_CR_ISP_RENDER_DIR_TYPE_BR2TL 0x00000003U
-+
-+#define ROGUE_CR_ISP_RENDER_MODE_TYPE_MASK 0x00000003U
-+/* Normal render */
-+#define ROGUE_CR_ISP_RENDER_MODE_TYPE_NORM 0x00000000U
-+/* Fast 2D render */
-+#define ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_2D 0x00000002U
-+/* Fast scale render */
-+#define ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_SCALE 0x00000003U
-+
-+/* Register ROGUE_CR_ISP_RENDER */
-+#define ROGUE_CR_ISP_RENDER 0x0F08U
-+#define ROGUE_CR_ISP_RENDER_MASKFULL 0x00000000000001FFULL
-+#define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_SHIFT 8U
-+#define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_EN 0x00000100U
-+#define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_SHIFT 7U
-+#define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_CLRMSK 0xFFFFFF7FU
-+#define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_EN 0x00000080U
-+#define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_SHIFT 6U
-+#define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_EN 0x00000040U
-+#define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_SHIFT 5U
-+#define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_EN 0x00000020U
-+#define ROGUE_CR_ISP_RENDER_RESUME_SHIFT 4U
-+#define ROGUE_CR_ISP_RENDER_RESUME_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_ISP_RENDER_RESUME_EN 0x00000010U
-+#define ROGUE_CR_ISP_RENDER_DIR_SHIFT 2U
-+#define ROGUE_CR_ISP_RENDER_DIR_CLRMSK 0xFFFFFFF3U
-+#define ROGUE_CR_ISP_RENDER_DIR_TL2BR 0x00000000U
-+#define ROGUE_CR_ISP_RENDER_DIR_TR2BL 0x00000004U
-+#define ROGUE_CR_ISP_RENDER_DIR_BL2TR 0x00000008U
-+#define ROGUE_CR_ISP_RENDER_DIR_BR2TL 0x0000000CU
-+#define ROGUE_CR_ISP_RENDER_MODE_SHIFT 0U
-+#define ROGUE_CR_ISP_RENDER_MODE_CLRMSK 0xFFFFFFFCU
-+#define ROGUE_CR_ISP_RENDER_MODE_NORM 0x00000000U
-+#define ROGUE_CR_ISP_RENDER_MODE_FAST_2D 0x00000002U
-+#define ROGUE_CR_ISP_RENDER_MODE_FAST_SCALE 0x00000003U
-+
-+/* Register ROGUE_CR_ISP_CTL */
-+#define ROGUE_CR_ISP_CTL 0x0F38U
-+#define ROGUE_CR_ISP_CTL_MASKFULL 0x00000000FFFFF3FFULL
-+#define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_SHIFT 31U
-+#define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_CLRMSK 0x7FFFFFFFU
-+#define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_EN 0x80000000U
-+#define ROGUE_CR_ISP_CTL_LINE_STYLE_SHIFT 30U
-+#define ROGUE_CR_ISP_CTL_LINE_STYLE_CLRMSK 0xBFFFFFFFU
-+#define ROGUE_CR_ISP_CTL_LINE_STYLE_EN 0x40000000U
-+#define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_SHIFT 29U
-+#define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_EN 0x20000000U
-+#define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_SHIFT 28U
-+#define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_EN 0x10000000U
-+#define ROGUE_CR_ISP_CTL_PAIR_TILES_SHIFT 27U
-+#define ROGUE_CR_ISP_CTL_PAIR_TILES_CLRMSK 0xF7FFFFFFU
-+#define ROGUE_CR_ISP_CTL_PAIR_TILES_EN 0x08000000U
-+#define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_SHIFT 26U
-+#define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_CLRMSK 0xFBFFFFFFU
-+#define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_EN 0x04000000U
-+#define ROGUE_CR_ISP_CTL_TILE_AGE_EN_SHIFT 25U
-+#define ROGUE_CR_ISP_CTL_TILE_AGE_EN_CLRMSK 0xFDFFFFFFU
-+#define ROGUE_CR_ISP_CTL_TILE_AGE_EN_EN 0x02000000U
-+#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_SHIFT 23U
-+#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_CLRMSK 0xFE7FFFFFU
-+#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_DX9 0x00000000U
-+#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_DX10 0x00800000U
-+#define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_OGL 0x01000000U
-+#define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_SHIFT 21U
-+#define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_CLRMSK 0xFF9FFFFFU
-+#define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_SHIFT 20U
-+#define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_CLRMSK 0xFFEFFFFFU
-+#define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_EN 0x00100000U
-+#define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_SHIFT 19U
-+#define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_CLRMSK 0xFFF7FFFFU
-+#define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_EN 0x00080000U
-+#define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_SHIFT 18U
-+#define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_CLRMSK 0xFFFBFFFFU
-+#define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_EN 0x00040000U
-+#define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_SHIFT 17U
-+#define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_CLRMSK 0xFFFDFFFFU
-+#define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_EN 0x00020000U
-+#define ROGUE_CR_ISP_CTL_SAMPLE_POS_SHIFT 16U
-+#define ROGUE_CR_ISP_CTL_SAMPLE_POS_CLRMSK 0xFFFEFFFFU
-+#define ROGUE_CR_ISP_CTL_SAMPLE_POS_EN 0x00010000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_SHIFT 12U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_CLRMSK 0xFFFF0FFFU
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_ONE 0x00000000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TWO 0x00001000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_THREE 0x00002000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FOUR 0x00003000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FIVE 0x00004000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SIX 0x00005000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SEVEN 0x00006000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_EIGHT 0x00007000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_NINE 0x00008000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TEN 0x00009000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_ELEVEN 0x0000A000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TWELVE 0x0000B000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_THIRTEEN 0x0000C000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FOURTEEN 0x0000D000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FIFTEEN 0x0000E000U
-+#define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SIXTEEN 0x0000F000U
-+#define ROGUE_CR_ISP_CTL_VALID_ID_SHIFT 4U
-+#define ROGUE_CR_ISP_CTL_VALID_ID_CLRMSK 0xFFFFFC0FU
-+#define ROGUE_CR_ISP_CTL_UPASS_START_SHIFT 0U
-+#define ROGUE_CR_ISP_CTL_UPASS_START_CLRMSK 0xFFFFFFF0U
-+
-+/* Register ROGUE_CR_ISP_STATUS */
-+#define ROGUE_CR_ISP_STATUS 0x1038U
-+#define ROGUE_CR_ISP_STATUS_MASKFULL 0x0000000000000007ULL
-+#define ROGUE_CR_ISP_STATUS_SPLIT_MAX_SHIFT 2U
-+#define ROGUE_CR_ISP_STATUS_SPLIT_MAX_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_ISP_STATUS_SPLIT_MAX_EN 0x00000004U
-+#define ROGUE_CR_ISP_STATUS_ACTIVE_SHIFT 1U
-+#define ROGUE_CR_ISP_STATUS_ACTIVE_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_ISP_STATUS_ACTIVE_EN 0x00000002U
-+#define ROGUE_CR_ISP_STATUS_EOR_SHIFT 0U
-+#define ROGUE_CR_ISP_STATUS_EOR_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_ISP_STATUS_EOR_EN 0x00000001U
-+
-+/* Register group: ROGUE_CR_ISP_XTP_RESUME, with 64 repeats */
-+#define ROGUE_CR_ISP_XTP_RESUME_REPEATCOUNT 64U
-+/* Register ROGUE_CR_ISP_XTP_RESUME0 */
-+#define ROGUE_CR_ISP_XTP_RESUME0 0x3A00U
-+#define ROGUE_CR_ISP_XTP_RESUME0_MASKFULL 0x00000000003FF3FFULL
-+#define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_SHIFT 12U
-+#define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_CLRMSK 0xFFC00FFFU
-+#define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_SHIFT 0U
-+#define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_CLRMSK 0xFFFFFC00U
-+
-+/* Register group: ROGUE_CR_ISP_XTP_STORE, with 32 repeats */
-+#define ROGUE_CR_ISP_XTP_STORE_REPEATCOUNT 32U
-+/* Register ROGUE_CR_ISP_XTP_STORE0 */
-+#define ROGUE_CR_ISP_XTP_STORE0 0x3C00U
-+#define ROGUE_CR_ISP_XTP_STORE0_MASKFULL 0x000000007F3FF3FFULL
-+#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_SHIFT 30U
-+#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_CLRMSK 0xBFFFFFFFU
-+#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_EN 0x40000000U
-+#define ROGUE_CR_ISP_XTP_STORE0_EOR_SHIFT 29U
-+#define ROGUE_CR_ISP_XTP_STORE0_EOR_CLRMSK 0xDFFFFFFFU
-+#define ROGUE_CR_ISP_XTP_STORE0_EOR_EN 0x20000000U
-+#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_SHIFT 28U
-+#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_EN 0x10000000U
-+#define ROGUE_CR_ISP_XTP_STORE0_MT_SHIFT 24U
-+#define ROGUE_CR_ISP_XTP_STORE0_MT_CLRMSK 0xF0FFFFFFU
-+#define ROGUE_CR_ISP_XTP_STORE0_TILE_X_SHIFT 12U
-+#define ROGUE_CR_ISP_XTP_STORE0_TILE_X_CLRMSK 0xFFC00FFFU
-+#define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_SHIFT 0U
-+#define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_CLRMSK 0xFFFFFC00U
-+
-+/* Register group: ROGUE_CR_BIF_CAT_BASE, with 8 repeats */
-+#define ROGUE_CR_BIF_CAT_BASE_REPEATCOUNT 8U
-+/* Register ROGUE_CR_BIF_CAT_BASE0 */
-+#define ROGUE_CR_BIF_CAT_BASE0 0x1200U
-+#define ROGUE_CR_BIF_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_BIF_CAT_BASE0_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_CAT_BASE1 */
-+#define ROGUE_CR_BIF_CAT_BASE1 0x1208U
-+#define ROGUE_CR_BIF_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_BIF_CAT_BASE1_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_CAT_BASE2 */
-+#define ROGUE_CR_BIF_CAT_BASE2 0x1210U
-+#define ROGUE_CR_BIF_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_BIF_CAT_BASE2_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_CAT_BASE3 */
-+#define ROGUE_CR_BIF_CAT_BASE3 0x1218U
-+#define ROGUE_CR_BIF_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_BIF_CAT_BASE3_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_CAT_BASE4 */
-+#define ROGUE_CR_BIF_CAT_BASE4 0x1220U
-+#define ROGUE_CR_BIF_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_BIF_CAT_BASE4_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_CAT_BASE5 */
-+#define ROGUE_CR_BIF_CAT_BASE5 0x1228U
-+#define ROGUE_CR_BIF_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_BIF_CAT_BASE5_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_CAT_BASE6 */
-+#define ROGUE_CR_BIF_CAT_BASE6 0x1230U
-+#define ROGUE_CR_BIF_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_BIF_CAT_BASE6_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_CAT_BASE7 */
-+#define ROGUE_CR_BIF_CAT_BASE7 0x1238U
-+#define ROGUE_CR_BIF_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_BIF_CAT_BASE7_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_CAT_BASE_INDEX */
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX 0x1240U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_MASKFULL 0x00070707073F0707ULL
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_SHIFT 48U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_CLRMSK 0xFFF8FFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_SHIFT 40U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_SHIFT 32U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_CLRMSK 0xFFFFFFF8FFFFFFFFULL
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_SHIFT 24U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_CLRMSK 0xFFFFFFFFF8FFFFFFULL
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_SHIFT 19U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_CLRMSK 0xFFFFFFFFFFC7FFFFULL
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_SHIFT 16U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_CLRMSK 0xFFFFFFFFFFF8FFFFULL
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_SHIFT 8U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_CLRMSK 0xFFFFFFFFFFFFF8FFULL
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_SHIFT 0U
-+#define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_CLRMSK 0xFFFFFFFFFFFFFFF8ULL
-+
-+/* Register ROGUE_CR_BIF_PM_CAT_BASE_VCE0 */
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0 0x1248U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_MASKFULL 0x0FFFFFFFFFFFF003ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_SHIFT 40U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_SHIFT 1U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_EN 0x0000000000000002ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_SHIFT 0U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_BIF_PM_CAT_BASE_TE0 */
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0 0x1250U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_MASKFULL 0x0FFFFFFFFFFFF003ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_SHIFT 40U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_SHIFT 1U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_EN 0x0000000000000002ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_SHIFT 0U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_BIF_PM_CAT_BASE_ALIST0 */
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0 0x1260U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_MASKFULL 0x0FFFFFFFFFFFF003ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT 40U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_SHIFT 1U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_EN 0x0000000000000002ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_SHIFT 0U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_BIF_PM_CAT_BASE_VCE1 */
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1 0x1268U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_MASKFULL 0x0FFFFFFFFFFFF003ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_SHIFT 40U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_SHIFT 1U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_EN 0x0000000000000002ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_SHIFT 0U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_BIF_PM_CAT_BASE_TE1 */
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1 0x1270U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_MASKFULL 0x0FFFFFFFFFFFF003ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_SHIFT 40U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_SHIFT 1U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_EN 0x0000000000000002ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_SHIFT 0U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_BIF_PM_CAT_BASE_ALIST1 */
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1 0x1280U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_MASKFULL 0x0FFFFFFFFFFFF003ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT 40U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_SHIFT 12U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_SHIFT 1U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_EN 0x0000000000000002ULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_SHIFT 0U
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_BIF_MMU_ENTRY_STATUS */
-+#define ROGUE_CR_BIF_MMU_ENTRY_STATUS 0x1288U
-+#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_MASKFULL 0x000000FFFFFFF0F3ULL
-+#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_SHIFT 12U
-+#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_SHIFT 4U
-+#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_CLRMSK 0xFFFFFFFFFFFFFF0FULL
-+#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_SHIFT 0U
-+#define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_CLRMSK 0xFFFFFFFFFFFFFFFCULL
-+
-+/* Register ROGUE_CR_BIF_MMU_ENTRY */
-+#define ROGUE_CR_BIF_MMU_ENTRY 0x1290U
-+#define ROGUE_CR_BIF_MMU_ENTRY_MASKFULL 0x0000000000000003ULL
-+#define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_SHIFT 1U
-+#define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_EN 0x00000002U
-+#define ROGUE_CR_BIF_MMU_ENTRY_PENDING_SHIFT 0U
-+#define ROGUE_CR_BIF_MMU_ENTRY_PENDING_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BIF_MMU_ENTRY_PENDING_EN 0x00000001U
-+
-+/* Register ROGUE_CR_BIF_CTRL_INVAL */
-+#define ROGUE_CR_BIF_CTRL_INVAL 0x12A0U
-+#define ROGUE_CR_BIF_CTRL_INVAL_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_BIF_CTRL_INVAL_TLB1_SHIFT 3U
-+#define ROGUE_CR_BIF_CTRL_INVAL_TLB1_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_BIF_CTRL_INVAL_TLB1_EN 0x00000008U
-+#define ROGUE_CR_BIF_CTRL_INVAL_PC_SHIFT 2U
-+#define ROGUE_CR_BIF_CTRL_INVAL_PC_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_BIF_CTRL_INVAL_PC_EN 0x00000004U
-+#define ROGUE_CR_BIF_CTRL_INVAL_PD_SHIFT 1U
-+#define ROGUE_CR_BIF_CTRL_INVAL_PD_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_BIF_CTRL_INVAL_PD_EN 0x00000002U
-+#define ROGUE_CR_BIF_CTRL_INVAL_PT_SHIFT 0U
-+#define ROGUE_CR_BIF_CTRL_INVAL_PT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BIF_CTRL_INVAL_PT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_BIF_CTRL */
-+#define ROGUE_CR_BIF_CTRL 0x12A8U
-+#define ROGUE_CR_BIF_CTRL__XE_MEM__MASKFULL 0x000000000000033FULL
-+#define ROGUE_CR_BIF_CTRL_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_SHIFT 9U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_CLRMSK 0xFFFFFDFFU
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_EN 0x00000200U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_SHIFT 8U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_EN 0x00000100U
-+#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_SHIFT 7U
-+#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_CLRMSK 0xFFFFFF7FU
-+#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_EN 0x00000080U
-+#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_SHIFT 6U
-+#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_EN 0x00000040U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_SHIFT 5U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_EN 0x00000020U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_SHIFT 4U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_EN 0x00000010U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_SHIFT 3U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_EN 0x00000008U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_SHIFT 2U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_EN 0x00000004U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_SHIFT 1U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_EN 0x00000002U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_SHIFT 0U
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_EN 0x00000001U
-+
-+/* Register ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS */
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS 0x12B0U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_MASKFULL 0x000000000000F775ULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_EN 0x00000010U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS */
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS 0x12B8U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__MASKFULL 0x001FFFFFFFFFFFF0ULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_SHIFT 52U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_CLRMSK 0xFFEFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_EN 0x0010000000000000ULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_EN 0x0004000000000000ULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_SHIFT 46U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_CLRMSK 0xFFF03FFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_SHIFT 40U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_CLRMSK 0xFFFFC0FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
-+#define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS */
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS 0x12C0U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_MASKFULL 0x000000000000F775ULL
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_SHIFT 12U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_SHIFT 8U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_SHIFT 5U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_SHIFT 4U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_EN 0x00000010U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_SHIFT 0U
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS */
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS 0x12C8U
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_SHIFT 50U
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_EN 0x0004000000000000ULL
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_SHIFT 44U
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_SHIFT 40U
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_SHIFT 4U
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
-+#define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_BIF_MMU_STATUS */
-+#define ROGUE_CR_BIF_MMU_STATUS 0x12D0U
-+#define ROGUE_CR_BIF_MMU_STATUS__XE_MEM__MASKFULL 0x000000001FFFFFF7ULL
-+#define ROGUE_CR_BIF_MMU_STATUS_MASKFULL 0x000000001FFFFFF7ULL
-+#define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_SHIFT 28U
-+#define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_CLRMSK 0xEFFFFFFFU
-+#define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_EN 0x10000000U
-+#define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U
-+#define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU
-+#define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U
-+#define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU
-+#define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U
-+#define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU
-+#define ROGUE_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U
-+#define ROGUE_CR_BIF_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_BIF_MMU_STATUS_STALLED_EN 0x00000004U
-+#define ROGUE_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U
-+#define ROGUE_CR_BIF_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_BIF_MMU_STATUS_PAUSED_EN 0x00000002U
-+#define ROGUE_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U
-+#define ROGUE_CR_BIF_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U
-+
-+/* Register group: ROGUE_CR_BIF_TILING_CFG, with 8 repeats */
-+#define ROGUE_CR_BIF_TILING_CFG_REPEATCOUNT 8U
-+/* Register ROGUE_CR_BIF_TILING_CFG0 */
-+#define ROGUE_CR_BIF_TILING_CFG0 0x12D8U
-+#define ROGUE_CR_BIF_TILING_CFG0_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_SHIFT 61U
-+#define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_SHIFT 60U
-+#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_SHIFT 32U
-+#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSIZE 4096U
-+#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_TILING_CFG1 */
-+#define ROGUE_CR_BIF_TILING_CFG1 0x12E0U
-+#define ROGUE_CR_BIF_TILING_CFG1_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_SHIFT 61U
-+#define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_SHIFT 60U
-+#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_SHIFT 32U
-+#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSIZE 4096U
-+#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_TILING_CFG2 */
-+#define ROGUE_CR_BIF_TILING_CFG2 0x12E8U
-+#define ROGUE_CR_BIF_TILING_CFG2_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_SHIFT 61U
-+#define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_SHIFT 60U
-+#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_SHIFT 32U
-+#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSIZE 4096U
-+#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_TILING_CFG3 */
-+#define ROGUE_CR_BIF_TILING_CFG3 0x12F0U
-+#define ROGUE_CR_BIF_TILING_CFG3_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_SHIFT 61U
-+#define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_SHIFT 60U
-+#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_SHIFT 32U
-+#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSIZE 4096U
-+#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_TILING_CFG4 */
-+#define ROGUE_CR_BIF_TILING_CFG4 0x12F8U
-+#define ROGUE_CR_BIF_TILING_CFG4_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_SHIFT 61U
-+#define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_SHIFT 60U
-+#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_SHIFT 32U
-+#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSIZE 4096U
-+#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_TILING_CFG5 */
-+#define ROGUE_CR_BIF_TILING_CFG5 0x1300U
-+#define ROGUE_CR_BIF_TILING_CFG5_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_SHIFT 61U
-+#define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_SHIFT 60U
-+#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_SHIFT 32U
-+#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSIZE 4096U
-+#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_TILING_CFG6 */
-+#define ROGUE_CR_BIF_TILING_CFG6 0x1308U
-+#define ROGUE_CR_BIF_TILING_CFG6_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_SHIFT 61U
-+#define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_SHIFT 60U
-+#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_SHIFT 32U
-+#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSIZE 4096U
-+#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_TILING_CFG7 */
-+#define ROGUE_CR_BIF_TILING_CFG7 0x1310U
-+#define ROGUE_CR_BIF_TILING_CFG7_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_SHIFT 61U
-+#define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_SHIFT 60U
-+#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_EN 0x1000000000000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_SHIFT 32U
-+#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-+#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSIZE 4096U
-+#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_SHIFT 0U
-+#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-+#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSHIFT 12U
-+#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_BIF_READS_EXT_STATUS */
-+#define ROGUE_CR_BIF_READS_EXT_STATUS 0x1320U
-+#define ROGUE_CR_BIF_READS_EXT_STATUS_MASKFULL 0x000000000FFFFFFFULL
-+#define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_SHIFT 16U
-+#define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_CLRMSK 0xF000FFFFU
-+#define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_SHIFT 0U
-+#define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_BIF_READS_INT_STATUS */
-+#define ROGUE_CR_BIF_READS_INT_STATUS 0x1328U
-+#define ROGUE_CR_BIF_READS_INT_STATUS_MASKFULL 0x0000000007FFFFFFULL
-+#define ROGUE_CR_BIF_READS_INT_STATUS_MMU_SHIFT 16U
-+#define ROGUE_CR_BIF_READS_INT_STATUS_MMU_CLRMSK 0xF800FFFFU
-+#define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_SHIFT 0U
-+#define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_BIFPM_READS_INT_STATUS */
-+#define ROGUE_CR_BIFPM_READS_INT_STATUS 0x1330U
-+#define ROGUE_CR_BIFPM_READS_INT_STATUS_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_SHIFT 0U
-+#define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_BIFPM_READS_EXT_STATUS */
-+#define ROGUE_CR_BIFPM_READS_EXT_STATUS 0x1338U
-+#define ROGUE_CR_BIFPM_READS_EXT_STATUS_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_SHIFT 0U
-+#define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_BIFPM_STATUS_MMU */
-+#define ROGUE_CR_BIFPM_STATUS_MMU 0x1350U
-+#define ROGUE_CR_BIFPM_STATUS_MMU_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_SHIFT 0U
-+#define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_BIF_STATUS_MMU */
-+#define ROGUE_CR_BIF_STATUS_MMU 0x1358U
-+#define ROGUE_CR_BIF_STATUS_MMU_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_SHIFT 0U
-+#define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_BIF_FAULT_READ */
-+#define ROGUE_CR_BIF_FAULT_READ 0x13E0U
-+#define ROGUE_CR_BIF_FAULT_READ_MASKFULL 0x000000FFFFFFFFF0ULL
-+#define ROGUE_CR_BIF_FAULT_READ_ADDRESS_SHIFT 4U
-+#define ROGUE_CR_BIF_FAULT_READ_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
-+#define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSHIFT 4U
-+#define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS */
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS 0x1430U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_MASKFULL 0x000000000000F775ULL
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_EN 0x00000010U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS */
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS 0x1438U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_EN 0x0004000000000000ULL
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
-+#define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_MCU_FENCE */
-+#define ROGUE_CR_MCU_FENCE 0x1740U
-+#define ROGUE_CR_MCU_FENCE_MASKFULL 0x000007FFFFFFFFE0ULL
-+#define ROGUE_CR_MCU_FENCE_DM_SHIFT 40U
-+#define ROGUE_CR_MCU_FENCE_DM_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_MCU_FENCE_DM_VERTEX 0x0000000000000000ULL
-+#define ROGUE_CR_MCU_FENCE_DM_PIXEL 0x0000010000000000ULL
-+#define ROGUE_CR_MCU_FENCE_DM_COMPUTE 0x0000020000000000ULL
-+#define ROGUE_CR_MCU_FENCE_DM_RAY_VERTEX 0x0000030000000000ULL
-+#define ROGUE_CR_MCU_FENCE_DM_RAY 0x0000040000000000ULL
-+#define ROGUE_CR_MCU_FENCE_DM_FASTRENDER 0x0000050000000000ULL
-+#define ROGUE_CR_MCU_FENCE_ADDR_SHIFT 5U
-+#define ROGUE_CR_MCU_FENCE_ADDR_CLRMSK 0xFFFFFF000000001FULL
-+#define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSHIFT 5U
-+#define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSIZE 32U
-+
-+/* Register group: ROGUE_CR_SCRATCH, with 16 repeats */
-+#define ROGUE_CR_SCRATCH_REPEATCOUNT 16U
-+/* Register ROGUE_CR_SCRATCH0 */
-+#define ROGUE_CR_SCRATCH0 0x1A00U
-+#define ROGUE_CR_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH1 */
-+#define ROGUE_CR_SCRATCH1 0x1A08U
-+#define ROGUE_CR_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH2 */
-+#define ROGUE_CR_SCRATCH2 0x1A10U
-+#define ROGUE_CR_SCRATCH2_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH2_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH3 */
-+#define ROGUE_CR_SCRATCH3 0x1A18U
-+#define ROGUE_CR_SCRATCH3_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH3_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH4 */
-+#define ROGUE_CR_SCRATCH4 0x1A20U
-+#define ROGUE_CR_SCRATCH4_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH4_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH4_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH5 */
-+#define ROGUE_CR_SCRATCH5 0x1A28U
-+#define ROGUE_CR_SCRATCH5_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH5_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH5_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH6 */
-+#define ROGUE_CR_SCRATCH6 0x1A30U
-+#define ROGUE_CR_SCRATCH6_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH6_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH6_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH7 */
-+#define ROGUE_CR_SCRATCH7 0x1A38U
-+#define ROGUE_CR_SCRATCH7_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH7_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH7_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH8 */
-+#define ROGUE_CR_SCRATCH8 0x1A40U
-+#define ROGUE_CR_SCRATCH8_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH8_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH8_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH9 */
-+#define ROGUE_CR_SCRATCH9 0x1A48U
-+#define ROGUE_CR_SCRATCH9_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH9_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH9_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH10 */
-+#define ROGUE_CR_SCRATCH10 0x1A50U
-+#define ROGUE_CR_SCRATCH10_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH10_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH10_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH11 */
-+#define ROGUE_CR_SCRATCH11 0x1A58U
-+#define ROGUE_CR_SCRATCH11_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH11_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH11_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH12 */
-+#define ROGUE_CR_SCRATCH12 0x1A60U
-+#define ROGUE_CR_SCRATCH12_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH12_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH12_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH13 */
-+#define ROGUE_CR_SCRATCH13 0x1A68U
-+#define ROGUE_CR_SCRATCH13_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH13_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH13_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH14 */
-+#define ROGUE_CR_SCRATCH14 0x1A70U
-+#define ROGUE_CR_SCRATCH14_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH14_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH14_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SCRATCH15 */
-+#define ROGUE_CR_SCRATCH15 0x1A78U
-+#define ROGUE_CR_SCRATCH15_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SCRATCH15_DATA_SHIFT 0U
-+#define ROGUE_CR_SCRATCH15_DATA_CLRMSK 0x00000000U
-+
-+/* Register group: ROGUE_CR_OS0_SCRATCH, with 2 repeats */
-+#define ROGUE_CR_OS0_SCRATCH_REPEATCOUNT 2U
-+/* Register ROGUE_CR_OS0_SCRATCH0 */
-+#define ROGUE_CR_OS0_SCRATCH0 0x1A80U
-+#define ROGUE_CR_OS0_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS0_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_OS0_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS0_SCRATCH1 */
-+#define ROGUE_CR_OS0_SCRATCH1 0x1A88U
-+#define ROGUE_CR_OS0_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS0_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_OS0_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS0_SCRATCH2 */
-+#define ROGUE_CR_OS0_SCRATCH2 0x1A90U
-+#define ROGUE_CR_OS0_SCRATCH2_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS0_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_OS0_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_OS0_SCRATCH3 */
-+#define ROGUE_CR_OS0_SCRATCH3 0x1A98U
-+#define ROGUE_CR_OS0_SCRATCH3_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS0_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_OS0_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register group: ROGUE_CR_OS1_SCRATCH, with 2 repeats */
-+#define ROGUE_CR_OS1_SCRATCH_REPEATCOUNT 2U
-+/* Register ROGUE_CR_OS1_SCRATCH0 */
-+#define ROGUE_CR_OS1_SCRATCH0 0x11A80U
-+#define ROGUE_CR_OS1_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS1_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_OS1_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS1_SCRATCH1 */
-+#define ROGUE_CR_OS1_SCRATCH1 0x11A88U
-+#define ROGUE_CR_OS1_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS1_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_OS1_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS1_SCRATCH2 */
-+#define ROGUE_CR_OS1_SCRATCH2 0x11A90U
-+#define ROGUE_CR_OS1_SCRATCH2_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS1_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_OS1_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_OS1_SCRATCH3 */
-+#define ROGUE_CR_OS1_SCRATCH3 0x11A98U
-+#define ROGUE_CR_OS1_SCRATCH3_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS1_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_OS1_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register group: ROGUE_CR_OS2_SCRATCH, with 2 repeats */
-+#define ROGUE_CR_OS2_SCRATCH_REPEATCOUNT 2U
-+/* Register ROGUE_CR_OS2_SCRATCH0 */
-+#define ROGUE_CR_OS2_SCRATCH0 0x21A80U
-+#define ROGUE_CR_OS2_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS2_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_OS2_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS2_SCRATCH1 */
-+#define ROGUE_CR_OS2_SCRATCH1 0x21A88U
-+#define ROGUE_CR_OS2_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS2_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_OS2_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS2_SCRATCH2 */
-+#define ROGUE_CR_OS2_SCRATCH2 0x21A90U
-+#define ROGUE_CR_OS2_SCRATCH2_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS2_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_OS2_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_OS2_SCRATCH3 */
-+#define ROGUE_CR_OS2_SCRATCH3 0x21A98U
-+#define ROGUE_CR_OS2_SCRATCH3_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS2_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_OS2_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register group: ROGUE_CR_OS3_SCRATCH, with 2 repeats */
-+#define ROGUE_CR_OS3_SCRATCH_REPEATCOUNT 2U
-+/* Register ROGUE_CR_OS3_SCRATCH0 */
-+#define ROGUE_CR_OS3_SCRATCH0 0x31A80U
-+#define ROGUE_CR_OS3_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS3_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_OS3_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS3_SCRATCH1 */
-+#define ROGUE_CR_OS3_SCRATCH1 0x31A88U
-+#define ROGUE_CR_OS3_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS3_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_OS3_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS3_SCRATCH2 */
-+#define ROGUE_CR_OS3_SCRATCH2 0x31A90U
-+#define ROGUE_CR_OS3_SCRATCH2_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS3_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_OS3_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_OS3_SCRATCH3 */
-+#define ROGUE_CR_OS3_SCRATCH3 0x31A98U
-+#define ROGUE_CR_OS3_SCRATCH3_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS3_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_OS3_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register group: ROGUE_CR_OS4_SCRATCH, with 2 repeats */
-+#define ROGUE_CR_OS4_SCRATCH_REPEATCOUNT 2U
-+/* Register ROGUE_CR_OS4_SCRATCH0 */
-+#define ROGUE_CR_OS4_SCRATCH0 0x41A80U
-+#define ROGUE_CR_OS4_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS4_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_OS4_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS4_SCRATCH1 */
-+#define ROGUE_CR_OS4_SCRATCH1 0x41A88U
-+#define ROGUE_CR_OS4_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS4_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_OS4_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS4_SCRATCH2 */
-+#define ROGUE_CR_OS4_SCRATCH2 0x41A90U
-+#define ROGUE_CR_OS4_SCRATCH2_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS4_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_OS4_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_OS4_SCRATCH3 */
-+#define ROGUE_CR_OS4_SCRATCH3 0x41A98U
-+#define ROGUE_CR_OS4_SCRATCH3_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS4_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_OS4_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register group: ROGUE_CR_OS5_SCRATCH, with 2 repeats */
-+#define ROGUE_CR_OS5_SCRATCH_REPEATCOUNT 2U
-+/* Register ROGUE_CR_OS5_SCRATCH0 */
-+#define ROGUE_CR_OS5_SCRATCH0 0x51A80U
-+#define ROGUE_CR_OS5_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS5_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_OS5_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS5_SCRATCH1 */
-+#define ROGUE_CR_OS5_SCRATCH1 0x51A88U
-+#define ROGUE_CR_OS5_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS5_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_OS5_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS5_SCRATCH2 */
-+#define ROGUE_CR_OS5_SCRATCH2 0x51A90U
-+#define ROGUE_CR_OS5_SCRATCH2_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS5_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_OS5_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_OS5_SCRATCH3 */
-+#define ROGUE_CR_OS5_SCRATCH3 0x51A98U
-+#define ROGUE_CR_OS5_SCRATCH3_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS5_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_OS5_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register group: ROGUE_CR_OS6_SCRATCH, with 2 repeats */
-+#define ROGUE_CR_OS6_SCRATCH_REPEATCOUNT 2U
-+/* Register ROGUE_CR_OS6_SCRATCH0 */
-+#define ROGUE_CR_OS6_SCRATCH0 0x61A80U
-+#define ROGUE_CR_OS6_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS6_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_OS6_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS6_SCRATCH1 */
-+#define ROGUE_CR_OS6_SCRATCH1 0x61A88U
-+#define ROGUE_CR_OS6_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS6_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_OS6_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS6_SCRATCH2 */
-+#define ROGUE_CR_OS6_SCRATCH2 0x61A90U
-+#define ROGUE_CR_OS6_SCRATCH2_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS6_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_OS6_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_OS6_SCRATCH3 */
-+#define ROGUE_CR_OS6_SCRATCH3 0x61A98U
-+#define ROGUE_CR_OS6_SCRATCH3_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS6_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_OS6_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register group: ROGUE_CR_OS7_SCRATCH, with 2 repeats */
-+#define ROGUE_CR_OS7_SCRATCH_REPEATCOUNT 2U
-+/* Register ROGUE_CR_OS7_SCRATCH0 */
-+#define ROGUE_CR_OS7_SCRATCH0 0x71A80U
-+#define ROGUE_CR_OS7_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS7_SCRATCH0_DATA_SHIFT 0U
-+#define ROGUE_CR_OS7_SCRATCH0_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS7_SCRATCH1 */
-+#define ROGUE_CR_OS7_SCRATCH1 0x71A88U
-+#define ROGUE_CR_OS7_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_OS7_SCRATCH1_DATA_SHIFT 0U
-+#define ROGUE_CR_OS7_SCRATCH1_DATA_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OS7_SCRATCH2 */
-+#define ROGUE_CR_OS7_SCRATCH2 0x71A90U
-+#define ROGUE_CR_OS7_SCRATCH2_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS7_SCRATCH2_DATA_SHIFT 0U
-+#define ROGUE_CR_OS7_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_OS7_SCRATCH3 */
-+#define ROGUE_CR_OS7_SCRATCH3 0x71A98U
-+#define ROGUE_CR_OS7_SCRATCH3_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_OS7_SCRATCH3_DATA_SHIFT 0U
-+#define ROGUE_CR_OS7_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_SPFILTER_SIGNAL_DESCR */
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR 0x2700U
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_SHIFT 0U
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_CLRMSK 0xFFFF0000U
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSHIFT 4U
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN */
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN 0x2708U
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_MASKFULL 0x000000FFFFFFFFF0ULL
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_SHIFT 4U
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_CLRMSK 0xFFFFFF000000000FULL
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSHIFT 4U
-+#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSIZE 16U
-+
-+/* Register group: ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG, with 16 repeats */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEATCOUNT 16U
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 0x3000U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 0x3008U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 0x3010U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 0x3018U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 0x3020U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 0x3028U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 0x3030U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 0x3038U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 0x3040U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 0x3048U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 0x3050U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 0x3058U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 0x3060U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 0x3068U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 0x3070U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 */
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 0x3078U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_MASKFULL 0x7FFFF7FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_SHIFT 62U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_EN 0x4000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_SHIFT 61U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_EN 0x2000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_SHIFT 60U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_EN 0x1000000000000000ULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_SHIFT 44U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_SHIFT 40U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_BOOT */
-+#define ROGUE_CR_FWCORE_BOOT 0x3090U
-+#define ROGUE_CR_FWCORE_BOOT_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_FWCORE_BOOT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_FWCORE_BOOT_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_FWCORE_BOOT_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_FWCORE_RESET_ADDR */
-+#define ROGUE_CR_FWCORE_RESET_ADDR 0x3098U
-+#define ROGUE_CR_FWCORE_RESET_ADDR_MASKFULL 0x00000000FFFFFFFEULL
-+#define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_SHIFT 1U
-+#define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_CLRMSK 0x00000001U
-+#define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSHIFT 1U
-+#define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSIZE 2U
-+
-+/* Register ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR */
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR 0x30A0U
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_MASKFULL 0x00000000FFFFFFFEULL
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_SHIFT 1U
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_CLRMSK 0x00000001U
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSHIFT 1U
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSIZE 2U
-+
-+/* Register ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT */
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT 0x30A8U
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_SHIFT 0U
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_EN 0x00000001U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS */
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS 0x30B0U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_MASKFULL 0x000000000000F771ULL
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_SHIFT 8U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_SHIFT 5U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_SHIFT 4U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_EN 0x00000010U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_SHIFT 0U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS */
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS 0x30B8U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_MASKFULL 0x001FFFFFFFFFFFF0ULL
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_SHIFT 52U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_CLRMSK 0xFFEFFFFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_EN 0x0010000000000000ULL
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_SHIFT 46U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_CLRMSK 0xFFF03FFFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_SHIFT 40U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFC0FFFFFFFFFFULL
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_SHIFT 4U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
-+#define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_CTRL_INVAL */
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL 0x30C0U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_SHIFT 3U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_EN 0x00000008U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_SHIFT 2U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_EN 0x00000004U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_SHIFT 1U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_EN 0x00000002U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_SHIFT 0U
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_MMU_STATUS */
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS 0x30C8U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_MASKFULL 0x000000000FFFFFF7ULL
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_SHIFT 20U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_SHIFT 4U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_SHIFT 2U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_EN 0x00000004U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_SHIFT 1U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_EN 0x00000002U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_SHIFT 0U
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_EN 0x00000001U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS */
-+#define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS 0x30D8U
-+#define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MASKFULL 0x0000000000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_SHIFT 0U
-+#define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_CLRMSK 0xFFFFF000U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_READS_INT_STATUS */
-+#define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS 0x30E0U
-+#define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MASKFULL 0x00000000000007FFULL
-+#define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_SHIFT 0U
-+#define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_CLRMSK 0xFFFFF800U
-+
-+/* Register ROGUE_CR_FWCORE_WRAPPER_FENCE */
-+#define ROGUE_CR_FWCORE_WRAPPER_FENCE 0x30E8U
-+#define ROGUE_CR_FWCORE_WRAPPER_FENCE_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_SHIFT 0U
-+#define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_EN 0x00000001U
-+
-+/* Register group: ROGUE_CR_FWCORE_MEM_CAT_BASE, with 8 repeats */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEATCOUNT 8U
-+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE0 */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE0 0x30F0U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE1 */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE1 0x30F8U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE2 */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE2 0x3100U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE3 */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE3 0x3108U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE4 */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE4 0x3110U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE5 */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE5 0x3118U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE6 */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE6 0x3120U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE7 */
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE7 0x3128U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_SHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_FWCORE_WDT_RESET */
-+#define ROGUE_CR_FWCORE_WDT_RESET 0x3130U
-+#define ROGUE_CR_FWCORE_WDT_RESET_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_FWCORE_WDT_RESET_EN_SHIFT 0U
-+#define ROGUE_CR_FWCORE_WDT_RESET_EN_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_FWCORE_WDT_RESET_EN_EN 0x00000001U
-+
-+/* Register ROGUE_CR_FWCORE_WDT_CTRL */
-+#define ROGUE_CR_FWCORE_WDT_CTRL 0x3138U
-+#define ROGUE_CR_FWCORE_WDT_CTRL_MASKFULL 0x00000000FFFF1F01ULL
-+#define ROGUE_CR_FWCORE_WDT_CTRL_PROT_SHIFT 16U
-+#define ROGUE_CR_FWCORE_WDT_CTRL_PROT_CLRMSK 0x0000FFFFU
-+#define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_SHIFT 8U
-+#define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_CLRMSK 0xFFFFE0FFU
-+#define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_FWCORE_WDT_COUNT */
-+#define ROGUE_CR_FWCORE_WDT_COUNT 0x3140U
-+#define ROGUE_CR_FWCORE_WDT_COUNT_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_SHIFT 0U
-+#define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_CLRMSK 0x00000000U
-+
-+/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED0, with 4 repeats */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEATCOUNT 4U
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED00 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED00 0x3400U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED00_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED01 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED01 0x3408U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED01_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED02 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED02 0x3410U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED02_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED03 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED03 0x3418U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED03_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_DATA0 */
-+#define ROGUE_CR_FWCORE_DMI_DATA0 0x3420U
-+#define ROGUE_CR_FWCORE_DMI_DATA0_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_DATA1 */
-+#define ROGUE_CR_FWCORE_DMI_DATA1 0x3428U
-+#define ROGUE_CR_FWCORE_DMI_DATA1_MASKFULL 0x0000000000000000ULL
-+
-+/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED1, with 5 repeats */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEATCOUNT 5U
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED10 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED10 0x3430U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED10_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED11 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED11 0x3438U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED11_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED12 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED12 0x3440U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED12_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED13 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED13 0x3448U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED13_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED14 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED14 0x3450U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED14_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_DMCONTROL */
-+#define ROGUE_CR_FWCORE_DMI_DMCONTROL 0x3480U
-+#define ROGUE_CR_FWCORE_DMI_DMCONTROL_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_DMSTATUS */
-+#define ROGUE_CR_FWCORE_DMI_DMSTATUS 0x3488U
-+#define ROGUE_CR_FWCORE_DMI_DMSTATUS_MASKFULL 0x0000000000000000ULL
-+
-+/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED2, with 4 repeats */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEATCOUNT 4U
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED20 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED20 0x3490U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED20_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED21 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED21 0x3498U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED21_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED22 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED22 0x34A0U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED22_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED23 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED23 0x34A8U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED23_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_ABSTRACTCS */
-+#define ROGUE_CR_FWCORE_DMI_ABSTRACTCS 0x34B0U
-+#define ROGUE_CR_FWCORE_DMI_ABSTRACTCS_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_COMMAND */
-+#define ROGUE_CR_FWCORE_DMI_COMMAND 0x34B8U
-+#define ROGUE_CR_FWCORE_DMI_COMMAND_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_SBCS */
-+#define ROGUE_CR_FWCORE_DMI_SBCS 0x35C0U
-+#define ROGUE_CR_FWCORE_DMI_SBCS_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_SBADDRESS0 */
-+#define ROGUE_CR_FWCORE_DMI_SBADDRESS0 0x35C8U
-+#define ROGUE_CR_FWCORE_DMI_SBADDRESS0_MASKFULL 0x0000000000000000ULL
-+
-+/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED3, with 2 repeats */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEATCOUNT 2U
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED30 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED30 0x34D0U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED30_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_RESERVED31 */
-+#define ROGUE_CR_FWCORE_DMI_RESERVED31 0x34D8U
-+#define ROGUE_CR_FWCORE_DMI_RESERVED31_MASKFULL 0x0000000000000000ULL
-+
-+/* Register group: ROGUE_CR_FWCORE_DMI_SBDATA, with 4 repeats */
-+#define ROGUE_CR_FWCORE_DMI_SBDATA_REPEATCOUNT 4U
-+/* Register ROGUE_CR_FWCORE_DMI_SBDATA0 */
-+#define ROGUE_CR_FWCORE_DMI_SBDATA0 0x35E0U
-+#define ROGUE_CR_FWCORE_DMI_SBDATA0_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_SBDATA1 */
-+#define ROGUE_CR_FWCORE_DMI_SBDATA1 0x35E8U
-+#define ROGUE_CR_FWCORE_DMI_SBDATA1_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_SBDATA2 */
-+#define ROGUE_CR_FWCORE_DMI_SBDATA2 0x35F0U
-+#define ROGUE_CR_FWCORE_DMI_SBDATA2_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_SBDATA3 */
-+#define ROGUE_CR_FWCORE_DMI_SBDATA3 0x35F8U
-+#define ROGUE_CR_FWCORE_DMI_SBDATA3_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_FWCORE_DMI_HALTSUM0 */
-+#define ROGUE_CR_FWCORE_DMI_HALTSUM0 0x3600U
-+#define ROGUE_CR_FWCORE_DMI_HALTSUM0_MASKFULL 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_SLC_CTRL_MISC */
-+#define ROGUE_CR_SLC_CTRL_MISC 0x3800U
-+#define ROGUE_CR_SLC_CTRL_MISC_MASKFULL 0xFFFFFFFF01FF010FULL
-+#define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_SHIFT 32U
-+#define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_CLRMSK 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_SHIFT 24U
-+#define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_CLRMSK 0xFFFFFFFFFEFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_EN 0x0000000001000000ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 16U
-+#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_CLRMSK 0xFFFFFFFFFF00FFFFULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_INTERLEAVED_64_BYTE 0x0000000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_INTERLEAVED_128_BYTE 0x0000000000010000ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SIMPLE_HASH1 0x0000000000100000ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SIMPLE_HASH2 0x0000000000110000ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH1 0x0000000000200000ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH2_SCRAMBLE 0x0000000000210000ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_PAUSE_SHIFT 8U
-+#define ROGUE_CR_SLC_CTRL_MISC_PAUSE_CLRMSK 0xFFFFFFFFFFFFFEFFULL
-+#define ROGUE_CR_SLC_CTRL_MISC_PAUSE_EN 0x0000000000000100ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_SHIFT 3U
-+#define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_EN 0x0000000000000008ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_SHIFT 2U
-+#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_CLRMSK 0xFFFFFFFFFFFFFFFBULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_EN 0x0000000000000004ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_SHIFT 1U
-+#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_EN 0x0000000000000002ULL
-+#define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_SHIFT 0U
-+#define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_SLC_CTRL_FLUSH_INVAL */
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL 0x3818U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_MASKFULL 0x0000000080000FFFULL
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_SHIFT 31U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_CLRMSK 0x7FFFFFFFU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_EN 0x80000000U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_SHIFT 11U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_CLRMSK 0xFFFFF7FFU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_EN 0x00000800U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_SHIFT 10U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_CLRMSK 0xFFFFFBFFU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_EN 0x00000400U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_SHIFT 9U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_CLRMSK 0xFFFFFDFFU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_EN 0x00000200U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_SHIFT 8U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_EN 0x00000100U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_SHIFT 7U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_CLRMSK 0xFFFFFF7FU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_EN 0x00000080U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_SHIFT 6U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_EN 0x00000040U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_SHIFT 5U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_EN 0x00000020U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_SHIFT 4U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_EN 0x00000010U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_SHIFT 3U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_EN 0x00000008U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_SHIFT 2U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_EN 0x00000004U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_SHIFT 1U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_EN 0x00000002U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_SHIFT 0U
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SLC_STATUS0 */
-+#define ROGUE_CR_SLC_STATUS0 0x3820U
-+#define ROGUE_CR_SLC_STATUS0_MASKFULL 0x0000000000000007ULL
-+#define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_SHIFT 2U
-+#define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_EN 0x00000004U
-+#define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_SHIFT 1U
-+#define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_EN 0x00000002U
-+#define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_SHIFT 0U
-+#define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SLC_CTRL_BYPASS */
-+#define ROGUE_CR_SLC_CTRL_BYPASS 0x3828U
-+#define ROGUE_CR_SLC_CTRL_BYPASS__XE_MEM__MASKFULL 0x0FFFFFFFFFFF7FFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_MASKFULL 0x000000000FFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_SHIFT 59U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_CLRMSK 0xF7FFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_EN 0x0800000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_SHIFT 58U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_CLRMSK 0xFBFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_EN 0x0400000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_SHIFT 57U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_CLRMSK 0xFDFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_EN 0x0200000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_SHIFT 56U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_CLRMSK 0xFEFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_EN 0x0100000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_SHIFT 55U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_CLRMSK 0xFF7FFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_EN 0x0080000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_SHIFT 54U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_CLRMSK 0xFFBFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_EN 0x0040000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_SHIFT 53U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_CLRMSK 0xFFDFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_EN 0x0020000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_SHIFT 52U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_CLRMSK 0xFFEFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_EN 0x0010000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_SHIFT 51U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_CLRMSK 0xFFF7FFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_EN 0x0008000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_SHIFT 50U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_CLRMSK 0xFFFBFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_EN 0x0004000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_SHIFT 49U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_CLRMSK 0xFFFDFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_EN 0x0002000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_SHIFT 48U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_CLRMSK 0xFFFEFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_EN 0x0001000000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_SHIFT 47U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_CLRMSK 0xFFFF7FFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_EN 0x0000800000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_SHIFT 46U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_CLRMSK 0xFFFFBFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_EN 0x0000400000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_SHIFT 45U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_CLRMSK 0xFFFFDFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_EN 0x0000200000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_SHIFT 44U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_CLRMSK 0xFFFFEFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_EN 0x0000100000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_SHIFT 43U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_CLRMSK 0xFFFFF7FFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_EN 0x0000080000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_SHIFT 42U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_CLRMSK 0xFFFFFBFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_EN 0x0000040000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_SHIFT 41U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_CLRMSK 0xFFFFFDFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_EN 0x0000020000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_SHIFT 40U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_CLRMSK 0xFFFFFEFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_EN 0x0000010000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_SHIFT 39U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_CLRMSK 0xFFFFFF7FFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_EN 0x0000008000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_SHIFT 38U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_CLRMSK 0xFFFFFFBFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_EN 0x0000004000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_SHIFT 37U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_CLRMSK 0xFFFFFFDFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_EN 0x0000002000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_SHIFT 36U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_CLRMSK 0xFFFFFFEFFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_EN 0x0000001000000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_SHIFT 35U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_CLRMSK 0xFFFFFFF7FFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_EN 0x0000000800000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_SHIFT 34U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_CLRMSK 0xFFFFFFFBFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_EN 0x0000000400000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_SHIFT 33U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_CLRMSK 0xFFFFFFFDFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_EN 0x0000000200000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_SHIFT 32U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_CLRMSK 0xFFFFFFFEFFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_EN 0x0000000100000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_SHIFT 31U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_CLRMSK 0xFFFFFFFF7FFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_EN 0x0000000080000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_SHIFT 30U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_CLRMSK 0xFFFFFFFFBFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_EN 0x0000000040000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_SHIFT 29U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_CLRMSK 0xFFFFFFFFDFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_EN 0x0000000020000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_SHIFT 28U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_CLRMSK 0xFFFFFFFFEFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_EN 0x0000000010000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_SHIFT 27U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_CLRMSK 0xFFFFFFFFF7FFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_EN 0x0000000008000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_SHIFT 26U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_CLRMSK 0xFFFFFFFFFBFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_EN 0x0000000004000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_SHIFT 25U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_CLRMSK 0xFFFFFFFFFDFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_EN 0x0000000002000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_SHIFT 24U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_CLRMSK 0xFFFFFFFFFEFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_EN 0x0000000001000000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_SHIFT 23U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_CLRMSK 0xFFFFFFFFFF7FFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_EN 0x0000000000800000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_SHIFT 22U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_CLRMSK 0xFFFFFFFFFFBFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_EN 0x0000000000400000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_SHIFT 21U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_EN 0x0000000000200000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_SHIFT 20U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_CLRMSK 0xFFFFFFFFFFEFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_EN 0x0000000000100000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_SHIFT 19U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_CLRMSK 0xFFFFFFFFFFF7FFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_EN 0x0000000000080000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_SHIFT 18U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_CLRMSK 0xFFFFFFFFFFFBFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_EN 0x0000000000040000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_SHIFT 17U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_CLRMSK 0xFFFFFFFFFFFDFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_EN 0x0000000000020000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_SHIFT 16U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_CLRMSK 0xFFFFFFFFFFFEFFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_EN 0x0000000000010000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SHIFT 15U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_CLRMSK 0xFFFFFFFFFFFF7FFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_EN 0x0000000000008000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_SHIFT 14U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_CLRMSK 0xFFFFFFFFFFFFBFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_EN 0x0000000000004000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_SHIFT 13U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_CLRMSK 0xFFFFFFFFFFFFDFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_EN 0x0000000000002000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_SHIFT 12U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_CLRMSK 0xFFFFFFFFFFFFEFFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_EN 0x0000000000001000ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_SHIFT 11U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_CLRMSK 0xFFFFFFFFFFFFF7FFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_EN 0x0000000000000800ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_SHIFT 10U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_CLRMSK 0xFFFFFFFFFFFFFBFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_EN 0x0000000000000400ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_SHIFT 9U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_CLRMSK 0xFFFFFFFFFFFFFDFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_EN 0x0000000000000200ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_SHIFT 8U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_CLRMSK 0xFFFFFFFFFFFFFEFFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_EN 0x0000000000000100ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_SHIFT 7U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_CLRMSK 0xFFFFFFFFFFFFFF7FULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_EN 0x0000000000000080ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_SHIFT 6U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_CLRMSK 0xFFFFFFFFFFFFFFBFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_EN 0x0000000000000040ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_SHIFT 5U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_EN 0x0000000000000020ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_SHIFT 4U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_CLRMSK 0xFFFFFFFFFFFFFFEFULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_EN 0x0000000000000010ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_SHIFT 3U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_EN 0x0000000000000008ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_SHIFT 2U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_CLRMSK 0xFFFFFFFFFFFFFFFBULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_EN 0x0000000000000004ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_SHIFT 1U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_EN 0x0000000000000002ULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_ALL_SHIFT 0U
-+#define ROGUE_CR_SLC_CTRL_BYPASS_ALL_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_SLC_CTRL_BYPASS_ALL_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_SLC_STATUS1 */
-+#define ROGUE_CR_SLC_STATUS1 0x3870U
-+#define ROGUE_CR_SLC_STATUS1_MASKFULL 0x800003FF03FFFFFFULL
-+#define ROGUE_CR_SLC_STATUS1_PAUSED_SHIFT 63U
-+#define ROGUE_CR_SLC_STATUS1_PAUSED_CLRMSK 0x7FFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC_STATUS1_PAUSED_EN 0x8000000000000000ULL
-+#define ROGUE_CR_SLC_STATUS1_READS1_SHIFT 32U
-+#define ROGUE_CR_SLC_STATUS1_READS1_CLRMSK 0xFFFFFC00FFFFFFFFULL
-+#define ROGUE_CR_SLC_STATUS1_READS0_SHIFT 16U
-+#define ROGUE_CR_SLC_STATUS1_READS0_CLRMSK 0xFFFFFFFFFC00FFFFULL
-+#define ROGUE_CR_SLC_STATUS1_READS1_EXT_SHIFT 8U
-+#define ROGUE_CR_SLC_STATUS1_READS1_EXT_CLRMSK 0xFFFFFFFFFFFF00FFULL
-+#define ROGUE_CR_SLC_STATUS1_READS0_EXT_SHIFT 0U
-+#define ROGUE_CR_SLC_STATUS1_READS0_EXT_CLRMSK 0xFFFFFFFFFFFFFF00ULL
-+
-+/* Register ROGUE_CR_SLC_IDLE */
-+#define ROGUE_CR_SLC_IDLE 0x3898U
-+#define ROGUE_CR_SLC_IDLE__XE_MEM__MASKFULL 0x00000000000003FFULL
-+#define ROGUE_CR_SLC_IDLE_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_SLC_IDLE_MH_SYSARB1_SHIFT 9U
-+#define ROGUE_CR_SLC_IDLE_MH_SYSARB1_CLRMSK 0xFFFFFDFFU
-+#define ROGUE_CR_SLC_IDLE_MH_SYSARB1_EN 0x00000200U
-+#define ROGUE_CR_SLC_IDLE_MH_SYSARB0_SHIFT 8U
-+#define ROGUE_CR_SLC_IDLE_MH_SYSARB0_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_SLC_IDLE_MH_SYSARB0_EN 0x00000100U
-+#define ROGUE_CR_SLC_IDLE_IMGBV4_SHIFT 7U
-+#define ROGUE_CR_SLC_IDLE_IMGBV4_CLRMSK 0xFFFFFF7FU
-+#define ROGUE_CR_SLC_IDLE_IMGBV4_EN 0x00000080U
-+#define ROGUE_CR_SLC_IDLE_CACHE_BANKS_SHIFT 6U
-+#define ROGUE_CR_SLC_IDLE_CACHE_BANKS_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_SLC_IDLE_CACHE_BANKS_EN 0x00000040U
-+#define ROGUE_CR_SLC_IDLE_RBOFIFO_SHIFT 5U
-+#define ROGUE_CR_SLC_IDLE_RBOFIFO_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_SLC_IDLE_RBOFIFO_EN 0x00000020U
-+#define ROGUE_CR_SLC_IDLE_FRC_CONV_SHIFT 4U
-+#define ROGUE_CR_SLC_IDLE_FRC_CONV_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_SLC_IDLE_FRC_CONV_EN 0x00000010U
-+#define ROGUE_CR_SLC_IDLE_VXE_CONV_SHIFT 3U
-+#define ROGUE_CR_SLC_IDLE_VXE_CONV_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_SLC_IDLE_VXE_CONV_EN 0x00000008U
-+#define ROGUE_CR_SLC_IDLE_VXD_CONV_SHIFT 2U
-+#define ROGUE_CR_SLC_IDLE_VXD_CONV_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SLC_IDLE_VXD_CONV_EN 0x00000004U
-+#define ROGUE_CR_SLC_IDLE_BIF1_CONV_SHIFT 1U
-+#define ROGUE_CR_SLC_IDLE_BIF1_CONV_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SLC_IDLE_BIF1_CONV_EN 0x00000002U
-+#define ROGUE_CR_SLC_IDLE_CBAR_SHIFT 0U
-+#define ROGUE_CR_SLC_IDLE_CBAR_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SLC_IDLE_CBAR_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SLC_STATUS2 */
-+#define ROGUE_CR_SLC_STATUS2 0x3908U
-+#define ROGUE_CR_SLC_STATUS2_MASKFULL 0x000003FF03FFFFFFULL
-+#define ROGUE_CR_SLC_STATUS2_READS3_SHIFT 32U
-+#define ROGUE_CR_SLC_STATUS2_READS3_CLRMSK 0xFFFFFC00FFFFFFFFULL
-+#define ROGUE_CR_SLC_STATUS2_READS2_SHIFT 16U
-+#define ROGUE_CR_SLC_STATUS2_READS2_CLRMSK 0xFFFFFFFFFC00FFFFULL
-+#define ROGUE_CR_SLC_STATUS2_READS3_EXT_SHIFT 8U
-+#define ROGUE_CR_SLC_STATUS2_READS3_EXT_CLRMSK 0xFFFFFFFFFFFF00FFULL
-+#define ROGUE_CR_SLC_STATUS2_READS2_EXT_SHIFT 0U
-+#define ROGUE_CR_SLC_STATUS2_READS2_EXT_CLRMSK 0xFFFFFFFFFFFFFF00ULL
-+
-+/* Register ROGUE_CR_SLC_CTRL_MISC2 */
-+#define ROGUE_CR_SLC_CTRL_MISC2 0x3930U
-+#define ROGUE_CR_SLC_CTRL_MISC2_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_SHIFT 0U
-+#define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE */
-+#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE 0x3938U
-+#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_SHIFT 0U
-+#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_EN 0x00000001U
-+
-+/* Register ROGUE_CR_USC_UVS0_CHECKSUM */
-+#define ROGUE_CR_USC_UVS0_CHECKSUM 0x5000U
-+#define ROGUE_CR_USC_UVS0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_USC_UVS1_CHECKSUM */
-+#define ROGUE_CR_USC_UVS1_CHECKSUM 0x5008U
-+#define ROGUE_CR_USC_UVS1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_USC_UVS2_CHECKSUM */
-+#define ROGUE_CR_USC_UVS2_CHECKSUM 0x5010U
-+#define ROGUE_CR_USC_UVS2_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_USC_UVS3_CHECKSUM */
-+#define ROGUE_CR_USC_UVS3_CHECKSUM 0x5018U
-+#define ROGUE_CR_USC_UVS3_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PPP_SIGNATURE */
-+#define ROGUE_CR_PPP_SIGNATURE 0x5020U
-+#define ROGUE_CR_PPP_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PPP_SIGNATURE_VALUE_SHIFT 0U
-+#define ROGUE_CR_PPP_SIGNATURE_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TE_SIGNATURE */
-+#define ROGUE_CR_TE_SIGNATURE 0x5028U
-+#define ROGUE_CR_TE_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TE_SIGNATURE_VALUE_SHIFT 0U
-+#define ROGUE_CR_TE_SIGNATURE_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TE_CHECKSUM */
-+#define ROGUE_CR_TE_CHECKSUM 0x5110U
-+#define ROGUE_CR_TE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TE_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_TE_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_USC_UVB_CHECKSUM */
-+#define ROGUE_CR_USC_UVB_CHECKSUM 0x5118U
-+#define ROGUE_CR_USC_UVB_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_VCE_CHECKSUM */
-+#define ROGUE_CR_VCE_CHECKSUM 0x5030U
-+#define ROGUE_CR_VCE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_VCE_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_VCE_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_ISP_PDS_CHECKSUM */
-+#define ROGUE_CR_ISP_PDS_CHECKSUM 0x5038U
-+#define ROGUE_CR_ISP_PDS_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_ISP_TPF_CHECKSUM */
-+#define ROGUE_CR_ISP_TPF_CHECKSUM 0x5040U
-+#define ROGUE_CR_ISP_TPF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TFPU_PLANE0_CHECKSUM */
-+#define ROGUE_CR_TFPU_PLANE0_CHECKSUM 0x5048U
-+#define ROGUE_CR_TFPU_PLANE0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TFPU_PLANE1_CHECKSUM */
-+#define ROGUE_CR_TFPU_PLANE1_CHECKSUM 0x5050U
-+#define ROGUE_CR_TFPU_PLANE1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PBE_CHECKSUM */
-+#define ROGUE_CR_PBE_CHECKSUM 0x5058U
-+#define ROGUE_CR_PBE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PBE_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_PBE_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PDS_DOUTM_STM_SIGNATURE */
-+#define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE 0x5060U
-+#define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_SHIFT 0U
-+#define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_IFPU_ISP_CHECKSUM */
-+#define ROGUE_CR_IFPU_ISP_CHECKSUM 0x5068U
-+#define ROGUE_CR_IFPU_ISP_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_USC_UVS4_CHECKSUM */
-+#define ROGUE_CR_USC_UVS4_CHECKSUM 0x5100U
-+#define ROGUE_CR_USC_UVS4_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_USC_UVS5_CHECKSUM */
-+#define ROGUE_CR_USC_UVS5_CHECKSUM 0x5108U
-+#define ROGUE_CR_USC_UVS5_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PPP_CLIP_CHECKSUM */
-+#define ROGUE_CR_PPP_CLIP_CHECKSUM 0x5120U
-+#define ROGUE_CR_PPP_CLIP_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_TA_PHASE */
-+#define ROGUE_CR_PERF_TA_PHASE 0x6008U
-+#define ROGUE_CR_PERF_TA_PHASE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_TA_PHASE_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_TA_PHASE_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_3D_PHASE */
-+#define ROGUE_CR_PERF_3D_PHASE 0x6010U
-+#define ROGUE_CR_PERF_3D_PHASE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_3D_PHASE_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_3D_PHASE_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_COMPUTE_PHASE */
-+#define ROGUE_CR_PERF_COMPUTE_PHASE 0x6018U
-+#define ROGUE_CR_PERF_COMPUTE_PHASE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_TA_CYCLE */
-+#define ROGUE_CR_PERF_TA_CYCLE 0x6020U
-+#define ROGUE_CR_PERF_TA_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_TA_CYCLE_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_TA_CYCLE_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_3D_CYCLE */
-+#define ROGUE_CR_PERF_3D_CYCLE 0x6028U
-+#define ROGUE_CR_PERF_3D_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_3D_CYCLE_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_3D_CYCLE_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_COMPUTE_CYCLE */
-+#define ROGUE_CR_PERF_COMPUTE_CYCLE 0x6030U
-+#define ROGUE_CR_PERF_COMPUTE_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_TA_OR_3D_CYCLE */
-+#define ROGUE_CR_PERF_TA_OR_3D_CYCLE 0x6038U
-+#define ROGUE_CR_PERF_TA_OR_3D_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_INITIAL_TA_CYCLE */
-+#define ROGUE_CR_PERF_INITIAL_TA_CYCLE 0x6040U
-+#define ROGUE_CR_PERF_INITIAL_TA_CYCLE_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_SLC0_READ_STALL */
-+#define ROGUE_CR_PERF_SLC0_READ_STALL 0x60B8U
-+#define ROGUE_CR_PERF_SLC0_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_SLC0_WRITE_STALL */
-+#define ROGUE_CR_PERF_SLC0_WRITE_STALL 0x60C0U
-+#define ROGUE_CR_PERF_SLC0_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_SLC1_READ_STALL */
-+#define ROGUE_CR_PERF_SLC1_READ_STALL 0x60E0U
-+#define ROGUE_CR_PERF_SLC1_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_SLC1_WRITE_STALL */
-+#define ROGUE_CR_PERF_SLC1_WRITE_STALL 0x60E8U
-+#define ROGUE_CR_PERF_SLC1_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_SLC2_READ_STALL */
-+#define ROGUE_CR_PERF_SLC2_READ_STALL 0x6158U
-+#define ROGUE_CR_PERF_SLC2_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_SLC2_WRITE_STALL */
-+#define ROGUE_CR_PERF_SLC2_WRITE_STALL 0x6160U
-+#define ROGUE_CR_PERF_SLC2_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_SLC3_READ_STALL */
-+#define ROGUE_CR_PERF_SLC3_READ_STALL 0x6180U
-+#define ROGUE_CR_PERF_SLC3_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_SLC3_WRITE_STALL */
-+#define ROGUE_CR_PERF_SLC3_WRITE_STALL 0x6188U
-+#define ROGUE_CR_PERF_SLC3_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_SHIFT 0U
-+#define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PERF_3D_SPINUP */
-+#define ROGUE_CR_PERF_3D_SPINUP 0x6220U
-+#define ROGUE_CR_PERF_3D_SPINUP_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PERF_3D_SPINUP_CYCLES_SHIFT 0U
-+#define ROGUE_CR_PERF_3D_SPINUP_CYCLES_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_AXI_ACE_LITE_CONFIGURATION */
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION 0x38C0U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_MASKFULL 0x00003FFFFFFFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_SHIFT 45U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_CLRMSK 0xFFFFDFFFFFFFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_EN 0x0000200000000000ULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_SHIFT 37U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_CLRMSK 0xFFFFE01FFFFFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_SHIFT 36U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_CLRMSK 0xFFFFFFEFFFFFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_EN 0x0000001000000000ULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_SHIFT 35U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_CLRMSK 0xFFFFFFF7FFFFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_EN 0x0000000800000000ULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_SHIFT 34U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_CLRMSK 0xFFFFFFFBFFFFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_EN 0x0000000400000000ULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_SHIFT 30U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_CLRMSK 0xFFFFFFFC3FFFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_SHIFT 26U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_CLRMSK 0xFFFFFFFFC3FFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_SHIFT 22U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_CLRMSK 0xFFFFFFFFFC3FFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_SHIFT 20U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_CLRMSK 0xFFFFFFFFFFCFFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_SHIFT 18U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_CLRMSK 0xFFFFFFFFFFF3FFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_SHIFT 16U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_CLRMSK 0xFFFFFFFFFFFCFFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_SHIFT 14U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_CLRMSK 0xFFFFFFFFFFFF3FFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_SHIFT 12U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_CLRMSK 0xFFFFFFFFFFFFCFFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_SHIFT 10U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFF3FFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_SHIFT 8U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFCFFULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_SHIFT 4U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFF0FULL
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_SHIFT 0U
-+#define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFFF0ULL
-+
-+/* Register ROGUE_CR_POWER_ESTIMATE_RESULT */
-+#define ROGUE_CR_POWER_ESTIMATE_RESULT 0x6328U
-+#define ROGUE_CR_POWER_ESTIMATE_RESULT_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_SHIFT 0U
-+#define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TA_PERF */
-+#define ROGUE_CR_TA_PERF 0x7600U
-+#define ROGUE_CR_TA_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_TA_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_TA_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_TA_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_TA_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_TA_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_TA_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_TA_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_TA_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_TA_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_TA_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_TA_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_TA_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_TA_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_TA_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_TA_PERF_SELECT0 */
-+#define ROGUE_CR_TA_PERF_SELECT0 0x7608U
-+#define ROGUE_CR_TA_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_TA_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_TA_PERF_SELECT1 */
-+#define ROGUE_CR_TA_PERF_SELECT1 0x7610U
-+#define ROGUE_CR_TA_PERF_SELECT1_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT1_MODE_SHIFT 21U
-+#define ROGUE_CR_TA_PERF_SELECT1_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT1_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_TA_PERF_SELECT2 */
-+#define ROGUE_CR_TA_PERF_SELECT2 0x7618U
-+#define ROGUE_CR_TA_PERF_SELECT2_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT2_MODE_SHIFT 21U
-+#define ROGUE_CR_TA_PERF_SELECT2_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT2_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_TA_PERF_SELECT3 */
-+#define ROGUE_CR_TA_PERF_SELECT3 0x7620U
-+#define ROGUE_CR_TA_PERF_SELECT3_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT3_MODE_SHIFT 21U
-+#define ROGUE_CR_TA_PERF_SELECT3_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT3_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_TA_PERF_SELECTED_BITS */
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS 0x7648U
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_SHIFT 48U
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_CLRMSK 0x0000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_SHIFT 32U
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_CLRMSK 0xFFFF0000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_SHIFT 16U
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_CLRMSK 0xFFFFFFFF0000FFFFULL
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_TA_PERF_COUNTER_0 */
-+#define ROGUE_CR_TA_PERF_COUNTER_0 0x7650U
-+#define ROGUE_CR_TA_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TA_PERF_COUNTER_1 */
-+#define ROGUE_CR_TA_PERF_COUNTER_1 0x7658U
-+#define ROGUE_CR_TA_PERF_COUNTER_1_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_COUNTER_1_REG_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_COUNTER_1_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TA_PERF_COUNTER_2 */
-+#define ROGUE_CR_TA_PERF_COUNTER_2 0x7660U
-+#define ROGUE_CR_TA_PERF_COUNTER_2_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_COUNTER_2_REG_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_COUNTER_2_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TA_PERF_COUNTER_3 */
-+#define ROGUE_CR_TA_PERF_COUNTER_3 0x7668U
-+#define ROGUE_CR_TA_PERF_COUNTER_3_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TA_PERF_COUNTER_3_REG_SHIFT 0U
-+#define ROGUE_CR_TA_PERF_COUNTER_3_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_RASTERISATION_PERF */
-+#define ROGUE_CR_RASTERISATION_PERF 0x7700U
-+#define ROGUE_CR_RASTERISATION_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_RASTERISATION_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_RASTERISATION_PERF_SELECT0 */
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0 0x7708U
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_RASTERISATION_PERF_COUNTER_0 */
-+#define ROGUE_CR_RASTERISATION_PERF_COUNTER_0 0x7750U
-+#define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_HUB_BIFPMCACHE_PERF */
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF 0x7800U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0 */
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0 0x7808U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0 */
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0 0x7850U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TPU_MCU_L0_PERF */
-+#define ROGUE_CR_TPU_MCU_L0_PERF 0x7900U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_TPU_MCU_L0_PERF_SELECT0 */
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0 0x7908U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0 */
-+#define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0 0x7950U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_USC_PERF */
-+#define ROGUE_CR_USC_PERF 0x8100U
-+#define ROGUE_CR_USC_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_USC_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_USC_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_USC_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_USC_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_USC_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_USC_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_USC_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_USC_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_USC_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_USC_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_USC_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_USC_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_USC_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_USC_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_USC_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_USC_PERF_SELECT0 */
-+#define ROGUE_CR_USC_PERF_SELECT0 0x8108U
-+#define ROGUE_CR_USC_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_USC_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_USC_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_USC_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_USC_PERF_COUNTER_0 */
-+#define ROGUE_CR_USC_PERF_COUNTER_0 0x8150U
-+#define ROGUE_CR_USC_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_USC_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_USC_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_JONES_IDLE */
-+#define ROGUE_CR_JONES_IDLE 0x8328U
-+#define ROGUE_CR_JONES_IDLE_MASKFULL 0x0000000000007FFFULL
-+#define ROGUE_CR_JONES_IDLE_TDM_SHIFT 14U
-+#define ROGUE_CR_JONES_IDLE_TDM_CLRMSK 0xFFFFBFFFU
-+#define ROGUE_CR_JONES_IDLE_TDM_EN 0x00004000U
-+#define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_SHIFT 13U
-+#define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_CLRMSK 0xFFFFDFFFU
-+#define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_EN 0x00002000U
-+#define ROGUE_CR_JONES_IDLE_FB_CDC_SHIFT 12U
-+#define ROGUE_CR_JONES_IDLE_FB_CDC_CLRMSK 0xFFFFEFFFU
-+#define ROGUE_CR_JONES_IDLE_FB_CDC_EN 0x00001000U
-+#define ROGUE_CR_JONES_IDLE_MMU_SHIFT 11U
-+#define ROGUE_CR_JONES_IDLE_MMU_CLRMSK 0xFFFFF7FFU
-+#define ROGUE_CR_JONES_IDLE_MMU_EN 0x00000800U
-+#define ROGUE_CR_JONES_IDLE_TLA_SHIFT 10U
-+#define ROGUE_CR_JONES_IDLE_TLA_CLRMSK 0xFFFFFBFFU
-+#define ROGUE_CR_JONES_IDLE_TLA_EN 0x00000400U
-+#define ROGUE_CR_JONES_IDLE_GARTEN_SHIFT 9U
-+#define ROGUE_CR_JONES_IDLE_GARTEN_CLRMSK 0xFFFFFDFFU
-+#define ROGUE_CR_JONES_IDLE_GARTEN_EN 0x00000200U
-+#define ROGUE_CR_JONES_IDLE_HOSTIF_SHIFT 8U
-+#define ROGUE_CR_JONES_IDLE_HOSTIF_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_JONES_IDLE_HOSTIF_EN 0x00000100U
-+#define ROGUE_CR_JONES_IDLE_SOCIF_SHIFT 7U
-+#define ROGUE_CR_JONES_IDLE_SOCIF_CLRMSK 0xFFFFFF7FU
-+#define ROGUE_CR_JONES_IDLE_SOCIF_EN 0x00000080U
-+#define ROGUE_CR_JONES_IDLE_TILING_SHIFT 6U
-+#define ROGUE_CR_JONES_IDLE_TILING_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_JONES_IDLE_TILING_EN 0x00000040U
-+#define ROGUE_CR_JONES_IDLE_IPP_SHIFT 5U
-+#define ROGUE_CR_JONES_IDLE_IPP_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_JONES_IDLE_IPP_EN 0x00000020U
-+#define ROGUE_CR_JONES_IDLE_USCS_SHIFT 4U
-+#define ROGUE_CR_JONES_IDLE_USCS_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_JONES_IDLE_USCS_EN 0x00000010U
-+#define ROGUE_CR_JONES_IDLE_PM_SHIFT 3U
-+#define ROGUE_CR_JONES_IDLE_PM_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_JONES_IDLE_PM_EN 0x00000008U
-+#define ROGUE_CR_JONES_IDLE_CDM_SHIFT 2U
-+#define ROGUE_CR_JONES_IDLE_CDM_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_JONES_IDLE_CDM_EN 0x00000004U
-+#define ROGUE_CR_JONES_IDLE_VDM_SHIFT 1U
-+#define ROGUE_CR_JONES_IDLE_VDM_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_JONES_IDLE_VDM_EN 0x00000002U
-+#define ROGUE_CR_JONES_IDLE_BIF_SHIFT 0U
-+#define ROGUE_CR_JONES_IDLE_BIF_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_JONES_IDLE_BIF_EN 0x00000001U
-+
-+/* Register ROGUE_CR_TORNADO_PERF */
-+#define ROGUE_CR_TORNADO_PERF 0x8228U
-+#define ROGUE_CR_TORNADO_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_TORNADO_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_TORNADO_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_TORNADO_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_TORNADO_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_TORNADO_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_TORNADO_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_TORNADO_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_TORNADO_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_TORNADO_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_TORNADO_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_TORNADO_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_TORNADO_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_TORNADO_PERF_SELECT0 */
-+#define ROGUE_CR_TORNADO_PERF_SELECT0 0x8230U
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_TORNADO_PERF_COUNTER_0 */
-+#define ROGUE_CR_TORNADO_PERF_COUNTER_0 0x8268U
-+#define ROGUE_CR_TORNADO_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_TEXAS_PERF */
-+#define ROGUE_CR_TEXAS_PERF 0x8290U
-+#define ROGUE_CR_TEXAS_PERF_MASKFULL 0x000000000000007FULL
-+#define ROGUE_CR_TEXAS_PERF_CLR_5_SHIFT 6U
-+#define ROGUE_CR_TEXAS_PERF_CLR_5_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_TEXAS_PERF_CLR_5_EN 0x00000040U
-+#define ROGUE_CR_TEXAS_PERF_CLR_4_SHIFT 5U
-+#define ROGUE_CR_TEXAS_PERF_CLR_4_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_TEXAS_PERF_CLR_4_EN 0x00000020U
-+#define ROGUE_CR_TEXAS_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_TEXAS_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_TEXAS_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_TEXAS_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_TEXAS_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_TEXAS_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_TEXAS_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_TEXAS_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_TEXAS_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_TEXAS_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_TEXAS_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_TEXAS_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_TEXAS_PERF_SELECT0 */
-+#define ROGUE_CR_TEXAS_PERF_SELECT0 0x8298U
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_MASKFULL 0x3FFF3FFF803FFFFFULL
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_SHIFT 31U
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFF7FFFFFFFULL
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_EN 0x0000000080000000ULL
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFC0FFFFULL
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_TEXAS_PERF_COUNTER_0 */
-+#define ROGUE_CR_TEXAS_PERF_COUNTER_0 0x82D8U
-+#define ROGUE_CR_TEXAS_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_JONES_PERF */
-+#define ROGUE_CR_JONES_PERF 0x8330U
-+#define ROGUE_CR_JONES_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_JONES_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_JONES_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_JONES_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_JONES_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_JONES_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_JONES_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_JONES_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_JONES_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_JONES_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_JONES_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_JONES_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_JONES_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_JONES_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_JONES_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_JONES_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_JONES_PERF_SELECT0 */
-+#define ROGUE_CR_JONES_PERF_SELECT0 0x8338U
-+#define ROGUE_CR_JONES_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_JONES_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_JONES_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_JONES_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_JONES_PERF_COUNTER_0 */
-+#define ROGUE_CR_JONES_PERF_COUNTER_0 0x8368U
-+#define ROGUE_CR_JONES_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_JONES_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_JONES_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_BLACKPEARL_PERF */
-+#define ROGUE_CR_BLACKPEARL_PERF 0x8400U
-+#define ROGUE_CR_BLACKPEARL_PERF_MASKFULL 0x000000000000007FULL
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_5_SHIFT 6U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_5_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_5_EN 0x00000040U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_4_SHIFT 5U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_4_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_4_EN 0x00000020U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_BLACKPEARL_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_BLACKPEARL_PERF_SELECT0 */
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0 0x8408U
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MASKFULL 0x3FFF3FFF803FFFFFULL
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_SHIFT 31U
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFF7FFFFFFFULL
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_EN 0x0000000080000000ULL
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFC0FFFFULL
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_BLACKPEARL_PERF_COUNTER_0 */
-+#define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0 0x8448U
-+#define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_PBE_PERF */
-+#define ROGUE_CR_PBE_PERF 0x8478U
-+#define ROGUE_CR_PBE_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_PBE_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_PBE_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_PBE_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_PBE_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_PBE_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_PBE_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_PBE_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_PBE_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_PBE_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_PBE_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_PBE_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_PBE_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_PBE_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_PBE_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_PBE_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_PBE_PERF_SELECT0 */
-+#define ROGUE_CR_PBE_PERF_SELECT0 0x8480U
-+#define ROGUE_CR_PBE_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_PBE_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_PBE_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_PBE_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_PBE_PERF_COUNTER_0 */
-+#define ROGUE_CR_PBE_PERF_COUNTER_0 0x84B0U
-+#define ROGUE_CR_PBE_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_PBE_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_PBE_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_OCP_REVINFO */
-+#define ROGUE_CR_OCP_REVINFO 0x9000U
-+#define ROGUE_CR_OCP_REVINFO_MASKFULL 0x00000007FFFFFFFFULL
-+#define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_SHIFT 33U
-+#define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_CLRMSK 0xFFFFFFF9FFFFFFFFULL
-+#define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_SHIFT 32U
-+#define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_CLRMSK 0xFFFFFFFEFFFFFFFFULL
-+#define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_EN 0x0000000100000000ULL
-+#define ROGUE_CR_OCP_REVINFO_REVISION_SHIFT 0U
-+#define ROGUE_CR_OCP_REVINFO_REVISION_CLRMSK 0xFFFFFFFF00000000ULL
-+
-+/* Register ROGUE_CR_OCP_SYSCONFIG */
-+#define ROGUE_CR_OCP_SYSCONFIG 0x9010U
-+#define ROGUE_CR_OCP_SYSCONFIG_MASKFULL 0x0000000000000FFFULL
-+#define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_SHIFT 10U
-+#define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_CLRMSK 0xFFFFF3FFU
-+#define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_SHIFT 8U
-+#define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_CLRMSK 0xFFFFFCFFU
-+#define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_SHIFT 6U
-+#define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_CLRMSK 0xFFFFFF3FU
-+#define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_SHIFT 4U
-+#define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_CLRMSK 0xFFFFFFCFU
-+#define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_SHIFT 2U
-+#define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_CLRMSK 0xFFFFFFF3U
-+#define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_SHIFT 0U
-+#define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_CLRMSK 0xFFFFFFFCU
-+
-+/* Register ROGUE_CR_OCP_IRQSTATUS_RAW_0 */
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_0 0x9020U
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_0_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQSTATUS_RAW_1 */
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_1 0x9028U
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_1_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQSTATUS_RAW_2 */
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_2 0x9030U
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_2_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQSTATUS_0 */
-+#define ROGUE_CR_OCP_IRQSTATUS_0 0x9038U
-+#define ROGUE_CR_OCP_IRQSTATUS_0_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQSTATUS_1 */
-+#define ROGUE_CR_OCP_IRQSTATUS_1 0x9040U
-+#define ROGUE_CR_OCP_IRQSTATUS_1_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQSTATUS_2 */
-+#define ROGUE_CR_OCP_IRQSTATUS_2 0x9048U
-+#define ROGUE_CR_OCP_IRQSTATUS_2_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQENABLE_SET_0 */
-+#define ROGUE_CR_OCP_IRQENABLE_SET_0 0x9050U
-+#define ROGUE_CR_OCP_IRQENABLE_SET_0_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQENABLE_SET_1 */
-+#define ROGUE_CR_OCP_IRQENABLE_SET_1 0x9058U
-+#define ROGUE_CR_OCP_IRQENABLE_SET_1_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQENABLE_SET_2 */
-+#define ROGUE_CR_OCP_IRQENABLE_SET_2 0x9060U
-+#define ROGUE_CR_OCP_IRQENABLE_SET_2_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQENABLE_CLR_0 */
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_0 0x9068U
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_0_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQENABLE_CLR_1 */
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_1 0x9070U
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_1_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQENABLE_CLR_2 */
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_2 0x9078U
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_2_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_IRQ_EVENT */
-+#define ROGUE_CR_OCP_IRQ_EVENT 0x9080U
-+#define ROGUE_CR_OCP_IRQ_EVENT_MASKFULL 0x00000000000FFFFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_SHIFT 19U
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_CLRMSK 0xFFFFFFFFFFF7FFFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_EN 0x0000000000080000ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_SHIFT 18U
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_CLRMSK 0xFFFFFFFFFFFBFFFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_EN 0x0000000000040000ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_SHIFT 17U
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_CLRMSK 0xFFFFFFFFFFFDFFFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_EN 0x0000000000020000ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_SHIFT 16U
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_CLRMSK 0xFFFFFFFFFFFEFFFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_EN 0x0000000000010000ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_SHIFT 15U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFF7FFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000008000ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_SHIFT 14U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFBFFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_EN 0x0000000000004000ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_SHIFT 13U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFDFFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_EN 0x0000000000002000ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_SHIFT 12U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFEFFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_EN 0x0000000000001000ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_SHIFT 11U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFF7FFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000800ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_SHIFT 10U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFBFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_EN 0x0000000000000400ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_SHIFT 9U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFDFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_EN 0x0000000000000200ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_SHIFT 8U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFEFFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_EN 0x0000000000000100ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_SHIFT 7U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFFF7FULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000080ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_SHIFT 6U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFFBFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_EN 0x0000000000000040ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_SHIFT 5U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_EN 0x0000000000000020ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_SHIFT 4U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFFEFULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_EN 0x0000000000000010ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_SHIFT 3U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000008ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_SHIFT 2U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFFFBULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_EN 0x0000000000000004ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_SHIFT 1U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFFFDULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_EN 0x0000000000000002ULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_SHIFT 0U
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_OCP_DEBUG_CONFIG */
-+#define ROGUE_CR_OCP_DEBUG_CONFIG 0x9088U
-+#define ROGUE_CR_OCP_DEBUG_CONFIG_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_OCP_DEBUG_CONFIG_REG_SHIFT 0U
-+#define ROGUE_CR_OCP_DEBUG_CONFIG_REG_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_OCP_DEBUG_CONFIG_REG_EN 0x00000001U
-+
-+/* Register ROGUE_CR_OCP_DEBUG_STATUS */
-+#define ROGUE_CR_OCP_DEBUG_STATUS 0x9090U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_MASKFULL 0x001F1F77FFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_SHIFT 51U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_CLRMSK 0xFFE7FFFFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_SHIFT 50U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_CLRMSK 0xFFFBFFFFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_EN 0x0004000000000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_SHIFT 48U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_CLRMSK 0xFFFCFFFFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_SHIFT 43U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_CLRMSK 0xFFFFE7FFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_SHIFT 42U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_CLRMSK 0xFFFFFBFFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_EN 0x0000040000000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_SHIFT 40U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_CLRMSK 0xFFFFFCFFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_SHIFT 38U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_CLRMSK 0xFFFFFFBFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_EN 0x0000004000000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_SHIFT 37U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_CLRMSK 0xFFFFFFDFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_EN 0x0000002000000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_SHIFT 36U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_CLRMSK 0xFFFFFFEFFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_EN 0x0000001000000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_SHIFT 34U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_CLRMSK 0xFFFFFFFBFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_EN 0x0000000400000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_SHIFT 33U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_CLRMSK 0xFFFFFFFDFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_EN 0x0000000200000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_SHIFT 32U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_CLRMSK 0xFFFFFFFEFFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_EN 0x0000000100000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_SHIFT 31U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_CLRMSK 0xFFFFFFFF7FFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_EN 0x0000000080000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_SHIFT 30U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_CLRMSK 0xFFFFFFFFBFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_EN 0x0000000040000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_SHIFT 29U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_CLRMSK 0xFFFFFFFFDFFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_EN 0x0000000020000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_SHIFT 27U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_CLRMSK 0xFFFFFFFFE7FFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_SHIFT 26U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_CLRMSK 0xFFFFFFFFFBFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_EN 0x0000000004000000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_SHIFT 24U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_CLRMSK 0xFFFFFFFFFCFFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_SHIFT 23U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_CLRMSK 0xFFFFFFFFFF7FFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_EN 0x0000000000800000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_SHIFT 22U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_CLRMSK 0xFFFFFFFFFFBFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_EN 0x0000000000400000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_SHIFT 21U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_EN 0x0000000000200000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_SHIFT 19U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_CLRMSK 0xFFFFFFFFFFE7FFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_SHIFT 18U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_CLRMSK 0xFFFFFFFFFFFBFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_EN 0x0000000000040000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_SHIFT 16U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_CLRMSK 0xFFFFFFFFFFFCFFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_SHIFT 15U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_CLRMSK 0xFFFFFFFFFFFF7FFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_EN 0x0000000000008000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_SHIFT 14U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_CLRMSK 0xFFFFFFFFFFFFBFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_EN 0x0000000000004000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_SHIFT 13U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_CLRMSK 0xFFFFFFFFFFFFDFFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_EN 0x0000000000002000ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_SHIFT 11U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_CLRMSK 0xFFFFFFFFFFFFE7FFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_SHIFT 10U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_CLRMSK 0xFFFFFFFFFFFFFBFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_EN 0x0000000000000400ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_SHIFT 8U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_CLRMSK 0xFFFFFFFFFFFFFCFFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_SHIFT 7U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_CLRMSK 0xFFFFFFFFFFFFFF7FULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_EN 0x0000000000000080ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_SHIFT 6U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_CLRMSK 0xFFFFFFFFFFFFFFBFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_EN 0x0000000000000040ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_SHIFT 5U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_CLRMSK 0xFFFFFFFFFFFFFFDFULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_EN 0x0000000000000020ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_SHIFT 3U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_CLRMSK 0xFFFFFFFFFFFFFFE7ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_SHIFT 2U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_CLRMSK 0xFFFFFFFFFFFFFFFBULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_EN 0x0000000000000004ULL
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_SHIFT 0U
-+#define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_CLRMSK 0xFFFFFFFFFFFFFFFCULL
-+
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_SHIFT 6U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_EN 0x00000040U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_SHIFT 5U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_EN 0x00000020U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_META_SHIFT 4U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_META_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_META_EN 0x00000010U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_SHIFT 3U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_EN 0x00000008U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_SHIFT 2U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_EN 0x00000004U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_SHIFT 1U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_EN 0x00000002U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_SHIFT 0U
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_EN 0x00000001U
-+
-+#define ROGUE_CR_BIF_TRUST_DM_MASK 0x0000007FU
-+
-+/* Register ROGUE_CR_BIF_TRUST */
-+#define ROGUE_CR_BIF_TRUST 0xA000U
-+#define ROGUE_CR_BIF_TRUST_MASKFULL 0x00000000001FFFFFULL
-+#define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_SHIFT 20U
-+#define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_CLRMSK 0xFFEFFFFFU
-+#define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_EN 0x00100000U
-+#define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_SHIFT 19U
-+#define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_CLRMSK 0xFFF7FFFFU
-+#define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_EN 0x00080000U
-+#define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_SHIFT 18U
-+#define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_CLRMSK 0xFFFBFFFFU
-+#define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_EN 0x00040000U
-+#define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_SHIFT 17U
-+#define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_CLRMSK 0xFFFDFFFFU
-+#define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_EN 0x00020000U
-+#define ROGUE_CR_BIF_TRUST_ENABLE_SHIFT 16U
-+#define ROGUE_CR_BIF_TRUST_ENABLE_CLRMSK 0xFFFEFFFFU
-+#define ROGUE_CR_BIF_TRUST_ENABLE_EN 0x00010000U
-+#define ROGUE_CR_BIF_TRUST_DM_TRUSTED_SHIFT 9U
-+#define ROGUE_CR_BIF_TRUST_DM_TRUSTED_CLRMSK 0xFFFF01FFU
-+#define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_SHIFT 8U
-+#define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_EN 0x00000100U
-+#define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_SHIFT 7U
-+#define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFF7FU
-+#define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_EN 0x00000080U
-+#define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_SHIFT 6U
-+#define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_EN 0x00000040U
-+#define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_SHIFT 5U
-+#define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_EN 0x00000020U
-+#define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_SHIFT 4U
-+#define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_EN 0x00000010U
-+#define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_SHIFT 3U
-+#define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_EN 0x00000008U
-+#define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_SHIFT 2U
-+#define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_EN 0x00000004U
-+#define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_SHIFT 1U
-+#define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_EN 0x00000002U
-+#define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_SHIFT 0U
-+#define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SYS_BUS_SECURE */
-+#define ROGUE_CR_SYS_BUS_SECURE 0xA100U
-+#define ROGUE_CR_SYS_BUS_SECURE__SECR__MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_SYS_BUS_SECURE_MASKFULL 0x0000000000000001ULL
-+#define ROGUE_CR_SYS_BUS_SECURE_ENABLE_SHIFT 0U
-+#define ROGUE_CR_SYS_BUS_SECURE_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SYS_BUS_SECURE_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_FBA_FC0_CHECKSUM */
-+#define ROGUE_CR_FBA_FC0_CHECKSUM 0xD170U
-+#define ROGUE_CR_FBA_FC0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_FBA_FC1_CHECKSUM */
-+#define ROGUE_CR_FBA_FC1_CHECKSUM 0xD178U
-+#define ROGUE_CR_FBA_FC1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_FBA_FC2_CHECKSUM */
-+#define ROGUE_CR_FBA_FC2_CHECKSUM 0xD180U
-+#define ROGUE_CR_FBA_FC2_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_FBA_FC3_CHECKSUM */
-+#define ROGUE_CR_FBA_FC3_CHECKSUM 0xD188U
-+#define ROGUE_CR_FBA_FC3_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_CLK_CTRL2 */
-+#define ROGUE_CR_CLK_CTRL2 0xD200U
-+#define ROGUE_CR_CLK_CTRL2_MASKFULL 0x0000000000000F33ULL
-+#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_SHIFT 10U
-+#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_CLRMSK 0xFFFFFFFFFFFFF3FFULL
-+#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_ON 0x0000000000000400ULL
-+#define ROGUE_CR_CLK_CTRL2_MCU_FBTC_AUTO 0x0000000000000800ULL
-+#define ROGUE_CR_CLK_CTRL2_VRDM_SHIFT 8U
-+#define ROGUE_CR_CLK_CTRL2_VRDM_CLRMSK 0xFFFFFFFFFFFFFCFFULL
-+#define ROGUE_CR_CLK_CTRL2_VRDM_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL2_VRDM_ON 0x0000000000000100ULL
-+#define ROGUE_CR_CLK_CTRL2_VRDM_AUTO 0x0000000000000200ULL
-+#define ROGUE_CR_CLK_CTRL2_SH_SHIFT 4U
-+#define ROGUE_CR_CLK_CTRL2_SH_CLRMSK 0xFFFFFFFFFFFFFFCFULL
-+#define ROGUE_CR_CLK_CTRL2_SH_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL2_SH_ON 0x0000000000000010ULL
-+#define ROGUE_CR_CLK_CTRL2_SH_AUTO 0x0000000000000020ULL
-+#define ROGUE_CR_CLK_CTRL2_FBA_SHIFT 0U
-+#define ROGUE_CR_CLK_CTRL2_FBA_CLRMSK 0xFFFFFFFFFFFFFFFCULL
-+#define ROGUE_CR_CLK_CTRL2_FBA_OFF 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_CTRL2_FBA_ON 0x0000000000000001ULL
-+#define ROGUE_CR_CLK_CTRL2_FBA_AUTO 0x0000000000000002ULL
-+
-+/* Register ROGUE_CR_CLK_STATUS2 */
-+#define ROGUE_CR_CLK_STATUS2 0xD208U
-+#define ROGUE_CR_CLK_STATUS2_MASKFULL 0x0000000000000015ULL
-+#define ROGUE_CR_CLK_STATUS2_VRDM_SHIFT 4U
-+#define ROGUE_CR_CLK_STATUS2_VRDM_CLRMSK 0xFFFFFFFFFFFFFFEFULL
-+#define ROGUE_CR_CLK_STATUS2_VRDM_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS2_VRDM_RUNNING 0x0000000000000010ULL
-+#define ROGUE_CR_CLK_STATUS2_SH_SHIFT 2U
-+#define ROGUE_CR_CLK_STATUS2_SH_CLRMSK 0xFFFFFFFFFFFFFFFBULL
-+#define ROGUE_CR_CLK_STATUS2_SH_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS2_SH_RUNNING 0x0000000000000004ULL
-+#define ROGUE_CR_CLK_STATUS2_FBA_SHIFT 0U
-+#define ROGUE_CR_CLK_STATUS2_FBA_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_CLK_STATUS2_FBA_GATED 0x0000000000000000ULL
-+#define ROGUE_CR_CLK_STATUS2_FBA_RUNNING 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_RPM_SHF_FPL */
-+#define ROGUE_CR_RPM_SHF_FPL 0xD520U
-+#define ROGUE_CR_RPM_SHF_FPL_MASKFULL 0x3FFFFFFFFFFFFFFCULL
-+#define ROGUE_CR_RPM_SHF_FPL_SIZE_SHIFT 40U
-+#define ROGUE_CR_RPM_SHF_FPL_SIZE_CLRMSK 0xC00000FFFFFFFFFFULL
-+#define ROGUE_CR_RPM_SHF_FPL_BASE_SHIFT 2U
-+#define ROGUE_CR_RPM_SHF_FPL_BASE_CLRMSK 0xFFFFFF0000000003ULL
-+#define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSHIFT 2U
-+#define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSIZE 4U
-+
-+/* Register ROGUE_CR_RPM_SHF_FPL_READ */
-+#define ROGUE_CR_RPM_SHF_FPL_READ 0xD528U
-+#define ROGUE_CR_RPM_SHF_FPL_READ_MASKFULL 0x00000000007FFFFFULL
-+#define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_SHIFT 22U
-+#define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_CLRMSK 0xFFBFFFFFU
-+#define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_EN 0x00400000U
-+#define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_SHIFT 0U
-+#define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_CLRMSK 0xFFC00000U
-+
-+/* Register ROGUE_CR_RPM_SHF_FPL_WRITE */
-+#define ROGUE_CR_RPM_SHF_FPL_WRITE 0xD530U
-+#define ROGUE_CR_RPM_SHF_FPL_WRITE_MASKFULL 0x00000000007FFFFFULL
-+#define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_SHIFT 22U
-+#define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_CLRMSK 0xFFBFFFFFU
-+#define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_EN 0x00400000U
-+#define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_SHIFT 0U
-+#define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_CLRMSK 0xFFC00000U
-+
-+/* Register ROGUE_CR_RPM_SHG_FPL */
-+#define ROGUE_CR_RPM_SHG_FPL 0xD538U
-+#define ROGUE_CR_RPM_SHG_FPL_MASKFULL 0x3FFFFFFFFFFFFFFCULL
-+#define ROGUE_CR_RPM_SHG_FPL_SIZE_SHIFT 40U
-+#define ROGUE_CR_RPM_SHG_FPL_SIZE_CLRMSK 0xC00000FFFFFFFFFFULL
-+#define ROGUE_CR_RPM_SHG_FPL_BASE_SHIFT 2U
-+#define ROGUE_CR_RPM_SHG_FPL_BASE_CLRMSK 0xFFFFFF0000000003ULL
-+#define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSHIFT 2U
-+#define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSIZE 4U
-+
-+/* Register ROGUE_CR_RPM_SHG_FPL_READ */
-+#define ROGUE_CR_RPM_SHG_FPL_READ 0xD540U
-+#define ROGUE_CR_RPM_SHG_FPL_READ_MASKFULL 0x00000000007FFFFFULL
-+#define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_SHIFT 22U
-+#define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_CLRMSK 0xFFBFFFFFU
-+#define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_EN 0x00400000U
-+#define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_SHIFT 0U
-+#define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_CLRMSK 0xFFC00000U
-+
-+/* Register ROGUE_CR_RPM_SHG_FPL_WRITE */
-+#define ROGUE_CR_RPM_SHG_FPL_WRITE 0xD548U
-+#define ROGUE_CR_RPM_SHG_FPL_WRITE_MASKFULL 0x00000000007FFFFFULL
-+#define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_SHIFT 22U
-+#define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_CLRMSK 0xFFBFFFFFU
-+#define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_EN 0x00400000U
-+#define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_SHIFT 0U
-+#define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_CLRMSK 0xFFC00000U
-+
-+/* Register ROGUE_CR_SH_PERF */
-+#define ROGUE_CR_SH_PERF 0xD5F8U
-+#define ROGUE_CR_SH_PERF_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_SH_PERF_CLR_3_SHIFT 4U
-+#define ROGUE_CR_SH_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_SH_PERF_CLR_3_EN 0x00000010U
-+#define ROGUE_CR_SH_PERF_CLR_2_SHIFT 3U
-+#define ROGUE_CR_SH_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_SH_PERF_CLR_2_EN 0x00000008U
-+#define ROGUE_CR_SH_PERF_CLR_1_SHIFT 2U
-+#define ROGUE_CR_SH_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SH_PERF_CLR_1_EN 0x00000004U
-+#define ROGUE_CR_SH_PERF_CLR_0_SHIFT 1U
-+#define ROGUE_CR_SH_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SH_PERF_CLR_0_EN 0x00000002U
-+#define ROGUE_CR_SH_PERF_CTRL_ENABLE_SHIFT 0U
-+#define ROGUE_CR_SH_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SH_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SH_PERF_SELECT0 */
-+#define ROGUE_CR_SH_PERF_SELECT0 0xD600U
-+#define ROGUE_CR_SH_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define ROGUE_CR_SH_PERF_SELECT0_MODE_SHIFT 21U
-+#define ROGUE_CR_SH_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define ROGUE_CR_SH_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_SH_PERF_COUNTER_0 */
-+#define ROGUE_CR_SH_PERF_COUNTER_0 0xD628U
-+#define ROGUE_CR_SH_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SH_PERF_COUNTER_0_REG_SHIFT 0U
-+#define ROGUE_CR_SH_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SHF_SHG_CHECKSUM */
-+#define ROGUE_CR_SHF_SHG_CHECKSUM 0xD1C0U
-+#define ROGUE_CR_SHF_SHG_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM */
-+#define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM 0xD1C8U
-+#define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SHF_VARY_BIF_CHECKSUM */
-+#define ROGUE_CR_SHF_VARY_BIF_CHECKSUM 0xD1D0U
-+#define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_RPM_BIF_CHECKSUM */
-+#define ROGUE_CR_RPM_BIF_CHECKSUM 0xD1D8U
-+#define ROGUE_CR_RPM_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SHG_BIF_CHECKSUM */
-+#define ROGUE_CR_SHG_BIF_CHECKSUM 0xD1E0U
-+#define ROGUE_CR_SHG_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register ROGUE_CR_SHG_FE_BE_CHECKSUM */
-+#define ROGUE_CR_SHG_FE_BE_CHECKSUM 0xD1E8U
-+#define ROGUE_CR_SHG_FE_BE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_SHIFT 0U
-+#define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_CLRMSK 0x00000000U
-+
-+/* Register DPX_CR_BF_PERF */
-+#define DPX_CR_BF_PERF 0xC458U
-+#define DPX_CR_BF_PERF_MASKFULL 0x000000000000001FULL
-+#define DPX_CR_BF_PERF_CLR_3_SHIFT 4U
-+#define DPX_CR_BF_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define DPX_CR_BF_PERF_CLR_3_EN 0x00000010U
-+#define DPX_CR_BF_PERF_CLR_2_SHIFT 3U
-+#define DPX_CR_BF_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define DPX_CR_BF_PERF_CLR_2_EN 0x00000008U
-+#define DPX_CR_BF_PERF_CLR_1_SHIFT 2U
-+#define DPX_CR_BF_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define DPX_CR_BF_PERF_CLR_1_EN 0x00000004U
-+#define DPX_CR_BF_PERF_CLR_0_SHIFT 1U
-+#define DPX_CR_BF_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define DPX_CR_BF_PERF_CLR_0_EN 0x00000002U
-+#define DPX_CR_BF_PERF_CTRL_ENABLE_SHIFT 0U
-+#define DPX_CR_BF_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define DPX_CR_BF_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register DPX_CR_BF_PERF_SELECT0 */
-+#define DPX_CR_BF_PERF_SELECT0 0xC460U
-+#define DPX_CR_BF_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define DPX_CR_BF_PERF_SELECT0_MODE_SHIFT 21U
-+#define DPX_CR_BF_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define DPX_CR_BF_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register DPX_CR_BF_PERF_COUNTER_0 */
-+#define DPX_CR_BF_PERF_COUNTER_0 0xC488U
-+#define DPX_CR_BF_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define DPX_CR_BF_PERF_COUNTER_0_REG_SHIFT 0U
-+#define DPX_CR_BF_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register DPX_CR_BT_PERF */
-+#define DPX_CR_BT_PERF 0xC3D0U
-+#define DPX_CR_BT_PERF_MASKFULL 0x000000000000001FULL
-+#define DPX_CR_BT_PERF_CLR_3_SHIFT 4U
-+#define DPX_CR_BT_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define DPX_CR_BT_PERF_CLR_3_EN 0x00000010U
-+#define DPX_CR_BT_PERF_CLR_2_SHIFT 3U
-+#define DPX_CR_BT_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define DPX_CR_BT_PERF_CLR_2_EN 0x00000008U
-+#define DPX_CR_BT_PERF_CLR_1_SHIFT 2U
-+#define DPX_CR_BT_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define DPX_CR_BT_PERF_CLR_1_EN 0x00000004U
-+#define DPX_CR_BT_PERF_CLR_0_SHIFT 1U
-+#define DPX_CR_BT_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define DPX_CR_BT_PERF_CLR_0_EN 0x00000002U
-+#define DPX_CR_BT_PERF_CTRL_ENABLE_SHIFT 0U
-+#define DPX_CR_BT_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define DPX_CR_BT_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register DPX_CR_BT_PERF_SELECT0 */
-+#define DPX_CR_BT_PERF_SELECT0 0xC3D8U
-+#define DPX_CR_BT_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define DPX_CR_BT_PERF_SELECT0_MODE_SHIFT 21U
-+#define DPX_CR_BT_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define DPX_CR_BT_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register DPX_CR_BT_PERF_COUNTER_0 */
-+#define DPX_CR_BT_PERF_COUNTER_0 0xC420U
-+#define DPX_CR_BT_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define DPX_CR_BT_PERF_COUNTER_0_REG_SHIFT 0U
-+#define DPX_CR_BT_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register DPX_CR_RQ_USC_DEBUG */
-+#define DPX_CR_RQ_USC_DEBUG 0xC110U
-+#define DPX_CR_RQ_USC_DEBUG_MASKFULL 0x00000000FFFFFFFFULL
-+#define DPX_CR_RQ_USC_DEBUG_CHECKSUM_SHIFT 0U
-+#define DPX_CR_RQ_USC_DEBUG_CHECKSUM_CLRMSK 0xFFFFFFFF00000000ULL
-+
-+/* Register DPX_CR_BIF_FAULT_BANK_MMU_STATUS */
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS 0xC5C8U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_MASKFULL 0x000000000000F775ULL
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_SHIFT 12U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_SHIFT 8U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_SHIFT 5U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_SHIFT 4U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_EN 0x00000010U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_SHIFT 0U
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU
-+#define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_EN 0x00000001U
-+
-+/* Register DPX_CR_BIF_FAULT_BANK_REQ_STATUS */
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS 0xC5D0U
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_MASKFULL 0x03FFFFFFFFFFFFF0ULL
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_SHIFT 57U
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_CLRMSK 0xFDFFFFFFFFFFFFFFULL
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_EN 0x0200000000000000ULL
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_SHIFT 44U
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_CLRMSK 0xFE000FFFFFFFFFFFULL
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_SHIFT 40U
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_SHIFT 4U
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U
-+#define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSIZE 16U
-+
-+/* Register DPX_CR_BIF_MMU_STATUS */
-+#define DPX_CR_BIF_MMU_STATUS 0xC5D8U
-+#define DPX_CR_BIF_MMU_STATUS_MASKFULL 0x000000000FFFFFF7ULL
-+#define DPX_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U
-+#define DPX_CR_BIF_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU
-+#define DPX_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U
-+#define DPX_CR_BIF_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU
-+#define DPX_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U
-+#define DPX_CR_BIF_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU
-+#define DPX_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U
-+#define DPX_CR_BIF_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU
-+#define DPX_CR_BIF_MMU_STATUS_STALLED_EN 0x00000004U
-+#define DPX_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U
-+#define DPX_CR_BIF_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU
-+#define DPX_CR_BIF_MMU_STATUS_PAUSED_EN 0x00000002U
-+#define DPX_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U
-+#define DPX_CR_BIF_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU
-+#define DPX_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U
-+
-+/* Register DPX_CR_RT_PERF */
-+#define DPX_CR_RT_PERF 0xC700U
-+#define DPX_CR_RT_PERF_MASKFULL 0x000000000000001FULL
-+#define DPX_CR_RT_PERF_CLR_3_SHIFT 4U
-+#define DPX_CR_RT_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define DPX_CR_RT_PERF_CLR_3_EN 0x00000010U
-+#define DPX_CR_RT_PERF_CLR_2_SHIFT 3U
-+#define DPX_CR_RT_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define DPX_CR_RT_PERF_CLR_2_EN 0x00000008U
-+#define DPX_CR_RT_PERF_CLR_1_SHIFT 2U
-+#define DPX_CR_RT_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define DPX_CR_RT_PERF_CLR_1_EN 0x00000004U
-+#define DPX_CR_RT_PERF_CLR_0_SHIFT 1U
-+#define DPX_CR_RT_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define DPX_CR_RT_PERF_CLR_0_EN 0x00000002U
-+#define DPX_CR_RT_PERF_CTRL_ENABLE_SHIFT 0U
-+#define DPX_CR_RT_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define DPX_CR_RT_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register DPX_CR_RT_PERF_SELECT0 */
-+#define DPX_CR_RT_PERF_SELECT0 0xC708U
-+#define DPX_CR_RT_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define DPX_CR_RT_PERF_SELECT0_MODE_SHIFT 21U
-+#define DPX_CR_RT_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define DPX_CR_RT_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register DPX_CR_RT_PERF_COUNTER_0 */
-+#define DPX_CR_RT_PERF_COUNTER_0 0xC730U
-+#define DPX_CR_RT_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define DPX_CR_RT_PERF_COUNTER_0_REG_SHIFT 0U
-+#define DPX_CR_RT_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register DPX_CR_BX_TU_PERF */
-+#define DPX_CR_BX_TU_PERF 0xC908U
-+#define DPX_CR_BX_TU_PERF_MASKFULL 0x000000000000001FULL
-+#define DPX_CR_BX_TU_PERF_CLR_3_SHIFT 4U
-+#define DPX_CR_BX_TU_PERF_CLR_3_CLRMSK 0xFFFFFFEFU
-+#define DPX_CR_BX_TU_PERF_CLR_3_EN 0x00000010U
-+#define DPX_CR_BX_TU_PERF_CLR_2_SHIFT 3U
-+#define DPX_CR_BX_TU_PERF_CLR_2_CLRMSK 0xFFFFFFF7U
-+#define DPX_CR_BX_TU_PERF_CLR_2_EN 0x00000008U
-+#define DPX_CR_BX_TU_PERF_CLR_1_SHIFT 2U
-+#define DPX_CR_BX_TU_PERF_CLR_1_CLRMSK 0xFFFFFFFBU
-+#define DPX_CR_BX_TU_PERF_CLR_1_EN 0x00000004U
-+#define DPX_CR_BX_TU_PERF_CLR_0_SHIFT 1U
-+#define DPX_CR_BX_TU_PERF_CLR_0_CLRMSK 0xFFFFFFFDU
-+#define DPX_CR_BX_TU_PERF_CLR_0_EN 0x00000002U
-+#define DPX_CR_BX_TU_PERF_CTRL_ENABLE_SHIFT 0U
-+#define DPX_CR_BX_TU_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU
-+#define DPX_CR_BX_TU_PERF_CTRL_ENABLE_EN 0x00000001U
-+
-+/* Register DPX_CR_BX_TU_PERF_SELECT0 */
-+#define DPX_CR_BX_TU_PERF_SELECT0 0xC910U
-+#define DPX_CR_BX_TU_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL
-+#define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_SHIFT 48U
-+#define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL
-+#define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_SHIFT 32U
-+#define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL
-+#define DPX_CR_BX_TU_PERF_SELECT0_MODE_SHIFT 21U
-+#define DPX_CR_BX_TU_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL
-+#define DPX_CR_BX_TU_PERF_SELECT0_MODE_EN 0x0000000000200000ULL
-+#define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_SHIFT 16U
-+#define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL
-+#define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_SHIFT 0U
-+#define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register DPX_CR_BX_TU_PERF_COUNTER_0 */
-+#define DPX_CR_BX_TU_PERF_COUNTER_0 0xC938U
-+#define DPX_CR_BX_TU_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL
-+#define DPX_CR_BX_TU_PERF_COUNTER_0_REG_SHIFT 0U
-+#define DPX_CR_BX_TU_PERF_COUNTER_0_REG_CLRMSK 0x00000000U
-+
-+/* Register DPX_CR_RS_PDS_RR_CHECKSUM */
-+#define DPX_CR_RS_PDS_RR_CHECKSUM 0xC0F0U
-+#define DPX_CR_RS_PDS_RR_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL
-+#define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_SHIFT 0U
-+#define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_CLRMSK 0xFFFFFFFF00000000ULL
-+
-+/* Register ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT */
-+#define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT 0xE140U
-+#define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_MASKFULL 0x00000000000000FFULL
-+#define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT 0U
-+#define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_MMU_CBASE_MAPPING */
-+#define ROGUE_CR_MMU_CBASE_MAPPING 0xE148U
-+#define ROGUE_CR_MMU_CBASE_MAPPING_MASKFULL 0x000000000FFFFFFFULL
-+#define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT 0U
-+#define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK 0xF0000000U
-+#define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT 12U
-+#define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE 4096U
-+
-+/* Register ROGUE_CR_MMU_FAULT_STATUS */
-+#define ROGUE_CR_MMU_FAULT_STATUS 0xE150U
-+#define ROGUE_CR_MMU_FAULT_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_SHIFT 28U
-+#define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_CLRMSK 0x000000000FFFFFFFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_SHIFT 20U
-+#define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_CLRMSK 0xFFFFFFFFF00FFFFFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_SHIFT 12U
-+#define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_CLRMSK 0xFFFFFFFFFFF00FFFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_SHIFT 6U
-+#define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_CLRMSK 0xFFFFFFFFFFFFF03FULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_SHIFT 4U
-+#define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_CLRMSK 0xFFFFFFFFFFFFFFCFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_RNW_SHIFT 3U
-+#define ROGUE_CR_MMU_FAULT_STATUS_RNW_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_RNW_EN 0x0000000000000008ULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_TYPE_SHIFT 1U
-+#define ROGUE_CR_MMU_FAULT_STATUS_TYPE_CLRMSK 0xFFFFFFFFFFFFFFF9ULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_FAULT_SHIFT 0U
-+#define ROGUE_CR_MMU_FAULT_STATUS_FAULT_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_FAULT_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_MMU_FAULT_STATUS_META */
-+#define ROGUE_CR_MMU_FAULT_STATUS_META 0xE158U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT 28U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK 0x000000000FFFFFFFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT 20U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK 0xFFFFFFFFF00FFFFFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_SHIFT 12U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_CLRMSK 0xFFFFFFFFFFF00FFFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT 6U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK 0xFFFFFFFFFFFFF03FULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT 4U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK 0xFFFFFFFFFFFFFFCFULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_SHIFT 3U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK 0xFFFFFFFFFFFFFFF7ULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_EN 0x0000000000000008ULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT 1U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK 0xFFFFFFFFFFFFFFF9ULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT 0U
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK 0xFFFFFFFFFFFFFFFEULL
-+#define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_EN 0x0000000000000001ULL
-+
-+/* Register ROGUE_CR_SLC3_CTRL_MISC */
-+#define ROGUE_CR_SLC3_CTRL_MISC 0xE200U
-+#define ROGUE_CR_SLC3_CTRL_MISC_MASKFULL 0x0000000000000107ULL
-+#define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_SHIFT 8U
-+#define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_CLRMSK 0xFFFFFEFFU
-+#define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_EN 0x00000100U
-+#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 0U
-+#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_CLRMSK 0xFFFFFFF8U
-+#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_LINEAR 0x00000000U
-+#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_IN_PAGE_HASH 0x00000001U
-+#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_FIXED_PVR_HASH 0x00000002U
-+#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SCRAMBLE_PVR_HASH 0x00000003U
-+#define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_WEAVED_HASH 0x00000004U
-+
-+/* Register ROGUE_CR_SLC3_SCRAMBLE */
-+#define ROGUE_CR_SLC3_SCRAMBLE 0xE208U
-+#define ROGUE_CR_SLC3_SCRAMBLE_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC3_SCRAMBLE_BITS_SHIFT 0U
-+#define ROGUE_CR_SLC3_SCRAMBLE_BITS_CLRMSK 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_SLC3_SCRAMBLE2 */
-+#define ROGUE_CR_SLC3_SCRAMBLE2 0xE210U
-+#define ROGUE_CR_SLC3_SCRAMBLE2_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC3_SCRAMBLE2_BITS_SHIFT 0U
-+#define ROGUE_CR_SLC3_SCRAMBLE2_BITS_CLRMSK 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_SLC3_SCRAMBLE3 */
-+#define ROGUE_CR_SLC3_SCRAMBLE3 0xE218U
-+#define ROGUE_CR_SLC3_SCRAMBLE3_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC3_SCRAMBLE3_BITS_SHIFT 0U
-+#define ROGUE_CR_SLC3_SCRAMBLE3_BITS_CLRMSK 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_SLC3_SCRAMBLE4 */
-+#define ROGUE_CR_SLC3_SCRAMBLE4 0xE260U
-+#define ROGUE_CR_SLC3_SCRAMBLE4_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC3_SCRAMBLE4_BITS_SHIFT 0U
-+#define ROGUE_CR_SLC3_SCRAMBLE4_BITS_CLRMSK 0x0000000000000000ULL
-+
-+/* Register ROGUE_CR_SLC3_STATUS */
-+#define ROGUE_CR_SLC3_STATUS 0xE220U
-+#define ROGUE_CR_SLC3_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC3_STATUS_WRITES1_SHIFT 48U
-+#define ROGUE_CR_SLC3_STATUS_WRITES1_CLRMSK 0x0000FFFFFFFFFFFFULL
-+#define ROGUE_CR_SLC3_STATUS_WRITES0_SHIFT 32U
-+#define ROGUE_CR_SLC3_STATUS_WRITES0_CLRMSK 0xFFFF0000FFFFFFFFULL
-+#define ROGUE_CR_SLC3_STATUS_READS1_SHIFT 16U
-+#define ROGUE_CR_SLC3_STATUS_READS1_CLRMSK 0xFFFFFFFF0000FFFFULL
-+#define ROGUE_CR_SLC3_STATUS_READS0_SHIFT 0U
-+#define ROGUE_CR_SLC3_STATUS_READS0_CLRMSK 0xFFFFFFFFFFFF0000ULL
-+
-+/* Register ROGUE_CR_SLC3_IDLE */
-+#define ROGUE_CR_SLC3_IDLE 0xE228U
-+#define ROGUE_CR_SLC3_IDLE_MASKFULL 0x00000000000FFFFFULL
-+#define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_SHIFT 18U
-+#define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_CLRMSK 0xFFF3FFFFU
-+#define ROGUE_CR_SLC3_IDLE_MMU_SHIFT 17U
-+#define ROGUE_CR_SLC3_IDLE_MMU_CLRMSK 0xFFFDFFFFU
-+#define ROGUE_CR_SLC3_IDLE_MMU_EN 0x00020000U
-+#define ROGUE_CR_SLC3_IDLE_RDI_SHIFT 16U
-+#define ROGUE_CR_SLC3_IDLE_RDI_CLRMSK 0xFFFEFFFFU
-+#define ROGUE_CR_SLC3_IDLE_RDI_EN 0x00010000U
-+#define ROGUE_CR_SLC3_IDLE_IMGBV4_SHIFT 12U
-+#define ROGUE_CR_SLC3_IDLE_IMGBV4_CLRMSK 0xFFFF0FFFU
-+#define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_SHIFT 4U
-+#define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_CLRMSK 0xFFFFF00FU
-+#define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_SHIFT 2U
-+#define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_CLRMSK 0xFFFFFFF3U
-+#define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_SHIFT 1U
-+#define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_EN 0x00000002U
-+#define ROGUE_CR_SLC3_IDLE_XBAR_SHIFT 0U
-+#define ROGUE_CR_SLC3_IDLE_XBAR_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SLC3_IDLE_XBAR_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SLC3_FAULT_STOP_STATUS */
-+#define ROGUE_CR_SLC3_FAULT_STOP_STATUS 0xE248U
-+#define ROGUE_CR_SLC3_FAULT_STOP_STATUS_MASKFULL 0x0000000000001FFFULL
-+#define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_SHIFT 0U
-+#define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_CLRMSK 0xFFFFE000U
-+
-+/* Register ROGUE_CR_VDM_CONTEXT_STORE_MODE */
-+#define ROGUE_CR_VDM_CONTEXT_STORE_MODE 0xF048U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MASKFULL 0x0000000000000003ULL
-+#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_SHIFT 0U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_CLRMSK 0xFFFFFFFCU
-+#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX 0x00000000U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE 0x00000001U
-+#define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST 0x00000002U
-+
-+/* Register ROGUE_CR_CONTEXT_MAPPING0 */
-+#define ROGUE_CR_CONTEXT_MAPPING0 0xF078U
-+#define ROGUE_CR_CONTEXT_MAPPING0_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING0_2D_SHIFT 24U
-+#define ROGUE_CR_CONTEXT_MAPPING0_2D_CLRMSK 0x00FFFFFFU
-+#define ROGUE_CR_CONTEXT_MAPPING0_CDM_SHIFT 16U
-+#define ROGUE_CR_CONTEXT_MAPPING0_CDM_CLRMSK 0xFF00FFFFU
-+#define ROGUE_CR_CONTEXT_MAPPING0_3D_SHIFT 8U
-+#define ROGUE_CR_CONTEXT_MAPPING0_3D_CLRMSK 0xFFFF00FFU
-+#define ROGUE_CR_CONTEXT_MAPPING0_TA_SHIFT 0U
-+#define ROGUE_CR_CONTEXT_MAPPING0_TA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_CONTEXT_MAPPING1 */
-+#define ROGUE_CR_CONTEXT_MAPPING1 0xF080U
-+#define ROGUE_CR_CONTEXT_MAPPING1_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING1_HOST_SHIFT 8U
-+#define ROGUE_CR_CONTEXT_MAPPING1_HOST_CLRMSK 0xFFFF00FFU
-+#define ROGUE_CR_CONTEXT_MAPPING1_TLA_SHIFT 0U
-+#define ROGUE_CR_CONTEXT_MAPPING1_TLA_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_CONTEXT_MAPPING2 */
-+#define ROGUE_CR_CONTEXT_MAPPING2 0xF088U
-+#define ROGUE_CR_CONTEXT_MAPPING2_MASKFULL 0x0000000000FFFFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_SHIFT 16U
-+#define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK 0xFF00FFFFU
-+#define ROGUE_CR_CONTEXT_MAPPING2_TE0_SHIFT 8U
-+#define ROGUE_CR_CONTEXT_MAPPING2_TE0_CLRMSK 0xFFFF00FFU
-+#define ROGUE_CR_CONTEXT_MAPPING2_VCE0_SHIFT 0U
-+#define ROGUE_CR_CONTEXT_MAPPING2_VCE0_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_CONTEXT_MAPPING3 */
-+#define ROGUE_CR_CONTEXT_MAPPING3 0xF090U
-+#define ROGUE_CR_CONTEXT_MAPPING3_MASKFULL 0x0000000000FFFFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_SHIFT 16U
-+#define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK 0xFF00FFFFU
-+#define ROGUE_CR_CONTEXT_MAPPING3_TE1_SHIFT 8U
-+#define ROGUE_CR_CONTEXT_MAPPING3_TE1_CLRMSK 0xFFFF00FFU
-+#define ROGUE_CR_CONTEXT_MAPPING3_VCE1_SHIFT 0U
-+#define ROGUE_CR_CONTEXT_MAPPING3_VCE1_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_BIF_JONES_OUTSTANDING_READ */
-+#define ROGUE_CR_BIF_JONES_OUTSTANDING_READ 0xF098U
-+#define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_SHIFT 0U
-+#define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ */
-+#define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ 0xF0A0U
-+#define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_SHIFT 0U
-+#define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_BIF_DUST_OUTSTANDING_READ */
-+#define ROGUE_CR_BIF_DUST_OUTSTANDING_READ 0xF0A8U
-+#define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL
-+#define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_SHIFT 0U
-+#define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U
-+
-+/* Register ROGUE_CR_CONTEXT_MAPPING4 */
-+#define ROGUE_CR_CONTEXT_MAPPING4 0xF210U
-+#define ROGUE_CR_CONTEXT_MAPPING4_MASKFULL 0x0000FFFFFFFFFFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_SHIFT 40U
-+#define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_CLRMSK 0xFFFF00FFFFFFFFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_SHIFT 32U
-+#define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_CLRMSK 0xFFFFFF00FFFFFFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_SHIFT 24U
-+#define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_CLRMSK 0xFFFFFFFF00FFFFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_SHIFT 16U
-+#define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_CLRMSK 0xFFFFFFFFFF00FFFFULL
-+#define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_SHIFT 8U
-+#define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_CLRMSK 0xFFFFFFFFFFFF00FFULL
-+#define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_SHIFT 0U
-+#define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_CLRMSK 0xFFFFFFFFFFFFFF00ULL
-+
-+/* Register ROGUE_CR_MULTICORE_GPU */
-+#define ROGUE_CR_MULTICORE_GPU 0xF300U
-+#define ROGUE_CR_MULTICORE_GPU_MASKFULL 0x000000000000007FULL
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_SHIFT 6U
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_EN 0x00000040U
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_SHIFT 5U
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_EN 0x00000020U
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_SHIFT 4U
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_EN 0x00000010U
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_SHIFT 3U
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_EN 0x00000008U
-+#define ROGUE_CR_MULTICORE_GPU_ID_SHIFT 0U
-+#define ROGUE_CR_MULTICORE_GPU_ID_CLRMSK 0xFFFFFFF8U
-+
-+/* Register ROGUE_CR_MULTICORE_SYSTEM */
-+#define ROGUE_CR_MULTICORE_SYSTEM 0xF308U
-+#define ROGUE_CR_MULTICORE_SYSTEM_MASKFULL 0x000000000000000FULL
-+#define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_SHIFT 0U
-+#define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_CLRMSK 0xFFFFFFF0U
-+
-+/* Register ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON */
-+#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON 0xF310U
-+#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
-+#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU
-+#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
-+#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU
-+#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON */
-+#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON 0xF320U
-+#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
-+#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU
-+#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
-+#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU
-+#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON */
-+#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON 0xF330U
-+#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL
-+#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U
-+#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU
-+#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U
-+#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU
-+#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
-+#define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U
-+
-+/* Register ROGUE_CR_ECC_RAM_ERR_INJ */
-+#define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U
-+
-+/* Register ROGUE_CR_ECC_RAM_INIT_KICK */
-+#define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_SHIFT 4U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_EN 0x00000010U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_USC_SHIFT 3U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_USC_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_USC_EN 0x00000008U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_SHIFT 2U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_EN 0x00000004U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_SHIFT 1U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_EN 0x00000002U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_SHIFT 0U
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_EN 0x00000001U
-+
-+/* Register ROGUE_CR_ECC_RAM_INIT_DONE */
-+#define ROGUE_CR_ECC_RAM_INIT_DONE 0xF350U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_MASKFULL 0x000000000000001FULL
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_SHIFT 4U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_EN 0x00000010U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_USC_SHIFT 3U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_USC_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_USC_EN 0x00000008U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_SHIFT 2U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_EN 0x00000004U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_SHIFT 1U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_EN 0x00000002U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_SHIFT 0U
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SAFETY_EVENT_ENABLE */
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE 0xF390U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_EN 0x00000008U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_EN 0x00000004U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_EN 0x00000002U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SAFETY_EVENT_STATUS */
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE 0xF398U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__MASKFULL 0x000000000000007FULL
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_SHIFT 3U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_EN 0x00000008U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_SHIFT 2U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN 0x00000004U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_SHIFT 1U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_EN 0x00000002U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_SAFETY_EVENT_CLEAR */
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE 0xF3A0U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__MASKFULL 0x000000000000007FULL
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_SHIFT 3U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_EN 0x00000008U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_SHIFT 2U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_EN 0x00000004U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_SHIFT 1U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_EN 0x00000002U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
-+
-+/* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_EN 0x00000008U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_EN 0x00000004U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_EN 0x00000002U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
-+#define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
-+
-+/* clang-format on */
-+
-+#endif /* __PVR_ROGUE_CR_DEFS_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_defs.h
-new file mode 100644
-index 000000000000..584835c5682a
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_defs.h
-@@ -0,0 +1,162 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_DEFS_H__
-+#define __PVR_ROGUE_DEFS_H__
-+
-+#include "pvr_rogue_cr_defs.h"
-+
-+#include <linux/bits.h>
-+
-+/*
-+ ******************************************************************************
-+ * ROGUE Defines
-+ ******************************************************************************
-+ */
-+
-+#define ROGUE_FW_MAX_NUM_OS (8U)
-+#define ROGUE_FW_HOST_OS (0U)
-+#define ROGUE_FW_GUEST_OSID_START (1U)
-+
-+#define ROGUE_FW_THREAD_0 (0U)
-+#define ROGUE_FW_THREAD_1 (1U)
-+
-+#define GET_ROGUE_CACHE_LINE_SIZE(x) ((((s32)(x)) > 0) ? ((x) / 8) : (0))
-+
-+#define MAX_HW_GEOM_FRAG_CONTEXTS 2U
-+
-+#define ROGUE_CR_CLK_CTRL_ALL_ON \
-+ (0x5555555555555555ull & ROGUE_CR_CLK_CTRL_MASKFULL)
-+#define ROGUE_CR_CLK_CTRL_ALL_AUTO \
-+ (0xaaaaaaaaaaaaaaaaull & ROGUE_CR_CLK_CTRL_MASKFULL)
-+#define ROGUE_CR_CLK_CTRL2_ALL_ON \
-+ (0x5555555555555555ull & ROGUE_CR_CLK_CTRL2_MASKFULL)
-+#define ROGUE_CR_CLK_CTRL2_ALL_AUTO \
-+ (0xaaaaaaaaaaaaaaaaull & ROGUE_CR_CLK_CTRL2_MASKFULL)
-+
-+#define ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN \
-+ (ROGUE_CR_SOFT_RESET_DUST_A_CORE_EN | \
-+ ROGUE_CR_SOFT_RESET_DUST_B_CORE_EN | \
-+ ROGUE_CR_SOFT_RESET_DUST_C_CORE_EN | \
-+ ROGUE_CR_SOFT_RESET_DUST_D_CORE_EN | \
-+ ROGUE_CR_SOFT_RESET_DUST_E_CORE_EN | \
-+ ROGUE_CR_SOFT_RESET_DUST_F_CORE_EN | \
-+ ROGUE_CR_SOFT_RESET_DUST_G_CORE_EN | \
-+ ROGUE_CR_SOFT_RESET_DUST_H_CORE_EN)
-+
-+/* SOFT_RESET Rascal and DUSTs bits */
-+#define ROGUE_CR_SOFT_RESET_RASCALDUSTS_EN \
-+ (ROGUE_CR_SOFT_RESET_RASCAL_CORE_EN | \
-+ ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN)
-+
-+/* SOFT_RESET steps as defined in the TRM */
-+#define ROGUE_S7_SOFT_RESET_DUSTS (ROGUE_CR_SOFT_RESET_DUST_n_CORE_EN)
-+
-+#define ROGUE_S7_SOFT_RESET_JONES \
-+ (ROGUE_CR_SOFT_RESET_PM_EN | ROGUE_CR_SOFT_RESET_VDM_EN | \
-+ ROGUE_CR_SOFT_RESET_ISP_EN)
-+
-+#define ROGUE_S7_SOFT_RESET_JONES_ALL \
-+ (ROGUE_S7_SOFT_RESET_JONES | ROGUE_CR_SOFT_RESET_BIF_EN | \
-+ ROGUE_CR_SOFT_RESET_SLC_EN | ROGUE_CR_SOFT_RESET_GARTEN_EN)
-+
-+#define ROGUE_S7_SOFT_RESET2 \
-+ (ROGUE_CR_SOFT_RESET2_BLACKPEARL_EN | ROGUE_CR_SOFT_RESET2_PIXEL_EN | \
-+ ROGUE_CR_SOFT_RESET2_CDM_EN | ROGUE_CR_SOFT_RESET2_VERTEX_EN)
-+
-+#define ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT (12U)
-+#define ROGUE_BIF_PM_PHYSICAL_PAGE_SIZE \
-+ BIT(ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT)
-+
-+#define ROGUE_BIF_PM_VIRTUAL_PAGE_ALIGNSHIFT (14U)
-+#define ROGUE_BIF_PM_VIRTUAL_PAGE_SIZE BIT(ROGUE_BIF_PM_VIRTUAL_PAGE_ALIGNSHIFT)
-+
-+#define ROGUE_BIF_PM_FREELIST_BASE_ADDR_ALIGNSIZE (16U)
-+
-+/*
-+ * To get the number of required Dusts, divide the number of
-+ * clusters by 2 and round up
-+ */
-+#define ROGUE_REQ_NUM_DUSTS(CLUSTERS) (((CLUSTERS) + 1U) / 2U)
-+
-+/*
-+ * To get the number of required Bernado/Phantom(s), divide
-+ * the number of clusters by 4 and round up
-+ */
-+#define ROGUE_REQ_NUM_PHANTOMS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)
-+#define ROGUE_REQ_NUM_BERNADOS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)
-+#define ROGUE_REQ_NUM_BLACKPEARLS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)
-+
-+/*
-+ * FW MMU contexts
-+ */
-+#define MMU_CONTEXT_MAPPING_FWPRIV (0x0) /* FW code/private data */
-+#define MMU_CONTEXT_MAPPING_FWIF (0x0) /* Host/FW data */
-+
-+/*
-+ * Utility macros to calculate CAT_BASE register addresses
-+ */
-+#define BIF_CAT_BASEX(n) \
-+ (ROGUE_CR_BIF_CAT_BASE0 + \
-+ (n) * (ROGUE_CR_BIF_CAT_BASE1 - ROGUE_CR_BIF_CAT_BASE0))
-+
-+#define FWCORE_MEM_CAT_BASEX(n) \
-+ (ROGUE_CR_FWCORE_MEM_CAT_BASE0 + \
-+ (n) * (ROGUE_CR_FWCORE_MEM_CAT_BASE1 - \
-+ ROGUE_CR_FWCORE_MEM_CAT_BASE0))
-+
-+/*
-+ * FWCORE wrapper register defines
-+ */
-+#define FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT \
-+ ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT
-+#define FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_CLRMSK \
-+ ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK
-+#define FWCORE_ADDR_REMAP_CONFIG0_SIZE_ALIGNSHIFT (12U)
-+
-+/*
-+ ******************************************************************************
-+ * WA HWBRNs
-+ ******************************************************************************
-+ */
-+
-+/* GPU CR timer tick in GPU cycles */
-+#define ROGUE_CRTIME_TICK_IN_CYCLES (256U)
-+
-+/* for nohw multicore return max cores possible to client */
-+#define ROGUE_MULTICORE_MAX_NOHW_CORES (4U)
-+
-+/*
-+ * If the size of the SLC is less than this value then the TPU bypasses the SLC.
-+ */
-+#define ROGUE_TPU_CACHED_SLC_SIZE_THRESHOLD (128U * 1024U)
-+
-+/*
-+ * If the size of the SLC is bigger than this value then the TCU must not be
-+ * bypassed in the SLC.
-+ * In XE_MEMORY_HIERARCHY cores, the TCU is bypassed by default.
-+ */
-+#define ROGUE_TCU_CACHED_SLC_SIZE_THRESHOLD (32U * 1024U)
-+
-+/*
-+ * Register used by the FW to track the current boot stage (not used in MIPS)
-+ */
-+#define ROGUE_FW_BOOT_STAGE_REGISTER (ROGUE_CR_POWER_ESTIMATE_RESULT)
-+
-+/*
-+ * Virtualisation definitions
-+ */
-+#define ROGUE_VIRTUALISATION_REG_SIZE_PER_OS \
-+ (ROGUE_CR_MTS_SCHEDULE1 - ROGUE_CR_MTS_SCHEDULE)
-+
-+/*
-+ * Macro used to indicate which version of HWPerf is active
-+ */
-+#define ROGUE_FEATURE_HWPERF_ROGUE
-+
-+/*
-+ * Maximum number of cores supported by TRP
-+ */
-+#define ROGUE_TRP_MAX_NUM_CORES (4U)
-+
-+#endif /* __PVR_ROGUE_DEFS_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif.h
-new file mode 100644
-index 000000000000..f17e8078c515
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif.h
-@@ -0,0 +1,2314 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_FWIF_H__
-+#define __PVR_ROGUE_FWIF_H__
-+
-+#include <linux/bits.h>
-+#include <linux/build_bug.h>
-+#include <linux/compiler.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+
-+#include "pvr_rogue_defs.h"
-+#include "pvr_rogue_fwif_common.h"
-+#include "pvr_rogue_fwif_shared.h"
-+
-+/*
-+ ****************************************************************************
-+ * Logging type
-+ ****************************************************************************
-+ */
-+#define ROGUE_FWIF_LOG_TYPE_NONE 0x00000000U
-+#define ROGUE_FWIF_LOG_TYPE_TRACE 0x00000001U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_MAIN 0x00000002U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_MTS 0x00000004U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_CLEANUP 0x00000008U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_CSW 0x00000010U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_BIF 0x00000020U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_PM 0x00000040U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_RTD 0x00000080U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_SPM 0x00000100U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_POW 0x00000200U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_HWR 0x00000400U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_HWP 0x00000800U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_RPM 0x00001000U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_DMA 0x00002000U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_MISC 0x00004000U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_DEBUG 0x80000000U
-+#define ROGUE_FWIF_LOG_TYPE_GROUP_MASK 0x80007FFEU
-+#define ROGUE_FWIF_LOG_TYPE_MASK 0x80007FFFU
-+
-+/* String used in pvrdebug -h output */
-+#define ROGUE_FWIF_LOG_GROUPS_STRING_LIST \
-+ "main,mts,cleanup,csw,bif,pm,rtd,spm,pow,hwr,hwp,rpm,dma,misc,debug"
-+
-+/* Table entry to map log group strings to log type value */
-+struct rogue_fwif_log_group_map_entry {
-+ const char *log_group_name;
-+ u32 log_group_type;
-+};
-+
-+/* clang-format off */
-+/*
-+ * Macro for use with the ROGUE_FWIF_LOG_GROUP_MAP_ENTRY type to create a lookup
-+ * table where needed. Keep log group names short, no more than 20 chars.
-+ */
-+#define ROGUE_FWIF_LOG_GROUP_NAME_VALUE_MAP \
-+ { "none", ROGUE_FWIF_LOG_TYPE_NONE }, \
-+ { "main", ROGUE_FWIF_LOG_TYPE_GROUP_MAIN }, \
-+ { "mts", ROGUE_FWIF_LOG_TYPE_GROUP_MTS }, \
-+ { "cleanup", ROGUE_FWIF_LOG_TYPE_GROUP_CLEANUP }, \
-+ { "csw", ROGUE_FWIF_LOG_TYPE_GROUP_CSW }, \
-+ { "bif", ROGUE_FWIF_LOG_TYPE_GROUP_BIF }, \
-+ { "pm", ROGUE_FWIF_LOG_TYPE_GROUP_PM }, \
-+ { "rtd", ROGUE_FWIF_LOG_TYPE_GROUP_RTD }, \
-+ { "spm", ROGUE_FWIF_LOG_TYPE_GROUP_SPM }, \
-+ { "pow", ROGUE_FWIF_LOG_TYPE_GROUP_POW }, \
-+ { "hwr", ROGUE_FWIF_LOG_TYPE_GROUP_HWR }, \
-+ { "hwp", ROGUE_FWIF_LOG_TYPE_GROUP_HWP }, \
-+ { "rpm", ROGUE_FWIF_LOG_TYPE_GROUP_RPM }, \
-+ { "dma", ROGUE_FWIF_LOG_TYPE_GROUP_DMA }, \
-+ { "misc", ROGUE_FWIF_LOG_TYPE_GROUP_MISC }, \
-+ { "debug", ROGUE_FWIF_LOG_TYPE_GROUP_DEBUG }
-+/* clang-format on */
-+
-+/*
-+ * Used in print statements to display log group state, one %s per group defined
-+ */
-+#define ROGUE_FWIF_LOG_ENABLED_GROUPS_LIST_PFSPEC \
-+ "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
-+
-+/* clang-format off */
-+/* Used in a print statement to display log group state, one per group */
-+#define ROGUE_FWIF_LOG_ENABLED_GROUPS_LIST(types) \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_MAIN)) ? ("main ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_MTS)) ? ("mts ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_CLEANUP)) ? ("cleanup ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_CSW)) ? ("csw ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_BIF)) ? ("bif ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_PM)) ? ("pm ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_RTD)) ? ("rtd ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_SPM)) ? ("spm ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_POW)) ? ("pow ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_HWR)) ? ("hwr ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_HWP)) ? ("hwp ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_RPM)) ? ("rpm ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_DMA)) ? ("dma ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_MISC)) ? ("misc ") : ("")), \
-+ (((types)(&ROGUE_FWIF_LOG_TYPE_GROUP_DEBUG)) ? ("debug ") : (""))
-+/* clang-format on */
-+
-+/*
-+ ****************************************************************************
-+ * ROGUE FW signature checks
-+ ****************************************************************************
-+ */
-+#define ROGUE_FW_SIG_BUFFER_SIZE_MIN (8192)
-+
-+/*
-+ ****************************************************************************
-+ * Trace Buffer
-+ ****************************************************************************
-+ */
-+
-+/* Default size of ROGUE_FWIF_TRACEBUF_SPACE in DWords */
-+#define ROGUE_FW_TRACE_BUF_DEFAULT_SIZE_IN_DWORDS 12000U
-+#define ROGUE_FW_TRACE_BUFFER_ASSERT_SIZE 200U
-+#define ROGUE_FW_THREAD_NUM 1U
-+
-+#define ROGUE_FW_POLL_TYPE_SET 0x80000000U
-+
-+struct rogue_fwif_file_info_buf {
-+ char path[ROGUE_FW_TRACE_BUFFER_ASSERT_SIZE];
-+ char info[ROGUE_FW_TRACE_BUFFER_ASSERT_SIZE];
-+ u32 line_num;
-+} __aligned(8);
-+
-+struct rogue_fwif_tracebuf_space {
-+ u32 trace_pointer;
-+
-+ u32 trace_buffer_fw_addr;
-+
-+ /* To be used by host when reading from trace buffer */
-+ u32 *trace_buffer;
-+
-+ struct rogue_fwif_file_info_buf assert_buf;
-+} __aligned(8);
-+
-+/* Total number of FW fault logs stored */
-+#define ROGUE_FWIF_FWFAULTINFO_MAX (8U)
-+
-+struct rogue_fw_fault_info {
-+ aligned_u64 cr_timer;
-+ aligned_u64 os_timer;
-+ u32 data __aligned(8);
-+ u32 reserved;
-+ struct rogue_fwif_file_info_buf fault_buf;
-+} __aligned(8);
-+
-+/* clang-format off */
-+#define ROGUE_FWIF_POW_STATES \
-+ X(ROGUE_FWIF_POW_OFF) /* idle and ready to full power down */ \
-+ X(ROGUE_FWIF_POW_ON) /* running HW commands */ \
-+ X(ROGUE_FWIF_POW_FORCED_IDLE) /* forced idle */ \
-+ X(ROGUE_FWIF_POW_IDLE) /* idle waiting for host handshake */
-+/* clang-format on */
-+
-+enum rogue_fwif_pow_state {
-+#define X(NAME) NAME,
-+ ROGUE_FWIF_POW_STATES
-+#undef X
-+};
-+
-+/* Firmware HWR states */
-+/* The HW state is ok or locked up */
-+#define ROGUE_FWIF_HWR_HARDWARE_OK BIT(0)
-+/* The analysis of a GPU lockup has been performed */
-+#define ROGUE_FWIF_HWR_ANALYSIS_DONE BIT(2)
-+/* A DM unrelated lockup has been detected */
-+#define ROGUE_FWIF_HWR_GENERAL_LOCKUP BIT(3)
-+/* At least one DM is running without being close to a lockup */
-+#define ROGUE_FWIF_HWR_DM_RUNNING_OK BIT(4)
-+/* At least one DM is close to lockup */
-+#define ROGUE_FWIF_HWR_DM_STALLING BIT(5)
-+/* The FW has faulted and needs to restart */
-+#define ROGUE_FWIF_HWR_FW_FAULT BIT(6)
-+/* The FW has requested the host to restart it */
-+#define ROGUE_FWIF_HWR_RESTART_REQUESTED BIT(7)
-+
-+#define ROGUE_FWIF_PHR_STATE_SHIFT (8U)
-+/* The FW has requested the host to restart it, per PHR configuration */
-+#define ROGUE_FWIF_PHR_RESTART_REQUESTED ((1) << ROGUE_FWIF_PHR_STATE_SHIFT)
-+/* A PHR triggered GPU reset has just finished */
-+#define ROGUE_FWIF_PHR_RESTART_FINISHED ((2) << ROGUE_FWIF_PHR_STATE_SHIFT)
-+#define ROGUE_FWIF_PHR_RESTART_MASK \
-+ (ROGUE_FWIF_PHR_RESTART_REQUESTED | ROGUE_FWIF_PHR_RESTART_FINISHED)
-+
-+/* Firmware per-DM HWR states */
-+/* DM is working if all flags are cleared */
-+#define ROGUE_FWIF_DM_STATE_WORKING (0)
-+/* DM is idle and ready for HWR */
-+#define ROGUE_FWIF_DM_STATE_READY_FOR_HWR BIT(0)
-+/* DM need to skip to next cmd before resuming processing */
-+#define ROGUE_FWIF_DM_STATE_NEEDS_SKIP BIT(2)
-+/* DM need partial render cleanup before resuming processing */
-+#define ROGUE_FWIF_DM_STATE_NEEDS_PR_CLEANUP BIT(3)
-+/* DM need to increment Recovery Count once fully recovered */
-+#define ROGUE_FWIF_DM_STATE_NEEDS_TRACE_CLEAR BIT(4)
-+/* DM was identified as locking up and causing HWR */
-+#define ROGUE_FWIF_DM_STATE_GUILTY_LOCKUP BIT(5)
-+/* DM was innocently affected by another lockup which caused HWR */
-+#define ROGUE_FWIF_DM_STATE_INNOCENT_LOCKUP BIT(6)
-+/* DM was identified as over-running and causing HWR */
-+#define ROGUE_FWIF_DM_STATE_GUILTY_OVERRUNING BIT(7)
-+/* DM was innocently affected by another DM over-running which caused HWR */
-+#define ROGUE_FWIF_DM_STATE_INNOCENT_OVERRUNING BIT(8)
-+/* DM was forced into HWR as it delayed more important workloads */
-+#define ROGUE_FWIF_DM_STATE_HARD_CONTEXT_SWITCH BIT(9)
-+
-+/* Firmware's connection state */
-+enum rogue_fwif_connection_fw_state {
-+ /* Firmware is offline */
-+ ROGUE_FW_CONNECTION_FW_OFFLINE = 0,
-+ /* Firmware is initialised */
-+ ROGUE_FW_CONNECTION_FW_READY,
-+ /* Firmware connection is fully established */
-+ ROGUE_FW_CONNECTION_FW_ACTIVE,
-+ /* Firmware is clearing up connection data*/
-+ ROGUE_FW_CONNECTION_FW_OFFLOADING,
-+ ROGUE_FW_CONNECTION_FW_STATE_COUNT
-+};
-+
-+/* OS' connection state */
-+enum rogue_fwif_connection_os_state {
-+ /* OS is offline */
-+ ROGUE_FW_CONNECTION_OS_OFFLINE = 0,
-+ /* OS's KM driver is setup and waiting */
-+ ROGUE_FW_CONNECTION_OS_READY,
-+ /* OS connection is fully established */
-+ ROGUE_FW_CONNECTION_OS_ACTIVE,
-+ ROGUE_FW_CONNECTION_OS_STATE_COUNT
-+};
-+
-+struct rogue_fwif_os_runtime_flags {
-+ int os_state : 3;
-+ int fl_ok : 1;
-+ int fl_grow_pending : 1;
-+ int isolated_os : 1;
-+ int reserved : 26;
-+};
-+
-+#define PVR_SLR_LOG_ENTRIES 10
-+/* MAX_CLIENT_CCB_NAME not visible to this header */
-+#define PVR_SLR_LOG_STRLEN 30
-+
-+struct rogue_fwif_slr_entry {
-+ aligned_u64 timestamp;
-+ u32 fw_ctx_addr;
-+ u32 num_ufos;
-+ char ccb_name[PVR_SLR_LOG_STRLEN];
-+} __aligned(8);
-+
-+/* firmware trace control data */
-+struct rogue_fwif_tracebuf {
-+ u32 log_type;
-+ struct rogue_fwif_tracebuf_space tracebuf[ROGUE_FW_THREAD_NUM];
-+ /*
-+ * Member initialised only when sTraceBuf is actually allocated (in
-+ * ROGUETraceBufferInitOnDemandResources)
-+ */
-+ u32 tracebuf_size_in_dwords;
-+ /* Compatibility and other flags */
-+ u32 tracebuf_flags;
-+} __aligned(8);
-+
-+/* firmware system data shared with the Host driver */
-+struct rogue_fwif_sysdata {
-+ /* Configuration flags from host */
-+ u32 config_flags;
-+ /* Extended configuration flags from host */
-+ u32 config_flags_ext;
-+ volatile enum rogue_fwif_pow_state pow_state;
-+ volatile u32 hw_perf_ridx;
-+ volatile u32 hw_perf_widx;
-+ volatile u32 hw_perf_wrap_count;
-+ /* Constant after setup, needed in FW */
-+ u32 hw_perf_size;
-+ /* The number of times the FW drops a packet due to buffer full */
-+ u32 hw_perf_drop_count;
-+
-+ /*
-+ * ui32HWPerfUt, ui32FirstDropOrdinal, ui32LastDropOrdinal only valid
-+ * when FW is built with ROGUE_HWPERF_UTILIZATION &
-+ * ROGUE_HWPERF_DROP_TRACKING defined in rogue_fw_hwperf.c
-+ */
-+ /* Buffer utilisation, high watermark of bytes in use */
-+ u32 hw_pert_ut;
-+ /* The ordinal of the first packet the FW dropped */
-+ u32 first_drop_ordinal;
-+ /* The ordinal of the last packet the FW dropped */
-+ u32 last_drop_ordinal;
-+ /* State flags for each Operating System mirrored from Fw coremem */
-+ struct rogue_fwif_os_runtime_flags
-+ os_runtime_flags_mirror[ROGUE_FW_MAX_NUM_OS];
-+ /* Priority for each Operating System mirrored from Fw coremem */
-+ u32 osid_prio_mirror[ROGUE_FW_MAX_NUM_OS];
-+
-+ /* Periodic Hardware Reset Mode mirrored from Fw coremem */
-+ u32 phr_mode_mirror;
-+ struct rogue_fw_fault_info fault_info[ROGUE_FWIF_FWFAULTINFO_MAX];
-+ u32 fw_faults;
-+ u32 cr_poll_addr[ROGUE_FW_THREAD_NUM];
-+ u32 cr_poll_mask[ROGUE_FW_THREAD_NUM];
-+ u32 cr_poll_count[ROGUE_FW_THREAD_NUM];
-+ aligned_u64 start_idle_time;
-+
-+ /*
-+ * Non-volatile power monitoring results:
-+ * * static power (by default)
-+ * * energy count (PVR_POWER_MONITOR_DYNAMIC_ENERGY)
-+ */
-+ u32 pow_mon_estimate;
-+
-+#if defined(SUPPORT_ROGUE_FW_STATS_FRAMEWORK)
-+# define ROGUE_FWIF_STATS_FRAMEWORK_LINESIZE (8)
-+# define ROGUE_FWIF_STATS_FRAMEWORK_MAX \
-+ (2048 * ROGUE_FWIF_STATS_FRAMEWORK_LINESIZE)
-+ u32 fw_stats_buf[ROGUE_FWIF_STATS_FRAMEWORK_MAX] __aligned(8);
-+#endif
-+ u32 hwr_state_flags;
-+ u32 hwr_recovery_flags[PVR_FWIF_DM_MAX];
-+ /* Compatibility and other flags */
-+ u32 fw_sys_data_flags;
-+} __aligned(8);
-+
-+/* per-os firmware shared data */
-+struct rogue_fwif_osdata {
-+ /* Configuration flags from an OS */
-+ u32 fw_os_config_flags;
-+ /* Markers to signal that the host should perform a full sync check */
-+ u32 fw_sync_check_mark;
-+ u32 host_sync_check_mark;
-+
-+ u32 force_updates_requested;
-+ u8 slr_log_wp;
-+ struct rogue_fwif_slr_entry slr_log_first;
-+ struct rogue_fwif_slr_entry slr_log[PVR_SLR_LOG_ENTRIES];
-+ aligned_u64 last_forced_update_time;
-+
-+ /* Interrupt count from Threads > */
-+ volatile u32 interrupt_count[ROGUE_FW_THREAD_NUM];
-+ u32 kccb_cmds_executed;
-+ u32 power_sync_fw_addr;
-+ /* Compatibility and other flags */
-+ u32 fw_os_data_flags;
-+} __aligned(8);
-+
-+/* Firmware trace time-stamp field breakup */
-+
-+/* ROGUE_CR_TIMER register read (48 bits) value*/
-+#define ROGUE_FWT_TIMESTAMP_TIME_SHIFT (0U)
-+#define ROGUE_FWT_TIMESTAMP_TIME_CLRMSK (0xFFFF000000000000ull)
-+
-+/* Extra debug-info (16 bits) */
-+#define ROGUE_FWT_TIMESTAMP_DEBUG_INFO_SHIFT (48U)
-+#define ROGUE_FWT_TIMESTAMP_DEBUG_INFO_CLRMSK ~ROGUE_FWT_TIMESTAMP_TIME_CLRMSK
-+
-+/* Debug-info sub-fields */
-+/*
-+ * Bit 0: ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT bit from ROGUE_CR_EVENT_STATUS
-+ * register
-+ */
-+#define ROGUE_FWT_DEBUG_INFO_MMU_PAGE_FAULT_SHIFT (0U)
-+#define ROGUE_FWT_DEBUG_INFO_MMU_PAGE_FAULT_SET \
-+ BIT(ROGUE_FWT_DEBUG_INFO_MMU_PAGE_FAULT_SHIFT)
-+
-+/* Bit 1: ROGUE_CR_BIF_MMU_ENTRY_PENDING bit from ROGUE_CR_BIF_MMU_ENTRY register */
-+#define ROGUE_FWT_DEBUG_INFO_MMU_ENTRY_PENDING_SHIFT (1U)
-+#define ROGUE_FWT_DEBUG_INFO_MMU_ENTRY_PENDING_SET \
-+ BIT(ROGUE_FWT_DEBUG_INFO_MMU_ENTRY_PENDING_SHIFT)
-+
-+/* Bit 2: ROGUE_CR_SLAVE_EVENT register is non-zero */
-+#define ROGUE_FWT_DEBUG_INFO_SLAVE_EVENTS_SHIFT (2U)
-+#define ROGUE_FWT_DEBUG_INFO_SLAVE_EVENTS_SET \
-+ BIT(ROGUE_FWT_DEBUG_INFO_SLAVE_EVENTS_SHIFT)
-+
-+/* Bit 3-15: Unused bits */
-+
-+#define ROGUE_FWT_DEBUG_INFO_STR_MAXLEN 64
-+#define ROGUE_FWT_DEBUG_INFO_STR_PREPEND " (debug info: "
-+#define ROGUE_FWT_DEBUG_INFO_STR_APPEND ")"
-+
-+/*
-+ * Table of debug info sub-field's masks and corresponding message strings
-+ * to be appended to firmware trace
-+ *
-+ * Mask : 16 bit mask to be applied to debug-info field
-+ * String : debug info message string
-+ */
-+
-+#define ROGUE_FWT_DEBUG_INFO_MSKSTRLIST \
-+ /*Mask, String*/ \
-+ X(ROGUE_FWT_DEBUG_INFO_MMU_PAGE_FAULT_SET, "mmu pf") \
-+ X(ROGUE_FWT_DEBUG_INFO_MMU_ENTRY_PENDING_SET, "mmu pending") \
-+ X(ROGUE_FWT_DEBUG_INFO_SLAVE_EVENTS_SET, "slave events")
-+
-+/*
-+ ******************************************************************************
-+ * HWR Data
-+ ******************************************************************************
-+ */
-+enum rogue_hwrtype {
-+ ROGUE_HWRTYPE_UNKNOWNFAILURE = 0,
-+ ROGUE_HWRTYPE_OVERRUN = 1,
-+ ROGUE_HWRTYPE_POLLFAILURE = 2,
-+ ROGUE_HWRTYPE_BIF0FAULT = 3,
-+ ROGUE_HWRTYPE_BIF1FAULT = 4,
-+ ROGUE_HWRTYPE_TEXASBIF0FAULT = 5,
-+ ROGUE_HWRTYPE_MMUFAULT = 6,
-+ ROGUE_HWRTYPE_MMUMETAFAULT = 7,
-+ ROGUE_HWRTYPE_MIPSTLBFAULT = 8,
-+ ROGUE_HWRTYPE_ECCFAULT = 9,
-+};
-+
-+#define ROGUE_FWIF_HWRTYPE_BIF_BANK_GET(hwr_type) \
-+ (((hwr_type) == ROGUE_HWRTYPE_BIF0FAULT) ? 0 : 1)
-+
-+#define ROGUE_FWIF_HWRTYPE_PAGE_FAULT_GET(hwr_type) \
-+ ((((hwr_type) == ROGUE_HWRTYPE_BIF0FAULT) || \
-+ ((hwr_type) == ROGUE_HWRTYPE_BIF1FAULT) || \
-+ ((hwr_type) == ROGUE_HWRTYPE_TEXASBIF0FAULT) || \
-+ ((hwr_type) == ROGUE_HWRTYPE_MMUFAULT) || \
-+ ((hwr_type) == ROGUE_HWRTYPE_MMUMETAFAULT) || \
-+ ((hwr_type) == ROGUE_HWRTYPE_MIPSTLBFAULT)) \
-+ ? true \
-+ : false)
-+
-+struct rogue_bifinfo {
-+ aligned_u64 bif_req_status;
-+ aligned_u64 bif_mmu_status;
-+ aligned_u64 pc_address; /* phys address of the page catalogue */
-+ aligned_u64 reserved;
-+};
-+
-+struct rogue_eccinfo {
-+ u32 fault_gpu;
-+};
-+
-+struct rogue_mmuinfo {
-+ aligned_u64 mmu_status;
-+ aligned_u64 pc_address; /* phys address of the page catalogue */
-+ aligned_u64 reserved;
-+};
-+
-+struct rogue_pollinfo {
-+ u32 thread_num;
-+ u32 cr_poll_addr;
-+ u32 cr_poll_mask;
-+ u32 cr_poll_last_value;
-+ aligned_u64 reserved;
-+} __aligned(8);
-+
-+struct rogue_tlbinfo {
-+ u32 bad_addr;
-+ u32 entry_lo;
-+} __aligned(8);
-+
-+struct rogue_hwrinfo {
-+ union {
-+ struct rogue_bifinfo bif_info;
-+ struct rogue_mmuinfo mmu_info;
-+ struct rogue_pollinfo poll_info;
-+ struct rogue_tlbinfo tlb_info;
-+ struct rogue_eccinfo ecc_info;
-+ } hwr_data;
-+
-+ aligned_u64 cr_timer;
-+ aligned_u64 os_timer;
-+ u32 frame_num;
-+ u32 pid;
-+ u32 active_hwrt_data;
-+ u32 hwr_number;
-+ u32 event_status;
-+ u32 hwr_recovery_flags;
-+ enum rogue_hwrtype hwr_type;
-+ u32 dm;
-+ u32 core_id;
-+ aligned_u64 cr_time_of_kick;
-+ aligned_u64 cr_time_hw_reset_start;
-+ aligned_u64 cr_time_hw_reset_finish;
-+ aligned_u64 cr_time_freelist_ready;
-+ aligned_u64 reserved[2];
-+} __aligned(8);
-+
-+/* Number of first HWR logs recorded (never overwritten by newer logs) */
-+#define ROGUE_FWIF_HWINFO_MAX_FIRST 8U
-+/* Number of latest HWR logs (older logs are overwritten by newer logs) */
-+#define ROGUE_FWIF_HWINFO_MAX_LAST 8U
-+/* Total number of HWR logs stored in a buffer */
-+#define ROGUE_FWIF_HWINFO_MAX \
-+ (ROGUE_FWIF_HWINFO_MAX_FIRST + ROGUE_FWIF_HWINFO_MAX_LAST)
-+/* Index of the last log in the HWR log buffer */
-+#define ROGUE_FWIF_HWINFO_LAST_INDEX (ROGUE_FWIF_HWINFO_MAX - 1U)
-+
-+struct rogue_fwif_hwrinfobuf {
-+ struct rogue_hwrinfo hwr_info[ROGUE_FWIF_HWINFO_MAX];
-+ u32 hwr_counter;
-+ u32 write_index;
-+ u32 dd_req_count;
-+ u32 hwr_info_buf_flags; /* Compatibility and other flags */
-+ u32 hwr_dm_locked_up_count[PVR_FWIF_DM_MAX];
-+ u32 hwr_dm_overran_count[PVR_FWIF_DM_MAX];
-+ u32 hwr_dm_recovered_count[PVR_FWIF_DM_MAX];
-+ u32 hwr_dm_false_detect_count[PVR_FWIF_DM_MAX];
-+} __aligned(8);
-+
-+enum rogue_activepm_conf {
-+ ROGUE_ACTIVEPM_FORCE_OFF = 0,
-+ ROGUE_ACTIVEPM_FORCE_ON = 1,
-+ ROGUE_ACTIVEPM_DEFAULT = 2
-+};
-+
-+enum rogue_rd_power_island_conf {
-+ ROGUE_RD_POWER_ISLAND_FORCE_OFF = 0,
-+ ROGUE_RD_POWER_ISLAND_FORCE_ON = 1,
-+ ROGUE_RD_POWER_ISLAND_DEFAULT = 2
-+};
-+
-+/*
-+ ******************************************************************************
-+ * Querying DM state
-+ ******************************************************************************
-+ */
-+
-+struct rogue_fw_register_list {
-+ /* Register number */
-+ u16 reg_num;
-+ /* Indirect register number (or 0 if not used) */
-+ u16 indirect_reg_num;
-+ /* Start value for indirect register */
-+ u16 indirect_start_val;
-+ /* End value for indirect register */
-+ u16 indirect_end_val;
-+};
-+
-+#define ROGUE_FWIF_CTXSWITCH_PROFILE_FAST_EN (1)
-+#define ROGUE_FWIF_CTXSWITCH_PROFILE_MEDIUM_EN (2)
-+#define ROGUE_FWIF_CTXSWITCH_PROFILE_SLOW_EN (3)
-+#define ROGUE_FWIF_CTXSWITCH_PROFILE_NODELAY_EN (4)
-+
-+#define ROGUE_FWIF_CDM_ARBITRATION_TASK_DEMAND_EN (1)
-+#define ROGUE_FWIF_CDM_ARBITRATION_ROUND_ROBIN_EN (2)
-+
-+#define ROGUE_FWIF_ISP_SCHEDMODE_VER1_IPP (1)
-+#define ROGUE_FWIF_ISP_SCHEDMODE_VER2_ISP (2)
-+/*
-+ ******************************************************************************
-+ * ROGUE firmware Init Config Data
-+ ******************************************************************************
-+ */
-+
-+/* Flag definitions affecting the firmware globally */
-+#define ROGUE_FWIF_INICFG_CTXSWITCH_MODE_RAND BIT(0)
-+#define ROGUE_FWIF_INICFG_CTXSWITCH_SRESET_EN BIT(1)
-+#define ROGUE_FWIF_INICFG_HWPERF_EN BIT(2)
-+#define ROGUE_FWIF_INICFG_DM_KILL_MODE_RAND_EN BIT(3)
-+#define ROGUE_FWIF_INICFG_POW_RASCALDUST BIT(4)
-+/* Bit 5 is reserved. */
-+#define ROGUE_FWIF_INICFG_FBCDC_V3_1_EN BIT(6)
-+#define ROGUE_FWIF_INICFG_CHECK_MLIST_EN BIT(7)
-+#define ROGUE_FWIF_INICFG_DISABLE_CLKGATING_EN BIT(8)
-+#define ROGUE_FWIF_INICFG_POLL_COUNTERS_EN BIT(9)
-+#define ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT (10)
-+#define ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_INDEX \
-+ (ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX \
-+ << ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
-+#define ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE \
-+ (ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE \
-+ << ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
-+#define ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_LIST \
-+ (ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST \
-+ << ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT)
-+#define ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_MASK \
-+ (ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_INDEX | \
-+ ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE | \
-+ ROGUE_FWIF_INICFG_VDM_CTX_STORE_MODE_LIST)
-+#define ROGUE_FWIF_INICFG_REGCONFIG_EN BIT(12)
-+#define ROGUE_FWIF_INICFG_ASSERT_ON_OUTOFMEMORY BIT(13)
-+#define ROGUE_FWIF_INICFG_HWP_DISABLE_FILTER BIT(14)
-+#define ROGUE_FWIF_INICFG_CUSTOM_PERF_TIMER_EN BIT(15)
-+#define ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_SHIFT (16)
-+#define ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_FAST \
-+ (ROGUE_FWIF_CTXSWITCH_PROFILE_FAST_EN \
-+ << ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
-+#define ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_MEDIUM \
-+ (ROGUE_FWIF_CTXSWITCH_PROFILE_MEDIUM_EN \
-+ << ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
-+#define ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_SLOW \
-+ (ROGUE_FWIF_CTXSWITCH_PROFILE_SLOW_EN \
-+ << ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
-+#define ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_NODELAY \
-+ (ROGUE_FWIF_CTXSWITCH_PROFILE_NODELAY_EN \
-+ << ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
-+#define ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_MASK \
-+ (7 << ROGUE_FWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
-+#define ROGUE_FWIF_INICFG_DISABLE_DM_OVERLAP BIT(19)
-+#define ROGUE_FWIF_INICFG_ASSERT_ON_HWR_TRIGGER BIT(20)
-+#define ROGUE_FWIF_INICFG_FABRIC_COHERENCY_ENABLED BIT(21)
-+#define ROGUE_FWIF_INICFG_VALIDATE_IRQ BIT(22)
-+#define ROGUE_FWIF_INICFG_DISABLE_PDP_EN BIT(23)
-+#define ROGUE_FWIF_INICFG_SPU_POWER_STATE_MASK_CHANGE_EN BIT(24)
-+#define ROGUE_FWIF_INICFG_WORKEST BIT(25)
-+#define ROGUE_FWIF_INICFG_PDVFS BIT(26)
-+#define ROGUE_FWIF_INICFG_CDM_ARBITRATION_SHIFT (27)
-+#define ROGUE_FWIF_INICFG_CDM_ARBITRATION_TASK_DEMAND \
-+ (ROGUE_FWIF_CDM_ARBITRATION_TASK_DEMAND_EN \
-+ << ROGUE_FWIF_INICFG_CDM_ARBITRATION_SHIFT)
-+#define ROGUE_FWIF_INICFG_CDM_ARBITRATION_ROUND_ROBIN \
-+ (ROGUE_FWIF_CDM_ARBITRATION_ROUND_ROBIN_EN \
-+ << ROGUE_FWIF_INICFG_CDM_ARBITRATION_SHIFT)
-+#define ROGUE_FWIF_INICFG_CDM_ARBITRATION_MASK \
-+ (3 << ROGUE_FWIF_INICFG_CDM_ARBITRATION_SHIFT)
-+#define ROGUE_FWIF_INICFG_ISPSCHEDMODE_SHIFT (29)
-+#define ROGUE_FWIF_INICFG_ISPSCHEDMODE_NONE (0)
-+#define ROGUE_FWIF_INICFG_ISPSCHEDMODE_VER1_IPP \
-+ (ROGUE_FWIF_ISP_SCHEDMODE_VER1_IPP \
-+ << ROGUE_FWIF_INICFG_ISPSCHEDMODE_SHIFT)
-+#define ROGUE_FWIF_INICFG_ISPSCHEDMODE_VER2_ISP \
-+ (ROGUE_FWIF_ISP_SCHEDMODE_VER2_ISP \
-+ << ROGUE_FWIF_INICFG_ISPSCHEDMODE_SHIFT)
-+#define ROGUE_FWIF_INICFG_ISPSCHEDMODE_MASK \
-+ (ROGUE_FWIF_INICFG_ISPSCHEDMODE_VER1_IPP | \
-+ ROGUE_FWIF_INICFG_ISPSCHEDMODE_VER2_ISP)
-+#define ROGUE_FWIF_INICFG_VALIDATE_SOCUSC_TIMER BIT(31)
-+
-+#define ROGUE_FWIF_INICFG_ALL (0xFFFFFFFFU)
-+
-+/* Extended Flag definitions affecting the firmware globally */
-+#define ROGUE_FWIF_INICFG_EXT_ALL (0x0U)
-+
-+/* Flag definitions affecting only workloads submitted by a particular OS */
-+#define ROGUE_FWIF_INICFG_OS_CTXSWITCH_TDM_EN BIT(0)
-+#define ROGUE_FWIF_INICFG_OS_CTXSWITCH_GEOM_EN BIT(1)
-+#define ROGUE_FWIF_INICFG_OS_CTXSWITCH_FRAG_EN BIT(2)
-+#define ROGUE_FWIF_INICFG_OS_CTXSWITCH_CDM_EN BIT(3)
-+
-+#define ROGUE_FWIF_INICFG_OS_LOW_PRIO_CS_TDM BIT(4)
-+#define ROGUE_FWIF_INICFG_OS_LOW_PRIO_CS_GEOM BIT(5)
-+#define ROGUE_FWIF_INICFG_OS_LOW_PRIO_CS_FRAG BIT(6)
-+#define ROGUE_FWIF_INICFG_OS_LOW_PRIO_CS_CDM BIT(7)
-+
-+#define ROGUE_FWIF_INICFG_OS_ALL (0xFF)
-+
-+#define ROGUE_FWIF_INICFG_SYS_CTXSWITCH_CLRMSK \
-+ ~(ROGUE_FWIF_INICFG_CTXSWITCH_MODE_RAND | \
-+ ROGUE_FWIF_INICFG_CTXSWITCH_SRESET_EN)
-+
-+#define ROGUE_FWIF_INICFG_OS_CTXSWITCH_DM_ALL \
-+ (ROGUE_FWIF_INICFG_OS_CTXSWITCH_TDM_EN | \
-+ ROGUE_FWIF_INICFG_OS_CTXSWITCH_GEOM_EN | \
-+ ROGUE_FWIF_INICFG_OS_CTXSWITCH_FRAG_EN | \
-+ ROGUE_FWIF_INICFG_OS_CTXSWITCH_CDM_EN)
-+
-+#define ROGUE_FWIF_INICFG_OS_CTXSWITCH_CLRMSK \
-+ ~(ROGUE_FWIF_INICFG_OS_CTXSWITCH_DM_ALL)
-+
-+#define ROGUE_FWIF_FILTCFG_TRUNCATE_HALF BIT(3)
-+#define ROGUE_FWIF_FILTCFG_TRUNCATE_INT BIT(2)
-+#define ROGUE_FWIF_FILTCFG_NEW_FILTER_MODE BIT(1)
-+
-+#if defined(ROGUE_FW_IRQ_OS_COUNTERS)
-+/* clang-format off */
-+/*
-+ * Unused registers re-purposed for storing counters of the Firmware's
-+ * interrupts for each OS
-+ */
-+# define IRQ_COUNTER_STORAGE_REGS \
-+ 0x2028U, /* ROGUE_CR_PM_TA_MMU_FSTACK */ \
-+ 0x2050U, /* ROGUE_CR_PM_3D_MMU_FSTACK */ \
-+ 0x2030U, /* ROGUE_CR_PM_START_OF_MMU_TACONTEXT*/ \
-+ 0x2058U, /* ROGUE_CR_PM_START_OF_MMU_3DCONTEXT*/ \
-+ 0x2058U, /* ROGUE_CR_PM_START_OF_MMU_3DCONTEXT*/ \
-+ 0x2058U, /* ROGUE_CR_PM_START_OF_MMU_3DCONTEXT*/ \
-+ 0x2058U, /* ROGUE_CR_PM_START_OF_MMU_3DCONTEXT*/ \
-+ 0x2058U, /* ROGUE_CR_PM_START_OF_MMU_3DCONTEXT*/
-+/* clang-format on */
-+#endif
-+
-+struct rogue_fwif_dllist_node {
-+ u32 p;
-+ u32 n;
-+};
-+
-+/*
-+ * This number is used to represent an invalid page catalogue physical address
-+ */
-+#define ROGUE_FWIF_INVALID_PC_PHYADDR 0xFFFFFFFFFFFFFFFFLLU
-+
-+/* This number is used to represent unallocated page catalog base register */
-+#define ROGUE_FW_BIF_INVALID_PCREG 0xFFFFFFFFU
-+
-+/* Firmware memory context. */
-+struct rogue_fwif_fwmemcontext {
-+ /* device physical address of context's page catalogue */
-+ aligned_u64 pc_dev_paddr;
-+ /*
-+ * associated page catalog base register (ROGUE_FW_BIF_INVALID_PCREG ==
-+ * unallocated)
-+ */
-+ u32 page_cat_base_reg_id;
-+ /* breakpoint address */
-+ u32 breakpoint_addr;
-+ /* breakpoint handler address */
-+ u32 bp_handler_addr;
-+ /* DM and enable control for BP */
-+ u32 breakpoint_ctl;
-+ /* Compatibility and other flags */
-+ u32 fw_mem_ctx_flags;
-+} __aligned(8);
-+
-+/*
-+ * FW context state flags
-+ */
-+#define ROGUE_FWIF_CONTEXT_FLAGS_NEED_RESUME (0x00000001U)
-+#define ROGUE_FWIF_CONTEXT_FLAGS_MC_NEED_RESUME_MASKFULL (0x000000FFU)
-+#define ROGUE_FWIF_CONTEXT_FLAGS_TDM_HEADER_STALE (0x00000100U)
-+
-+/*
-+ * Fast scale blit renders can be divided into smaller slices. The maximum
-+ * screen size is 8192x8192 pixels or 256x256 tiles. The blit is sliced
-+ * into 512x512 pixel blits or 16x16 tiles. Therefore, there are at most
-+ * 256 slices of 16x16 tiles, which means we need 8bits to count up to
-+ * which slice we have blitted so far.
-+ */
-+#define ROGUE_FWIF_CONTEXT_SLICE_BLIT_X_MASK (0x00000F00)
-+#define ROGUE_FWIF_CONTEXT_SLICE_BLIT_X_SHIFT (8)
-+#define ROGUE_FWIF_CONTEXT_SLICE_BLIT_Y_MASK (0x0000F000)
-+#define ROGUE_FWIF_CONTEXT_SLICE_BLIT_Y_SHIFT (12)
-+
-+/*
-+ * FW-accessible TA state which must be written out to memory on context store
-+ */
-+struct rogue_fwif_geom_ctx_state {
-+ /* To store in mid-TA */
-+ aligned_u64 geom_reg_vdm_call_stack_pointer;
-+ /* Initial value (in case is 'lost' due to a lock-up */
-+ aligned_u64 geom_reg_vdm_call_stack_pointer_init;
-+ aligned_u64 geom_reg_vdm_batch;
-+ aligned_u64 geom_reg_vbs_so_prim0;
-+ aligned_u64 geom_reg_vbs_so_prim1;
-+ aligned_u64 geom_reg_vbs_so_prim2;
-+ aligned_u64 geom_reg_vbs_so_prim3;
-+ s16 geom_current_idx;
-+} __aligned(8);
-+
-+/*
-+ * FW-accessible ISP state which must be written out to memory on context store
-+ */
-+struct rogue_fwif_frag_ctx_state {
-+ aligned_u64 frag_reg_pm_deallocated_mask_status;
-+ aligned_u64 frag_reg_dm_pds_mtilefree_status;
-+ /* Compatibility and other flags */
-+ u32 ctx_state_flags;
-+ /*
-+ * frag_reg_isp_store should be the last element of the structure as this
-+ * is an array whose size is determined at runtime after detecting the
-+ * ROGUE core
-+ */
-+ u32 frag_reg_isp_store[];
-+} __aligned(8);
-+
-+#define ROGUE_FWIF_CTX_USING_BUFFER_A (0)
-+#define ROGUE_FWIF_CTX_USING_BUFFER_B (1U)
-+
-+struct rogue_fwif_compute_ctx_state {
-+ u32 ctx_state_flags; /* Target buffer and other flags */
-+};
-+
-+struct rogue_fwif_fwcommoncontext {
-+ /* CCB details for this firmware context */
-+ u32 ccbctl_fw_addr; /* CCB control */
-+ u32 ccb_fw_addr; /* CCB base */
-+ struct rogue_fwif_dma_addr ccb_meta_dma_addr;
-+
-+ /* List entry for the waiting list */
-+ struct rogue_fwif_dllist_node waiting_node __aligned(8);
-+ /* List entry for the run list */
-+ struct rogue_fwif_dllist_node run_node __aligned(8);
-+ /* UFO that last failed (or NULL) */
-+ struct rogue_fwif_ufo last_failed_ufo;
-+
-+ /* Memory context */
-+ u32 fw_mem_context_fw_addr;
-+
-+ /* Context suspend state */
-+ /* geom/frag context suspend state, read/written by FW */
-+ u32 context_state_addr __aligned(8);
-+
-+ /* Framework state */
-+ /* Register updates for Framework */
-+ u32 rf_cmd_addr __aligned(8);
-+
-+ /* Flags e.g. for context switching */
-+ u32 fw_com_ctx_flags;
-+ u32 priority;
-+ u32 priority_seq_num;
-+
-+ /* References to the host side originators */
-+ /* the Server Common Context */
-+ u32 server_common_context_id;
-+ /* associated process ID */
-+ u32 pid;
-+
-+ /* Statistic updates waiting to be passed back to the host... */
-+ /* True when some stats are pending */
-+ bool stats_pending __aligned(4);
-+ /* Number of stores on this context since last update */
-+ s32 stats_num_stores;
-+ /* Number of OOMs on this context since last update */
-+ s32 stats_num_out_of_memory;
-+ /* Number of PRs on this context since last update */
-+ s32 stats_num_partial_renders;
-+ /* Data Master type */
-+ u32 dm;
-+ /* Device Virtual Address of the signal the context is waiting on */
-+ aligned_u64 wait_signal_address;
-+ /* List entry for the wait-signal list */
-+ struct rogue_fwif_dllist_node wait_signal_node __aligned(8);
-+ /* List entry for the buffer stalled list */
-+ struct rogue_fwif_dllist_node buf_stalled_node __aligned(8);
-+ /* Address of the circular buffer queue pointers */
-+ aligned_u64 cbuf_queue_ctrl_addr;
-+
-+ aligned_u64 robustness_address;
-+ /* Max HWR deadline limit in ms */
-+ u32 max_deadline_ms;
-+ /* Following HWR circular buffer read-offset needs resetting */
-+ bool read_offset_needs_reset __aligned(4);
-+} __aligned(8);
-+
-+/* Firmware render context. */
-+struct rogue_fwif_fwrendercontext {
-+ /* Geometry firmware context. */
-+ struct rogue_fwif_fwcommoncontext geom_context;
-+ /* Fragment firmware context. */
-+ struct rogue_fwif_fwcommoncontext frag_context;
-+
-+ struct rogue_fwif_static_rendercontext_state static_render_context_state;
-+
-+ /* Number of commands submitted to the WorkEst FW CCB */
-+ u32 work_est_ccb_submitted;
-+
-+ /* Compatibility and other flags */
-+ u32 fw_render_ctx_flags;
-+} __aligned(8);
-+
-+/* Firmware compute context. */
-+struct rogue_fwif_fwcomputecontext {
-+ /* Firmware context for the CDM */
-+ struct rogue_fwif_fwcommoncontext cdm_context;
-+
-+ struct rogue_fwif_static_computecontext_state
-+ static_compute_context_state;
-+
-+ /* Number of commands submitted to the WorkEst FW CCB */
-+ u32 work_est_ccb_submitted;
-+
-+ /* Compatibility and other flags */
-+ u32 compute_ctx_flags;
-+
-+ u32 kz_state;
-+ u32 kz_checksum;
-+ u32 core_mask_a;
-+ u32 core_mask_b;
-+} __aligned(8);
-+
-+/* Firmware TDM context. */
-+struct rogue_fwif_fwtdmcontext {
-+ /* Firmware context for the TDM */
-+ struct rogue_fwif_fwcommoncontext tdm_context;
-+
-+ /* Number of commands submitted to the WorkEst FW CCB */
-+ u32 work_est_ccb_submitted;
-+} __aligned(8);
-+
-+/* Firmware TQ3D context. */
-+struct rogue_fwif_fwtransfercontext {
-+ /* Firmware context for TQ3D. */
-+ struct rogue_fwif_fwcommoncontext tq_context;
-+};
-+
-+/*
-+ ******************************************************************************
-+ * Defines for CMD_TYPE corruption detection and forward compatibility check
-+ ******************************************************************************
-+ */
-+
-+/*
-+ * CMD_TYPE 32bit contains:
-+ * 31:16 Reserved for magic value to detect corruption (16 bits)
-+ * 15 Reserved for ROGUE_CCB_TYPE_TASK (1 bit)
-+ * 14:0 Bits available for CMD_TYPEs (15 bits)
-+ */
-+
-+/* Magic value to detect corruption */
-+#define ROGUE_CMD_MAGIC_DWORD (0x2ABC)
-+#define ROGUE_CMD_MAGIC_DWORD_MASK (0xFFFF0000U)
-+#define ROGUE_CMD_MAGIC_DWORD_SHIFT (16U)
-+#define ROGUE_CMD_MAGIC_DWORD_SHIFTED \
-+ (ROGUE_CMD_MAGIC_DWORD << ROGUE_CMD_MAGIC_DWORD_SHIFT)
-+
-+/* Kernel CCB control for ROGUE */
-+struct rogue_fwif_ccb_ctl {
-+ /* write offset into array of commands (MUST be aligned to 16 bytes!) */
-+ volatile u32 write_offset;
-+ /* read offset into array of commands */
-+ volatile u32 read_offset;
-+ /* Offset wrapping mask (Total capacity of the CCB - 1) */
-+ u32 wrap_mask;
-+ /* size of each command in bytes */
-+ u32 cmd_size;
-+} __aligned(8);
-+
-+/* Kernel CCB command structure for ROGUE */
-+
-+#define ROGUE_FWIF_MMUCACHEDATA_FLAGS_PT (0x1U) /* MMU_CTRL_INVAL_PT_EN */
-+#define ROGUE_FWIF_MMUCACHEDATA_FLAGS_PD (0x2U) /* MMU_CTRL_INVAL_PD_EN */
-+#define ROGUE_FWIF_MMUCACHEDATA_FLAGS_PC (0x4U) /* MMU_CTRL_INVAL_PC_EN */
-+
-+/*
-+ * can't use PM_TLB0 bit from BIFPM_CTRL reg because it collides with PT
-+ * bit from BIF_CTRL reg
-+ */
-+#define ROGUE_FWIF_MMUCACHEDATA_FLAGS_PMTLB (0x10)
-+/* BIF_CTRL_INVAL_TLB1_EN */
-+#define ROGUE_FWIF_MMUCACHEDATA_FLAGS_TLB \
-+ (ROGUE_FWIF_MMUCACHEDATA_FLAGS_PMTLB | 0x8)
-+/* MMU_CTRL_INVAL_ALL_CONTEXTS_EN */
-+#define ROGUE_FWIF_MMUCACHEDATA_FLAGS_CTX_ALL (0x800)
-+
-+/* indicates FW should interrupt the host */
-+#define ROGUE_FWIF_MMUCACHEDATA_FLAGS_INTERRUPT (0x4000000U)
-+
-+struct rogue_fwif_mmucachedata {
-+ u32 cache_flags;
-+ u32 mmu_cache_sync_fw_addr;
-+ u32 mmu_cache_sync_update_value;
-+};
-+
-+#define ROGUE_FWIF_BPDATA_FLAGS_ENABLE BIT(0)
-+#define ROGUE_FWIF_BPDATA_FLAGS_WRITE BIT(1)
-+#define ROGUE_FWIF_BPDATA_FLAGS_CTL BIT(2)
-+#define ROGUE_FWIF_BPDATA_FLAGS_REGS BIT(3)
-+
-+struct rogue_fwif_bpdata {
-+ /* Memory context */
-+ u32 fw_mem_context_fw_addr;
-+ /* Breakpoint address */
-+ u32 bp_addr;
-+ /* Breakpoint handler */
-+ u32 bp_handler_addr;
-+ /* Breakpoint control */
-+ u32 bp_dm;
-+ u32 bp_data_flags;
-+ /* Number of temporary registers to overallocate */
-+ u32 temp_regs;
-+ /* Number of shared registers to overallocate */
-+ u32 shared_regs;
-+ /* DM associated with the breakpoint */
-+ u32 dm;
-+};
-+
-+#define ROGUE_FWIF_KCCB_CMD_KICK_DATA_MAX_NUM_CLEANUP_CTLS \
-+ (ROGUE_FWIF_PRBUFFER_MAXSUPPORTED + 1U) /* +1 is RTDATASET cleanup */
-+
-+struct rogue_fwif_kccb_cmd_kick_data {
-+ /* address of the firmware context */
-+ u32 context_fw_addr;
-+ /* Client CCB woff update */
-+ u32 client_woff_update;
-+ /* Client CCB wrap mask update after CCCB growth */
-+ u32 client_wrap_mask_update;
-+ /* number of CleanupCtl pointers attached */
-+ u32 num_cleanup_ctl;
-+ /* CleanupCtl structures associated with command */
-+ u32 cleanup_ctl_fw_addr
-+ [ROGUE_FWIF_KCCB_CMD_KICK_DATA_MAX_NUM_CLEANUP_CTLS];
-+ /*
-+ * offset to the CmdHeader which houses the workload estimation kick
-+ * data.
-+ */
-+ u32 work_est_cmd_header_offset;
-+};
-+
-+struct rogue_fwif_kccb_cmd_combined_geom_frag_kick_data {
-+ struct rogue_fwif_kccb_cmd_kick_data geom_cmd_kick_data;
-+ struct rogue_fwif_kccb_cmd_kick_data frag_cmd_kick_data;
-+};
-+
-+struct rogue_fwif_kccb_cmd_force_update_data {
-+ /* address of the firmware context */
-+ u32 context_fw_addr;
-+ /* Client CCB fence offset */
-+ u32 ccb_fence_offset;
-+};
-+
-+struct rogue_fwif_kccb_cmd_phr_cfg_data {
-+ /* Variable containing PHR configuration values */
-+ u32 phr_mode;
-+};
-+
-+#define ROGUEIF_PHR_MODE_OFF (0UL)
-+#define ROGUEIF_PHR_MODE_RD_RESET (1UL)
-+#define ROGUEIF_PHR_MODE_FULL_RESET (2UL)
-+
-+struct rogue_fwif_kccb_cmd_wdg_cfg_data {
-+ /* Variable containing the requested watchdog period in microseconds */
-+ u32 wdg_period_us;
-+};
-+
-+enum rogue_fwif_cleanup_type {
-+ /* FW common context cleanup */
-+ ROGUE_FWIF_CLEANUP_FWCOMMONCONTEXT,
-+ /* FW HW RT data cleanup */
-+ ROGUE_FWIF_CLEANUP_HWRTDATA,
-+ /* FW freelist cleanup */
-+ ROGUE_FWIF_CLEANUP_FREELIST,
-+ /* FW ZS Buffer cleanup */
-+ ROGUE_FWIF_CLEANUP_ZSBUFFER,
-+};
-+
-+struct rogue_fwif_cleanup_request {
-+ /* Cleanup type */
-+ enum rogue_fwif_cleanup_type cleanup_type;
-+ union {
-+ /* FW common context to cleanup */
-+ u32 context_fw_addr;
-+ /* HW RT to cleanup */
-+ u32 hwrt_data_fw_addr;
-+ /* Freelist to cleanup */
-+ u32 freelist_fw_addr;
-+ /* ZS Buffer to cleanup */
-+ u32 zs_buffer_fw_addr;
-+ } cleanup_data;
-+};
-+
-+enum rogue_fwif_power_type {
-+ ROGUE_FWIF_POW_OFF_REQ = 1,
-+ ROGUE_FWIF_POW_FORCED_IDLE_REQ,
-+ ROGUE_FWIF_POW_NUM_UNITS_CHANGE,
-+ ROGUE_FWIF_POW_APM_LATENCY_CHANGE
-+};
-+
-+enum rogue_fwif_power_force_idle_type {
-+ ROGUE_FWIF_POWER_FORCE_IDLE = 1,
-+ ROGUE_FWIF_POWER_CANCEL_FORCED_IDLE,
-+ ROGUE_FWIF_POWER_HOST_TIMEOUT,
-+};
-+
-+struct rogue_fwif_power_request {
-+ /* Type of power request */
-+ enum rogue_fwif_power_type pow_type;
-+ union {
-+ /* Number of active Dusts */
-+ u32 num_of_dusts;
-+ /* If the operation is mandatory */
-+ bool forced __aligned(4);
-+ /*
-+ * Type of Request. Consolidating Force Idle, Cancel Forced
-+ * Idle, Host Timeout
-+ */
-+ enum rogue_fwif_power_force_idle_type pow_request_type;
-+ /* Number of milliseconds to set APM latency */
-+ u32 active_pm_latency_ms;
-+ } power_req_data;
-+};
-+
-+struct rogue_fwif_slcflushinvaldata {
-+ /* Context to fence on (only useful when bDMContext == TRUE) */
-+ u32 context_fw_addr;
-+ /* Invalidate the cache as well as flushing */
-+ bool inval __aligned(4);
-+ /* The data to flush/invalidate belongs to a specific DM context */
-+ bool dm_context __aligned(4);
-+};
-+
-+struct rogue_fwif_hcs_ctl {
-+ /* New number of milliseconds C/S is allowed to last */
-+ u32 hcs_deadling_ms;
-+};
-+
-+enum rogue_fwif_hwperf_update_config {
-+ ROGUE_FWIF_HWPERF_CTRL_TOGGLE = 0,
-+ ROGUE_FWIF_HWPERF_CTRL_SET = 1,
-+ ROGUE_FWIF_HWPERF_CTRL_EMIT_FEATURES_EV = 2
-+};
-+
-+struct rogue_fwif_hwperf_ctrl {
-+ enum rogue_fwif_hwperf_update_config opcode; /* Control operation code */
-+ aligned_u64 mask; /* Mask of events to toggle */
-+};
-+
-+struct rogue_fwif_hwperf_config_enable_blks {
-+ /* Number of ROGUE_HWPERF_CONFIG_CNTBLK in the array */
-+ u32 num_blocks;
-+ /* Address of the ROGUE_HWPERF_CONFIG_CNTBLK array */
-+ u32 block_configs_fw_addr;
-+};
-+
-+struct rogue_fwif_coreclkspeedchange_data {
-+ u32 new_clock_speed; /* New clock speed */
-+};
-+
-+#define ROGUE_FWIF_HWPERF_CTRL_BLKS_MAX 16
-+
-+struct rogue_fwif_hwperf_ctrl_blks {
-+ bool enable __aligned(4);
-+ /* Number of block IDs in the array */
-+ u32 num_blocks;
-+ /* Array of ROGUE_HWPERF_CNTBLK_ID values */
-+ u16 block_ids[ROGUE_FWIF_HWPERF_CTRL_BLKS_MAX];
-+};
-+
-+struct rogue_fwif_hwperf_select_custom_cntrs {
-+ u16 custom_block;
-+ u16 num_counters;
-+ u32 custom_counter_ids_fw_addr;
-+};
-+
-+struct rogue_fwif_zsbuffer_backing_data {
-+ u32 zs_buffer_fw_addr; /* ZS-Buffer FW address */
-+ bool done __aligned(4); /* action backing/unbacking succeeded */
-+};
-+
-+struct rogue_fwif_freelist_gs_data {
-+ /* Freelist FW address */
-+ u32 freelist_fw_addr;
-+ /* Amount of the Freelist change */
-+ u32 delta_pages;
-+ /* New amount of pages on the freelist (including ready pages) */
-+ u32 new_pages;
-+ /* Number of ready pages to be held in reserve until OOM */
-+ u32 ready_pages;
-+};
-+
-+#define ROGUE_FWIF_MAX_FREELISTS_TO_RECONSTRUCT \
-+ (MAX_HW_GEOM_FRAG_CONTEXTS * ROGUE_FW_MAX_FREELISTS * 2U)
-+#define ROGUE_FWIF_FREELISTS_RECONSTRUCTION_FAILED_FLAG 0x80000000U
-+
-+struct rogue_fwif_freelists_reconstruction_data {
-+ u32 freelist_count;
-+ u32 freelist_ids[ROGUE_FWIF_MAX_FREELISTS_TO_RECONSTRUCT];
-+};
-+
-+struct rogue_fwif_signal_update_data {
-+ /* device virtual address of the updated signal */
-+ aligned_u64 dev_signal_address;
-+ /* Memory context */
-+ u32 fw_mem_context_fw_addr;
-+} __aligned(8);
-+
-+struct rogue_fwif_write_offset_update_data {
-+ /*
-+ * Context to that may need to be resumed following write offset update
-+ */
-+ u32 context_fw_addr;
-+} __aligned(8);
-+
-+/*
-+ ******************************************************************************
-+ * Proactive DVFS Structures
-+ ******************************************************************************
-+ */
-+#define NUM_OPP_VALUES 16
-+
-+struct pdvfs_opp {
-+ u32 volt; /* V */
-+ u32 freq; /* Hz */
-+} __aligned(8);
-+
-+struct rogue_fwif_pdvfs_opp {
-+ struct pdvfs_opp opp_salues[NUM_OPP_VALUES];
-+ u32 max_opp_point;
-+} __aligned(8);
-+
-+struct rogue_fwif_pdvfs_max_freq_data {
-+ u32 max_opp_point;
-+} __aligned(8);
-+
-+struct rogue_fwif_pdvfs_min_freq_data {
-+ u32 min_opp_point;
-+} __aligned(8);
-+
-+/*
-+ ******************************************************************************
-+ * Register configuration structures
-+ ******************************************************************************
-+ */
-+
-+#define ROGUE_FWIF_REG_CFG_MAX_SIZE 512
-+
-+enum rogue_fwif_regdata_cmd_type {
-+ ROGUE_FWIF_REGCFG_CMD_ADD = 101,
-+ ROGUE_FWIF_REGCFG_CMD_CLEAR = 102,
-+ ROGUE_FWIF_REGCFG_CMD_ENABLE = 103,
-+ ROGUE_FWIF_REGCFG_CMD_DISABLE = 104
-+};
-+
-+enum rogue_fwif_reg_cfg_type {
-+ /* Sidekick power event */
-+ ROGUE_FWIF_REG_CFG_TYPE_PWR_ON = 0,
-+ /* Rascal / dust power event */
-+ ROGUE_FWIF_REG_CFG_TYPE_DUST_CHANGE,
-+ /* Geometry kick */
-+ ROGUE_FWIF_REG_CFG_TYPE_GEOM,
-+ /* Fragment kick */
-+ ROGUE_FWIF_REG_CFG_TYPE_FRAG,
-+ /* Compute kick */
-+ ROGUE_FWIF_REG_CFG_TYPE_CDM,
-+ /* TLA kick */
-+ ROGUE_FWIF_REG_CFG_TYPE_TLA,
-+ /* TDM kick */
-+ ROGUE_FWIF_REG_CFG_TYPE_TDM,
-+ /* Applies to all types. Keep as last element */
-+ ROGUE_FWIF_REG_CFG_TYPE_ALL
-+};
-+
-+struct rogue_fwif_reg_cfg_rec {
-+ u64 sddr;
-+ u64 mask;
-+ u64 value;
-+};
-+
-+struct rogue_fwif_regconfig_data {
-+ enum rogue_fwif_regdata_cmd_type cmd_type;
-+ enum rogue_fwif_reg_cfg_type reg_config_type;
-+ struct rogue_fwif_reg_cfg_rec reg_config __aligned(8);
-+};
-+
-+struct rogue_fwif_reg_cfg {
-+ /*
-+ * PDump WRW command write granularity is 32 bits.
-+ * Add padding to ensure array size is 32 bit granular.
-+ */
-+ u8 num_regs_type[ALIGN((u32)ROGUE_FWIF_REG_CFG_TYPE_ALL,
-+ sizeof(u32))] __aligned(8);
-+ struct rogue_fwif_reg_cfg_rec
-+ reg_configs[ROGUE_FWIF_REG_CFG_MAX_SIZE] __aligned(8);
-+} __aligned(8);
-+
-+/* OSid Scheduling Priority Change */
-+struct rogue_fwif_osid_priority_data {
-+ u32 osid_num;
-+ u32 priority;
-+};
-+
-+/* clang-format off */
-+enum rogue_fwif_os_state_change {
-+ ROGUE_FWIF_OS_ONLINE = 1,
-+ ROGUE_FWIF_OS_OFFLINE
-+};
-+/* clang-format on */
-+
-+struct rogue_fwif_os_state_change_data {
-+ u32 osid;
-+ enum rogue_fwif_os_state_change new_os_state;
-+} __aligned(8);
-+
-+enum rogue_fwif_counter_dump_request {
-+ ROGUE_FWIF_PWR_COUNTER_DUMP_START = 1,
-+ ROGUE_FWIF_PWR_COUNTER_DUMP_STOP,
-+ ROGUE_FWIF_PWR_COUNTER_DUMP_SAMPLE,
-+};
-+
-+struct rogue_fwif_counter_dump_data {
-+ enum rogue_fwif_counter_dump_request counter_dump_request;
-+} __aligned(8);
-+
-+enum rogue_fwif_kccb_cmd_type {
-+ /* Common commands */
-+ ROGUE_FWIF_KCCB_CMD_KICK = 101U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ ROGUE_FWIF_KCCB_CMD_MMUCACHE = 102U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ ROGUE_FWIF_KCCB_CMD_BP = 103U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* SLC flush and invalidation request */
-+ ROGUE_FWIF_KCCB_CMD_SLCFLUSHINVAL = 105U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /*
-+ * Requests cleanup of a FW resource (type specified in the command
-+ * data)
-+ */
-+ ROGUE_FWIF_KCCB_CMD_CLEANUP = 106U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Power request */
-+ ROGUE_FWIF_KCCB_CMD_POW = 107U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Backing for on-demand ZS-Buffer done */
-+ ROGUE_FWIF_KCCB_CMD_ZSBUFFER_BACKING_UPDATE =
-+ 108U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Unbacking for on-demand ZS-Buffer done */
-+ ROGUE_FWIF_KCCB_CMD_ZSBUFFER_UNBACKING_UPDATE =
-+ 109U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Freelist Grow done */
-+ ROGUE_FWIF_KCCB_CMD_FREELIST_GROW_UPDATE =
-+ 110U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Freelists Reconstruction done */
-+ ROGUE_FWIF_KCCB_CMD_FREELISTS_RECONSTRUCTION_UPDATE =
-+ 112U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Informs the firmware that the host has performed a signal update */
-+ ROGUE_FWIF_KCCB_CMD_NOTIFY_SIGNAL_UPDATE =
-+ 113U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /*
-+ * Informs the firmware that the host has added more data to a CDM2
-+ * Circular Buffer
-+ */
-+ ROGUE_FWIF_KCCB_CMD_NOTIFY_WRITE_OFFSET_UPDATE =
-+ 114U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Health check request */
-+ ROGUE_FWIF_KCCB_CMD_HEALTH_CHECK = 115U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Forcing signalling of all unmet UFOs for a given CCB offset */
-+ ROGUE_FWIF_KCCB_CMD_FORCE_UPDATE = 116U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+
-+ /* There is a geometry and a fragment command in this single kick */
-+ ROGUE_FWIF_KCCB_CMD_COMBINED_GEOM_FRAG_KICK = 117U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+
-+ /* Commands only permitted to the native or host OS */
-+ ROGUE_FWIF_KCCB_CMD_REGCONFIG = 200U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Configure the custom counters for HWPerf */
-+ ROGUE_FWIF_KCCB_CMD_HWPERF_SELECT_CUSTOM_CNTRS =
-+ 201U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /*
-+ * Ask the firmware to update its cached ui32LogType value from the
-+ * (shared) tracebuf control structure
-+ */
-+ ROGUE_FWIF_KCCB_CMD_LOGTYPE_UPDATE = 202U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Set a maximum frequency/OPP point */
-+ ROGUE_FWIF_KCCB_CMD_PDVFS_LIMIT_MAX_FREQ =
-+ 203U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /*
-+ * Changes the relative scheduling priority for a particular OSid. It
-+ * can only be serviced for the Host DDK
-+ */
-+ ROGUE_FWIF_KCCB_CMD_OSID_PRIORITY_CHANGE =
-+ 204U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Set or clear firmware state flags */
-+ ROGUE_FWIF_KCCB_CMD_STATEFLAGS_CTRL = 205U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Set hard context switching deadline */
-+ ROGUE_FWIF_KCCB_CMD_HCS_SET_DEADLINE = 206U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /*
-+ * Informs the FW that a Guest OS has come online / offline. It can only
-+ * be serviced for the Host DDK
-+ */
-+ ROGUE_FWIF_KCCB_CMD_OS_ONLINE_STATE_CONFIGURE =
-+ 207U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Controls counter dumping in the FW */
-+ ROGUE_FWIF_KCCB_CMD_COUNTER_DUMP = 208U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /*
-+ * Configure HWPerf events (to be generated) and HWPerf buffer address
-+ * (if required)
-+ */
-+ ROGUE_FWIF_KCCB_CMD_HWPERF_UPDATE_CONFIG =
-+ 209U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Configure, clear and enable multiple HWPerf blocks */
-+ ROGUE_FWIF_KCCB_CMD_HWPERF_CONFIG_ENABLE_BLKS =
-+ 210U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /*
-+ * Enable or disable multiple HWPerf blocks (reusing existing
-+ * configuration)
-+ */
-+ ROGUE_FWIF_KCCB_CMD_HWPERF_CTRL_BLKS = 211U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Core clock speed change event */
-+ ROGUE_FWIF_KCCB_CMD_CORECLKSPEEDCHANGE = 212U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Set a minimum frequency/OPP point */
-+ ROGUE_FWIF_KCCB_CMD_PDVFS_LIMIT_MIN_FREQ =
-+ 213U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Configure Periodic Hardware Reset behaviour */
-+ ROGUE_FWIF_KCCB_CMD_PHR_CFG = 214U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Configure Safety Firmware Watchdog */
-+ ROGUE_FWIF_KCCB_CMD_WDG_CFG = 216U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+};
-+
-+#define ROGUE_FWIF_LAST_ALLOWED_GUEST_KCCB_CMD \
-+ (ROGUE_FWIF_KCCB_CMD_REGCONFIG - 1)
-+
-+/* Kernel CCB command packet */
-+struct rogue_fwif_kccb_cmd {
-+ /* Command type */
-+ enum rogue_fwif_kccb_cmd_type cmd_type;
-+ /* Compatibility and other flags */
-+ u32 kccb_flags;
-+
-+ /*
-+ * NOTE: Make sure that uCmdData is the last member of this struct
-+ * This is to calculate actual command size for device mem copy.
-+ * (Refer ROGUEGetCmdMemCopySize())
-+ */
-+ union {
-+ /* Data for Kick command */
-+ struct rogue_fwif_kccb_cmd_kick_data cmd_kick_data;
-+ /* Data for combined geom/frag Kick command */
-+ struct rogue_fwif_kccb_cmd_combined_geom_frag_kick_data
-+ combined_geom_frag_cmd_kick_data;
-+ /* Data for MMU cache command */
-+ struct rogue_fwif_mmucachedata mmu_cache_data;
-+ /* Data for Breakpoint Commands */
-+ struct rogue_fwif_bpdata bp_data;
-+ /* Data for SLC Flush/Inval commands */
-+ struct rogue_fwif_slcflushinvaldata slc_flush_inval_data;
-+ /* Data for cleanup commands */
-+ struct rogue_fwif_cleanup_request cleanup_data;
-+ /* Data for power request commands */
-+ struct rogue_fwif_power_request pow_data;
-+ /* Data for HWPerf control command */
-+ struct rogue_fwif_hwperf_ctrl hw_perf_ctrl;
-+ /*
-+ * Data for HWPerf configure, clear and enable performance
-+ * counter block command
-+ */
-+ struct rogue_fwif_hwperf_config_enable_blks
-+ hw_perf_cfg_enable_blks;
-+ /*
-+ * Data for HWPerf enable or disable performance counter block
-+ * commands
-+ */
-+ struct rogue_fwif_hwperf_ctrl_blks hw_perf_ctrl_blks;
-+ /* Data for HWPerf configure the custom counters to read */
-+ struct rogue_fwif_hwperf_select_custom_cntrs
-+ hw_perf_select_cstm_cntrs;
-+ /* Data for core clock speed change */
-+ struct rogue_fwif_coreclkspeedchange_data
-+ core_clk_speed_change_data;
-+ /* Feedback for Z/S Buffer backing/unbacking */
-+ struct rogue_fwif_zsbuffer_backing_data zs_buffer_backing_data;
-+ /* Feedback for Freelist grow/shrink */
-+ struct rogue_fwif_freelist_gs_data free_list_gs_data;
-+ /* Feedback for Freelists reconstruction*/
-+ struct rogue_fwif_freelists_reconstruction_data
-+ free_lists_reconstruction_data;
-+ /* Data for custom register configuration */
-+ struct rogue_fwif_regconfig_data reg_config_data;
-+ /* Data for informing the FW about the signal update */
-+ struct rogue_fwif_signal_update_data signal_update_data;
-+ /* Data for informing the FW about the write offset update */
-+ struct rogue_fwif_write_offset_update_data
-+ write_offset_update_data;
-+ /* Data for setting the max frequency/OPP */
-+ struct rogue_fwif_pdvfs_max_freq_data pdvfs_max_freq_data;
-+ /* Data for setting the min frequency/OPP */
-+ struct rogue_fwif_pdvfs_min_freq_data pdvfs_min_freq_data;
-+ /* Data for updating an OSid priority */
-+ struct rogue_fwif_osid_priority_data cmd_osid_priority_data;
-+ /* Data for Hard Context Switching */
-+ struct rogue_fwif_hcs_ctl hcs_ctrl;
-+ /* Data for updating the Guest Online states */
-+ struct rogue_fwif_os_state_change_data cmd_os_online_state_data;
-+ /* Dev address for TBI buffer allocated on demand */
-+ u32 tbi_buffer_fw_addr;
-+ /* Data for dumping of register ranges */
-+ struct rogue_fwif_counter_dump_data counter_dump_config_data;
-+ /* Data for signalling all unmet fences for a given CCB */
-+ struct rogue_fwif_kccb_cmd_force_update_data force_update_data;
-+ /* Data for configuring the Periodic Hw Reset behaviour */
-+ struct rogue_fwif_kccb_cmd_phr_cfg_data periodic_hw_reset_cfg;
-+ /* Data for configuring the Safety Firmware Watchdog */
-+ struct rogue_fwif_kccb_cmd_wdg_cfg_data safety_watchdog_cfg;
-+ } cmd_data __aligned(8);
-+} __aligned(8);
-+
-+PVR_FW_STRUCT_SIZE_ASSERT(struct rogue_fwif_kccb_cmd);
-+
-+/*
-+ ******************************************************************************
-+ * Firmware CCB command structure for ROGUE
-+ ******************************************************************************
-+ */
-+
-+struct rogue_fwif_fwccb_cmd_zsbuffer_backing_data {
-+ u32 zs_buffer_id;
-+};
-+
-+struct rogue_fwif_fwccb_cmd_freelist_gs_data {
-+ u32 freelist_id;
-+};
-+
-+struct rogue_fwif_fwccb_cmd_freelists_reconstruction_data {
-+ u32 freelist_count;
-+ u32 hwr_counter;
-+ u32 freelist_ids[ROGUE_FWIF_MAX_FREELISTS_TO_RECONSTRUCT];
-+};
-+
-+struct rogue_fwif_fwccb_cmd_context_reset_data {
-+ /* Context affected by the reset */
-+ u32 server_common_context_id;
-+ /* Reason for reset */
-+ enum rogue_context_reset_reason reset_reason;
-+ /* Data Master affected by the reset */
-+ u32 dm;
-+ /* Job ref running at the time of reset */
-+ u32 reset_job_ref;
-+ /* Did a page fault happen */
-+ bool page_fault __aligned(4);
-+ /* At what page catalog address */
-+ aligned_u64 pc_address;
-+ /* Page fault address (only when applicable) */
-+ aligned_u64 fault_address;
-+};
-+
-+enum rogue_fwif_fwccb_cmd_type {
-+ /* Requests ZSBuffer to be backed with physical pages */
-+ ROGUE_FWIF_FWCCB_CMD_ZSBUFFER_BACKING = 101U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Requests ZSBuffer to be unbacked */
-+ ROGUE_FWIF_FWCCB_CMD_ZSBUFFER_UNBACKING = 102U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Requests an on-demand freelist grow/shrink */
-+ ROGUE_FWIF_FWCCB_CMD_FREELIST_GROW = 103U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Requests freelists reconstruction */
-+ ROGUE_FWIF_FWCCB_CMD_FREELISTS_RECONSTRUCTION =
-+ 104U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Notifies host of a HWR event on a context */
-+ ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_NOTIFICATION =
-+ 105U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Requests an on-demand debug dump */
-+ ROGUE_FWIF_FWCCB_CMD_DEBUG_DUMP = 106U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ /* Requests an on-demand update on process stats */
-+ ROGUE_FWIF_FWCCB_CMD_UPDATE_STATS = 107U |
-+ ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+
-+ ROGUE_FWIF_FWCCB_CMD_CORE_CLK_RATE_CHANGE =
-+ 108U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+ ROGUE_FWIF_FWCCB_CMD_REQUEST_GPU_RESTART =
-+ 109U | ROGUE_CMD_MAGIC_DWORD_SHIFTED,
-+};
-+
-+enum rogue_fwif_fwccb_cmd_update_stats_type {
-+ /*
-+ * PVRSRVStatsUpdateRenderContextStats should increase the value of the
-+ * ui32TotalNumPartialRenders stat
-+ */
-+ ROGUE_FWIF_FWCCB_CMD_UPDATE_NUM_PARTIAL_RENDERS = 1,
-+ /*
-+ * PVRSRVStatsUpdateRenderContextStats should increase the value of the
-+ * ui32TotalNumOutOfMemory stat
-+ */
-+ ROGUE_FWIF_FWCCB_CMD_UPDATE_NUM_OUT_OF_MEMORY,
-+ /*
-+ * PVRSRVStatsUpdateRenderContextStats should increase the value of the
-+ * ui32NumGeomStores stat
-+ */
-+ ROGUE_FWIF_FWCCB_CMD_UPDATE_NUM_GEOM_STORES,
-+ /*
-+ * PVRSRVStatsUpdateRenderContextStats should increase the value of the
-+ * ui32NumFragStores stat
-+ */
-+ ROGUE_FWIF_FWCCB_CMD_UPDATE_NUM_FRAG_STORES,
-+ /*
-+ * PVRSRVStatsUpdateRenderContextStats should increase the value of the
-+ * ui32NumCDMStores stat
-+ */
-+ ROGUE_FWIF_FWCCB_CMD_UPDATE_NUM_CDM_STORES,
-+ /*
-+ * PVRSRVStatsUpdateRenderContextStats should increase the value of the
-+ * ui32NumTDMStores stat
-+ */
-+ ROGUE_FWIF_FWCCB_CMD_UPDATE_NUM_TDM_STORES
-+};
-+
-+struct rogue_fwif_fwccb_cmd_update_stats_data {
-+ /* Element to update */
-+ enum rogue_fwif_fwccb_cmd_update_stats_type element_to_update;
-+ /* The pid of the process whose stats are being updated */
-+ u32 pid_owner;
-+ /* Adjustment to be made to the statistic */
-+ s32 adjustment_value;
-+};
-+
-+struct rogue_fwif_fwccb_cmd_core_clk_rate_change_data {
-+ u32 core_clk_rate;
-+} __aligned(8);
-+
-+struct rogue_fwif_fwccb_cmd {
-+ /* Command type */
-+ enum rogue_fwif_fwccb_cmd_type cmd_type;
-+ /* Compatibility and other flags */
-+ u32 fwccb_flags;
-+
-+ union {
-+ /* Data for Z/S-Buffer on-demand (un)backing*/
-+ struct rogue_fwif_fwccb_cmd_zsbuffer_backing_data
-+ cmd_zs_buffer_backing;
-+ /* Data for on-demand freelist grow/shrink */
-+ struct rogue_fwif_fwccb_cmd_freelist_gs_data cmd_free_list_gs;
-+ /* Data for freelists reconstruction */
-+ struct rogue_fwif_fwccb_cmd_freelists_reconstruction_data
-+ cmd_freelists_reconstruction;
-+ /* Data for context reset notification */
-+ struct rogue_fwif_fwccb_cmd_context_reset_data
-+ cmd_context_reset_notification;
-+ /* Data for updating process stats */
-+ struct rogue_fwif_fwccb_cmd_update_stats_data
-+ cmd_update_stats_data;
-+ struct rogue_fwif_fwccb_cmd_core_clk_rate_change_data
-+ cmd_core_clk_rate_change;
-+ } cmd_data __aligned(8);
-+} __aligned(8);
-+
-+PVR_FW_STRUCT_SIZE_ASSERT(struct rogue_fwif_fwccb_cmd);
-+
-+/*
-+ ******************************************************************************
-+ * Workload estimation Firmware CCB command structure for ROGUE
-+ ******************************************************************************
-+ */
-+struct rogue_fwif_workest_fwccb_cmd {
-+ /* Index for return data array */
-+ aligned_u64 return_data_index;
-+ /* The cycles the workload took on the hardware */
-+ aligned_u64 cycles_taken;
-+};
-+
-+/*
-+ ******************************************************************************
-+ * Client CCB commands for ROGUE
-+ ******************************************************************************
-+ */
-+
-+/*
-+ * Required memory alignment for 64-bit variables accessible by Meta
-+ * (The gcc meta aligns 64-bit variables to 64-bit; therefore, memory shared
-+ * between the host and meta that contains 64-bit variables has to maintain
-+ * this alignment)
-+ */
-+#define ROGUE_FWIF_FWALLOC_ALIGN sizeof(u64)
-+
-+#define ROGUE_CCB_TYPE_TASK BIT(15)
-+#define ROGUE_CCB_FWALLOC_ALIGN(size) \
-+ (((size) + (ROGUE_FWIF_FWALLOC_ALIGN - 1)) & \
-+ ~(ROGUE_FWIF_FWALLOC_ALIGN - 1))
-+
-+#define ROGUE_FWIF_CCB_CMD_TYPE_GEOM \
-+ (201U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_TQ_3D \
-+ (202U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_FRAG \
-+ (203U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_FRAG_PR \
-+ (204U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_CDM \
-+ (205U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_TQ_TDM \
-+ (206U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_FBSC_INVALIDATE \
-+ (207U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_TQ_2D \
-+ (208U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_PRE_TIMESTAMP \
-+ (209U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_NULL \
-+ (210U | ROGUE_CMD_MAGIC_DWORD_SHIFTED | ROGUE_CCB_TYPE_TASK)
-+
-+/* Leave a gap between CCB specific commands and generic commands */
-+#define ROGUE_FWIF_CCB_CMD_TYPE_FENCE (211U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_UPDATE (212U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_RMW_UPDATE \
-+ (213U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_FENCE_PR (214U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_PRIORITY (215U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+/*
-+ * Pre and Post timestamp commands are supposed to sandwich the DM cmd. The
-+ * padding code with the CCB wrap upsets the FW if we don't have the task type
-+ * bit cleared for POST_TIMESTAMPs. That's why we have 2 different cmd types.
-+ */
-+#define ROGUE_FWIF_CCB_CMD_TYPE_POST_TIMESTAMP \
-+ (216U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_UNFENCED_UPDATE \
-+ (217U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+#define ROGUE_FWIF_CCB_CMD_TYPE_UNFENCED_RMW_UPDATE \
-+ (218U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+
-+#define ROGUE_FWIF_CCB_CMD_TYPE_PADDING (220U | ROGUE_CMD_MAGIC_DWORD_SHIFTED)
-+
-+struct rogue_fwif_workest_kick_data {
-+ /* Index for the KM Workload estimation return data array */
-+ aligned_u64 return_data_index;
-+ /* Deadline for the workload */
-+ aligned_u64 deadline;
-+ /* Predicted time taken to do the work in cycles */
-+ aligned_u64 cycles_prediction;
-+};
-+
-+struct rogue_fwif_ccb_cmd_header {
-+ u32 cmd_type;
-+ u32 cmd_size;
-+ /*
-+ * external job reference - provided by client and used in debug for
-+ * tracking submitted work
-+ */
-+ u32 ext_job_ref;
-+ /*
-+ * internal job reference - generated by services and used in debug for
-+ * tracking submitted work
-+ */
-+ u32 int_job_ref;
-+ /* Workload Estimation - Workload Estimation Data */
-+ struct rogue_fwif_workest_kick_data work_est_kick_data;
-+};
-+
-+/*
-+ ******************************************************************************
-+ * Client CCB commands which are only required by the kernel
-+ ******************************************************************************
-+ */
-+struct rogue_fwif_cmd_priority {
-+ u32 priority;
-+};
-+
-+/*
-+ ******************************************************************************
-+ * Signature and Checksums Buffer
-+ ******************************************************************************
-+ */
-+struct rogue_fwif_sigbuf_ctl {
-+ /* Ptr to Signature Buffer memory */
-+ u32 buffer_fw_addr;
-+ /* Amount of space left for storing regs in the buffer */
-+ u32 left_size_in_regs;
-+} __aligned(8);
-+
-+struct rogue_fwif_counter_dump_ctl {
-+ /* Ptr to counter dump buffer */
-+ u32 buffer_fw_addr;
-+ /* Amount of space for storing in the buffer */
-+ u32 size_in_dwords;
-+} __aligned(8);
-+
-+struct rogue_fwif_firmware_gcov_ctl {
-+ /* Ptr to firmware gcov buffer */
-+ u32 buffer_fw_addr;
-+ /* Amount of space for storing in the buffer */
-+ u32 size;
-+} __aligned(8);
-+
-+/*
-+ *****************************************************************************
-+ * ROGUE Compatibility checks
-+ *****************************************************************************
-+ */
-+
-+/*
-+ * WARNING: Whenever the layout of ROGUE_FWIF_COMPCHECKS_BVNC changes, the
-+ * following define should be increased by 1 to indicate to the compatibility
-+ * logic that layout has changed.
-+ */
-+#define ROGUE_FWIF_COMPCHECKS_LAYOUT_VERSION 3
-+
-+struct rogue_fwif_compchecks_bvnc {
-+ /* WARNING: This field must be defined as first one in this structure */
-+ u32 layout_version;
-+ aligned_u64 bvnc;
-+} __aligned(8);
-+
-+struct rogue_fwif_init_options {
-+ u8 os_count_support;
-+} __aligned(8);
-+
-+#define ROGUE_FWIF_COMPCHECKS_BVNC_DECLARE_AND_INIT(name) \
-+ struct rogue_fwif_compchecks_bvnc(name) = { \
-+ ROGUE_FWIF_COMPCHECKS_LAYOUT_VERSION, \
-+ 0, \
-+ }
-+#define ROGUE_FWIF_COMPCHECKS_BVNC_INIT(name) \
-+ do { \
-+ (name).layout_version = ROGUE_FWIF_COMPCHECKS_LAYOUT_VERSION; \
-+ (name).bvnc = 0; \
-+ } while (0)
-+
-+struct rogue_fwif_compchecks {
-+ /* hardware BVNC (from the ROGUE registers) */
-+ struct rogue_fwif_compchecks_bvnc hw_bvnc;
-+ /* firmware BVNC */
-+ struct rogue_fwif_compchecks_bvnc fw_bvnc;
-+ /* identifier of the FW processor version */
-+ u32 fw_processor_version;
-+ /* software DDK version */
-+ u32 ddk_version;
-+ /* software DDK build no. */
-+ u32 ddk_build;
-+ /* build options bit-field */
-+ u32 build_options;
-+ /* initialisation options bit-field */
-+ struct rogue_fwif_init_options init_options;
-+ /* Information is valid */
-+ bool updated __aligned(4);
-+} __aligned(8);
-+
-+/*
-+ ******************************************************************************
-+ * Updated configuration post FW data init.
-+ ******************************************************************************
-+ */
-+struct rogue_fwif_runtime_cfg {
-+ /* APM latency in ms before signalling IDLE to the host */
-+ u32 active_pm_latency_ms;
-+ /* Compatibility and other flags */
-+ u32 runtime_cfg_flags;
-+ /*
-+ * If set, APM latency does not reset to system default each GPU power
-+ * transition
-+ */
-+ bool active_pm_latency_persistant __aligned(4);
-+ /* Core clock speed, currently only used to calculate timer ticks */
-+ u32 core_clock_speed;
-+ /* Last number of dusts change requested by the host */
-+ u32 default_dusts_num_init;
-+ /* On-demand allocated HWPerf buffer address, to be passed to the FW */
-+ u32 hwperf_buf_fw_addr;
-+};
-+
-+/*
-+ *****************************************************************************
-+ * Control data for ROGUE
-+ *****************************************************************************
-+ */
-+
-+#define ROGUE_FWIF_HWR_DEBUG_DUMP_ALL (99999U)
-+
-+enum rogue_fwif_tpu_dm {
-+ ROGUE_FWIF_TPU_DM_PDM = 0,
-+ ROGUE_FWIF_TPU_DM_VDM = 1,
-+ ROGUE_FWIF_TPU_DM_CDM = 2,
-+ ROGUE_FWIF_TPU_DM_TDM = 3,
-+ ROGUE_FWIF_TPU_DM_LAST
-+};
-+
-+enum rogue_fwif_gpio_val_mode {
-+ /* No GPIO validation */
-+ ROGUE_FWIF_GPIO_VAL_OFF = 0,
-+ /*
-+ * Simple test case that initiates by sending data via the GPIO and then
-+ * sends back any data received over the GPIO
-+ */
-+ ROGUE_FWIF_GPIO_VAL_GENERAL = 1,
-+ /*
-+ * More complex test case that writes and reads data across the entire
-+ * GPIO AP address range.
-+ */
-+ ROGUE_FWIF_GPIO_VAL_AP = 2,
-+ /* Validates the GPIO Testbench. */
-+ ROGUE_FWIF_GPIO_VAL_TESTBENCH = 5,
-+ ROGUE_FWIF_GPIO_VAL_LAST
-+};
-+
-+enum fw_perf_conf {
-+ FW_PERF_CONF_NONE = 0,
-+ FW_PERF_CONF_ICACHE = 1,
-+ FW_PERF_CONF_DCACHE = 2,
-+ FW_PERF_CONF_POLLS = 3,
-+ FW_PERF_CONF_CUSTOM_TIMER = 4,
-+ FW_PERF_CONF_JTLB_INSTR = 5,
-+ FW_PERF_CONF_INSTRUCTIONS = 6
-+};
-+
-+enum fw_boot_stage {
-+ FW_BOOT_STAGE_TLB_INIT_FAILURE = -2,
-+ FW_BOOT_STAGE_NOT_AVAILABLE = -1,
-+ FW_BOOT_NOT_STARTED = 0,
-+ FW_BOOT_BLDR_STARTED = 1,
-+ FW_BOOT_CACHE_DONE,
-+ FW_BOOT_TLB_DONE,
-+ FW_BOOT_MAIN_STARTED,
-+ FW_BOOT_ALIGNCHECKS_DONE,
-+ FW_BOOT_INIT_DONE,
-+};
-+
-+/*
-+ * Kernel CCB return slot responses. Usage of bit-fields instead of bare
-+ * integers allows FW to possibly pack-in several responses for each single kCCB
-+ * command.
-+ */
-+/* Command executed (return status from FW) */
-+#define ROGUE_FWIF_KCCB_RTN_SLOT_CMD_EXECUTED BIT(0)
-+/* A cleanup was requested but resource busy */
-+#define ROGUE_FWIF_KCCB_RTN_SLOT_CLEANUP_BUSY BIT(1)
-+/* Poll failed in FW for a HW operation to complete */
-+#define ROGUE_FWIF_KCCB_RTN_SLOT_POLL_FAILURE BIT(2)
-+/* Reset value of a kCCB return slot (set by host) */
-+#define ROGUE_FWIF_KCCB_RTN_SLOT_NO_RESPONSE 0x0U
-+
-+struct rogue_fwif_connection_ctl {
-+ /* Fw-Os connection states */
-+ volatile enum rogue_fwif_connection_fw_state connection_fw_state;
-+ volatile enum rogue_fwif_connection_os_state connection_os_state;
-+ volatile u32 alive_fw_token;
-+ volatile u32 alive_os_token;
-+} __aligned(8);
-+
-+struct rogue_fwif_osinit {
-+ /* Kernel CCB */
-+ u32 kernel_ccbctl_fw_addr;
-+ u32 kernel_ccb_fw_addr;
-+ u32 kernel_ccb_rtn_slots_fw_addr;
-+
-+ /* Firmware CCB */
-+ u32 firmware_ccbctl_fw_addr;
-+ u32 firmware_ccb_fw_addr;
-+
-+ /* Workload Estimation Firmware CCB */
-+ u32 work_est_firmware_ccbctl_fw_addr;
-+ u32 work_est_firmware_ccb_fw_addr;
-+
-+ u32 rogue_fwif_hwr_info_buf_ctl_fw_addr;
-+
-+ u32 hwr_debug_dump_limit;
-+
-+ u32 fw_os_data_fw_addr;
-+
-+ /* Compatibility checks to be populated by the Firmware */
-+ struct rogue_fwif_compchecks rogue_comp_checks;
-+} __aligned(8);
-+
-+/* BVNC Features */
-+struct rogue_hwperf_bvnc_block {
-+ /* Counter block ID, see ROGUE_HWPERF_CNTBLK_ID */
-+ u16 block_id;
-+
-+ /* Number of counters in this block type */
-+ u16 num_counters;
-+
-+ /* Number of blocks of this type */
-+ u16 num_blocks;
-+
-+ u16 reserved;
-+};
-+
-+#define ROGUE_HWPERF_MAX_BVNC_LEN (24)
-+
-+#define ROGUE_HWPERF_MAX_BVNC_BLOCK_LEN (16U)
-+
-+/* BVNC Features */
-+struct rogue_hwperf_bvnc {
-+ /* BVNC string */
-+ char bvnc_string[ROGUE_HWPERF_MAX_BVNC_LEN];
-+ /* See ROGUE_HWPERF_FEATURE_FLAGS */
-+ u32 bvnc_km_feature_flags;
-+ /* Number of blocks described in aBvncBlocks */
-+ u16 num_bvnc_blocks;
-+ /* Number of GPU cores present */
-+ u16 bvnc_gpu_cores;
-+ /* Supported Performance Blocks for BVNC */
-+ struct rogue_hwperf_bvnc_block
-+ bvnc_blocks[ROGUE_HWPERF_MAX_BVNC_BLOCK_LEN];
-+};
-+
-+PVR_FW_STRUCT_SIZE_ASSERT(struct rogue_hwperf_bvnc);
-+
-+struct rogue_fwif_sysinit {
-+ aligned_u64 fault_phys_addr;
-+
-+ aligned_u64 pds_exec_base;
-+ aligned_u64 usc_exec_base;
-+
-+ u32 filter_flags;
-+
-+ struct rogue_fwif_sigbuf_ctl sig_buf_ctl[PVR_FWIF_DM_MAX];
-+
-+ u32 runtime_cfg_fw_addr;
-+
-+ u32 trace_buf_ctl_fw_addr;
-+ u32 fw_sys_data_fw_addr;
-+
-+ aligned_u64 hw_perf_filter;
-+
-+ u32 gpu_util_fw_cb_ctl_fw_addr;
-+ u32 reg_cfg_fw_addr;
-+ u32 hwperf_ctl_fw_addr;
-+
-+ struct rogue_fwif_counter_dump_ctl counter_dump_ctl;
-+
-+ u32 align_checks;
-+
-+ /* Core clock speed at FW boot time */
-+ u32 initial_core_clock_speed;
-+
-+ /* APM latency in ms before signalling IDLE to the host */
-+ u32 active_pm_latency_ms;
-+
-+ /* Flag to be set by the Firmware after successful start */
-+ bool firmware_started __aligned(4);
-+
-+ u32 marker_val;
-+
-+ u32 firmware_started_timestamp;
-+
-+ u32 jones_disable_mask;
-+
-+ struct rogue_fwif_dma_addr coremem_data_store;
-+
-+ enum fw_perf_conf firmware_perf;
-+
-+ aligned_u64 slc3_fence_dev_addr;
-+
-+ struct rogue_fwif_pdvfs_opp pdvfs_opp_info;
-+
-+ /*
-+ * FW Pointer to memory containing core clock rate in Hz.
-+ * Firmware (PDVFS) updates the memory when running on non primary FW
-+ * thread to communicate to host driver.
-+ */
-+ u32 core_clock_rate_fw_addr;
-+
-+ enum rogue_fwif_gpio_val_mode gpio_validation_mode;
-+ u32 tpu_trilinear_frac_mask[ROGUE_FWIF_TPU_DM_LAST] __aligned(8);
-+
-+ /* Used in HWPerf for decoding BVNC Features */
-+ struct rogue_hwperf_bvnc bvnc_km_feature_flags;
-+} __aligned(8);
-+
-+/*
-+ *****************************************************************************
-+ * Timer correlation shared data and defines
-+ *****************************************************************************
-+ */
-+
-+struct rogue_fwif_time_corr {
-+ aligned_u64 os_timestamp;
-+ aligned_u64 os_mono_timestamp;
-+ aligned_u64 cr_timestamp;
-+
-+ /*
-+ * Utility variable used to convert CR timer deltas to OS timer deltas
-+ * (nS), where the deltas are relative to the timestamps above:
-+ * deltaOS = (deltaCR * K) >> decimal_shift, see full explanation below
-+ */
-+ aligned_u64 cr_delta_to_os_delta_kns;
-+
-+ u32 core_clock_speed;
-+ u32 reserved;
-+} __aligned(8);
-+
-+/*
-+ * The following macros are used to help converting FW timestamps to the Host
-+ * time domain. On the FW the ROGUE_CR_TIMER counter is used to keep track of
-+ * time; it increments by 1 every 256 GPU clock ticks, so the general
-+ * formula to perform the conversion is:
-+ *
-+ * [ GPU clock speed in Hz, if (scale == 10^9) then deltaOS is in nS,
-+ * otherwise if (scale == 10^6) then deltaOS is in uS ]
-+ *
-+ * deltaCR * 256 256 * scale
-+ * deltaOS = --------------- * scale = deltaCR * K [ K = --------------- ]
-+ * GPUclockspeed GPUclockspeed
-+ *
-+ * The actual K is multiplied by 2^20 (and deltaCR * K is divided by 2^20)
-+ * to get some better accuracy and to avoid returning 0 in the integer
-+ * division 256000000/GPUfreq if GPUfreq is greater than 256MHz.
-+ * This is the same as keeping K as a decimal number.
-+ *
-+ * The maximum deltaOS is slightly more than 5hrs for all GPU frequencies
-+ * (deltaCR * K is more or less a constant), and it's relative to the base
-+ * OS timestamp sampled as a part of the timer correlation data.
-+ * This base is refreshed on GPU power-on, DVFS transition and periodic
-+ * frequency calibration (executed every few seconds if the FW is doing
-+ * some work), so as long as the GPU is doing something and one of these
-+ * events is triggered then deltaCR * K will not overflow and deltaOS will be
-+ * correct.
-+ */
-+
-+#define ROGUE_FWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT (20)
-+
-+#define ROGUE_FWIF_GET_DELTA_OSTIME_NS(delta_cr, k) \
-+ (((delta_cr) * (k)) >> ROGUE_FWIF_CRDELTA_TO_OSDELTA_ACCURACY_SHIFT)
-+
-+/*
-+ ******************************************************************************
-+ * GPU Utilisation
-+ ******************************************************************************
-+ */
-+
-+/* See rogue_common.h for a list of GPU states */
-+#define ROGUE_FWIF_GPU_UTIL_TIME_MASK \
-+ (0xFFFFFFFFFFFFFFFFull & ~ROGUE_FWIF_GPU_UTIL_STATE_MASK)
-+
-+#define ROGUE_FWIF_GPU_UTIL_GET_TIME(word) \
-+ ((word)(&ROGUE_FWIF_GPU_UTIL_TIME_MASK))
-+#define ROGUE_FWIF_GPU_UTIL_GET_STATE(word) \
-+ ((word)(&ROGUE_FWIF_GPU_UTIL_STATE_MASK))
-+
-+/*
-+ * The OS timestamps computed by the FW are approximations of the real time,
-+ * which means they could be slightly behind or ahead the real timer on the
-+ * Host. In some cases we can perform subtractions between FW approximated
-+ * timestamps and real OS timestamps, so we need a form of protection against
-+ * negative results if for instance the FW one is a bit ahead of time.
-+ */
-+#define ROGUE_FWIF_GPU_UTIL_GET_PERIOD(newtime, oldtime) \
-+ (((newtime) > (oldtime)) ? ((newtime) - (oldtime)) : 0U)
-+
-+#define ROGUE_FWIF_GPU_UTIL_MAKE_WORD(time, state) \
-+ (ROGUE_FWIF_GPU_UTIL_GET_TIME(time) | \
-+ ROGUE_FWIF_GPU_UTIL_GET_STATE(state))
-+
-+/*
-+ * The timer correlation array must be big enough to ensure old entries won't be
-+ * overwritten before all the HWPerf events linked to those entries are
-+ * processed by the MISR. The update frequency of this array depends on how fast
-+ * the system can change state (basically how small the APM latency is) and
-+ * perform DVFS transitions.
-+ *
-+ * The minimum size is 2 (not 1) to avoid race conditions between the FW reading
-+ * an entry while the Host is updating it. With 2 entries in the worst case the
-+ * FW will read old data, which is still quite ok if the Host is updating the
-+ * timer correlation at that time.
-+ */
-+#define ROGUE_FWIF_TIME_CORR_ARRAY_SIZE 256U
-+#define ROGUE_FWIF_TIME_CORR_CURR_INDEX(seqcount) \
-+ ((seqcount) % ROGUE_FWIF_TIME_CORR_ARRAY_SIZE)
-+
-+/* Make sure the timer correlation array size is a power of 2 */
-+static_assert((ROGUE_FWIF_TIME_CORR_ARRAY_SIZE &
-+ (ROGUE_FWIF_TIME_CORR_ARRAY_SIZE - 1U)) == 0U,
-+ "ROGUE_FWIF_TIME_CORR_ARRAY_SIZE must be a power of two");
-+
-+struct rogue_fwif_gpu_util_fwcb {
-+ struct rogue_fwif_time_corr time_corr[ROGUE_FWIF_TIME_CORR_ARRAY_SIZE];
-+ u32 time_corr_seq_count;
-+
-+ /* Last GPU state + OS time of the last state update */
-+ aligned_u64 last_word;
-+
-+ /* Counters for the amount of time the GPU was active/idle/blocked */
-+ aligned_u64 stats_counters[PVR_FWIF_GPU_UTIL_STATE_NUM];
-+
-+ /* Compatibility and other flags */
-+ u32 gpu_util_flags;
-+} __aligned(8);
-+
-+struct rogue_fwif_rta_ctl {
-+ /* Render number */
-+ u32 render_target_index;
-+ /* index in RTA */
-+ u32 current_render_target;
-+ /* total active RTs */
-+ u32 active_render_targets;
-+ /* total active RTs from the first TA kick, for OOM */
-+ u32 cumul_active_render_targets;
-+ /* Array of valid RT indices */
-+ u32 valid_render_targets_fw_addr;
-+ /* Array of number of occurred partial renders per render target */
-+ u32 rta_num_partial_renders_fw_addr;
-+ /* Number of render targets in the array */
-+ u32 max_rts;
-+ /* Compatibility and other flags */
-+ u32 rta_ctl_flags;
-+} __aligned(8);
-+
-+struct rogue_fwif_freelist {
-+ aligned_u64 freelist_dev_addr;
-+ aligned_u64 current_dev_addr;
-+ u32 current_stack_top;
-+ u32 max_pages;
-+ u32 grow_pages;
-+ /* HW pages */
-+ u32 current_pages;
-+ u32 allocated_page_count;
-+ u32 allocated_mmu_page_count;
-+ u32 freelist_id;
-+ bool grow_pending __aligned(4);
-+ /* Pages that should be used only when OOM is reached */
-+ u32 ready_pages;
-+ /* Compatibility and other flags */
-+ u32 freelist_flags;
-+} __aligned(8);
-+
-+/*
-+ ******************************************************************************
-+ * Parameter Management (PM) control data for ROGUE
-+ ******************************************************************************
-+ */
-+
-+/*
-+ * Used only by Firmware but defined here for similarity with Volcanic where
-+ * it's required for SW TRP
-+ */
-+
-+enum rogue_fw_spm_state {
-+ ROGUE_FW_SPM_STATE_NONE = 0,
-+ ROGUE_FW_SPM_STATE_PR_BLOCKED,
-+ ROGUE_FW_SPM_STATE_WAIT_FOR_GROW,
-+ ROGUE_FW_SPM_STATE_WAIT_FOR_HW,
-+ ROGUE_FW_SPM_STATE_PR_RUNNING,
-+ ROGUE_FW_SPM_STATE_PR_AVOIDED,
-+ ROGUE_FW_SPM_STATE_PR_EXECUTED,
-+};
-+
-+struct rogue_fw_spmctl {
-+ /* Current owner of this PM data structure */
-+ enum rogue_fw_spm_state spm_state;
-+ /*
-+ * Geometry/fragment fence object holding the value to let through the fragment partial
-+ * command
-+ */
-+ struct rogue_fwif_ufo partial_render_geom_frag_fence;
-+ /* Pointer to the fragment context holding the partial render */
-+ struct rogue_fwif_fwcommoncontext *frag_context;
-+ /* Pointer to the header of the command holding the partial render */
-+ struct rogue_fwif_ccb_cmd_header *cmd_header;
-+ /* Pointer to the fragment command holding the partial render register info */
-+ struct rogue_fwif_cmd_frag_struct *frag_cmd;
-+ /*
-+ * Array of pointers to PR Buffers which may be used if partial render
-+ * is needed
-+ */
-+ struct rogue_fwif_prbuffer *pr_buffer[ROGUE_FWIF_PRBUFFER_MAXSUPPORTED];
-+ /* Indicates the freelist type that went out of memory */
-+ u32 oom_freelist_type;
-+ /* Indicates if a fragment Memory Free has been detected, which resolves OOM. */
-+ bool frag_mem_free_detected __aligned(4);
-+};
-+
-+/*
-+ ******************************************************************************
-+ * HWRTData
-+ ******************************************************************************
-+ */
-+
-+/* HWRTData flags */
-+/* Deprecated flags 1:0 */
-+#define HWRTDATA_HAS_LAST_GEOM BIT(2)
-+#define HWRTDATA_PARTIAL_RENDERED BIT(3)
-+#define HWRTDATA_DISABLE_TILE_REORDERING BIT(4)
-+#define HWRTDATA_NEED_BRN65101_BLIT BIT(5)
-+#define HWRTDATA_FIRST_BRN65101_STRIP BIT(6)
-+#define HWRTDATA_NEED_BRN67182_2ND_RENDER BIT(7)
-+
-+enum rogue_fwif_rtdata_state {
-+ ROGUE_FWIF_RTDATA_STATE_NONE = 0,
-+ ROGUE_FWIF_RTDATA_STATE_KICK_GEOM,
-+ ROGUE_FWIF_RTDATA_STATE_KICK_GEOM_FIRST,
-+ ROGUE_FWIF_RTDATA_STATE_GEOM_FINISHED,
-+ ROGUE_FWIF_RTDATA_STATE_KICK_FRAG,
-+ ROGUE_FWIF_RTDATA_STATE_FRAG_FINISHED,
-+ ROGUE_FWIF_RTDATA_STATE_GEOM_OUTOFMEM,
-+ ROGUE_FWIF_RTDATA_STATE_PARTIALRENDERFINISHED,
-+ /*
-+ * In case of HWR, we can't set the RTDATA state to NONE, as this will
-+ * cause any TA to become a first TA. To ensure all related TA's are
-+ * skipped, we use the HWR state
-+ */
-+ ROGUE_FWIF_RTDATA_STATE_HWR,
-+ ROGUE_FWIF_RTDATA_STATE_UNKNOWN = 0x7FFFFFFFU
-+};
-+
-+struct rogue_fwif_hwrtdata_common {
-+ bool geom_caches_need_zeroing __aligned(4);
-+} __aligned(8);
-+
-+struct rogue_fwif_hwrtdata {
-+ u32 hwrt_data_common_fw_addr;
-+
-+ u32 hwrt_data_flags;
-+ enum rogue_fwif_rtdata_state state;
-+
-+ /* MList Data Store */
-+ aligned_u64 pm_mlist_dev_addr;
-+
-+ aligned_u64 vce_cat_base[4];
-+ aligned_u64 vce_last_cat_base[4];
-+ aligned_u64 te_cat_base[4];
-+ aligned_u64 te_last_cat_base[4];
-+ aligned_u64 alist_cat_base;
-+ aligned_u64 alist_last_cat_base;
-+
-+ aligned_u64 pm_alist_stack_pointer;
-+ u32 pm_mlist_stack_pointer;
-+
-+ u32 freelists_fw_addr[ROGUE_FW_MAX_FREELISTS] __aligned(8);
-+ u32 freelist_hwr_snapshot[ROGUE_FW_MAX_FREELISTS];
-+
-+ aligned_u64 vheap_table_dev_addr;
-+
-+ struct rogue_fwif_cleanup_ctl cleanup_state;
-+
-+ struct rogue_fwif_rta_ctl rta_ctl;
-+
-+ u32 screen_pixel_max;
-+ aligned_u64 multi_sample_ctl;
-+ u64 flipped_multi_sample_ctl;
-+ u32 tpc_stride;
-+ aligned_u64 tail_ptrs_dev_addr;
-+ u32 tpc_size;
-+ u32 te_screen;
-+ u32 mtile_stride;
-+ u32 teaa;
-+ u32 te_mtile1;
-+ u32 te_mtile2;
-+ u32 isp_merge_lower_x;
-+ u32 isp_merge_lower_y;
-+ u32 isp_merge_upper_x;
-+ u32 isp_mergy_upper_y;
-+ u32 isp_merge_scale_x;
-+ u32 isp_merge_scale_y;
-+ aligned_u64 macrotile_array_dev_addr;
-+ aligned_u64 rgn_header_dev_addr;
-+ aligned_u64 rtc_dev_addr;
-+ aligned_u64 rgn_header_size;
-+ u32 isp_mtile_size;
-+ u32 owner_geom_not_used_by_host __aligned(8);
-+} __aligned(8);
-+
-+/*
-+ ******************************************************************************
-+ * Sync checkpoints
-+ ******************************************************************************
-+ */
-+
-+#define PVR_SYNC_CHECKPOINT_UNDEF 0x000
-+#define PVR_SYNC_CHECKPOINT_ACTIVE 0xac1 /* Checkpoint has not signaled. */
-+#define PVR_SYNC_CHECKPOINT_SIGNALED 0x519 /* Checkpoint has signaled. */
-+#define PVR_SYNC_CHECKPOINT_ERRORED 0xeff /* Checkpoint has been errored. */
-+
-+#endif /* __PVR_ROGUE_FWIF_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_client.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_client.h
-new file mode 100644
-index 000000000000..f527cfd3c268
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_client.h
-@@ -0,0 +1,158 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_FWIF_CLIENT_H__
-+#define __PVR_ROGUE_FWIF_CLIENT_H__
-+
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+
-+#include "pvr_rogue_fwif_shared.h"
-+
-+/*
-+ ************************************************
-+ * Parameter/HWRTData control structures.
-+ ************************************************
-+ */
-+
-+/*
-+ * Configuration registers which need to be loaded by the firmware before a geometry
-+ * job can be started.
-+ */
-+struct rogue_fwif_geom_regs {
-+ u64 vdm_ctrl_stream_base;
-+ u64 tpu_border_colour_table;
-+
-+ u32 ppp_ctrl;
-+ u32 te_psg;
-+ u32 tpu;
-+
-+ u32 vdm_context_resume_task0_size;
-+
-+ /* FIXME: HIGH: FIX_HW_BRN_56279 changes the structure's layout, given we
-+ * are supporting Features/ERNs/BRNs at runtime, we need to look into this
-+ * and find a solution to keep layout intact.
-+ */
-+ /* Available if FIX_HW_BRN_56279 is present. */
-+ u32 pds_ctrl;
-+
-+ u32 view_idx;
-+};
-+
-+/*
-+ * Represents a geometry command that can be used to tile a whole scene's objects as
-+ * per TA behavior.
-+ */
-+struct rogue_fwif_cmd_geom {
-+ /*
-+ * rogue_fwif_cmd_geom_frag_shared field must always be at the beginning of the
-+ * struct.
-+ *
-+ * The command struct (rogue_fwif_cmd_geom) is shared between Client and
-+ * Firmware. Kernel is unable to perform read/write operations on the
-+ * command struct, the SHARED region is the only exception from this rule.
-+ * This region must be the first member so that Kernel can easily access it.
-+ * For more info, see rogue_fwif_cmd_geom_frag_shared definition.
-+ */
-+ struct rogue_fwif_cmd_geom_frag_shared cmd_shared;
-+
-+ struct rogue_fwif_geom_regs geom_regs __aligned(8);
-+ u32 flags __aligned(8);
-+
-+ /*
-+ * Holds the geometry/fragment fence value to allow the fragment partial render command
-+ * to go through.
-+ */
-+ struct rogue_fwif_ufo partial_render_geom_frag_fence;
-+};
-+
-+/*
-+ * Configuration registers which need to be loaded by the firmware before ISP
-+ * can be started.
-+ */
-+struct rogue_fwif_frag_regs {
-+ u32 usc_pixel_output_ctrl;
-+
-+ /* FIXME: HIGH: ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL changes the structure's layout. */
-+#define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U
-+ u32 usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL];
-+
-+ u32 isp_bgobjdepth;
-+ u32 isp_bgobjvals;
-+ u32 isp_aa;
-+ u32 isp_ctl;
-+
-+ u32 tpu;
-+
-+ u32 event_pixel_pds_info;
-+
-+ /* FIXME: HIGH: RGX_FEATURE_CLUSTER_GROUPING changes the structure's layout. */
-+ u32 pixel_phantom;
-+
-+ u32 view_idx;
-+
-+ u32 event_pixel_pds_data;
-+ /*
-+ * FIXME: HIGH: MULTIBUFFER_OCLQRY changes the structure's layout.
-+ * Commenting out for now as it's not supported by 4.V.2.51.
-+ */
-+ /* uint32_t isp_oclqry_stride; */
-+
-+ /* All values below the ALIGN(8) must be 64 bit. */
-+ aligned_u64 isp_scissor_base;
-+ u64 isp_dbias_base;
-+ u64 isp_oclqry_base;
-+ u64 isp_zlsctl;
-+ u64 isp_zload_store_base;
-+ u64 isp_stencil_load_store_base;
-+ /* FIXME: HIGH: RGX_FEATURE_ZLS_SUBTILE changes the structure's layout. */
-+ u64 isp_zls_pixels;
-+
-+ /* FIXME: HIGH: RGX_HW_REQUIRES_FB_CDC_ZLS_SETUP changes the structure's layout. */
-+ u64 deprecated;
-+
-+ /* FIXME: HIGH: RGX_PBE_WORDS_REQUIRED_FOR_RENDERS changes the structure's layout. */
-+#define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 2U
-+ u64 pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS];
-+ u64 tpu_border_colour_table;
-+ u64 pds_bgnd[3U];
-+ u64 pds_pr_bgnd[3U];
-+};
-+
-+struct rogue_fwif_cmd_frag {
-+ struct rogue_fwif_cmd_geom_frag_shared cmd_shared __aligned(8);
-+
-+ struct rogue_fwif_frag_regs regs __aligned(8);
-+ /* command control flags. */
-+ u32 flags;
-+ /* Stride IN BYTES for Z-Buffer in case of RTAs. */
-+ u32 zls_stride;
-+ /* Stride IN BYTES for S-Buffer in case of RTAs. */
-+ u32 sls_stride;
-+};
-+
-+/*
-+ * Configuration registers which need to be loaded by the firmware before CDM
-+ * can be started.
-+ */
-+struct rogue_fwif_compute_regs {
-+ u64 tpu_border_colour_table;
-+ u64 cdm_item;
-+ u64 compute_cluster;
-+ u64 cdm_ctrl_stream_base;
-+ u32 tpu;
-+ u32 cdm_resume_pds1;
-+};
-+
-+struct rogue_fwif_cmd_compute {
-+ /* Common command attributes */
-+ struct rogue_fwif_cmd_common common __aligned(8);
-+
-+ /* CDM registers */
-+ struct rogue_fwif_compute_regs cmd_regs;
-+
-+ /* Control flags */
-+ u32 flags __aligned(8);
-+};
-+
-+#endif /* __PVR_ROGUE_FWIF_CLIENT_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_common.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_common.h
-new file mode 100644
-index 000000000000..68083d0d1832
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_common.h
-@@ -0,0 +1,55 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_FWIF_COMMON_H__
-+#define __PVR_ROGUE_FWIF_COMMON_H__
-+
-+#include <linux/build_bug.h>
-+
-+/*
-+ * This macro represents a mask of LSBs that must be zero on data structure
-+ * sizes and offsets to ensure they are 8-byte granular on types shared between
-+ * the FW and host driver.
-+ */
-+#define PVR_FW_ALIGNMENT_LSB 7U
-+
-+/* Macro to test structure size alignment. */
-+#define PVR_FW_STRUCT_SIZE_ASSERT(_a) \
-+ static_assert((sizeof(_a) & PVR_FW_ALIGNMENT_LSB) == 0U, \
-+ "Size of " #_a " is not properly aligned")
-+
-+/* The master definition for data masters known to the firmware. */
-+
-+#define PVR_FWIF_DM_GP 0U
-+/* Either TDM or 2D DM is present. */
-+/* When the 'tla' feature is present in the hw (as per @pvr_device_features). */
-+#define PVR_FWIF_DM_2D 1U
-+/*
-+ * When the 'fastrender_dm' feature is present in the hw (as per
-+ * @pvr_device_features).
-+ */
-+#define PVR_FWIF_DM_TDM 1U
-+#define PVR_FWIF_DM_GEOM 2U
-+#define PVR_FWIF_DM_FRAG 3U
-+#define PVR_FWIF_DM_CDM 4U
-+#define PVR_FWIF_DM_LAST PVR_FWIF_DM_CDM
-+
-+/* Maximum number of DM in use: GP, 2D/TDM, GEOM, FRAG, CDM */
-+#define PVR_FWIF_DM_MAX (PVR_FWIF_DM_LAST + 1U)
-+#define PVR_FWIF_HWDM_MAX PVR_FWIF_DM_MAX
-+
-+/* GPU Utilisation states */
-+#define PVR_FWIF_GPU_UTIL_STATE_IDLE 0U
-+#define PVR_FWIF_GPU_UTIL_STATE_ACTIVE 1U
-+#define PVR_FWIF_GPU_UTIL_STATE_BLOCKED 2U
-+#define PVR_FWIF_GPU_UTIL_STATE_NUM 3U
-+#define PVR_FWIF_GPU_UTIL_STATE_MASK 0x3ULL
-+
-+/*
-+ * Maximum amount of register writes that can be done by the register
-+ * programmer (FW or META DMA). This is not a HW limitation, it is only
-+ * a protection against malformed inputs to the register programmer.
-+ */
-+#define PVR_MAX_NUM_REGISTER_PROGRAMMER_WRITES 128U
-+
-+#endif /* __PVR_ROGUE_FWIF_COMMON_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_resetframework.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_resetframework.h
-new file mode 100644
-index 000000000000..de3e4d6114cd
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_resetframework.h
-@@ -0,0 +1,28 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_FWIF_RESETFRAMEWORK_H__
-+#define __PVR_ROGUE_FWIF_RESETFRAMEWORK_H__
-+
-+#include <linux/bits.h>
-+#include <linux/types.h>
-+
-+#include "pvr_rogue_fwif_shared.h"
-+
-+struct rogue_fwif_rf_registers {
-+ u64 cdmreg_cdm_ctrl_stream_base;
-+};
-+
-+/* enables the reset framework in the firmware */
-+#define ROGUE_FWIF_RF_FLAG_ENABLE BIT(0)
-+
-+struct rogue_fwif_rf_cmd {
-+ u32 flags;
-+
-+ /* THIS MUST BE THE LAST MEMBER OF THE CONTAINING STRUCTURE */
-+ struct rogue_fwif_rf_registers fw_registers __aligned(8);
-+};
-+
-+#define ROGUE_FWIF_RF_CMD_SIZE sizeof(struct rogue_fwif_rf_cmd)
-+
-+#endif /* __PVR_ROGUE_FWIF_RESETFRAMEWORK_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_sf.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_sf.h
-new file mode 100644
-index 000000000000..202d3ba9716b
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_sf.h
-@@ -0,0 +1,846 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_FWIF_SF_H__
-+#define __PVR_ROGUE_FWIF_SF_H__
-+
-+/*
-+ ******************************************************************************
-+ * *DO*NOT* rearrange or delete lines in SFIDLIST or SFGROUPLIST or you
-+ * WILL BREAK fw tracing message compatibility with previous
-+ * fw versions. Only add new ones, if so required.
-+ ******************************************************************************
-+ */
-+/* Available log groups. */
-+#define ROGUE_FW_LOG_SFGROUPLIST \
-+ X(ROGUE_FW_GROUP_NULL, NULL) \
-+ X(ROGUE_FW_GROUP_MAIN, MAIN) \
-+ X(ROGUE_FW_GROUP_CLEANUP, CLEANUP) \
-+ X(ROGUE_FW_GROUP_CSW, CSW) \
-+ X(ROGUE_FW_GROUP_PM, PM) \
-+ X(ROGUE_FW_GROUP_RTD, RTD) \
-+ X(ROGUE_FW_GROUP_SPM, SPM) \
-+ X(ROGUE_FW_GROUP_MTS, MTS) \
-+ X(ROGUE_FW_GROUP_BIF, BIF) \
-+ X(ROGUE_FW_GROUP_MISC, MISC) \
-+ X(ROGUE_FW_GROUP_POW, POW) \
-+ X(ROGUE_FW_GROUP_HWR, HWR) \
-+ X(ROGUE_FW_GROUP_HWP, HWP) \
-+ X(ROGUE_FW_GROUP_RPM, RPM) \
-+ X(ROGUE_FW_GROUP_DMA, DMA) \
-+ X(ROGUE_FW_GROUP_DBG, DBG)
-+
-+enum rogue_fw_log_sfgroups {
-+#define X(A, B) A,
-+ ROGUE_FW_LOG_SFGROUPLIST
-+#undef X
-+};
-+
-+#define PVR_SF_STRING_MAX_SIZE 256U
-+
-+/* pair of string format id and string formats */
-+struct rogue_fw_stid_fmt {
-+ u32 id;
-+ char name[PVR_SF_STRING_MAX_SIZE];
-+};
-+
-+/* pair of string format id and string formats */
-+struct rogue_km_stid_fmt {
-+ u32 id;
-+ const char *name;
-+};
-+
-+/*
-+ * Table of String Format specifiers, the group they belong and the number of
-+ * arguments each expects. Xmacro styled macros are used to generate what is
-+ * needed without requiring hand editing.
-+ *
-+ * id : id within a group
-+ * gid : group id
-+ * Sym name : name of enumerations used to identify message strings
-+ * String : Actual string
-+ * #args : number of arguments the string format requires
-+ */
-+#define ROGUE_FW_LOG_SFIDLIST \
-+/*id, gid, id name, string, # arguments */ \
-+X(0, ROGUE_FW_GROUP_NULL, ROGUE_FW_SF_FIRST, "You should not use this string", 0) \
-+\
-+X(1, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_3D_DEPRECATED, "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x. Partial render:%d, CSW resume:%d, prio:%d", 6) \
-+X(2, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_3D_FINISHED, "3D finished, HWRTData0State=%x, HWRTData1State=%x", 2) \
-+X(3, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK3D_TQ_DEPRECATED, "Kick 3D TQ: FWCtx 0x%08.8x @ %d, CSW resume:%d, prio: %d", 4) \
-+X(4, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_3D_TQ_FINISHED, "3D Transfer finished", 0) \
-+X(5, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_COMPUTE_DEPRECATED, "Kick Compute: FWCtx 0x%08.8x @ %d, prio: %d", 3) \
-+X(6, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_FINISHED, "Compute finished", 0) \
-+X(7, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_TA_DEPRECATED, "Kick TA: FWCtx 0x%08.8x @ %d, RTD 0x%08x. First kick:%d, Last kick:%d, CSW resume:%d, prio:%d", 7) \
-+X(8, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TA_FINISHED, "TA finished", 0) \
-+X(9, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TA_RESTART_AFTER_PRENDER, "Restart TA after partial render", 0) \
-+X(10, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TA_RESUME_WOUT_PRENDER, "Resume TA without partial render", 0) \
-+X(11, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OOM, "Out of memory! Context 0x%08x, HWRTData 0x%x", 2) \
-+X(12, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_TLA_DEPRECATED, "Kick TLA: FWCtx 0x%08.8x @ %d, prio:%d", 3) \
-+X(13, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TLA_FINISHED, "TLA finished", 0) \
-+X(14, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_CCCB_WOFF_UPDATE, "cCCB Woff update = %d, DM = %d, FWCtx = 0x%08.8x", 3) \
-+X(16, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_CHECK_START, "UFO Checks for FWCtx 0x%08.8x @ %d", 2) \
-+X(17, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_CHECK, "UFO Check: [0x%08.8x] is 0x%08.8x requires 0x%08.8x", 3) \
-+X(18, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_CHECK_SUCCEEDED, "UFO Checks succeeded", 0) \
-+X(19, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_PR_CHECK, "UFO PR-Check: [0x%08.8x] is 0x%08.8x requires >= 0x%08.8x", 3) \
-+X(20, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_SPM_PR_CHECK_START, "UFO SPM PR-Checks for FWCtx 0x%08.8x", 1) \
-+X(21, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_SPM_PR_CHECK_DEPRECATED, "UFO SPM special PR-Check: [0x%08.8x] is 0x%08.8x requires >= ????????, [0x%08.8x] is ???????? requires 0x%08.8x", 4) \
-+X(22, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_UPDATE_START, "UFO Updates for FWCtx 0x%08.8x @ %d", 2) \
-+X(23, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_UPDATE, "UFO Update: [0x%08.8x] = 0x%08.8x", 2) \
-+X(24, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_ASSERT_FAILED, "ASSERT Failed: line %d of:", 1) \
-+X(25, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_LOCKUP_DEPRECATED, "HWR: Lockup detected on DM%d, FWCtx: 0x%08.8x", 2) \
-+X(26, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_RESET_FW_DEPRECATED, "HWR: Reset fw state for DM%d, FWCtx: 0x%08.8x, MemCtx: 0x%08.8x", 3) \
-+X(27, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_RESET_HW_DEPRECATED, "HWR: Reset HW", 0) \
-+X(28, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_TERMINATED_DEPRECATED, "HWR: Lockup recovered.", 0) \
-+X(29, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_FALSE_LOCKUP_DEPRECATED, "HWR: False lockup detected for DM%u", 1) \
-+X(30, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_ALIGN_FAILED, "Alignment check %d failed: host = 0x%x, fw = 0x%x", 3) \
-+X(31, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_GP_USC_TRIGGERED, "GP USC triggered", 0) \
-+X(32, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BREAKPOINT_OVERALLOC_REGS, "Overallocating %u temporary registers and %u shared registers for breakpoint handler", 2) \
-+X(33, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BREAKPOINT_SET_DEPRECATED, "Setting breakpoint: Addr 0x%08.8x", 1) \
-+X(34, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BREAKPOINT_STORE, "Store breakpoint state", 0) \
-+X(35, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BREAKPOINT_UNSET, "Unsetting BP Registers", 0) \
-+X(36, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_NONZERO_RT, "Active RTs expected to be zero, actually %u", 1) \
-+X(37, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_RTC_PRESENT, "RTC present, %u active render targets", 1) \
-+X(38, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_EST_POWER_DEPRECATED, "Estimated Power 0x%x", 1) \
-+X(39, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_RTA_TARGET, "RTA render target %u", 1) \
-+X(40, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_RTA_KICK_RENDER, "Kick RTA render %u of %u", 2) \
-+X(41, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_SIZES_CHECK_DEPRECATED, "HWR sizes check %d failed: addresses = %d, sizes = %d", 3) \
-+X(42, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_POW_DUSTS_ENABLE_DEPRECATED, "Pow: DUSTS_ENABLE = 0x%x", 1) \
-+X(43, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_POW_HWREQ_DEPRECATED, "Pow: On(1)/Off(0): %d, Units: 0x%08.8x", 2) \
-+X(44, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_POW_DUSTS_CHANGE_DEPRECATED, "Pow: Changing number of dusts from %d to %d", 2) \
-+X(45, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_POW_SIDEKICK_IDLE_DEPRECATED, "Pow: Sidekick ready to be powered down", 0) \
-+X(46, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_POW_DUSTS_CHANGE_REQ_DEPRECATED, "Pow: Request to change num of dusts to %d (bPowRascalDust=%d)", 2) \
-+X(47, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_PARTIALRENDER_WITHOUT_ZSBUFFER_STORE, "No ZS Buffer used for partial render (store)", 0) \
-+X(48, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_PARTIALRENDER_WITHOUT_ZSBUFFER_LOAD, "No Depth/Stencil Buffer used for partial render (load)", 0) \
-+X(49, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_SET_LOCKUP_DEPRECATED, "HWR: Lock-up DM%d FWCtx: 0x%08.8x", 2) \
-+X(50, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_MLIST_CHECKER_REG_VALUE_DEPRECATED, "MLIST%d checker: CatBase TE=0x%08x (%d Pages), VCE=0x%08x (%d Pages), ALIST=0x%08x, IsTA=%d", 7) \
-+X(51, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_MLIST_CHECKER_MLIST_VALUE, "MLIST%d checker: MList[%d] = 0x%08x", 3) \
-+X(52, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_MLIST_CHECKER_OK, "MLIST%d OK", 1) \
-+X(53, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_MLIST_CHECKER_EMPTY, "MLIST%d is empty", 1) \
-+X(54, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_MLIST_CHECKER_REG_VALUE, "MLIST%d checker: CatBase TE=0x%08x%08x, VCE=0x%08x%08x, ALIST=0x%08x%08x, IsTA=%d", 8) \
-+X(55, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_3D_40480KICK, "3D OQ flush kick", 0) \
-+X(56, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWP_UNSUPPORTED_BLOCK, "HWPerf block ID (0x%x) unsupported by device", 1) \
-+X(57, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BREAKPOINT_SET_DEPRECATED2, "Setting breakpoint: Addr 0x%08.8x DM%u", 2) \
-+X(58, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_RTU_DEPRECATED, "Kick RTU: FWCtx 0x%08.8x @ %d, prio: %d", 3) \
-+X(59, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_RTU_FINISHED_DEPRECATED, "RDM finished on context %u", 1) \
-+X(60, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_SHG_DEPRECATED, "Kick SHG: FWCtx 0x%08.8x @ %d, prio: %d", 3) \
-+X(61, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SHG_FINISHED_DEPRECATED, "SHG finished", 0) \
-+X(62, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FBA_FINISHED_DEPRECATED, "FBA finished on context %u", 1) \
-+X(63, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_CHECK_FAILED, "UFO Checks failed", 0) \
-+X(64, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KILLDM_START, "Kill DM%d start", 1) \
-+X(65, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KILLDM_COMPLETE, "Kill DM%d complete", 1) \
-+X(66, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FC_CCB_UPDATE_DEPRECATED, "FC%u cCCB Woff update = %u", 2) \
-+X(67, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_RTU_DEPRECATED2, "Kick RTU: FWCtx 0x%08.8x @ %d, prio: %d, Frame Context: %d", 4) \
-+X(68, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_GPU_INIT, "GPU init", 0) \
-+X(69, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UNITS_INIT, "GPU Units init (# mask: 0x%x)", 1) \
-+X(70, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_REGTIMES, "Register access cycles: read: %d cycles, write: %d cycles, iterations: %d", 3) \
-+X(71, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_REGCONFIG_ADD, "Register configuration added. Address: 0x%x Value: 0x%x%x", 3) \
-+X(72, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_REGCONFIG_SET, "Register configuration applied to type %d. (0:pow on, 1:Rascal/dust init, 2-5: TA,3D,CDM,TLA, 6:All)", 1) \
-+X(73, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TPC_FLUSH, "Perform TPC flush.", 0) \
-+X(74, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_HIT_LOCKUP_DEPRECATED, "GPU has locked up (see HWR logs for more info)", 0) \
-+X(75, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_HIT_OUTOFTIME, "HWR has been triggered - GPU has overrun its deadline (see HWR logs)", 0) \
-+X(76, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_HIT_POLLFAILURE, "HWR has been triggered - GPU has failed a poll (see HWR logs)", 0) \
-+X(77, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_DOPPLER_OOM_DEPRECATED, "Doppler out of memory event for FC %u", 1) \
-+X(78, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_SPM_PR_CHECK1, "UFO SPM special PR-Check: [0x%08.8x] is 0x%08.8x requires >= 0x%08.8x", 3) \
-+X(79, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_SPM_PR_CHECK2, "UFO SPM special PR-Check: [0x%08.8x] is 0x%08.8x requires 0x%08.8x", 3) \
-+X(80, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TIMESTAMP, "TIMESTAMP -> [0x%08.8x]", 1) \
-+X(81, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_RMW_UPDATE_START, "UFO RMW Updates for FWCtx 0x%08.8x @ %d", 2) \
-+X(82, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_RMW_UPDATE, "UFO Update: [0x%08.8x] = 0x%08.8x", 2) \
-+X(83, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_NULLCMD, "Kick Null cmd: FWCtx 0x%08.8x @ %d", 2) \
-+X(84, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_RPM_OOM_DEPRECATED, "RPM Out of memory! Context 0x%08x, SH requestor %d", 2) \
-+X(85, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_RTU_ABORT_DISCARD_DEPRECATED, "Discard RTU due to RPM abort: FWCtx 0x%08.8x @ %d, prio: %d, Frame Context: %d", 4) \
-+X(86, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_DEFERRED, "Deferring DM%u from running context 0x%08x @ %d (deferred DMs = 0x%08x)", 4) \
-+X(87, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_DEFERRED_WAITING_TURN_DEPRECATED, "Deferring DM%u from running context 0x%08x @ %d to let other deferred DMs run (deferred DMs = 0x%08x)", 4) \
-+X(88, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_DEFERRED_NO_LONGER, "No longer deferring DM%u from running context = 0x%08x @ %d (deferred DMs = 0x%08x)", 4) \
-+X(89, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_WAITING_FOR_FWCCB_DEPRECATED, "FWCCB for DM%u is full, we will have to wait for space! (Roff = %u, Woff = %u)", 3) \
-+X(90, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_WAITING_FOR_FWCCB, "FWCCB for OSid %u is full, we will have to wait for space! (Roff = %u, Woff = %u)", 3) \
-+X(91, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SYNC_PART, "Host Sync Partition marker: %d", 1) \
-+X(92, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SYNC_PART_RPT, "Host Sync Partition repeat: %d", 1) \
-+X(93, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_CLOCK_SPEED_CHANGE, "Core clock set to %d Hz", 1) \
-+X(94, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_OFFSETS, "Compute Queue: FWCtx 0x%08.8x, prio: %d, queue: 0x%08x%08x (Roff = %u, Woff = %u, Size = %u)", 7) \
-+X(95, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SIGNAL_WAIT_FAILURE_DEPRECATED, "Signal check failed, Required Data: 0x%x, Address: 0x%08x%08x", 3) \
-+X(96, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SIGNAL_UPDATE_DEPRECATED, "Signal update, Snoop Filter: %u, MMU Ctx: %u, Signal Id: %u, Signals Base: 0x%08x%08x", 5) \
-+X(97, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FWCONTEXT_SIGNALED, "Signalled the previously waiting FWCtx: 0x%08.8x, OSId: %u, Signal Address: 0x%08x%08x", 4) \
-+X(98, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_STALLED_DEPRECATED, "Compute stalled", 0) \
-+X(99, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_STALLED, "Compute stalled (Roff = %u, Woff = %u, Size = %u)", 3) \
-+X(100, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_RESUMED_FROM_STALL, "Compute resumed (Roff = %u, Woff = %u, Size = %u)", 3) \
-+X(101, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_NOTIFY_SIGNAL_UPDATE, "Signal update notification from the host, PC Physical Address: 0x%08x%08x, Signal Virtual Address: 0x%08x%08x", 4) \
-+X(102, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SIGNAL_UPDATE_OSID_DM_DEPRECATED, "Signal update from DM: %u, OSId: %u, PC Physical Address: 0x%08x%08x", 4) \
-+X(103, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SIGNAL_WAIT_FAILURE_DM_DEPRECATED, "DM: %u signal check failed", 1) \
-+X(104, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_TDM_DEPRECATED, "Kick TDM: FWCtx 0x%08.8x @ %d, prio:%d", 3) \
-+X(105, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_FINISHED, "TDM finished", 0) \
-+X(106, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TE_PIPE_STATUS_DEPRECATED, "MMU_PM_CAT_BASE_TE[%d]_PIPE[%d]: 0x%08x 0x%08x)", 4) \
-+X(107, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BRN_54141_HIT_DEPRECATED, "BRN 54141 HIT", 0) \
-+X(108, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BRN_54141_APPLYING_DUMMY_TA_DEPRECATED, "BRN 54141 Dummy TA kicked", 0) \
-+X(109, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BRN_54141_RESUME_TA_DEPRECATED, "BRN 54141 resume TA", 0) \
-+X(110, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BRN_54141_DOUBLE_HIT_DEPRECATED, "BRN 54141 double hit after applying WA", 0) \
-+X(111, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BRN_54141_DUMMY_TA_VDM_BASE_DEPRECATED, "BRN 54141 Dummy TA VDM base address: 0x%08x%08x", 2) \
-+X(112, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SIGNAL_WAIT_FAILURE_WITH_CURRENT, "Signal check failed, Required Data: 0x%x, Current Data: 0x%x, Address: 0x%08x%08x", 4) \
-+X(113, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_BUFFER_STALL_DEPRECATED, "TDM stalled (Roff = %u, Woff = %u)", 2) \
-+X(114, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_NOTIFY_WRITE_OFFSET_UPDATE, "Write Offset update notification for stalled FWCtx 0x%08.8x", 1) \
-+X(115, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_PRIORITY_CHANGE, "Changing OSid %d's priority from %u to %u", 3) \
-+X(116, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_RESUMED, "Compute resumed", 0) \
-+X(117, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_TLA, "Kick TLA: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7) \
-+X(118, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_TDM, "Kick TDM: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7) \
-+X(119, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_TA, "Kick TA: FWCtx 0x%08.8x @ %d, RTD 0x%08x, First kick:%d, Last kick:%d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 11) \
-+X(120, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_3D, "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x, Partial render:%d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 10) \
-+X(121, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_3DTQ, "Kick 3D TQ: FWCtx 0x%08.8x @ %d, CSW resume:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 8) \
-+X(122, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_COMPUTE, "Kick Compute: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, ext:0x%08x, int:0x%08x)", 6) \
-+X(123, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_RTU_DEPRECATED3, "Kick RTU: FWCtx 0x%08.8x @ %d, Frame Context:%d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 8) \
-+X(124, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KICK_SHG_DEPRECATED2, "Kick SHG: FWCtx 0x%08.8x @ %d. (PID:%d, prio:%d, frame:%d, ext:0x%08x, int:0x%08x)", 7) \
-+X(125, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_CSRM_RECONFIG, "Reconfigure CSRM: special coeff support enable %d.", 1) \
-+X(127, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TA_REQ_MAX_COEFFS, "TA requires max coeff mode, deferring: %d.", 1) \
-+X(128, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_3D_REQ_MAX_COEFFS, "3D requires max coeff mode, deferring: %d.", 1) \
-+X(129, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KILLDM_FAILED, "Kill DM%d failed", 1) \
-+X(130, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_WAITING_FOR_QUEUE, "Thread Queue is full, we will have to wait for space! (Roff = %u, Woff = %u)", 2) \
-+X(131, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_WAITING_FOR_QUEUE_FENCE, "Thread Queue is fencing, we are waiting for Roff = %d (Roff = %u, Woff = %u)", 3) \
-+X(132, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SET_HCS_TRIGGERED, "DM %d failed to Context Switch on time. Triggered HCS (see HWR logs).", 1) \
-+X(133, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HCS_SET, "HCS changed to %d ms", 1) \
-+X(134, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UPDATE_TILES_IN_FLIGHT_DEPRECATED, "Updating Tiles In Flight (Dusts=%d, PartitionMask=0x%08x, ISPCtl=0x%08x%08x)", 4) \
-+X(135, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SET_TILES_IN_FLIGHT, " Phantom %d: USCTiles=%d", 2) \
-+X(136, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_ISOLATION_CONF_OFF, "Isolation grouping is disabled", 0) \
-+X(137, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_ISOLATION_CONF_DEPRECATED, "Isolation group configured with a priority threshold of %d", 1) \
-+X(138, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_ONLINE_DEPRECATED, "OS %d has come online", 1) \
-+X(139, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_OFFLINE_DEPRECATED, "OS %d has gone offline", 1) \
-+X(140, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FWCONTEXT_SIGNAL_REKICK, "Signalled the previously stalled FWCtx: 0x%08.8x, OSId: %u, Signal Address: 0x%08x%08x", 4) \
-+X(141, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_OFFSETS_DEPRECATED, "TDM Queue: FWCtx 0x%08.8x, prio: %d, queue: 0x%08x%08x (Roff = %u, Woff = %u, Size = %u)", 7) \
-+X(142, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_OFFSET_READ_RESET, "Reset TDM Queue Read Offset: FWCtx 0x%08.8x, queue: 0x%08x%08x (Roff = %u becomes 0, Woff = %u, Size = %u)", 6) \
-+X(143, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UMQ_MISMATCHED_READ_OFFSET, "User Mode Queue mismatched stream start: FWCtx 0x%08.8x, queue: 0x%08x%08x (Roff = %u, StreamStartOffset = %u)", 5) \
-+X(144, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_GPU_DEINIT, "GPU deinit", 0) \
-+X(145, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UNITS_DEINIT, "GPU units deinit", 0) \
-+X(146, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_INIT_CONFIG, "Initialised OS %d with config flags 0x%08x", 2) \
-+X(147, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_LIMIT, "UFO limit exceeded %d/%d", 2) \
-+X(148, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_3D_62850KICK, "3D Dummy stencil store", 0) \
-+X(149, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_INIT_CONFIG_DEPRECATED, "Initialised OS %d with config flags 0x%08x and extended config flags 0x%08x", 3) \
-+X(150, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UNKNOWN_COMMAND_DEPRECATED, "Unknown Command (eCmdType=0x%08x)", 1) \
-+X(151, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_FORCED_UPDATE, "UFO forced update: FWCtx 0x%08.8x @ %d [0x%08.8x] = 0x%08.8x", 4) \
-+X(152, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UFO_FORCED_UPDATE_NOP, "UFO forced update NOP: FWCtx 0x%08.8x @ %d [0x%08.8x] = 0x%08.8x, reason %d", 5) \
-+X(153, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_BRN66075_CHECK, "TDM context switch check: Roff %u points to 0x%08x, Match=%u", 3) \
-+X(154, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_INIT_CCBS, "OSid %d CCB init status: %d (1-ok 0-fail): kCCBCtl@0x%x kCCB@0x%x fwCCBCtl@0x%x fwCCB@0x%x", 6) \
-+X(155, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FWIRQ, "FW IRQ # %u @ %u", 2) \
-+X(156, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BREAKPOINT_SET, "Setting breakpoint: Addr 0x%08.8x DM%u usc_breakpoint_ctrl_dm = %u", 3) \
-+X(157, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INVALID_KERNEL_CCB_DEPRECATED, "Invalid KCCB setup for OSid %u: KCCB 0x%08x, KCCB Ctrl 0x%08x", 3) \
-+X(158, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INVALID_KERNEL_CCB_CMD, "Invalid KCCB cmd (%u) for OSid %u @ KCCB 0x%08x", 3) \
-+X(159, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FW_FAULT, "FW FAULT: At line %d in file 0x%08x%08x, additional data=0x%08x", 4) \
-+X(160, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_BREAKPOINT_INVALID, "Invalid breakpoint: MemCtx 0x%08x Addr 0x%08.8x DM%u usc_breakpoint_ctrl_dm = %u", 4) \
-+X(161, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FLUSHINVAL_CMD_INVALID_DEPRECATED, "Discarding invalid SLC flushinval command for OSid %u: DM %u, FWCtx 0x%08x", 3) \
-+X(162, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INVALID_NOTIFY_WRITE_OFFSET_UPDATE_DEPRECATED, "Invalid Write Offset update notification from OSid %u to DM %u: FWCtx 0x%08x, MemCtx 0x%08x", 4) \
-+X(163, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INVALID_KCCB_KICK_CMD_DEPRECATED, "Null FWCtx in KCCB kick cmd for OSid %u: KCCB 0x%08x, ROff %u, WOff %u", 4) \
-+X(164, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FULL_CHPTCCB, "Checkpoint CCB for OSid %u is full, signalling host for full check state (Roff = %u, Woff = %u)", 3) \
-+X(165, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_INIT_CCBS_DEPRECATED, "OSid %d CCB init status: %d (1-ok 0-fail): kCCBCtl@0x%x kCCB@0x%x fwCCBCtl@0x%x fwCCB@0x%x chptCCBCtl@0x%x chptCCB@0x%x", 8) \
-+X(166, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_STATE_CHANGE, "OSid %d fw state transition request: from %d to %d (0-offline 1-ready 2-active 3-offloading). Status %d (1-ok 0-fail)", 4) \
-+X(167, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_STALE_KCCB_CMDS, "OSid %u has %u stale commands in its KCCB", 2) \
-+X(168, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TA_VCE_PAUSE, "Applying VCE pause", 0) \
-+X(169, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_KCCB_UPDATE_RTN_SLOT_DEPRECATED, "OSid %u KCCB slot %u value updated to %u", 3) \
-+X(170, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UNKNOWN_KCCB_COMMAND, "Unknown KCCB Command: KCCBCtl=0x%08x, KCCB=0x%08x, Roff=%u, Woff=%u, Wrap=%u, Cmd=0x%08x, CmdType=0x%08x", 7) \
-+X(171, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UNKNOWN_CCB_COMMAND1, "Unknown Client CCB Command processing fences: FWCtx=0x%08x, CCBCtl=0x%08x, CCB=0x%08x, Roff=%u, Doff=%u, Woff=%u, Wrap=%u, CmdHdr=0x%08x, CmdType=0x%08x, CmdSize=%u", 10) \
-+X(172, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UNKNOWN_CCB_COMMAND2, "Unknown Client CCB Command executing kick: FWCtx=0x%08x, CCBCtl=0x%08x, CCB=0x%08x, Roff=%u, Doff=%u, Woff=%u, Wrap=%u, CmdHdr=0x%08x, CmdType=0x%08x, CmdSize=%u", 10) \
-+X(173, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INVALID_KCCB_KICK_CMD, "Null FWCtx in KCCB kick cmd for OSid %u with WOff %u", 2) \
-+X(174, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FLUSHINVAL_CMD_INVALID, "Discarding invalid SLC flushinval command for OSid %u, FWCtx 0x%08x", 2) \
-+X(175, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INVALID_NOTIFY_WRITE_OFFSET_UPDATE, "Invalid Write Offset update notification from OSid %u: FWCtx 0x%08x, MemCtx 0x%08x", 3) \
-+X(176, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FW_INIT_CONFIG, "Initialised Firmware with config flags 0x%08x and extended config flags 0x%08x", 2) \
-+X(177, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_PHR_CONFIG, "Set Periodic Hardware Reset Mode: %d", 1) \
-+X(179, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_PHR_TRIG, "PHR mode %d, FW state: 0x%08x, HWR flags: 0x%08x", 3) \
-+X(180, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_PHR_RESET_DEPRECATED, "PHR mode %d triggered a reset", 1) \
-+X(181, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SIGNAL_UPDATE, "Signal update, Snoop Filter: %u, Signal Id: %u", 2) \
-+X(182, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FIXME_SERIES8, "WARNING: Skipping FW KCCB Cmd type %d which is not yet supported on Series8.", 1) \
-+X(183, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INCONSISTENT_MMU_FLAGS, "MMU context cache data NULL, but cache flags=0x%x (sync counter=%u, update value=%u) OSId=%u", 4) \
-+X(184, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SLC_FLUSH, "SLC range based flush: Context=%u VAddr=0x%02x%08x, Size=0x%08x, Invalidate=%d", 5) \
-+X(185, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FBSC_INVAL, "FBSC invalidate for Context [0x%08x]: Entry mask 0x%08x%08x.", 3) \
-+X(186, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_BRN66284_UPDATE, "TDM context switch check: Roff %u was not valid for kick starting at %u, moving back to %u", 3) \
-+X(187, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SPFILTER_UPDATES, "Signal updates: FIFO: %u, Signals: 0x%08x", 2) \
-+X(188, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INVALID_FBSC_CMD, "Invalid FBSC cmd: FWCtx 0x%08x, MemCtx 0x%08x", 2) \
-+X(189, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_BRN68497_BLIT, "Insert BRN68497 WA blit after TDM Context store.", 0) \
-+X(190, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_PENDING_UFO_UPDATE_START, "UFO Updates for previously finished FWCtx 0x%08.8x", 1) \
-+X(191, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_RTC_RTA_PRESENT, "RTC with RTA present, %u active render targets", 1) \
-+X(192, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_NULL_RTAS, "Invalid RTA Set-up. The ValidRenderTargets array in RTACtl is Null!", 0) \
-+X(193, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_INVALID_COUNTER, "Block 0x%x / Counter 0x%x INVALID and ignored", 2) \
-+X(194, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_ECC_FAULT_DEPRECATED, "ECC fault GPU=0x%08x FW=0x%08x", 2) \
-+X(195, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_PROCESS_XPU_EVENT, "Processing XPU event on DM = %d", 1) \
-+X(196, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_VZ_WDG_TRIGGER, "OSid %u failed to respond to the virtualisation watchdog in time. Timestamp of its last input = %u", 2) \
-+X(197, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_HIT_LOCKUP, "GPU-%u has locked up (see HWR logs for more info)", 1) \
-+X(198, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UPDATE_TILES_IN_FLIGHT, "Updating Tiles In Flight (Dusts=%d, PartitionMask=0x%08x, ISPCtl=0x%08x)", 3) \
-+X(199, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_HWR_HIT_LOCKUP_DM, "GPU has locked up (see HWR logs for more info)", 0) \
-+X(200, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_REPROCESS_XPU_EVENTS, "Reprocessing outstanding XPU events from cores 0x%02x", 1) \
-+X(201, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SECONDARY_XPU_EVENT, "Secondary XPU event on DM=%d, CoreMask=0x%02x, Raised=0x%02x", 3) \
-+X(202, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_OFFSETS, "TDM Queue: Core %u, FWCtx 0x%08.8x, prio: %d, queue: 0x%08x%08x (Roff = %u, Woff = %u, Size = %u)", 8) \
-+X(203, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_BUFFER_STALL, "TDM stalled Core %u (Roff = %u, Woff = %u)", 3) \
-+X(204, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_CORE_OFFSETS, "Compute Queue: Core %u, FWCtx 0x%08.8x, prio: %d, queue: 0x%08x%08x (Roff = %u, Woff = %u, Size = %u)", 8) \
-+X(205, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_CORE_STALLED, "Compute stalled core %u (Roff = %u, Woff = %u, Size = %u)", 4) \
-+X(206, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_UMQ_MISMATCHED_CORE_READ_OFFSET, "User Mode Queue mismatched stream start: Core %u, FWCtx 0x%08.8x, queue: 0x%08x%08x (Roff = %u, StreamStartOffset = %u)", 6) \
-+X(207, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TDM_RESUMED_FROM_STALL, "TDM resumed core %u (Roff = %u, Woff = %u)", 3) \
-+X(208, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_COMPUTE_CORE_RESUMED_FROM_STALL, "Compute resumed core %u (Roff = %u, Woff = %u, Size = %u)", 4) \
-+X(209, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_OS_MTS_PERMISSION_CHANGED, " Updated permission for OSid %u to perform MTS kicks: %u (1 = allowed, 0 = not allowed)", 2) \
-+X(210, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TEST1, "Mask = 0x%X, mask2 = 0x%X", 2) \
-+X(211, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_TEST2, " core %u, reg = %u, mask = 0x%X)", 3) \
-+X(212, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_ECC_FAULT_SAFETY_BUS, "ECC fault received from safety bus: 0x%08x", 1) \
-+X(213, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SAFETY_WDG_CONFIG, "Safety Watchdog threshold period set to 0x%x clock cycles", 1) \
-+X(214, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_SAFETY_WDG_TRIGGER, "MTS Safety Event trigged by the safety watchdog.", 0) \
-+X(215, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_USC_TASKS_RANGE, "DM%d USC tasks range limit 0 - %d, stride %d", 3) \
-+X(216, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_GPU_ECC_FAULT, "ECC fault GPU=0x%08x", 1) \
-+X(217, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_GPU_SAFETY_RESET, "GPU Hardware units reset to prevent transient faults.", 0) \
-+X(221, ROGUE_FW_GROUP_MAIN, ROGUE_FW_SF_MAIN_FWDATA_INIT_STATUS, "State of firmware's private data at boot time: %d (0 = uninitialised, 1 = initialised); Fw State Flags = 0x%08X", 2) \
-+\
-+X(1, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_BG_KICK_DEPRECATED, "Bg Task DM = %u, counted = %d", 2) \
-+X(2, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_BG_COMPLETE_DEPRECATED, "Bg Task complete DM = %u", 1) \
-+X(3, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_IRQ_KICK, "Irq Task DM = %u, Breq = %d, SBIrq = 0x%x", 3) \
-+X(4, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_IRQ_COMPLETE_DEPRECATED, "Irq Task complete DM = %u", 1) \
-+X(5, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_KICK_MTS_BG_ALL_DEPRECATED, "Kick MTS Bg task DM=All", 0) \
-+X(6, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_KICK_MTS_IRQ, "Kick MTS Irq task DM=%d", 1) \
-+X(7, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_READYCELLTYPE_DEPRECATED, "Ready queue debug DM = %u, celltype = %d", 2) \
-+X(8, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_READYTORUN_DEPRECATED, "Ready-to-run debug DM = %u, item = 0x%x", 2) \
-+X(9, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_CMDHEADER, "Client command header DM = %u, client CCB = 0x%x, cmd = 0x%x", 3) \
-+X(10, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_READYTORUN, "Ready-to-run debug OSid = %u, DM = %u, item = 0x%x", 3) \
-+X(11, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_READYCELLTYPE_DEPRECATED2, "Ready queue debug DM = %u, celltype = %d, OSid = %u", 3) \
-+X(12, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_BG_KICK_DEPRECATED2, "Bg Task DM = %u, counted = %d, OSid = %u", 3) \
-+X(13, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_BG_COMPLETE, "Bg Task complete DM Bitfield: %u", 1) \
-+X(14, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_IRQ_COMPLETE, "Irq Task complete.", 0) \
-+X(15, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_CMD_DISCARD, "Discarded Command Type: %d OS ID = %d PID = %d context = 0x%08x cccb ROff = 0x%x, due to USC breakpoint hit by OS ID = %d PID = %d.", 7) \
-+X(16, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_KCCBCMD_EXEC_DEPRECATED, "KCCB Slot %u: DM=%u, Cmd=0x%08x, OSid=%u", 4) \
-+X(17, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_KCCBCMD_RTN_VALUE, "KCCB Slot %u: Return value %u", 2) \
-+X(18, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_BG_KICK, "Bg Task OSid = %u", 1) \
-+X(19, ROGUE_FW_GROUP_MTS, ROGUE_FW_SF_MTS_KCCBCMD_EXEC, "KCCB Slot %u: Cmd=0x%08x, OSid=%u", 3) \
-+\
-+X(1, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_FWCTX_CLEANUP, "FwCommonContext [0x%08x] cleaned", 1) \
-+X(2, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_FWCTX_BUSY, "FwCommonContext [0x%08x] is busy: ReadOffset = %d, WriteOffset = %d", 3) \
-+X(3, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRTD_CLEANUP_DEPRECATED, "HWRTData [0x%08x] for DM=%d, received cleanup request", 2) \
-+X(4, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRTD_CLEANED_FOR_DM_DEPRECATED, "HWRTData [0x%08x] HW Context cleaned for DM%u, executed commands = %d", 3) \
-+X(5, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRTD_BUSY_DEPRECATED, "HWRTData [0x%08x] HW Context for DM%u is busy", 2) \
-+X(6, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRTD_CLEANED_DEPRECATED, "HWRTData [0x%08x] HW Context %u cleaned", 2) \
-+X(7, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_FL_CLEANED, "Freelist [0x%08x] cleaned", 1) \
-+X(8, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_ZSBUFFER_CLEANED, "ZSBuffer [0x%08x] cleaned", 1) \
-+X(9, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_ZSBUFFER_BUSY, "ZSBuffer [0x%08x] is busy: submitted = %d, executed = %d", 3) \
-+X(10, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRTD_BUSY_DEPRECATED2, "HWRTData [0x%08x] HW Context for DM%u is busy: submitted = %d, executed = %d", 4) \
-+X(11, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRFD_CLEANUP_DEPRECATED, "HW Ray Frame data [0x%08x] for DM=%d, received cleanup request", 2) \
-+X(12, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRFD_CLEANED_FOR_DM_DEPRECATED, "HW Ray Frame Data [0x%08x] cleaned for DM%u, executed commands = %d", 3) \
-+X(13, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRFD_BUSY_DEPRECATED, "HW Ray Frame Data [0x%08x] for DM%u is busy: submitted = %d, executed = %d", 4) \
-+X(14, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRFD_CLEANED_DEPRECATED, "HW Ray Frame Data [0x%08x] HW Context %u cleaned", 2) \
-+X(15, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_INVALID_REQUEST, "Discarding invalid cleanup request of type 0x%x", 1) \
-+X(16, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRTD_CLEANUP, "Received cleanup request for HWRTData [0x%08x]", 1) \
-+X(17, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRTD_BUSY, "HWRTData [0x%08x] HW Context is busy: submitted = %d, executed = %d", 3) \
-+X(18, ROGUE_FW_GROUP_CLEANUP, ROGUE_FW_SF_CLEANUP_HWRTD_CLEANED, "HWRTData [0x%08x] HW Context %u cleaned, executed commands = %d", 3) \
-+\
-+X(1, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_CDM_NEEDS_RESUME, "CDM FWCtx 0x%08.8x needs resume", 1) \
-+X(2, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_CDM_RESUME_DEPRECATED, "*** CDM FWCtx 0x%08.8x resume from snapshot buffer 0x%08x%08x", 3) \
-+X(3, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_CDM_SHARED, "CDM FWCtx shared alloc size load 0x%x", 1) \
-+X(4, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_CDM_STORE_COMPLETE, "*** CDM FWCtx store complete", 0) \
-+X(5, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_CDM_STORE_START, "*** CDM FWCtx store start", 0) \
-+X(6, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_CDM_SOFT_RESET, "CDM Soft Reset", 0) \
-+X(7, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_NEEDS_RESUME, "3D FWCtx 0x%08.8x needs resume", 1) \
-+X(8, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_RESUME, "*** 3D FWCtx 0x%08.8x resume", 1) \
-+X(9, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_STORE_COMPLETE, "*** 3D context store complete", 0) \
-+X(10, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_STORE_PIPE_STATE_DEPRECATED, "3D context store pipe state: 0x%08.8x 0x%08.8x 0x%08.8x", 3) \
-+X(11, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_STORE_START, "*** 3D context store start", 0) \
-+X(12, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_TQ_RESUME, "*** 3D TQ FWCtx 0x%08.8x resume", 1) \
-+X(13, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_NEEDS_RESUME, "TA FWCtx 0x%08.8x needs resume", 1) \
-+X(14, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_RESUME, "*** TA FWCtx 0x%08.8x resume from snapshot buffer 0x%08x%08x", 3) \
-+X(15, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_SHARED, "TA context shared alloc size store 0x%x, load 0x%x", 2) \
-+X(16, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_STORE_COMPLETE, "*** TA context store complete", 0) \
-+X(17, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_STORE_START, "*** TA context store start", 0) \
-+X(18, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_HIGHER_PRIORITY_SCHEDULED_DEPRECATED, "Higher priority context scheduled for DM %u, old prio:%d, new prio:%d", 3) \
-+X(19, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_SET_CONTEXT_PRIORITY, "Set FWCtx 0x%x priority to %u", 2) \
-+X(20, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_STORE_PIPE_STATE_DEPRECATED2, "3D context store pipe%d state: 0x%08.8x", 2) \
-+X(21, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_RESUME_PIPE_STATE_DEPRECATED, "3D context resume pipe%d state: 0x%08.8x", 2) \
-+X(22, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_SHG_NEEDS_RESUME_DEPRECATED, "SHG FWCtx 0x%08.8x needs resume", 1) \
-+X(23, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_SHG_RESUME_DEPRECATED, "*** SHG FWCtx 0x%08.8x resume from snapshot buffer 0x%08x%08x", 3) \
-+X(24, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_SHG_SHARED_DEPRECATED, "SHG context shared alloc size store 0x%x, load 0x%x", 2) \
-+X(25, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_SHG_STORE_COMPLETE_DEPRECATED, "*** SHG context store complete", 0) \
-+X(26, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_SHG_STORE_START_DEPRECATED, "*** SHG context store start", 0) \
-+X(27, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_PIPE_INDIRECT, "Performing TA indirection, last used pipe %d", 1) \
-+X(28, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_CDM_STORE_CTRL_STREAM_TERMINATE, "CDM context store hit ctrl stream terminate. Skip resume.", 0) \
-+X(29, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_CDM_RESUME_AB_BUFFER, "*** CDM FWCtx 0x%08.8x resume from snapshot buffer 0x%08x%08x, shader state %u", 4) \
-+X(30, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_STATE_BUFFER_FLIP, "TA PDS/USC state buffer flip (%d->%d)", 2) \
-+X(31, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_STORE_52563_HIT_DEPRECATED, "TA context store hit BRN 52563: vertex store tasks outstanding", 0) \
-+X(32, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_STORE_USC_POLL_FAILED, "TA USC poll failed (USC vertex task count: %d)", 1) \
-+X(33, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TA_STORE_DEFERRED_DEPRECATED, "TA context store deferred due to BRN 54141.", 0) \
-+X(34, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_HIGHER_PRIORITY_SCHEDULED_DEPRECATED2, "Higher priority context scheduled for DM %u. Prios (OSid, OSid Prio, Context Prio): Current: %u, %u, %u New: %u, %u, %u", 7) \
-+X(35, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TDM_STORE_START, "*** TDM context store start", 0) \
-+X(36, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TDM_STORE_COMPLETE, "*** TDM context store complete", 0) \
-+X(37, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TDM_STORE_NEEDS_RESUME_DEPRECATED, "TDM context needs resume, header [0x%08.8x, 0x%08.8x]", 2) \
-+X(38, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_HIGHER_PRIORITY_SCHEDULED, "Higher priority context scheduled for DM %u. Prios (OSid, OSid Prio, Context Prio): Current: %u, %u, %u New: %u, %u, %u. Hard Context Switching: %u", 8) \
-+X(39, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_STORE_PIPE_STATE, "3D context store pipe %2d (%2d) state: 0x%08.8x", 3) \
-+X(40, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_RESUME_PIPE_STATE, "3D context resume pipe %2d (%2d) state: 0x%08.8x", 3) \
-+X(41, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_STORE_START_VOLCANIC, "*** 3D context store start version %d (1=IPP_TILE, 2=ISP_TILE)", 1) \
-+X(42, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_STORE_PIPE_STATE_VOLCANIC, "3D context store pipe%d state: 0x%08.8x%08x", 3) \
-+X(43, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_RESUME_PIPE_STATE_VOLCANIC, "3D context resume pipe%d state: 0x%08.8x%08x", 3) \
-+X(44, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_RESUME_IPP_STATE, "3D context resume IPP state: 0x%08.8x%08x", 2) \
-+X(45, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_PIPES_EMPTY, "All 3D pipes empty after ISP tile mode store! IPP_status: 0x%08x", 1) \
-+X(46, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TDM_RESUME_PIPE_STATE_DEPRECATED, "TDM context resume pipe%d state: 0x%08.8x%08x", 3) \
-+X(47, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_3D_LEVEL4_STORE_START, "*** 3D context store start version 4", 0) \
-+X(48, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_RESUME_MULTICORE, "Multicore context resume on DM%d active core mask 0x%04.4x", 2) \
-+X(49, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_STORE_MULTICORE, "Multicore context store on DM%d active core mask 0x%04.4x", 2) \
-+X(50, ROGUE_FW_GROUP_CSW, ROGUE_FW_SF_CSW_TDM_RESUME_PIPE_STATE, "TDM context resume Core %d, pipe%d state: 0x%08.8x%08x%08x", 5) \
-+\
-+X(1, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_ACTIVATE_BIFREQ_DEPRECATED, "Activate MemCtx=0x%08x BIFreq=%d secure=%d", 3) \
-+X(2, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_DEACTIVATE, "Deactivate MemCtx=0x%08x", 1) \
-+X(3, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_PCREG_ALLOC, "Alloc PC reg %d", 1) \
-+X(4, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_PCREG_GRAB, "Grab reg %d refcount now %d", 2) \
-+X(5, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_PCREG_UNGRAB, "Ungrab reg %d refcount now %d", 2) \
-+X(6, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_SETUP_REG_BIFREQ_DEPRECATED, "Setup reg=%d BIFreq=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \
-+X(7, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_TRUST_DEPRECATED, "Trust enabled:%d, for BIFreq=%d", 2) \
-+X(8, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_TILECFG_DEPRECATED, "BIF Tiling Cfg %d base 0x%08x%08x len 0x%08x%08x enable %d stride %d --> 0x%08x%08x", 9) \
-+X(9, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_OSID0, "Wrote the Value %d to OSID0, Cat Base %d, Register's contents are now 0x%08x 0x%08x", 4) \
-+X(10, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_OSID1, "Wrote the Value %d to OSID1, Context %d, Register's contents are now 0x%04x", 3) \
-+X(11, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_OSIDx, "ui32OSid = %u, Catbase = %u, Reg Address = 0x%x, Reg index = %u, Bitshift index = %u, Val = 0x%08x%08x", 7) \
-+X(12, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_MAP_GPU_MEMORY_BIFREQ_DEPRECATED, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u, BIFREQ %u", 5) \
-+X(13, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_UNMAP_GPU_MEMORY, "Unmap GPU memory (event status 0x%x)", 1) \
-+X(14, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_ACTIVATE_DM, "Activate MemCtx=0x%08x DM=%d secure=%d", 3) \
-+X(15, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_SETUP_REG_DM, "Setup reg=%d DM=%d, expect=0x%08x%08x, actual=0x%08x%08x", 6) \
-+X(16, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_MAP_GPU_MEMORY, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u", 4) \
-+X(17, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_TRUST_DM, "Trust enabled:%d, for DM=%d", 2) \
-+X(18, ROGUE_FW_GROUP_BIF, ROGUE_FW_SF_BIF_MAP_GPU_MEMORY_DM, "Map GPU memory DevVAddr 0x%x%08x, Size %u, Context ID %u, DM %u", 5) \
-+\
-+X(1, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_WRITE, "GPIO write 0x%02x", 1) \
-+X(2, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_READ, "GPIO read 0x%02x", 1) \
-+X(3, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_ENABLED, "GPIO enabled", 0) \
-+X(4, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_DISABLED, "GPIO disabled", 0) \
-+X(5, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_STATUS, "GPIO status=%d (0=OK, 1=Disabled)", 1) \
-+X(6, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_AP_READ, "GPIO_AP: Read address=0x%02x (%d byte(s))", 2) \
-+X(7, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_AP_WRITE, "GPIO_AP: Write address=0x%02x (%d byte(s))", 2) \
-+X(8, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_AP_TIMEOUT, "GPIO_AP timeout!", 0) \
-+X(9, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_AP_ERROR, "GPIO_AP error. GPIO status=%d (0=OK, 1=Disabled)", 1) \
-+X(10, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_GPIO_ALREADY_READ, "GPIO already read 0x%02x", 1) \
-+X(11, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_CHECK_BUFFER_AVAILABLE, "SR: Check buffer %d available returned %d", 2) \
-+X(12, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_WAITING_BUFFER_AVAILABLE, "SR: Waiting for buffer %d", 1) \
-+X(13, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_WAIT_BUFFER_TIMEOUT, "SR: Timeout waiting for buffer %d (after %d ticks)", 2) \
-+X(14, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_SKIP_FRAME_CHECK, "SR: Skip frame check for strip %d returned %d (0=No skip, 1=Skip frame)", 2) \
-+X(15, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_SKIP_REMAINING_STRIPS, "SR: Skip remaining strip %d in frame", 1) \
-+X(16, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_FRAME_SKIP_NEW_FRAME, "SR: Inform HW that strip %d is a new frame", 1) \
-+X(17, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_SKIP_FRAME_TIMEOUT, "SR: Timeout waiting for INTERRUPT_FRAME_SKIP (after %d ticks)", 1) \
-+X(18, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_STRIP_MODE, "SR: Strip mode is %d", 1) \
-+X(19, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_STRIP_INDEX, "SR: Strip Render start (strip %d)", 1) \
-+X(20, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_BUFFER_RENDERED, "SR: Strip Render complete (buffer %d)", 1) \
-+X(21, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SR_BUFFER_FAULT, "SR: Strip Render fault (buffer %d)", 1) \
-+X(22, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_TRP_STATE, "TRP state: %d", 1) \
-+X(23, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_TRP_FAILURE, "TRP failure: %d", 1) \
-+X(24, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SW_TRP_STATE, "SW TRP State: %d", 1) \
-+X(25, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_SW_TRP_FAILURE, "SW TRP failure: %d", 1) \
-+X(26, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_HW_KICK, "HW kick event (%u)", 1) \
-+X(27, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_WGP_CHECKSUMS, "GPU core (%u/%u): checksum 0x%08x vs. 0x%08x", 4) \
-+X(28, ROGUE_FW_GROUP_MISC, ROGUE_FW_SF_MISC_WGP_UNIT_CHECKSUMS, "GPU core (%u/%u), unit (%u,%u): checksum 0x%08x vs. 0x%08x", 6) \
-+\
-+X(1, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_AMLIST, "ALIST%d SP = %u, MLIST%d SP = %u (VCE 0x%08x%08x, TE 0x%08x%08x, ALIST 0x%08x%08x)", 10) \
-+X(2, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_SHARED_DEPRECATED, "Is TA: %d, finished: %d on HW %u (HWRTData = 0x%08x, MemCtx = 0x%08x). FL different between TA/3D: global:%d, local:%d, mmu:%d", 8) \
-+X(3, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_3DBASE_DEPRECATED, "UFL-3D-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u), FL-3D-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u), MFL-3D-Base: 0x%08x%08x (SP = %u, 4PT = %u)", 14) \
-+X(4, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_TABASE_DEPRECATED, "UFL-TA-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u), FL-TA-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u), MFL-TA-Base: 0x%08x%08x (SP = %u, 4PT = %u)", 14) \
-+X(5, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_FL_GROW_COMPLETE_DEPRECATED, "Freelist grow completed [0x%08x]: added pages 0x%08x, total pages 0x%08x, new DevVirtAddr 0x%08x%08x", 5) \
-+X(6, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_FL_GROW_DENIED_DEPRECATED, "Grow for freelist ID=0x%08x denied by host", 1) \
-+X(7, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_FL_UPDATE_COMPLETE, "Freelist update completed [0x%08x]: old total pages 0x%08x, new total pages 0x%08x, new DevVirtAddr 0x%08x%08x", 5) \
-+X(8, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_FL_RECONSTRUCTION_FAILED_DEPRECATED, "Reconstruction of freelist ID=0x%08x failed", 1) \
-+X(9, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_DM_PAUSE_WARNING, "Ignored attempt to pause or unpause the DM while there is no relevant operation in progress (0-TA,1-3D): %d, operation(0-unpause, 1-pause): %d", 2) \
-+X(10, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_3D_TIMEOUT_STATUS, "Force free 3D Context memory, FWCtx: 0x%08x, status(1:success, 0:fail): %d", 2)\
-+X(11, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_DM_PAUSE_ALLOC, "PM pause TA ALLOC: PM_PAGE_MANAGEOP set to 0x%x", 1) \
-+X(12, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_DM_UNPAUSE_ALLOC, "PM unpause TA ALLOC: PM_PAGE_MANAGEOP set to 0x%x", 1) \
-+X(13, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_DM_PAUSE_DALLOC, "PM pause 3D DALLOC: PM_PAGE_MANAGEOP set to 0x%x", 1) \
-+X(14, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_DM_UNPAUSE_DALLOC, "PM unpause 3D DALLOC: PM_PAGE_MANAGEOP set to 0x%x", 1) \
-+X(15, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_DM_PAUSE_FAILED, "PM ALLOC/DALLOC change was not actioned: PM_PAGE_MANAGEOP_STATUS=0x%x", 1) \
-+X(16, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_SHARED, "Is TA: %d, finished: %d on HW %u (HWRTData = 0x%08x, MemCtx = 0x%08x). FL different between TA/3D: global:%d, local:%d", 7) \
-+X(17, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_3DBASE, "UFL-3D-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u), FL-3D-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u)", 10) \
-+X(18, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_TABASE, "UFL-TA-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u), FL-TA-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u)", 10) \
-+X(19, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_FL_UPDATE_COMPLETE_VOLCANIC, "Freelist update completed [0x%08x / FL State 0x%08x%08x]: old total pages 0x%08x, new total pages 0x%08x, new DevVirtAddr 0x%08x%08x", 7) \
-+X(20, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_FL_UPDATE_FAILED, "Freelist update failed [0x%08x / FL State 0x%08x%08x]: old total pages 0x%08x, new total pages 0x%08x, new DevVirtAddr 0x%08x%08x", 7) \
-+X(21, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_3DBASE_VOLCANIC, "UFL-3D-State-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u), FL-3D-State-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u)", 10) \
-+X(22, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_TABASE_VOLCANIC, "UFL-TA-State-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u), FL-TA-State-Base: 0x%08x%08x (SP = %u, 4PB = %u, 4PT = %u)", 10) \
-+X(23, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_CHECK_FL_BASEADDR, "Freelist 0x%08x base address from HW: 0x%02x%08x (expected value: 0x%02x%08x)", 5) \
-+X(24, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_ANALYSE_FL_GROW, "Analysis of FL grow: Pause=(%u,%u) Paused+Valid(%u,%u) PMStateBuffer=0x%x", 5) \
-+X(25, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_ATTEMPT_FL_GROW, "Attempt FL grow for FL: 0x%08x, new dev address: 0x%02x%08x, new page count: %u, new ready count: %u", 5) \
-+X(26, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_DEFER_FL_GROW, "Deferring FL grow for non-loaded FL: 0x%08x, new dev address: 0x%02x%08x, new page count: %u, new ready count: %u", 5) \
-+X(27, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_UFL_SHARED_ALBIORIX, "Is GEOM: %d, finished: %d (HWRTData = 0x%08x, MemCtx = 0x%08x)", 4) \
-+X(28, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_3D_TIMEOUT, "3D Timeout Now for FWCtx 0x%08.8x", 1) \
-+X(29, ROGUE_FW_GROUP_PM, ROGUE_FW_SF_PM_RECYCLE, "GEOM PM Recycle for FWCtx 0x%08.8x", 1) \
-+\
-+X(1, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_GLL_DYNAMIC_STATUS_DEPRECATED, "Global link list dynamic page count: vertex 0x%x, varying 0x%x, node 0x%x", 3) \
-+X(2, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_GLL_STATIC_STATUS_DEPRECATED, "Global link list static page count: vertex 0x%x, varying 0x%x, node 0x%x", 3) \
-+X(3, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_STATE_WAIT_FOR_GROW_DEPRECATED, "RPM request failed. Waiting for freelist grow.", 0) \
-+X(4, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_STATE_ABORT_DEPRECATED, "RPM request failed. Aborting the current frame.", 0) \
-+X(5, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_STATE_WAIT_FOR_PENDING_GROW_DEPRECATED, "RPM waiting for pending grow on freelist 0x%08x", 1) \
-+X(6, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_REQUEST_HOST_GROW_DEPRECATED, "Request freelist grow [0x%08x] current pages %d, grow size %d", 3) \
-+X(7, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_FREELIST_LOAD_DEPRECATED, "Freelist load: SHF = 0x%08x, SHG = 0x%08x", 2) \
-+X(8, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_SHF_FPL_DEPRECATED, "SHF FPL register: 0x%08x.0x%08x", 2) \
-+X(9, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_SHG_FPL_DEPRECATED, "SHG FPL register: 0x%08x.0x%08x", 2) \
-+X(10, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_GROW_FREELIST_DEPRECATED, "Kernel requested RPM grow on freelist (type %d) at 0x%08x from current size %d to new size %d, RPM restart: %d (1=Yes)", 5) \
-+X(11, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_GROW_RESTART_DEPRECATED, "Restarting SHG", 0) \
-+X(12, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_GROW_ABORTED_DEPRECATED, "Grow failed, aborting the current frame.", 0) \
-+X(13, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_ABORT_COMPLETE_DEPRECATED, "RPM abort complete on HWFrameData [0x%08x].", 1) \
-+X(14, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_CLEANUP_NEEDS_ABORT_DEPRECATED, "RPM freelist cleanup [0x%08x] requires abort to proceed.", 1) \
-+X(15, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_RPM_PT_DEPRECATED, "RPM page table base register: 0x%08x.0x%08x", 2) \
-+X(16, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_OOM_ABORT_DEPRECATED, "Issuing RPM abort.", 0) \
-+X(17, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_OOM_TOGGLE_CHECK_FULL_DEPRECATED, "RPM OOM received but toggle bits indicate free pages available", 0) \
-+X(18, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_STATE_HW_TIMEOUT_DEPRECATED, "RPM hardware timeout. Unable to process OOM event.", 0) \
-+X(19, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_SHF_FPL_LOAD_DEPRECATED_DEPRECATED, "SHF FL (0x%08x) load, FPL: 0x%08x.0x%08x, roff: 0x%08x, woff: 0x%08x", 5) \
-+X(20, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_SHG_FPL_LOAD_DEPRECATED, "SHG FL (0x%08x) load, FPL: 0x%08x.0x%08x, roff: 0x%08x, woff: 0x%08x", 5) \
-+X(21, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_SHF_FPL_STORE_DEPRECATED, "SHF FL (0x%08x) store, roff: 0x%08x, woff: 0x%08x", 3) \
-+X(22, ROGUE_FW_GROUP_RPM, ROGUE_FW_SF_RPM_SHG_FPL_STORE_DEPRECATED, "SHG FL (0x%08x) store, roff: 0x%08x, woff: 0x%08x", 3) \
-+\
-+X(1, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_3D_RTDATA_FINISHED, "3D RTData 0x%08x finished on HW context %u", 2) \
-+X(2, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_3D_RTDATA_READY, "3D RTData 0x%08x ready on HW context %u", 2) \
-+X(3, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_PB_SET_TO_DEPRECATED, "CONTEXT_PB_BASE set to 0x%x, FL different between TA/3D: local: %d, global: %d, mmu: %d", 4) \
-+X(4, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_LOADVFP_3D_DEPRECATED, "Loading VFP table 0x%08x%08x for 3D", 2) \
-+X(5, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_LOADVFP_TA_DEPRECATED, "Loading VFP table 0x%08x%08x for TA", 2) \
-+X(6, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_LOAD_FL_DEPRECATED, "Load Freelist 0x%x type: %d (0:local,1:global,2:mmu) for DM%d: TotalPMPages = %d, FL-addr = 0x%08x%08x, stacktop = 0x%08x%08x, Alloc Page Count = %u, Alloc MMU Page Count = %u", 10) \
-+X(7, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_VHEAP_STORE, "Perform VHEAP table store", 0) \
-+X(8, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_RTDATA_MATCH_FOUND, "RTData 0x%08x: found match in Context=%d: Load=No, Store=No", 2) \
-+X(9, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_RTDATA_NULL_FOUND, "RTData 0x%08x: found NULL in Context=%d: Load=Yes, Store=No", 2) \
-+X(10, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_RTDATA_3D_FINISHED, "RTData 0x%08x: found state 3D finished (0x%08x) in Context=%d: Load=Yes, Store=Yes", 3) \
-+X(11, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_RTDATA_TA_FINISHED, "RTData 0x%08x: found state TA finished (0x%08x) in Context=%d: Load=Yes, Store=Yes", 3) \
-+X(12, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_LOAD_STACK_POINTERS, "Loading stack-pointers for %d (0:MidTA,1:3D) on context %d, MLIST = 0x%08x, ALIST = 0x%08x%08x", 5) \
-+X(13, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_STORE_PB_DEPRECATED, "Store Freelist 0x%x type: %d (0:local,1:global,2:mmu) for DM%d: TotalPMPages = %d, FL-addr = 0x%08x%08x, stacktop = 0x%08x%08x, Alloc Page Count = %u, Alloc MMU Page Count = %u", 10) \
-+X(14, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_TA_RTDATA_FINISHED, "TA RTData 0x%08x finished on HW context %u", 2) \
-+X(15, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_TA_RTDATA_LOADED, "TA RTData 0x%08x loaded on HW context %u", 2) \
-+X(16, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_STORE_PB_DEPRECATED2, "Store Freelist 0x%x type: %d (0:local,1:global,2:mmu) for DM%d: FL Total Pages %u (max=%u,grow size=%u), FL-addr = 0x%08x%08x, stacktop = 0x%08x%08x, Alloc Page Count = %u, Alloc MMU Page Count = %u", 12) \
-+X(17, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_LOAD_FL_DEPRECATED2, "Load Freelist 0x%x type: %d (0:local,1:global,2:mmu) for DM%d: FL Total Pages %u (max=%u,grow size=%u), FL-addr = 0x%08x%08x, stacktop = 0x%08x%08x, Alloc Page Count = %u, Alloc MMU Page Count = %u", 12) \
-+X(18, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_DEBUG_DEPRECATED, "Freelist 0x%x RESET!!!!!!!!", 1) \
-+X(19, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_DEBUG2_DEPRECATED, "Freelist 0x%x stacktop = 0x%08x%08x, Alloc Page Count = %u, Alloc MMU Page Count = %u", 5) \
-+X(20, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_FL_RECON_DEPRECATED, "Request reconstruction of Freelist 0x%x type: %d (0:local,1:global,2:mmu) on HW context %u", 3) \
-+X(21, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_FL_RECON_ACK_DEPRECATED, "Freelist reconstruction ACK from host (HWR state :%u)", 1) \
-+X(22, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_FL_RECON_ACK_DEPRECATED2, "Freelist reconstruction completed", 0) \
-+X(23, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_TA_RTDATA_LOADED_DEPRECATED, "TA RTData 0x%08x loaded on HW context %u HWRTDataNeedsLoading=%d", 3) \
-+X(24, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_TE_RGNHDR_INFO, "TE Region headers base 0x%08x%08x (RGNHDR Init: %d)", 3) \
-+X(25, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_TA_RTDATA_BUFFER_ADDRS_DEPRECATED, "TA Buffers: FWCtx 0x%08x, RT 0x%08x, RTData 0x%08x, VHeap 0x%08x%08x, TPC 0x%08x%08x (MemCtx 0x%08x)", 8) \
-+X(26, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_3D_RTDATA_LOADED_DEPRECATED, "3D RTData 0x%08x loaded on HW context %u", 2) \
-+X(27, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_3D_RTDATA_BUFFER_ADDRS_DEPRECATED, "3D Buffers: FWCtx 0x%08x, RT 0x%08x, RTData 0x%08x (MemCtx 0x%08x)", 4) \
-+X(28, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_TA_RESTART_AFTER_PR_EXECUTED, "Restarting TA after partial render, HWRTData0State=0x%x, HWRTData1State=0x%x", 2) \
-+X(29, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_PB_SET_TO, "CONTEXT_PB_BASE set to 0x%x, FL different between TA/3D: local: %d, global: %d", 3) \
-+X(30, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_STORE_FL, "Store Freelist 0x%x type: %d (0:local,1:global) for PMDM%d: FL Total Pages %u (max=%u,grow size=%u), FL-addr = 0x%08x%08x, stacktop = 0x%08x%08x, Alloc Page Count = %u, Alloc MMU Page Count = %u", 12) \
-+X(31, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_LOAD_FL, "Load Freelist 0x%x type: %d (0:local,1:global) for PMDM%d: FL Total Pages %u (max=%u,grow size=%u), FL-addr = 0x%08x%08x, stacktop = 0x%08x%08x, Alloc Page Count = %u, Alloc MMU Page Count = %u", 12) \
-+X(32, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_3D_RTDATA_BUFFER_ADDRS_DEPRECATED2, "3D Buffers: FWCtx 0x%08x, parent RT 0x%08x, RTData 0x%08x on ctx %d, (MemCtx 0x%08x)", 5) \
-+X(33, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_TA_RTDATA_BUFFER_ADDRS, "TA Buffers: FWCtx 0x%08x, RTData 0x%08x, VHeap 0x%08x%08x, TPC 0x%08x%08x (MemCtx 0x%08x)", 7) \
-+X(34, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_3D_RTDATA_BUFFER_ADDRS, "3D Buffers: FWCtx 0x%08x, RTData 0x%08x on ctx %d, (MemCtx 0x%08x)", 4) \
-+X(35, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_LOAD_FL_V2, "Load Freelist 0x%x type: %d (0:local,1:global) for PMDM%d: FL Total Pages %u (max=%u,grow size=%u)", 6) \
-+X(36, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_KILLED_TA, "TA RTData 0x%08x marked as killed.", 1) \
-+X(37, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_KILLED_3D, "3D RTData 0x%08x marked as killed.", 1) \
-+X(38, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_KILL_TA_AFTER_RESTART, "RTData 0x%08x will be killed after TA restart.", 1) \
-+X(39, ROGUE_FW_GROUP_RTD, ROGUE_FW_SF_RTD_RENDERSTATE_RESET, "RTData 0x%08x Render State Buffer 0x%08x%08x will be reset.", 3) \
-+\
-+X(1, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZLOAD_DEPRECATED, "Force Z-Load for partial render", 0) \
-+X(2, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSTORE_DEPRECATED, "Force Z-Store for partial render", 0) \
-+X(3, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_3DMEMFREE_LOCAL_DEPRECATED, "3D MemFree: Local FL 0x%08x", 1) \
-+X(4, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_3DMEMFREE_MMU_DEPRECATED, "3D MemFree: MMU FL 0x%08x", 1) \
-+X(5, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_3DMEMFREE_GLOBAL_DEPRECATED, "3D MemFree: Global FL 0x%08x", 1) \
-+X(6, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OOM_TACMD_DEPRECATED, "OOM TA/3D PR Check: [0x%08.8x] is 0x%08.8x requires 0x%08.8x, HardwareSync Fence [0x%08.8x] is 0x%08.8x requires 0x%08.8x", 6) \
-+X(7, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OOM_TACMD_UN_FL, "OOM TA_cmd=0x%08x, U-FL 0x%08x, N-FL 0x%08x", 3) \
-+X(8, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OOM_TACMD_UN_MMU_FL_DEPRECATED, "OOM TA_cmd=0x%08x, OOM MMU:%d, U-FL 0x%08x, N-FL 0x%08x, MMU-FL 0x%08x", 5) \
-+X(9, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_PRENDER_AVOIDED_DEPRECATED, "Partial render avoided", 0) \
-+X(10, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_PRENDER_DISCARDED_DEPRECATED, "Partial render discarded", 0) \
-+X(11, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_PRENDER_FINISHED, "Partial Render finished", 0) \
-+X(12, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OWNER_3DBG_DEPRECATED, "SPM Owner = 3D-BG", 0) \
-+X(13, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OWNER_3DIRQ_DEPRECATED, "SPM Owner = 3D-IRQ", 0) \
-+X(14, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OWNER_NONE_DEPRECATED, "SPM Owner = NONE", 0) \
-+X(15, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OWNER_TABG_DEPRECATED, "SPM Owner = TA-BG", 0) \
-+X(16, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OWNER_TAIRQ_DEPRECATED, "SPM Owner = TA-IRQ", 0) \
-+X(17, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSTORE_ADDRESS, "ZStore address 0x%08x%08x", 2) \
-+X(18, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_SSTORE_ADDRESS, "SStore address 0x%08x%08x", 2) \
-+X(19, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZLOAD_ADDRESS, "ZLoad address 0x%08x%08x", 2) \
-+X(20, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_SLOAD_ADDRESS, "SLoad address 0x%08x%08x", 2) \
-+X(21, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_NO_DEFERRED_ZSBUFFER_DEPRECATED, "No deferred ZS Buffer provided", 0) \
-+X(22, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_POPULATED, "ZS Buffer successfully populated (ID=0x%08x)", 1) \
-+X(23, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_POP_UNNEEDED_DEPRECATED, "No need to populate ZS Buffer (ID=0x%08x)", 1) \
-+X(24, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_UNPOPULATED, "ZS Buffer successfully unpopulated (ID=0x%08x)", 1) \
-+X(25, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_UNPOP_UNNEEDED_DEPRECATED, "No need to unpopulate ZS Buffer (ID=0x%08x)", 1) \
-+X(26, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_BACKING_REQUEST_DEPRECATED, "Send ZS-Buffer backing request to host (ID=0x%08x)", 1) \
-+X(27, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_UNBACKING_REQUEST_DEPRECATED, "Send ZS-Buffer unbacking request to host (ID=0x%08x)", 1) \
-+X(28, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_BACKING_REQUEST_PENDING_DEPRECATED, "Don't send ZS-Buffer backing request. Previous request still pending (ID=0x%08x)", 1) \
-+X(29, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_UNBACKING_REQUEST_PENDING_DEPRECATED, "Don't send ZS-Buffer unbacking request. Previous request still pending (ID=0x%08x)", 1) \
-+X(30, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZBUFFER_NOT_READY_DEPRECATED, "Partial Render waiting for ZBuffer to be backed (ID=0x%08x)", 1) \
-+X(31, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_SBUFFER_NOT_READY_DEPRECATED, "Partial Render waiting for SBuffer to be backed (ID=0x%08x)", 1) \
-+X(32, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_STATE_NONE, "SPM State = none", 0) \
-+X(33, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_STATE_PR_BLOCKED, "SPM State = PR blocked", 0) \
-+X(34, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_STATE_WAIT_FOR_GROW, "SPM State = wait for grow", 0) \
-+X(35, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_STATE_WAIT_FOR_HW, "SPM State = wait for HW", 0) \
-+X(36, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_STATE_PR_RUNNING, "SPM State = PR running", 0) \
-+X(37, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_STATE_PR_AVOIDED, "SPM State = PR avoided", 0) \
-+X(38, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_STATE_PR_EXECUTED, "SPM State = PR executed", 0) \
-+X(39, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_FREELIST_MATCH, "3DMemFree matches freelist 0x%08x (FL type = %u)", 2) \
-+X(40, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_3DMEMFREE_FLAG_SET, "Raise the 3DMemFreeDedected flag", 0) \
-+X(41, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_STATE_WAIT_FOR_PENDING_GROW, "Wait for pending grow on Freelist 0x%08x", 1) \
-+X(42, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ZSBUFFER_BACKING_REQUEST_FAILED, "ZS Buffer failed to be populated (ID=0x%08x)", 1) \
-+X(43, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_FL_GROW_DEBUG, "Grow update inconsistency: FL addr: 0x%02x%08x, curr pages: %u, ready: %u, new: %u", 5) \
-+X(44, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_RESUMED_TA_WITH_SP, "OOM: Resumed TA with ready pages, FL addr: 0x%02x%08x, current pages: %u, SP : %u", 4) \
-+X(45, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ACK_GROW_UPDATE_DEPRECATED, "Received grow update, FL addr: 0x%02x%08x, current pages: %u, ready pages: %u, threshold: %u", 5) \
-+X(46, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_NO_DEFERRED_PRBUFFER, "No deferred partial render FW (Type=%d) Buffer provided", 1) \
-+X(47, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_BUFFER_POP_UNNEEDED, "No need to populate PR Buffer (ID=0x%08x)", 1) \
-+X(48, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_BUFFER_UNPOP_UNNEEDED, "No need to unpopulate PR Buffer (ID=0x%08x)", 1) \
-+X(49, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_BUFFER_BACKING_REQUEST, "Send PR Buffer backing request to host (ID=0x%08x)", 1) \
-+X(50, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_BUFFER_UNBACKING_REQUEST, "Send PR Buffer unbacking request to host (ID=0x%08x)", 1) \
-+X(51, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_BUFFER_BACKING_REQUEST_PENDING, "Don't send PR Buffer backing request. Previous request still pending (ID=0x%08x)", 1) \
-+X(52, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_BUFFER_UNBACKING_REQUEST_PENDING, "Don't send PR Buffer unbacking request. Previous request still pending (ID=0x%08x)", 1) \
-+X(53, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_BUFFER_NOT_READY, "Partial Render waiting for Buffer %d type to be backed (ID=0x%08x)", 2) \
-+X(54, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_ACK_GROW_UPDATE, "Received grow update, FL addr: 0x%02x%08x, new pages: %u, ready pages: %u", 4) \
-+X(66, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_OOM_TACMD, "OOM TA/3D PR Check: [0x%08.8x] is 0x%08.8x requires 0x%08.8x", 3) \
-+X(67, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_RESUMED_TA, "OOM: Resumed TA with ready pages, FL addr: 0x%02x%08x, current pages: %u", 3) \
-+X(68, ROGUE_FW_GROUP_SPM, ROGUE_FW_SF_SPM_PR_DEADLOCK_UNBLOCKED, "OOM TA/3D PR deadlock unblocked reordering DM%d runlist head from Context 0x%08x to 0x%08x", 3) \
-+\
-+X(1, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CHECK_DEPRECATED, "Check Pow state DM%d int: 0x%x, ext: 0x%x, pow flags: 0x%x", 4) \
-+X(2, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_GPU_IDLE, "GPU idle (might be powered down). Pow state int: 0x%x, ext: 0x%x, flags: 0x%x", 3) \
-+X(3, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_OSREQ_DEPRECATED, "OS requested pow off (forced = %d), DM%d, pow flags: 0x%x", 3) \
-+X(4, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_INIOFF_DEPRECATED, "Initiate powoff query. Inactive DMs: %d %d %d %d", 4) \
-+X(5, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CHECKOFF_DEPRECATED, "Any RD-DM pending? %d, Any RD-DM Active? %d", 2) \
-+X(6, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_GPU_OFF, "GPU ready to be powered down. Pow state int: 0x%x, ext: 0x%x, flags: 0x%x", 3) \
-+X(7, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_HWREQ, "HW Request On(1)/Off(0): %d, Units: 0x%08.8x", 2) \
-+X(8, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_DUSTS_CHANGE_REQ, "Request to change num of dusts to %d (Power flags=%d)", 2) \
-+X(9, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_DUSTS_CHANGE, "Changing number of dusts from %d to %d", 2) \
-+X(11, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_SIDEKICK_INIT_DEPRECATED, "Sidekick init", 0) \
-+X(12, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_RD_INIT_DEPRECATED, "Rascal+Dusts init (# dusts mask: 0x%x)", 1) \
-+X(13, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_INIOFF_RD, "Initiate powoff query for RD-DMs.", 0) \
-+X(14, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_INIOFF_TLA, "Initiate powoff query for TLA-DM.", 0) \
-+X(15, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_REQUESTEDOFF_RD, "Any RD-DM pending? %d, Any RD-DM Active? %d", 2) \
-+X(16, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_REQUESTEDOFF_TLA, "TLA-DM pending? %d, TLA-DM Active? %d", 2) \
-+X(17, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_BRN37270_DEPRECATED, "Request power up due to BRN37270. Pow stat int: 0x%x", 1) \
-+X(18, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_REQ_CANCEL, "Cancel power off request int: 0x%x, ext: 0x%x, pow flags: 0x%x", 3) \
-+X(19, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_FORCED_IDLE, "OS requested forced IDLE, pow flags: 0x%x", 1) \
-+X(20, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CANCEL_FORCED_IDLE, "OS cancelled forced IDLE, pow flags: 0x%x", 1) \
-+X(21, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_IDLE_TIMER, "Idle timer start. Pow state int: 0x%x, ext: 0x%x, flags: 0x%x", 3) \
-+X(22, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CANCEL_IDLE_TIMER, "Cancel idle timer. Pow state int: 0x%x, ext: 0x%x, flags: 0x%x", 3) \
-+X(23, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_APM_LATENCY_CHANGE, "Active PM latency set to %dms. Core clock: %d Hz", 2) \
-+X(24, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CDM_CLUSTERS, "Compute cluster mask change to 0x%x, %d dusts powered.", 2) \
-+X(25, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_NULL_CMD_INIOFF_RD, "Null command executed, repeating initiate powoff query for RD-DMs.", 0) \
-+X(26, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_POWMON_ENERGY, "Power monitor: Estimate of dynamic energy %u", 1) \
-+X(27, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CHECK_DEPRECATED2, "Check Pow state: Int: 0x%x, Ext: 0x%x, Pow flags: 0x%x", 3) \
-+X(28, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_NEW_DEADLINE, "Proactive DVFS: New deadline, time = 0x%08x%08x", 2) \
-+X(29, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_NEW_WORKLOAD, "Proactive DVFS: New workload, cycles = 0x%08x%08x", 2) \
-+X(30, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_CALCULATE, "Proactive DVFS: Proactive frequency calculated = %u", 1) \
-+X(31, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_UTILISATION, "Proactive DVFS: Reactive utilisation = %u percent", 1) \
-+X(32, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_REACT, "Proactive DVFS: Reactive frequency calculated = %u.%u", 2) \
-+X(33, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_GPIO_SEND_DEPRECATED, "Proactive DVFS: OPP Point Sent = 0x%x", 1) \
-+X(34, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_DEADLINE_REMOVED, "Proactive DVFS: Deadline removed = 0x%08x%08x", 2) \
-+X(35, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_WORKLOAD_REMOVED, "Proactive DVFS: Workload removed = 0x%08x%08x", 2) \
-+X(36, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_THROTTLE, "Proactive DVFS: Throttle to a maximum = 0x%x", 1) \
-+X(37, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_GPIO_FAILURE, "Proactive DVFS: Failed to pass OPP point via GPIO.", 0) \
-+X(38, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_INVALID_NODE_DEPRECATED, "Proactive DVFS: Invalid node passed to function.", 0) \
-+X(39, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_GUEST_BAD_ACCESS_DEPRECATED, "Proactive DVFS: Guest OS attempted to do a privileged action. OSid = %u", 1) \
-+X(40, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_UNPROFILED_STARTED, "Proactive DVFS: Unprofiled work started. Total unprofiled work present: %u", 1) \
-+X(41, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_UNPROFILED_FINISHED, "Proactive DVFS: Unprofiled work finished. Total unprofiled work present: %u", 1) \
-+X(42, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_DISABLED, "Proactive DVFS: Disabled: Not enabled by host.", 0) \
-+X(43, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_HWREQ_RESULT, "HW Request Completed(1)/Aborted(0): %d, Ticks: %d", 2) \
-+X(44, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_DUSTS_CHANGE_FIX_59042_DEPRECATED, "Allowed number of dusts is %d due to BRN59042.", 1) \
-+X(45, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_HOST_TIMEOUT_NOTIFICATION, "Host timed out while waiting for a forced idle state. Pow state int: 0x%x, ext: 0x%x, flags: 0x%x", 3) \
-+X(46, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CHECK, "Check Pow state: Int: 0x%x, Ext: 0x%x, Pow flags: 0x%x, Fence Counters: Check: %u - Update: %u", 5) \
-+X(47, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_GPIO_SEND, "Proactive DVFS: OPP Point Sent = 0x%x, Success = 0x%x", 2) \
-+X(48, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_TO_IDLE, "Proactive DVFS: GPU transitioned to idle", 0) \
-+X(49, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_TO_ACTIVE, "Proactive DVFS: GPU transitioned to active", 0) \
-+X(50, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_POWDUMP_BUFFER_SIZE, "Power counter dumping: Data truncated writing register %u. Buffer too small.", 1) \
-+X(51, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_POWCTRL_ABORT, "Power controller returned ABORT for last request so retrying.", 0) \
-+X(52, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_INVALID_POWER_REQUEST_DEPRECATED, "Discarding invalid power request: type 0x%x, DM %u", 2) \
-+X(53, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CANCEL_FORCED_IDLE_NOT_IDLE, "Detected attempt to cancel forced idle while not forced idle (pow state 0x%x, pow flags 0x%x)", 2) \
-+X(54, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_FORCED_POW_OFF_NOT_IDLE, "Detected attempt to force power off while not forced idle (pow state 0x%x, pow flags 0x%x)", 2) \
-+X(55, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_NUMDUST_CHANGE_NOT_IDLE, "Detected attempt to change dust count while not forced idle (pow state 0x%x)", 1) \
-+X(56, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_POWMON_RESULT, "Power monitor: Type = %d (0 = power, 1 = energy), Estimate result = 0x%08x%08x", 3) \
-+X(57, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_MINMAX_CONFLICT, "Conflicting clock frequency range: OPP min = %u, max = %u", 2) \
-+X(58, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_PDVFS_FLOOR, "Proactive DVFS: Set floor to a minimum = 0x%x", 1) \
-+X(59, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_OSREQ, "OS requested pow off (forced = %d), pow flags: 0x%x", 2) \
-+X(60, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_INVALID_POWER_REQUEST, "Discarding invalid power request: type 0x%x", 1) \
-+X(61, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_SPU_POW_STATE_CHANGE_REQ, "Request to change SPU power state mask from 0x%x to 0x%x. Pow flags: 0x%x", 3) \
-+X(62, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_SPU_POW_STATE_CHANGE, "Changing SPU power state mask from 0x%x to 0x%x", 2) \
-+X(63, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_SPU_POW_CHANGE_NOT_IDLE, "Detected attempt to change SPU power state mask while not forced idle (pow state 0x%x)", 1) \
-+X(64, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_INVALID_SPU_POWER_MASK, "Invalid SPU power mask 0x%x! Changing to 1", 1) \
-+X(65, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_CLKDIV_UPDATE, "Proactive DVFS: Send OPP %u with clock divider value %u", 2) \
-+X(66, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_POWMON_PERF_MODE, "PPA block started in perf validation mode.", 0) \
-+X(67, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_POWMON_RESET, "Reset PPA block state %u (1=reset, 0=recalculate).", 1) \
-+X(68, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_POWCTRL_ABORT_WITH_CORE, "Power controller returned ABORT for Core-%d last request so retrying.", 1) \
-+X(69, ROGUE_FW_GROUP_POW, ROGUE_FW_SF_POW_HWREQ64BIT, "HW Request On(1)/Off(0): %d, Units: 0x%08x%08x", 3) \
-+\
-+X(1, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_LOCKUP_DEPRECATED, "Lockup detected on DM%d, FWCtx: 0x%08.8x", 2) \
-+X(2, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_RESET_FW_DEPRECATED, "Reset fw state for DM%d, FWCtx: 0x%08.8x, MemCtx: 0x%08.8x", 3) \
-+X(3, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_RESET_HW_DEPRECATED, "Reset HW", 0) \
-+X(4, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_TERMINATED_DEPRECATED, "Lockup recovered.", 0) \
-+X(5, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_SET_LOCKUP_DEPRECATED, "Lock-up DM%d FWCtx: 0x%08.8x", 2) \
-+X(6, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_LOCKUP_DETECTED_DEPRECATED, "Lockup detected: GLB(%d->%d), PER-DM(0x%08x->0x%08x)", 4) \
-+X(7, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_EARLY_FAULT_DETECTION_DEPRECATED, "Early fault detection: GLB(%d->%d), PER-DM(0x%08x)", 3) \
-+X(8, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HOLD_SCHEDULING_DUE_TO_LOCKUP_DEPRECATED, "Hold scheduling due lockup: GLB(%d), PER-DM(0x%08x->0x%08x)", 3) \
-+X(9, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FALSE_LOCKUP_DEPRECATED, "False lockup detected: GLB(%d->%d), PER-DM(0x%08x->0x%08x)", 4) \
-+X(10, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_BRN37729_DEPRECATED, "BRN37729: GLB(%d->%d), PER-DM(0x%08x->0x%08x)", 4) \
-+X(11, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FREELISTS_RECONSTRUCTED_DEPRECATED, "Freelists reconstructed: GLB(%d->%d), PER-DM(0x%08x)", 3) \
-+X(12, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_RECONSTRUCTING_FREELISTS_DEPRECATED, "Reconstructing freelists: %u (0-No, 1-Yes): GLB(%d->%d), PER-DM(0x%08x)", 4) \
-+X(13, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FAILED_HW_POLL, "HW poll %u (0-Unset 1-Set) failed (reg:0x%08x val:0x%08x)", 3) \
-+X(14, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_DM_DISCARDED_DEPRECATED, "Discarded cmd on DM%u FWCtx=0x%08x", 2) \
-+X(15, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_DM_DISCARDED, "Discarded cmd on DM%u (reason=%u) HWRTData=0x%08x (st: %d), FWCtx 0x%08x @ %d", 6) \
-+X(16, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_PM_FENCE_DEPRECATED, "PM fence WA could not be applied, Valid TA Setup: %d, RD powered off: %d", 2) \
-+X(17, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_SNAPSHOT, "FL snapshot RTD 0x%08.8x - local (0x%08.8x): %d, global (0x%08.8x): %d", 5) \
-+X(18, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_CHECK, "FL check RTD 0x%08.8x, discard: %d - local (0x%08.8x): s%d?=c%d, global (0x%08.8x): s%d?=c%d", 8) \
-+X(19, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_DEPRECATED, "FL reconstruction 0x%08.8x c%d", 2) \
-+X(20, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_3D_CHECK, "3D check: missing TA FWCtx 0x%08.8x @ %d, RTD 0x%08x.", 3) \
-+X(21, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_RESET_HW_DEPRECATED2, "Reset HW (mmu:%d, extmem: %d)", 2) \
-+X(22, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_ZERO_TA_CACHES, "Zero TA caches for FWCtx: 0x%08.8x (TPC addr: 0x%08x%08x, size: %d bytes)", 4) \
-+X(23, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FREELISTS_RECONSTRUCTED_DEPRECATED2, "Recovery DM%u: Freelists reconstructed. New R-Flags=0x%08x", 2) \
-+X(24, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_SKIPPED_CMD, "Recovery DM%u: FWCtx 0x%08x skipped to command @ %u. PR=%u. New R-Flags=0x%08x", 5) \
-+X(25, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_DM_RECOVERED, "Recovery DM%u: DM fully recovered", 1) \
-+X(26, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HOLD_SCHEDULING_DUE_TO_LOCKUP, "DM%u: Hold scheduling due to R-Flag = 0x%08x", 2) \
-+X(27, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_NEEDS_RECONSTRUCTION, "Analysis: Need freelist reconstruction", 0) \
-+X(28, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_NEEDS_SKIP, "Analysis DM%u: Lockup FWCtx: 0x%08.8x. Need to skip to next command", 2) \
-+X(29, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_NEEDS_SKIP_OOM_TA, "Analysis DM%u: Lockup while TA is OOM FWCtx: 0x%08.8x. Need to skip to next command", 2) \
-+X(30, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_NEEDS_PR_CLEANUP, "Analysis DM%u: Lockup while partial render FWCtx: 0x%08.8x. Need PR cleanup", 2) \
-+X(31, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_SET_LOCKUP_DEPRECATED2, "GPU has locked up", 0) \
-+X(32, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_READY, "DM%u ready for HWR", 1) \
-+X(33, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_DM_UPDATE_RECOVERY, "Recovery DM%u: Updated Recovery counter. New R-Flags=0x%08x", 2) \
-+X(34, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_BRN37729_DEPRECATED2, "Analysis: BRN37729 detected, reset TA and re-kicked 0x%08x)", 1) \
-+X(35, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_DM_TIMED_OUT, "DM%u timed out", 1) \
-+X(36, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_EVENT_STATUS_REG, "RGX_CR_EVENT_STATUS=0x%08x", 1) \
-+X(37, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_DM_FALSE_LOCKUP, "DM%u lockup falsely detected, R-Flags=0x%08x", 2) \
-+X(38, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_SET_OUTOFTIME, "GPU has overrun its deadline", 0) \
-+X(39, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_SET_POLLFAILURE, "GPU has failed a poll", 0) \
-+X(40, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_PERF_PHASE_REG, "RGX DM%u phase count=0x%08x", 2) \
-+X(41, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_RESET_HW_DEPRECATED3, "Reset HW (loop:%d, poll failures: 0x%08x)", 2) \
-+X(42, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_MMU_FAULT_EVENT, "MMU fault event: 0x%08x", 1) \
-+X(43, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_BIF1_FAULT, "BIF1 page fault detected (Bank1 MMU Status: 0x%08x)", 1) \
-+X(44, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_CRC_CHECK_TRUE_DEPRECATED, "Fast CRC Failed. Proceeding to full register checking (DM: %u).", 1) \
-+X(45, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_MMU_META_FAULT, "Meta MMU page fault detected (Meta MMU Status: 0x%08x%08x)", 2) \
-+X(46, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_CRC_CHECK_DEPRECATED, "Fast CRC Check result for DM%u is HWRNeeded=%u", 2) \
-+X(47, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FULL_CHECK_DEPRECATED, "Full Signature Check result for DM%u is HWRNeeded=%u", 2) \
-+X(48, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FINAL_RESULT, "Final result for DM%u is HWRNeeded=%u with HWRChecksToGo=%u", 3) \
-+X(49, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_USC_SLOTS_CHECK_DEPRECATED, "USC Slots result for DM%u is HWRNeeded=%u USCSlotsUsedByDM=%d", 3) \
-+X(50, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_DEADLINE_CHECK_DEPRECATED, "Deadline counter for DM%u is HWRDeadline=%u", 2) \
-+X(51, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HOLD_SCHEDULING_DUE_TO_FREELIST_DEPRECATED, "Holding Scheduling on OSid %u due to pending freelist reconstruction", 1) \
-+X(52, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_REQUEST, "Requesting reconstruction for freelist 0x%x (ID=%d)", 2) \
-+X(53, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_PASSED, "Reconstruction of freelist ID=%d complete", 1) \
-+X(54, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_NEEDED_DEPRECATED, "Reconstruction needed for freelist 0x%x (ID=%d) type: %d (0:local,1:global,2:mmu) on HW context %u", 4) \
-+X(55, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_FAILED, "Reconstruction of freelist ID=%d failed", 1) \
-+X(56, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_RESTRICTING_PDS_TASKS, "Restricting PDS Tasks to help other stalling DMs (RunningMask=0x%02x, StallingMask=0x%02x, PDS_CTRL=0x%08x%08x)", 4) \
-+X(57, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_UNRESTRICTING_PDS_TASKS, "Unrestricting PDS Tasks again (RunningMask=0x%02x, StallingMask=0x%02x, PDS_CTRL=0x%08x%08x)", 4) \
-+X(58, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_USC_SLOTS_USED, "USC slots: %u used by DM%u", 2) \
-+X(59, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_USC_SLOTS_EMPTY, "USC slots: %u empty", 1) \
-+X(60, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HCS_FIRE, "HCS DM%d's Context Switch failed to meet deadline. Current time: 0x%08x%08x, deadline: 0x%08x%08x", 5) \
-+X(61, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_START_HW_RESET, "Begin hardware reset (HWR Counter=%d)", 1) \
-+X(62, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FINISH_HW_RESET, "Finished hardware reset (HWR Counter=%d)", 1) \
-+X(63, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HOLD_SCHEDULING_DUE_TO_FREELIST, "Holding Scheduling on DM %u for OSid %u due to pending freelist reconstruction", 2) \
-+X(64, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_RESET_UMQ_READ_OFFSET, "User Mode Queue ROff reset: FWCtx 0x%08.8x, queue: 0x%08x%08x (Roff = %u becomes StreamStartOffset = %u)", 5) \
-+X(65, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_NEEDED_DEPRECATED2, "Reconstruction needed for freelist 0x%x (ID=%d) type: %d (0:local,1:global) on HW context %u", 4) \
-+X(66, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_MIPS_FAULT, "Mips page fault detected (BadVAddr: 0x%08x, EntryLo0: 0x%08x, EntryLo1: 0x%08x)", 3) \
-+X(67, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_ANOTHER_CHANCE, "At least one other DM is running okay so DM%u will get another chance", 1) \
-+X(68, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_FW, "Reconstructing in FW, FL: 0x%x (ID=%d)", 2) \
-+X(69, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_ZERO_RTC, "Zero RTC for FWCtx: 0x%08.8x (RTC addr: 0x%08x%08x, size: %d bytes)", 4) \
-+X(70, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_NEEDED_DEPRECATED3, "Reconstruction needed for freelist 0x%x (ID=%d) type: %d (0:local,1:global) phase: %d (0:TA, 1:3D) on HW context %u", 5) \
-+X(71, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_START_LONG_HW_POLL, "Start long HW poll %u (0-Unset 1-Set) for (reg:0x%08x val:0x%08x)", 3) \
-+X(72, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_END_LONG_HW_POLL, "End long HW poll (result=%d)", 1) \
-+X(73, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_DEADLINE_CHECK, "DM%u has taken %d ticks and deadline is %d ticks", 3) \
-+X(74, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_WATCHDOG_CHECK_DEPRECATED, "USC Watchdog result for DM%u is HWRNeeded=%u Status=%u USCs={0x%x} with HWRChecksToGo=%u", 5) \
-+X(75, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FL_RECON_NEEDED, "Reconstruction needed for freelist 0x%x (ID=%d) OSid: %d type: %d (0:local,1:global) phase: %d (0:TA, 1:3D) on HW context %u", 6) \
-+X(76, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_SET_LOCKUP, "GPU-%u has locked up", 1) \
-+X(77, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_SET_LOCKUP_DM, "DM%u has locked up", 1) \
-+X(78, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_CORE_EVENT_STATUS_REG, "Core %d RGX_CR_EVENT_STATUS=0x%08x", 2) \
-+X(79, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_MULTICORE_EVENT_STATUS_REG, "RGX_CR_MULTICORE_EVENT_STATUS%u=0x%08x", 2) \
-+X(80, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_CORE_BIF0_FAULT, "BIF0 page fault detected (Core %d MMU Status: 0x%08x%08x Req Status: 0x%08x%08x)", 5) \
-+X(81, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_CORE_MMU_FAULT_S7, "MMU page fault detected (Core %d MMU Status: 0x%08x%08x)", 3) \
-+X(82, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_CORE_MMU_FAULT, "MMU page fault detected (Core %d MMU Status: 0x%08x%08x 0x%08x)", 4) \
-+X(83, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_RESET_HW, "Reset HW (core:%d of %d, loop:%d, poll failures: 0x%08x)", 4) \
-+X(84, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_CRC_CHECK, "Fast CRC Check result for Core%u, DM%u is HWRNeeded=%u", 3) \
-+X(85, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_FULL_CHECK, "Full Signature Check result for Core%u, DM%u is HWRNeeded=%u", 3) \
-+X(86, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_USC_SLOTS_CHECK, "USC Slots result for Core%u, DM%u is HWRNeeded=%u USCSlotsUsedByDM=%d", 4) \
-+X(87, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_WATCHDOG_CHECK, "USC Watchdog result for Core%u DM%u is HWRNeeded=%u Status=%u USCs={0x%x} with HWRChecksToGo=%u", 6) \
-+X(88, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_MMU_RISCV_FAULT, "RISC-V MMU page fault detected (FWCORE MMU Status 0x%08x Req Status 0x%08x%08x)", 3) \
-+X(89, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS1_PFS_DEPRECATED, "After FW fault was raised, TEXAS1_PFS poll failed on core %d with value 0x%08x", 2) \
-+X(90, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HWR_FAULT_POLL_BIF_PFS, "After FW fault was raised, BIF_PFS poll failed on core %d with value 0x%08x", 2) \
-+X(91, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HWR_FAULT_POLL_SET_ABORT_PM_STATUS, "After FW fault was raised, MMU_ABORT_PM_STATUS set poll failed on core %d with value 0x%08x", 2) \
-+X(92, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HWR_FAULT_POLL_UNSET_ABORT_PM_STATUS, "After FW fault was raised, MMU_ABORT_PM_STATUS unset poll failed on core %d with value 0x%08x", 2) \
-+X(93, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HWR_FAULT_POLL_SLC_INVAL, "After FW fault was raised, MMU_CTRL_INVAL poll (all but fw) failed on core %d with value 0x%08x", 2) \
-+X(94, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HWR_FAULT_POLL_SLCMMU_INVAL, "After FW fault was raised, MMU_CTRL_INVAL poll (all) failed on core %d with value 0x%08x", 2) \
-+X(95, ROGUE_FW_GROUP_HWR, ROGUE_FW_SF_HWR_HWR_FAULT_POLL_BIF_TEXAS_PFS, "After FW fault was raised, TEXAS%d_PFS poll failed on core %d with value 0x%08x", 3) \
-+\
-+X(1, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CFGBLK, "Block 0x%x mapped to Config Idx %u", 2) \
-+X(2, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_OMTBLK, "Block 0x%x omitted from event - not enabled in HW", 1) \
-+X(3, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_INCBLK, "Block 0x%x included in event - enabled in HW", 1) \
-+X(4, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_SELREG, "Select register state hi_0x%x lo_0x%x", 2) \
-+X(5, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CSBHDR, "Counter stream block header word 0x%x", 1) \
-+X(6, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CTROFF, "Counter register offset 0x%x", 1) \
-+X(7, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CFGSKP, "Block 0x%x config unset, skipping", 1) \
-+X(8, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_INDBLK, "Accessing Indirect block 0x%x", 1) \
-+X(9, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_DIRBLK, "Accessing Direct block 0x%x", 1) \
-+X(10, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CNTPRG, "Programmed counter select register at offset 0x%x", 1) \
-+X(11, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_BLKPRG, "Block register offset 0x%x and value 0x%x", 2) \
-+X(12, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_UBLKCG, "Reading config block from driver 0x%x", 1) \
-+X(13, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_UBLKRG, "Reading block range 0x%x to 0x%x", 2) \
-+X(14, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_BLKREC, "Recording block 0x%x config from driver", 1) \
-+X(15, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_UBLKED, "Finished reading config block from driver", 0) \
-+X(16, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CUSTOM_COUNTER, "Custom Counter offset: 0x%x value: 0x%x", 2) \
-+X(17, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_SELECT_CNTR, "Select counter n:%u ID:0x%x", 2) \
-+X(18, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_DROP_SELECT_PACK, "The counter ID 0x%x is not allowed. The package [b:%u, n:%u] will be discarded", 3) \
-+X(19, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CHANGE_FILTER_STATUS_CUSTOM, "Custom Counters filter status %d", 1) \
-+X(20, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_DROP_WRONG_BLOCK, "The Custom block %d is not allowed. Use only blocks lower than %d. The package will be discarded", 2) \
-+X(21, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_DROP_TOO_MANY_ID, "The package will be discarded because it contains %d counters IDs while the upper limit is %d", 2) \
-+X(22, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CHECK_FILTER, "Check Filter 0x%x is 0x%x ?", 2) \
-+X(23, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_RESET_CUSTOM_BLOCK, "The custom block %u is reset", 1) \
-+X(24, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_INVALID_CMD_DEPRECATED, "Encountered an invalid command (%d)", 1) \
-+X(25, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_WAITING_FOR_QUEUE_DEPRECATED, "HWPerf Queue is full, we will have to wait for space! (Roff = %u, Woff = %u)", 2) \
-+X(26, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_WAITING_FOR_QUEUE_FENCE_DEPRECATED, "HWPerf Queue is fencing, we are waiting for Roff = %d (Roff = %u, Woff = %u)", 3) \
-+X(27, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CUSTOM_BLOCK, "Custom Counter block: %d", 1) \
-+X(28, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_BLKENA, "Block 0x%x ENABLED", 1) \
-+X(29, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_BLKDIS, "Block 0x%x DISABLED", 1) \
-+X(30, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_INDBLK_INSTANCE, "Accessing Indirect block 0x%x, instance %u", 2) \
-+X(31, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CTRVAL, "Counter register 0x%x, Value 0x%x", 2) \
-+X(32, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CHANGE_FILTER_STATUS, "Counters filter status %d", 1) \
-+X(33, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CTLBLK, "Block 0x%x mapped to Ctl Idx %u", 2) \
-+X(34, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_WORKEST_EN, "Block(s) in use for workload estimation.", 0) \
-+X(35, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CYCCTR, "GPU %u Cycle counter 0x%x, Value 0x%x", 3) \
-+X(36, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_CYCMAX, "GPU Mask 0x%x Cycle counter 0x%x, Value 0x%x", 3) \
-+X(37, ROGUE_FW_GROUP_HWP, ROGUE_FW_SF_HWP_I_IGNORE_BLOCKS, "Blocks IGNORED for GPU %u", 1) \
-+\
-+X(1, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_TRANSFER_REQUEST_DEPRECATED, "Transfer 0x%02x request: 0x%02x%08x -> 0x%08x, size %u", 5) \
-+X(2, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_TRANSFER_COMPLETE, "Transfer of type 0x%02x expected on channel %u, 0x%02x found, status %u", 4) \
-+X(3, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_INT_REG, "DMA Interrupt register 0x%08x", 1) \
-+X(4, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_WAIT, "Waiting for transfer of type 0x%02x completion...", 1) \
-+X(5, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_CCB_LOADING_FAILED, "Loading of cCCB data from FW common context 0x%08x (offset: %u, size: %u) failed", 3) \
-+X(6, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_CCB_LOAD_INVALID, "Invalid load of cCCB data from FW common context 0x%08x (offset: %u, size: %u)", 3) \
-+X(7, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_POLL_FAILED, "Transfer 0x%02x request poll failure", 1) \
-+X(8, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_BOOT_TRANSFER_FAILED, "Boot transfer(s) failed (code? %u, data? %u), used slower memcpy instead", 2) \
-+X(9, ROGUE_FW_GROUP_DMA, ROGUE_FW_SF_DMA_TRANSFER_REQUEST, "Transfer 0x%02x request on ch. %u: system 0x%02x%08x, coremem 0x%08x, flags 0x%x, size %u", 7) \
-+\
-+X(1, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_INTPAIR, "0x%08x 0x%08x", 2) \
-+X(2, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_1HEX, "0x%08x", 1) \
-+X(3, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_2HEX, "0x%08x 0x%08x", 2) \
-+X(4, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_3HEX, "0x%08x 0x%08x 0x%08x", 3) \
-+X(5, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_4HEX, "0x%08x 0x%08x 0x%08x 0x%08x", 4) \
-+X(6, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_5HEX, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", 5) \
-+X(7, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_6HEX, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", 6) \
-+X(8, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_7HEX, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", 7) \
-+X(9, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_8HEX, "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", 8) \
-+X(10, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_1SIGNED, "%d", 1) \
-+X(11, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_2SIGNED, "%d %d", 2) \
-+X(12, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_3SIGNED, "%d %d %d", 3) \
-+X(13, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_4SIGNED, "%d %d %d %d", 4) \
-+X(14, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_5SIGNED, "%d %d %d %d %d", 5) \
-+X(15, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_6SIGNED, "%d %d %d %d %d %d", 6) \
-+X(16, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_7SIGNED, "%d %d %d %d %d %d %d", 7) \
-+X(17, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_8SIGNED, "%d %d %d %d %d %d %d %d", 8) \
-+X(18, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_1UNSIGNED, "%u", 1) \
-+X(19, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_2UNSIGNED, "%u %u", 2) \
-+X(20, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_3UNSIGNED, "%u %u %u", 3) \
-+X(21, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_4UNSIGNED, "%u %u %u %u", 4) \
-+X(22, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_5UNSIGNED, "%u %u %u %u %u", 5) \
-+X(23, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_6UNSIGNED, "%u %u %u %u %u %u", 6) \
-+X(24, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_7UNSIGNED, "%u %u %u %u %u %u %u", 7) \
-+X(25, ROGUE_FW_GROUP_DBG, ROGUE_FW_SF_DBG_8UNSIGNED, "%u %u %u %u %u %u %u %u", 8) \
-+\
-+X(65535, ROGUE_FW_GROUP_NULL, ROGUE_FW_SF_LAST, "You should not use this string", 15)
-+
-+
-+/*
-+ * The symbolic names found in the table above are assigned an u32 value of
-+ * the following format:
-+ * 31 30 28 27 20 19 16 15 12 11 0 bits
-+ * - --- ---- ---- ---- ---- ---- ---- ----
-+ * 0-11: id number
-+ * 12-15: group id number
-+ * 16-19: number of parameters
-+ * 20-27: unused
-+ * 28-30: active: identify SF packet, otherwise regular int32
-+ * 31: reserved for signed/unsigned compatibility
-+ *
-+ * The following macro assigns those values to the enum generated SF ids list.
-+ */
-+#define ROGUE_FW_LOG_IDMARKER (0x70000000U)
-+#define ROGUE_FW_LOG_CREATESFID(a, b, e) ((u32)(a) | ((u32)(b)<<12U) | ((u32)(e)<<16U)) | ROGUE_FW_LOG_IDMARKER
-+
-+#define ROGUE_FW_LOG_IDMASK (0xFFF00000)
-+#define ROGUE_FW_LOG_VALIDID(I) (((I) & ROGUE_FW_LOG_IDMASK) == ROGUE_FW_LOG_IDMARKER)
-+
-+enum rogue_fw_log_sfids {
-+#define X(a, b, c, d, e) c = ROGUE_FW_LOG_CREATESFID(a, b, e),
-+ ROGUE_FW_LOG_SFIDLIST
-+#undef X
-+};
-+
-+/* Return the group id that the given (enum generated) id belongs to */
-+#define ROGUE_FW_SF_GID(x) (((u32)(x)>>12) & 0xfU)
-+/* Returns how many arguments the SF(string format) for the given (enum generated) id requires */
-+#define ROGUE_FW_SF_PARAMNUM(x) (((u32)(x)>>16) & 0xfU)
-+
-+#endif /* __PVR_ROGUE_FWIF_SF_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
-new file mode 100644
-index 000000000000..d71bf348ecd0
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
-@@ -0,0 +1,235 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_FWIF_SHARED_H__
-+#define __PVR_ROGUE_FWIF_SHARED_H__
-+
-+#include <linux/compiler.h>
-+#include <linux/types.h>
-+
-+#define ROGUE_FWIF_NUM_RTDATAS 2U
-+#define ROGUE_FWIF_NUM_GEOMDATAS 1U
-+#define ROGUE_FWIF_NUM_RTDATA_FREELISTS 2U
-+
-+/*
-+ * Maximum number of UFOs in a CCB command.
-+ * The number is based on having 32 sync prims (as originally), plus 32 sync
-+ * checkpoints.
-+ * Once the use of sync prims is no longer supported, we will retain
-+ * the same total (64) as the number of sync checkpoints which may be
-+ * supporting a fence is not visible to the client driver and has to
-+ * allow for the number of different timelines involved in fence merges.
-+ */
-+#define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U)
-+
-+/*
-+ * This is a generic limit imposed on any DM (GEOMETRY,FRAGMENT,CDM,TDM,2D,TRANSFER)
-+ * command passed through the bridge.
-+ * Just across the bridge in the server, any incoming kick command size is
-+ * checked against this maximum limit.
-+ * In case the incoming command size is larger than the specified limit,
-+ * the bridge call is retired with error.
-+ */
-+#define ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE (1024U)
-+
-+#define ROGUE_FWIF_PRBUFFER_START (0)
-+#define ROGUE_FWIF_PRBUFFER_ZSBUFFER (0)
-+#define ROGUE_FWIF_PRBUFFER_MSAABUFFER (1)
-+#define ROGUE_FWIF_PRBUFFER_MAXSUPPORTED (2)
-+
-+struct rogue_fwif_dma_addr {
-+ aligned_u64 dev_addr;
-+ u32 fw_addr;
-+} __aligned(8);
-+
-+struct rogue_fwif_ufo {
-+ u32 addr;
-+ u32 value;
-+};
-+
-+#define ROGUE_FWIF_UFO_ADDR_IS_SYNC_CHECKPOINT (1)
-+
-+struct rogue_fwif_sync_checkpoint {
-+ u32 state;
-+ u32 fw_ref_count;
-+};
-+
-+struct rogue_fwif_cleanup_ctl {
-+ /* Number of commands received by the FW */
-+ u32 submitted_commands;
-+ /* Number of commands executed by the FW */
-+ u32 executed_commands;
-+} __aligned(8);
-+
-+/*
-+ * Used to share frame numbers across UM-KM-FW,
-+ * frame number is set in UM,
-+ * frame number is required in both KM for HTB and FW for FW trace.
-+ *
-+ * May be used to house Kick flags in the future.
-+ */
-+struct rogue_fwif_cmd_common {
-+ /* associated frame number */
-+ u32 frame_num;
-+};
-+
-+/*
-+ * Geometry and fragment commands require set of firmware addresses that are stored in the Kernel.
-+ * Client has handle(s) to Kernel containers storing these addresses, instead of raw addresses. We
-+ * have to patch/write these addresses in KM to prevent UM from controlling FW addresses directly.
-+ * Typedefs for geometry and fragment commands are shared between Client and Firmware (both
-+ * single-BVNC). Kernel is implemented in a multi-BVNC manner, so it can't use geometry|fragment
-+ * CMD type definitions directly. Therefore we have a SHARED block that is shared between UM-KM-FW
-+ * across all BVNC configurations.
-+ */
-+struct rogue_fwif_cmd_geom_frag_shared {
-+ /* Common command attributes */
-+ struct rogue_fwif_cmd_common cmn;
-+ /*
-+ * RTData associated with this command, this is used for context
-+ * selection and for storing out HW-context, when TA is switched out for
-+ * continuing later
-+ */
-+ u32 hwrt_data_fw_addr;
-+
-+ /* Supported PR Buffers like Z/S/MSAA Scratch */
-+ u32 pr_buffer_fw_addr[ROGUE_FWIF_PRBUFFER_MAXSUPPORTED];
-+};
-+
-+/*
-+ * Client Circular Command Buffer (CCCB) control structure.
-+ * This is shared between the Server and the Firmware and holds byte offsets
-+ * into the CCCB as well as the wrapping mask to aid wrap around. A given
-+ * snapshot of this queue with Cmd 1 running on the GPU might be:
-+ *
-+ * Roff Doff Woff
-+ * [..........|-1----------|=2===|=3===|=4===|~5~~~~|~6~~~~|~7~~~~|..........]
-+ * < runnable commands >< !ready to run >
-+ *
-+ * Cmd 1 : Currently executing on the GPU data master.
-+ * Cmd 2,3,4: Fence dependencies met, commands runnable.
-+ * Cmd 5... : Fence dependency not met yet.
-+ */
-+struct rogue_fwif_cccb_ctl {
-+ /* Host write offset into CCB. This must be aligned to 16 bytes. */
-+ u32 write_offset;
-+ /*
-+ * Firmware read offset into CCB. Points to the command that is runnable
-+ * on GPU, if R!=W
-+ */
-+ u32 read_offset;
-+ /*
-+ * Firmware fence dependency offset. Points to commands not ready, i.e.
-+ * fence dependencies are not met.
-+ */
-+ u32 dep_offset;
-+ /* Offset wrapping mask, total capacity in bytes of the CCB-1 */
-+ u32 wrap_mask;
-+} __aligned(8);
-+
-+#define ROGUE_FW_LOCAL_FREELIST (0)
-+#define ROGUE_FW_GLOBAL_FREELIST (1)
-+#define ROGUE_FW_FREELIST_TYPE_LAST ROGUE_FW_GLOBAL_FREELIST
-+#define ROGUE_FW_MAX_FREELISTS (ROGUE_FW_FREELIST_TYPE_LAST + 1U)
-+
-+struct rogue_fwif_geom_registers_caswitch {
-+ u64 geom_reg_vdm_context_state_base_addr;
-+ u64 geom_reg_vdm_context_state_resume_addr;
-+ u64 geom_reg_ta_context_state_base_addr;
-+
-+ struct {
-+ u64 geom_reg_vdm_context_store_task0;
-+ u64 geom_reg_vdm_context_store_task1;
-+ u64 geom_reg_vdm_context_store_task2;
-+
-+ /* VDM resume state update controls */
-+ u64 geom_reg_vdm_context_resume_task0;
-+ u64 geom_reg_vdm_context_resume_task1;
-+ u64 geom_reg_vdm_context_resume_task2;
-+
-+ u64 geom_reg_vdm_context_store_task3;
-+ u64 geom_reg_vdm_context_store_task4;
-+
-+ u64 geom_reg_vdm_context_resume_task3;
-+ u64 geom_reg_vdm_context_resume_task4;
-+ } geom_state[2];
-+};
-+
-+#define ROGUE_FWIF_GEOM_REGISTERS_CSWITCH_SIZE \
-+ sizeof(struct rogue_fwif_geom_registers_caswitch)
-+
-+struct rogue_fwif_cdm_registers_cswitch {
-+ u64 cdmreg_cdm_context_state_base_addr;
-+ u64 cdmreg_cdm_context_pds0;
-+ u64 cdmreg_cdm_context_pds1;
-+ u64 cdmreg_cdm_terminate_pds;
-+ u64 cdmreg_cdm_terminate_pds1;
-+
-+ /* CDM resume controls */
-+ u64 cdmreg_cdm_resume_pds0;
-+ u64 cdmreg_cdm_context_pds0_b;
-+ u64 cdmreg_cdm_resume_pds0_b;
-+};
-+
-+struct rogue_fwif_static_rendercontext_state {
-+ /* Geom registers for ctx switch */
-+ struct rogue_fwif_geom_registers_caswitch ctxswitch_regs __aligned(8);
-+};
-+
-+#define ROGUE_FWIF_STATIC_RENDERCONTEXT_SIZE \
-+ sizeof(struct rogue_fwif_static_rendercontext_state)
-+
-+struct rogue_fwif_static_computecontext_state {
-+ /* CDM registers for ctx switch */
-+ struct rogue_fwif_cdm_registers_cswitch ctxswitch_regs __aligned(8);
-+};
-+
-+#define ROGUE_FWIF_STATIC_COMPUTECONTEXT_SIZE \
-+ sizeof(struct rogue_fwif_static_computecontext_state)
-+
-+enum rogue_fwif_prbuffer_state {
-+ ROGUE_FWIF_PRBUFFER_UNBACKED = 0,
-+ ROGUE_FWIF_PRBUFFER_BACKED,
-+ ROGUE_FWIF_PRBUFFER_BACKING_PENDING,
-+ ROGUE_FWIF_PRBUFFER_UNBACKING_PENDING,
-+};
-+
-+struct rogue_fwif_prbuffer {
-+ /* Buffer ID*/
-+ u32 buffer_id;
-+ /* Needs On-demand Z/S/MSAA Buffer allocation */
-+ bool on_demand __aligned(4);
-+ /* Z/S/MSAA -Buffer state */
-+ enum rogue_fwif_prbuffer_state state;
-+ /* Cleanup state */
-+ struct rogue_fwif_cleanup_ctl cleanup_sate;
-+ /* Compatibility and other flags */
-+ u32 prbuffer_flags;
-+} __aligned(8);
-+
-+/* Last reset reason for a context. */
-+enum rogue_context_reset_reason {
-+ /* No reset reason recorded */
-+ ROGUE_CONTEXT_RESET_REASON_NONE = 0,
-+ /* Caused a reset due to locking up */
-+ ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP = 1,
-+ /* Affected by another context locking up */
-+ ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP = 2,
-+ /* Overran the global deadline */
-+ ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING = 3,
-+ /* Affected by another context overrunning */
-+ ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4,
-+ /* Forced reset to ensure scheduling requirements */
-+ ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5,
-+ /* CDM Mission/safety checksum mismatch */
-+ ROGUE_CONTEXT_RESET_REASON_KZ_CHECKSUM = 6,
-+ /* TRP checksum mismatch */
-+ ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM = 7,
-+};
-+
-+struct rogue_context_reset_reason_data {
-+ enum rogue_context_reset_reason reset_reason;
-+ u32 reset_ext_job_ref;
-+};
-+
-+#endif /* __PVR_ROGUE_FWIF_SHARED_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h b/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
-new file mode 100644
-index 000000000000..96006f8cb374
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_heap_config.h
-@@ -0,0 +1,103 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_HEAP_CONFIG_H__
-+#define __PVR_ROGUE_HEAP_CONFIG_H__
-+
-+#include <linux/sizes.h>
-+
-+/*
-+ * ROGUE Device Virtual Address Space Definitions
-+ *
-+ * This file defines the ROGUE virtual address heaps that are used in
-+ * application memory contexts. It also shows where the Firmware memory heap
-+ * fits into this, but the firmware heap is only ever created in the
-+ * kernel driver and never exposed to userspace.
-+ *
-+ * ROGUE_PDSCODEDATA_HEAP_BASE and ROGUE_USCCODE_HEAP_BASE will be programmed,
-+ * on a global basis, into ROGUE_CR_PDS_EXEC_BASE and ROGUE_CR_USC_CODE_BASE_*
-+ * respectively. Therefore if client drivers use multiple configs they must
-+ * still be consistent with their definitions for these heaps.
-+ *
-+ * Base addresses have to be a multiple of 4MiB.
-+ * Heaps must not start at 0x0000000000, as this is reserved for internal
-+ * use within the driver.
-+ * Range comments, those starting in column 0 below are a section heading of
-+ * sorts and are above the heaps in that range. Often this is the reserved
-+ * size of the heap within the range.
-+ */
-+
-+/* 0x00_0000_0000 ************************************************************/
-+
-+/* 0x00_0000_0000 - 0x00_0040_0000 */
-+/* 0 MiB to 4 MiB, size of 4 MiB : RESERVED */
-+
-+/* 0x00_0040_0000 - 0x7F_FFC0_0000 **/
-+/* 4 MiB to 512 GiB, size of 512 GiB less 4 MiB : RESERVED **/
-+
-+/* 0x80_0000_0000 ************************************************************/
-+
-+/* 0x80_0000_0000 - 0x9F_FFFF_FFFF **/
-+/* 512 GiB to 640 GiB, size of 128 GiB : GENERAL_HEAP **/
-+#define ROGUE_GENERAL_HEAP_BASE 0x8000000000ull
-+#define ROGUE_GENERAL_HEAP_SIZE SZ_128G
-+
-+/* 0xA0_0000_0000 - 0xAF_FFFF_FFFF */
-+/* 640 GiB to 704 GiB, size of 64 GiB : FREE */
-+
-+/* B0_0000_0000 - 0xB7_FFFF_FFFF */
-+/* 704 GiB to 736 GiB, size of 32 GiB : FREE */
-+
-+/* 0xB8_0000_0000 - 0xBF_FFFF_FFFF */
-+/* 736 GiB to 768 GiB, size of 32 GiB : RESERVED */
-+
-+/* 0xC0_0000_0000 ************************************************************/
-+
-+/* 0xC0_0000_0000 - 0xD9_FFFF_FFFF */
-+/* 768 GiB to 872 GiB, size of 104 GiB : FREE */
-+
-+/* 0xDA_0000_0000 - 0xDA_FFFF_FFFF */
-+/* 872 GiB to 876 GiB, size of 4 GiB : PDSCODEDATA_HEAP */
-+#define ROGUE_PDSCODEDATA_HEAP_BASE 0xDA00000000ull
-+#define ROGUE_PDSCODEDATA_HEAP_SIZE SZ_4G
-+
-+/* 0xDB_0000_0000 - 0xDB_FFFF_FFFF */
-+/* 876 GiB to 880 GiB, size of 256 MiB (reserved 4GiB) : BRN **/
-+/*
-+ * The BRN63142 quirk workaround requires Region Header memory to be at the top
-+ * of a 16GiB aligned range. This is so when masked with 0x03FFFFFFFF the
-+ * address will avoid aliasing PB addresses. Start at 879.75GiB. Size of 256MiB.
-+ */
-+#define ROGUE_RGNHDR_HEAP_BASE 0xDBF0000000ull
-+#define ROGUE_RGNHDR_HEAP_SIZE SZ_256M
-+
-+/* 0xDC_0000_0000 - 0xDF_FFFF_FFFF */
-+/* 880 GiB to 896 GiB, size of 16 GiB : FREE */
-+
-+/* 0xE0_0000_0000 - 0xE0_FFFF_FFFF */
-+/* 896 GiB to 900 GiB, size of 4 GiB : USCCODE_HEAP */
-+#define ROGUE_USCCODE_HEAP_BASE 0xE000000000ull
-+#define ROGUE_USCCODE_HEAP_SIZE SZ_4G
-+
-+/* 0xE1_0000_0000 - 0xE1_BFFF_FFFF */
-+/* 900 GiB to 903 GiB, size of 3 GiB : RESERVED */
-+
-+/* 0xE1_C000_000 - 0xE1_FFFF_FFFF */
-+/* 903 GiB to 904 GiB, reserved 1 GiB, : FIRMWARE_HEAP */
-+#define ROGUE_FW_HEAP_BASE 0xE1C0000000ull
-+
-+/* 0xE2_0000_0000 - 0xE3_FFFF_FFFF */
-+/* 904 GiB to 912 GiB, size of 8 GiB : FREE */
-+
-+/* 0xE4_0000_0000 - 0xF2_001F_FFFF */
-+/* 912 GiB to 969 GiB, size of 57 GiB : RESERVED */
-+
-+/* 0xF2_4000_0000 - 0xF2_FFFF_FFFF */
-+/* 969 GiB to 972 GiB, size of 3 GiB : FREE */
-+
-+/* 0xF3_0000_0000 - 0xFF_FFFF_FFFF */
-+/* 972 GiB to 1024 GiB, size of 52 GiB : FREE */
-+
-+/* 0xFF_FFFF_FFFF ************************************************************/
-+
-+#endif /* __PVR_ROGUE_HEAP_CONFIG_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_meta.h b/drivers/gpu/drm/imagination/pvr_rogue_meta.h
-new file mode 100644
-index 000000000000..0ae7aa3ecd43
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_meta.h
-@@ -0,0 +1,357 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_META_H__
-+#define __PVR_ROGUE_META_H__
-+
-+/***** The META HW register definitions in the file are updated manually *****/
-+
-+#include <linux/bits.h>
-+#include <linux/types.h>
-+
-+/*
-+ ******************************************************************************
-+ * META registers and MACROS
-+ *****************************************************************************
-+ */
-+#define META_CR_CTRLREG_BASE(t) (0x04800000U + (0x1000U * (t)))
-+
-+#define META_CR_TXPRIVEXT (0x048000E8)
-+#define META_CR_TXPRIVEXT_MINIM_EN BIT(7)
-+
-+#define META_CR_SYSC_JTAG_THREAD (0x04830030)
-+#define META_CR_SYSC_JTAG_THREAD_PRIV_EN (0x00000004)
-+
-+#define META_CR_PERF_COUNT0 (0x0480FFE0)
-+#define META_CR_PERF_COUNT1 (0x0480FFE8)
-+#define META_CR_PERF_COUNT_CTRL_SHIFT (28)
-+#define META_CR_PERF_COUNT_CTRL_MASK (0xF0000000)
-+#define META_CR_PERF_COUNT_CTRL_DCACHEHITS (8 << META_CR_PERF_COUNT_CTRL_SHIFT)
-+#define META_CR_PERF_COUNT_CTRL_ICACHEHITS (9 << META_CR_PERF_COUNT_CTRL_SHIFT)
-+#define META_CR_PERF_COUNT_CTRL_ICACHEMISS \
-+ (0xA << META_CR_PERF_COUNT_CTRL_SHIFT)
-+#define META_CR_PERF_COUNT_CTRL_ICORE (0xD << META_CR_PERF_COUNT_CTRL_SHIFT)
-+#define META_CR_PERF_COUNT_THR_SHIFT (24)
-+#define META_CR_PERF_COUNT_THR_MASK (0x0F000000)
-+#define META_CR_PERF_COUNT_THR_0 (0x1 << META_CR_PERF_COUNT_THR_SHIFT)
-+#define META_CR_PERF_COUNT_THR_1 (0x2 << META_CR_PERF_COUNT_THR_1)
-+
-+#define META_CR_TxVECINT_BHALT (0x04820500)
-+#define META_CR_PERF_ICORE0 (0x0480FFD0)
-+#define META_CR_PERF_ICORE1 (0x0480FFD8)
-+#define META_CR_PERF_ICORE_DCACHEMISS (0x8)
-+
-+#define META_CR_PERF_COUNT(ctrl, thr) \
-+ ((META_CR_PERF_COUNT_CTRL_##ctrl << META_CR_PERF_COUNT_CTRL_SHIFT) | \
-+ ((thr) << META_CR_PERF_COUNT_THR_SHIFT))
-+
-+#define META_CR_TXUXXRXDT_OFFSET (META_CR_CTRLREG_BASE(0U) + 0x0000FFF0U)
-+#define META_CR_TXUXXRXRQ_OFFSET (META_CR_CTRLREG_BASE(0U) + 0x0000FFF8U)
-+
-+/* Poll for done. */
-+#define META_CR_TXUXXRXRQ_DREADY_BIT (0x80000000U)
-+/* Set for read. */
-+#define META_CR_TXUXXRXRQ_RDnWR_BIT (0x00010000U)
-+#define META_CR_TXUXXRXRQ_TX_S (12)
-+#define META_CR_TXUXXRXRQ_RX_S (4)
-+#define META_CR_TXUXXRXRQ_UXX_S (0)
-+
-+/* Internal ctrl regs. */
-+#define META_CR_TXUIN_ID (0x0)
-+/* Data unit regs. */
-+#define META_CR_TXUD0_ID (0x1)
-+/* Data unit regs. */
-+#define META_CR_TXUD1_ID (0x2)
-+/* Address unit regs. */
-+#define META_CR_TXUA0_ID (0x3)
-+/* Address unit regs. */
-+#define META_CR_TXUA1_ID (0x4)
-+/* PC registers. */
-+#define META_CR_TXUPC_ID (0x5)
-+
-+/* Macros to calculate register access values. */
-+#define META_CR_CORE_REG(thr, reg_num, unit) \
-+ (((u32)(thr) << META_CR_TXUXXRXRQ_TX_S) | \
-+ ((u32)(reg_num) << META_CR_TXUXXRXRQ_RX_S) | \
-+ ((u32)(unit) << META_CR_TXUXXRXRQ_UXX_S))
-+
-+#define META_CR_THR0_PC META_CR_CORE_REG(0, 0, META_CR_TXUPC_ID)
-+#define META_CR_THR0_PCX META_CR_CORE_REG(0, 1, META_CR_TXUPC_ID)
-+#define META_CR_THR0_SP META_CR_CORE_REG(0, 0, META_CR_TXUA0_ID)
-+
-+#define META_CR_THR1_PC META_CR_CORE_REG(1, 0, META_CR_TXUPC_ID)
-+#define META_CR_THR1_PCX META_CR_CORE_REG(1, 1, META_CR_TXUPC_ID)
-+#define META_CR_THR1_SP META_CR_CORE_REG(1, 0, META_CR_TXUA0_ID)
-+
-+#define SP_ACCESS(thread) META_CR_CORE_REG(thread, 0, META_CR_TXUA0_ID)
-+#define PC_ACCESS(thread) META_CR_CORE_REG(thread, 0, META_CR_TXUPC_ID)
-+
-+#define META_CR_COREREG_ENABLE (0x0000000U)
-+#define META_CR_COREREG_STATUS (0x0000010U)
-+#define META_CR_COREREG_DEFR (0x00000A0U)
-+#define META_CR_COREREG_PRIVEXT (0x00000E8U)
-+
-+#define META_CR_T0ENABLE_OFFSET \
-+ (META_CR_CTRLREG_BASE(0U) + META_CR_COREREG_ENABLE)
-+#define META_CR_T0STATUS_OFFSET \
-+ (META_CR_CTRLREG_BASE(0U) + META_CR_COREREG_STATUS)
-+#define META_CR_T0DEFR_OFFSET (META_CR_CTRLREG_BASE(0U) + META_CR_COREREG_DEFR)
-+#define META_CR_T0PRIVEXT_OFFSET \
-+ (META_CR_CTRLREG_BASE(0U) + META_CR_COREREG_PRIVEXT)
-+
-+#define META_CR_T1ENABLE_OFFSET \
-+ (META_CR_CTRLREG_BASE(1U) + META_CR_COREREG_ENABLE)
-+#define META_CR_T1STATUS_OFFSET \
-+ (META_CR_CTRLREG_BASE(1U) + META_CR_COREREG_STATUS)
-+#define META_CR_T1DEFR_OFFSET (META_CR_CTRLREG_BASE(1U) + META_CR_COREREG_DEFR)
-+#define META_CR_T1PRIVEXT_OFFSET \
-+ (META_CR_CTRLREG_BASE(1U) + META_CR_COREREG_PRIVEXT)
-+
-+#define META_CR_TXENABLE_ENABLE_BIT (0x00000001U) /* Set if running */
-+#define META_CR_TXSTATUS_PRIV (0x00020000U)
-+#define META_CR_TXPRIVEXT_MINIM (0x00000080U)
-+
-+#define META_MEM_GLOBAL_RANGE_BIT (0x80000000U)
-+
-+#define META_CR_TXCLKCTRL (0x048000B0)
-+#define META_CR_TXCLKCTRL_ALL_ON (0x55111111)
-+#define META_CR_TXCLKCTRL_ALL_AUTO (0xAA222222)
-+
-+#define META_CR_MMCU_LOCAL_EBCTRL (0x04830600)
-+#define META_CR_MMCU_LOCAL_EBCTRL_ICWIN (0x3 << 14)
-+#define META_CR_MMCU_LOCAL_EBCTRL_DCWIN (0x3 << 6)
-+#define META_CR_SYSC_DCPART(n) (0x04830200 + (n)*0x8)
-+#define META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE (0x1 << 31)
-+#define META_CR_SYSC_ICPART(n) (0x04830220 + (n)*0x8)
-+#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_OFFSET_TOP_HALF (0x8 << 16)
-+#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE (0xF)
-+#define META_CR_SYSC_XCPARTX_LOCAL_ADDR_HALF_CACHE (0x7)
-+#define META_CR_MMCU_DCACHE_CTRL (0x04830018)
-+#define META_CR_MMCU_ICACHE_CTRL (0x04830020)
-+#define META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN (0x1)
-+
-+/*
-+ ******************************************************************************
-+ * META LDR Format
-+ ******************************************************************************
-+ */
-+/* Block header structure. */
-+struct rogue_meta_ldr_block_hdr {
-+ u32 dev_id;
-+ u32 sl_code;
-+ u32 sl_data;
-+ u16 pc_ctrl;
-+ u16 crc;
-+};
-+
-+/* High level data stream block structure. */
-+struct rogue_meta_ldr_l1_data_blk {
-+ u16 cmd;
-+ u16 length;
-+ u32 next;
-+ u32 cmd_data[4];
-+};
-+
-+/* High level data stream block structure. */
-+struct rogue_meta_ldr_l2_data_blk {
-+ u16 tag;
-+ u16 length;
-+ u32 block_data[4];
-+};
-+
-+/* Config command structure. */
-+struct rogue_meta_ldr_cfg_blk {
-+ u32 type;
-+ u32 block_data[4];
-+};
-+
-+/* Block type definitions */
-+#define ROGUE_META_LDR_COMMENT_TYPE_MASK (0x0010U)
-+#define ROGUE_META_LDR_BLK_IS_COMMENT(x) \
-+ (((x)&ROGUE_META_LDR_COMMENT_TYPE_MASK) != 0U)
-+
-+/*
-+ * Command definitions
-+ * Value Name Description
-+ * 0 LoadMem Load memory with binary data.
-+ * 1 LoadCore Load a set of core registers.
-+ * 2 LoadMMReg Load a set of memory mapped registers.
-+ * 3 StartThreads Set each thread PC and SP, then enable threads.
-+ * 4 ZeroMem Zeros a memory region.
-+ * 5 Config Perform a configuration command.
-+ */
-+#define ROGUE_META_LDR_CMD_MASK (0x000FU)
-+
-+#define ROGUE_META_LDR_CMD_LOADMEM (0x0000U)
-+#define ROGUE_META_LDR_CMD_LOADCORE (0x0001U)
-+#define ROGUE_META_LDR_CMD_LOADMMREG (0x0002U)
-+#define ROGUE_META_LDR_CMD_START_THREADS (0x0003U)
-+#define ROGUE_META_LDR_CMD_ZEROMEM (0x0004U)
-+#define ROGUE_META_LDR_CMD_CONFIG (0x0005U)
-+
-+/*
-+ * Config Command definitions
-+ * Value Name Description
-+ * 0 Pause Pause for x times 100 instructions
-+ * 1 Read Read a value from register - No value return needed.
-+ * Utilises effects of issuing reads to certain registers
-+ * 2 Write Write to mem location
-+ * 3 MemSet Set mem to value
-+ * 4 MemCheck check mem for specific value.
-+ */
-+#define ROGUE_META_LDR_CFG_PAUSE (0x0000)
-+#define ROGUE_META_LDR_CFG_READ (0x0001)
-+#define ROGUE_META_LDR_CFG_WRITE (0x0002)
-+#define ROGUE_META_LDR_CFG_MEMSET (0x0003)
-+#define ROGUE_META_LDR_CFG_MEMCHECK (0x0004)
-+
-+/*
-+ ******************************************************************************
-+ * ROGUE FW segmented MMU definitions
-+ ******************************************************************************
-+ */
-+/* All threads can access the segment. */
-+#define ROGUE_FW_SEGMMU_ALLTHRS (0xf << 8U)
-+/* Writable. */
-+#define ROGUE_FW_SEGMMU_WRITEABLE (0x1U << 1U)
-+/* All threads can access and writable. */
-+#define ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE \
-+ (ROGUE_FW_SEGMMU_ALLTHRS | ROGUE_FW_SEGMMU_WRITEABLE)
-+
-+/* Direct map region 10 used for mapping GPU memory - max 8MB. */
-+#define ROGUE_FW_SEGMMU_DMAP_GPU_ID (10U)
-+#define ROGUE_FW_SEGMMU_DMAP_GPU_ADDR_START (0x07000000U)
-+#define ROGUE_FW_SEGMMU_DMAP_GPU_MAX_SIZE (0x00800000U)
-+
-+/* Segment IDs. */
-+#define ROGUE_FW_SEGMMU_DATA_ID (1U)
-+#define ROGUE_FW_SEGMMU_BOOTLDR_ID (2U)
-+#define ROGUE_FW_SEGMMU_TEXT_ID (ROGUE_FW_SEGMMU_BOOTLDR_ID)
-+
-+/*
-+ * SLC caching strategy in S7 and volcanic is emitted through the segment MMU.
-+ * All the segments configured through the macro ROGUE_FW_SEGMMU_OUTADDR_TOP are
-+ * CACHED in the SLC.
-+ * The interface has been kept the same to simplify the code changes.
-+ * The bifdm argument is ignored (no longer relevant) in S7 and volcanic.
-+ */
-+#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(pers, slc_policy, mmu_ctx) \
-+ ((((u64)((pers)&0x3)) << 52) | (((u64)((mmu_ctx)&0xFF)) << 44) | \
-+ (((u64)((slc_policy)&0x1)) << 40))
-+#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_CACHED(mmu_ctx) \
-+ ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x3, 0x0, mmu_ctx)
-+#define ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC_UNCACHED(mmu_ctx) \
-+ ROGUE_FW_SEGMMU_OUTADDR_TOP_VIVT_SLC(0x0, 0x1, mmu_ctx)
-+
-+/*
-+ * To configure the Page Catalog and BIF-DM fed into the BIF for Garten
-+ * accesses through this segment.
-+ */
-+#define ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(pc, bifdm) \
-+ (((u64)((u64)(pc)&0xFU) << 44U) | ((u64)((u64)(bifdm)&0xFU) << 40U))
-+
-+#define ROGUE_FW_SEGMMU_META_BIFDM_ID (0x7U)
-+
-+/* META segments have 4kB minimum size. */
-+#define ROGUE_FW_SEGMMU_ALIGN (0x1000U)
-+
-+/* Segmented MMU registers (n = segment id). */
-+#define META_CR_MMCU_SEGMENTn_BASE(n) (0x04850000U + ((n)*0x10U))
-+#define META_CR_MMCU_SEGMENTn_LIMIT(n) (0x04850004U + ((n)*0x10U))
-+#define META_CR_MMCU_SEGMENTn_OUTA0(n) (0x04850008U + ((n)*0x10U))
-+#define META_CR_MMCU_SEGMENTn_OUTA1(n) (0x0485000CU + ((n)*0x10U))
-+
-+/*
-+ * The following defines must be recalculated if the Meta MMU segments used
-+ * to access Host-FW data are changed
-+ * Current combinations are:
-+ * - SLC uncached, META cached, FW base address 0x70000000
-+ * - SLC uncached, META uncached, FW base address 0xF0000000
-+ * - SLC cached, META cached, FW base address 0x10000000
-+ * - SLC cached, META uncached, FW base address 0x90000000
-+ */
-+#define ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS (0x10000000U)
-+#define ROGUE_FW_SEGMMU_DATA_META_CACHED (0x0U)
-+#define ROGUE_FW_SEGMMU_DATA_META_UNCACHED (META_MEM_GLOBAL_RANGE_BIT)
-+#define ROGUE_FW_SEGMMU_DATA_META_CACHE_MASK (META_MEM_GLOBAL_RANGE_BIT)
-+/*
-+ * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
-+ * the PTEs for the FW data, not in the Meta Segment MMU, which means these
-+ * defines have no real effect in those cases.
-+ */
-+#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHED (0x0U)
-+#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED (0x60000000U)
-+#define ROGUE_FW_SEGMMU_DATA_VIVT_SLC_CACHE_MASK (0x60000000U)
-+
-+/*
-+ ******************************************************************************
-+ * ROGUE FW Bootloader defaults
-+ ******************************************************************************
-+ */
-+#define ROGUE_FW_BOOTLDR_META_ADDR (0x40000000U)
-+#define ROGUE_FW_BOOTLDR_DEVV_ADDR_0 (0xC0000000U)
-+#define ROGUE_FW_BOOTLDR_DEVV_ADDR_1 (0x000000E1)
-+#define ROGUE_FW_BOOTLDR_DEVV_ADDR \
-+ ((((u64)ROGUE_FW_BOOTLDR_DEVV_ADDR_1) << 32) | \
-+ ROGUE_FW_BOOTLDR_DEVV_ADDR_0)
-+#define ROGUE_FW_BOOTLDR_LIMIT (0x1FFFF000)
-+#define ROGUE_FW_MAX_BOOTLDR_OFFSET (0x1000)
-+
-+/* Bootloader configuration offset is in dwords (512 bytes) */
-+#define ROGUE_FW_BOOTLDR_CONF_OFFSET (0x80)
-+
-+/*
-+ ******************************************************************************
-+ * ROGUE META Stack
-+ ******************************************************************************
-+ */
-+#define ROGUE_META_STACK_SIZE (0x1000U)
-+
-+/*
-+ ******************************************************************************
-+ * ROGUE META Core memory
-+ ******************************************************************************
-+ */
-+/* Code and data both map to the same physical memory. */
-+#define ROGUE_META_COREMEM_CODE_ADDR (0x80000000U)
-+#define ROGUE_META_COREMEM_DATA_ADDR (0x82000000U)
-+#define ROGUE_META_COREMEM_OFFSET_MASK (0x01ffffffU)
-+
-+#define ROGUE_META_IS_COREMEM_CODE(a, b) \
-+ ({ \
-+ u32 _a = (a), _b = (b); \
-+ ((_a) >= ROGUE_META_COREMEM_CODE_ADDR) && \
-+ ((_a) < (ROGUE_META_COREMEM_CODE_ADDR + (_b))); \
-+ })
-+#define ROGUE_META_IS_COREMEM_DATA(a, b) \
-+ ({ \
-+ u32 _a = (a), _b = (b); \
-+ ((_a) >= ROGUE_META_COREMEM_DATA_ADDR) && \
-+ ((_a) < (ROGUE_META_COREMEM_DATA_ADDR + (_b))); \
-+ })
-+/*
-+ ******************************************************************************
-+ * 2nd thread
-+ ******************************************************************************
-+ */
-+#define ROGUE_FW_THR1_PC (0x18930000)
-+#define ROGUE_FW_THR1_SP (0x78890000)
-+
-+/*
-+ ******************************************************************************
-+ * META compatibility
-+ ******************************************************************************
-+ */
-+
-+#define META_CR_CORE_ID (0x04831000)
-+#define META_CR_CORE_ID_VER_SHIFT (16U)
-+#define META_CR_CORE_ID_VER_CLRMSK (0XFF00FFFFU)
-+
-+#define ROGUE_CR_META_MTP218_CORE_ID_VALUE 0x19
-+#define ROGUE_CR_META_MTP219_CORE_ID_VALUE 0x1E
-+#define ROGUE_CR_META_LTP218_CORE_ID_VALUE 0x1C
-+#define ROGUE_CR_META_LTP217_CORE_ID_VALUE 0x1F
-+
-+#define ROGUE_FW_PROCESSOR_META "META"
-+
-+#endif /* __PVR_ROGUE_META_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_mips.h b/drivers/gpu/drm/imagination/pvr_rogue_mips.h
-new file mode 100644
-index 000000000000..270e0dd51e69
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_mips.h
-@@ -0,0 +1,336 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_ROGUE_MIPS_H__
-+#define __PVR_ROGUE_MIPS_H__
-+
-+#include <linux/types.h>
-+
-+/* Utility defines for memory management. */
-+#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K (12)
-+#define ROGUE_MIPSFW_PAGE_SIZE_4K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
-+#define ROGUE_MIPSFW_PAGE_MASK_4K (ROGUE_MIPSFW_PAGE_SIZE_4K - 1)
-+#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_64K (16)
-+#define ROGUE_MIPSFW_PAGE_SIZE_64K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_64K)
-+#define ROGUE_MIPSFW_PAGE_MASK_64K (ROGUE_MIPSFW_PAGE_SIZE_64K - 1)
-+#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_256K (18)
-+#define ROGUE_MIPSFW_PAGE_SIZE_256K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_256K)
-+#define ROGUE_MIPSFW_PAGE_MASK_256K (ROGUE_MIPSFW_PAGE_SIZE_256K - 1)
-+#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_1MB (20)
-+#define ROGUE_MIPSFW_PAGE_SIZE_1MB (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_1MB)
-+#define ROGUE_MIPSFW_PAGE_MASK_1MB (ROGUE_MIPSFW_PAGE_SIZE_1MB - 1)
-+#define ROGUE_MIPSFW_LOG2_PAGE_SIZE_4MB (22)
-+#define ROGUE_MIPSFW_PAGE_SIZE_4MB (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4MB)
-+#define ROGUE_MIPSFW_PAGE_MASK_4MB (ROGUE_MIPSFW_PAGE_SIZE_4MB - 1)
-+#define ROGUE_MIPSFW_LOG2_PTE_ENTRY_SIZE (2)
-+/* log2 page table sizes dependent on FW heap size and page size (for each OS). */
-+#define ROGUE_MIPSFW_LOG2_PAGETABLE_SIZE_4K(pvr_dev) ((pvr_dev)->fw_heap_info.log2_size - \
-+ ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K + \
-+ ROGUE_MIPSFW_LOG2_PTE_ENTRY_SIZE)
-+#define ROGUE_MIPSFW_LOG2_PAGETABLE_SIZE_64K(pvr_dev) ((pvr_dev)->fw_heap_info.log2_size - \
-+ ROGUE_MIPSFW_LOG2_PAGE_SIZE_64K + \
-+ ROGUE_MIPSFW_LOG2_PTE_ENTRY_SIZE)
-+/* Maximum number of page table pages (both Host and MIPS pages). */
-+#define ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES (4)
-+/* Total number of TLB entries. */
-+#define ROGUE_MIPSFW_NUMBER_OF_TLB_ENTRIES (16)
-+/* "Uncached" caching policy. */
-+#define ROGUE_MIPSFW_UNCACHED_CACHE_POLICY (2)
-+/* "Write-back write-allocate" caching policy. */
-+#define ROGUE_MIPSFW_WRITEBACK_CACHE_POLICY (3)
-+/* "Write-through no write-allocate" caching policy. */
-+#define ROGUE_MIPSFW_WRITETHROUGH_CACHE_POLICY (1)
-+/* Cached policy used by MIPS in case of physical bus on 32 bit. */
-+#define ROGUE_MIPSFW_CACHED_POLICY (ROGUE_MIPSFW_WRITEBACK_CACHE_POLICY)
-+/* Cached policy used by MIPS in case of physical bus on more than 32 bit. */
-+#define ROGUE_MIPSFW_CACHED_POLICY_ABOVE_32BIT (ROGUE_MIPSFW_WRITETHROUGH_CACHE_POLICY)
-+/* Total number of Remap entries. */
-+#define ROGUE_MIPSFW_NUMBER_OF_REMAP_ENTRIES (2 * ROGUE_MIPSFW_NUMBER_OF_TLB_ENTRIES)
-+
-+
-+/* MIPS EntryLo/PTE format. */
-+
-+#define ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_SHIFT (31U)
-+#define ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_CLRMSK (0X7FFFFFFF)
-+#define ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000)
-+
-+#define ROGUE_MIPSFW_ENTRYLO_EXEC_INHIBIT_SHIFT (30U)
-+#define ROGUE_MIPSFW_ENTRYLO_EXEC_INHIBIT_CLRMSK (0XBFFFFFFF)
-+#define ROGUE_MIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000)
-+
-+/* Page Frame Number */
-+#define ROGUE_MIPSFW_ENTRYLO_PFN_SHIFT (6)
-+#define ROGUE_MIPSFW_ENTRYLO_PFN_ALIGNSHIFT (12)
-+/* Mask used for the MIPS Page Table in case of physical bus on 32 bit. */
-+#define ROGUE_MIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0)
-+#define ROGUE_MIPSFW_ENTRYLO_PFN_SIZE (20)
-+/* Mask used for the MIPS Page Table in case of physical bus on more than 32 bit. */
-+#define ROGUE_MIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0)
-+#define ROGUE_MIPSFW_ENTRYLO_PFN_SIZE_ABOVE_32BIT (24)
-+#define ROGUE_MIPSFW_ADDR_TO_ENTRYLO_PFN_RSHIFT (ROGUE_MIPSFW_ENTRYLO_PFN_ALIGNSHIFT - \
-+ ROGUE_MIPSFW_ENTRYLO_PFN_SHIFT)
-+
-+#define ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_SHIFT (3U)
-+#define ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7)
-+
-+#define ROGUE_MIPSFW_ENTRYLO_DIRTY_SHIFT (2U)
-+#define ROGUE_MIPSFW_ENTRYLO_DIRTY_CLRMSK (0XFFFFFFFB)
-+#define ROGUE_MIPSFW_ENTRYLO_DIRTY_EN (0X00000004)
-+
-+#define ROGUE_MIPSFW_ENTRYLO_VALID_SHIFT (1U)
-+#define ROGUE_MIPSFW_ENTRYLO_VALID_CLRMSK (0XFFFFFFFD)
-+#define ROGUE_MIPSFW_ENTRYLO_VALID_EN (0X00000002)
-+
-+#define ROGUE_MIPSFW_ENTRYLO_GLOBAL_SHIFT (0U)
-+#define ROGUE_MIPSFW_ENTRYLO_GLOBAL_CLRMSK (0XFFFFFFFE)
-+#define ROGUE_MIPSFW_ENTRYLO_GLOBAL_EN (0X00000001)
-+
-+#define ROGUE_MIPSFW_ENTRYLO_DVG (ROGUE_MIPSFW_ENTRYLO_DIRTY_EN | \
-+ ROGUE_MIPSFW_ENTRYLO_VALID_EN | \
-+ ROGUE_MIPSFW_ENTRYLO_GLOBAL_EN)
-+#define ROGUE_MIPSFW_ENTRYLO_UNCACHED (ROGUE_MIPSFW_UNCACHED_CACHE_POLICY << \
-+ ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_SHIFT)
-+#define ROGUE_MIPSFW_ENTRYLO_DVG_UNCACHED (ROGUE_MIPSFW_ENTRYLO_DVG | \
-+ ROGUE_MIPSFW_ENTRYLO_UNCACHED)
-+
-+
-+/* Remap Range Config Addr Out. */
-+/* These defines refer to the upper half of the Remap Range Config register. */
-+#define ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_MASK (0x0FFFFFF0)
-+#define ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_SHIFT (4) /* wrt upper half of the register. */
-+#define ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_ALIGNSHIFT (12)
-+#define ROGUE_MIPSFW_ADDR_TO_RR_ADDR_OUT_RSHIFT (ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_ALIGNSHIFT - \
-+ ROGUE_MIPSFW_REMAP_RANGE_ADDR_OUT_SHIFT)
-+
-+
-+/*
-+ * Pages to trampoline problematic physical addresses:
-+ * - ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN : 0x1FC0_0000
-+ * - ROGUE_MIPSFW_DATA_REMAP_PHYS_ADDR_IN : 0x1FC0_1000
-+ * - ROGUE_MIPSFW_CODE_REMAP_PHYS_ADDR_IN : 0x1FC0_2000
-+ * - (benign trampoline) : 0x1FC0_3000
-+ * that would otherwise be erroneously remapped by the MIPS wrapper.
-+ * (see "Firmware virtual layout and remap configuration" section below)
-+ */
-+
-+#define ROGUE_MIPSFW_TRAMPOLINE_LOG2_NUMPAGES (2)
-+#define ROGUE_MIPSFW_TRAMPOLINE_NUMPAGES (1 << ROGUE_MIPSFW_TRAMPOLINE_LOG2_NUMPAGES)
-+#define ROGUE_MIPSFW_TRAMPOLINE_SIZE (ROGUE_MIPSFW_TRAMPOLINE_NUMPAGES << \
-+ ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
-+#define ROGUE_MIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE (ROGUE_MIPSFW_TRAMPOLINE_LOG2_NUMPAGES + \
-+ ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
-+
-+#define ROGUE_MIPSFW_TRAMPOLINE_TARGET_PHYS_ADDR (ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
-+#define ROGUE_MIPSFW_TRAMPOLINE_OFFSET(a) ((a) - ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
-+
-+#define ROGUE_MIPSFW_SENSITIVE_ADDR(a) (ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN == \
-+ (~((1 << ROGUE_MIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE) - 1) \
-+ & (a)))
-+
-+/* Firmware virtual layout and remap configuration. */
-+/*
-+ * For each remap region we define:
-+ * - the virtual base used by the Firmware to access code/data through that region
-+ * - the microAptivAP physical address correspondent to the virtual base address,
-+ * used as input address and remapped to the actual physical address
-+ * - log2 of size of the region remapped by the MIPS wrapper, i.e. number of bits from
-+ * the bottom of the base input address that survive onto the output address
-+ * (this defines both the alignment and the maximum size of the remapped region)
-+ * - one or more code/data segments within the remapped region.
-+ */
-+
-+/* Boot remap setup. */
-+#define ROGUE_MIPSFW_BOOT_REMAP_VIRTUAL_BASE (0xBFC00000)
-+#define ROGUE_MIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000)
-+#define ROGUE_MIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE (12)
-+#define ROGUE_MIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE (ROGUE_MIPSFW_BOOT_REMAP_VIRTUAL_BASE)
-+
-+/* Data remap setup. */
-+#define ROGUE_MIPSFW_DATA_REMAP_VIRTUAL_BASE (0xBFC01000)
-+#define ROGUE_MIPSFW_DATA_CACHED_REMAP_VIRTUAL_BASE (0x9FC01000)
-+#define ROGUE_MIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000)
-+#define ROGUE_MIPSFW_DATA_REMAP_LOG2_SEGMENT_SIZE (12)
-+#define ROGUE_MIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE (ROGUE_MIPSFW_DATA_REMAP_VIRTUAL_BASE)
-+
-+/* Code remap setup. */
-+#define ROGUE_MIPSFW_CODE_REMAP_VIRTUAL_BASE (0x9FC02000)
-+#define ROGUE_MIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000)
-+#define ROGUE_MIPSFW_CODE_REMAP_LOG2_SEGMENT_SIZE (12)
-+#define ROGUE_MIPSFW_EXCEPTIONS_VIRTUAL_BASE (ROGUE_MIPSFW_CODE_REMAP_VIRTUAL_BASE)
-+
-+/* Permanent mappings setup. */
-+#define ROGUE_MIPSFW_PT_VIRTUAL_BASE (0xCF000000)
-+#define ROGUE_MIPSFW_REGISTERS_VIRTUAL_BASE (0xCF800000)
-+#define ROGUE_MIPSFW_STACK_VIRTUAL_BASE (0xCF600000)
-+
-+
-+/* Bootloader configuration data. */
-+/*
-+ * Bootloader configuration offset (where ROGUE_MIPSFW_BOOT_DATA lives)
-+ * within the bootloader/NMI data page.
-+ */
-+#define ROGUE_MIPSFW_BOOTLDR_CONF_OFFSET (0x0)
-+
-+/* NMI shared data. */
-+/* Base address of the shared data within the bootloader/NMI data page. */
-+#define ROGUE_MIPSFW_NMI_SHARED_DATA_BASE (0x100)
-+/* Size used by Debug dump data. */
-+#define ROGUE_MIPSFW_NMI_SHARED_SIZE (0x2B0)
-+/* Offsets in the NMI shared area in 32-bit words. */
-+#define ROGUE_MIPSFW_NMI_SYNC_FLAG_OFFSET (0x0)
-+#define ROGUE_MIPSFW_NMI_STATE_OFFSET (0x1)
-+#define ROGUE_MIPSFW_NMI_ERROR_STATE_SET (0x1)
-+
-+/* MIPS boot stage. */
-+#define ROGUE_MIPSFW_BOOT_STAGE_OFFSET (0x400)
-+
-+/*
-+ * MIPS private data in the bootloader data page.
-+ * Memory below this offset is used by the FW only, no interface data allowed.
-+ */
-+#define ROGUE_MIPSFW_PRIVATE_DATA_OFFSET (0x800)
-+
-+struct rogue_mipsfw_boot_data {
-+ u64 stack_phys_addr;
-+ u64 reg_base;
-+ u64 pt_phys_addr[ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES];
-+ u32 pt_log2_page_size;
-+ u32 pt_num_pages;
-+ u32 reserved1;
-+ u32 reserved2;
-+};
-+
-+#define ROGUE_MIPSFW_GET_OFFSET_IN_DWORDS(offset) ((offset) / sizeof(u32))
-+#define ROGUE_MIPSFW_GET_OFFSET_IN_QWORDS(offset) ((offset) / sizeof(u64))
-+
-+/* Used for compatibility checks. */
-+#define ROGUE_MIPSFW_ARCHTYPE_VER_CLRMSK (0xFFFFE3FFU)
-+#define ROGUE_MIPSFW_ARCHTYPE_VER_SHIFT (10U)
-+#define ROGUE_MIPSFW_CORE_ID_VALUE (0x001U)
-+#define ROGUE_FW_PROCESSOR_MIPS "MIPS"
-+
-+/* microAptivAP cache line size. */
-+#define ROGUE_MIPSFW_MICROAPTIVEAP_CACHELINE_SIZE (16U)
-+
-+/*
-+ * The SOCIF transactions are identified with the top 16 bits of the physical address emitted by
-+ * the MIPS.
-+ */
-+#define ROGUE_MIPSFW_WRAPPER_CONFIG_REGBANK_ADDR_ALIGN (16U)
-+
-+/* Values to put in the MIPS selectors for performance counters. */
-+/* Icache accesses in COUNTER0. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ICACHE_ACCESSES_C0 (9U)
-+/* Icache misses in COUNTER1. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ICACHE_MISSES_C1 (9U)
-+
-+/* Dcache accesses in COUNTER0. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_DCACHE_ACCESSES_C0 (10U)
-+/* Dcache misses in COUNTER1. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_DCACHE_MISSES_C1 (11U)
-+
-+/* ITLB instruction accesses in COUNTER0. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_ITLB_INSTR_ACCESSES_C0 (5U)
-+/* JTLB instruction accesses misses in COUNTER1. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_JTLB_INSTR_MISSES_C1 (7U)
-+
-+ /* Instructions completed in COUNTER0. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_INSTR_COMPLETED_C0 (1U)
-+/* JTLB data misses in COUNTER1. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_JTLB_DATA_MISSES_C1 (8U)
-+
-+/* Shift for the Event field in the MIPS perf ctrl registers. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_EVENT_SHIFT (5U)
-+
-+/* Additional flags for performance counters. See MIPS manual for further reference. */
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_USER_MODE (8U)
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_KERNEL_MODE (2U)
-+#define ROGUE_MIPSFW_PERF_COUNT_CTRL_COUNT_EXL (1U)
-+
-+#define ROGUE_MIPSFW_C0_NBHWIRQ 8
-+
-+/* Macros to decode C0_Cause register. */
-+#define ROGUE_MIPSFW_C0_CAUSE_EXCCODE(cause) (((cause) & 0x7c) >> 2)
-+#define ROGUE_MIPSFW_C0_CAUSE_EXCCODE_FWERROR 9
-+/* Use only when Coprocessor Unusable exception. */
-+#define ROGUE_MIPSFW_C0_CAUSE_UNUSABLE_UNIT(cause) (((cause) >> 28) & 0x3)
-+#define ROGUE_MIPSFW_C0_CAUSE_PENDING_HWIRQ(cause) (((cause) & 0x3fc00) >> 10)
-+#define ROGUE_MIPSFW_C0_CAUSE_FDCIPENDING (1 << 21)
-+#define ROGUE_MIPSFW_C0_CAUSE_IV (1 << 23)
-+#define ROGUE_MIPSFW_C0_CAUSE_IC (1 << 25)
-+#define ROGUE_MIPSFW_C0_CAUSE_PCIPENDING (1 << 26)
-+#define ROGUE_MIPSFW_C0_CAUSE_TIPENDING (1 << 30)
-+#define ROGUE_MIPSFW_C0_CAUSE_BRANCH_DELAY (1 << 31)
-+
-+/* Macros to decode C0_Debug register. */
-+#define ROGUE_MIPSFW_C0_DEBUG_EXCCODE(debug) (((debug) >> 10) & 0x1f)
-+#define ROGUE_MIPSFW_C0_DEBUG_DSS (1 << 0)
-+#define ROGUE_MIPSFW_C0_DEBUG_DBP (1 << 1)
-+#define ROGUE_MIPSFW_C0_DEBUG_DDBL (1 << 2)
-+#define ROGUE_MIPSFW_C0_DEBUG_DDBS (1 << 3)
-+#define ROGUE_MIPSFW_C0_DEBUG_DIB (1 << 4)
-+#define ROGUE_MIPSFW_C0_DEBUG_DINT (1 << 5)
-+#define ROGUE_MIPSFW_C0_DEBUG_DIBIMPR (1 << 6)
-+#define ROGUE_MIPSFW_C0_DEBUG_DDBLIMPR (1 << 18)
-+#define ROGUE_MIPSFW_C0_DEBUG_DDBSIMPR (1 << 19)
-+#define ROGUE_MIPSFW_C0_DEBUG_IEXI (1 << 20)
-+#define ROGUE_MIPSFW_C0_DEBUG_DBUSEP (1 << 21)
-+#define ROGUE_MIPSFW_C0_DEBUG_CACHEEP (1 << 22)
-+#define ROGUE_MIPSFW_C0_DEBUG_MCHECKP (1 << 23)
-+#define ROGUE_MIPSFW_C0_DEBUG_IBUSEP (1 << 24)
-+#define ROGUE_MIPSFW_C0_DEBUG_DM (1 << 30)
-+#define ROGUE_MIPSFW_C0_DEBUG_DBD (1 << 31)
-+
-+/* Macros to decode TLB entries. */
-+#define ROGUE_MIPSFW_TLB_GET_MASK(page_mask) (((page_mask) >> 13) & 0XFFFFU)
-+/* Page size in KB. */
-+#define ROGUE_MIPSFW_TLB_GET_PAGE_SIZE(page_mask) ((((page_mask) | 0x1FFF) + 1) >> 11)
-+/* Page size in KB. */
-+#define ROGUE_MIPSFW_TLB_GET_PAGE_MASK(page_size) ((((page_size) << 11) - 1) & ~0x7FF)
-+#define ROGUE_MIPSFW_TLB_GET_VPN2(entry_hi) ((entry_hi) >> 13)
-+#define ROGUE_MIPSFW_TLB_GET_COHERENCY(entry_lo) (((entry_lo) >> 3) & 0x7U)
-+#define ROGUE_MIPSFW_TLB_GET_PFN(entry_lo) (((entry_lo) >> 6) & 0XFFFFFU)
-+/* GET_PA uses a non-standard PFN mask for 36 bit addresses. */
-+#define ROGUE_MIPSFW_TLB_GET_PA(entry_lo) (((u64)(entry_lo) & \
-+ ROGUE_MIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT) << 6)
-+#define ROGUE_MIPSFW_TLB_GET_INHIBIT(entry_lo) (((entry_lo) >> 30) & 0x3U)
-+#define ROGUE_MIPSFW_TLB_GET_DGV(entry_lo) ((entry_lo) & 0x7U)
-+#define ROGUE_MIPSFW_TLB_GLOBAL (1U)
-+#define ROGUE_MIPSFW_TLB_VALID (1U << 1)
-+#define ROGUE_MIPSFW_TLB_DIRTY (1U << 2)
-+#define ROGUE_MIPSFW_TLB_XI (1U << 30)
-+#define ROGUE_MIPSFW_TLB_RI (1U << 31)
-+
-+#define ROGUE_MIPSFW_REMAP_GET_REGION_SIZE(region_size_encoding) (1 << (((region_size_encoding) \
-+ + 1) << 1))
-+
-+struct rogue_mips_tlb_entry {
-+ u32 tlb_page_mask;
-+ u32 tlb_hi;
-+ u32 tlb_lo0;
-+ u32 tlb_lo1;
-+};
-+
-+struct rogue_mips_remap_entry {
-+ u32 remap_addr_in; /* Always 4k aligned. */
-+ u32 remap_addr_out; /* Always 4k aligned. */
-+ u32 remap_region_size;
-+};
-+
-+struct rogue_mips_state {
-+ u32 error_state; /* This must come first in the structure. */
-+ u32 error_epc;
-+ u32 status_register;
-+ u32 cause_register;
-+ u32 bad_register;
-+ u32 epc;
-+ u32 sp;
-+ u32 debug;
-+ u32 depc;
-+ u32 bad_instr;
-+ u32 unmapped_address;
-+ struct rogue_mips_tlb_entry tlb[ROGUE_MIPSFW_NUMBER_OF_TLB_ENTRIES];
-+ struct rogue_mips_remap_entry remap[ROGUE_MIPSFW_NUMBER_OF_REMAP_ENTRIES];
-+};
-+
-+#endif /* __PVR_ROGUE_MIPS_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_rogue_mmu_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_mmu_defs.h
-new file mode 100644
-index 000000000000..040978f40cdb
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_rogue_mmu_defs.h
-@@ -0,0 +1,136 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+/* *** Autogenerated C -- do not edit *** */
-+
-+#ifndef __PVR_ROGUE_MMU_DEFS_H__
-+#define __PVR_ROGUE_MMU_DEFS_H__
-+
-+#define ROGUE_MMU_DEFS_REVISION 0
-+
-+#define ROGUE_BIF_DM_ENCODING_VERTEX (0x00000000U)
-+#define ROGUE_BIF_DM_ENCODING_PIXEL (0x00000001U)
-+#define ROGUE_BIF_DM_ENCODING_COMPUTE (0x00000002U)
-+#define ROGUE_BIF_DM_ENCODING_TLA (0x00000003U)
-+#define ROGUE_BIF_DM_ENCODING_PB_VCE (0x00000004U)
-+#define ROGUE_BIF_DM_ENCODING_PB_TE (0x00000005U)
-+#define ROGUE_BIF_DM_ENCODING_META (0x00000007U)
-+#define ROGUE_BIF_DM_ENCODING_HOST (0x00000008U)
-+#define ROGUE_BIF_DM_ENCODING_PM_ALIST (0x00000009U)
-+
-+#define ROGUE_MMUCTRL_VADDR_PT_L2_INDEX_SHIFT (30U)
-+#define ROGUE_MMUCTRL_VADDR_PT_L2_INDEX_CLRMSK (0xFFFFFF003FFFFFFFULL)
-+#define ROGUE_MMUCTRL_VADDR_PT_L1_INDEX_SHIFT (21U)
-+#define ROGUE_MMUCTRL_VADDR_PT_L1_INDEX_CLRMSK (0xFFFFFFFFC01FFFFFULL)
-+#define ROGUE_MMUCTRL_VADDR_PT_L0_INDEX_SHIFT (12U)
-+#define ROGUE_MMUCTRL_VADDR_PT_L0_INDEX_CLRMSK (0xFFFFFFFFFFE00FFFULL)
-+
-+#define ROGUE_MMUCTRL_ENTRIES_PT_L2_VALUE (0x00000400U)
-+#define ROGUE_MMUCTRL_ENTRIES_PT_L1_VALUE (0x00000200U)
-+#define ROGUE_MMUCTRL_ENTRIES_PT_L0_VALUE (0x00000200U)
-+
-+#define ROGUE_MMUCTRL_ENTRY_SIZE_PT_L2_VALUE (0x00000020U)
-+#define ROGUE_MMUCTRL_ENTRY_SIZE_PT_L1_VALUE (0x00000040U)
-+#define ROGUE_MMUCTRL_ENTRY_SIZE_PT_L0_VALUE (0x00000040U)
-+
-+#define ROGUE_MMUCTRL_PAGE_SIZE_MASK (0x00000007U)
-+#define ROGUE_MMUCTRL_PAGE_SIZE_4KB (0x00000000U)
-+#define ROGUE_MMUCTRL_PAGE_SIZE_16KB (0x00000001U)
-+#define ROGUE_MMUCTRL_PAGE_SIZE_64KB (0x00000002U)
-+#define ROGUE_MMUCTRL_PAGE_SIZE_256KB (0x00000003U)
-+#define ROGUE_MMUCTRL_PAGE_SIZE_1MB (0x00000004U)
-+#define ROGUE_MMUCTRL_PAGE_SIZE_2MB (0x00000005U)
-+
-+#define ROGUE_MMUCTRL_PAGE_4KB_RANGE_SHIFT (12U)
-+#define ROGUE_MMUCTRL_PAGE_4KB_RANGE_CLRMSK (0xFFFFFF0000000FFFULL)
-+
-+#define ROGUE_MMUCTRL_PAGE_16KB_RANGE_SHIFT (14U)
-+#define ROGUE_MMUCTRL_PAGE_16KB_RANGE_CLRMSK (0xFFFFFF0000003FFFULL)
-+
-+#define ROGUE_MMUCTRL_PAGE_64KB_RANGE_SHIFT (16U)
-+#define ROGUE_MMUCTRL_PAGE_64KB_RANGE_CLRMSK (0xFFFFFF000000FFFFULL)
-+
-+#define ROGUE_MMUCTRL_PAGE_256KB_RANGE_SHIFT (18U)
-+#define ROGUE_MMUCTRL_PAGE_256KB_RANGE_CLRMSK (0xFFFFFF000003FFFFULL)
-+
-+#define ROGUE_MMUCTRL_PAGE_1MB_RANGE_SHIFT (20U)
-+#define ROGUE_MMUCTRL_PAGE_1MB_RANGE_CLRMSK (0xFFFFFF00000FFFFFULL)
-+
-+#define ROGUE_MMUCTRL_PAGE_2MB_RANGE_SHIFT (21U)
-+#define ROGUE_MMUCTRL_PAGE_2MB_RANGE_CLRMSK (0xFFFFFF00001FFFFFULL)
-+
-+#define ROGUE_MMUCTRL_PT_L0_BASE_4KB_RANGE_SHIFT (12U)
-+#define ROGUE_MMUCTRL_PT_L0_BASE_4KB_RANGE_CLRMSK (0xFFFFFF0000000FFFULL)
-+
-+#define ROGUE_MMUCTRL_PT_L0_BASE_16KB_RANGE_SHIFT (10U)
-+#define ROGUE_MMUCTRL_PT_L0_BASE_16KB_RANGE_CLRMSK (0xFFFFFF00000003FFULL)
-+
-+#define ROGUE_MMUCTRL_PT_L0_BASE_64KB_RANGE_SHIFT (8U)
-+#define ROGUE_MMUCTRL_PT_L0_BASE_64KB_RANGE_CLRMSK (0xFFFFFF00000000FFULL)
-+
-+#define ROGUE_MMUCTRL_PT_L0_BASE_256KB_RANGE_SHIFT (6U)
-+#define ROGUE_MMUCTRL_PT_L0_BASE_256KB_RANGE_CLRMSK (0xFFFFFF000000003FULL)
-+
-+#define ROGUE_MMUCTRL_PT_L0_BASE_1MB_RANGE_SHIFT (5U)
-+#define ROGUE_MMUCTRL_PT_L0_BASE_1MB_RANGE_CLRMSK (0xFFFFFF000000001FULL)
-+
-+#define ROGUE_MMUCTRL_PT_L0_BASE_2MB_RANGE_SHIFT (5U)
-+#define ROGUE_MMUCTRL_PT_L0_BASE_2MB_RANGE_CLRMSK (0xFFFFFF000000001FULL)
-+
-+#define ROGUE_MMUCTRL_PT_L0_DATA_PM_META_PROTECT_SHIFT (62U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_PM_META_PROTECT_CLRMSK (0xBFFFFFFFFFFFFFFFULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_PM_META_PROTECT_EN (0x4000000000000000ULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_VP_PAGE_HI_SHIFT (40U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_VP_PAGE_HI_CLRMSK (0xC00000FFFFFFFFFFULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_PAGE_SHIFT (12U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_PAGE_CLRMSK (0xFFFFFF0000000FFFULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_VP_PAGE_LO_SHIFT (6U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_VP_PAGE_LO_CLRMSK (0xFFFFFFFFFFFFF03FULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_ENTRY_PENDING_SHIFT (5U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_ENTRY_PENDING_CLRMSK (0xFFFFFFFFFFFFFFDFULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_ENTRY_PENDING_EN (0x0000000000000020ULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_PM_SRC_SHIFT (4U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_PM_SRC_CLRMSK (0xFFFFFFFFFFFFFFEFULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_PM_SRC_EN (0x0000000000000010ULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_SLC_BYPASS_CTRL_SHIFT (3U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_SLC_BYPASS_CTRL_CLRMSK (0xFFFFFFFFFFFFFFF7ULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_SLC_BYPASS_CTRL_EN (0x0000000000000008ULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_CC_SHIFT (2U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_CC_CLRMSK (0xFFFFFFFFFFFFFFFBULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_CC_EN (0x0000000000000004ULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_READ_ONLY_SHIFT (1U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_READ_ONLY_CLRMSK (0xFFFFFFFFFFFFFFFDULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_READ_ONLY_EN (0x0000000000000002ULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_VALID_SHIFT (0U)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_VALID_CLRMSK (0xFFFFFFFFFFFFFFFEULL)
-+#define ROGUE_MMUCTRL_PT_L0_DATA_VALID_EN (0x0000000000000001ULL)
-+
-+#define ROGUE_MMUCTRL_PT_L1_DATA_ENTRY_PENDING_SHIFT (40U)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_ENTRY_PENDING_CLRMSK (0xFFFFFEFFFFFFFFFFULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_ENTRY_PENDING_EN (0x0000010000000000ULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PT_L0_BASE_SHIFT (5U)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PT_L0_BASE_CLRMSK (0xFFFFFF000000001FULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PAGE_SIZE_SHIFT (1U)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PAGE_SIZE_CLRMSK (0xFFFFFFFFFFFFFFF1ULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PAGE_SIZE_4KB (0x0000000000000000ULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PAGE_SIZE_16KB (0x0000000000000002ULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PAGE_SIZE_64KB (0x0000000000000004ULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PAGE_SIZE_256KB (0x0000000000000006ULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PAGE_SIZE_1MB (0x0000000000000008ULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_PAGE_SIZE_2MB (0x000000000000000aULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_VALID_SHIFT (0U)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_VALID_CLRMSK (0xFFFFFFFFFFFFFFFEULL)
-+#define ROGUE_MMUCTRL_PT_L1_DATA_VALID_EN (0x0000000000000001ULL)
-+
-+#define ROGUE_MMUCTRL_PT_L2_DATA_PT_L1_BASE_SHIFT (4U)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_PT_L1_BASE_CLRMSK (0x0000000FU)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_PT_L1_BASE_ALIGNSHIFT (12U)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_PT_L1_BASE_ALIGNSIZE (4096U)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_ENTRY_PENDING_SHIFT (1U)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_ENTRY_PENDING_CLRMSK (0xFFFFFFFDU)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_ENTRY_PENDING_EN (0x00000002U)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_VALID_SHIFT (0U)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_VALID_CLRMSK (0xFFFFFFFEU)
-+#define ROGUE_MMUCTRL_PT_L2_DATA_VALID_EN (0x00000001U)
-+
-+#endif /* __PVR_ROGUE_MMU_DEFS_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_vendor.h b/drivers/gpu/drm/imagination/pvr_vendor.h
-new file mode 100644
-index 000000000000..fa52e21f4bbc
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_vendor.h
-@@ -0,0 +1,77 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_VENDOR_H__
-+#define __PVR_VENDOR_H__
-+
-+/* Forward declaration from "pvr_device.h". */
-+struct pvr_device;
-+
-+/**
-+ * struct pvr_vendor_callbacks - Vendor-specific callbacks
-+ */
-+struct pvr_vendor_callbacks {
-+ /**
-+ * @init: Initialise vendor-specific functionality
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This callback should initialise any vendor-specific data in @pvr_dev->vendor.data, and
-+ * retrieve any required resources. It should not attempt to power on the GPU or interact
-+ * with the GPU hardware in any way.
-+ *
-+ * This callback is optional.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any negative error (see individual implementations for details).
-+ */
-+ int (*init)(struct pvr_device *pvr_dev);
-+
-+ /**
-+ * @fini: Close vendor-specific functionality
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This callback is optional.
-+ */
-+ void (*fini)(struct pvr_device *pvr_dev);
-+
-+ /**
-+ * @power_enable: Enable GPU power
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * On function entry the GPU clocks in device tree will be enabled, but the GPU will
-+ * otherwise be unpowered.
-+ *
-+ * On function exit the GPU will be fully powered and the register file will be accessible.
-+ *
-+ * This callback is optional.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%EINVAL if the GPU was already powered, or
-+ * * -%EBUSY if the GPU fails to power on.
-+ */
-+ int (*power_enable)(struct pvr_device *pvr_dev);
-+
-+ /**
-+ * @power_disable: Disable GPU power
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * On function entry the GPU will be fully powered.
-+ *
-+ * On function exit the GPU will be unpowered. This function will not affect the clocks
-+ * defined in device tree; the driver will disable these later.
-+ *
-+ * This callback is optional.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * -%EINVAL if the GPU was already unpowered, or
-+ * * -%EBUSY if the GPU fails to power off.
-+ */
-+ int (*power_disable)(struct pvr_device *pvr_dev);
-+};
-+
-+extern const struct pvr_vendor_callbacks pvr_mt8173_callbacks;
-+
-+#endif /* __PVR_VENDOR_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_vm.c b/drivers/gpu/drm/imagination/pvr_vm.c
-new file mode 100644
-index 000000000000..e2daa99427a9
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_vm.c
-@@ -0,0 +1,4177 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_vm.h"
-+
-+#include "pvr_device.h"
-+#include "pvr_gem.h"
-+#include "pvr_rogue_heap_config.h"
-+#include "pvr_rogue_mmu_defs.h"
-+
-+#include <drm/drm_gem.h>
-+
-+#include <linux/bitops.h>
-+#include <linux/compiler_attributes.h>
-+#include <linux/dma-direction.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/err.h>
-+#include <linux/errno.h>
-+#include <linux/gfp.h>
-+#include <linux/highmem.h>
-+#include <linux/interval_tree_generic.h>
-+#include <linux/kernel.h>
-+#include <linux/limits.h>
-+#include <linux/lockdep.h>
-+#include <linux/math.h>
-+#include <linux/mutex.h>
-+#include <linux/overflow.h>
-+#include <linux/rbtree.h>
-+#include <linux/scatterlist.h>
-+#include <linux/sizes.h>
-+#include <linux/slab.h>
-+#include <linux/stddef.h>
-+#include <linux/string.h>
-+#include <linux/types.h>
-+
-+struct pvr_vm_mapping;
-+
-+static int
-+pvr_vm_mapping_unmap(struct pvr_vm_context *vm_ctx, struct pvr_vm_mapping *mapping);
-+static void
-+pvr_vm_mapping_fini(struct pvr_vm_mapping *mapping);
-+
-+/**
-+ * pvr_mmu_flush() - Request flush of MMU caches
-+ * @pvr_dev: Target PowerVR device
-+ *
-+ * This must be called following any possible change to the MMU page tables.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_kccb_send_cmd(), or
-+ * * Any error returned by pvr_kccb_wait_for_completion().
-+ */
-+int
-+pvr_vm_mmu_flush(struct pvr_device *pvr_dev)
-+{
-+ struct rogue_fwif_kccb_cmd cmd_mmu_cache;
-+ struct rogue_fwif_mmucachedata *cmd_mmu_cache_data =
-+ &cmd_mmu_cache.cmd_data.mmu_cache_data;
-+ u32 slot;
-+ int err;
-+
-+ /* Can't flush MMU if the firmware hasn't booted yet. */
-+ if (!pvr_dev->fw_booted) {
-+ err = 0;
-+ goto err_out;
-+ }
-+
-+ cmd_mmu_cache.cmd_type = ROGUE_FWIF_KCCB_CMD_MMUCACHE;
-+ /* Request a complete MMU flush, across all pagetable levels, TLBs and contexts. */
-+ cmd_mmu_cache_data->cache_flags = ROGUE_FWIF_MMUCACHEDATA_FLAGS_PT |
-+ ROGUE_FWIF_MMUCACHEDATA_FLAGS_PD |
-+ ROGUE_FWIF_MMUCACHEDATA_FLAGS_PC |
-+ ROGUE_FWIF_MMUCACHEDATA_FLAGS_TLB |
-+ ROGUE_FWIF_MMUCACHEDATA_FLAGS_INTERRUPT;
-+ WARN_ON(!pvr_gem_get_fw_addr(pvr_dev->fw_mmucache_sync_obj,
-+ &cmd_mmu_cache_data->mmu_cache_sync_fw_addr));
-+ cmd_mmu_cache_data->mmu_cache_sync_update_value = 0;
-+
-+ err = pvr_kccb_send_cmd(pvr_dev, &cmd_mmu_cache, &slot);
-+ if (err)
-+ goto err_out;
-+
-+ err = pvr_kccb_wait_for_completion(pvr_dev, slot, HZ);
-+ if (err)
-+ goto err_out;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * DOC: PowerVR Virtual Memory Handling
-+ *
-+ * There's a lot going on in this section... TODO
-+ *
-+ * .. admonition:: Note on page table naming
-+ *
-+ * This file uses a different naming convention for page table levels than
-+ * the original DDK materials. Since page table implementation details are
-+ * not exposed outside this file, the description of the name mapping exists
-+ * here in its normative form:
-+ *
-+ * * L0 page table => DDK page table
-+ * * L1 page table => DDK page directory
-+ * * L2 page table => DDK page catalog
-+ *
-+ * The variable/function naming convention in this file is
-+ * ``page_table_lx_*`` where x is either ``0``, ``1`` or ``2`` to represent
-+ * the level of the page table structure. The name ``page_table_*`` without
-+ * the ``_lx`` suffix is used for references to the entire tree structure
-+ * including all three levels, or an operation or value which is
-+ * level-agnostic.
-+ */
-+
-+/**
-+ * PVR_IDX_INVALID - Default value for a u16-based index.
-+ *
-+ * This value cannot be zero, since zero is a valid index value.
-+ */
-+#define PVR_IDX_INVALID ((u16)(-1))
-+
-+/**
-+ * DOC: VM backing pages
-+ *
-+ * While the page tables hold memory accessible to the rest of the driver,
-+ * the page tables themselves must have memory allocated to back them. We
-+ * call this memory "VM backing pages". Conveniently, each page table is
-+ * (currently) exactly 4KiB, as defined by %PVR_VM_BACKING_PAGE_SIZE. We
-+ * currently support any CPU page size of this size or greater by ignoring
-+ * any space after the first 4KiB of a CPU page allocated as a VM backing page.
-+ *
-+ * .. admonition:: Future work
-+ *
-+ * We should be able to efficiently support CPU page sizes greater than 4KiB
-+ * by allocating multiple page tables to each CPU page. It is unlikely
-+ * that we will ever need to support CPU page sizes less than 4KiB.
-+ *
-+ * Usage
-+ * -----
-+ * To add this functionality to a structure which wraps a raw page table, embed
-+ * an instance of &struct pvr_vm_backing_page in the wrapper struct. Call
-+ * pvr_vm_backing_page_init() to allocate and map the backing page, and
-+ * pvr_vm_backing_page_fini() to perform the reverse operations when you're
-+ * finished with it. Use pvr_vm_backing_page_sync() to flush the memory from
-+ * the host to the device. As this is an expensive operation (calling out to
-+ * dma_sync_single_for_device()), be sure to perform all necessary changes to
-+ * the backing memory before calling it.
-+ *
-+ * Between calls to pvr_vm_backing_page_init() and pvr_vm_backing_page_fini(),
-+ * the public fields of &struct pvr_vm_backing_page can be used to access the
-+ * allocated page. To access the memory from the CPU, use
-+ * &pvr_vm_backing_page.host_ptr. For an address which can be passed to the
-+ * device, use &pvr_vm_backing_page.dma_addr.
-+ *
-+ * It is expected that the embedded &struct pvr_vm_backing_page will be zeroed
-+ * before calling pvr_vm_backing_page_init(). In return,
-+ * pvr_vm_backing_page_fini() will re-zero it before returning. You can
-+ * therefore compare the value of either &pvr_vm_backing_page.dma_addr or
-+ * &pvr_vm_backing_page.host_ptr to zero or %NULL to check if the backing
-+ * page is ready for use.
-+ *
-+ * .. note:: This API is not expected to be exposed outside ``pvr_vm.c``.
-+ */
-+/**
-+ * DOC: VM backing pages (constants)
-+ *
-+ * .. c:macro:: PVR_VM_BACKING_PAGE_SIZE
-+ *
-+ * Page size of a PowerVR device's integrated MMU. The CPU page size must be
-+ * at least as large as this value for the current implementation; this is
-+ * checked at compile-time.
-+ */
-+
-+/**
-+ * PVR_VM_BACKING_PAGE_SIZE - Page size of a PowerVR device's integrated MMU.
-+ *
-+ * *This doc comment is not rendered - see DOC: VM backing pages (constants).*
-+ */
-+#define PVR_VM_BACKING_PAGE_SIZE SZ_4K
-+static_assert(PAGE_SIZE >= PVR_VM_BACKING_PAGE_SIZE);
-+
-+/**
-+ * struct pvr_vm_backing_page - Represents a single page used to back a page
-+ * table of any level.
-+ */
-+struct pvr_vm_backing_page {
-+ /** @dma_addr: DMA (quasi-physical) address of this page. */
-+ dma_addr_t dma_addr;
-+ /** @host_ptr: CPU address of this page. */
-+ void *host_ptr;
-+
-+ /**
-+ * @pvr_dev: The PowerVR device to which this page is associated.
-+ * **For internal use only.**
-+ */
-+ struct pvr_device *pvr_dev;
-+};
-+
-+/**
-+ * pvr_vm_backing_page_init() - Initialize a VM backing page.
-+ * @page: Target backing page.
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * This function performs three distinct operations:
-+ *
-+ * 1. Allocate a single page,
-+ * 2. Map the page to the CPU, and
-+ * 3. Map the page to DMA-space.
-+ *
-+ * It is expected that @page be zeroed (e.g. from kzalloc()) before calling
-+ * this function.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%ENOMEM if allocation of the backing page or mapping of the backing
-+ * page to DMA fails.
-+ */
-+static int
-+pvr_vm_backing_page_init(struct pvr_vm_backing_page *page,
-+ struct pvr_device *pvr_dev)
-+{
-+ struct device *dev = from_pvr_device(pvr_dev)->dev;
-+
-+ struct page *raw_page;
-+ int err;
-+
-+ dma_addr_t dma_addr;
-+ void *host_ptr;
-+
-+ raw_page = alloc_page(__GFP_ZERO | GFP_KERNEL);
-+ if (!raw_page) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ host_ptr = kmap(raw_page);
-+
-+ dma_addr = dma_map_page(dev, raw_page, 0, PVR_VM_BACKING_PAGE_SIZE,
-+ DMA_TO_DEVICE);
-+ if (dma_mapping_error(dev, dma_addr)) {
-+ err = -ENOMEM;
-+ goto err_unmap_free_page;
-+ }
-+
-+ page->dma_addr = dma_addr;
-+ page->host_ptr = host_ptr;
-+ page->pvr_dev = pvr_dev;
-+
-+ return 0;
-+
-+err_unmap_free_page:
-+ kunmap(raw_page);
-+ __free_page(raw_page);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_backing_page_fini() - Teardown a VM backing page.
-+ * @page: Target backing page.
-+ *
-+ * This function performs the mirror operations to pvr_vm_backing_page_init(),
-+ * in reverse order:
-+ *
-+ * 1. Unmap the page from DMA-space,
-+ * 2. Unmap the page from the CPU, and
-+ * 3. Free the page.
-+ *
-+ * It also zeros @page.
-+ *
-+ * It is a no-op to call this function a second (or further) time on any @page.
-+ */
-+static void
-+pvr_vm_backing_page_fini(struct pvr_vm_backing_page *page)
-+{
-+ struct device *dev = from_pvr_device(page->pvr_dev)->dev;
-+ struct page *raw_page = kmap_to_page(page->host_ptr);
-+
-+ /* Do nothing if no allocation is present. */
-+ if (!page->pvr_dev)
-+ return;
-+
-+ dma_unmap_page(dev, page->dma_addr, PVR_VM_BACKING_PAGE_SIZE,
-+ DMA_TO_DEVICE);
-+
-+ kunmap(raw_page);
-+
-+ __free_page(raw_page);
-+
-+ memset(page, 0, sizeof(*page));
-+}
-+
-+/**
-+ * pvr_vm_backing_page_sync() - Flush a VM backing page from the CPU to the
-+ * device.
-+ * @page: Target backing page.
-+ *
-+ * .. caution::
-+ *
-+ * **This is an expensive function call.** Only call
-+ * pvr_vm_backing_page_sync() once you're sure you have no more changes to
-+ * make to the backing page in the immediate future.
-+ */
-+static void
-+pvr_vm_backing_page_sync(struct pvr_vm_backing_page *page)
-+{
-+ struct device *dev;
-+
-+ /*
-+ * Do nothing if no allocation is present. This may be the case if
-+ * we are unmapping pages.
-+ */
-+ if (!page->pvr_dev)
-+ return;
-+
-+ dev = from_pvr_device(page->pvr_dev)->dev;
-+
-+ dma_sync_single_for_device(dev, page->dma_addr,
-+ PVR_VM_BACKING_PAGE_SIZE, DMA_TO_DEVICE);
-+}
-+
-+/**
-+ * DOC: Raw page tables
-+ *
-+ * These types define the lowest level representation of the page table
-+ * structure. This is the format which a PowerVR device's MMU can interpret
-+ * directly. As such, their definitions are taken directly from hardware
-+ * documentation.
-+ *
-+ * To store additional information required by the driver, we use
-+ * :ref:`mirror page tables<Mirror page tables>`. In most cases, the mirror
-+ * types are the ones you want to use for handles.
-+ */
-+
-+#define PVR_PAGE_TABLE_TYPEOF_ENTRY(level_) \
-+ typeof_member(struct pvr_page_table_l##level_##_entry_raw, val)
-+
-+#define PVR_PAGE_TABLE_FIELD_GET(level_, field_, entry_) \
-+ (((entry_).val & \
-+ ~ROGUE_MMUCTRL_PT_L##level_##_DATA_##field_##_CLRMSK) >> \
-+ ROGUE_MMUCTRL_PT_L##level_##_DATA_##field_##_SHIFT)
-+
-+#define PVR_PAGE_TABLE_FIELD_PREP(level_, field_, val_) \
-+ ((((PVR_PAGE_TABLE_TYPEOF_ENTRY(level_))(val_)) \
-+ << ROGUE_MMUCTRL_PT_L##level_##_DATA_##field_##_SHIFT) & \
-+ ~ROGUE_MMUCTRL_PT_L##level_##_DATA_##field_##_CLRMSK)
-+
-+/**
-+ * struct pvr_page_table_l2_entry_raw - A single entry in a level 2 page table.
-+ *
-+ * This type is a structure for type-checking purposes. At compile-time, its
-+ * size is checked against %ROGUE_MMUCTRL_ENTRY_SIZE_PC_VALUE.
-+ *
-+ * The value stored in this structure can be decoded using the following bitmap:
-+ *
-+ * .. flat-table::
-+ * :widths: 1 5
-+ * :stub-columns: 1
-+ *
-+ * * - 31..4
-+ * - **Level 1 Page Table Base Address:** Bits 39..12 of the L1
-+ * page table base address, which is 4KiB aligned.
-+ *
-+ * * - 3..2
-+ * - *(reserved)*
-+ *
-+ * * - 1
-+ * - **Pending:** When valid bit is not set, indicates that a valid
-+ * entry is pending and the MMU should wait for the driver to map
-+ * the entry. This is used to support page demand mapping of
-+ * memory.
-+ *
-+ * * - 0
-+ * - **Valid:** Indicates that the entry contains a valid L1 page
-+ * table. If the valid bit is not set, then an attempted use of
-+ * the page would result in a page fault.
-+ */
-+struct pvr_page_table_l2_entry_raw {
-+ /** @val: The raw value of this entry. */
-+ u32 val;
-+} __packed;
-+static_assert(sizeof(struct pvr_page_table_l2_entry_raw) * 8 ==
-+ ROGUE_MMUCTRL_ENTRY_SIZE_PT_L2_VALUE);
-+
-+static __always_inline bool
-+pvr_page_table_l2_entry_raw_is_valid(struct pvr_page_table_l2_entry_raw entry)
-+{
-+ return PVR_PAGE_TABLE_FIELD_GET(2, VALID, entry);
-+}
-+
-+static __always_inline void
-+pvr_page_table_l2_entry_raw_set(struct pvr_page_table_l2_entry_raw *entry,
-+ dma_addr_t child_table_dma_addr)
-+{
-+ child_table_dma_addr >>= ROGUE_MMUCTRL_PT_L2_DATA_PT_L1_BASE_ALIGNSHIFT;
-+
-+ entry->val =
-+ PVR_PAGE_TABLE_FIELD_PREP(2, VALID, true) |
-+ PVR_PAGE_TABLE_FIELD_PREP(2, ENTRY_PENDING, false) |
-+ PVR_PAGE_TABLE_FIELD_PREP(2, PT_L1_BASE, child_table_dma_addr);
-+}
-+
-+static __always_inline void
-+pvr_page_table_l2_entry_raw_clear(struct pvr_page_table_l2_entry_raw *entry)
-+{
-+ entry->val = 0;
-+}
-+
-+/**
-+ * struct pvr_page_table_l1_entry_raw - A single entry in a level 1 page table.
-+ *
-+ * This type is a structure for type-checking purposes. At compile-time, its
-+ * size is checked against %ROGUE_MMUCTRL_ENTRY_SIZE_PD_VALUE.
-+ *
-+ * The value stored in this structure can be decoded using the following bitmap:
-+ *
-+ * .. flat-table::
-+ * :widths: 1 5
-+ * :stub-columns: 1
-+ *
-+ * * - 63..41
-+ * - *(reserved)*
-+ *
-+ * * - 40
-+ * - **Pending:** When valid bit is not set, indicates that a valid entry
-+ * is pending and the MMU should wait for the driver to map the entry.
-+ * This is used to support page demand mapping of memory.
-+ *
-+ * * - 39..5
-+ * - **Level 0 Page Table Base Address:** The way this value is
-+ * interpreted depends on the page size. Bits not specified in the
-+ * table below (e.g. bits 11..5 for page size 4KiB) should be
-+ * considered reserved.
-+ *
-+ * This table shows the bits used in an L1 page table entry to
-+ * represent the Physical Table Base Address for a given Page Size.
-+ * Since each L1 page table entry covers 2MiB of address space, the
-+ * maximum page size is 2MiB.
-+ *
-+ * .. flat-table::
-+ * :widths: 1 1 1 1
-+ * :header-rows: 1
-+ * :stub-columns: 1
-+ *
-+ * * - Page size
-+ * - L0 page table base address bits
-+ * - Number of L0 page table entries
-+ * - Size of L0 page table
-+ *
-+ * * - 4KiB
-+ * - 39..12
-+ * - 512
-+ * - 4KiB
-+ *
-+ * * - 16KiB
-+ * - 39..10
-+ * - 128
-+ * - 1KiB
-+ *
-+ * * - 64KiB
-+ * - 39..8
-+ * - 32
-+ * - 256B
-+ *
-+ * * - 256KiB
-+ * - 39..6
-+ * - 8
-+ * - 64B
-+ *
-+ * * - 1MiB
-+ * - 39..5 (4 = '0')
-+ * - 2
-+ * - 16B
-+ *
-+ * * - 2MiB
-+ * - 39..5 (4..3 = '00')
-+ * - 1
-+ * - 8B
-+ *
-+ * * - 4
-+ * - *(reserved)*
-+ *
-+ * * - 3..1
-+ * - **Page Size:** Sets the page size, from 4KiB to 2MiB.
-+ *
-+ * * - 0
-+ * - **Valid:** Indicates that the entry contains a valid L0 page table.
-+ * If the valid bit is not set, then an attempted use of the page would
-+ * result in a page fault.
-+ */
-+struct pvr_page_table_l1_entry_raw {
-+ /** @val: The raw value of this entry. */
-+ u64 val;
-+} __packed;
-+static_assert(sizeof(struct pvr_page_table_l1_entry_raw) * 8 ==
-+ ROGUE_MMUCTRL_ENTRY_SIZE_PT_L1_VALUE);
-+
-+static __always_inline bool
-+pvr_page_table_l1_entry_raw_is_valid(struct pvr_page_table_l1_entry_raw entry)
-+{
-+ return PVR_PAGE_TABLE_FIELD_GET(1, VALID, entry);
-+}
-+
-+static void
-+pvr_page_table_l1_entry_raw_set(struct pvr_page_table_l1_entry_raw *entry,
-+ dma_addr_t child_table_dma_addr)
-+{
-+ entry->val = PVR_PAGE_TABLE_FIELD_PREP(1, VALID, true) |
-+ PVR_PAGE_TABLE_FIELD_PREP(1, ENTRY_PENDING, false) |
-+ PVR_PAGE_TABLE_FIELD_PREP(1, PAGE_SIZE,
-+ ROGUE_MMUCTRL_PAGE_SIZE_4KB) |
-+ (child_table_dma_addr &
-+ ~ROGUE_MMUCTRL_PT_L0_BASE_4KB_RANGE_CLRMSK);
-+}
-+
-+static __always_inline void
-+pvr_page_table_l1_entry_raw_clear(struct pvr_page_table_l1_entry_raw *entry)
-+{
-+ entry->val = 0;
-+}
-+
-+/**
-+ * struct pvr_page_table_l0_entry_raw - A single entry in a level 0 page table.
-+ *
-+ * This type is a structure for type-checking purposes. At compile-time, its
-+ * size is checked against %ROGUE_MMUCTRL_ENTRY_SIZE_PT_VALUE.
-+ *
-+ * The value stored in this structure can be decoded using the following bitmap:
-+ *
-+ * .. flat-table::
-+ * :widths: 1 5
-+ * :stub-columns: 1
-+ *
-+ * * - 63
-+ * - *(reserved)*
-+ *
-+ * * - 62
-+ * - **PM/FW Protect:** Indicates a protected region which only the
-+ * Parameter Manager (PM) or firmware processor can write to.
-+ *
-+ * * - 61..40
-+ * - **VP Page (High):** Virtual-physical page used for Parameter Manager
-+ * (PM) memory. This field is only used if the additional level of PB
-+ * virtualization is enabled. The VP Page field is needed by the PM in
-+ * order to correctly reconstitute the free lists after render
-+ * completion. This (High) field holds bits 39..18 of the value; the
-+ * Low field holds bits 17..12. Bits 11..0 are always zero because the
-+ * value is always aligned to the 4KiB page size.
-+ *
-+ * * - 39..12
-+ * - **Physical Page Address:** he way this value is
-+ * interpreted depends on the page size. Bits not specified in the
-+ * table below (e.g. bits 20..12 for page size 2MiB) should be
-+ * considered reserved.
-+ *
-+ * This table shows the bits used in an L0 page table entry to represent
-+ * the Physical Page Address for a given page size (as defined in the
-+ * associated L1 page table entry).
-+ *
-+ * .. flat-table::
-+ * :widths: 1 1
-+ * :header-rows: 1
-+ * :stub-columns: 1
-+ *
-+ * * - Page size
-+ * - Physical address bits
-+ *
-+ * * - 4KiB
-+ * - 39..12
-+ *
-+ * * - 16KiB
-+ * - 39..14
-+ *
-+ * * - 64KiB
-+ * - 39..16
-+ *
-+ * * - 256KiB
-+ * - 39..18
-+ *
-+ * * - 1MiB
-+ * - 39..20
-+ *
-+ * * - 2MiB
-+ * - 39..21
-+ *
-+ * * - 11..6
-+ * - **VP Page (Low):** Continuation of VP Page (High).
-+ *
-+ * * - 5
-+ * - **Pending:** When valid bit is not set, indicates that a valid entry
-+ * is pending and the MMU should wait for the driver to map the entry.
-+ * This is used to support page demand mapping of memory.
-+ *
-+ * * - 4
-+ * - **PM Src:** Set on Parameter Manager (PM) allocated page table
-+ * entries when indicated by the PM. Note that this bit will only be set
-+ * by the PM, not by the device driver.
-+ *
-+ * * - 3
-+ * - **SLC Bypass Control:** Specifies requests to this page should bypass
-+ * the System Level Cache (SLC), if enabled in SLC configuration.
-+ *
-+ * * - 2
-+ * - **Cache Coherency:** Indicates that the page is coherent (i.e. it
-+ * does not require a cache flush between operations on the CPU and the
-+ * device).
-+ *
-+ * * - 1
-+ * - **Read Only:** If set, this bit indicates that the page is read only.
-+ * An attempted write to this page would result in a write-protection
-+ * fault.
-+ *
-+ * * - 0
-+ * - **Valid:** Indicates that the entry contains a valid page. If the
-+ * valid bit is not set, then an attempted use of the page would result
-+ * in a page fault.
-+ */
-+struct pvr_page_table_l0_entry_raw {
-+ /** @val: The raw value of this entry. */
-+ u64 val;
-+} __packed;
-+static_assert(sizeof(struct pvr_page_table_l0_entry_raw) * 8 ==
-+ ROGUE_MMUCTRL_ENTRY_SIZE_PT_L0_VALUE);
-+
-+/**
-+ * struct pvr_page_flags_raw - The configurable flags from a single entry in a
-+ * level 0 page table.
-+ *
-+ * The flags stored in this type are: PM/FW Protect; SLC Bypass Control; Cache
-+ * Coherency, and Read Only (bits 62, 3, 2 and 1 respectively).
-+ */
-+struct pvr_page_flags_raw {
-+ /**
-+ * @val: The raw value of these flags. Since these are a strict subset
-+ * of struct pvr_page_table_l0_entry_raw; use that type for our member
-+ * here.
-+ */
-+ struct pvr_page_table_l0_entry_raw val;
-+} __packed;
-+static_assert(sizeof(struct pvr_page_flags_raw) ==
-+ sizeof(struct pvr_page_table_l0_entry_raw));
-+
-+static __always_inline bool
-+pvr_page_table_l0_entry_raw_is_valid(struct pvr_page_table_l0_entry_raw entry)
-+{
-+ return PVR_PAGE_TABLE_FIELD_GET(0, VALID, entry);
-+}
-+
-+static void
-+pvr_page_table_l0_entry_raw_set(struct pvr_page_table_l0_entry_raw *entry,
-+ dma_addr_t dma_addr,
-+ struct pvr_page_flags_raw flags)
-+{
-+ entry->val = PVR_PAGE_TABLE_FIELD_PREP(0, VALID, true) |
-+ PVR_PAGE_TABLE_FIELD_PREP(0, ENTRY_PENDING, false) |
-+ (dma_addr & ~ROGUE_MMUCTRL_PAGE_4KB_RANGE_CLRMSK) |
-+ flags.val.val;
-+}
-+
-+static __always_inline void
-+pvr_page_table_l0_entry_raw_clear(struct pvr_page_table_l0_entry_raw *entry)
-+{
-+ entry->val = 0;
-+}
-+
-+static struct pvr_page_flags_raw
-+pvr_page_flags_raw_create(bool read_only, bool cache_coherent, bool slc_bypass,
-+ bool pm_fw_protect)
-+{
-+ struct pvr_page_flags_raw flags;
-+
-+ flags.val.val =
-+ PVR_PAGE_TABLE_FIELD_PREP(0, READ_ONLY, read_only) |
-+ PVR_PAGE_TABLE_FIELD_PREP(0, CC, cache_coherent) |
-+ PVR_PAGE_TABLE_FIELD_PREP(0, SLC_BYPASS_CTRL, slc_bypass) |
-+ PVR_PAGE_TABLE_FIELD_PREP(0, PM_META_PROTECT, pm_fw_protect);
-+
-+ return flags;
-+}
-+
-+/**
-+ * struct pvr_page_table_l2_raw - The raw data of an L2 page table.
-+ *
-+ * This type is a structure for type-checking purposes. At compile-time, its
-+ * size is checked against %PVR_VM_BACKING_PAGE_SIZE.
-+ */
-+struct pvr_page_table_l2_raw {
-+ /** @entries: The raw values of this table. */
-+ struct pvr_page_table_l2_entry_raw
-+ entries[ROGUE_MMUCTRL_ENTRIES_PT_L2_VALUE];
-+} __packed;
-+static_assert(sizeof(struct pvr_page_table_l2_raw) == PVR_VM_BACKING_PAGE_SIZE);
-+
-+/**
-+ * struct pvr_page_table_l1_raw - The raw data of an L1 page table.
-+ *
-+ * This type is a structure for type-checking purposes. At compile-time, its
-+ * size is checked against %PVR_VM_BACKING_PAGE_SIZE.
-+ */
-+struct pvr_page_table_l1_raw {
-+ /** @entries: The raw values of this table. */
-+ struct pvr_page_table_l1_entry_raw
-+ entries[ROGUE_MMUCTRL_ENTRIES_PT_L1_VALUE];
-+} __packed;
-+static_assert(sizeof(struct pvr_page_table_l1_raw) == PVR_VM_BACKING_PAGE_SIZE);
-+
-+/**
-+ * struct pvr_page_table_l0_raw - The raw data of an L0 page table.
-+ *
-+ * This type is a structure for type-checking purposes. At compile-time, its
-+ * size is checked against %PVR_VM_BACKING_PAGE_SIZE.
-+ *
-+ * .. caution::
-+ *
-+ * The size of L0 page tables is variable depending on the page size
-+ * specified in the associated L1 page table entry. For simplicity, this
-+ * type is fixed to contain the maximum possible number of entries.
-+ * **You should never read or write beyond the last supported entry.**
-+ */
-+struct pvr_page_table_l0_raw {
-+ /** @entries: The raw values of this table. */
-+ struct pvr_page_table_l0_entry_raw
-+ entries[ROGUE_MMUCTRL_ENTRIES_PT_L0_VALUE];
-+} __packed;
-+static_assert(sizeof(struct pvr_page_table_l0_raw) == PVR_VM_BACKING_PAGE_SIZE);
-+
-+/**
-+ * DOC: Mirror page tables
-+ *
-+ * These structures hold additional information required by the driver that
-+ * cannot be stored in :ref:`raw page tables<Raw page tables>` (since those are
-+ * defined by the hardware).
-+ *
-+ * In most cases, you should hold a handle to these types instead of the raw
-+ * types directly.
-+ */
-+
-+/*
-+ * We pre-declare these types because they cross-depend on pointers to each
-+ * other.
-+ */
-+struct pvr_page_table_l2;
-+struct pvr_page_table_l1;
-+struct pvr_page_table_l0;
-+
-+/**
-+ * struct pvr_page_table_l2 - A wrapped L2 page table.
-+ *
-+ * To access the raw part of this table, use pvr_page_table_l2_get_raw().
-+ * Alternatively to access a raw entry directly, use
-+ * pvr_page_table_l2_get_entry_raw().
-+ *
-+ * An L2 page table forms the root of the page table tree structure, so this
-+ * type has no &parent or &parent_idx members.
-+ */
-+struct pvr_page_table_l2 {
-+ /**
-+ * @entries: The children of this node in the page table tree
-+ * structure. These are also mirror tables. The indexing of this array
-+ * is identical to that of the raw equivalent
-+ * (&pvr_page_table_l1_raw.entries).
-+ */
-+ struct pvr_page_table_l1 *entries[ROGUE_MMUCTRL_ENTRIES_PT_L2_VALUE];
-+
-+ /**
-+ * @backing_page: A handle to the memory which holds the raw
-+ * equivalent of this table. **For internal use only.**
-+ */
-+ struct pvr_vm_backing_page backing_page;
-+
-+ /**
-+ * @entry_count: The current number of valid entries (that we know of)
-+ * in this table. This value is essentially a refcount - the table is
-+ * destroyed when this value is decremented to zero by
-+ * pvr_page_table_l2_remove().
-+ */
-+ u16 entry_count;
-+};
-+
-+/**
-+ * pvr_page_table_l2_init() - Initialize an L2 page table.
-+ * @table: Target L2 page table.
-+ * @pvr_dev: Target PowerVR device
-+ *
-+ * It is expected that @table be zeroed (e.g. from kzalloc()) before calling
-+ * this function.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_vm_backing_page_init().
-+ */
-+static __always_inline int
-+pvr_page_table_l2_init(struct pvr_page_table_l2 *table,
-+ struct pvr_device *pvr_dev)
-+{
-+ return pvr_vm_backing_page_init(&table->backing_page, pvr_dev);
-+}
-+
-+/**
-+ * pvr_page_table_l2_fini() - Teardown an L2 page table.
-+ * @table: Target L2 page table.
-+ *
-+ * It is an error to attempt to use @table after calling this function.
-+ */
-+static __always_inline void
-+pvr_page_table_l2_fini(struct pvr_page_table_l2 *table)
-+{
-+ pvr_vm_backing_page_fini(&table->backing_page);
-+}
-+
-+/**
-+ * pvr_page_table_l2_sync() - Flush an L2 page table from the CPU to the device.
-+ * @table: Target L2 page table.
-+ *
-+ * This is just a thin wrapper around pvr_vm_backing_page_sync(), so the
-+ * warning there applies here too: **Only call pvr_page_table_l2_sync() once
-+ * you're sure you have no more changes to make to** @table **in the immediate
-+ * future.**
-+ *
-+ * If child L1 page tables of @table also need to be flushed, this should be
-+ * done first using pvr_page_table_l1_sync() *before* calling this function.
-+ */
-+static __always_inline void
-+pvr_page_table_l2_sync(struct pvr_page_table_l2 *table)
-+{
-+ pvr_vm_backing_page_sync(&table->backing_page);
-+}
-+
-+/**
-+ * pvr_page_table_l2_get_raw() - Access the raw equivalent of a mirror L2 page
-+ * table.
-+ * @table: Target L2 page table.
-+ *
-+ * Essentially returns the CPU address of the raw equivalent of @table, cast to
-+ * a &struct pvr_page_table_l2_raw pointer.
-+ *
-+ * You probably want to call pvr_page_table_l2_get_entry_raw() instead.
-+ *
-+ * Return:
-+ * * The raw equivalent of @table.
-+ */
-+static __always_inline struct pvr_page_table_l2_raw *
-+pvr_page_table_l2_get_raw(struct pvr_page_table_l2 *table)
-+{
-+ return table->backing_page.host_ptr;
-+}
-+
-+/**
-+ * pvr_page_table_l2_get_entry_raw() - Access an entry from the raw equivalent
-+ * of a mirror L2 page table.
-+ * @table: Target L2 page table.
-+ * @idx: Index of the entry to access.
-+ *
-+ * Technically this function returns a pointer to a slot in a raw L2 page
-+ * table, since the returned "entry" is not guaranteed to be valid. The caller
-+ * must verify the validity of the entry at the returned address before reading
-+ * or overwriting it.
-+ *
-+ * Return:
-+ * * A pointer to the requested raw L2 page table entry.
-+ */
-+static __always_inline struct pvr_page_table_l2_entry_raw *
-+pvr_page_table_l2_get_entry_raw(struct pvr_page_table_l2 *table, u16 idx)
-+{
-+ return &pvr_page_table_l2_get_raw(table)->entries[idx];
-+}
-+
-+/**
-+ * pvr_page_table_l2_entry_is_valid() - Check if an L2 page table entry is
-+ * marked as valid.
-+ * @table: Target L2 page table.
-+ * @idx: Index of the entry to check.
-+ *
-+ * Return:
-+ * * %true if there is a valid entry at @idx in @table, or
-+ * * %false otherwise.
-+ */
-+static __always_inline bool
-+pvr_page_table_l2_entry_is_valid(struct pvr_page_table_l2 *table, u16 idx)
-+{
-+ struct pvr_page_table_l2_entry_raw entry_raw =
-+ *pvr_page_table_l2_get_entry_raw(table, idx);
-+
-+ return pvr_page_table_l2_entry_raw_is_valid(entry_raw);
-+}
-+
-+/**
-+ * struct pvr_page_table_l1 - A wrapped L1 page table.
-+ *
-+ * To access the raw part of this table, use pvr_page_table_l1_get_raw().
-+ * Alternatively to access a raw entry directly, use
-+ * pvr_page_table_l1_get_entry_raw().
-+ */
-+struct pvr_page_table_l1 {
-+ /**
-+ * @entries: The children of this node in the page table tree
-+ * structure. These are also mirror tables. The indexing of this array
-+ * is identical to that of the raw equivalent
-+ * (&pvr_page_table_l0_raw.entries).
-+ */
-+ struct pvr_page_table_l0 *entries[ROGUE_MMUCTRL_ENTRIES_PT_L1_VALUE];
-+
-+ /**
-+ * @backing_page: A handle to the memory which holds the raw
-+ * equivalent of this table. **For internal use only.**
-+ */
-+ struct pvr_vm_backing_page backing_page;
-+
-+ /**
-+ * @parent: The parent of this node in the page table tree structure.
-+ * This is also a mirror table.
-+ */
-+ struct pvr_page_table_l2 *parent;
-+
-+ /**
-+ * @parent_idx: The index of the entry in the parent table (see
-+ * @parent) which corresponds to this table.
-+ */
-+ u16 parent_idx;
-+
-+ /**
-+ * @entry_count: The current number of valid entries (that we know of)
-+ * in this table. This value is essentially a refcount - the table is
-+ * destroyed when this value is decremented to zero by
-+ * pvr_page_table_l1_remove().
-+ */
-+ u16 entry_count;
-+};
-+
-+/**
-+ * pvr_page_table_l1_init() - Initialize an L1 page table.
-+ * @table: Target L1 page table.
-+ * @pvr_dev: Target PowerVR device
-+ *
-+ * When this function returns successfully, @table is still not considered
-+ * valid. It must be inserted into the page table tree structure with
-+ * pvr_page_table_l2_insert() before it is ready for use.
-+ *
-+ * It is expected that @table be zeroed (e.g. from kzalloc()) before calling
-+ * this function.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_vm_backing_page_init().
-+ */
-+static __always_inline int
-+pvr_page_table_l1_init(struct pvr_page_table_l1 *table,
-+ struct pvr_device *pvr_dev)
-+{
-+ table->parent_idx = PVR_IDX_INVALID;
-+
-+ return pvr_vm_backing_page_init(&table->backing_page, pvr_dev);
-+}
-+
-+/**
-+ * pvr_page_table_l1_fini() - Teardown an L1 page table.
-+ * @table: Target L1 page table.
-+ *
-+ * It is an error to attempt to use @table after calling this function, even
-+ * indirectly. This includes calling pvr_page_table_l2_remove(), which must
-+ * be called *before* pvr_page_table_l1_fini().
-+ */
-+static __always_inline void
-+pvr_page_table_l1_fini(struct pvr_page_table_l1 *table)
-+{
-+ pvr_vm_backing_page_fini(&table->backing_page);
-+}
-+
-+/**
-+ * pvr_page_table_l1_sync() - Flush an L1 page table from the CPU to the device.
-+ * @table: Target L1 page table.
-+ *
-+ * This is just a thin wrapper around pvr_vm_backing_page_sync(), so the
-+ * warning there applies here too: **Only call pvr_page_table_l1_sync() once
-+ * you're sure you have no more changes to make to** @table **in the immediate
-+ * future.**
-+ *
-+ * If child L0 page tables of @table also need to be flushed, this should be
-+ * done first using pvr_page_table_l0_sync() *before* calling this function.
-+ */
-+static __always_inline void
-+pvr_page_table_l1_sync(struct pvr_page_table_l1 *table)
-+{
-+ pvr_vm_backing_page_sync(&table->backing_page);
-+}
-+
-+/**
-+ * pvr_page_table_l1_get_raw() - Access the raw equivalent of a mirror L1 page
-+ * table.
-+ * @table: Target L1 page table.
-+ *
-+ * Essentially returns the CPU address of the raw equivalent of @table, cast to
-+ * a &struct pvr_page_table_l1_raw pointer.
-+ *
-+ * You probably want to call pvr_page_table_l1_get_entry_raw() instead.
-+ *
-+ * Return:
-+ * * The raw equivalent of @table.
-+ */
-+static __always_inline struct pvr_page_table_l1_raw *
-+pvr_page_table_l1_get_raw(struct pvr_page_table_l1 *table)
-+{
-+ return table->backing_page.host_ptr;
-+}
-+
-+/**
-+ * pvr_page_table_l1_get_entry_raw() - Access an entry from the raw equivalent
-+ * of a mirror L1 page table.
-+ * @table: Target L1 page table.
-+ * @idx: Index of the entry to access.
-+ *
-+ * Technically this function returns a pointer to a slot in a raw L1 page
-+ * table, since the returned "entry" is not guaranteed to be valid. The caller
-+ * must verify the validity of the entry at the returned address before reading
-+ * or overwriting it.
-+ *
-+ * Return:
-+ * * A pointer to the requested raw L1 page table entry.
-+ */
-+static __always_inline struct pvr_page_table_l1_entry_raw *
-+pvr_page_table_l1_get_entry_raw(struct pvr_page_table_l1 *table, u16 idx)
-+{
-+ return &pvr_page_table_l1_get_raw(table)->entries[idx];
-+}
-+
-+/**
-+ * pvr_page_table_l1_entry_is_valid() - Check if an L1 page table entry is
-+ * marked as valid.
-+ * @table: Target L1 page table.
-+ * @idx: Index of the entry to check.
-+ *
-+ * Return:
-+ * * %true if there is a valid entry at @idx in @table, or
-+ * * %false otherwise.
-+ */
-+static __always_inline bool
-+pvr_page_table_l1_entry_is_valid(struct pvr_page_table_l1 *table, u16 idx)
-+{
-+ struct pvr_page_table_l1_entry_raw entry_raw =
-+ *pvr_page_table_l1_get_entry_raw(table, idx);
-+
-+ return pvr_page_table_l1_entry_raw_is_valid(entry_raw);
-+}
-+
-+/**
-+ * struct pvr_page_table_l0 - A wrapped L0 page table.
-+ *
-+ * To access the raw part of this table, use pvr_page_table_l0_get_raw().
-+ * Alternatively to access a raw entry directly, use
-+ * pvr_page_table_l0_get_entry_raw().
-+ *
-+ * There is no mirror representation of an individual page, so this type has no
-+ * &entries member.
-+ */
-+struct pvr_page_table_l0 {
-+ /**
-+ * @backing_page: A handle to the memory which holds the raw
-+ * equivalent of this table. **For internal use only.**
-+ */
-+ struct pvr_vm_backing_page backing_page;
-+
-+ /**
-+ * @parent: The parent of this node in the page table tree structure.
-+ * This is also a mirror table.
-+ */
-+ struct pvr_page_table_l1 *parent;
-+
-+ /**
-+ * @parent_idx: The index of the entry in the parent table (see
-+ * @parent) which corresponds to this table.
-+ */
-+ u16 parent_idx;
-+
-+ /**
-+ * @entry_count: The current number of valid entries (that we know of)
-+ * in this table. This value is essentially a refcount - the table is
-+ * destroyed when this value is decremented to zero by
-+ * pvr_page_table_l0_remove().
-+ */
-+ u16 entry_count;
-+};
-+
-+/**
-+ * pvr_page_table_l0_init() - Initialize an L0 page table.
-+ * @table: Target L0 page table.
-+ * @pvr_dev: Target PowerVR device
-+ *
-+ * When this function returns successfully, @table is still not considered
-+ * valid. It must be inserted into the page table tree structure with
-+ * pvr_page_table_l1_insert() before it is ready for use.
-+ *
-+ * It is expected that @table be zeroed (e.g. from kzalloc()) before calling
-+ * this function.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_vm_backing_page_init().
-+ */
-+static __always_inline int
-+pvr_page_table_l0_init(struct pvr_page_table_l0 *table,
-+ struct pvr_device *pvr_dev)
-+{
-+ table->parent_idx = PVR_IDX_INVALID;
-+
-+ return pvr_vm_backing_page_init(&table->backing_page, pvr_dev);
-+}
-+
-+/**
-+ * pvr_page_table_l0_fini() - Teardown an L0 page table.
-+ * @table: Target L0 page table.
-+ *
-+ * It is an error to attempt to use @table after calling this function, even
-+ * indirectly. This includes calling pvr_page_table_l1_remove(), which must
-+ * be called *before* pvr_page_table_l0_fini().
-+ */
-+static __always_inline void
-+pvr_page_table_l0_fini(struct pvr_page_table_l0 *table)
-+{
-+ pvr_vm_backing_page_fini(&table->backing_page);
-+}
-+
-+/**
-+ * pvr_page_table_l0_sync() - Flush an L0 page table from the CPU to the device.
-+ * @table: Target L0 page table.
-+ *
-+ * This is just a thin wrapper around pvr_vm_backing_page_sync(), so the
-+ * warning there applies here too: **Only call pvr_page_table_l0_sync() once
-+ * you're sure you have no more changes to make to** @table **in the immediate
-+ * future.**
-+ *
-+ * If child pages of @table also need to be flushed, this should be done first
-+ * using a DMA sync function (e.g. dma_sync_sg_for_device()) *before* calling
-+ * this function.
-+ */
-+static __always_inline void
-+pvr_page_table_l0_sync(struct pvr_page_table_l0 *table)
-+{
-+ pvr_vm_backing_page_sync(&table->backing_page);
-+}
-+
-+/**
-+ * pvr_page_table_l0_get_raw() - Access the raw equivalent of a mirror L0 page
-+ * table.
-+ * @table: Target L0 page table.
-+ *
-+ * Essentially returns the CPU address of the raw equivalent of @table, cast to
-+ * a &struct pvr_page_table_l0_raw pointer.
-+ *
-+ * You probably want to call pvr_page_table_l0_get_entry_raw() instead.
-+ *
-+ * Return:
-+ * * The raw equivalent of @table.
-+ */
-+static __always_inline struct pvr_page_table_l0_raw *
-+pvr_page_table_l0_get_raw(struct pvr_page_table_l0 *table)
-+{
-+ return table->backing_page.host_ptr;
-+}
-+
-+/**
-+ * pvr_page_table_l0_get_entry_raw() - Access an entry from the raw equivalent
-+ * of a mirror L0 page table.
-+ * @table: Target L0 page table.
-+ * @idx: Index of the entry to access.
-+ *
-+ * Technically this function returns a pointer to a slot in a raw L0 page
-+ * table, since the returned "entry" is not guaranteed to be valid. The caller
-+ * must verify the validity of the entry at the returned address before reading
-+ * or overwriting it.
-+ *
-+ * Return:
-+ * * A pointer to the requested raw L0 page table entry.
-+ */
-+static __always_inline struct pvr_page_table_l0_entry_raw *
-+pvr_page_table_l0_get_entry_raw(struct pvr_page_table_l0 *table, u16 idx)
-+{
-+ return &pvr_page_table_l0_get_raw(table)->entries[idx];
-+}
-+
-+/**
-+ * pvr_page_table_l0_entry_is_valid() - Check if an L0 page table entry is
-+ * marked as valid.
-+ * @table: Target L0 page table.
-+ * @idx: Index of the entry to check.
-+ *
-+ * Return:
-+ * * %true if there is a valid entry at @idx in @table, or
-+ * * %false otherwise.
-+ */
-+static __always_inline bool
-+pvr_page_table_l0_entry_is_valid(struct pvr_page_table_l0 *table, u16 idx)
-+{
-+ struct pvr_page_table_l0_entry_raw entry_raw =
-+ *pvr_page_table_l0_get_entry_raw(table, idx);
-+
-+ return pvr_page_table_l0_entry_raw_is_valid(entry_raw);
-+}
-+
-+/**
-+ * pvr_page_table_l2_insert() - TODO
-+ * @table: Target L2 page table.
-+ * @idx: Index of the entry to write.
-+ * @child_table: Target L1 page table to be referenced by the new entry.
-+ *
-+ * This function is unchecked. Do not call it unless you're absolutely sure
-+ * there is not already a valid entry at @idx in @table.
-+ */
-+static void
-+pvr_page_table_l2_insert(struct pvr_page_table_l2 *table, u16 idx,
-+ struct pvr_page_table_l1 *child_table)
-+{
-+ struct pvr_page_table_l2_entry_raw *entry_raw =
-+ pvr_page_table_l2_get_entry_raw(table, idx);
-+
-+ pvr_page_table_l2_entry_raw_set(entry_raw,
-+ child_table->backing_page.dma_addr);
-+
-+ child_table->parent = table;
-+ child_table->parent_idx = idx;
-+
-+ table->entries[idx] = child_table;
-+ ++table->entry_count;
-+}
-+
-+/**
-+ * pvr_page_table_l2_remove() - TODO
-+ * @table: Target L2 page table.
-+ * @idx: Index of the entry to remove.
-+ *
-+ * This function is unchecked. Do not call it unless you're absolutely sure
-+ * there is a valid entry at @idx in @table.
-+ */
-+static void
-+pvr_page_table_l2_remove(struct pvr_page_table_l2 *table, u16 idx)
-+{
-+ struct pvr_page_table_l1 *child_table = table->entries[idx];
-+ struct pvr_page_table_l2_entry_raw *entry_raw =
-+ pvr_page_table_l2_get_entry_raw(table, idx);
-+
-+ pvr_page_table_l2_entry_raw_clear(entry_raw);
-+
-+ child_table->parent = NULL;
-+ child_table->parent_idx = PVR_IDX_INVALID;
-+
-+ table->entries[idx] = NULL;
-+ --table->entry_count;
-+}
-+
-+/**
-+ * pvr_page_table_l1_insert() - TODO
-+ * @table: Target L1 page table.
-+ * @idx: Index of the entry to write.
-+ * @child_table: Target L0 page table to be referenced by the new entry.
-+ *
-+ * This function is unchecked. Do not call it unless you're absolutely sure
-+ * there is not already a valid entry at @idx in @table.
-+ */
-+static void
-+pvr_page_table_l1_insert(struct pvr_page_table_l1 *table, u16 idx,
-+ struct pvr_page_table_l0 *child_table)
-+{
-+ struct pvr_page_table_l1_entry_raw *entry_raw =
-+ pvr_page_table_l1_get_entry_raw(table, idx);
-+
-+ pvr_page_table_l1_entry_raw_set(entry_raw,
-+ child_table->backing_page.dma_addr);
-+
-+ child_table->parent = table;
-+ child_table->parent_idx = idx;
-+
-+ table->entries[idx] = child_table;
-+ ++table->entry_count;
-+}
-+
-+/* Forward declaration from below. */
-+static void __pvr_page_table_l1_destroy(struct pvr_page_table_l1 *table);
-+
-+/**
-+ * pvr_page_table_l1_remove() - TODO
-+ * @table: Target L1 page table.
-+ * @idx: Index of the entry to remove.
-+ *
-+ * This function is unchecked. Do not call it unless you're absolutely sure
-+ * there is a valid entry at @idx in @table.
-+ */
-+static void
-+pvr_page_table_l1_remove(struct pvr_page_table_l1 *table, u16 idx)
-+{
-+ struct pvr_page_table_l0 *child_table = table->entries[idx];
-+ struct pvr_page_table_l1_entry_raw *entry_raw =
-+ pvr_page_table_l1_get_entry_raw(table, idx);
-+
-+ pvr_page_table_l1_entry_raw_clear(entry_raw);
-+
-+ child_table->parent = NULL;
-+ child_table->parent_idx = PVR_IDX_INVALID;
-+
-+ table->entries[idx] = NULL;
-+ if (--table->entry_count == 0)
-+ __pvr_page_table_l1_destroy(table);
-+}
-+
-+/**
-+ * pvr_page_table_l0_insert() - TODO
-+ * @table: Target L0 page table.
-+ * @idx: Index of the entry to write.
-+ * @dma_addr: Target DMA address to be referenced by the new entry.
-+ * @flags: Page options to be stored in the new entry.
-+ *
-+ * This function is unchecked. Do not call it unless you're absolutely sure
-+ * there is not already a valid entry at @idx in @table.
-+ */
-+static void
-+pvr_page_table_l0_insert(struct pvr_page_table_l0 *table, u16 idx,
-+ dma_addr_t dma_addr, struct pvr_page_flags_raw flags)
-+{
-+ struct pvr_page_table_l0_entry_raw *entry_raw =
-+ pvr_page_table_l0_get_entry_raw(table, idx);
-+
-+ pvr_page_table_l0_entry_raw_set(entry_raw, dma_addr, flags);
-+
-+ /*
-+ * There is no entry to set here - we don't keep a mirror of
-+ * individual pages.
-+ */
-+
-+ ++table->entry_count;
-+}
-+
-+/* Forward declaration from below. */
-+static void __pvr_page_table_l0_destroy(struct pvr_page_table_l0 *table);
-+
-+/**
-+ * pvr_page_table_l0_remove() - TODO
-+ * @table: Target L0 page table.
-+ * @idx: Index of the entry to remove.
-+ *
-+ * This function is unchecked. Do not call it unless you're absolutely sure
-+ * there is a valid entry at @idx in @table.
-+ */
-+static void
-+pvr_page_table_l0_remove(struct pvr_page_table_l0 *table, u16 idx)
-+{
-+ struct pvr_page_table_l0_entry_raw *entry_raw =
-+ pvr_page_table_l0_get_entry_raw(table, idx);
-+
-+ pvr_page_table_l0_entry_raw_clear(entry_raw);
-+
-+ /*
-+ * There is no entry to clear here - we don't keep a mirror of
-+ * individual pages.
-+ */
-+
-+ if (--table->entry_count == 0)
-+ __pvr_page_table_l0_destroy(table);
-+}
-+
-+/**
-+ * DOC: Page table index utilities
-+ *
-+ * These utilities are not tied to the raw or mirror page tables since they
-+ * operate only on virtual device addresses which are identical between the two
-+ * structures.
-+ */
-+/**
-+ * DOC: Page table index utilities (constants)
-+ *
-+ * .. c:macro:: PVR_PAGE_TABLE_ADDR_SPACE_SIZE
-+ *
-+ * Size of device-virtual address space which can be represented in the page
-+ * table structure.
-+ *
-+ * This value is checked at runtime against
-+ * &pvr_device_features.virtual_address_space_bits by
-+ * pvr_vm_create_context(), which will return an error if the feature value
-+ * does not match this constant.
-+ *
-+ * .. admonition:: Future work
-+ *
-+ * It should be possible to support other values of
-+ * &pvr_device_features.virtual_address_space_bits, but so far no
-+ * hardware has been created which advertises an unsupported value.
-+ *
-+ * .. c:macro:: PVR_PAGE_TABLE_ADDR_BITS
-+ *
-+ * Number of bits needed to represent any value less than
-+ * %PVR_PAGE_TABLE_ADDR_SPACE_SIZE exactly.
-+ *
-+ * .. c:macro:: PVR_PAGE_TABLE_ADDR_MASK
-+ *
-+ * Bitmask of virtual devices addresses which are valid in the page table
-+ * structure.
-+ *
-+ * This value is derived from %PVR_PAGE_TABLE_ADDR_SPACE_SIZE, so the same
-+ * notes on that constant apply here.
-+ */
-+
-+/**
-+ * PVR_PAGE_TABLE_ADDR_SPACE_SIZE - Size of device-virtual address space which
-+ * can be represented in the page table structure.
-+ *
-+ * *This doc comment is not rendered - see DOC: Page table index utilities
-+ * (constants).*
-+ */
-+#define PVR_PAGE_TABLE_ADDR_SPACE_SIZE SZ_1T
-+
-+/**
-+ * PVR_PAGE_TABLE_ADDR_BITS - Number of bits needed to represent any value less
-+ * than %PVR_PAGE_TABLE_ADDR_SPACE_SIZE exactly.
-+ *
-+ * *This doc comment is not rendered - see DOC: Page table index utilities
-+ * (constants).*
-+ */
-+#define PVR_PAGE_TABLE_ADDR_BITS __ffs(PVR_PAGE_TABLE_ADDR_SPACE_SIZE)
-+
-+/**
-+ * PVR_PAGE_TABLE_ADDR_MASK - Bitmask of virtual devices addresses which are
-+ * valid in the page table structure.
-+ *
-+ * *This doc comment is not rendered - see DOC: Page table index utilities
-+ * (constants).*
-+ */
-+#define PVR_PAGE_TABLE_ADDR_MASK (PVR_PAGE_TABLE_ADDR_SPACE_SIZE - 1)
-+
-+/**
-+ * pvr_page_table_l2_idx() - Calculate the L2 page table index for a virtual
-+ * device address.
-+ * @device_addr: Target virtual device address.
-+ *
-+ * This function does not perform any bounds checking - it is the caller's
-+ * responsibility to ensure that @device_addr is valid before interpreting
-+ * the result.
-+ *
-+ * Return:
-+ * * The index into an L2 page table corresponding to @device_addr.
-+ */
-+static __always_inline u16
-+pvr_page_table_l2_idx(u64 device_addr)
-+{
-+ return (device_addr & ~ROGUE_MMUCTRL_VADDR_PT_L2_INDEX_CLRMSK) >>
-+ ROGUE_MMUCTRL_VADDR_PT_L2_INDEX_SHIFT;
-+}
-+
-+/**
-+ * pvr_page_table_l1_idx() - Calculate the L1 page table index for a virtual
-+ * device address.
-+ * @device_addr: Target virtual device address.
-+ *
-+ * This function does not perform any bounds checking - it is the caller's
-+ * responsibility to ensure that @device_addr is valid before interpreting
-+ * the result.
-+ *
-+ * Return:
-+ * * The index into an L1 page table corresponding to @device_addr.
-+ */
-+static __always_inline u16
-+pvr_page_table_l1_idx(u64 device_addr)
-+{
-+ return (device_addr & ~ROGUE_MMUCTRL_VADDR_PT_L1_INDEX_CLRMSK) >>
-+ ROGUE_MMUCTRL_VADDR_PT_L1_INDEX_SHIFT;
-+}
-+
-+/**
-+ * pvr_page_table_l0_idx() - Calculate the L0 page table index for a virtual
-+ * device address.
-+ * @device_addr: Target virtual device address.
-+ *
-+ * This function does not perform any bounds checking - it is the caller's
-+ * responsibility to ensure that @device_addr is valid before interpreting
-+ * the result.
-+ *
-+ * Return:
-+ * * The index into an L0 page table corresponding to @device_addr.
-+ */
-+static __always_inline u16
-+pvr_page_table_l0_idx(u64 device_addr)
-+{
-+ return (device_addr & ~ROGUE_MMUCTRL_VADDR_PT_L0_INDEX_CLRMSK) >>
-+ ROGUE_MMUCTRL_VADDR_PT_L0_INDEX_SHIFT;
-+}
-+
-+/**
-+ * DOC: High-level page table operations
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * pvr_page_table_l1_create_unchecked() - Create an L1 page table and insert
-+ * it into an L2 page table.
-+ * @pvr_dev: Target PowerVR device.
-+ * @parent_table: L2 page table into which the created L1 page table will be
-+ * inserted.
-+ * @idx: Index into @parent_table at which to insert the created L1 page table.
-+ *
-+ * This function is unchecked. By using it, the caller is asserting that slot
-+ * @idx in @parent_table does not contain a valid entry.
-+ *
-+ * Return:
-+ * * The newly-minted L1 page table on success,
-+ * * -%ENOMEM if allocation of a &struct pvr_page_table_l1 fails, or
-+ * * Any error returned by pvr_page_table_l1_init().
-+ */
-+static struct pvr_page_table_l1 *
-+pvr_page_table_l1_create_unchecked(struct pvr_device *pvr_dev,
-+ struct pvr_page_table_l2 *parent_table,
-+ u16 idx)
-+{
-+ struct pvr_page_table_l1 *table;
-+ int err;
-+
-+ table = kzalloc(sizeof(*table), GFP_KERNEL);
-+ if (!table) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ err = pvr_page_table_l1_init(table, pvr_dev);
-+ if (err)
-+ goto err_free_table;
-+
-+ /* Store the new L1 page table in the parent L2 page table. */
-+ pvr_page_table_l2_insert(parent_table, idx, table);
-+
-+ return table;
-+
-+err_free_table:
-+ kfree(table);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * __pvr_page_table_l1_destroy() - Destroy an L1 page table after removing it
-+ * from its parent L2 page table.
-+ * @table: Target L1 page table.
-+ *
-+ * Although this function is defined in the "High-level page table operations"
-+ * section for symmetry, it should never be called directly (hence the ``__``
-+ * prefix). Instead, it's called automatically when pvr_page_table_l1_remove()
-+ * causes @table to become empty.
-+ */
-+static void
-+__pvr_page_table_l1_destroy(struct pvr_page_table_l1 *table)
-+{
-+ /* Clear the parent L2 page table entry. */
-+ if (table->parent_idx != PVR_IDX_INVALID)
-+ pvr_page_table_l2_remove(table->parent, table->parent_idx);
-+
-+ pvr_page_table_l1_fini(table);
-+ kfree(table);
-+}
-+
-+/**
-+ * pvr_page_table_l1_get_or_create() - Retrieves (optionally creating if
-+ * necessary) an L1 page table from the
-+ * specified L2 page table entry.
-+ * @pvr_dev: [IN] Target PowerVR device.
-+ * @parent_table: [IN] L2 page table which contains the target L1 page table.
-+ * @idx: [IN] Index into @parent_table of the entry to fetch.
-+ * @should_create: [IN] Specifies whether new page tables should be created
-+ * when empty page table entries are encountered during traversal.
-+ * @did_create: [OUT] Optional pointer to a flag which is set when
-+ * @should_create is %true and new page table entries are created. In any
-+ * other case, the value will not be modified.
-+ *
-+ * Return:
-+ * * The selected L1 page table on success,
-+ * * -%ENXIO if @should_create is %false and an L1 page table would have been
-+ * created, or
-+ * * Any error returned by pvr_page_table_l1_create_unchecked() if
-+ * @should_create is %true and a new L1 page table needs to be created.
-+ */
-+static struct pvr_page_table_l1 *
-+pvr_page_table_l1_get_or_create(struct pvr_device *pvr_dev,
-+ struct pvr_page_table_l2 *parent_table, u16 idx,
-+ bool should_create, bool *did_create)
-+{
-+ struct pvr_page_table_l1 *table;
-+
-+ if (pvr_page_table_l2_entry_is_valid(parent_table, idx))
-+ return parent_table->entries[idx];
-+
-+ if (!should_create)
-+ return ERR_PTR(-ENXIO);
-+
-+ /*
-+ * Use the unchecked version of pvr_page_table_l1_create() because we
-+ * just verified the entry does not exist yet.
-+ */
-+ table = pvr_page_table_l1_create_unchecked(pvr_dev, parent_table, idx);
-+ if (!IS_ERR(table) && did_create)
-+ *did_create = true;
-+
-+ return table;
-+}
-+
-+/**
-+ * pvr_page_table_l0_create_unchecked() - Create an L0 page table and insert
-+ * it into an L1 page table.
-+ * @pvr_dev: Target PowerVR device.
-+ * @parent_table: L1 page table into which the created L0 page table will be
-+ * inserted.
-+ * @idx: Index into @parent_table at which to insert the created L0 page table.
-+ *
-+ * This function is unchecked. By using it, the caller is asserting that slot
-+ * @idx in @parent_table does not contain a valid entry.
-+ *
-+ * Return:
-+ * * The newly-minted L0 page table on success,
-+ * * -%ENOMEM if allocation of a &struct pvr_page_table_l0 fails, or
-+ * * Any error returned by pvr_page_table_l0_init().
-+ */
-+static struct pvr_page_table_l0 *
-+pvr_page_table_l0_create_unchecked(struct pvr_device *pvr_dev,
-+ struct pvr_page_table_l1 *parent_table,
-+ u16 idx)
-+{
-+ struct pvr_page_table_l0 *table;
-+ int err;
-+
-+ table = kzalloc(sizeof(*table), GFP_KERNEL);
-+ if (!table) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ err = pvr_page_table_l0_init(table, pvr_dev);
-+ if (err)
-+ goto err_free_table;
-+
-+ /* Store the new L0 page table in the parent L1 page table. */
-+ pvr_page_table_l1_insert(parent_table, idx, table);
-+
-+ return table;
-+
-+err_free_table:
-+ kfree(table);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * __pvr_page_table_l0_destroy() - Destroy an L0 page table after removing it
-+ * from its parent L1 page table.
-+ * @table: Target L0 page table.
-+ *
-+ * Although this function is defined in the "High-level page table operations"
-+ * section for symmetry, it should never be called directly (hence the ``__``
-+ * prefix). Instead, it's called automatically when pvr_page_table_l0_remove()
-+ * causes @table to become empty.
-+ */
-+static void
-+__pvr_page_table_l0_destroy(struct pvr_page_table_l0 *table)
-+{
-+ /* Clear the parent L1 page table entry. */
-+ if (table->parent_idx != PVR_IDX_INVALID)
-+ pvr_page_table_l1_remove(table->parent, table->parent_idx);
-+
-+ pvr_page_table_l0_fini(table);
-+ kfree(table);
-+}
-+
-+/**
-+ * pvr_page_table_l0_get_or_create() - Retrieves (optionally creating if
-+ * necessary) an L0 page table from the
-+ * specified L1 page table entry.
-+ * @pvr_dev: [IN] Target PowerVR device.
-+ * @parent_table: [IN] L1 page table which contains the target L0 page table.
-+ * @idx: [IN] Index into @parent_table of the entry to fetch.
-+ * @should_create: [IN] Specifies whether new page tables should be created
-+ * when empty page table entries are encountered during traversal.
-+ * @did_create: [OUT] Optional pointer to a flag which is set when
-+ * @should_create is %true and new page table entries are created. In any
-+ * other case, the value will not be modified.
-+ *
-+ * Return:
-+ * * The selected L0 page table on success,
-+ * * -%ENXIO if @should_create is %false and an L0 page table would have been
-+ * created, or
-+ * * Any error returned by pvr_page_table_l1_create_unchecked() if
-+ * @should_create is %true and a new L0 page table needs to be created.
-+ */
-+static struct pvr_page_table_l0 *
-+pvr_page_table_l0_get_or_create(struct pvr_device *pvr_dev,
-+ struct pvr_page_table_l1 *parent_table, u16 idx,
-+ bool should_create, bool *did_create)
-+{
-+ struct pvr_page_table_l0 *table;
-+
-+ if (pvr_page_table_l1_entry_is_valid(parent_table, idx))
-+ return parent_table->entries[idx];
-+
-+ if (!should_create)
-+ return ERR_PTR(-ENXIO);
-+
-+ /*
-+ * Use the unchecked version of pvr_page_table_l0_create() because we
-+ * just verified the entry does not exist yet.
-+ */
-+ table = pvr_page_table_l0_create_unchecked(pvr_dev, parent_table, idx);
-+ if (!IS_ERR(table) && did_create)
-+ *did_create = true;
-+
-+ return table;
-+}
-+
-+/**
-+ * DOC: Page table pointer
-+ *
-+ * Traversing the page table tree structure is not a straightforward
-+ * operation since there are multiple layers, each with different properties.
-+ * To contain and attempt to reduce this complexity, it's mostly encompassed
-+ * in a "heavy pointer" type (&struct pvr_page_table_ptr) and its associated
-+ * functions.
-+ *
-+ * Usage
-+ * -----
-+ * To start using a &struct pvr_page_table_ptr instance, you must first
-+ * initialize it to the starting address of your traversal using
-+ * pvr_page_table_ptr_init().
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * struct pvr_page_table_ptr - TODO
-+ */
-+struct pvr_page_table_ptr {
-+ /**
-+ * @pvr_dev: The PowerVR device associated with the VM context the
-+ * pointer is traversing.
-+ */
-+ struct pvr_device *pvr_dev;
-+
-+ /**
-+ * @l2_table: A cached handle to the L2 page table the pointer is
-+ * currently traversing.
-+ */
-+ struct pvr_page_table_l2 *l2_table;
-+
-+ /**
-+ * @l1_table: A cached handle to the L1 page table the pointer is
-+ * currently traversing.
-+ */
-+ struct pvr_page_table_l1 *l1_table;
-+
-+ /**
-+ * @l0_table: A cached handle to the L0 page table the pointer is
-+ * currently traversing.
-+ */
-+ struct pvr_page_table_l0 *l0_table;
-+
-+ /**
-+ * @l2_idx: Index into the L2 page table the pointer is currently
-+ * referencing.
-+ */
-+ u16 l2_idx;
-+
-+ /**
-+ * @l1_idx: Index into the L1 page table the pointer is currently
-+ * referencing.
-+ */
-+ u16 l1_idx;
-+
-+ /**
-+ * @l0_idx: Index into the L0 page table the pointer is currently
-+ * referencing.
-+ */
-+ u16 l0_idx;
-+
-+ /**
-+ * @sync_level_required: The maximum level of the page table tree
-+ * structure which has (possibly) been modified since it was last
-+ * flushed to the device.
-+ *
-+ * This field should only be set with pvr_page_table_ptr_require_sync()
-+ * or indirectly by pvr_page_table_ptr_sync_partial().
-+ */
-+ s8 sync_level_required;
-+};
-+
-+static __always_inline void
-+pvr_page_table_ptr_require_sync(struct pvr_page_table_ptr *ptr, s8 level)
-+{
-+ if (ptr->sync_level_required < level)
-+ ptr->sync_level_required = level;
-+}
-+
-+/**
-+ * pvr_page_table_ptr_sync_manual() - TODO
-+ * @ptr: Target page table pointer.
-+ * @level: TODO
-+ *
-+ * Do not call this function directly. Instead use
-+ * pvr_page_table_ptr_sync_partial() which is checked against the current
-+ * value of &ptr->sync_level_required.
-+ */
-+static void
-+pvr_page_table_ptr_sync_manual(struct pvr_page_table_ptr *ptr, s8 level)
-+{
-+ /*
-+ * We sync the pages table levels in ascending order (starting from
-+ * the leaf node) to ensure consistency.
-+ */
-+
-+ if (level < 0)
-+ return;
-+
-+ pvr_page_table_l0_sync(ptr->l0_table);
-+
-+ if (level < 1)
-+ return;
-+
-+ pvr_page_table_l1_sync(ptr->l1_table);
-+
-+ if (level < 2)
-+ return;
-+
-+ pvr_page_table_l2_sync(ptr->l2_table);
-+}
-+
-+/**
-+ * pvr_page_table_ptr_sync_partial() - TODO
-+ * @ptr: Target page table pointer.
-+ * @level: TODO
-+ */
-+static void
-+pvr_page_table_ptr_sync_partial(struct pvr_page_table_ptr *ptr, s8 level)
-+{
-+ /*
-+ * If the requested sync level is greater than or equal to the
-+ * currently required sync level, we do two things:
-+ * * Don't waste time syncing levels we haven't previously marked as
-+ * requiring a sync, and
-+ * * Reset the required sync level since we are about to sync
-+ * everything that was previously marked as requiring a sync.
-+ */
-+ if (level >= ptr->sync_level_required) {
-+ level = ptr->sync_level_required;
-+ ptr->sync_level_required = -1;
-+ }
-+
-+ pvr_page_table_ptr_sync_manual(ptr, level);
-+}
-+
-+/**
-+ * pvr_page_table_ptr_sync() - TODO
-+ * @ptr: Target page table pointer.
-+ */
-+static __always_inline void
-+pvr_page_table_ptr_sync(struct pvr_page_table_ptr *ptr)
-+{
-+ pvr_page_table_ptr_sync_manual(ptr, ptr->sync_level_required);
-+}
-+
-+/**
-+ * pvr_page_table_ptr_load_tables() - TODO
-+ * @ptr: Target page table pointer.
-+ * @should_create: Specifies whether new page tables should be created when
-+ * empty page table entries are encountered during traversal.
-+ * @load_level_required: TODO
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * ...
-+ */
-+static int
-+pvr_page_table_ptr_load_tables(struct pvr_page_table_ptr *ptr,
-+ bool should_create, s8 load_level_required)
-+{
-+ bool did_create_l1;
-+ bool did_create_l0;
-+ int err;
-+
-+ /* Clear tables we're about to fetch in case of error states. */
-+ if (load_level_required >= 1)
-+ ptr->l1_table = NULL;
-+
-+ if (load_level_required >= 0)
-+ ptr->l0_table = NULL;
-+
-+ /* Get or create L1 page table. */
-+ if (load_level_required >= 1) {
-+ ptr->l1_table = pvr_page_table_l1_get_or_create(ptr->pvr_dev,
-+ ptr->l2_table,
-+ ptr->l2_idx,
-+ should_create,
-+ &did_create_l1);
-+ if (IS_ERR(ptr->l1_table)) {
-+ err = PTR_ERR(ptr->l1_table);
-+ ptr->l1_table = NULL;
-+
-+ /*
-+ * If @should_create is %false and no L1 page table was
-+ * found, return early but without an error. Since
-+ * pvr_page_table_l1_get_or_create() can only return
-+ * -%ENXIO if @should_create is %false, there is no
-+ * need to check it here.
-+ */
-+ if (err == -ENXIO)
-+ err = 0;
-+
-+ goto err_out;
-+ }
-+ }
-+
-+ /* Get or create L0 page table. */
-+ if (load_level_required >= 0) {
-+ ptr->l0_table = pvr_page_table_l0_get_or_create(ptr->pvr_dev,
-+ ptr->l1_table,
-+ ptr->l1_idx,
-+ should_create,
-+ &did_create_l0);
-+ if (IS_ERR(ptr->l0_table)) {
-+ err = PTR_ERR(ptr->l0_table);
-+ ptr->l0_table = NULL;
-+
-+ /*
-+ * If @should_create is %false and no L0 page table was
-+ * found, return early but without an error. Since
-+ * pvr_page_table_l0_get_or_create() can only return
-+ * -%ENXIO if @should_create is %false, there is no
-+ * need to check it here.
-+ */
-+ if (err == -ENXIO)
-+ err = 0;
-+
-+ /*
-+ * At this point, an L1 page table could have been
-+ * created but is now empty due to the failed attempt
-+ * at creating an L0 page table. In this instance, we
-+ * must destroy the empty L1 page table ourselves as
-+ * pvr_page_table_l1_remove() is never called as part
-+ * of the error path in
-+ * pvr_page_table_l0_get_or_create().
-+ */
-+ if (did_create_l1)
-+ __pvr_page_table_l1_destroy(ptr->l1_table);
-+
-+ goto err_out;
-+ }
-+ }
-+
-+ if (did_create_l1)
-+ pvr_page_table_ptr_require_sync(ptr, 2);
-+ else if (did_create_l0)
-+ pvr_page_table_ptr_require_sync(ptr, 1);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_page_table_ptr_set() - TODO
-+ * @ptr: Target page table pointer.
-+ * @device_addr: New pointer target.
-+ * @should_create: Specify whether new page tables should be created when
-+ * empty page table entries are encountered during traversal.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * ...
-+ */
-+static int
-+pvr_page_table_ptr_set(struct pvr_page_table_ptr *ptr, u64 device_addr,
-+ bool should_create)
-+{
-+ pvr_page_table_ptr_sync(ptr);
-+
-+ ptr->l2_idx = pvr_page_table_l2_idx(device_addr);
-+ ptr->l1_idx = pvr_page_table_l1_idx(device_addr);
-+ ptr->l0_idx = pvr_page_table_l0_idx(device_addr);
-+
-+ return pvr_page_table_ptr_load_tables(ptr, should_create, 1);
-+}
-+
-+/**
-+ * pvr_page_table_ptr_init() - Initialize a page table pointer.
-+ * @ptr: Target page table pointer.
-+ * @pvr_dev: TODO
-+ * @root_table: TODO
-+ * @device_addr: TODO
-+ * @should_create: Specify whether new page tables should be created when
-+ * empty page table entries are encountered during traversal.
-+ *
-+ * If @should_create is %true, the L0 page table will be flagged for
-+ *
-+ * It is expected that @ptr be zeroed (e.g. from kzalloc()) before calling this
-+ * function. Since &struct pvr_page_table_ptr is small-ish (4-5 words), it is
-+ * intended to be allocated on the stack. By default, this is zeroed memory
-+ * so this warning is essentially just a formality.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * ...
-+ */
-+static int
-+pvr_page_table_ptr_init(struct pvr_page_table_ptr *ptr,
-+ struct pvr_device *pvr_dev,
-+ struct pvr_page_table_l2 *root_table, u64 device_addr,
-+ bool should_create)
-+{
-+ ptr->pvr_dev = pvr_dev;
-+ ptr->l2_table = root_table;
-+ ptr->sync_level_required = -1;
-+
-+ return pvr_page_table_ptr_set(ptr, device_addr, should_create);
-+}
-+
-+/**
-+ * pvr_page_table_ptr_fini() - Teardown a page table pointer.
-+ * @ptr: Target page table pointer.
-+ */
-+static void
-+pvr_page_table_ptr_fini(struct pvr_page_table_ptr *ptr)
-+{
-+ pvr_page_table_ptr_sync(ptr);
-+}
-+
-+/**
-+ * pvr_page_table_ptr_next_page() - Advance a page table pointer.
-+ * @ptr: Target page table pointer.
-+ * @should_create: Specify whether new page tables should be created when
-+ * empty page table entries are encountered during traversal.
-+ *
-+ * If @should_create is %false, it is the callers responsibility to verify that
-+ * the state of the table references in @ptr is valid on return. If -%ENXIO is
-+ * returned, at least one of the table references is invalid. It should be
-+ * noted that @ptr as a whole will be left in a valid state if -%ENXIO is
-+ * returned, unlike other error codes. The caller should check which references
-+ * are invalid by comparing them to %NULL. Only &@ptr->l2_table is guaranteed
-+ * to be valid, since it represents the root of the page table tree structure.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EPERM if the operation would wrap at the top of the page table
-+ * hierarchy,
-+ * * -%ENXIO if @should_create is %false and a page table of any level would
-+ * have otherwise been created, or
-+ * * Any error returned while attempting to create missing page tables if
-+ * @should_create is %true.
-+ */
-+static int
-+pvr_page_table_ptr_next_page(struct pvr_page_table_ptr *ptr, bool should_create)
-+{
-+ s8 load_level_required = -1;
-+
-+ if (++ptr->l0_idx != ROGUE_MMUCTRL_ENTRIES_PT_L0_VALUE)
-+ goto load_tables;
-+
-+ ptr->l0_idx = 0;
-+ load_level_required = 0;
-+
-+ if (++ptr->l1_idx != ROGUE_MMUCTRL_ENTRIES_PT_L1_VALUE)
-+ goto load_tables;
-+
-+ ptr->l1_idx = 0;
-+ load_level_required = 1;
-+
-+ if (++ptr->l2_idx != ROGUE_MMUCTRL_ENTRIES_PT_L2_VALUE)
-+ goto load_tables;
-+
-+ /*
-+ * If the pattern continued, we would set &ptr->l2_idx to zero here.
-+ * However, that would wrap the top layer of the page table hierarchy
-+ * which is not a valid operation. Instead, we warn and return an
-+ * error.
-+ */
-+ WARN(true,
-+ "%s(%p) attempted to loop the top of the page table hierarchy",
-+ __func__, ptr);
-+ return -EPERM;
-+
-+ /* If indices have wrapped, we need to load new tables. */
-+load_tables:
-+ /* First, flush tables which will be unloaded. */
-+ pvr_page_table_ptr_sync_partial(ptr, load_level_required);
-+
-+ /* Then load tables from the required level down. */
-+ return pvr_page_table_ptr_load_tables(ptr, should_create,
-+ load_level_required);
-+}
-+
-+/**
-+ * pvr_page_table_ptr_copy() - TODO
-+ * @dst: TODO
-+ * @src: TODO
-+ */
-+static void
-+pvr_page_table_ptr_copy(struct pvr_page_table_ptr *dst,
-+ const struct pvr_page_table_ptr *src)
-+{
-+ memcpy(dst, src, sizeof(*dst));
-+
-+ /*
-+ * Nothing currently in the clone requires a sync later on, since the
-+ * original will handle it either when advancing or during teardown.
-+ */
-+ dst->sync_level_required = -1;
-+}
-+
-+/**
-+ * DOC: Single page operations
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * pvr_page_create() - Create a device virtual memory page and insert it into
-+ * an L0 page table.
-+ * @ptr: TODO
-+ * @dma_addr: DMA (quasi-physical) address which the created page should point
-+ * to.
-+ * @flags: Page options saved on the L0 page table entry for reading by the
-+ * device.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EEXIST if the requested page already exists.
-+ */
-+static int
-+pvr_page_create(struct pvr_page_table_ptr *ptr, dma_addr_t dma_addr,
-+ struct pvr_page_flags_raw flags)
-+{
-+ /* Do not create a new page if one already exists. */
-+ if (pvr_page_table_l0_entry_is_valid(ptr->l0_table, ptr->l0_idx))
-+ return -EEXIST;
-+
-+ pvr_page_table_l0_insert(ptr->l0_table, ptr->l0_idx, dma_addr, flags);
-+
-+ pvr_page_table_ptr_require_sync(ptr, 0);
-+
-+ return 0;
-+}
-+
-+/**
-+ * pvr_page_destroy() - Destroy a device page after removing it from its
-+ * parent L0 page table.
-+ * @ptr: TODO
-+ */
-+static void
-+pvr_page_destroy(struct pvr_page_table_ptr *ptr)
-+{
-+ /* Do nothing if the page does not exist. */
-+ if (!pvr_page_table_l0_entry_is_valid(ptr->l0_table, ptr->l0_idx))
-+ return;
-+
-+ /* Clear the parent L0 page table entry. */
-+ pvr_page_table_l0_remove(ptr->l0_table, ptr->l0_idx);
-+
-+ pvr_page_table_ptr_require_sync(ptr, 0);
-+}
-+
-+/**
-+ * DOC: Interval tree base implementation
-+ *
-+ * There is a note in <linux/interval_tree_generic.h> which says:
-+ *
-+ * Note - before using this, please consider if generic version
-+ * (interval_tree.h) would work for you...
-+ *
-+ * Here, then, is our justification for using the generic version, instead
-+ * of the generic version (naming is hard, okay!):
-+ *
-+ * The generic version of &struct interval_tree_node (from
-+ * <linux/interval_tree.h> uses unsigned long. We always need the elements to
-+ * be 64 bits wide, regardless of host pointer size. We could gate this
-+ * implementation on %BITS_PER_LONG, but it's better for us to store &start
-+ * and &size then derive &last rather than the way &struct interval_tree_node
-+ * does it, storing &start and &last] then deriving &size.
-+ */
-+
-+/**
-+ * pvr_vm_interval_tree_compute_last() - Compute the inclusive last value of
-+ * a range.
-+ * @start: Start of range.
-+ * @size: Size of range.
-+ *
-+ * This seemingly useless function was added to attempt to eliminate some
-+ * off-by-one errors which managed to creep in before it existed.
-+ *
-+ * Return:
-+ * * The last (inclusive) value of the range specified by @start and @size.
-+ */
-+static __always_inline u64
-+pvr_vm_interval_tree_compute_last(u64 start, u64 size)
-+{
-+ if (!size)
-+ return start;
-+
-+ return start + size - 1;
-+}
-+
-+/**
-+ * struct pvr_vm_interval_tree_node - A node in our implementation of an
-+ * interval tree.
-+ *
-+ * Unlike the generic implementation in <linux/interval_tree.h>, we store the
-+ * size of the interval instead of the last value. To access the last value (as
-+ * required by the implementation behind INTERVAL_TREE_DEFINE()) use
-+ * pvr_vm_internal_tree_node_last().
-+ */
-+struct pvr_vm_interval_tree_node {
-+ /** @rb: Base RB-tree node. **For internal use only.** */
-+ struct rb_node rb;
-+
-+ /**
-+ * @start: The start value of the range represented by this node.
-+ * **For internal use only.**
-+ *
-+ * Do not access this member directly, instead call
-+ * pvr_vm_interval_tree_node_start().
-+ */
-+ u64 start;
-+
-+ /**
-+ * @size: The size of the range represented by this node.
-+ * **For internal use only.**
-+ *
-+ * Do not access this member directly, instead call
-+ * pvr_vm_interval_tree_node_size().
-+ */
-+ u64 size;
-+
-+ /**
-+ * @__subtree_last: Required for the implementation generated by
-+ * INTERVAL_TREE_DEFINE(). **For internal use only.**
-+ */
-+ u64 __subtree_last;
-+};
-+
-+static __always_inline bool
-+pvr_vm_interval_tree_node_is_inserted(struct pvr_vm_interval_tree_node *node)
-+{
-+ return !RB_EMPTY_NODE(&node->rb);
-+}
-+
-+static __always_inline void
-+pvr_vm_interval_tree_node_mark_removed(struct pvr_vm_interval_tree_node *node)
-+{
-+ RB_CLEAR_NODE(&node->rb);
-+}
-+
-+static __always_inline void
-+pvr_vm_interval_tree_node_init(struct pvr_vm_interval_tree_node *node,
-+ u64 start, u64 size)
-+{
-+ pvr_vm_interval_tree_node_mark_removed(node);
-+
-+ node->start = start;
-+ node->size = size;
-+}
-+
-+static __always_inline void
-+pvr_vm_interval_tree_node_fini(struct pvr_vm_interval_tree_node *node)
-+{
-+ WARN(pvr_vm_interval_tree_node_is_inserted(node),
-+ "%s(%p) called before removing node from tree", __func__, node);
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_node_start() - TODO
-+ * @node: Target VM interval tree node.
-+ *
-+ * Return:
-+ * * The start value of @node.
-+ */
-+static __always_inline u64
-+pvr_vm_interval_tree_node_start(struct pvr_vm_interval_tree_node *node)
-+{
-+ return node->start;
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_node_size() - TODO
-+ * @node: Target VM interval tree node.
-+ *
-+ * Return:
-+ * * The size of @node.
-+ */
-+static __always_inline u64
-+pvr_vm_interval_tree_node_size(struct pvr_vm_interval_tree_node *node)
-+{
-+ return node->size;
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_node_last() - TODO
-+ * @node: Target VM interval tree node.
-+ *
-+ * Return:
-+ * * The last (inclusive) value of @node.
-+ */
-+static __always_inline u64
-+pvr_vm_interval_tree_node_last(struct pvr_vm_interval_tree_node *node)
-+{
-+ return pvr_vm_interval_tree_compute_last(node->start, node->size);
-+}
-+
-+INTERVAL_TREE_DEFINE(struct pvr_vm_interval_tree_node, rb, u64, __subtree_last,
-+ pvr_vm_interval_tree_node_start,
-+ pvr_vm_interval_tree_node_last, static,
-+ __pvr_vm_interval_tree)
-+
-+/**
-+ * for_each_pvr_vm_interval_tree_node() - Helper macro to iterate a specific
-+ * range of an interval tree.
-+ * @tree_:
-+ * @node_:
-+ * @start_:
-+ * @size_:
-+ *
-+ * Due to the way interval tree iteration works, formulating a ``for`` loop
-+ * around it is pretty verbose! We can encapsulate all that lengthiness in a
-+ * single macro (so we did).
-+ */
-+#define for_each_pvr_vm_interval_tree_node(tree_, node_, start_, size_) \
-+ for ((node_) = pvr_vm_interval_tree_iter_first((tree_), (start_), \
-+ (size_)); \
-+ (node_); \
-+ (node_) = pvr_vm_interval_tree_iter_next((node_), (start_), \
-+ (size_)))
-+
-+/**
-+ * struct pvr_vm_interval_tree - TODO
-+ */
-+struct pvr_vm_interval_tree {
-+ /** @root: TODO */
-+ struct rb_root_cached root;
-+} __packed;
-+
-+/**
-+ * pvr_vm_interval_tree_insert() - TODO
-+ * @tree: Target VM interval tree.
-+ * @node: Node to be inserted.
-+ */
-+static __always_inline void
-+pvr_vm_interval_tree_insert(struct pvr_vm_interval_tree *tree,
-+ struct pvr_vm_interval_tree_node *node)
-+{
-+ WARN(pvr_vm_interval_tree_node_is_inserted(node),
-+ "%s(%p,%p) called on a node which is already in a tree", __func__,
-+ tree, node);
-+
-+ /* This function is generated by INTERVAL_TREE_DEFINE(). */
-+ __pvr_vm_interval_tree_insert(node, &tree->root);
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_remove() - TODO
-+ * @tree: Target VM interval tree.
-+ * @node: Node to be removed.
-+ */
-+static __always_inline void
-+pvr_vm_interval_tree_remove(struct pvr_vm_interval_tree *tree,
-+ struct pvr_vm_interval_tree_node *node)
-+{
-+ WARN(!pvr_vm_interval_tree_node_is_inserted(node),
-+ "%s(%p,%p) called on a node which is not in a tree", __func__,
-+ tree, node);
-+
-+ /* This function is generated by INTERVAL_TREE_DEFINE(). */
-+ __pvr_vm_interval_tree_remove(node, &tree->root);
-+
-+ pvr_vm_interval_tree_node_mark_removed(node);
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_subtree_search() - TODO
-+ * @node: Node to search from.
-+ * @start: Start value of the iterable range.
-+ * @size: Size of the iterable range.
-+ */
-+static __always_inline struct pvr_vm_interval_tree_node *
-+pvr_vm_interval_tree_subtree_search(struct pvr_vm_interval_tree_node *node,
-+ u64 start, u64 size)
-+{
-+ /* This function is generated by INTERVAL_TREE_DEFINE(). */
-+ return __pvr_vm_interval_tree_subtree_search(
-+ node, start, pvr_vm_interval_tree_compute_last(start, size));
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_iter_first() - TODO
-+ * @tree: Target VM interval tree.
-+ * @start: Start value of the iterable range.
-+ * @size: Size of the iterable range.
-+ *
-+ * *This function is generated by INTERVAL_TREE_DEFINE().*
-+ */
-+static __always_inline struct pvr_vm_interval_tree_node *
-+pvr_vm_interval_tree_iter_first(struct pvr_vm_interval_tree *tree, u64 start,
-+ u64 size)
-+{
-+ u64 last = pvr_vm_interval_tree_compute_last(start, size);
-+
-+ /* This function is generated by INTERVAL_TREE_DEFINE(). */
-+ return __pvr_vm_interval_tree_iter_first(&tree->root, start, last);
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_iter_next() - TODO
-+ * @node: Node to iterate from.
-+ * @start: Start value of the iterable range.
-+ * @size: Size of the iterable range.
-+ */
-+static __always_inline struct pvr_vm_interval_tree_node *
-+pvr_vm_interval_tree_iter_next(struct pvr_vm_interval_tree_node *node,
-+ u64 start, u64 size)
-+{
-+ u64 last = pvr_vm_interval_tree_compute_last(start, size);
-+
-+ /* This function is generated by INTERVAL_TREE_DEFINE(). */
-+ return __pvr_vm_interval_tree_iter_next(node, start, last);
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_init() - Initialize an interval tree.
-+ * @tree: Target VM interval tree.
-+ */
-+static __always_inline void
-+pvr_vm_interval_tree_init(struct pvr_vm_interval_tree *tree)
-+{
-+ tree->root = RB_ROOT_CACHED;
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_fini() - Teardown an interval tree.
-+ * @tree: Target VM interval tree.
-+ *
-+ * It is an error to call this function on a non-empty interval tree. Doing
-+ * so is very likely to cause a memory leak. For this reason,
-+ * pvr_vm_interval_tree_fini() will emit a kernel warning for each entry found
-+ * in the target tree before returning.
-+ */
-+static void
-+pvr_vm_interval_tree_fini(struct pvr_vm_interval_tree *tree)
-+{
-+ struct pvr_vm_interval_tree_node *node;
-+
-+ /* clang-format off */
-+ for_each_pvr_vm_interval_tree_node(tree, node, 0, U64_MAX) {
-+ WARN(true, "%s(%p) found [%llx,%llx]@%p", __func__, tree,
-+ pvr_vm_interval_tree_node_start(node),
-+ pvr_vm_interval_tree_node_last(node), node);
-+ }
-+ /* clang-format on */
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_contains() - Check if any node in an interval tree
-+ * overlaps with a specified range.
-+ * @tree: Target VM interval tree.
-+ * @start: Start value of the search range.
-+ * @size: Size of the search range.
-+ *
-+ * This function is just a call to pvr_vm_interval_tree_iter_first() with the
-+ * returned pointer coerced into a ``bool`` for convenience. It should always
-+ * be inlined.
-+ *
-+ * Return:
-+ * * %true if any node in the target interval tree overlaps with the range
-+ * specified by @start and @size, or
-+ * * %false otherwise.
-+ */
-+static __always_inline bool
-+pvr_vm_interval_tree_contains(struct pvr_vm_interval_tree *tree, u64 start,
-+ u64 size)
-+{
-+ return pvr_vm_interval_tree_iter_first(tree, start, size);
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_find() - Find a node which completely contains a range.
-+ * @tree: Target VM interval tree.
-+ * @start: Start value of the required range.
-+ * @size: Size of the required range.
-+ *
-+ * Return:
-+ * * A node containing the entire range specified by @start and @size, or
-+ * * %NULL if such a node does not currently exist in @tree.
-+ */
-+static struct pvr_vm_interval_tree_node *
-+pvr_vm_interval_tree_find(struct pvr_vm_interval_tree *tree, u64 start,
-+ u64 size)
-+{
-+ /*
-+ * We only search for the start of the range here, because the search
-+ * implementation for interval_tree only looks for intersections. After
-+ * a node is found that contains the start value, we can check that it
-+ * also contains the last value.
-+ */
-+ struct pvr_vm_interval_tree_node *node =
-+ pvr_vm_interval_tree_iter_first(tree, start, 0);
-+
-+ /*
-+ * Check that a node exists around the requested range and that it
-+ * encompasses the entire range.
-+ */
-+ if (!node || pvr_vm_interval_tree_compute_last(start, size) >
-+ pvr_vm_interval_tree_node_last(node))
-+ return NULL;
-+
-+ return node;
-+}
-+
-+/**
-+ * pvr_vm_interval_tree_get() - Fetch a node by its exact start value.
-+ * @tree: Target VM interval tree.
-+ * @start: Start value of the required node.
-+ *
-+ * Return:
-+ * * A node whose start address is exactly @start, or
-+ * * %NULL if such a node does not currently exist in @tree.
-+ */
-+static struct pvr_vm_interval_tree_node *
-+pvr_vm_interval_tree_get(struct pvr_vm_interval_tree *tree, u64 start)
-+{
-+ struct pvr_vm_interval_tree_node *node =
-+ pvr_vm_interval_tree_iter_first(tree, start, 0);
-+
-+ if (!node || pvr_vm_interval_tree_node_start(node) != start)
-+ return NULL;
-+
-+ return node;
-+}
-+
-+/**
-+ * DOC: Type-save VM interval tree wrappers
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * PVR_GEN_INTERVAL_TREE_WRAPPER_TYPE_AND_DECLS() - TODO
-+ * @node_wrapper_: Type name of the structure to use as a node.
-+ *
-+ * TODO
-+ *
-+ * This is the first half of a two-part implementation. The second half can be
-+ * found in PVR_GEN_INTERVAL_TREE_WRAPPER_DEFS().
-+ */
-+#define PVR_GEN_INTERVAL_TREE_WRAPPER_TYPE_AND_DECLS(node_wrapper_) \
-+ struct node_wrapper_##_tree { \
-+ struct pvr_vm_interval_tree tree; \
-+ } __packed; \
-+ \
-+ struct node_wrapper_; \
-+ \
-+ static __always_inline void node_wrapper_##_tree_init( \
-+ struct node_wrapper_##_tree *tree); \
-+ \
-+ static __always_inline void node_wrapper_##_tree_fini( \
-+ struct node_wrapper_##_tree *tree); \
-+ \
-+ static __always_inline u64 node_wrapper_##_start( \
-+ struct node_wrapper_ *node); \
-+ \
-+ static __always_inline u64 node_wrapper_##_last( \
-+ struct node_wrapper_ *node); \
-+ \
-+ static __always_inline void node_wrapper_##_tree_insert( \
-+ struct node_wrapper_##_tree *tree, \
-+ struct node_wrapper_ *node); \
-+ \
-+ static __always_inline void node_wrapper_##_tree_remove( \
-+ struct node_wrapper_##_tree *tree, \
-+ struct node_wrapper_ *node); \
-+ \
-+ static __always_inline struct node_wrapper_ \
-+ *node_wrapper_##_tree_iter_first( \
-+ struct node_wrapper_##_tree *tree, u64 start, \
-+ u64 size); \
-+ \
-+ static __always_inline struct node_wrapper_ \
-+ *node_wrapper_##_tree_iter_next(struct node_wrapper_ *node, \
-+ u64 start, u64 size); \
-+ \
-+ static __always_inline bool node_wrapper_##_tree_contains( \
-+ struct node_wrapper_##_tree *tree, u64 start, u64 size); \
-+ \
-+ static __always_inline struct node_wrapper_ *node_wrapper_##_tree_find( \
-+ struct node_wrapper_##_tree *tree, u64 start, u64 size); \
-+ \
-+ static __always_inline struct node_wrapper_ *node_wrapper_##_tree_get( \
-+ struct node_wrapper_##_tree *tree, u64 start);
-+
-+/**
-+ * PVR_GEN_INTERVAL_TREE_WRAPPER_DEFS() - TODO
-+ * @node_wrapper_: Type name of the structure to use as a node.
-+ * @node_wrapper_member_: Member name of the base
-+ * &struct pvr_vm_interval_tree_node in the structure specified by
-+ * @node_wrapper_.
-+ *
-+ * TODO
-+ *
-+ * This is the second half of a two-part implementation. The first half can be
-+ * found in PVR_GEN_INTERVAL_TREE_WRAPPER_TYPE_AND_DECLS().
-+ */
-+#define PVR_GEN_INTERVAL_TREE_WRAPPER_DEFS(node_wrapper_, \
-+ node_wrapper_member_) \
-+ static __always_inline void node_wrapper_##_tree_init( \
-+ struct node_wrapper_##_tree *tree) \
-+ { \
-+ pvr_vm_interval_tree_init(&tree->tree); \
-+ } \
-+ \
-+ static __always_inline void node_wrapper_##_tree_fini( \
-+ struct node_wrapper_##_tree *tree) \
-+ { \
-+ pvr_vm_interval_tree_fini(&tree->tree); \
-+ } \
-+ \
-+ static __always_inline u64 node_wrapper_##_start( \
-+ struct node_wrapper_ *node) \
-+ { \
-+ return pvr_vm_interval_tree_node_start( \
-+ &node->node_wrapper_member_); \
-+ } \
-+ \
-+ static __always_inline u64 node_wrapper_##_size( \
-+ struct node_wrapper_ *node) \
-+ { \
-+ return pvr_vm_interval_tree_node_size( \
-+ &node->node_wrapper_member_); \
-+ } \
-+ \
-+ static __always_inline u64 node_wrapper_##_last( \
-+ struct node_wrapper_ *node) \
-+ { \
-+ return pvr_vm_interval_tree_node_last( \
-+ &node->node_wrapper_member_); \
-+ } \
-+ \
-+ static __always_inline struct node_wrapper_ *node_wrapper_##_from_node( \
-+ struct pvr_vm_interval_tree_node *node) \
-+ { \
-+ return container_of_safe(node, struct node_wrapper_, \
-+ node_wrapper_member_); \
-+ } \
-+ \
-+ static __always_inline void node_wrapper_##_tree_insert( \
-+ struct node_wrapper_##_tree *tree, struct node_wrapper_ *node) \
-+ { \
-+ pvr_vm_interval_tree_insert(&tree->tree, \
-+ &node->node_wrapper_member_); \
-+ } \
-+ \
-+ static __always_inline void node_wrapper_##_tree_remove( \
-+ struct node_wrapper_##_tree *tree, struct node_wrapper_ *node) \
-+ { \
-+ pvr_vm_interval_tree_remove(&tree->tree, \
-+ &node->node_wrapper_member_); \
-+ } \
-+ \
-+ static __always_inline struct node_wrapper_ \
-+ *node_wrapper_##_tree_iter_first( \
-+ struct node_wrapper_##_tree *tree, u64 start, \
-+ u64 size) \
-+ { \
-+ return node_wrapper_##_from_node( \
-+ pvr_vm_interval_tree_iter_first(&tree->tree, start, \
-+ size)); \
-+ } \
-+ \
-+ static __always_inline struct node_wrapper_ \
-+ *node_wrapper_##_tree_iter_next(struct node_wrapper_ *node, \
-+ u64 start, u64 size) \
-+ { \
-+ return node_wrapper_##_from_node( \
-+ pvr_vm_interval_tree_iter_next( \
-+ &node->node_wrapper_member_, start, size)); \
-+ } \
-+ \
-+ static __always_inline bool node_wrapper_##_tree_contains( \
-+ struct node_wrapper_##_tree *tree, u64 start, u64 size) \
-+ { \
-+ return pvr_vm_interval_tree_contains(&tree->tree, start, \
-+ size); \
-+ } \
-+ \
-+ static __always_inline struct node_wrapper_ *node_wrapper_##_tree_find( \
-+ struct node_wrapper_##_tree *tree, u64 start, u64 size) \
-+ { \
-+ return node_wrapper_##_from_node( \
-+ pvr_vm_interval_tree_find(&tree->tree, start, size)); \
-+ } \
-+ \
-+ static __always_inline struct node_wrapper_ *node_wrapper_##_tree_get( \
-+ struct node_wrapper_##_tree *tree, u64 start) \
-+ { \
-+ return node_wrapper_##_from_node( \
-+ pvr_vm_interval_tree_get(&tree->tree, start)); \
-+ }
-+
-+PVR_GEN_INTERVAL_TREE_WRAPPER_TYPE_AND_DECLS(pvr_vm_mapping);
-+
-+/**
-+ * DOC: Memory context
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * struct pvr_vm_context - TODO
-+ */
-+struct pvr_vm_context {
-+ /**
-+ * @pvr_dev: TODO
-+ */
-+ struct pvr_device *pvr_dev;
-+
-+ /** @root_table: The root of the page table tree structure.*/
-+ struct pvr_page_table_l2 root_table;
-+
-+ /**
-+ * @mappings: TODO
-+ */
-+ struct pvr_vm_mapping_tree mappings;
-+
-+ /**
-+ * @lock: Global lock on this entire structure of page tables.
-+ *
-+ * .. admonition:: Future work
-+ *
-+ * This "global" lock is potentially not the most efficient method
-+ * of protecting the entire page table tree structure. Investigation
-+ * into more granular methods would be a good idea.
-+ */
-+ struct mutex lock;
-+};
-+
-+dma_addr_t pvr_vm_get_page_catalogue_addr(struct pvr_vm_context *vm_ctx)
-+{
-+ return vm_ctx->root_table.backing_page.dma_addr;
-+}
-+
-+/**
-+ * pvr_vm_context_init() - TODO
-+ * @vm_ctx: Target VM context.
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+static int
-+pvr_vm_context_init(struct pvr_vm_context *vm_ctx, struct pvr_device *pvr_dev)
-+{
-+ int err;
-+
-+ err = pvr_page_table_l2_init(&vm_ctx->root_table, pvr_dev);
-+ if (err)
-+ goto err_out;
-+
-+ pvr_vm_mapping_tree_init(&vm_ctx->mappings);
-+
-+ mutex_init(&vm_ctx->lock);
-+
-+ vm_ctx->pvr_dev = pvr_dev;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_context_fini() - TODO
-+ * @vm_ctx: Target VM context.
-+ * @enable_warnings: Whether to print warnings for remaining mappings.
-+ */
-+static void
-+pvr_vm_context_fini(struct pvr_vm_context *vm_ctx, bool enable_warnings)
-+{
-+ struct pvr_vm_mapping *mapping;
-+
-+ /* Destroy any remaining mappings. */
-+ mutex_lock(&vm_ctx->lock);
-+
-+ while ((mapping = pvr_vm_mapping_tree_iter_first(&vm_ctx->mappings, 0, U64_MAX)) != NULL) {
-+ WARN(enable_warnings, "%s(%p) found [%llx,%llx]@%p", __func__, &vm_ctx->mappings,
-+ pvr_vm_mapping_start(mapping), pvr_vm_mapping_last(mapping), mapping);
-+ pvr_vm_mapping_unmap(vm_ctx, mapping);
-+ pvr_vm_mapping_fini(mapping);
-+ kfree(mapping);
-+ }
-+
-+ mutex_unlock(&vm_ctx->lock);
-+
-+ mutex_destroy(&vm_ctx->lock);
-+ pvr_vm_mapping_tree_fini(&vm_ctx->mappings);
-+ pvr_page_table_l2_fini(&vm_ctx->root_table);
-+}
-+
-+static int
-+pvr_vm_context_unmap_from_ptr(struct pvr_page_table_ptr *ptr, u64 nr_pages)
-+{
-+ u64 page;
-+ int err;
-+
-+ if (nr_pages == 0)
-+ return 0;
-+
-+ /*
-+ * Destroy first page outside loop, as it doesn't require a pointer
-+ * increment beforehand. If the L0 page table reference in @ptr is
-+ * %NULL, there cannot be a mapped page at @ptr (so skip ahead).
-+ */
-+ if (ptr->l0_table)
-+ pvr_page_destroy(ptr);
-+
-+ for (page = 1; page < nr_pages; ++page) {
-+ err = pvr_page_table_ptr_next_page(ptr, false);
-+ /*
-+ * If the page table tree structure at @ptr is incomplete,
-+ * skip ahead. We don't care about unmapping pages that
-+ * cannot exist.
-+ *
-+ * FIXME: This could be made more efficient by jumping ahead
-+ * using pvr_page_table_ptr_set().
-+ */
-+ if (err == -ENXIO)
-+ continue;
-+
-+ if (err)
-+ goto err_out;
-+
-+ pvr_page_destroy(ptr);
-+ }
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_context_unmap() - TODO
-+ * @vm_ctx: Target memory context.
-+ * @device_addr: First virtual device address to unmap.
-+ * @nr_pages: Number of pages to unmap.
-+ *
-+ * The total amount of virtual memory unmapped by pvr_vm_context_unmap()
-+ * is @nr_pages * 4KiB.
-+ */
-+static int
-+pvr_vm_context_unmap(struct pvr_vm_context *vm_ctx, u64 device_addr,
-+ u64 nr_pages)
-+{
-+ struct pvr_page_table_ptr ptr;
-+ int err;
-+
-+ err = pvr_page_table_ptr_init(&ptr, vm_ctx->pvr_dev,
-+ &vm_ctx->root_table, device_addr, false);
-+ if (err && err != -ENXIO)
-+ goto err_out;
-+
-+ err = pvr_vm_context_unmap_from_ptr(&ptr, nr_pages);
-+ if (err)
-+ goto err_ptr_fini;
-+
-+ err = 0;
-+ goto err_ptr_fini;
-+
-+err_ptr_fini:
-+ pvr_page_table_ptr_fini(&ptr);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_vm_context_map_direct(struct pvr_vm_context *vm_ctx, dma_addr_t dma_addr,
-+ u64 size, struct pvr_page_table_ptr *ptr,
-+ struct pvr_page_flags_raw flags)
-+{
-+ unsigned int pages = size >> PVR_DEVICE_PAGE_SHIFT;
-+ unsigned int page;
-+
-+ struct pvr_page_table_ptr ptr_copy;
-+
-+ int err;
-+
-+ /*
-+ * Before progressing, save a copy of the start pointer so we can use
-+ * it again if we enter an error state and have to destroy pages.
-+ */
-+ pvr_page_table_ptr_copy(&ptr_copy, ptr);
-+
-+ /*
-+ * Create first page outside loop, as it doesn't require a pointer
-+ * increment beforehand.
-+ */
-+ err = pvr_page_create(ptr, dma_addr, flags);
-+ if (err)
-+ goto err_fini_ptr_copy;
-+
-+ for (page = 1; page < pages; ++page) {
-+ err = pvr_page_table_ptr_next_page(ptr, true);
-+ if (err)
-+ goto err_destroy_pages;
-+
-+ dma_addr += PVR_DEVICE_PAGE_SIZE;
-+
-+ err = pvr_page_create(ptr, dma_addr, flags);
-+ if (err)
-+ goto err_destroy_pages;
-+ }
-+
-+ err = 0;
-+ goto err_fini_ptr_copy;
-+
-+err_destroy_pages:
-+ err = pvr_vm_context_unmap_from_ptr(&ptr_copy, page);
-+
-+err_fini_ptr_copy:
-+ pvr_page_table_ptr_fini(&ptr_copy);
-+
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_context_map_partial_sgl() - Map part of a scatter-gather table entry
-+ * to virtual device memory.
-+ * @vm_ctx: Target VM context.
-+ * @sgl: Target scatter-gather table entry.
-+ * @offset: Offset into @sgl to map from. Must result in a starting address
-+ * from @sgl which is CPU page-aligned.
-+ * @size: Size of the memory to be mapped in bytes. Must be a non-zero multiple
-+ * of the device page size.
-+ * @ptr: Page table pointer which points to the first page that should be
-+ * mapped to. This will point to the last page mapped to on return.
-+ * @page_flags: Page options to be applied to every virtual device memory page
-+ * in the created mapping.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * -%EINVAL if the range specified by @offset and @size is not completely
-+ * within @sgl.
-+ */
-+static int
-+pvr_vm_context_map_partial_sgl(struct pvr_vm_context *vm_ctx,
-+ struct scatterlist *sgl, u64 offset, u64 size,
-+ struct pvr_page_table_ptr *ptr,
-+ struct pvr_page_flags_raw page_flags)
-+{
-+ dma_addr_t dma_addr = sg_dma_address(sgl);
-+ unsigned int dma_len = sg_dma_len(sgl);
-+
-+ if (offset + size > dma_len || offset > dma_len)
-+ return -EINVAL;
-+
-+ return pvr_vm_context_map_direct(vm_ctx, dma_addr + offset, size, ptr,
-+ page_flags);
-+}
-+
-+static int
-+pvr_vm_context_map_sgl(struct pvr_vm_context *vm_ctx, struct scatterlist *sgl,
-+ struct pvr_page_table_ptr *ptr,
-+ struct pvr_page_flags_raw page_flags)
-+{
-+ dma_addr_t dma_addr = sg_dma_address(sgl);
-+ unsigned int dma_len = sg_dma_len(sgl);
-+
-+ return pvr_vm_context_map_direct(vm_ctx, dma_addr, dma_len, ptr,
-+ page_flags);
-+}
-+
-+/**
-+ * pvr_vm_context_map_sgt() - Map an entire scatter-gather table into virtual
-+ * device memory.
-+ * @vm_ctx: Target VM context.
-+ * @sgt: Target scatter-gather table.
-+ * @device_addr: Virtual device address to map to. Must be device page-aligned.
-+ * @page_flags: Page options to be applied to every virtual device memory page
-+ * in the created mapping.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * ...
-+ */
-+static int
-+pvr_vm_context_map_sgt(struct pvr_vm_context *vm_ctx, struct sg_table *sgt,
-+ u64 device_addr, struct pvr_page_flags_raw page_flags)
-+{
-+ struct pvr_page_table_ptr ptr;
-+ struct pvr_page_table_ptr ptr_copy;
-+
-+ struct scatterlist *sgl;
-+ unsigned int sgt_idx;
-+
-+ u64 accumulated_size = 0;
-+ u64 created_size;
-+
-+ int err;
-+
-+ /*
-+ * Ensure that every sg table entry has a DMA address and length that
-+ * is a multiple of the device page size.
-+ */
-+ /* clang-format off */
-+ for_each_sgtable_dma_sg(sgt, sgl, sgt_idx) {
-+ accumulated_size += sg_dma_len(sgl);
-+
-+ if (sg_dma_address(sgl) & ~PVR_DEVICE_PAGE_MASK ||
-+ sg_dma_len(sgl) & ~PVR_DEVICE_PAGE_MASK) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+ }
-+ /* clang-format on */
-+
-+ err = pvr_page_table_ptr_init(&ptr, vm_ctx->pvr_dev,
-+ &vm_ctx->root_table, device_addr, true);
-+ if (err) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ /*
-+ * Before progressing, save a copy of the start pointer so we can use
-+ * it again if we enter an error state and have to destroy pages.
-+ */
-+ pvr_page_table_ptr_copy(&ptr_copy, &ptr);
-+
-+ /*
-+ * Map first sg table entry outside loop, as it doesn't require a
-+ * pointer increment beforehand. We know &sgl is valid here because an
-+ * sg table must contain at least one entry.
-+ */
-+ sgl = sgt->sgl;
-+ err = pvr_vm_context_map_sgl(vm_ctx, sgl, &ptr, page_flags);
-+ if (err)
-+ goto err_fini_ptr;
-+
-+ created_size = sg_dma_len(sgl);
-+
-+ while ((sgl = sg_next(sgl))) {
-+ err = pvr_page_table_ptr_next_page(&ptr, true);
-+ if (err) {
-+ err = -EINVAL;
-+ goto err_unmap;
-+ }
-+
-+ err = pvr_vm_context_map_sgl(vm_ctx, sgl, &ptr, page_flags);
-+ if (err)
-+ goto err_unmap;
-+
-+ created_size += sg_dma_len(sgl);
-+ }
-+
-+ err = 0;
-+ goto err_fini_ptr_and_ptr_copy;
-+
-+err_unmap:
-+ pvr_vm_context_unmap_from_ptr(&ptr_copy,
-+ created_size >> PVR_DEVICE_PAGE_SHIFT);
-+
-+err_fini_ptr_and_ptr_copy:
-+ pvr_page_table_ptr_fini(&ptr_copy);
-+
-+err_fini_ptr:
-+ pvr_page_table_ptr_fini(&ptr);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_context_map_partial_sgt() - Map part of a scatter-gather table into
-+ * virtual device memory.
-+ * @vm_ctx: Target VM context.
-+ * @sgt: Target scatter-gather table.
-+ * @sgt_offset: Offset into @sgt to map from. Must result in a starting
-+ * address from @sgt which is CPU page-aligned.
-+ * @device_addr: Virtual device address to map to. Must be device page-aligned.
-+ * @size: Size of memory to be mapped in bytes. Must be a non-zero multiple
-+ * of the device page size.
-+ * @page_flags: Page options to be applied to every virtual device memory page
-+ * in the created mapping.
-+ *
-+ * Return:
-+ * * 0 on success, or
-+ * * ...
-+ */
-+static int
-+pvr_vm_context_map_partial_sgt(struct pvr_vm_context *vm_ctx,
-+ struct sg_table *sgt, u64 sgt_offset,
-+ u64 device_addr, u64 size,
-+ struct pvr_page_flags_raw page_flags)
-+{
-+ struct pvr_page_table_ptr ptr;
-+ struct pvr_page_table_ptr ptr_copy;
-+
-+ struct scatterlist *sgl;
-+
-+ struct scatterlist *first_sgl;
-+ struct scatterlist *last_sgl;
-+
-+ /*
-+ * For these three (four) values:
-+ * * "offset" refers to the position in the given sgl to start mapping
-+ * from, and
-+ * * "size" refers to the amount of that sgl to map.
-+ *
-+ * For &first_sgl, "size" is the distance between "offset" and the
-+ * total size of the sgl.
-+ *
-+ * For &last_sgl, "offset" is always zero because it is contiguous with
-+ * the previous sgl. The only case it would be non-zero is when the
-+ * first and last sgls are the same, but this case is handled
-+ * specially.
-+ */
-+ u64 first_sgl_offset;
-+ /* There is no last_sgl_offset (see above). */
-+ u64 first_sgl_size;
-+ u64 last_sgl_size;
-+
-+ u64 accumulated_size = 0;
-+ u64 created_size;
-+
-+ int err;
-+
-+ /* @sgt must contain at least one entry. */
-+ if (!sgt->sgl) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ /*
-+ * First, skip through the sg table until we hit an entry which
-+ * contains sgt_offset.
-+ */
-+ sgl = sgt->sgl;
-+ do {
-+ accumulated_size += sg_dma_len(sgl);
-+
-+ if (accumulated_size > sgt_offset)
-+ goto found_first_sgl;
-+ } while ((sgl = sg_next(sgl)) != NULL);
-+
-+ /*
-+ * If we fall out of the loop above, we've reached the end of @sgt
-+ * without finding the start of the requested range.
-+ */
-+ err = -EINVAL;
-+ goto err_out;
-+
-+found_first_sgl:
-+ /* Record the entry discovered in the loop above. */
-+ first_sgl = sgl;
-+ first_sgl_size = accumulated_size - sgt_offset;
-+ first_sgl_offset = sg_dma_len(first_sgl) - first_sgl_size;
-+
-+ /*
-+ * Ensure that sgt_offset is within the bounds of the sg table; that
-+ * the DMA address given by the offset into the first sg table entry
-+ * is aligned to the device page size, and that the part of the first
-+ * sg table entry past the offset is a multiple of the device page
-+ * size.
-+ */
-+ if (accumulated_size < sgt_offset ||
-+ (sg_dma_address(sgl) + first_sgl_offset) & ~PVR_DEVICE_PAGE_MASK ||
-+ first_sgl_size & ~PVR_DEVICE_PAGE_MASK) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ /*
-+ * Resume iterating through the sg table until we hit an entry which
-+ * contains (sgt_offset + size). Use do-while here because the first
-+ * and last entries could be the same.
-+ */
-+ do {
-+ if (accumulated_size >= sgt_offset + size)
-+ goto found_last_sgl;
-+
-+ accumulated_size += sg_dma_len(sgl);
-+
-+ /*
-+ * This check should technically be at the top of this loop.
-+ * However, we've already performed it above for the first
-+ * iteration, so we move it to the bottom to prevent evaluating
-+ * it again. It will still be performed before every break
-+ * conditional.
-+ */
-+ if (sg_dma_address(sgl) & ~PVR_DEVICE_PAGE_MASK ||
-+ sg_dma_len(sgl) & ~PVR_DEVICE_PAGE_MASK) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+ } while ((sgl = sg_next(sgl)) != NULL);
-+
-+ /*
-+ * If we fall out of the loop above, we've reached the end of @sgt
-+ * without finding the end of the requested range.
-+ */
-+ err = -EINVAL;
-+ goto err_out;
-+
-+found_last_sgl:
-+ /* Record the entry discovered in the loop above. */
-+ last_sgl = sgl;
-+ last_sgl_size = accumulated_size - (sgt_offset + size);
-+
-+ /*
-+ * Ensure (sgt_offset + size) is within the bounds of the sg table and
-+ * that the part of the last sg table entry up to size is a
-+ * multiple of the page size.
-+ */
-+ if (accumulated_size < sgt_offset + size ||
-+ last_sgl_size & ~PVR_DEVICE_PAGE_MASK ||
-+ sg_dma_address(last_sgl) & ~PVR_DEVICE_PAGE_MASK) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ err = pvr_page_table_ptr_init(&ptr, vm_ctx->pvr_dev,
-+ &vm_ctx->root_table, device_addr, true);
-+ if (err) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ /*
-+ * If we only need to look at a single sg table entry, do that now so
-+ * we can apply both first_sgt_offset and last_sgt_size to it.
-+ */
-+ if (first_sgl == last_sgl) {
-+ err = pvr_vm_context_map_partial_sgl(vm_ctx, first_sgl,
-+ first_sgl_offset,
-+ last_sgl_size, &ptr,
-+ page_flags);
-+ if (err)
-+ goto err_fini_ptr;
-+
-+ /*
-+ * Flag the L0 page table as requiring a flush when the page
-+ * table pointer is destroyed.
-+ */
-+ pvr_page_table_ptr_require_sync(&ptr, 0);
-+
-+ goto out;
-+ }
-+
-+ /*
-+ * Before progressing, save a copy of the start pointer so we can use
-+ * it again if we enter an error state and have to destroy pages.
-+ * This is not needed for the case covered above since there is no
-+ * route to err_unmap from there.
-+ */
-+ pvr_page_table_ptr_copy(&ptr_copy, &ptr);
-+
-+ /*
-+ * When multiple sgls are mapped, we do so in three stages. Stages one
-+ * and three take care of the first and last sgls respectively. Each of
-+ * these use the associated values "offset" and "size" described above.
-+ *
-+ * The remaining "middle" sgls are mapped in their entirety by stage
-+ * two which does not need to care about those values.
-+ *
-+ * If the first and last sgls are adjacent (i.e. there are exactly two
-+ * sgls to map), stage two is skipped.
-+ */
-+
-+ /* [1/3] Map first page. */
-+ err = pvr_vm_context_map_partial_sgl(vm_ctx, first_sgl,
-+ first_sgl_offset, first_sgl_size,
-+ &ptr, page_flags);
-+ if (err)
-+ goto err_fini_ptr_and_ptr_copy;
-+
-+ created_size = first_sgl_size;
-+
-+ /* [2/3] Map middle pages (if any). */
-+ for (sgl = sg_next(first_sgl); sgl != last_sgl; sgl = sg_next(sgl)) {
-+ err = pvr_page_table_ptr_next_page(&ptr, true);
-+ if (err) {
-+ err = -EINVAL;
-+ goto err_unmap;
-+ }
-+
-+ err = pvr_vm_context_map_sgl(vm_ctx, sgl, &ptr, page_flags);
-+ if (err)
-+ goto err_unmap;
-+
-+ created_size += sg_dma_len(sgl);
-+ }
-+
-+ /* [3/3] Map last page. */
-+ err = pvr_page_table_ptr_next_page(&ptr, true);
-+ if (err) {
-+ err = -EINVAL;
-+ goto err_unmap;
-+ }
-+
-+ err = pvr_vm_context_map_partial_sgl(vm_ctx, last_sgl, 0, last_sgl_size,
-+ &ptr, page_flags);
-+ if (err)
-+ goto err_unmap;
-+
-+ /*
-+ * No need to update &created_size here as there are no more routes
-+ * to err_unmap past this point.
-+ */
-+
-+out:
-+ err = 0;
-+ goto err_fini_ptr_and_ptr_copy;
-+
-+err_unmap:
-+ pvr_vm_context_unmap_from_ptr(&ptr_copy,
-+ created_size >> PVR_DEVICE_PAGE_SHIFT);
-+
-+err_fini_ptr_and_ptr_copy:
-+ pvr_page_table_ptr_fini(&ptr_copy);
-+
-+err_fini_ptr:
-+ pvr_page_table_ptr_fini(&ptr);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * DOC: Memory mappings
-+ *
-+ * TODO
-+ */
-+/**
-+ * DOC: Memory mappings (constants)
-+ *
-+ * .. c:macro:: PVR_VM_MAPPING_COMPLETE
-+ *
-+ * This is a "magic" value which, when assigned to the
-+ * &pvr_vm_mapping->pvr_obj_offset member of a &struct pvr_vm_mapping,
-+ * indicates that it maps the entire associated &struct pvr_gem_object.
-+ */
-+
-+#define PVR_VM_MAPPING_COMPLETE ((unsigned int)(UINT_MAX))
-+
-+/**
-+ * struct pvr_vm_mapping - TODO
-+ *
-+ * This structure implicitly contains the device address and size of the
-+ * mapping through @node members &pvr_vm_interval_tree_node.start and
-+ * &pvr_vm_interval_tree_node.size respectively.
-+ */
-+struct pvr_vm_mapping {
-+ struct pvr_vm_interval_tree_node node;
-+ struct pvr_gem_object *pvr_obj;
-+ unsigned int pvr_obj_offset;
-+
-+ bool slc_bypass;
-+ bool pm_fw_protect;
-+};
-+
-+/**
-+ * DOC: Memory mappings (implementation)
-+ */
-+
-+PVR_GEN_INTERVAL_TREE_WRAPPER_DEFS(pvr_vm_mapping, node)
-+
-+static struct pvr_page_flags_raw
-+pvr_vm_mapping_page_flags_raw(struct pvr_vm_mapping *mapping)
-+{
-+ /*
-+ * FIXME: There is currently no way to mark a mapping as read-only or
-+ * cache-coherent. Should there be?
-+ */
-+ return pvr_page_flags_raw_create(false, false, mapping->slc_bypass,
-+ mapping->pm_fw_protect);
-+}
-+
-+/**
-+ * pvr_vm_mapping_init_partial() - TODO
-+ * @mapping: Target memory mapping.
-+ * @device_addr: TODO
-+ * @size: TODO
-+ * @pvr_obj: TODO
-+ * @pvr_obj_offset: TODO
-+ *
-+ * The memory behind @mapping should be zeroed before calling this function.
-+ */
-+static void
-+pvr_vm_mapping_init_partial(struct pvr_vm_mapping *mapping, u64 device_addr,
-+ u64 size, struct pvr_gem_object *pvr_obj,
-+ u64 pvr_obj_offset)
-+{
-+ u64 flags = pvr_obj->flags;
-+
-+ /*
-+ * Increment the refcount on the underlying physical memory resource
-+ * to prevent de-allocation while the mapping exists.
-+ */
-+ pvr_gem_object_get(pvr_obj);
-+
-+ mapping->pvr_obj = pvr_obj;
-+ mapping->pvr_obj_offset = pvr_obj_offset;
-+
-+ mapping->slc_bypass = flags & DRM_PVR_BO_DEVICE_BYPASS_CACHE;
-+ mapping->pm_fw_protect = flags & DRM_PVR_BO_DEVICE_PM_FW_PROTECT;
-+
-+ pvr_vm_interval_tree_node_init(&mapping->node, device_addr, size);
-+}
-+
-+/**
-+ * pvr_vm_mapping_init() - TODO
-+ * @mapping: Target memory mapping.
-+ * @device_addr: TODO
-+ * @pvr_obj: TODO
-+ *
-+ * Internally, this function just calls pvr_vm_mapping_init_partial() with the
-+ * extra arguments &size and &pvr_obj_offset populated with the size of
-+ * @pvr_obj and the "magic" constant %PVR_VM_MAPPING_COMPLETE respectively.
-+ */
-+static __always_inline void
-+pvr_vm_mapping_init(struct pvr_vm_mapping *mapping, u64 device_addr,
-+ struct pvr_gem_object *pvr_obj)
-+{
-+ pvr_vm_mapping_init_partial(mapping, device_addr,
-+ pvr_gem_object_size(pvr_obj), pvr_obj,
-+ PVR_VM_MAPPING_COMPLETE);
-+}
-+
-+static void
-+pvr_vm_mapping_fini(struct pvr_vm_mapping *mapping)
-+{
-+ pvr_vm_interval_tree_node_fini(&mapping->node);
-+
-+ pvr_gem_object_put(mapping->pvr_obj);
-+}
-+
-+static int
-+pvr_vm_mapping_map(struct pvr_vm_context *vm_ctx,
-+ struct pvr_vm_mapping *mapping)
-+{
-+ int err;
-+
-+ if (!pvr_gem_object_is_imported(mapping->pvr_obj)) {
-+ err = pvr_gem_object_get_pages(mapping->pvr_obj);
-+ if (err)
-+ goto err_out;
-+ }
-+
-+ if (mapping->pvr_obj_offset == PVR_VM_MAPPING_COMPLETE) {
-+ err = pvr_vm_context_map_sgt(
-+ vm_ctx, mapping->pvr_obj->sgt,
-+ pvr_vm_mapping_start(mapping),
-+ pvr_vm_mapping_page_flags_raw(mapping));
-+ } else {
-+ err = pvr_vm_context_map_partial_sgt(
-+ vm_ctx, mapping->pvr_obj->sgt, mapping->pvr_obj_offset,
-+ pvr_vm_mapping_start(mapping),
-+ pvr_vm_mapping_size(mapping),
-+ pvr_vm_mapping_page_flags_raw(mapping));
-+ }
-+ WARN_ON(pvr_vm_mmu_flush(vm_ctx->pvr_dev));
-+ if (err)
-+ goto err_put_pages;
-+
-+ pvr_vm_mapping_tree_insert(&vm_ctx->mappings, mapping);
-+
-+ return 0;
-+
-+err_put_pages:
-+ if (!pvr_gem_object_is_imported(mapping->pvr_obj))
-+ pvr_gem_object_put_pages(mapping->pvr_obj);
-+
-+err_out:
-+ return err;
-+}
-+
-+static int
-+pvr_vm_mapping_unmap(struct pvr_vm_context *vm_ctx,
-+ struct pvr_vm_mapping *mapping)
-+{
-+ int err;
-+
-+ pvr_vm_mapping_tree_remove(&vm_ctx->mappings, mapping);
-+
-+ err = pvr_vm_context_unmap(vm_ctx, pvr_vm_mapping_start(mapping),
-+ pvr_vm_mapping_size(mapping) >> PVR_DEVICE_PAGE_SHIFT);
-+ WARN_ON(pvr_vm_mmu_flush(vm_ctx->pvr_dev));
-+ if (err)
-+ goto err_out;
-+
-+ if (!pvr_gem_object_is_imported(mapping->pvr_obj))
-+ pvr_gem_object_put_pages(mapping->pvr_obj);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/*
-+ * Public API
-+ *
-+ * For an overview of these functions, see *DOC: Public API* in "pvr_vm.h".
-+ */
-+
-+/**
-+ * pvr_device_addr_is_valid() - Tests whether a virtual device address
-+ * is valid.
-+ * @device_addr: Virtual device address to test.
-+ *
-+ * Return:
-+ * * %true if @device_addr is within the valid range for a device page
-+ * table and is aligned to the device page size, or
-+ * * %false otherwise.
-+ */
-+bool
-+pvr_device_addr_is_valid(u64 device_addr)
-+{
-+ return (device_addr & ~PVR_PAGE_TABLE_ADDR_MASK) == 0 &&
-+ (device_addr & ~PVR_DEVICE_PAGE_MASK) == 0;
-+}
-+
-+/**
-+ * pvr_device_addr_and_size_are_valid() - Tests whether a device-virtual
-+ * address and associated size are both valid.
-+ *
-+ * Calling pvr_device_addr_is_valid() twice (once on @size, and again on
-+ * @device_addr + @size) to verify a device-virtual address range initially
-+ * seems intuitive, but it produces a false-negative when the address range
-+ * is right at the end of device-virtual address space.
-+ *
-+ * This function catches that corner case, as well as checking that
-+ * @size is non-zero.
-+ *
-+ * Return:
-+ * * %true if @device_addr is device page aligned; @size is device page
-+ * aligned; the range specified by @device_addr and @size is within the
-+ * bounds of the device-virtual address space, and @size is non-zero, or
-+ * * %false otherwise.
-+ */
-+bool
-+pvr_device_addr_and_size_are_valid(u64 device_addr, u64 size)
-+{
-+ return pvr_device_addr_is_valid(device_addr) &&
-+ size != 0 && (size & ~PVR_DEVICE_PAGE_MASK) == 0 &&
-+ (device_addr + size <= PVR_PAGE_TABLE_ADDR_SPACE_SIZE);
-+}
-+
-+/**
-+ * pvr_vm_create_context() - Create a new VM context.
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Return:
-+ * * A handle to the newly-minted VM context on success,
-+ * * -%EINVAL if the feature "virtual address space bits" on @pvr_dev is
-+ * missing or has an unsupported value,
-+ * * -%ENOMEM if allocation of the structure behind the opaque handle fails,
-+ * or
-+ * * Any error encountered while setting up internal structures.
-+ */
-+struct pvr_vm_context *
-+pvr_vm_create_context(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+
-+ struct pvr_vm_context *vm_ctx;
-+ u16 device_addr_bits;
-+
-+ int err;
-+
-+ err = PVR_FEATURE_VALUE(pvr_dev, virtual_address_space_bits,
-+ &device_addr_bits);
-+ if (err) {
-+ drm_err(drm_dev,
-+ "Failed to get device virtual address space bits\n");
-+ goto err_out;
-+ }
-+
-+ if (device_addr_bits != PVR_PAGE_TABLE_ADDR_BITS) {
-+ drm_err(drm_dev,
-+ "Device has unsupported virtual address space size\n");
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ vm_ctx = kzalloc(sizeof(*vm_ctx), GFP_KERNEL);
-+ if (!vm_ctx) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ err = pvr_vm_context_init(vm_ctx, pvr_dev);
-+ if (err)
-+ goto err_free_vm_ctx;
-+
-+ return vm_ctx;
-+
-+err_free_vm_ctx:
-+ kfree(vm_ctx);
-+
-+err_out:
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * pvr_vm_destroy_context() - Destroy an existing VM context.
-+ * @vm_ctx: Target VM context.
-+ * @enable_warnings: Whether to print warnings for remaining mappings.
-+ *
-+ * It is an error to call pvr_vm_destroy_context() on a VM context that has
-+ * already been destroyed.
-+ */
-+void
-+pvr_vm_destroy_context(struct pvr_vm_context *vm_ctx, bool enable_warnings)
-+{
-+ pvr_vm_context_fini(vm_ctx, enable_warnings);
-+ kfree(vm_ctx);
-+}
-+
-+static int
-+pvr_vm_map_mapping_locked(struct pvr_vm_context *vm_ctx,
-+ struct pvr_vm_mapping *mapping)
-+{
-+ u64 device_addr = pvr_vm_mapping_start(mapping);
-+ u64 size = pvr_vm_mapping_size(mapping);
-+
-+ int err;
-+
-+ lockdep_assert_held(&vm_ctx->lock);
-+
-+ /*
-+ * Check that the requested mapping range does not overlap with an
-+ * existing mapping.
-+ */
-+ if (pvr_vm_mapping_tree_contains(&vm_ctx->mappings, device_addr,
-+ size)) {
-+ err = -EEXIST;
-+ goto err_out;
-+ }
-+
-+ err = pvr_vm_mapping_map(vm_ctx, mapping);
-+ if (err)
-+ goto err_out;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_map() - Map a section of physical memory into a section of virtual
-+ * device memory.
-+ * @vm_ctx: Target VM context.
-+ * @pvr_obj: Target PowerVR memory object.
-+ * @device_addr: Virtual device address at the start of the requested mapping.
-+ *
-+ * If you only need to map part of @pvr_obj, use pvr_vm_map_partial() instead.
-+ *
-+ * No handle is returned to represent the mapping. Instead, callers should
-+ * remember @device_addr and use that as a handle.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if @device_addr is not a valid page-aligned virtual device
-+ * address or any part of @pvr_obj is not device virtual page-aligned,
-+ * * -%EEXIST if the requested mapping overlaps with an existing mapping,
-+ * * -%ENOMEM if allocation of internally required CPU memory fails, or
-+ * * Any error encountered while performing internal operations required to
-+ * create the mapping.
-+ */
-+int
-+pvr_vm_map(struct pvr_vm_context *vm_ctx, struct pvr_gem_object *pvr_obj,
-+ u64 device_addr)
-+{
-+ size_t size = pvr_gem_object_size(pvr_obj);
-+
-+ struct pvr_vm_mapping *mapping;
-+ int err;
-+
-+ if (!pvr_device_addr_and_size_are_valid(device_addr, size) ||
-+ size & ~PAGE_MASK) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
-+ if (!mapping) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ mutex_lock(&vm_ctx->lock);
-+
-+ pvr_vm_mapping_init(mapping, device_addr, pvr_obj);
-+
-+ err = pvr_vm_map_mapping_locked(vm_ctx, mapping);
-+ if (err)
-+ goto err_fini_mapping;
-+
-+ err = 0;
-+ goto err_unlock;
-+
-+err_fini_mapping:
-+ pvr_vm_mapping_fini(mapping);
-+ kfree(mapping);
-+
-+err_unlock:
-+ mutex_unlock(&vm_ctx->lock);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_map_partial() - Map a section of physical memory into a section of
-+ * virtual device memory.
-+ * @vm_ctx: Target VM context.
-+ * @pvr_obj: Target PowerVR memory object.
-+ * @pvr_obj_offset: Offset into @pvr_obj to map from.
-+ * @device_addr: Virtual device address at the start of the requested mapping.
-+ * @size: Size of the requested mapping.
-+ *
-+ * If you need to map an entire @pvr_obj, use pvr_vm_map() instead.
-+ *
-+ * No handle is returned to represent the mapping. Instead, callers should
-+ * remember @device_addr and use that as a handle.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if @device_addr is not a valid page-aligned virtual device
-+ * address; the region specified by @pvr_obj_offset and @size does not fall
-+ * entirely within @pvr_obj, or any part of the specified region of @pvr_obj
-+ * is not device virtual page-aligned,
-+ * * -%EEXIST if the requested mapping overlaps with an existing mapping,
-+ * * -%ENOMEM if allocation of internally required CPU memory fails, or
-+ * * Any error encountered while performing internal operations required to
-+ * create the mapping.
-+ */
-+int
-+pvr_vm_map_partial(struct pvr_vm_context *vm_ctx,
-+ struct pvr_gem_object *pvr_obj, u64 pvr_obj_offset,
-+ u64 device_addr, u64 size)
-+{
-+ size_t pvr_obj_size = pvr_gem_object_size(pvr_obj);
-+
-+ struct pvr_vm_mapping *mapping;
-+ int err;
-+
-+ if (!pvr_device_addr_and_size_are_valid(device_addr, size) ||
-+ pvr_obj_offset & ~PAGE_MASK || size & ~PAGE_MASK ||
-+ pvr_obj_offset + size > pvr_obj_size ||
-+ pvr_obj_offset > pvr_obj_size) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
-+ if (!mapping) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ mutex_lock(&vm_ctx->lock);
-+
-+ pvr_vm_mapping_init_partial(mapping, device_addr, size, pvr_obj,
-+ pvr_obj_offset);
-+
-+ err = pvr_vm_map_mapping_locked(vm_ctx, mapping);
-+ if (err)
-+ goto err_fini_mapping;
-+
-+ err = 0;
-+ goto err_unlock;
-+
-+err_fini_mapping:
-+ pvr_vm_mapping_fini(mapping);
-+ kfree(mapping);
-+
-+err_unlock:
-+ mutex_unlock(&vm_ctx->lock);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_unmap() - Unmap an already mapped section of virtual device memory.
-+ * @vm_ctx: Target VM context.
-+ * @device_addr: Virtual device address at the start of the target mapping.
-+ *
-+ * Return:
-+ * * 0 on success,
-+ * * -%EINVAL if @device_addr is not a valid page-aligned virtual device
-+ * address,
-+ * * -%ENOENT if @device_addr is not a handle to an existing mapping, or
-+ * * Any error encountered while performing internal operations required to
-+ * destroy the mapping.
-+ */
-+int
-+pvr_vm_unmap(struct pvr_vm_context *vm_ctx, u64 device_addr)
-+{
-+ struct pvr_vm_mapping *mapping;
-+ int err;
-+
-+ if (!pvr_device_addr_is_valid(device_addr)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ mutex_lock(&vm_ctx->lock);
-+
-+ mapping = pvr_vm_mapping_tree_iter_first(&vm_ctx->mappings,
-+ device_addr, 0);
-+ if (!mapping || pvr_vm_mapping_start(mapping) != device_addr) {
-+ err = -ENOENT;
-+ goto err_unlock;
-+ }
-+
-+ err = pvr_vm_mapping_unmap(vm_ctx, mapping);
-+ if (err)
-+ goto err_unlock;
-+
-+ pvr_vm_mapping_fini(mapping);
-+ kfree(mapping);
-+
-+ err = 0;
-+ goto err_unlock;
-+
-+err_unlock:
-+ mutex_unlock(&vm_ctx->lock);
-+
-+err_out:
-+ return err;
-+}
-+
-+/*
-+ * Static data areas are determined by firmware. Each array must be kept
-+ * in order of increasing offset, as this is used to determine the size of the
-+ * reserved area for each heap.
-+ */
-+static const struct drm_pvr_static_data_area general_static_data_areas[] = {
-+ {
-+ .id = DRM_PVR_STATIC_DATA_AREA_FENCE,
-+ .offset = 0,
-+ .size = 128,
-+ },
-+ {
-+ .id = DRM_PVR_STATIC_DATA_AREA_YUV_CSC,
-+ .offset = 128,
-+ .size = 1024,
-+ },
-+};
-+
-+static const struct drm_pvr_static_data_area pds_static_data_areas[] = {
-+ {
-+ .id = DRM_PVR_STATIC_DATA_AREA_VDM_SYNC,
-+ .offset = 0,
-+ .size = 128,
-+ },
-+ {
-+ .id = DRM_PVR_STATIC_DATA_AREA_EOT,
-+ .offset = 128,
-+ .size = 128,
-+ },
-+};
-+
-+static const struct drm_pvr_static_data_area usc_static_data_areas[] = {
-+ {
-+ .id = DRM_PVR_STATIC_DATA_AREA_VDM_SYNC,
-+ .offset = 0,
-+ .size = 128,
-+ },
-+};
-+
-+#define LAST_AREA(areas) (areas[ARRAY_SIZE(areas) - 1])
-+
-+#define GET_RESERVED_SIZE(areas) round_up((LAST_AREA(areas).offset + LAST_AREA(areas).size), \
-+ PAGE_SIZE)
-+
-+static const struct pvr_heap pvr_heaps[] = {
-+ {
-+ .id = DRM_PVR_HEAP_GENERAL,
-+ .flags = 0,
-+ .base = ROGUE_GENERAL_HEAP_BASE,
-+ .size = ROGUE_GENERAL_HEAP_SIZE,
-+ .reserved_base = ROGUE_GENERAL_HEAP_BASE,
-+ .reserved_size = GET_RESERVED_SIZE(general_static_data_areas),
-+ .page_size_log2 = 12,
-+ .static_data_areas = general_static_data_areas,
-+ .nr_static_data_areas = ARRAY_SIZE(general_static_data_areas),
-+ },
-+ {
-+ .id = DRM_PVR_HEAP_PDS_CODE_DATA,
-+ .flags = 0,
-+ .base = ROGUE_PDSCODEDATA_HEAP_BASE,
-+ .size = ROGUE_PDSCODEDATA_HEAP_SIZE,
-+ .reserved_base = ROGUE_PDSCODEDATA_HEAP_BASE,
-+ .reserved_size = GET_RESERVED_SIZE(pds_static_data_areas),
-+ .page_size_log2 = 12,
-+ .static_data_areas = pds_static_data_areas,
-+ .nr_static_data_areas = ARRAY_SIZE(pds_static_data_areas),
-+ },
-+ {
-+ .id = DRM_PVR_HEAP_USC_CODE,
-+ .flags = 0,
-+ .base = ROGUE_USCCODE_HEAP_BASE,
-+ .size = ROGUE_USCCODE_HEAP_SIZE,
-+ .reserved_base = ROGUE_USCCODE_HEAP_BASE,
-+ .reserved_size = GET_RESERVED_SIZE(usc_static_data_areas),
-+ .page_size_log2 = 12,
-+ .static_data_areas = usc_static_data_areas,
-+ .nr_static_data_areas = ARRAY_SIZE(usc_static_data_areas),
-+ },
-+};
-+
-+static const struct pvr_heap rgnhdr_heap = {
-+ .id = DRM_PVR_HEAP_RGNHDR,
-+ .flags = 0,
-+ .base = ROGUE_RGNHDR_HEAP_BASE,
-+ .size = ROGUE_RGNHDR_HEAP_SIZE,
-+ .reserved_base = 0,
-+ .reserved_size = 0,
-+ .page_size_log2 = 12,
-+};
-+
-+static __always_inline u32
-+pvr_get_nr_heaps(struct pvr_device *pvr_dev)
-+{
-+ u32 heaps = ARRAY_SIZE(pvr_heaps);
-+
-+ /* Region header heap is only present if BRN63142 is present. */
-+ if (PVR_HAS_QUIRK(pvr_dev, 63142))
-+ heaps++;
-+
-+ return heaps;
-+}
-+
-+int
-+pvr_get_heap_info(struct pvr_device *pvr_dev, struct drm_pvr_ioctl_get_heap_info_args *args)
-+{
-+ int err;
-+
-+ if (args->data) {
-+ const struct pvr_heap *pvr_heap;
-+
-+ if (args->heap_nr < ARRAY_SIZE(pvr_heaps)) {
-+ pvr_heap = &pvr_heaps[args->heap_nr];
-+ } else if (args->heap_nr == ARRAY_SIZE(pvr_heaps) &&
-+ PVR_HAS_QUIRK(pvr_dev, 63142)) {
-+ /* Region header heap is only present if BRN63142 is present. */
-+ pvr_heap = &rgnhdr_heap;
-+ } else {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ switch (args->op) {
-+ case DRM_PVR_HEAP_OP_GET_HEAP_INFO: {
-+ struct drm_pvr_heap heap_out;
-+
-+ heap_out.id = pvr_heap->id;
-+ heap_out.flags = pvr_heap->flags;
-+ heap_out.base = pvr_heap->base;
-+ heap_out.size = pvr_heap->size;
-+ heap_out.reserved_base = pvr_heap->reserved_base;
-+ heap_out.reserved_size = pvr_heap->reserved_size;
-+ heap_out.page_size_log2 = pvr_heap->page_size_log2;
-+ heap_out.nr_static_data_areas = pvr_heap->nr_static_data_areas;
-+
-+ if (copy_to_user(u64_to_user_ptr(args->data), &heap_out,
-+ sizeof(heap_out))) {
-+ err = -EFAULT;
-+ goto err_out;
-+ }
-+ break;
-+ }
-+
-+ case DRM_PVR_HEAP_OP_GET_STATIC_DATA_AREAS: {
-+ if (!pvr_heap->nr_static_data_areas) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if (copy_to_user(u64_to_user_ptr(args->data),
-+ pvr_heap->static_data_areas,
-+ pvr_heap->nr_static_data_areas *
-+ sizeof(struct drm_pvr_static_data_area))) {
-+ err = -EFAULT;
-+ goto err_out;
-+ }
-+ break;
-+ }
-+
-+ default:
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+ }
-+
-+ /* Always write the number of heaps, regardless of whether a data pointer was provided. */
-+ args->nr_heaps = pvr_get_nr_heaps(pvr_dev);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_heap_contains_range() - Determine if a given heap contains the specified
-+ * device-virtual address range.
-+ * @heap: Target heap.
-+ * @start: Inclusive start of the target range.
-+ * @end: Inclusive end of the target range.
-+ *
-+ * It is an error to call this function with values of @start and @end that do
-+ * not satisfy the condition @start <= @end.
-+ *
-+ * Return:
-+ * * %true iff @heap completely contains the range specified by @start and
-+ * @end, or
-+ * * %false otherwise.
-+ */
-+static __always_inline bool
-+pvr_heap_contains_range(const struct pvr_heap *pvr_heap, u64 start, u64 end)
-+{
-+ return pvr_heap->base <= start && end < pvr_heap->base + pvr_heap->size;
-+}
-+
-+/**
-+ * pvr_find_heap_containing() - Find a heap which contains the specified
-+ * device-virtual address range.
-+ * @pvr_dev: Target PowerVR device.
-+ * @start: Start of the target range.
-+ * @size: Size of the target range.
-+ *
-+ * Return:
-+ * * A pointer to a constant instance of struct drm_pvr_heap representing the
-+ * heap containing the entire range specified by @start and @size on
-+ * success, or
-+ * * %NULL if no such heap exists.
-+ */
-+const struct pvr_heap *
-+pvr_find_heap_containing(struct pvr_device *pvr_dev, u64 start, u64 size)
-+{
-+ u32 heap_id;
-+ u64 end;
-+
-+ if (check_add_overflow(start, size - 1, &end))
-+ return NULL;
-+
-+ /*
-+ * There are no optimizations to be made here, since there are no
-+ * guarantees about the order of &pvr_heaps. Iterate over the entire
-+ * array.
-+ */
-+ for (heap_id = 0; heap_id < ARRAY_SIZE(pvr_heaps); ++heap_id) {
-+ /*
-+ * If the target range is completely within this heap, break
-+ * out and return the heap.
-+ */
-+ if (pvr_heap_contains_range(&pvr_heaps[heap_id], start, end))
-+ return &pvr_heaps[heap_id];
-+ }
-+
-+ /* Search quirky heaps only if the associated quirk is present. */
-+ if (PVR_HAS_QUIRK(pvr_dev, 63142) &&
-+ pvr_heap_contains_range(&rgnhdr_heap, start, end)) {
-+ return &rgnhdr_heap;
-+ }
-+
-+ /* If we make it this far, we've exhausted all possible heaps. */
-+ return NULL;
-+}
-+
-+/**
-+ * pvr_vm_find_gem_object() - Look up a buffer object from a given virtual
-+ * device address.
-+ * @vm_ctx: [IN] Target VM context.
-+ * @device_addr: [IN] Virtual device address at the start of the required
-+ * object.
-+ * @mapped_offset_out: [OUT] Pointer to location to write offset of the start
-+ * of the mapped region within the buffer object. May be %NULL if this
-+ * information is not required.
-+ * @mapped_size_out: [OUT] Pointer to location to write size of the mapped
-+ * region. May be %NULL if this information is not required.
-+ *
-+ * If successful, a reference will be taken on the buffer object. The caller
-+ * must drop the reference with pvr_gem_object_put().
-+ *
-+ * Return:
-+ * * The PowerVR buffer object mapped at @device_addr if one exists, or
-+ * * -%EINVAL otherwise.
-+ */
-+struct pvr_gem_object *
-+pvr_vm_find_gem_object(struct pvr_vm_context *vm_ctx, u64 device_addr,
-+ u64 *mapped_offset_out, u64 *mapped_size_out)
-+{
-+ struct pvr_vm_mapping *mapping;
-+ struct pvr_gem_object *pvr_obj;
-+ int err;
-+
-+ mutex_lock(&vm_ctx->lock);
-+
-+ mapping = pvr_vm_mapping_tree_iter_first(&vm_ctx->mappings,
-+ device_addr, 0);
-+ if (!mapping || pvr_vm_mapping_start(mapping) != device_addr) {
-+ err = -EINVAL;
-+ goto err_unlock;
-+ }
-+
-+ pvr_obj = mapping->pvr_obj;
-+ if (WARN_ON(!pvr_obj)) {
-+ err = -EINVAL;
-+ goto err_unlock;
-+ }
-+
-+ pvr_gem_object_get(pvr_obj);
-+
-+ if (mapped_offset_out)
-+ *mapped_offset_out = mapping->pvr_obj_offset;
-+ if (mapped_size_out)
-+ *mapped_size_out = pvr_vm_mapping_size(mapping);
-+
-+ mutex_unlock(&vm_ctx->lock);
-+
-+ return pvr_obj;
-+
-+err_unlock:
-+ mutex_unlock(&vm_ctx->lock);
-+
-+ return ERR_PTR(err);
-+}
-+
-+/**
-+ * pvr_vm_fw_mem_context_create() - Create firmware memory context
-+ * @pvr_file: Pointer to pvr_file structure.
-+ *
-+ * Returns:
-+ * * 0 on success, or
-+ * * Any error returned by pvr_gem_create_and_map_fw_object().
-+ */
-+int pvr_vm_fw_mem_context_create(struct pvr_file *pvr_file)
-+{
-+ struct pvr_vm_context *vm_ctx = pvr_file->user_vm_ctx;
-+ struct rogue_fwif_fwmemcontext *fw_mem_ctx;
-+ int err;
-+
-+ fw_mem_ctx = pvr_gem_create_and_map_fw_object(pvr_file->pvr_dev, sizeof(*fw_mem_ctx),
-+ PVR_BO_FW_FLAGS_DEVICE_UNCACHED | DRM_PVR_BO_CREATE_ZEROED,
-+ &pvr_file->fw_mem_ctx_obj);
-+ if (IS_ERR(fw_mem_ctx)) {
-+ err = PTR_ERR(fw_mem_ctx);
-+ goto err_out;
-+ }
-+
-+ fw_mem_ctx->pc_dev_paddr = vm_ctx->root_table.backing_page.dma_addr;
-+ fw_mem_ctx->page_cat_base_reg_id = ROGUE_FW_BIF_INVALID_PCREG;
-+
-+ pvr_fw_object_vunmap(pvr_file->fw_mem_ctx_obj, fw_mem_ctx, true);
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_fw_mem_context_destroy() - Destroy firmware memory context
-+ * @pvr_file: Pointer to pvr_file structure.
-+ */
-+void pvr_vm_fw_mem_context_destroy(struct pvr_file *pvr_file)
-+{
-+ pvr_fw_object_release(pvr_file->fw_mem_ctx_obj);
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_vm.h b/drivers/gpu/drm/imagination/pvr_vm.h
-new file mode 100644
-index 000000000000..6a97e3c754d7
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_vm.h
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_VM_H__
-+#define __PVR_VM_H__
-+
-+#include "pvr_rogue_mmu_defs.h"
-+
-+#include <uapi/drm/pvr_drm.h>
-+
-+#include <linux/bitops.h>
-+#include <linux/types.h>
-+
-+/* Forward declaration from "pvr_device.h" */
-+struct pvr_device;
-+struct pvr_file;
-+
-+/* Forward declaration from "pvr_gem.h" */
-+struct pvr_gem_object;
-+
-+/* Forward declaration of opaque handle from "pvr_vm.c" */
-+struct pvr_vm_context;
-+
-+/* Forward declaration from uapi/drm/pvr_drm.h. */
-+struct drm_pvr_ioctl_get_heap_info_args;
-+
-+/**
-+ * DOC: Public API
-+ *
-+ * The public-facing API of our virtual memory management is exposed as 7
-+ * functions (well, 6 and a helper) along with an opaque handle type.
-+ *
-+ * The opaque handle is &struct pvr_vm_context. This holds a "global state",
-+ * including a complete page table tree structure. You do not need to consider
-+ * this internal structure (or anything else in &struct pvr_vm_context) when
-+ * using this API; it is designed to operate as a black box.
-+ *
-+ * Usage
-+ * -----
-+ * Begin by calling pvr_vm_create_context() to obtain a VM context. It is bound
-+ * to a PowerVR device (&struct pvr_device) and holds a reference to it. This
-+ * binding is immutable.
-+ *
-+ * Once you're finished with a VM context, call pvr_vm_destroy_context() to
-+ * release it. This should be done before freeing or otherwise releasing the
-+ * PowerVR device to which the VM context is bound.
-+ *
-+ * It is an error to destroy a VM context while it still contains valid
-+ * allocation ranges (and by extension, memory mappings). The operation will
-+ * succeed, but memory will be leaked and kernel warnings will be printed.
-+ *
-+ * Mappings
-+ * ~~~~~~~~
-+ * Physical memory is exposed to the device via **mappings**. Mappings may
-+ * never overlap, although any given region of physical memory may be
-+ * referenced by multiple mappings.
-+ *
-+ * Use pvr_vm_map() to create a mapping, providing a &struct pvr_gem_object
-+ * holding the physical memory to be mapped. The physical memory behind the
-+ * object does not have to be contiguous (it may be backed by a scatter-gather
-+ * table) but each contiguous "section" must be device page-aligned. This
-+ * restriction is checked by pvr_vm_map(), which returns -%EINVAL if the check
-+ * fails.
-+ *
-+ * If only part of the &struct pvr_gem_object must be mapped, use
-+ * pvr_vm_map_partial() instead. In addition to the parameters accepted by
-+ * pvr_vm_map(), this also takes an offset into the the object and the size of
-+ * the mapping to be created. The restrictions regarding alignment on
-+ * pvr_vm_map() also apply here, with the exception that only the region of the
-+ * object within the bounds specified by the offset and size must satisfy them.
-+ * These are checked by pvr_vm_map_partial(), along with the offset and size
-+ * values to ensure that the region they specify falls entirely within the
-+ * bounds of the provided object.
-+ *
-+ * Both of these mapping functions call pvr_gem_object_get() to ensure the
-+ * underlying physical memory is not freed until *after* the mapping is
-+ * released.
-+ *
-+ * Mappings are tracked internally so that it is theoretically impossible to
-+ * accidentally create overlapping mappings. No handle is returned after a
-+ * mapping operation succeeds; callers should instead use the start device
-+ * virtual address of the mapping as its handle.
-+ *
-+ * When mapped memory is no longer required by the device, it should be
-+ * unmapped using pvr_vm_unmap(). In addition to making the memory inaccessible
-+ * to the device, this will call pvr_gem_object_put() to release the
-+ * underlying physical memory. If the mapping held the last reference, the
-+ * physical memory will automatically be freed. Attempting to unmap an invalid
-+ * mapping (or one that has already been unmapped) will result in an -%ENOENT
-+ * error.
-+ */
-+/**
-+ * DOC: Public API (constants)
-+ *
-+ * .. c:macro:: PVR_DEVICE_PAGE_SIZE
-+ *
-+ * Fixed page size referenced by leaf nodes in the page table tree
-+ * structure.
-+ *
-+ * .. admonition:: Future work
-+ *
-+ * The PowerVR device MMU supports multiple page sizes (6 of them!).
-+ * While we currently only support 4KiB pages (the smallest), this
-+ * constant (as well as the two derived values %PVR_DEVICE_PAGE_SHIFT and
-+ * %PVR_DEVICE_PAGE_MASK) may have to become a lookup table at some point
-+ * to support some or all of the additional page sizes.
-+ *
-+ * .. c:macro:: PVR_DEVICE_PAGE_SHIFT
-+ *
-+ * Shift value used to efficiently multiply or divide by
-+ * %PVR_DEVICE_PAGE_SIZE.
-+ *
-+ * .. c:macro:: PVR_DEVICE_PAGE_MASK
-+ *
-+ * Mask used to round a value down to the nearest multiple of
-+ * %PVR_DEVICE_PAGE_SIZE. When bitwise negated, it will indicate whether a
-+ * value is already a multiple of %PVR_DEVICE_PAGE_SIZE.
-+ */
-+
-+/* PVR_DEVICE_PAGE_SIZE determines the page size */
-+#define PVR_DEVICE_PAGE_SIZE (SZ_4K)
-+#define PVR_DEVICE_PAGE_SHIFT (__ffs(PVR_DEVICE_PAGE_SIZE))
-+#define PVR_DEVICE_PAGE_MASK (~(PVR_DEVICE_PAGE_SIZE - 1))
-+
-+struct pvr_heap {
-+ /** @id: Heap ID. */
-+ enum drm_pvr_heap_id id;
-+
-+ /** @flags: Flags for this heap. Currently always 0. */
-+ u32 flags;
-+
-+ /** @base: Base address of heap. */
-+ u64 base;
-+
-+ /** @size: Size of heap, in bytes. */
-+ u64 size;
-+
-+ /** @reserved_base: Base address of reserved area. */
-+ u64 reserved_base;
-+
-+ /**
-+ * @reserved_size: Size of reserved area, in bytes. May be 0 if this
-+ * heap has no reserved area.
-+ */
-+ u64 reserved_size;
-+
-+ /** @page_size_log2: Log2 of page size. */
-+ u32 page_size_log2;
-+
-+ /** @nr_static_data_areas: Number of static data areas in this heap. */
-+ u32 nr_static_data_areas;
-+
-+ /**
-+ * @static_data_areas: Pointer to description of static data areas in this heap. May be
-+ * %NULL if &nr_static_data_areas is 0.
-+ */
-+ const struct drm_pvr_static_data_area *static_data_areas;
-+};
-+
-+/* Functions defined in pvr_vm.c */
-+
-+bool pvr_device_addr_is_valid(u64 device_addr);
-+bool pvr_device_addr_and_size_are_valid(u64 device_addr, u64 size);
-+
-+struct pvr_vm_context *pvr_vm_create_context(struct pvr_device *pvr_dev);
-+void pvr_vm_destroy_context(struct pvr_vm_context *vm_ctx, bool enable_warnings);
-+
-+int pvr_vm_map(struct pvr_vm_context *vm_ctx, struct pvr_gem_object *pvr_obj,
-+ u64 device_addr);
-+int pvr_vm_map_partial(struct pvr_vm_context *vm_ctx,
-+ struct pvr_gem_object *pvr_obj, u64 pvr_obj_offset,
-+ u64 device_addr, u64 size);
-+int pvr_vm_unmap(struct pvr_vm_context *vm_ctx, u64 device_addr);
-+
-+dma_addr_t pvr_vm_get_page_catalogue_addr(struct pvr_vm_context *vm_ctx);
-+
-+int
-+pvr_get_heap_info(struct pvr_device *pvr_dev, struct drm_pvr_ioctl_get_heap_info_args *args);
-+
-+const struct pvr_heap *
-+pvr_find_heap_containing(struct pvr_device *pvr_dev, u64 addr, u64 size);
-+
-+struct pvr_gem_object *
-+pvr_vm_find_gem_object(struct pvr_vm_context *vm_ctx, u64 device_addr,
-+ u64 *mapped_offset_out, u64 *mapped_size_out);
-+int pvr_vm_fw_mem_context_create(struct pvr_file *pvr_file);
-+void pvr_vm_fw_mem_context_destroy(struct pvr_file *pvr_file);
-+
-+int
-+pvr_vm_mmu_flush(struct pvr_device *pvr_dev);
-+
-+#endif /* __PVR_VM_H__ */
-diff --git a/drivers/gpu/drm/imagination/pvr_vm_mips.c b/drivers/gpu/drm/imagination/pvr_vm_mips.c
-new file mode 100644
-index 000000000000..1b88b009e991
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_vm_mips.c
-@@ -0,0 +1,220 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#include "pvr_device.h"
-+#include "pvr_fw_mips.h"
-+#include "pvr_gem.h"
-+#include "pvr_rogue_mips.h"
-+#include "pvr_vm_mips.h"
-+
-+#include <linux/err.h>
-+#include <linux/slab.h>
-+#include <linux/types.h>
-+
-+/**
-+ * pvr_vm_mips_init() - Initialise MIPS FW pagetable
-+ * @pvr_dev: Target PowerVR device.
-+ *
-+ * Returns:
-+ * * 0 on success,
-+ * * -%EINVAL,
-+ * * Any error returned by pvr_gem_object_create(), or
-+ * * And error returned by pvr_gem_object_vmap().
-+ */
-+int
-+pvr_vm_mips_init(struct pvr_device *pvr_dev)
-+{
-+ u32 pt_size = 1 << ROGUE_MIPSFW_LOG2_PAGETABLE_SIZE_4K(pvr_dev);
-+ struct pvr_fw_mips_data *mips_data;
-+ u32 phys_bus_width;
-+ int err;
-+
-+ /* Page table size must be at most ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * 4k pages. */
-+ if (pt_size > ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * SZ_4K) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if (PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ mips_data = kzalloc(sizeof(*mips_data), GFP_KERNEL);
-+ if (!mips_data) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ mips_data->pt_obj = pvr_gem_object_create(pvr_dev, pt_size,
-+ DRM_PVR_BO_DEVICE_PM_FW_PROTECT |
-+ DRM_PVR_BO_CREATE_ZEROED);
-+ if (IS_ERR(mips_data->pt_obj)) {
-+ err = PTR_ERR(mips_data->pt_obj);
-+ goto err_kfree;
-+ }
-+
-+ mips_data->pt = pvr_gem_object_vmap(mips_data->pt_obj, false);
-+ if (IS_ERR(mips_data->pt)) {
-+ err = PTR_ERR(mips_data->pt);
-+ goto err_put_obj;
-+ }
-+
-+ mips_data->pfn_mask = (phys_bus_width > 32) ? ROGUE_MIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT :
-+ ROGUE_MIPSFW_ENTRYLO_PFN_MASK;
-+
-+ mips_data->cache_policy = (phys_bus_width > 32) ? ROGUE_MIPSFW_CACHED_POLICY_ABOVE_32BIT :
-+ ROGUE_MIPSFW_CACHED_POLICY;
-+
-+ pvr_dev->fw_data.mips_data = mips_data;
-+
-+ return 0;
-+
-+err_put_obj:
-+ pvr_gem_object_put(mips_data->pt_obj);
-+
-+err_kfree:
-+ kfree(mips_data);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_mips_fini() - Release MIPS FW pagetable
-+ * @pvr_dev: Target PowerVR device.
-+ */
-+void
-+pvr_vm_mips_fini(struct pvr_device *pvr_dev)
-+{
-+ struct pvr_fw_mips_data *mips_data = pvr_dev->fw_data.mips_data;
-+
-+ pvr_gem_object_vunmap(mips_data->pt_obj, mips_data->pt, false);
-+ pvr_gem_object_put(mips_data->pt_obj);
-+ kfree(mips_data);
-+ pvr_dev->fw_data.mips_data = NULL;
-+}
-+
-+static u32
-+get_mips_pte_flags(bool read, bool write, int cache_policy)
-+{
-+ u32 flags = 0;
-+
-+ if (read && write) /* Read/write. */
-+ flags |= ROGUE_MIPSFW_ENTRYLO_DIRTY_EN;
-+ else if (write) /* Write only. */
-+ flags |= ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_EN;
-+ else
-+ WARN_ON(!read);
-+
-+ flags |= cache_policy << ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_SHIFT;
-+
-+ flags |= ROGUE_MIPSFW_ENTRYLO_VALID_EN | ROGUE_MIPSFW_ENTRYLO_GLOBAL_EN;
-+
-+ return flags;
-+}
-+
-+/**
-+ * pvr_vm_mips_map() - Map a FW object into MIPS address space
-+ * @pvr_dev: Target PowerVR device.
-+ * @fw_obj: FW object to map.
-+ *
-+ * Returns:
-+ * * 0 on success,
-+ * * -%EINVAL if object does not reside within FW address space, or
-+ * * Any error returned by pvr_fw_get_dma_addr().
-+ */
-+int
-+pvr_vm_mips_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
-+{
-+ struct pvr_fw_mips_data *mips_data = pvr_dev->fw_data.mips_data;
-+ struct pvr_gem_object *pvr_obj = &fw_obj->base;
-+ u64 start = fw_obj->fw_mm_node.start;
-+ u64 size = fw_obj->fw_mm_node.size;
-+ u64 end;
-+ u32 cache_policy;
-+ u32 pte_flags;
-+ u32 start_pfn;
-+ u32 end_pfn;
-+ u32 pfn;
-+ int err;
-+
-+ if (check_add_overflow(start, size - 1, &end)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ if (start < ROGUE_FW_HEAP_BASE ||
-+ start >= ROGUE_FW_HEAP_BASE + pvr_dev->fw_heap_info.raw_size ||
-+ end < ROGUE_FW_HEAP_BASE ||
-+ end >= ROGUE_FW_HEAP_BASE + pvr_dev->fw_heap_info.raw_size ||
-+ (start & ROGUE_MIPSFW_PAGE_MASK_4K) ||
-+ ((end + 1) & ROGUE_MIPSFW_PAGE_MASK_4K)) {
-+ err = -EINVAL;
-+ goto err_out;
-+ }
-+
-+ start_pfn = (start & pvr_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
-+ end_pfn = (end & pvr_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
-+
-+ if (pvr_obj->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
-+ cache_policy = ROGUE_MIPSFW_UNCACHED_CACHE_POLICY;
-+ else
-+ cache_policy = mips_data->cache_policy;
-+
-+ pte_flags = get_mips_pte_flags(true, true, cache_policy);
-+
-+ for (pfn = start_pfn; pfn <= end_pfn; pfn++) {
-+ dma_addr_t dma_addr;
-+ u32 pte;
-+
-+ err = pvr_fw_get_dma_addr(fw_obj,
-+ (pfn - start_pfn) << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K,
-+ &dma_addr);
-+ if (err)
-+ goto err_unmap_pages;
-+
-+ pte = ((dma_addr >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
-+ << ROGUE_MIPSFW_ENTRYLO_PFN_SHIFT) & mips_data->pfn_mask;
-+ pte |= pte_flags;
-+
-+ WRITE_ONCE(mips_data->pt[pfn], pte);
-+ }
-+
-+ pvr_vm_mmu_flush(pvr_dev);
-+
-+ return 0;
-+
-+err_unmap_pages:
-+ for (; pfn >= start_pfn; pfn--)
-+ WRITE_ONCE(mips_data->pt[pfn], 0);
-+
-+ pvr_vm_mmu_flush(pvr_dev);
-+
-+err_out:
-+ return err;
-+}
-+
-+/**
-+ * pvr_vm_mips_unmap() - Unmap a FW object into MIPS address space
-+ * @pvr_dev: Target PowerVR device.
-+ * @fw_obj: FW object to unmap.
-+ */
-+void
-+pvr_vm_mips_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
-+{
-+ struct pvr_fw_mips_data *mips_data = pvr_dev->fw_data.mips_data;
-+ u64 start = fw_obj->fw_mm_node.start;
-+ u64 size = fw_obj->fw_mm_node.size;
-+ u64 end = start + size;
-+
-+ u32 start_pfn = (start & pvr_dev->fw_heap_info.offset_mask) >>
-+ ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
-+ u32 end_pfn = (end & pvr_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
-+ u32 pfn;
-+
-+ for (pfn = start_pfn; pfn < end_pfn; pfn++)
-+ WRITE_ONCE(mips_data->pt[pfn], 0);
-+
-+ pvr_vm_mmu_flush(pvr_dev);
-+}
-diff --git a/drivers/gpu/drm/imagination/pvr_vm_mips.h b/drivers/gpu/drm/imagination/pvr_vm_mips.h
-new file mode 100644
-index 000000000000..8d0926052520
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/pvr_vm_mips.h
-@@ -0,0 +1,22 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_VM_MIPS_H__
-+#define __PVR_VM_MIPS_H__
-+
-+/* Forward declaration from pvr_device.h. */
-+struct pvr_device;
-+
-+/* Forward declaration from pvr_gem.h. */
-+struct pvr_fw_object;
-+
-+int
-+pvr_vm_mips_init(struct pvr_device *pvr_dev);
-+void
-+pvr_vm_mips_fini(struct pvr_device *pvr_dev);
-+int
-+pvr_vm_mips_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj);
-+void
-+pvr_vm_mips_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj);
-+
-+#endif /* __PVR_VM_MIPS_H__ */
-diff --git a/drivers/gpu/drm/imagination/vendor/pvr_mt8173.c b/drivers/gpu/drm/imagination/vendor/pvr_mt8173.c
-new file mode 100644
-index 000000000000..864814e38059
---- /dev/null
-+++ b/drivers/gpu/drm/imagination/vendor/pvr_mt8173.c
-@@ -0,0 +1,121 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+/* Parts copyright (c) 2014 MediaTek Inc. */
-+#include "pvr_device.h"
-+#include "pvr_vendor.h"
-+
-+#include <drm/drm_print.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+/* Taken from img-rogue/mt8173/mt8173_mfgsys.c in ChromeOS kernel */
-+#define REG_MFG_AXI BIT(0)
-+#define REG_MFG_MEM BIT(1)
-+#define REG_MFG_G3D BIT(2)
-+#define REG_MFG_26M BIT(3)
-+#define REG_MFG_ALL (REG_MFG_AXI | REG_MFG_MEM | REG_MFG_G3D | REG_MFG_26M)
-+
-+#define REG_MFG_CG_STA 0x00
-+#define REG_MFG_CG_SET 0x04
-+#define REG_MFG_CG_CLR 0x08
-+
-+struct pvr_mt8173_data {
-+ void __iomem *regs;
-+};
-+
-+static int
-+mt8173_init(struct pvr_device *pvr_dev)
-+{
-+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
-+ struct platform_device *plat_dev = to_platform_device(drm_dev->dev);
-+ struct pvr_mt8173_data *mt8173_data;
-+ void __iomem *regs;
-+ int err;
-+
-+ mt8173_data = kzalloc(sizeof(*mt8173_data), GFP_KERNEL);
-+ if (!mt8173_data) {
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
-+
-+ regs = devm_platform_ioremap_resource(plat_dev, 1);
-+ if (IS_ERR(regs)) {
-+ err = PTR_ERR(regs);
-+ drm_err(drm_dev,
-+ "failed to ioremap mt8173 gpu registers (err=%d)\n",
-+ err);
-+ goto err_free;
-+ }
-+
-+ mt8173_data->regs = regs;
-+
-+ pvr_dev->vendor.data = mt8173_data;
-+
-+ return 0;
-+
-+err_free:
-+ kfree(mt8173_data);
-+
-+err_out:
-+ return err;
-+}
-+
-+static void
-+mt8173_fini(struct pvr_device *pvr_dev)
-+{
-+ struct pvr_mt8173_data *mt8173_data = pvr_dev->vendor.data;
-+
-+ kfree(mt8173_data);
-+ pvr_dev->vendor.data = NULL;
-+}
-+
-+static void
-+mtk_mfg_enable_hw_apm(struct pvr_mt8173_data *mt8173_data)
-+{
-+ /* Taken from img-rogue/mt8173/mt8173_mfgsys.c in ChromeOS kernel */
-+ writel(0x003c3d4d, mt8173_data->regs + 0x24);
-+ writel(0x4d45440b, mt8173_data->regs + 0x28);
-+ writel(0x7a710184, mt8173_data->regs + 0xe0);
-+ writel(0x835f6856, mt8173_data->regs + 0xe4);
-+ writel(0x002b0234, mt8173_data->regs + 0xe8);
-+ writel(0x80000000, mt8173_data->regs + 0xec);
-+ writel(0x08000000, mt8173_data->regs + 0xa0);
-+}
-+
-+static void
-+mtk_mfg_disable_hw_apm(struct pvr_mt8173_data *mt8173_data)
-+{
-+ /* Taken from img-rogue/mt8173/mt8173_mfgsys.c in ChromeOS kernel */
-+ writel(0x00, mt8173_data->regs + 0xec);
-+}
-+
-+static int
-+mt8173_power_enable(struct pvr_device *pvr_dev)
-+{
-+ struct pvr_mt8173_data *mt8173_data = pvr_dev->vendor.data;
-+
-+ /* Taken from img-rogue/mt8173/mt8173_mfgsys.c in ChromeOS kernel */
-+ writel(REG_MFG_ALL, mt8173_data->regs + REG_MFG_CG_CLR);
-+ mtk_mfg_enable_hw_apm(mt8173_data);
-+
-+ return 0;
-+}
-+
-+static int
-+mt8173_power_disable(struct pvr_device *pvr_dev)
-+{
-+ struct pvr_mt8173_data *mt8173_data = pvr_dev->vendor.data;
-+
-+ mtk_mfg_disable_hw_apm(mt8173_data);
-+
-+ return 0;
-+}
-+
-+const struct pvr_vendor_callbacks pvr_mt8173_callbacks = {
-+ .init = mt8173_init,
-+ .fini = mt8173_fini,
-+ .power_enable = mt8173_power_enable,
-+ .power_disable = mt8173_power_disable,
-+};
-diff --git a/include/uapi/drm/pvr_drm.h b/include/uapi/drm/pvr_drm.h
-new file mode 100644
-index 000000000000..d3ecd5b6fcd3
---- /dev/null
-+++ b/include/uapi/drm/pvr_drm.h
-@@ -0,0 +1,1524 @@
-+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note OR MIT */
-+/* Copyright (c) 2022 Imagination Technologies Ltd. */
-+
-+#ifndef __PVR_DRM_H__
-+#define __PVR_DRM_H__
-+
-+#include "drm.h"
-+
-+#include <linux/const.h>
-+#include <linux/types.h>
-+
-+/**
-+ * DOC: PowerVR UAPI
-+ *
-+ * TODO
-+ */
-+
-+#if defined(__cplusplus)
-+extern "C" {
-+#endif
-+
-+/**
-+ * DOC: IOCTLS
-+ *
-+ * The PowerVR IOCTL argument structs have a few limitations in place, in
-+ * addition to the standard kernel restrictions:
-+ *
-+ * - All members must be type-aligned.
-+ * - The overall struct must be padded to 64-bit alignment.
-+ * - Explicit padding is almost always required. This takes the form of
-+ * &_padding_x members of sufficient size to pad to the next power-of-two
-+ * alignment, where x is the offset into the struct in hexadecimal. Arrays
-+ * are never used for alignment. Padding fields must be zeroed; this is
-+ * always checked.
-+ * - Unions may only appear as the last member of a struct.
-+ * - Individual union members may grow in the future. The space between the
-+ * end of a union member and the end of its containing union is considered
-+ * "implicit padding" and must be zeroed. This is always checked.
-+ */
-+
-+/* clang-format off */
-+/**
-+ * PVR_IOCTL() - Build a PowerVR IOCTL number
-+ * @_ioctl: An incrementing id for this IOCTL. Added to %DRM_COMMAND_BASE.
-+ * @_mode: Must be one of DRM_IO{R,W,WR}.
-+ * @_data: The type of the args struct passed by this IOCTL.
-+ *
-+ * The struct referred to by @_data must have a &drm_pvr_ioctl_ prefix and an
-+ * &_args suffix. They are therefore omitted from @_data.
-+ *
-+ * This should only be used to build the constants described below; it should
-+ * never be used to call an IOCTL directly.
-+ *
-+ * Return:
-+ * An IOCTL number to be passed to ioctl() from userspace.
-+ */
-+#define PVR_IOCTL(_ioctl, _mode, _data) \
-+ _mode(DRM_COMMAND_BASE + (_ioctl), struct drm_pvr_ioctl_##_data##_args)
-+
-+#define DRM_IOCTL_PVR_CREATE_BO PVR_IOCTL(0x00, DRM_IOWR, create_bo)
-+#define DRM_IOCTL_PVR_GET_BO_MMAP_OFFSET PVR_IOCTL(0x01, DRM_IOWR, get_bo_mmap_offset)
-+#define DRM_IOCTL_PVR_GET_PARAM PVR_IOCTL(0x02, DRM_IOWR, get_param)
-+#define DRM_IOCTL_PVR_CREATE_CONTEXT PVR_IOCTL(0x03, DRM_IOWR, create_context)
-+#define DRM_IOCTL_PVR_DESTROY_CONTEXT PVR_IOCTL(0x04, DRM_IOW, destroy_context)
-+#define DRM_IOCTL_PVR_CREATE_OBJECT PVR_IOCTL(0x05, DRM_IOWR, create_object)
-+#define DRM_IOCTL_PVR_DESTROY_OBJECT PVR_IOCTL(0x06, DRM_IOW, destroy_object)
-+#define DRM_IOCTL_PVR_GET_HEAP_INFO PVR_IOCTL(0x07, DRM_IOWR, get_heap_info)
-+#define DRM_IOCTL_PVR_VM_OP PVR_IOCTL(0x08, DRM_IOW, vm_op)
-+#define DRM_IOCTL_PVR_SUBMIT_JOB PVR_IOCTL(0x09, DRM_IOW, submit_job)
-+/* clang-format on */
-+
-+/**
-+ * DOC: IOCTL CREATE_BO
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * DOC: Flags for CREATE_BO
-+ *
-+ * The &drm_pvr_ioctl_create_bo_args.flags field is 64 bits wide and consists
-+ * of three groups of flags: creation, device mapping and CPU mapping.
-+ *
-+ * We use "device" to refer to the GPU here because of the ambiguity between
-+ * CPU and GPU in some fonts.
-+ *
-+ * Creation options
-+ * These use the prefix DRM_PVR_BO_CREATE_.
-+ *
-+ * :ZEROED: Require the allocated buffer to be zeroed before returning. Note
-+ * that this is an active operation, and is never zero cost. Unless it is
-+ * explicitly required, this option should not be set.
-+ *
-+ * Device mapping options
-+ * These use the prefix DRM_PVR_BO_DEVICE_.
-+ *
-+ * :BYPASS_CACHE: There are very few situations where this flag is useful.
-+ * By default, the device flushes its memory caches after every job.
-+ * :PM_FW_PROTECT: Specify that only the Parameter Manager (PM) and/or
-+ * firmware processor should be allowed to access this memory when mapped
-+ * to the device. It is not valid to specify this flag with
-+ * CPU_ALLOW_USERSPACE_ACCESS.
-+ *
-+ * CPU mapping options
-+ * These use the prefix DRM_PVR_BO_CPU_.
-+ *
-+ * :ALLOW_USERSPACE_ACCESS: Allow userspace to map and access the contents
-+ * of this memory. It is not valid to specify this flag with
-+ * DEVICE_PM_FW_PROTECT.
-+ */
-+#define DRM_PVR_BO_DEVICE_BYPASS_CACHE _BITULL(0)
-+#define DRM_PVR_BO_DEVICE_PM_FW_PROTECT _BITULL(1)
-+#define DRM_PVR_BO_CPU_ALLOW_USERSPACE_ACCESS _BITULL(2)
-+#define DRM_PVR_BO_CREATE_ZEROED _BITULL(3)
-+/* Bits 4..63 are reserved. */
-+
-+/**
-+ * struct drm_pvr_ioctl_create_bo_args - Arguments for %DRM_IOCTL_PVR_CREATE_BO
-+ */
-+struct drm_pvr_ioctl_create_bo_args {
-+ /**
-+ * @size: [IN/OUT] Unaligned size of buffer object to create. On
-+ * return, this will be populated with the actual aligned size of the
-+ * new buffer.
-+ */
-+ __u64 size;
-+
-+ /**
-+ * @handle: [OUT] GEM handle of the new buffer object for use in
-+ * userspace.
-+ */
-+ __u32 handle;
-+
-+ /** @_padding_c: Reserved. This field must be zeroed. */
-+ __u32 _padding_c;
-+
-+ /**
-+ * @flags: [IN] Options which will affect the behaviour of this
-+ * creation operation and future mapping operations on the created
-+ * object. This field must be a valid combination of DRM_PVR_BO_*
-+ * values, with all bits marked as reserved set to zero.
-+ */
-+ __u64 flags;
-+};
-+
-+/**
-+ * DOC: IOCTL GET_BO_MMAP_OFFSET
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * struct drm_pvr_ioctl_get_bo_mmap_offset_args - Arguments for
-+ * %DRM_IOCTL_PVR_GET_BO_MMAP_OFFSET
-+ *
-+ * Like other DRM drivers, the "mmap" IOCTL doesn't actually map any memory.
-+ * Instead, it allocates a fake offset which refers to the specified buffer
-+ * object. This offset can be used with a real mmap call on the DRM device
-+ * itself.
-+ */
-+struct drm_pvr_ioctl_get_bo_mmap_offset_args {
-+ /** @handle: [IN] GEM handle of the buffer object to be mapped. */
-+ __u32 handle;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /** @offset: [OUT] Fake offset to use in the real mmap call. */
-+ __u64 offset;
-+};
-+
-+/**
-+ * DOC: IOCTL GET_PARAM
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * enum drm_pvr_param - Arguments for &drm_pvr_ioctl_get_param_args.param
-+ */
-+enum drm_pvr_param {
-+ /** @DRM_PVR_PARAM_INVALID: Invalid parameter. Do not use. */
-+ DRM_PVR_PARAM_INVALID = 0,
-+
-+ /**
-+ * @DRM_PVR_PARAM_GPU_ID: GPU identifier.
-+ *
-+ * For all currently supported GPUs this is the BVNC encoded as a 64-bit
-+ * value as follows:
-+ *
-+ * +--------+--------+--------+-------+
-+ * | 63..48 | 47..32 | 31..16 | 15..0 |
-+ * +========+========+========+=======+
-+ * | B | V | N | C |
-+ * +--------+--------+--------+-------+
-+ */
-+ DRM_PVR_PARAM_GPU_ID,
-+
-+ /**
-+ * @DRM_PVR_PARAM_HWRT_NUM_GEOMDATAS: Number of geom data arguments
-+ * required when creating a HWRT dataset.
-+ */
-+ DRM_PVR_PARAM_HWRT_NUM_GEOMDATAS,
-+
-+ /**
-+ * @DRM_PVR_PARAM_HWRT_NUM_RTDATAS: Number of RT data arguments
-+ * required when creating a HWRT dataset.
-+ */
-+ DRM_PVR_PARAM_HWRT_NUM_RTDATAS,
-+
-+ /**
-+ * @DRM_PVR_PARAM_HWRT_NUM_FREELISTS: Number of free list data
-+ * arguments required when creating a HWRT dataset.
-+ */
-+ DRM_PVR_PARAM_HWRT_NUM_FREELISTS,
-+
-+ /**
-+ * @DRM_PVR_PARAM_FW_VERSION: Version number of GPU firmware.
-+ *
-+ * This is encoded with the major version number in the upper 32 bits of
-+ * the output value, and the minor version number in the lower 32 bits.
-+ */
-+ DRM_PVR_PARAM_FW_VERSION,
-+
-+ DRM_PVR_PARAM_MAX /* non-ABI */
-+};
-+
-+/**
-+ * struct drm_pvr_ioctl_get_param_args - Arguments for %DRM_IOCTL_PVR_GET_PARAM
-+ */
-+struct drm_pvr_ioctl_get_param_args {
-+ /**
-+ * @param: [IN] Parameter for which a value should be returned.
-+ *
-+ * This must be one of the values defined by &enum drm_pvr_param, with
-+ * the exception of %DRM_PVR_PARAM_INVALID.
-+ */
-+ __u32 param;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /** @value: [OUT] Value for @param. */
-+ __u64 value;
-+};
-+
-+/**
-+ * DOC: IOCTL CREATE_CONTEXT
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * enum drm_pvr_ctx_priority - Arguments for
-+ * &drm_pvr_ioctl_create_context_args.priority
-+ */
-+enum drm_pvr_ctx_priority {
-+ DRM_PVR_CTX_PRIORITY_LOW = -512,
-+ DRM_PVR_CTX_PRIORITY_NORMAL = 0,
-+ /* A priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER. */
-+ DRM_PVR_CTX_PRIORITY_HIGH = 512,
-+};
-+
-+/**
-+ * enum drm_pvr_static_render_context_state_format - Arguments for
-+ * &drm_pvr_static_render_context_state.format
-+ */
-+enum drm_pvr_static_render_context_state_format {
-+ /** @DRM_PVR_SRCS_FORMAT_1: Format 1, used by firmware version 1.14. */
-+ DRM_PVR_SRCS_FORMAT_1 = 0,
-+};
-+
-+/**
-+ * struct drm_pvr_static_render_context_state - Static render context state
-+ * arguments for %DRM_IOCTL_PVR_CREATE_CONTEXT
-+ */
-+struct drm_pvr_static_render_context_state {
-+ /**
-+ * @format: [IN] Format of @data.
-+ *
-+ * This must be one of the values defined by
-+ * &enum drm_pvr_static_render_context_state_format.
-+ *
-+ * For firmware version 1.14, this is %DRM_PVR_SRCS_FORMAT_1.
-+ */
-+ __u32 format;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /** @data: [IN] Static render context state data. */
-+ union {
-+ /**
-+ * @format_1: Static render context state data when @format ==
-+ * %DRM_PVR_SRCS_FORMAT_1.
-+ */
-+ struct {
-+ __u64 geom_reg_vdm_context_state_base_addr;
-+ __u64 geom_reg_vdm_context_state_resume_addr;
-+ __u64 geom_reg_ta_context_state_base_addr;
-+
-+ struct {
-+ __u64 geom_reg_vdm_context_store_task0;
-+ __u64 geom_reg_vdm_context_store_task1;
-+ __u64 geom_reg_vdm_context_store_task2;
-+
-+ __u64 geom_reg_vdm_context_resume_task0;
-+ __u64 geom_reg_vdm_context_resume_task1;
-+ __u64 geom_reg_vdm_context_resume_task2;
-+
-+ __u64 geom_reg_vdm_context_store_task3;
-+ __u64 geom_reg_vdm_context_store_task4;
-+
-+ __u64 geom_reg_vdm_context_resume_task3;
-+ __u64 geom_reg_vdm_context_resume_task4;
-+ } geom_state[2];
-+ } format_1;
-+ } data;
-+};
-+
-+/**
-+ * enum drm_pvr_static_compute_context_state_format - Arguments for
-+ * &drm_pvr_static_compute_context_state.format
-+ */
-+enum drm_pvr_static_compute_context_state_format {
-+ /** @DRM_PVR_SCCS_FORMAT_1: Format 1, used by firmware version 1.14. */
-+ DRM_PVR_SCCS_FORMAT_1 = 0,
-+};
-+
-+/**
-+ * struct drm_pvr_static_compute_context_state - Static compute context state
-+ * arguments for %DRM_IOCTL_PVR_CREATE_CONTEXT
-+ */
-+struct drm_pvr_static_compute_context_state {
-+ /**
-+ * @format: [IN] Format of @data.
-+ *
-+ * This must be one of the values defined by
-+ * &enum drm_pvr_static_compute_context_state_format.
-+ *
-+ * For firmware version 1.14, this is %DRM_PVR_SCCS_FORMAT_1.
-+ */
-+ __u32 format;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /** @data: [IN] Static compute context state data. */
-+ union {
-+ /**
-+ * @format_1: Static compute context state data when @format ==
-+ * %DRM_PVR_SCCS_FORMAT_1.
-+ */
-+ struct {
-+ __u64 cdmreg_cdm_context_state_base_addr;
-+ __u64 cdmreg_cdm_context_pds0;
-+ __u64 cdmreg_cdm_context_pds1;
-+ __u64 cdmreg_cdm_terminate_pds;
-+ __u64 cdmreg_cdm_terminate_pds1;
-+ __u64 cdmreg_cdm_resume_pds0;
-+ __u64 cdmreg_cdm_context_pds0_b;
-+ __u64 cdmreg_cdm_resume_pds0_b;
-+ } format_1;
-+ } data;
-+};
-+
-+/**
-+ * struct drm_pvr_ioctl_create_render_context_args - Arguments for
-+ * drm_pvr_ioctl_create_context_args.args.render.
-+ */
-+struct drm_pvr_ioctl_create_render_context_args {
-+ /**
-+ * @vdm_callstack_addr: [IN] Address for initial TA call stack pointer.
-+ */
-+ __u64 vdm_callstack_addr;
-+
-+ /**
-+ * @static_render_context_state: [IN] Pointer to static render context
-+ * state to copy to new context.
-+ */
-+ __u64 static_render_context_state;
-+};
-+
-+/**
-+ * struct drm_pvr_ioctl_create_compute_context_args - Arguments for %DRM_PVR_CTX_COMPUTE.
-+ */
-+struct drm_pvr_ioctl_create_compute_context_args {
-+ /**
-+ * @static_compute_context_state: [IN] Pointer to static compute context state to copy to
-+ * new context.
-+ */
-+ __u64 static_compute_context_state;
-+};
-+
-+/**
-+ * enum drm_pvr_reset_framework_format - Arguments for
-+ * &drm_pvr_reset_framework.format
-+ */
-+enum drm_pvr_reset_framework_format {
-+ /** @DRM_PVR_RF_FORMAT_CDM_1: Format 1, used by firmware 1.14. */
-+ DRM_PVR_RF_FORMAT_CDM_1 = 0,
-+};
-+
-+/**
-+ * struct drm_pvr_reset_framework - Reset framework arguments for
-+ * %DRM_IOCTL_PVR_CREATE_CONTEXT
-+ */
-+struct drm_pvr_reset_framework {
-+ /**
-+ * @flags: [IN] Flags for reset framework.
-+ *
-+ * This is currently unused and must be set to 0.
-+ */
-+ __u32 flags;
-+
-+ /**
-+ * @format: [IN] Format of @data.
-+ *
-+ * This must be one of the values defined by
-+ * &enum drm_pvr_reset_framework_format.
-+ *
-+ * For firmware version 1.14, this is %DRM_PVR_RF_FORMAT_CDM_1.
-+ */
-+ __u32 format;
-+
-+ /** @data: [IN] Reset framework data. */
-+ union {
-+ /**
-+ * @cdm_format_1: Reset framework data when @format ==
-+ * %DRM_PVR_RF_FORMAT_CDM_1.
-+ */
-+ struct {
-+ /**
-+ * @cdm_ctrl_stream_base: Base address of CDM control
-+ * stream
-+ */
-+ __u64 cdm_ctrl_stream_base;
-+ } cdm_format_1;
-+ } data;
-+};
-+
-+/* clang-format off */
-+
-+/**
-+ * enum drm_pvr_ctx_type - Arguments for
-+ * &drm_pvr_ioctl_create_context_args.type
-+ */
-+enum drm_pvr_ctx_type {
-+ /**
-+ * @DRM_PVR_CTX_TYPE_RENDER: Render context. Use &struct
-+ * drm_pvr_ioctl_create_render_context_args for context creation arguments.
-+ */
-+ DRM_PVR_CTX_TYPE_RENDER = 0,
-+
-+ /**
-+ * @DRM_PVR_CTX_TYPE_COMPUTE: Compute context. Use &struct
-+ * drm_pvr_ioctl_create_compute_context_args for context creation arguments.
-+ */
-+ DRM_PVR_CTX_TYPE_COMPUTE,
-+};
-+
-+/* clang-format on */
-+
-+/**
-+ * struct drm_pvr_ioctl_create_context_args - Arguments for
-+ * %DRM_IOCTL_PVR_CREATE_CONTEXT
-+ */
-+struct drm_pvr_ioctl_create_context_args {
-+ /**
-+ * @type: [IN] Type of context to create.
-+ *
-+ * This must be one of the values defined by &enum drm_pvr_ctx_type.
-+ */
-+ __u32 type;
-+
-+ /** @flags: [IN] Flags for context. */
-+ __u32 flags;
-+
-+ /**
-+ * @reset_framework_registers: [IN] Pointer to reset framework
-+ * registers.
-+ *
-+ * May be 0 to indicate no reset framework.
-+ */
-+ __u64 reset_framework_registers;
-+
-+ /**
-+ * @priority: [IN] Priority of new context.
-+ *
-+ * This must be one of the values defined by &enum drm_pvr_ctx_priority.
-+ */
-+ __s32 priority;
-+
-+ /** @handle: [OUT] Handle for new context. */
-+ __u32 handle;
-+
-+ /** @data: [IN] User pointer to context type specific arguments. */
-+ __u64 data;
-+};
-+
-+/**
-+ * DOC: IOCTL DESTROY_CONTEXT
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * struct drm_pvr_ioctl_destroy_context_args - Arguments for
-+ * %DRM_IOCTL_PVR_DESTROY_CONTEXT
-+ */
-+struct drm_pvr_ioctl_destroy_context_args {
-+ /**
-+ * @handle: [IN] Handle for context to be destroyed.
-+ */
-+ __u32 handle;
-+};
-+
-+/**
-+ * DOC: IOCTL CREATE_OBJECT
-+ *
-+ * TODO
-+ */
-+
-+/* clang-format off */
-+
-+/**
-+ * enum drm_pvr_object_type - Arguments for
-+ * &drm_pvr_ioctl_create_object_args.type
-+ */
-+enum drm_pvr_object_type {
-+ /**
-+ * @DRM_PVR_OBJECT_TYPE_FREE_LIST: Free list object. Use &struct
-+ * drm_pvr_ioctl_create_free_list_args for object creation arguments.
-+ */
-+ DRM_PVR_OBJECT_TYPE_FREE_LIST = 0,
-+ /**
-+ * @DRM_PVR_OBJECT_TYPE_HWRT_DATASET: HWRT data set. Use &struct
-+ * drm_pvr_ioctl_create_hwrt_dataset_args for object creation arguments.
-+ */
-+ DRM_PVR_OBJECT_TYPE_HWRT_DATASET,
-+
-+ DRM_PVR_OBJECT_TYPE_MAX /* non-ABI */
-+};
-+
-+/* clang-format on */
-+
-+/**
-+ * struct drm_pvr_ioctl_create_free_list_args - Arguments for
-+ * %DRM_PVR_OBJECT_TYPE_FREE_LIST
-+ *
-+ * Free list arguments have the following constraints :
-+ *
-+ * - &max_num_pages must be greater than zero.
-+ * - &grow_threshold must be between 0 and 100.
-+ * - &grow_num_pages must be less than or equal to &max_num_pages.
-+ * - &initial_num_pages, &max_num_pages and &grow_num_pages must be multiples
-+ * of 4.
-+ *
-+ * When &grow_num_pages is 0 :
-+ * - &initial_num_pages must be equal to &max_num_pages
-+ *
-+ * When &grow_num_pages is non-zero :
-+ * - &initial_num_pages must be less than &max_num_pages.
-+ */
-+struct drm_pvr_ioctl_create_free_list_args {
-+ /**
-+ * @free_list_gpu_addr: [IN] Address of GPU mapping of buffer object
-+ * containing memory to be used by free list.
-+ *
-+ * The mapped region of the buffer object must be at least
-+ * @max_num_pages * sizeof(__u32).
-+ *
-+ * The buffer object must have been created with
-+ * %DRM_PVR_BO_DEVICE_PM_FW_PROTECT set and
-+ * %DRM_PVR_BO_CPU_ALLOW_USERSPACE_ACCESS not set.
-+ */
-+ __u64 free_list_gpu_addr;
-+
-+ /** @initial_num_pages: [IN] Pages initially allocated to free list. */
-+ __u32 initial_num_pages;
-+
-+ /** @max_num_pages: [IN] Maximum number of pages in free list. */
-+ __u32 max_num_pages;
-+
-+ /** @grow_num_pages: [IN] Pages to grow free list by per request. */
-+ __u32 grow_num_pages;
-+
-+ /**
-+ * @grow_threshold: [IN] Percentage of FL memory used that should
-+ * trigger a new grow request.
-+ */
-+ __u32 grow_threshold;
-+};
-+
-+struct create_hwrt_geom_data_args {
-+ /** @tail_ptrs_dev_addr: [IN] Tail pointers GPU virtual address. */
-+ __u64 tail_ptrs_dev_addr;
-+
-+ /** @vheap_table_dev_addr: [IN] VHEAP table GPU virtual address. */
-+ __u64 vheap_table_dev_addr;
-+
-+ /** @rtc_dev_addr: [IN] Render Target Cache virtual address. */
-+ __u64 rtc_dev_addr;
-+};
-+
-+struct create_hwrt_rt_data_args {
-+ /** @pm_mlist_dev_addr: [IN] PM MLIST GPU virtual address. */
-+ __u64 pm_mlist_dev_addr;
-+
-+ /** @macrotile_array_dev_addr: [IN] Macrotile array GPU virtual address. */
-+ __u64 macrotile_array_dev_addr;
-+
-+ /** @region_header_dev_addr: [IN] Region header GPU virtual address. */
-+ __u64 region_header_dev_addr;
-+};
-+
-+struct create_hwrt_free_list_args {
-+ /** @free_list_handle: [IN] Free list object handle. */
-+ __u32 free_list_handle;
-+};
-+
-+struct drm_pvr_ioctl_create_hwrt_dataset_args {
-+ /**
-+ * @geom_data_args: [IN] User pointer to one or more &struct
-+ * create_hwrt_geom_data_args.
-+ *
-+ * Number of &struct create_hwrt_geom_data_args must be equal to
-+ * &num_geom_datas.
-+ */
-+ __u64 geom_data_args;
-+
-+ /**
-+ * @rt_data_args: [IN] User pointer to one or more &struct
-+ * create_hwrt_rt_data_args.
-+ *
-+ * Number of &struct create_hwrt_rt_data_args must be equal to
-+ * &num_rt_datas.
-+ */
-+ __u64 rt_data_args;
-+
-+ /**
-+ * @free_list_args: [IN] User pointer to one or more &struct
-+ * create_hwrt_free_list_args.
-+ *
-+ * Number of &struct create_hwrt_free_list_args must be equal to
-+ * &num_free_lists.
-+ */
-+ __u64 free_list_args;
-+
-+ /**
-+ * @num_geom_datas: [IN] Number of geom data arguments.
-+ *
-+ * This should be equal to the value returned for
-+ * %DRM_PVR_PARAM_HWRT_NUM_GEOMDATAS by %DRM_IOCTL_PVR_GET_PARAM.
-+ */
-+ __u32 num_geom_datas;
-+
-+ /**
-+ * @num_rt_datas: [IN] Number of rt data arguments.
-+ *
-+ * This should be equal to the value returned for
-+ * %DRM_PVR_PARAM_HWRT_NUM_RTDATAS by %DRM_IOCTL_PVR_GET_PARAM.
-+ */
-+ __u32 num_rt_datas;
-+
-+ /**
-+ * @num_free_lists: [IN] Number of free list arguments.
-+ *
-+ * This should be equal to the value returned for
-+ * %DRM_PVR_PARAM_HWRT_NUM_FREELISTS by %DRM_IOCTL_PVR_GET_PARAM.
-+ */
-+ __u32 num_free_lists;
-+
-+ /** @mtile_stride: [IN] Macrotile stride. */
-+ __u32 mtile_stride;
-+
-+ /** @region_header_size: [IN] Region header size. */
-+ __u64 region_header_size;
-+
-+ /** @flipped_multi_sample_control: [IN] Flipped multi sample control. */
-+ __u64 flipped_multi_sample_control;
-+
-+ /** @multi_sample_control: [IN] Multi sample control. */
-+ __u64 multi_sample_control;
-+
-+ /** @screen_pixel_max: [IN] Maximum screen size. */
-+ __u32 screen_pixel_max;
-+
-+ /** @te_aa: [IN] TE anti-aliasing. */
-+ __u32 te_aa;
-+
-+ /** @te_mtile: [IN] TE macrotile boundaries. */
-+ __u32 te_mtile[2];
-+
-+ /** @te_screen_size: [IN] TE screen size. */
-+ __u32 te_screen_size;
-+
-+ /** @tpc_size: [IN] Tail Pointer Cache size */
-+ __u32 tpc_size;
-+
-+ /** @tpc_stride: [IN] Tail Pointer Cache stride */
-+ __u32 tpc_stride;
-+
-+ /** @isp_merge_lower_x: [IN] Lower X coefficient for triangle merging. */
-+ __u32 isp_merge_lower_x;
-+
-+ /** @isp_merge_lower_y: [IN] Lower Y coefficient for triangle merging. */
-+ __u32 isp_merge_lower_y;
-+
-+ /** @isp_merge_scale_x: [IN] Scale X coefficient for triangle merging. */
-+ __u32 isp_merge_scale_x;
-+
-+ /** @isp_merge_scale_y: [IN] Scale Y coefficient for triangle merging. */
-+ __u32 isp_merge_scale_y;
-+
-+ /** @isp_merge_upper_x: [IN] Upper X coefficient for triangle merging. */
-+ __u32 isp_merge_upper_x;
-+
-+ /** @isp_merge_upper_y: [IN] Upper Y coefficient for triangle merging. */
-+ __u32 isp_merge_upper_y;
-+
-+ /** @isp_mtile_size: [IN] Macrotile size. */
-+ __u32 isp_mtile_size;
-+
-+ /** @max_rts: [IN] Maximum Render Targets. */
-+ __u16 max_rts;
-+
-+ /** @_padding_7a: Reserved. This field must be zeroed. */
-+ __u16 _padding_7a;
-+
-+ /** @_padding_7c: Reserved. This field must be zeroed. */
-+ __u32 _padding_7c;
-+};
-+
-+/**
-+ * struct drm_pvr_ioctl_create_object_args - Arguments for
-+ * %DRM_IOCTL_PVR_CREATE_OBJECT
-+ */
-+struct drm_pvr_ioctl_create_object_args {
-+ /**
-+ * @type: [IN] Type of object to create.
-+ *
-+ * This must be one of the values defined by &enum drm_pvr_object_type.
-+ */
-+ __u32 type;
-+
-+ /**
-+ * @handle: [OUT] Handle for created object.
-+ */
-+ __u32 handle;
-+
-+ /** @data: [IN] User pointer to object type specific arguments. */
-+ __u64 data;
-+};
-+
-+/**
-+ * DOC: IOCTL DESTROY_OBJECT
-+ *
-+ * TODO
-+ */
-+
-+/**
-+ * struct drm_pvr_ioctl_destroy_object_args - Arguments for
-+ * %DRM_IOCTL_PVR_DESTROY_OBJECT
-+ */
-+struct drm_pvr_ioctl_destroy_object_args {
-+ /**
-+ * @handle: [IN] Handle for object to be destroyed.
-+ */
-+ __u32 handle;
-+};
-+
-+/**
-+ * DOC: IOCTL GET_HEAP_INFO
-+ *
-+ * TODO
-+ */
-+
-+enum drm_pvr_get_heap_info_op {
-+ /** @DRM_PVR_HEAP_OP_GET_HEAP_INFO: Get &struct drm_pvr_heap for the requested heap. */
-+ DRM_PVR_HEAP_OP_GET_HEAP_INFO = 0,
-+ /**
-+ * @DRM_PVR_HEAP_OP_GET_STATIC_DATA_AREAS: Get array of &struct drm_pvr_static_data_area
-+ * for the requested heap.
-+ */
-+ DRM_PVR_HEAP_OP_GET_STATIC_DATA_AREAS = 1,
-+};
-+
-+/**
-+ * enum drm_pvr_heap_id - Valid heap IDs returned by %DRM_IOCTL_PVR_GET_HEAP_INFO
-+ */
-+enum drm_pvr_heap_id {
-+ /** @DRM_PVR_HEAP_GENERAL: General purpose heap. */
-+ DRM_PVR_HEAP_GENERAL = 0,
-+ /** @DRM_PVR_HEAP_PDS_CODE_DATA: PDS code & data heap. */
-+ DRM_PVR_HEAP_PDS_CODE_DATA,
-+ /** @DRM_PVR_HEAP_USC_CODE: USC code heap. */
-+ DRM_PVR_HEAP_USC_CODE,
-+ /** @DRM_PVR_HEAP_RGNHDR: Region header heap. Only used if GPU has BRN63142. */
-+ DRM_PVR_HEAP_RGNHDR,
-+};
-+
-+struct drm_pvr_heap {
-+ /** @id: Heap ID. This must be one of the values defined by &enum drm_pvr_heap_id. */
-+ __u32 id;
-+
-+ /** @flags: Flags for this heap. Currently always 0. */
-+ __u32 flags;
-+
-+ /** @base: Base address of heap. */
-+ __u64 base;
-+
-+ /** @size: Size of heap, in bytes. */
-+ __u64 size;
-+
-+ /**
-+ * @reserved_base: Base address of reserved area.
-+ *
-+ * The reserved area must be located at the beginning or end of the heap. Any other location
-+ * is invalid and should be rejected by the caller.
-+ */
-+ __u64 reserved_base;
-+
-+ /**
-+ * @reserved_size: Size of reserved area, in bytes. May be 0 if this
-+ * heap has no reserved area.
-+ */
-+ __u64 reserved_size;
-+
-+ /** @page_size_log2: Log2 of page size. */
-+ __u32 page_size_log2;
-+
-+ /**
-+ * @nr_static_data_areas: Number of &struct drm_pvr_static_data_areas
-+ * returned for this heap by
-+ * %DRM_PVR_HEAP_OP_GET_STATIC_DATA_AREAS.
-+ */
-+ __u32 nr_static_data_areas;
-+};
-+
-+enum drm_pvr_static_data_area_id {
-+ DRM_PVR_STATIC_DATA_AREA_EOT = 0,
-+ DRM_PVR_STATIC_DATA_AREA_FENCE,
-+ DRM_PVR_STATIC_DATA_AREA_VDM_SYNC,
-+ DRM_PVR_STATIC_DATA_AREA_YUV_CSC,
-+
-+ DRM_PVR_STATIC_DATA_AREA_MAX /* non-ABI */
-+};
-+
-+struct drm_pvr_static_data_area {
-+ /** @id: ID of static data area. */
-+ __u32 id;
-+
-+ /** @size: Size of static data area. */
-+ __u32 size;
-+
-+ /** @offset: Offset of static data area from start of reserved area. */
-+ __u64 offset;
-+};
-+
-+/**
-+ * struct drm_pvr_ioctl_get_heap_info_args - Arguments for
-+ * %DRM_IOCTL_PVR_GET_HEAP_INFO
-+ */
-+struct drm_pvr_ioctl_get_heap_info_args {
-+ /**
-+ * @op: [IN] Operation to perform for this ioctl. Must be one of
-+ * &enum drm_pvr_get_heap_info_op.
-+ */
-+ __u32 op;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /**
-+ * @data: [IN] User pointer to memory that this ioctl writes to. This should point to
-+ * &struct drm_pvr_heap when &op == %DRM_PVR_HEAP_OP_GET_HEAP_INFO, or an
-+ * array of &struct drm_pvr_static_data_area, of size
-+ * %drm_pvr_heap.nr_static_data_areas elements, when &op ==
-+ * %DRM_PVR_HEAP_OP_GET_STATIC_DATA_AREAS.
-+ * May be zero, in which case this ioctl will not write any heap information.
-+ */
-+ __u64 data;
-+
-+ /** @heap_nr: [IN] Number of heap to get information for. Not used if @data is 0. */
-+ __u32 heap_nr;
-+
-+ /**
-+ * @nr_heaps: [OUT] Number of heaps provided by the driver.
-+ */
-+ __u32 nr_heaps;
-+};
-+
-+/**
-+ * DOC: IOCTL VM_OP
-+ *
-+ * This IOCTL groups together several operations performed on device-virtual
-+ * memory. For a list of the currently supported options, see the flags section
-+ * below.
-+ */
-+
-+/**
-+ * DOC: Flags for VM_OP
-+ *
-+ * Operations
-+ * ~~~~~~~~~~
-+ * .. c:macro:: DRM_PVR_VM_OP_MAP
-+ *
-+ * Map a PowerVR buffer object into device-virtual address space.
-+ *
-+ * .. c:macro:: DRM_PVR_VM_OP_UNMAP
-+ *
-+ * Unmap a PowerVR buffer object from device-virtual address space.
-+ */
-+#define DRM_PVR_VM_OP_MAP _UL(0)
-+#define DRM_PVR_VM_OP_UNMAP _UL(1)
-+
-+/**
-+ * struct drm_pvr_ioctl_vm_op_map_args - Additional arguments for
-+ * %DRM_IOCTL_PVR_VM_OP when &drm_pvr_ioctl_vm_op_args.operation is
-+ * %DRM_PVR_VM_OP_MAP.
-+ */
-+struct drm_pvr_ioctl_vm_op_map_args {
-+ /**
-+ * @device_addr: [IN] Requested device-virtual address for the mapping.
-+ * This must be non-zero and aligned to the device page size for the
-+ * heap containing the requested address. It is an error to specify an
-+ * address which is not contained within one of the heaps returned by
-+ * %DRM_IOCTL_PVR_GET_HEAP_INFO.
-+ */
-+ __u64 device_addr;
-+
-+ /** @flags: [IN] Flags which affect this mapping. Currently always 0. */
-+ __u32 flags;
-+
-+ /**
-+ * @handle: [IN] Handle of the target buffer object. This must be a
-+ * valid handle returned by %DRM_IOCTL_PVR_CREATE_BO.
-+ */
-+ __u32 handle;
-+
-+ /**
-+ * @offset: [IN] Offset into the target bo from which to begin the
-+ * mapping.
-+ */
-+ __u64 offset;
-+
-+ /**
-+ * @size: [IN] Size of the requested mapping. Must be aligned to
-+ * the device page size for the heap containing the requested address,
-+ * as well as the host page size. When added to @device_addr, the
-+ * result must not overflow the heap which contains @device_addr (i.e.
-+ * the range specified by @device_addr and @size must be completely
-+ * contained within a single heap specified by
-+ * %DRM_IOCTL_PVR_GET_HEAP_INFO).
-+ */
-+ __u64 size;
-+};
-+
-+/**
-+ * struct drm_pvr_ioctl_vm_op_unmap_args - Additional arguments for
-+ * %DRM_IOCTL_PVR_VM_OP when &drm_pvr_ioctl_vm_op_args.operation is
-+ * %DRM_PVR_VM_OP_UNMAP.
-+ */
-+struct drm_pvr_ioctl_vm_op_unmap_args {
-+ /**
-+ * @device_addr: [IN] Device-virtual address at the start of the target
-+ * mapping. This must be non-zero.
-+ */
-+ __u64 device_addr;
-+};
-+
-+/**
-+ * struct drm_pvr_ioctl_vm_op_args - Arguments for %DRM_IOCTL_PVR_VM_OP.
-+ */
-+struct drm_pvr_ioctl_vm_op_args {
-+ /**
-+ * @operation: [IN] Specific operation requested. Must be one of
-+ * DRM_PVR_VM_OP_*.
-+ */
-+ __u32 operation;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /** @data: [IN] Operation-specific arguments. */
-+ union {
-+ struct drm_pvr_ioctl_vm_op_map_args map;
-+ struct drm_pvr_ioctl_vm_op_unmap_args unmap;
-+ } data;
-+};
-+
-+/**
-+ * enum drm_pvr_cmd_geom_format - Arguments for
-+ * &drm_pvr_cmd_geom.format
-+ */
-+enum drm_pvr_cmd_geom_format {
-+ DRM_PVR_CMD_GEOM_FORMAT_1 = 0,
-+};
-+
-+/**
-+ * struct drm_pvr_geom_regs_format_1 - Configuration registers which need to be loaded by the
-+ * firmware before the VDM can be started
-+ *
-+ * Valid for %DRM_PVR_CMD_GEOM_FORMAT_1.
-+ */
-+struct drm_pvr_geom_regs_format_1 {
-+ __u64 vdm_ctrl_stream_base;
-+ __u64 tpu_border_colour_table;
-+ __u32 ppp_ctrl;
-+ __u32 te_psg;
-+ __u32 tpu;
-+ __u32 vdm_context_resume_task0_size;
-+ __u32 pds_ctrl;
-+ __u32 view_idx;
-+};
-+
-+/**
-+ * DOC: Flags for SUBMIT_JOB ioctl geometry command.
-+ *
-+ * Operations
-+ * ~~~~~~~~~~
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_GEOM_CMD_FIRST
-+ *
-+ * Indicates if this the first command to be issued for a render.
-+ *
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_GEOM_CMD_LAST
-+ *
-+ * Indicates if this the last command to be issued for a render.
-+ *
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_GEOM_CMD_SINGLE_CORE
-+ *
-+ * Forces to use single core in a multi core device.
-+ *
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_GEOM_CMD_FLAGS_MASK
-+ *
-+ * Logical OR of all the geometry cmd flags.
-+ */
-+#define DRM_PVR_SUBMIT_JOB_GEOM_CMD_FIRST _BITULL(0)
-+#define DRM_PVR_SUBMIT_JOB_GEOM_CMD_LAST _BITULL(1)
-+#define DRM_PVR_SUBMIT_JOB_GEOM_CMD_SINGLE_CORE _BITULL(3)
-+#define DRM_PVR_SUBMIT_JOB_GEOM_CMD_FLAGS_MASK \
-+ (DRM_PVR_SUBMIT_JOB_GEOM_CMD_FIRST | \
-+ DRM_PVR_SUBMIT_JOB_GEOM_CMD_LAST | \
-+ DRM_PVR_SUBMIT_JOB_GEOM_CMD_SINGLE_CORE)
-+
-+/**
-+ * struct drm_pvr_cmd_geom_format_1 - structure representing a geometry command, for format
-+ * %DRM_PVR_CMD_GEOM_FORMAT_1
-+ */
-+struct drm_pvr_cmd_geom_format_1 {
-+ /** @frame_num: Associated frame number. */
-+ __u32 frame_num;
-+
-+ /** @flags: command control flags. */
-+ __u32 flags;
-+
-+ /**
-+ * @regs: Configuration registers which need to be loaded by the
-+ * firmware before the VDM can be started.
-+ */
-+ struct drm_pvr_geom_regs_format_1 geom_regs;
-+};
-+
-+/**
-+ * struct drm_pvr_cmd_geom - structure representing a geometry command
-+ */
-+struct drm_pvr_cmd_geom {
-+ /**
-+ * @format: [IN] Format of @data.
-+ *
-+ * This must be one of the values defined by
-+ * &enum drm_pvr_cmd_geom_format.
-+ *
-+ * For firmware version 1.14, this is %DRM_PVR_CMD_GEOM_FORMAT_1.
-+ */
-+ __u32 format;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /** @data: [IN] Geometry job data. */
-+ union {
-+ /**
-+ * @cmd_frag_format_1: Command data when @format ==
-+ * %DRM_PVR_CMD_GEOM_FORMAT_1.
-+ */
-+ struct drm_pvr_cmd_geom_format_1 cmd_geom_format_1;
-+ } data;
-+};
-+
-+/**
-+ * enum drm_pvr_cmd_frag_format - Arguments for
-+ * &drm_pvr_cmd_frag.format
-+ */
-+enum drm_pvr_cmd_frag_format {
-+ DRM_PVR_CMD_FRAG_FORMAT_1 = 0,
-+};
-+
-+/**
-+ * struct drm_pvr_frag_regs_format_1 - Configuration registers which need to be loaded by the
-+ * firmware before the ISP can be started
-+ *
-+ * Valid for format %DRM_PVR_CMD_FRAG_FORMAT_1.
-+ */
-+struct drm_pvr_frag_regs_format_1 {
-+#define PVR_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U
-+ __u32 usc_clear_register[PVR_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL];
-+ __u32 usc_pixel_output_ctrl;
-+ __u32 isp_bgobjdepth;
-+ __u32 isp_bgobjvals;
-+ __u32 isp_aa;
-+ __u32 isp_ctl;
-+ __u32 tpu;
-+ __u32 event_pixel_pds_info;
-+ __u32 pixel_phantom;
-+ __u32 view_idx;
-+ __u32 event_pixel_pds_data;
-+ __u64 isp_scissor_base;
-+ __u64 isp_dbias_base;
-+ __u64 isp_oclqry_base;
-+ __u64 isp_zlsctl;
-+ __u64 isp_zload_store_base;
-+ __u64 isp_stencil_load_store_base;
-+ __u64 isp_zls_pixels;
-+#define PVR_PBE_WORDS_REQUIRED_FOR_RENDERS 2U
-+ __u64 pbe_word[8][PVR_PBE_WORDS_REQUIRED_FOR_RENDERS];
-+ __u64 tpu_border_colour_table;
-+ __u64 pds_bgnd[3];
-+ __u64 pds_pr_bgnd[3];
-+};
-+
-+/**
-+ * DOC: Flags for SUBMIT_JOB ioctl fragment command.
-+ *
-+ * Operations
-+ * ~~~~~~~~~~
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_FRAG_CMD_SINGLE_CORE
-+ *
-+ * Use single core in a multi core setup.
-+ *
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_FRAG_CMD_DEPTHBUFFER
-+ *
-+ * Indicates whether a depth buffer is present.
-+ *
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_FRAG_CMD_STENCILBUFFER
-+ *
-+ * Indicates whether a stencil buffer is present.
-+ *
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_FRAG_CMD_PREVENT_CDM_OVERLAP
-+ *
-+ * Disallow compute overlapped with this render.
-+ *
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_FRAG_CMD_FLAGS_MASK
-+ *
-+ * Logical OR of all the fragment cmd flags.
-+ */
-+#define DRM_PVR_SUBMIT_JOB_FRAG_CMD_SINGLE_CORE _BITULL(3)
-+#define DRM_PVR_SUBMIT_JOB_FRAG_CMD_DEPTHBUFFER _BITULL(7)
-+#define DRM_PVR_SUBMIT_JOB_FRAG_CMD_STENCILBUFFER _BITULL(8)
-+#define DRM_PVR_SUBMIT_JOB_FRAG_CMD_PREVENT_CDM_OVERLAP _BITULL(26)
-+#define DRM_PVR_SUBMIT_JOB_FRAG_CMD_FLAGS_MASK \
-+ (DRM_PVR_SUBMIT_JOB_FRAG_CMD_SINGLE_CORE | \
-+ DRM_PVR_SUBMIT_JOB_FRAG_CMD_DEPTHBUFFER | \
-+ DRM_PVR_SUBMIT_JOB_FRAG_CMD_STENCILBUFFER | \
-+ DRM_PVR_SUBMIT_JOB_FRAG_CMD_PREVENT_CDM_OVERLAP)
-+
-+/**
-+ * struct drm_pvr_cmd_frag_format_1 - structure representing a fragment command, for format
-+ * %DRM_PVR_CMD_FRAG_FORMAT_1
-+ */
-+struct drm_pvr_cmd_frag_format_1 {
-+ /** @frame_num: Associated frame number. */
-+ __u32 frame_num;
-+
-+ /** @flags: command control flags. */
-+ __u32 flags;
-+
-+ /** @zls_stride: Stride IN BYTES for Z-Buffer in case of RTAs. */
-+ __u32 zls_stride;
-+
-+ /** @sls_stride: Stride IN BYTES for S-Buffer in case of RTAs. */
-+ __u32 sls_stride;
-+
-+ /**
-+ * @regs: Configuration registers which need to be loaded by the
-+ * firmware before the ISP can be started.
-+ */
-+ struct drm_pvr_frag_regs_format_1 regs;
-+};
-+
-+/**
-+ * struct drm_pvr_cmd_frag - structure representing a fragment command
-+ */
-+struct drm_pvr_cmd_frag {
-+ /**
-+ * @format: [IN] Format of @data.
-+ *
-+ * This must be one of the values defined by
-+ * &enum drm_pvr_cmd_frag_format.
-+ *
-+ * For firmware version 1.14, this is %DRM_PVR_CMD_FRAG_FORMAT_1.
-+ */
-+ __u32 format;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /** @data: [IN] Fragment job data. */
-+ union {
-+ /**
-+ * @cmd_frag_format_1: Command data when @format ==
-+ * %DRM_PVR_CMD_FRAG_FORMAT_1.
-+ */
-+ struct drm_pvr_cmd_frag_format_1 cmd_frag_format_1;
-+ } data;
-+};
-+
-+/**
-+ * enum drm_pvr_cmd_compute_format - Arguments for
-+ * &drm_pvr_cmd_compute.format
-+ */
-+enum drm_pvr_cmd_compute_format {
-+ DRM_PVR_CMD_COMPUTE_FORMAT_1 = 0,
-+};
-+
-+/**
-+ * struct drm_pvr_compute_regs_format_1 - Configuration registers which need to be loaded by the
-+ * firmware before the CDM can be started
-+ *
-+ * Valid for format %DRM_PVR_CMD_COMPUTE_FORMAT_1.
-+ */
-+struct drm_pvr_compute_regs_format_1 {
-+ __u64 tpu_border_colour_table;
-+ __u64 cdm_item;
-+ __u64 compute_cluster;
-+ __u64 cdm_ctrl_stream_base;
-+ __u32 tpu;
-+ __u32 cdm_resume_pds1;
-+};
-+
-+/**
-+ * DOC: Flags for SUBMIT_JOB ioctl compute command.
-+ *
-+ * Operations
-+ * ~~~~~~~~~~
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_PREVENT_ALL_OVERLAP
-+ *
-+ * Disallow other jobs overlapped with this compute.
-+ *
-+ * .. c:macro:: DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_SINGLE_CORE
-+ *
-+ * Forces to use single core in a multi core device.
-+ */
-+#define DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_PREVENT_ALL_OVERLAP _BITULL(1)
-+#define DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_SINGLE_CORE _BITULL(5)
-+#define DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_FLAGS_MASK \
-+ (DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_PREVENT_ALL_OVERLAP | \
-+ DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_SINGLE_CORE)
-+
-+/**
-+ * struct drm_pvr_cmd_compute_format_1 - structure representing a compute command, for format
-+ * %DRM_PVR_CMD_COMPUTE_FORMAT_1
-+ */
-+struct drm_pvr_cmd_compute_format_1 {
-+ /** @frame_num: Associated frame number. */
-+ __u32 frame_num;
-+
-+ /** @flags: command control flags. */
-+ __u32 flags;
-+
-+ /**
-+ * @regs: Configuration registers which need to be loaded by the
-+ * firmware before the CDM can be started.
-+ */
-+ struct drm_pvr_compute_regs_format_1 regs;
-+};
-+
-+/**
-+ * struct drm_pvr_cmd_compute - structure representing a compute command
-+ */
-+struct drm_pvr_cmd_compute {
-+ /**
-+ * @format: [IN] Format of @data.
-+ *
-+ * This must be one of the values defined by
-+ * &enum drm_pvr_cmd_compute_format.
-+ *
-+ * For firmware version 1.14, this is %DRM_PVR_CMD_COMPUTE_FORMAT_1.
-+ */
-+ __u32 format;
-+
-+ /** @_padding_4: Reserved. This field must be zeroed. */
-+ __u32 _padding_4;
-+
-+ /** @data: [IN] Compute job data. */
-+ union {
-+ /**
-+ * @cmd_compute_format_1: Command data when @format ==
-+ * %DRM_PVR_CMD_COMPUTE_FORMAT_1.
-+ */
-+ struct drm_pvr_cmd_compute_format_1 cmd_compute_format_1;
-+ } data;
-+};
-+
-+/**
-+ * DOC: Flags for &struct drm_pvr_bo_ref.flags
-+ *
-+ * DRM_PVR_BO_REF_READ - This buffer object will be read by the device.
-+ *
-+ * DRM_PVR_BO_REF_WRITE - This buffer object will be written to by the device.
-+ */
-+#define DRM_PVR_BO_REF_READ _BITUL(0)
-+#define DRM_PVR_BO_REF_WRITE _BITUL(1)
-+
-+/**
-+ * struct drm_pvr_bo_ref - structure representing a DRM buffer object
-+ */
-+struct drm_pvr_bo_ref {
-+ /** @handle: DRM buffer object handle. */
-+ __u32 handle;
-+
-+ /** @flags: Flags for this buffer object. Must be a combination of %DRM_PVR_BO_REF_*. */
-+ __u32 flags;
-+};
-+
-+/*
-+ * struct drm_pvr_job_render_args - Arguments for %DRM_PVR_JOB_TYPE_RENDER
-+ */
-+struct drm_pvr_job_render_args {
-+ /**
-+ * @cmd_geom: [IN] Pointer to &struct drm_pvr_cmd_geom, representing geometry command.
-+ * May be zero.
-+ */
-+ __u64 cmd_geom;
-+
-+ /**
-+ * @cmd_frag: [IN] Pointer to &struct drm_pvr_cmd_frag, representing fragment command.
-+ * May be zero.
-+ */
-+ __u64 cmd_frag;
-+
-+ /**
-+ * @cmd_frag_pr: [IN] Pointer to &struct drm_pvr_cmd_frag, representing fragment PR command.
-+ * May be zero.
-+ */
-+ __u64 cmd_frag_pr;
-+
-+ /**
-+ * @in_syncobj_handles_geom: [IN] Pointer to array of drm_syncobj handles for
-+ * input fences for geometry job.
-+ *
-+ * This array must be &num_in_syncobj_handles_geom entries large.
-+ */
-+ __u64 in_syncobj_handles_geom;
-+
-+ /**
-+ * @in_syncobj_handles_frag: [IN] Pointer to array of drm_syncobj handles for
-+ * input fences for fragment job.
-+ *
-+ * This array must be &num_in_syncobj_handles_frag entries large.
-+ */
-+ __u64 in_syncobj_handles_frag;
-+
-+ /**
-+ * @in_syncobj_handles_frag_pr: [IN] Pointer to array of drm_syncobj handles for
-+ * input fences for fragment PR job.
-+ *
-+ * This array must be &num_in_syncobj_handles_frag_pr entries large.
-+ */
-+ __u64 in_syncobj_handles_frag_pr;
-+
-+ /**
-+ * @bo_handles: [IN] Pointer to array of struct drm_pvr_bo_ref.
-+ *
-+ * This array must be &num_bo_handles entries large.
-+ */
-+ __u64 bo_handles;
-+
-+ /**
-+ * @num_in_syncobj_handles_geom: [IN] Number of input syncobj handles for geometry job.
-+ */
-+ __u32 num_in_syncobj_handles_geom;
-+
-+ /**
-+ * @num_in_syncobj_handles_frag: [IN] Number of input syncobj handles for fragment job.
-+ */
-+ __u32 num_in_syncobj_handles_frag;
-+
-+ /**
-+ * @num_in_syncobj_handles_frag_pr: [IN] Number of input syncobj handles for fragment PR
-+ * job.
-+ */
-+ __u32 num_in_syncobj_handles_frag_pr;
-+
-+ /**
-+ * @num_bo_handles: [IN] Number of DRM Buffer Objects.
-+ *
-+ * This detemines the size of the array &bo_handles points to.
-+ */
-+ __u32 num_bo_handles;
-+
-+ /**
-+ * @out_syncobj_geom: [OUT] drm_syncobj handle for geometry output fence
-+ */
-+ __u32 out_syncobj_geom;
-+
-+ /**
-+ * @out_syncobj_frag: [OUT] drm_syncobj handle for fragment output fence
-+ */
-+ __u32 out_syncobj_frag;
-+
-+ /**
-+ * @hwrt_data_set_handle: [IN] Handle for HWRT data set.
-+ *
-+ * This must be a valid handle returned by %DRM_IOCTL_PVR_CREATE_OBJECT.
-+ */
-+ __u32 hwrt_data_set_handle;
-+
-+ /**
-+ * @hwrt_data_index: [IN] Index of HWRT data within data set.
-+ */
-+ __u32 hwrt_data_index;
-+
-+ /**
-+ * @msaa_scratch_buffer_handle: [IN] Handle for MSAA scratch buffer.
-+ */
-+ __u32 msaa_scratch_buffer_handle;
-+
-+ /**
-+ * @zs_buffer_handle: [IN] Handle for Z/stencil buffer.
-+ */
-+ __u32 zs_buffer_handle;
-+};
-+
-+/*
-+ * struct drm_pvr_job_compute_args - Arguments for %DRM_PVR_JOB_TYPE_COMPUTE
-+ */
-+struct drm_pvr_job_compute_args {
-+ /**
-+ * @cmd: [IN] Pointer to &struct drm_pvr_cmd_compute, representing compute command.
-+ */
-+ __u64 cmd;
-+
-+ /**
-+ * @in_syncobj_handles: [IN] Pointer to array of drm_syncobj handles for input fences.
-+ *
-+ * This array must be &num_in_syncobj_handles entries large.
-+ */
-+ __u64 in_syncobj_handles;
-+
-+ /**
-+ * @bo_handles: [IN] Pointer to array of struct drm_pvr_bo_ref.
-+ *
-+ * This array must be &num_bo_handles entries large.
-+ */
-+ __u64 bo_handles;
-+
-+ /**
-+ * @num_in_syncobj_handles: [IN] Number of input syncobj handles.
-+ */
-+ __u32 num_in_syncobj_handles;
-+
-+ /**
-+ * @num_bo_handles: [IN] Number of DRM Buffer Objects.
-+ *
-+ * This detemines the size of the array &bo_handles points to.
-+ */
-+ __u32 num_bo_handles;
-+
-+ /**
-+ * @out_syncobj: [OUT] drm_syncobj handle for output fence
-+ */
-+ __u32 out_syncobj;
-+
-+ /** @_padding_24: Reserved. This field must be zeroed. */
-+ __u32 _padding_24;
-+};
-+
-+/**
-+ * enum drm_pvr_job_type - Arguments for &drm_pvr_ioctl_submit_job_args.job_type
-+ */
-+enum drm_pvr_job_type {
-+ DRM_PVR_JOB_TYPE_RENDER = 0,
-+ DRM_PVR_JOB_TYPE_COMPUTE,
-+};
-+
-+/**
-+ * struct drm_pvr_ioctl_submit_job_args - Arguments for %DRM_IOCTL_PVR_SUBMIT_JOB
-+ */
-+struct drm_pvr_ioctl_submit_job_args {
-+
-+ /**
-+ * @job_type: [IN] Type of job being submitted
-+ *
-+ * This must be one of the values defined by &enum drm_pvr_job_type.
-+ */
-+ __u32 job_type;
-+
-+ /**
-+ * @context: [IN] Context handle.
-+ *
-+ * This must be a valid handle returned by %DRM_IOCTL_PVR_CREATE_CONTEXT. The type of
-+ * context must be compatible with the type of job being submitted.
-+ */
-+ __u32 context_handle;
-+
-+ /**
-+ * @ext_job_ref: [IN] Job reference.
-+ */
-+ __u32 ext_job_ref;
-+
-+ /** @_padding_c: Reserved. This field must be zeroed. */
-+ __u32 _padding_c;
-+
-+ /** @data: [IN] User pointer to job type specific arguments. */
-+ __u64 data;
-+};
-+
-+#if defined(__cplusplus)
-+}
-+#endif
-+
-+#endif /* __PVR_DRM_H__ */
---
-2.30.2
-
diff --git a/patches/drivers/powervr/0004-Documentation-gpu-imagination-Add-initial-PowerVR-dr.patch b/patches/drivers/powervr/0004-Documentation-gpu-imagination-Add-initial-PowerVR-dr.patch
deleted file mode 100644
index 19004febe57acbf12af5eb54e481df99441d8375..0000000000000000000000000000000000000000
--- a/patches/drivers/powervr/0004-Documentation-gpu-imagination-Add-initial-PowerVR-dr.patch
+++ /dev/null
@@ -1,387 +0,0 @@
-From afa72bcb756a0cb595aa7bd9a657b381c877de49 Mon Sep 17 00:00:00 2001
-From: Matt Coster <matt.coster@imgtec.com>
-Date: Wed, 1 Sep 2021 15:37:46 +0100
-Subject: [PATCH 4/4] Documentation: gpu/imagination: Add initial PowerVR
- driver documentation
-
-Signed-off-by: Matt Coster <matt.coster@imgtec.com>
----
- Documentation/gpu/drivers.rst | 2 +
- Documentation/gpu/imagination/index.rst | 12 ++
- Documentation/gpu/imagination/uapi.rst | 131 ++++++++++++
- .../gpu/imagination/virtual_memory.rst | 190 ++++++++++++++++++
- 4 files changed, 335 insertions(+)
- create mode 100644 Documentation/gpu/imagination/index.rst
- create mode 100644 Documentation/gpu/imagination/uapi.rst
- create mode 100644 Documentation/gpu/imagination/virtual_memory.rst
-
-diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst
-index 3a52f48215a3..5487deb218a3 100644
---- a/Documentation/gpu/drivers.rst
-+++ b/Documentation/gpu/drivers.rst
-@@ -3,9 +3,11 @@ GPU Driver Documentation
- ========================
-
- .. toctree::
-+ :maxdepth: 3
-
- amdgpu/index
- i915
-+ imagination/index
- mcde
- meson
- pl111
-diff --git a/Documentation/gpu/imagination/index.rst b/Documentation/gpu/imagination/index.rst
-new file mode 100644
-index 000000000000..7f25c8560822
---- /dev/null
-+++ b/Documentation/gpu/imagination/index.rst
-@@ -0,0 +1,12 @@
-+=======================================
-+drm/imagination PowerVR Graphics Driver
-+=======================================
-+
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_drv.c
-+ :doc: PowerVR Graphics Driver
-+
-+.. toctree::
-+ :maxdepth: 3
-+
-+ uapi
-+ virtual_memory
-diff --git a/Documentation/gpu/imagination/uapi.rst b/Documentation/gpu/imagination/uapi.rst
-new file mode 100644
-index 000000000000..5530e8103b64
---- /dev/null
-+++ b/Documentation/gpu/imagination/uapi.rst
-@@ -0,0 +1,131 @@
-+====
-+UAPI
-+====
-+The sources associated with this section can be found in ``pvr_drm.h``.
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: PowerVR UAPI
-+
-+
-+IOCTLS
-+======
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTLS
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: PVR_IOCTL
-+
-+CREATE_BO
-+---------
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL CREATE_BO
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_create_bo_args
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: Flags for CREATE_BO
-+
-+GET_BO_MMAP_OFFSET
-+------------------
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL GET_BO_MMAP_OFFSET
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_get_bo_mmap_offset_args
-+
-+GET_PARAM
-+---------
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL GET_PARAM
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_get_param_args
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_param
-+
-+CREATE_CONTEXT
-+--------------
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL CREATE_CONTEXT
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_create_context_args
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ctx_priority
-+ drm_pvr_ctx_type
-+ drm_pvr_static_render_context_state
-+ drm_pvr_static_render_context_state_format
-+ drm_pvr_reset_framework
-+ drm_pvr_reset_framework_format
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: Flags for CREATE_CONTEXT
-+
-+DESTROY_CONTEXT
-+---------------
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL DESTROY_CONTEXT
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_destroy_context_args
-+
-+CREATE_OBJECT
-+-------------
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL CREATE_OBJECT
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_create_object_args
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_object_type
-+ drm_pvr_ioctl_create_free_list_args
-+ create_hwrt_geom_data_args
-+ create_hwrt_rt_data_args
-+ create_hwrt_free_list_args
-+ drm_pvr_ioctl_create_hwrt_dataset_args
-+
-+DESTROY_OBJECT
-+--------------
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL DESTROY_OBJECT
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_destroy_object_args
-+
-+GET_HEAP_INFO
-+-------------
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL GET_HEAP_INFO
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_get_heap_info_args
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_heap_id
-+
-+VM_OP
-+-----
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: IOCTL VM_OP
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_vm_op_args
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :identifiers: drm_pvr_ioctl_vm_op_map_args drm_pvr_ioctl_vm_op_unmap_args
-+
-+.. kernel-doc:: include/uapi/drm/pvr_drm.h
-+ :doc: Flags for VM_OP
-+
-+Internal notes
-+==============
-+.. kernel-doc:: include/gpu/drm/imagination/pvr_device.h
-+ :doc: IOCTL validation helpers
-+
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_device.h
-+ :identifiers: PVR_STATIC_ASSERT_64BIT_ALIGNED PVR_IOCTL_UNION_PADDING_CHECK
-+ pvr_ioctl_union_padding_check
-diff --git a/Documentation/gpu/imagination/virtual_memory.rst b/Documentation/gpu/imagination/virtual_memory.rst
-new file mode 100644
-index 000000000000..17c434055d03
---- /dev/null
-+++ b/Documentation/gpu/imagination/virtual_memory.rst
-@@ -0,0 +1,190 @@
-+===========================
-+GPU Virtual Memory Handling
-+===========================
-+The sources associated with this section can be found in ``pvr_vm.c`` and
-+``pvr_vm.h``.
-+
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: PowerVR Virtual Memory Handling
-+
-+
-+Public API
-+==========
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.h
-+ :doc: Public API
-+
-+Types
-+-----
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.h
-+ :identifiers: pvr_vm_page_options
-+
-+Functions
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_vm_create_context pvr_vm_destroy_context
-+ pvr_vm_map pvr_vm_map_partial pvr_vm_unmap
-+
-+Helper functions
-+----------------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_device_addr_is_valid
-+
-+Constants
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.h
-+ :doc: Public API (constants)
-+
-+
-+VM backing pages
-+================
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: VM backing pages
-+
-+Types
-+-----
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_vm_backing_page
-+
-+Functions
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_vm_backing_page_init pvr_vm_backing_page_fini
-+ pvr_vm_backing_page_sync
-+
-+Constants
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: VM backing pages (constants)
-+
-+
-+Raw page tables
-+===============
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: Raw page tables
-+
-+Types
-+-----
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_l2_entry_raw pvr_page_table_l1_entry_raw
-+ pvr_page_table_l0_entry_raw
-+ pvr_page_table_l2_raw pvr_page_table_l1_raw
-+ pvr_page_table_l0_raw
-+
-+Functions
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_l2_entry_raw_is_valid
-+ pvr_page_table_l2_entry_raw_set
-+ pvr_page_table_l2_entry_raw_clear
-+ pvr_page_table_l1_entry_raw_is_valid
-+ pvr_page_table_l1_entry_raw_set
-+ pvr_page_table_l1_entry_raw_clear
-+ pvr_page_table_l0_entry_raw_is_valid
-+ pvr_page_table_l0_entry_raw_set
-+ pvr_page_table_l0_entry_raw_clear
-+
-+
-+Mirror page tables
-+==================
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: Mirror page tables
-+
-+Types
-+-----
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_l2 pvr_page_table_l1 pvr_page_table_l0
-+
-+Functions
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_l2_init pvr_page_table_l2_fini
-+ pvr_page_table_l2_sync pvr_page_table_l2_get_raw
-+ pvr_page_table_l2_get_entry_raw
-+ pvr_page_table_l2_insert pvr_page_table_l2_remove
-+ pvr_page_table_l1_init pvr_page_table_l1_fini
-+ pvr_page_table_l1_sync pvr_page_table_l1_get_raw
-+ pvr_page_table_l1_get_entry_raw
-+ pvr_page_table_l1_insert pvr_page_table_l1_remove
-+ pvr_page_table_l0_init pvr_page_table_l0_fini
-+ pvr_page_table_l0_sync pvr_page_table_l0_get_raw
-+ pvr_page_table_l0_get_entry_raw
-+ pvr_page_table_l0_insert pvr_page_table_l0_remove
-+
-+
-+Page table index utilities
-+==========================
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: Page table index utilities
-+
-+Functions
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_l2_idx pvr_page_table_l1_idx
-+ pvr_page_table_l0_idx
-+
-+Constants
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: Page table index utilities (constants)
-+
-+
-+High-level page table operations
-+================================
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: High-level page table operations
-+
-+Functions
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_l1_create pvr_page_table_l1_get_or_create
-+ pvr_page_table_l0_create pvr_page_table_l0_get_or_create
-+ pvr_page_create pvr_page_destroy
-+
-+Internal functions
-+------------------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_l1_create_unchecked __pvr_page_table_l1_destroy
-+ pvr_page_table_l0_create_unchecked __pvr_page_table_l0_destroy
-+
-+
-+Page table pointer
-+==================
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: Page table pointer
-+
-+Types
-+-----
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_ptr
-+
-+Functions
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_ptr_init pvr_page_table_ptr_fini
-+ pvr_page_table_ptr_next_page pvr_page_table_ptr_set
-+ pvr_page_table_ptr_require_sync pvr_page_table_ptr_copy
-+ pvr_page_table_ptr_sync pvr_page_table_ptr_sync_partial
-+
-+Internal functions
-+------------------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_page_table_ptr_sync_manual pvr_page_table_ptr_load_tables
-+
-+
-+Interval tree base implementation
-+=================================
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :doc: Interval tree base implementation
-+
-+Types
-+-----
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_vm_interval_tree_node
-+
-+Functions
-+---------
-+.. kernel-doc:: drivers/gpu/drm/imagination/pvr_vm.c
-+ :identifiers: pvr_vm_interval_tree_compute_last
-+ pvr_vm_interval_tree_node_start pvr_vm_interval_tree_node_size
-+ pvr_vm_interval_tree_node_last
-+ pvr_vm_interval_tree_insert
---
-2.30.2
-
diff --git a/patches/drivers/powervr/0005-MAINTAINERS-Add-entry-for-PowerVR-DRM-driver.patch b/patches/drivers/powervr/0005-MAINTAINERS-Add-entry-for-PowerVR-DRM-driver.patch
deleted file mode 100644
index f0e27ad59dbedd4aa2b9f66f64b5401da53d3f89..0000000000000000000000000000000000000000
--- a/patches/drivers/powervr/0005-MAINTAINERS-Add-entry-for-PowerVR-DRM-driver.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 59d4fe2d97f8e0845385465c8c64a780ed958181 Mon Sep 17 00:00:00 2001
-From: Frank Binns <frank.binns@imgtec.com>
-Date: Sun, 19 Dec 2021 19:13:42 +0000
-Subject: [PATCH 5/5] MAINTAINERS: Add entry for PowerVR DRM driver
-
-Signed-off-by: Frank Binns <frank.binns@imgtec.com>
----
- MAINTAINERS | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/MAINTAINERS b/MAINTAINERS
-index 05fd080b82f3..c754e9575f6a 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -9380,6 +9380,15 @@ IMGTEC IR DECODER DRIVER
- S: Orphan
- F: drivers/media/rc/img-ir/
-
-+IMGTEC POWERVR DRM DRIVER
-+M: Frank Binns <frank.binns@imgtec.com>
-+M: Sarah Walker <sarah.walker@imgtec.com>
-+R: Matt Coster <matt.coster@imgtec.com>
-+S: Supported
-+F: Documentation/gpu/imagination/
-+F: drivers/gpu/drm/imagination/
-+F: include/uapi/drm/pvr_drm.h
-+
- IMON SOUNDGRAPH USB IR RECEIVER
- M: Sean Young <sean@mess.org>
- L: linux-media@vger.kernel.org
---
-2.30.2
-
diff --git a/patches/drivers/serdev/0001-serdev-Add-serdev_device_id.patch b/patches/drivers/serdev/0001-serdev-Add-serdev_device_id.patch
deleted file mode 100644
index 5c7433e9903877b217d35413ac9ae97a4bc8f5ae..0000000000000000000000000000000000000000
--- a/patches/drivers/serdev/0001-serdev-Add-serdev_device_id.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From e52e4ccf1de73e51ac5fc27989f376c9725f9582 Mon Sep 17 00:00:00 2001
-From: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
-Date: Sun, 18 Oct 2020 05:26:39 +0530
-Subject: [RFC PATCH 1/5] serdev: Add serdev_device_id
-
-Currently,a serdev device driver can only be used with devices that are
-nodes of a device tree, or are part of the ACPI table.id_table will be
-used for devices that are not part of the device tree nor the ACPI table
-(example: device on greybus gbphy created uart).
-
-corresponding modalias field is introduced to name the driver to be
-used with the device, required device(s) that are neither described
-by device tree nor ACPI table.
-
-serdev_device_uevent is also extended for modalias devices.
-
-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
----
- drivers/tty/serdev/core.c | 41 ++++++++++++++++++++++++++++-----
- include/linux/mod_devicetable.h | 10 ++++++++
- include/linux/serdev.h | 3 +++
- 3 files changed, 48 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c
-index c5f0d936b003..01b248fdc264 100644
---- a/drivers/tty/serdev/core.c
-+++ b/drivers/tty/serdev/core.c
-@@ -27,12 +27,17 @@ static ssize_t modalias_show(struct device *dev,
- struct device_attribute *attr, char *buf)
- {
- int len;
-+ struct serdev_device *serdev = to_serdev_device(dev);
-
- len = acpi_device_modalias(dev, buf, PAGE_SIZE - 1);
- if (len != -ENODEV)
- return len;
-
-- return of_device_modalias(dev, buf, PAGE_SIZE);
-+ len = of_device_modalias(dev, buf, PAGE_SIZE);
-+ if (len != -ENODEV)
-+ return len;
-+
-+ return sprintf(buf, "%s%s\n", SERDEV_MODULE_PREFIX, serdev->modalias);
- }
- static DEVICE_ATTR_RO(modalias);
-
-@@ -45,14 +50,18 @@ ATTRIBUTE_GROUPS(serdev_device);
- static int serdev_device_uevent(struct device *dev, struct kobj_uevent_env *env)
- {
- int rc;
--
-- /* TODO: platform modalias */
-+ struct serdev_device *serdev = to_serdev_device(dev);
-
- rc = acpi_device_uevent_modalias(dev, env);
- if (rc != -ENODEV)
- return rc;
-
-- return of_device_uevent_modalias(dev, env);
-+ rc = of_device_uevent_modalias(dev, env);
-+ if (rc != -ENODEV)
-+ return rc;
-+
-+ return add_uevent_var(env, "MODALIAS=%s%s", SERDEV_MODULE_PREFIX,
-+ serdev->modalias);
- }
-
- static void serdev_device_release(struct device *dev)
-@@ -83,16 +92,36 @@ static const struct device_type serdev_ctrl_type = {
- .release = serdev_ctrl_release,
- };
-
-+static int serdev_match_id(const struct serdev_device_id *id,
-+ const struct serdev_device *sdev)
-+{
-+ while (id->name[0]) {
-+ if (!strcmp(sdev->modalias, id->name))
-+ return 1;
-+ id++;
-+ }
-+
-+ return 0;
-+}
-+
- static int serdev_device_match(struct device *dev, struct device_driver *drv)
- {
-+ const struct serdev_device *sdev = to_serdev_device(dev);
-+ const struct serdev_device_driver *sdrv = to_serdev_device_driver(drv);
-+
- if (!is_serdev_device(dev))
- return 0;
-
-- /* TODO: platform matching */
- if (acpi_driver_match_device(dev, drv))
- return 1;
-
-- return of_driver_match_device(dev, drv);
-+ if (of_driver_match_device(dev, drv))
-+ return 1;
-+
-+ if (sdrv->id_table)
-+ return serdev_match_id(sdrv->id_table, sdev);
-+
-+ return strcmp(sdev->modalias, drv->name) == 0;
- }
-
- /**
-diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
-index 5b08a473cdba..656353952da2 100644
---- a/include/linux/mod_devicetable.h
-+++ b/include/linux/mod_devicetable.h
-@@ -486,6 +486,16 @@ struct i3c_device_id {
- const void *data;
- };
-
-+/* serdev */
-+
-+#define SERDEV_NAME_SIZE 32
-+#define SERDEV_MODULE_PREFIX "serdev:"
-+
-+struct serdev_device_id {
-+ char name[SERDEV_NAME_SIZE];
-+ kernel_ulong_t driver_data;
-+};
-+
- /* spi */
-
- #define SPI_NAME_SIZE 32
-diff --git a/include/linux/serdev.h b/include/linux/serdev.h
-index 9f14f9c12ec4..0d9c90a250b0 100644
---- a/include/linux/serdev.h
-+++ b/include/linux/serdev.h
-@@ -7,6 +7,7 @@
-
- #include <linux/types.h>
- #include <linux/device.h>
-+#include <linux/mod_devicetable.h>
- #include <linux/termios.h>
- #include <linux/delay.h>
-
-@@ -45,6 +46,7 @@ struct serdev_device {
- const struct serdev_device_ops *ops;
- struct completion write_comp;
- struct mutex write_lock;
-+ char modalias[SERDEV_NAME_SIZE];
- };
-
- static inline struct serdev_device *to_serdev_device(struct device *d)
-@@ -63,6 +65,7 @@ struct serdev_device_driver {
- struct device_driver driver;
- int (*probe)(struct serdev_device *);
- void (*remove)(struct serdev_device *);
-+ const struct serdev_device_id *id_table;
- };
-
- static inline struct serdev_device_driver *to_serdev_device_driver(struct device_driver *d)
---
-2.25.1
-
diff --git a/patches/drivers/serdev/0002-file2alias-Support-for-serdev-devices.patch b/patches/drivers/serdev/0002-file2alias-Support-for-serdev-devices.patch
deleted file mode 100644
index ce00ea7b0c75e45fa046a3316c096bf43ce2f3fe..0000000000000000000000000000000000000000
--- a/patches/drivers/serdev/0002-file2alias-Support-for-serdev-devices.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 68d7f278257a1f0dc7533ee17c3f9d5da2455bb7 Mon Sep 17 00:00:00 2001
-From: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
-Date: Sun, 18 Oct 2020 05:46:10 +0530
-Subject: [RFC PATCH 2/5] file2alias: Support for serdev devices
-
-This patch allows file2alias to generate the proper module headers to
-support serdev modalias drivers.
-
-Eg:
-
-root@qt5022:~# modinfo serdev:ttydev | grep alias
-alias: serdev:ttydev_serdev
-alias: serdev:ttydev
-
-root@qt5022:~#
- cat /lib/modules/4.16.0-qtec-standard/modules.alias | grep serdev
-alias serdev:ttydev_serdev serdev_ttydev
-alias serdev:ttydev serdev_ttydev
-
-Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
----
- scripts/mod/devicetable-offsets.c | 3 +++
- scripts/mod/file2alias.c | 10 ++++++++++
- 2 files changed, 13 insertions(+)
-
-diff --git a/scripts/mod/devicetable-offsets.c b/scripts/mod/devicetable-offsets.c
-index 27007c18e754..732cd03e911d 100644
---- a/scripts/mod/devicetable-offsets.c
-+++ b/scripts/mod/devicetable-offsets.c
-@@ -152,6 +152,9 @@ int main(void)
- DEVID_FIELD(i3c_device_id, part_id);
- DEVID_FIELD(i3c_device_id, extra_info);
-
-+ DEVID(serdev_device_id);
-+ DEVID_FIELD(serdev_device_id, name);
-+
- DEVID(spi_device_id);
- DEVID_FIELD(spi_device_id, name);
-
-diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
-index 2417dd1dee33..540fee036d9d 100644
---- a/scripts/mod/file2alias.c
-+++ b/scripts/mod/file2alias.c
-@@ -947,6 +947,15 @@ static int do_spi_entry(const char *filename, void *symval,
- return 1;
- }
-
-+static int do_serdev_entry(const char *filename, void *symval,
-+ char *alias)
-+{
-+ DEF_FIELD_ADDR(symval, serdev_device_id, name);
-+ sprintf(alias, SERDEV_MODULE_PREFIX "%s", *name);
-+
-+ return 1;
-+}
-+
- static const struct dmifield {
- const char *prefix;
- int field;
-@@ -1420,6 +1429,7 @@ static const struct devtable devtable[] = {
- {"rpmsg", SIZE_rpmsg_device_id, do_rpmsg_entry},
- {"i2c", SIZE_i2c_device_id, do_i2c_entry},
- {"i3c", SIZE_i3c_device_id, do_i3c_entry},
-+ {"serdev", SIZE_serdev_device_id, do_serdev_entry},
- {"spi", SIZE_spi_device_id, do_spi_entry},
- {"dmi", SIZE_dmi_system_id, do_dmi_entry},
- {"platform", SIZE_platform_device_id, do_platform_entry},
---
-2.25.1
-
diff --git a/patches/drivers/serdev/0003-serdev-add-of_-helper-to-get-serdev-controller.patch b/patches/drivers/serdev/0003-serdev-add-of_-helper-to-get-serdev-controller.patch
deleted file mode 100644
index 20f0dc86d3d6dddca3320e77a06129642f83d20c..0000000000000000000000000000000000000000
--- a/patches/drivers/serdev/0003-serdev-add-of_-helper-to-get-serdev-controller.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 5a117e6146ac68b67a563a931c11664b52b0a158 Mon Sep 17 00:00:00 2001
-From: Vaishnav M A <vaishnav@beagleboard.org>
-Date: Sun, 18 Oct 2020 06:28:30 +0530
-Subject: [RFC PATCH 3/5] serdev: add of_ helper to get serdev controller
-
-add of_find_serdev_controller_by_node to obtain a
-serdev_controller from the device_node, which
-can help if the serdev_device is not described
-over device tree and instantiation of the device
-happens from a different driver, for the same purpose
-an option to not delete an empty serdev controller
-is added.
-
-Signed-off-by: Vaishnav M A <vaishnav@beagleboard.org>
----
- drivers/tty/serdev/core.c | 17 +++++++++++++++++
- include/linux/serdev.h | 2 ++
- 2 files changed, 19 insertions(+)
-
-diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c
-index 01b248fdc264..85977b36ed7f 100644
---- a/drivers/tty/serdev/core.c
-+++ b/drivers/tty/serdev/core.c
-@@ -582,6 +582,17 @@ static int of_serdev_register_devices(struct serdev_controller *ctrl)
- return 0;
- }
-
-+struct serdev_controller *of_find_serdev_controller_by_node(struct device_node *node)
-+{
-+ struct device *dev = bus_find_device_by_of_node(&serdev_bus_type, node);
-+
-+ if (!dev)
-+ return NULL;
-+
-+ return (dev->type == &serdev_ctrl_type) ? to_serdev_controller(dev) : NULL;
-+}
-+EXPORT_SYMBOL_GPL(of_find_serdev_controller_by_node);
-+
- #ifdef CONFIG_ACPI
-
- #define SERDEV_ACPI_MAX_SCAN_DEPTH 32
-@@ -779,6 +790,12 @@ int serdev_controller_add(struct serdev_controller *ctrl)
-
- pm_runtime_enable(&ctrl->dev);
-
-+ /* provide option to not delete a serdev controller without devices
-+ * if property is present
-+ */
-+ if (device_property_present(&ctrl->dev, "force-empty-serdev-controller"))
-+ return 0;
-+
- ret_of = of_serdev_register_devices(ctrl);
- ret_acpi = acpi_serdev_register_devices(ctrl);
- if (ret_of && ret_acpi) {
-diff --git a/include/linux/serdev.h b/include/linux/serdev.h
-index 0d9c90a250b0..2e1eb4d17e1b 100644
---- a/include/linux/serdev.h
-+++ b/include/linux/serdev.h
-@@ -115,6 +115,8 @@ static inline struct serdev_controller *to_serdev_controller(struct device *d)
- return container_of(d, struct serdev_controller, dev);
- }
-
-+struct serdev_controller *of_find_serdev_controller_by_node(struct device_node *node);
-+
- static inline void *serdev_device_get_drvdata(const struct serdev_device *serdev)
- {
- return dev_get_drvdata(&serdev->dev);
---
-2.25.1
-
diff --git a/patches/drivers/serdev/0004-gnss-ubx-add-MODULE_DEVICE_TABLE-serdev.patch b/patches/drivers/serdev/0004-gnss-ubx-add-MODULE_DEVICE_TABLE-serdev.patch
deleted file mode 100644
index 5a0badb4f5dfc3b390842c4b36b26ba23e784559..0000000000000000000000000000000000000000
--- a/patches/drivers/serdev/0004-gnss-ubx-add-MODULE_DEVICE_TABLE-serdev.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 625e5885def0997235d3153b60adb2e9044fc5c6 Mon Sep 17 00:00:00 2001
-From: Vaishnav M A <vaishnav@beagleboard.org>
-Date: Sun, 18 Oct 2020 06:58:01 +0530
-Subject: [RFC PATCH 4/5] gnss: ubx add MODULE_DEVICE_TABLE(serdev)
-
-export serdev id table to the module header.
-
-Signed-off-by: Vaishnav M A <vaishnav@beagleboard.org>
----
- drivers/gnss/ubx.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/drivers/gnss/ubx.c b/drivers/gnss/ubx.c
-index 7b05bc40532e..e50056cc4223 100644
---- a/drivers/gnss/ubx.c
-+++ b/drivers/gnss/ubx.c
-@@ -138,6 +138,14 @@ static const struct of_device_id ubx_of_match[] = {
- MODULE_DEVICE_TABLE(of, ubx_of_match);
- #endif
-
-+static const struct serdev_device_id ubx_serdev_id[] = {
-+ { "neo-6m", },
-+ { "neo-8", },
-+ { "neo-m8", },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(serdev, ubx_serdev_id);
-+
- static struct serdev_device_driver ubx_driver = {
- .driver = {
- .name = "gnss-ubx",
-@@ -146,6 +154,7 @@ static struct serdev_device_driver ubx_driver = {
- },
- .probe = ubx_probe,
- .remove = ubx_remove,
-+ .id_table = ubx_serdev_id,
- };
- module_serdev_device_driver(ubx_driver);
-
---
-2.25.1
-
diff --git a/patches/drivers/serdev/0005-gnss-change-of_property_read-to-device_property_read.patch b/patches/drivers/serdev/0005-gnss-change-of_property_read-to-device_property_read.patch
deleted file mode 100644
index 385e764736a571879d76e82a02a95efdc9a9ad4e..0000000000000000000000000000000000000000
--- a/patches/drivers/serdev/0005-gnss-change-of_property_read-to-device_property_read.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 960e964ca8b6bc8fa60fd9c6a6fd0163e82dad40 Mon Sep 17 00:00:00 2001
-From: Vaishnav M A <vaishnav@beagleboard.org>
-Date: Sun, 18 Oct 2020 07:03:27 +0530
-Subject: [RFC PATCH 5/5] gnss: change of_property_read to device_property_read
-
-change of_property_read_u32 for the current-speed property
-to use the device_property_read_u32 offered by the
-Unified Device Properties Interface, this helps
-passing the properties over a suitably populated struct
-property_entry.
-
-Signed-off-by: Vaishnav M A <vaishnav@beagleboard.org>
----
- drivers/gnss/serial.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/gnss/serial.c b/drivers/gnss/serial.c
-index def64b36d994..473faeea6aae 100644
---- a/drivers/gnss/serial.c
-+++ b/drivers/gnss/serial.c
-@@ -110,10 +110,9 @@ static int gnss_serial_set_power(struct gnss_serial *gserial,
- static int gnss_serial_parse_dt(struct serdev_device *serdev)
- {
- struct gnss_serial *gserial = serdev_device_get_drvdata(serdev);
-- struct device_node *node = serdev->dev.of_node;
- u32 speed = 4800;
-
-- of_property_read_u32(node, "current-speed", &speed);
-+ device_property_read_u32(&serdev->dev, "current-speed", &speed);
-
- gserial->speed = speed;
-
---
-2.25.1
-
diff --git a/patches/drivers/ti/serial/0001-quiet-8250_omap.c-use-pr_info-over-pr_err.patch b/patches/drivers/ti/serial/0001-quiet-8250_omap.c-use-pr_info-over-pr_err.patch
deleted file mode 100644
index 37f9b6bc8794899084bee5a2a44f8f336dbba505..0000000000000000000000000000000000000000
--- a/patches/drivers/ti/serial/0001-quiet-8250_omap.c-use-pr_info-over-pr_err.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From c7ce33cb5f4f0dab18ebb10584eec77e8f84fce5 Mon Sep 17 00:00:00 2001
-From: Robert Nelson <robertcnelson@gmail.com>
-Date: Thu, 16 Jul 2015 17:24:57 -0500
-Subject: [PATCH] quiet: 8250_omap.c use pr_info over pr_err
-
-Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
----
- drivers/tty/serial/8250/8250_omap.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c
-index 0a8316632d75..8ecebd14c655 100644
---- a/drivers/tty/serial/8250/8250_omap.c
-+++ b/drivers/tty/serial/8250/8250_omap.c
-@@ -1503,10 +1503,10 @@ static int __init omap8250_console_fixup(void)
- }
-
- add_preferred_console("ttyS", idx, options);
-- pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
-+ pr_info("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
- idx, idx);
-- pr_err("This ensures that you still see kernel messages. Please\n");
-- pr_err("update your kernel commandline.\n");
-+ pr_info("This ensures that you still see kernel messages. Please\n");
-+ pr_info("update your kernel commandline.\n");
- return 0;
- }
- console_initcall(omap8250_console_fixup);
---
-2.20.1
-
diff --git a/patches/drivers/ti/serial/0002-Revert-Revert-serial-8250-Fix-clearing-FIFOs-in-RS48.patch b/patches/drivers/ti/serial/0002-Revert-Revert-serial-8250-Fix-clearing-FIFOs-in-RS48.patch
deleted file mode 100644
index 40eaa0f0f2fcb86eb631d0ba8b01cf53057caa1c..0000000000000000000000000000000000000000
--- a/patches/drivers/ti/serial/0002-Revert-Revert-serial-8250-Fix-clearing-FIFOs-in-RS48.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 9ac130a78dfbdf33927401cd00e99538f05bc0ff Mon Sep 17 00:00:00 2001
-From: Robert Nelson <robertcnelson@gmail.com>
-Date: Thu, 20 May 2021 16:51:43 -0500
-Subject: [PATCH 2/2] Revert "Revert "serial: 8250: Fix clearing FIFOs in RS485
- mode again""
-
-This reverts commit 3c9dc275dba1124c1e16e7037226038451286813.
-
-Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
----
- drivers/tty/serial/8250/8250_port.c | 29 ++++++++++++++++++++++++-----
- 1 file changed, 24 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
-index b0af13074cd3..16c548481283 100644
---- a/drivers/tty/serial/8250/8250_port.c
-+++ b/drivers/tty/serial/8250/8250_port.c
-@@ -550,11 +550,30 @@ static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
- */
- static void serial8250_clear_fifos(struct uart_8250_port *p)
- {
-+ unsigned char fcr;
-+ unsigned char clr_mask = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;
-+
- if (p->capabilities & UART_CAP_FIFO) {
-- serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
-- serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
-- UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
-- serial_out(p, UART_FCR, 0);
-+ /*
-+ * Make sure to avoid changing FCR[7:3] and ENABLE_FIFO bits.
-+ * In case ENABLE_FIFO is not set, there is nothing to flush
-+ * so just return. Furthermore, on certain implementations of
-+ * the 8250 core, the FCR[7:3] bits may only be changed under
-+ * specific conditions and changing them if those conditions
-+ * are not met can have nasty side effects. One such core is
-+ * the 8250-omap present in TI AM335x.
-+ */
-+ fcr = serial_in(p, UART_FCR);
-+
-+ /* FIFO is not enabled, there's nothing to clear. */
-+ if (!(fcr & UART_FCR_ENABLE_FIFO))
-+ return;
-+
-+ fcr |= clr_mask;
-+ serial_out(p, UART_FCR, fcr);
-+
-+ fcr &= ~clr_mask;
-+ serial_out(p, UART_FCR, fcr);
- }
- }
-
-@@ -1456,7 +1475,7 @@ void serial8250_em485_stop_tx(struct uart_8250_port *p)
- * Enable previously disabled RX interrupts.
- */
- if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
-- serial8250_clear_and_reinit_fifos(p);
-+ serial8250_clear_fifos(p);
-
- p->ier |= UART_IER_RLSI | UART_IER_RDI;
- serial_port_out(&p->port, UART_IER, p->ier);
---
-2.30.2
-
diff --git a/patches/drivers/tps65217/0001-HACK-tps65217_pwr_but.patch b/patches/drivers/tps65217/0001-HACK-tps65217_pwr_but.patch
deleted file mode 100644
index f5d3abcacae46f55cab87a62f4214187d4c2f16e..0000000000000000000000000000000000000000
--- a/patches/drivers/tps65217/0001-HACK-tps65217_pwr_but.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From fd9c8bf4ac08100d58d5e51a383db18d66bf1714 Mon Sep 17 00:00:00 2001
-From: Robert Nelson <robertcnelson@gmail.com>
-Date: Fri, 28 Oct 2016 14:14:27 -0500
-Subject: [PATCH] HACK: tps65217_pwr_but
-
-Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
----
- drivers/input/misc/tps65218-pwrbutton.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/input/misc/tps65218-pwrbutton.c b/drivers/input/misc/tps65218-pwrbutton.c
-index a4455bb12ae0..b6d4321d421f 100644
---- a/drivers/input/misc/tps65218-pwrbutton.c
-+++ b/drivers/input/misc/tps65218-pwrbutton.c
-@@ -36,7 +36,7 @@ struct tps6521x_data {
- static const struct tps6521x_data tps65217_data = {
- .reg_status = TPS65217_REG_STATUS,
- .pb_mask = TPS65217_STATUS_PB,
-- .name = "tps65217_pwrbutton",
-+ .name = "tps65217_pwr_but",
- };
-
- static const struct tps6521x_data tps65218_data = {
---
-2.20.1
-
diff --git a/patches/dts/omap/0001-ARM-dts-am335x-boneblue-add-gpio-line-names.patch b/patches/dts/omap/0001-ARM-dts-am335x-boneblue-add-gpio-line-names.patch
deleted file mode 100644
index a791bbc38453b0727ef8f11dca757c8aa97ec6c4..0000000000000000000000000000000000000000
--- a/patches/dts/omap/0001-ARM-dts-am335x-boneblue-add-gpio-line-names.patch
+++ /dev/null
@@ -1,176 +0,0 @@
-From 885971db68665badce8d9a0b0454376918391960 Mon Sep 17 00:00:00 2001
-From: David Lechner <david@lechnology.com>
-Date: Fri, 9 Jul 2021 16:47:06 -0500
-Subject: [PATCH 1/4] ARM: dts: am335x-boneblue: add gpio-line-names
-
-This adds gpio-line-names to the BeagleBone Blue DTS. The line names
-are based on the BeagleBone Blue rev A2 schematic.
-
-Signed-off-by: David Lechner <david@lechnology.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
- arch/arm/boot/dts/am335x-boneblue.dts | 143 +++++++++++++++++++++++++-
- 1 file changed, 142 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
-index 0afcc2ee0b63..c6bb325ead33 100644
---- a/arch/arm/boot/dts/am335x-boneblue.dts
-+++ b/arch/arm/boot/dts/am335x-boneblue.dts
-@@ -435,12 +435,153 @@ &dcan1 {
- status = "okay";
- };
-
-+&gpio0 {
-+ gpio-line-names =
-+ "UART3_CTS", /* M17 */
-+ "UART3_RTS", /* M18 */
-+ "UART2_RX", /* A17 */
-+ "UART2_TX", /* B17 */
-+ "I2C1_SDA", /* B16 */
-+ "I2C1_SCL", /* A16 */
-+ "MMC0_CD", /* C15 */
-+ "SPI1_SS2", /* C18 */
-+ "EQEP_1A", /* V2 */
-+ "EQEP_1B", /* V3 */
-+ "MDIR_2B", /* V4 */
-+ "BATT_LED_2", /* T5 */
-+ "I2C2_SDA", /* D18 */
-+ "I2C2_SCL", /* D17 */
-+ "UART1_RX", /* D16 */
-+ "UART1_TX", /* D15 */
-+ "MMC2_DAT1", /* J18 */
-+ "MMC2_DAT2", /* K15 */
-+ "NC", /* F16 */
-+ "WIFI_LED", /* A15 */
-+ "MOT_STBY", /* D14 */
-+ "WLAN_IRQ", /* K16 */
-+ "PWM_2A", /* U10 */
-+ "PWM_2B", /* T10 */
-+ "",
-+ "",
-+ "BATT_LED_4", /* T11 */
-+ "BATT_LED_1", /* U12 */
-+ "BT_EN", /* K17 */
-+ "SPI1_SS1", /* H18 */
-+ "UART4_RX", /* T17 */
-+ "MDIR_1B"; /* U17 */
-+};
-+
-+&gpio1 {
-+ gpio-line-names =
-+ "MMC1_DAT0", /* U7 */
-+ "MMC1_DAT1", /* V7 */
-+ "MMC1_DAT2", /* R8 */
-+ "MMC1_DAT3", /* T8 */
-+ "MMC1_DAT4", /* U8 */
-+ "MMC1_DAT5", /* V8 */
-+ "MMC1_DAT6", /* R9 */
-+ "MMC1_DAT7", /* T9 */
-+ "DCAN1_TX", /* E18 */
-+ "DCAN1_RX", /* E17 */
-+ "UART0_RX", /* E15 */
-+ "UART0_TX", /* E16 */
-+ "EQEP_2A", /* T12 */
-+ "EQEP_2B", /* R12 */
-+ "PRU_E_A", /* V13 */
-+ "PRU_E_B", /* U13 */
-+ "MDIR_2A", /* R13 */
-+ "GPIO1_17", /* V14 */
-+ "PWM_1A", /* U14 */
-+ "PWM_1B", /* T14 */
-+ "EMMC_RST", /* R14 */
-+ "USR_LED_0", /* V15 */
-+ "USR_LED_1", /* U15 */
-+ "USR_LED_2", /* T15 */
-+ "USR_LED_3", /* V16 */
-+ "GPIO1_25", /* U16 */
-+ "MCASP0_AXR0", /* T16 */
-+ "MCASP0_AXR1", /* V17 */
-+ "MCASP0_ACLKR", /* U18 */
-+ "BATT_LED_3", /* V6 */
-+ "MMC1_CLK", /* U9 */
-+ "MMC1_CMD"; /* V9 */
-+};
-+
-+&gpio2 {
-+ gpio-line-names =
-+ "MDIR_1A", /* T13 */
-+ "MCASP0_FSR", /* V12 */
-+ "LED_RED", /* R7 */
-+ "LED_GREEN", /* T7 */
-+ "MODE_BTN", /* U6 */
-+ "PAUSE_BTN", /* T6 */
-+ "MDIR_4A", /* R1 */
-+ "MDIR_4B", /* R2 */
-+ "MDIR_3B", /* R3 */
-+ "MDIR_3A", /* R4 */
-+ "SVO7", /* T1 */
-+ "SVO8", /* T2 */
-+ "SVO5", /* T3 */
-+ "SVO6", /* T4 */
-+ "UART5_TX", /* U1 */
-+ "UART5_RX", /* U2 */
-+ "SERVO_EN", /* U3 */
-+ "NC", /* U4 */
-+ "UART3_RX", /* L17 */
-+ "UART3_TX", /* L16 */
-+ "MMC2_CLK", /* L15 */
-+ "DCAN1_SILENT", /* M16 */
-+ "SVO1", /* U5 */
-+ "SVO3", /* R5 */
-+ "SVO2", /* V5 */
-+ "SVO4", /* R6 */
-+ "MMC0_DAT3", /* F17 */
-+ "MMC0_DAT2", /* F18 */
-+ "MMC0_DAT1", /* G15 */
-+ "MMC0_DAT0", /* G16 */
-+ "MMC0_CLK", /* G17 */
-+ "MMC0_CMD"; /* G18 */
-+};
-+
- &gpio3 {
-+ gpio-line-names =
-+ "MMC2_DAT3", /* H16 */
-+ "GPIO3_1", /* H17 */
-+ "GPIO3_2", /* J15 */
-+ "MMC2_CMD", /* J16 */
-+ "MMC2_DAT0", /* J17 */
-+ "I2C0_SDA", /* C17 */
-+ "I2C0_SCL", /* C16 */
-+ "EMU1", /* C14 */
-+ "EMU0", /* B14 */
-+ "WL_EN", /* K18 */
-+ "WL_BT_OE", /* L18 */
-+ "",
-+ "",
-+ "NC", /* F15 */
-+ "SPI1_SCK", /* A13 */
-+ "SPI1_MISO", /* B13 */
-+ "SPI1_MOSI", /* D12 */
-+ "GPIO3_17", /* C12 */
-+ "EQEP_0A", /* B12 */
-+ "EQEP_0B", /* C13 */
-+ "GPIO3_20", /* D13 */
-+ "IMU_INT", /* A14 */
-+ "",
-+ "",
-+ "",
-+ "",
-+ "",
-+ "",
-+ "",
-+ "",
-+ "",
-+ "";
-+
- ls-buf-en-hog {
- gpio-hog;
- gpios = <10 GPIO_ACTIVE_HIGH>;
- output-high;
-- line-name = "LS_BUF_EN";
- };
- };
-
---
-2.30.2
-
diff --git a/patches/dts/omap/0002-ARM-dts-am335x-boneblack-Extract-HDMI-config.patch b/patches/dts/omap/0002-ARM-dts-am335x-boneblack-Extract-HDMI-config.patch
deleted file mode 100644
index 3228feb4b217f314ad35c23096cd06d190454a5e..0000000000000000000000000000000000000000
--- a/patches/dts/omap/0002-ARM-dts-am335x-boneblack-Extract-HDMI-config.patch
+++ /dev/null
@@ -1,369 +0,0 @@
-From 8b113de254951b51dc2026af863ab6b9fef56c34 Mon Sep 17 00:00:00 2001
-From: Paul Barker <paul.barker@sancloud.com>
-Date: Tue, 20 Jul 2021 09:39:25 +0100
-Subject: [PATCH 2/4] ARM: dts: am335x-boneblack: Extract HDMI config
-
-Move the HDMI hardware configuration for the BeagleBone Black out of the
-boneblack common dtsi file and into its own separate dtsi file. This
-allows the devicetree for BeagleBone Black derivatives which lack the
-hdmi encoding hardware to include the common dtsi file without needing
-to duplicate configuration or override the status of all hdmi-related
-nodes.
-
-Signed-off-by: Paul Barker <paul.barker@sancloud.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
- .../arm/boot/dts/am335x-boneblack-common.dtsi | 135 -----------------
- arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi | 141 ++++++++++++++++++
- .../boot/dts/am335x-boneblack-wireless.dts | 1 +
- arch/arm/boot/dts/am335x-boneblack.dts | 1 +
- arch/arm/boot/dts/am335x-sancloud-bbe.dts | 1 +
- 5 files changed, 144 insertions(+), 135 deletions(-)
- create mode 100644 arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi
-
-diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
-index 64c3e9269f40..10494c4431b9 100644
---- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi
-+++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
-@@ -3,9 +3,6 @@
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
--#include <dt-bindings/display/tda998x.h>
--#include <dt-bindings/interrupt-controller/irq.h>
--
- &ldo3_reg {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-@@ -25,145 +22,13 @@ &mmc2 {
- non-removable;
- };
-
--&am33xx_pinmux {
-- nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
-- pinctrl-single,pins = <
-- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-- >;
-- };
--
-- nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
-- pinctrl-single,pins = <
-- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-- >;
-- };
--
-- mcasp0_pins: mcasp0_pins {
-- pinctrl-single,pins = <
-- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
-- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
-- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
-- >;
-- };
--};
--
--&lcdc {
-- status = "okay";
--
-- /* If you want to get 24 bit RGB and 16 BGR mode instead of
-- * current 16 bit RGB and 24 BGR modes, set the propety
-- * below to "crossed" and uncomment the video-ports -property
-- * in tda19988 node.
-- */
-- blue-and-red-wiring = "straight";
--
-- port {
-- lcdc_0: endpoint@0 {
-- remote-endpoint = <&hdmi_0>;
-- };
-- };
--};
--
--&i2c0 {
-- tda19988: tda19988@70 {
-- compatible = "nxp,tda998x";
-- reg = <0x70>;
-- nxp,calib-gpios = <&gpio1 25 0>;
-- interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>;
--
-- pinctrl-names = "default", "off";
-- pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
-- pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
--
-- /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
-- /* video-ports = <0x234501>; */
--
-- #sound-dai-cells = <0>;
-- audio-ports = < TDA998x_I2S 0x03>;
--
-- ports {
-- port@0 {
-- hdmi_0: endpoint@0 {
-- remote-endpoint = <&lcdc_0>;
-- };
-- };
-- };
-- };
--};
--
- &rtc {
- system-power-controller;
- };
-
--&mcasp0 {
-- #sound-dai-cells = <0>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&mcasp0_pins>;
-- status = "okay";
-- op-mode = <0>; /* MCASP_IIS_MODE */
-- tdm-slots = <2>;
-- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
-- 0 0 1 0
-- >;
-- tx-num-evt = <32>;
-- rx-num-evt = <32>;
--};
--
- / {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x20000000>; /* 512 MB */
- };
--
-- clk_mcasp0_fixed: clk_mcasp0_fixed {
-- #clock-cells = <0>;
-- compatible = "fixed-clock";
-- clock-frequency = <24576000>;
-- };
--
-- clk_mcasp0: clk_mcasp0 {
-- #clock-cells = <0>;
-- compatible = "gpio-gate-clock";
-- clocks = <&clk_mcasp0_fixed>;
-- enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */
-- };
--
-- sound {
-- compatible = "simple-audio-card";
-- simple-audio-card,name = "TI BeagleBone Black";
-- simple-audio-card,format = "i2s";
-- simple-audio-card,bitclock-master = <&dailink0_master>;
-- simple-audio-card,frame-master = <&dailink0_master>;
--
-- dailink0_master: simple-audio-card,cpu {
-- sound-dai = <&mcasp0>;
-- clocks = <&clk_mcasp0>;
-- };
--
-- simple-audio-card,codec {
-- sound-dai = <&tda19988>;
-- };
-- };
- };
-diff --git a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi
-new file mode 100644
-index 000000000000..7cfddada9348
---- /dev/null
-+++ b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi
-@@ -0,0 +1,141 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
-+ */
-+
-+#include <dt-bindings/display/tda998x.h>
-+#include <dt-bindings/interrupt-controller/irq.h>
-+
-+&am33xx_pinmux {
-+ nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
-+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ >;
-+ };
-+
-+ nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
-+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-+ >;
-+ };
-+
-+ mcasp0_pins: mcasp0_pins {
-+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
-+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
-+ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
-+ >;
-+ };
-+};
-+
-+&lcdc {
-+ status = "okay";
-+
-+ /* If you want to get 24 bit RGB and 16 BGR mode instead of
-+ * current 16 bit RGB and 24 BGR modes, set the propety
-+ * below to "crossed" and uncomment the video-ports -property
-+ * in tda19988 node.
-+ */
-+ blue-and-red-wiring = "straight";
-+
-+ port {
-+ lcdc_0: endpoint@0 {
-+ remote-endpoint = <&hdmi_0>;
-+ };
-+ };
-+};
-+
-+&i2c0 {
-+ tda19988: tda19988@70 {
-+ compatible = "nxp,tda998x";
-+ reg = <0x70>;
-+ nxp,calib-gpios = <&gpio1 25 0>;
-+ interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>;
-+
-+ pinctrl-names = "default", "off";
-+ pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
-+ pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
-+
-+ /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
-+ /* video-ports = <0x234501>; */
-+
-+ #sound-dai-cells = <0>;
-+ audio-ports = < TDA998x_I2S 0x03>;
-+
-+ ports {
-+ port@0 {
-+ hdmi_0: endpoint@0 {
-+ remote-endpoint = <&lcdc_0>;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&mcasp0 {
-+ #sound-dai-cells = <0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mcasp0_pins>;
-+ status = "okay";
-+ op-mode = <0>; /* MCASP_IIS_MODE */
-+ tdm-slots = <2>;
-+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
-+ 0 0 1 0
-+ >;
-+ tx-num-evt = <32>;
-+ rx-num-evt = <32>;
-+};
-+
-+/ {
-+ clk_mcasp0_fixed: clk_mcasp0_fixed {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+ clock-frequency = <24576000>;
-+ };
-+
-+ clk_mcasp0: clk_mcasp0 {
-+ #clock-cells = <0>;
-+ compatible = "gpio-gate-clock";
-+ clocks = <&clk_mcasp0_fixed>;
-+ enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */
-+ };
-+
-+ sound {
-+ compatible = "simple-audio-card";
-+ simple-audio-card,name = "TI BeagleBone Black";
-+ simple-audio-card,format = "i2s";
-+ simple-audio-card,bitclock-master = <&dailink0_master>;
-+ simple-audio-card,frame-master = <&dailink0_master>;
-+
-+ dailink0_master: simple-audio-card,cpu {
-+ sound-dai = <&mcasp0>;
-+ clocks = <&clk_mcasp0>;
-+ };
-+
-+ simple-audio-card,codec {
-+ sound-dai = <&tda19988>;
-+ };
-+ };
-+};
-diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
-index 80116646a3fe..8b2b24c80670 100644
---- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
-+++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
-@@ -7,6 +7,7 @@
- #include "am33xx.dtsi"
- #include "am335x-bone-common.dtsi"
- #include "am335x-boneblack-common.dtsi"
-+#include "am335x-boneblack-hdmi.dtsi"
- #include <dt-bindings/interrupt-controller/irq.h>
-
- / {
-diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
-index e2ee8b8c07bc..9312197316f0 100644
---- a/arch/arm/boot/dts/am335x-boneblack.dts
-+++ b/arch/arm/boot/dts/am335x-boneblack.dts
-@@ -7,6 +7,7 @@
- #include "am33xx.dtsi"
- #include "am335x-bone-common.dtsi"
- #include "am335x-boneblack-common.dtsi"
-+#include "am335x-boneblack-hdmi.dtsi"
-
- / {
- model = "TI AM335x BeagleBone Black";
-diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-index 275ba339adf4..c82295654bdd 100644
---- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-+++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-@@ -7,6 +7,7 @@
- #include "am33xx.dtsi"
- #include "am335x-bone-common.dtsi"
- #include "am335x-boneblack-common.dtsi"
-+#include "am335x-boneblack-hdmi.dtsi"
- #include <dt-bindings/interrupt-controller/irq.h>
-
- / {
---
-2.30.2
-
diff --git a/patches/dts/omap/0003-ARM-dts-am335x-sancloud-bbe-Extract-common-code.patch b/patches/dts/omap/0003-ARM-dts-am335x-sancloud-bbe-Extract-common-code.patch
deleted file mode 100644
index 8d053c0f5297044a3aca515a0cc06db2d345c8d3..0000000000000000000000000000000000000000
--- a/patches/dts/omap/0003-ARM-dts-am335x-sancloud-bbe-Extract-common-code.patch
+++ /dev/null
@@ -1,242 +0,0 @@
-From a70b987a4be9781c67d792f827a851112be1d0f6 Mon Sep 17 00:00:00 2001
-From: Paul Barker <paul.barker@sancloud.com>
-Date: Tue, 20 Jul 2021 09:39:26 +0100
-Subject: [PATCH 3/4] ARM: dts: am335x-sancloud-bbe: Extract common code
-
-The Sancloud BBE, BBE Lite and BBE Extended+WiFi share a common hardware
-base so we can avoid duplication via a dtsi file.
-
-Signed-off-by: Paul Barker <paul.barker@sancloud.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
- .../boot/dts/am335x-sancloud-bbe-common.dtsi | 96 +++++++++++++++++++
- arch/arm/boot/dts/am335x-sancloud-bbe.dts | 91 +-----------------
- 2 files changed, 97 insertions(+), 90 deletions(-)
- create mode 100644 arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-
-diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-new file mode 100644
-index 000000000000..bd9c21813192
---- /dev/null
-+++ b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-@@ -0,0 +1,96 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
-+ */
-+
-+&am33xx_pinmux {
-+ cpsw_default: cpsw_default {
-+ pinctrl-single,pins = <
-+ /* Slave 1 */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
-+ >;
-+ };
-+
-+ cpsw_sleep: cpsw_sleep {
-+ pinctrl-single,pins = <
-+ /* Slave 1 reset value */
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ >;
-+ };
-+
-+ davinci_mdio_default: davinci_mdio_default {
-+ pinctrl-single,pins = <
-+ /* MDIO */
-+ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
-+ >;
-+ };
-+
-+ davinci_mdio_sleep: davinci_mdio_sleep {
-+ pinctrl-single,pins = <
-+ /* MDIO reset value */
-+ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
-+ >;
-+ };
-+
-+ usb_hub_ctrl: usb_hub_ctrl {
-+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */
-+ >;
-+ };
-+};
-+
-+&mac {
-+ pinctrl-names = "default", "sleep";
-+ pinctrl-0 = <&cpsw_default>;
-+ pinctrl-1 = <&cpsw_sleep>;
-+ status = "okay";
-+};
-+
-+&davinci_mdio {
-+ pinctrl-names = "default", "sleep";
-+ pinctrl-0 = <&davinci_mdio_default>;
-+ pinctrl-1 = <&davinci_mdio_sleep>;
-+ status = "okay";
-+
-+ ethphy0: ethernet-phy@0 {
-+ reg = <0>;
-+ };
-+};
-+
-+&cpsw_emac0 {
-+ phy-handle = <ðphy0>;
-+ phy-mode = "rgmii-id";
-+};
-+
-+&i2c0 {
-+ usb2512b: usb-hub@2c {
-+ compatible = "microchip,usb2512b";
-+ reg = <0x2c>;
-+ reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
-+ /* wifi on port 4 */
-+ };
-+};
-diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-index c82295654bdd..2a0ac9f5dda7 100644
---- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-+++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-@@ -8,6 +8,7 @@
- #include "am335x-bone-common.dtsi"
- #include "am335x-boneblack-common.dtsi"
- #include "am335x-boneblack-hdmi.dtsi"
-+#include "am335x-sancloud-bbe-common.dtsi"
- #include <dt-bindings/interrupt-controller/irq.h>
-
- / {
-@@ -16,66 +17,6 @@ / {
- };
-
- &am33xx_pinmux {
-- pinctrl-names = "default";
--
-- cpsw_default: cpsw_default {
-- pinctrl-single,pins = <
-- /* Slave 1 */
-- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */
-- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
-- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
-- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
-- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
-- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
-- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
-- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
-- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
-- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
-- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
-- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
-- >;
-- };
--
-- cpsw_sleep: cpsw_sleep {
-- pinctrl-single,pins = <
-- /* Slave 1 reset value */
-- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- >;
-- };
--
-- davinci_mdio_default: davinci_mdio_default {
-- pinctrl-single,pins = <
-- /* MDIO */
-- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
-- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
-- >;
-- };
--
-- davinci_mdio_sleep: davinci_mdio_sleep {
-- pinctrl-single,pins = <
-- /* MDIO reset value */
-- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
-- >;
-- };
--
-- usb_hub_ctrl: usb_hub_ctrl {
-- pinctrl-single,pins = <
-- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */
-- >;
-- };
--
- mpu6050_pins: pinmux_mpu6050_pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */
-@@ -89,29 +30,6 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_
- };
- };
-
--&mac {
-- pinctrl-names = "default", "sleep";
-- pinctrl-0 = <&cpsw_default>;
-- pinctrl-1 = <&cpsw_sleep>;
-- status = "okay";
--};
--
--&davinci_mdio {
-- pinctrl-names = "default", "sleep";
-- pinctrl-0 = <&davinci_mdio_default>;
-- pinctrl-1 = <&davinci_mdio_sleep>;
-- status = "okay";
--
-- ethphy0: ethernet-phy@0 {
-- reg = <0>;
-- };
--};
--
--&cpsw_emac0 {
-- phy-handle = <ðphy0>;
-- phy-mode = "rgmii-id";
--};
--
- &i2c0 {
- lps331ap: barometer@5c {
- compatible = "st,lps331ap-press";
-@@ -128,11 +46,4 @@ mpu6050: accelerometer@68 {
- interrupts = <2 IRQ_TYPE_EDGE_RISING>;
- orientation = <0xff 0 0 0 1 0 0 0 0xff>;
- };
--
-- usb2512b: usb-hub@2c {
-- compatible = "microchip,usb2512b";
-- reg = <0x2c>;
-- reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
-- /* wifi on port 4 */
-- };
- };
---
-2.30.2
-
diff --git a/patches/dts/omap/0004-ARM-dts-am335x-sancloud-bbe-lite-New-devicetree.patch b/patches/dts/omap/0004-ARM-dts-am335x-sancloud-bbe-lite-New-devicetree.patch
deleted file mode 100644
index aff311cbb760343d90c93ab390c21dfff41d87fa..0000000000000000000000000000000000000000
--- a/patches/dts/omap/0004-ARM-dts-am335x-sancloud-bbe-lite-New-devicetree.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From ac262b7f9a3e58acbc9c40d55826fc09cd089fbf Mon Sep 17 00:00:00 2001
-From: Paul Barker <paul.barker@sancloud.com>
-Date: Tue, 20 Jul 2021 09:39:27 +0100
-Subject: [PATCH 4/4] ARM: dts: am335x-sancloud-bbe-lite: New devicetree
-
-This adds support for the Sancloud BBE Lite which shares a common
-hardware base with the non-Lite version of the BBE.
-
-Signed-off-by: Paul Barker <paul.barker@sancloud.com>
-Signed-off-by: Tony Lindgren <tony@atomide.com>
----
- arch/arm/boot/dts/Makefile | 1 +
- .../arm/boot/dts/am335x-sancloud-bbe-lite.dts | 50 +++++++++++++++++++
- 2 files changed, 51 insertions(+)
- create mode 100644 arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts
-
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index 863347b6b65e..8da525e7f0ab 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -843,6 +843,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
- am335x-pocketbeagle.dtb \
- am335x-regor-rdk.dtb \
- am335x-sancloud-bbe.dtb \
-+ am335x-sancloud-bbe-lite.dtb \
- am335x-shc.dtb \
- am335x-sbc-t335.dtb \
- am335x-sl50.dtb \
-diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts
-new file mode 100644
-index 000000000000..d6ef19311a91
---- /dev/null
-+++ b/arch/arm/boot/dts/am335x-sancloud-bbe-lite.dts
-@@ -0,0 +1,50 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-+ * Copyright (C) 2021 SanCloud Ltd
-+ */
-+/dts-v1/;
-+
-+#include "am33xx.dtsi"
-+#include "am335x-bone-common.dtsi"
-+#include "am335x-boneblack-common.dtsi"
-+#include "am335x-sancloud-bbe-common.dtsi"
-+
-+/ {
-+ model = "SanCloud BeagleBone Enhanced Lite";
-+ compatible = "sancloud,am335x-boneenhanced",
-+ "ti,am335x-bone-black",
-+ "ti,am335x-bone",
-+ "ti,am33xx";
-+};
-+
-+&am33xx_pinmux {
-+ bb_spi0_pins: pinmux_bb_spi0_pins {
-+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0)
-+ >;
-+ };
-+};
-+
-+&spi0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ status = "okay";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&bb_spi0_pins>;
-+
-+ channel@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ compatible = "micron,spi-authenta";
-+
-+ reg = <0>;
-+ spi-max-frequency = <16000000>;
-+ spi-cpha;
-+ };
-+};
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0001-ARM-dts-am33xx-l4-Add-PRUSS-node.patch b/patches/dts/omap_pruss/0001-ARM-dts-am33xx-l4-Add-PRUSS-node.patch
deleted file mode 100644
index 6283c6b93c8405f8d1c64d608a456f674a049937..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0001-ARM-dts-am33xx-l4-Add-PRUSS-node.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From 389093c2f12e8e2fb822d726a2927f0f8a04a7e8 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:11 -0500
-Subject: [PATCH 01/11] ARM: dts: am33xx-l4: Add PRUSS node
-
-Add the DT nodes for the PRU-ICSS on AM33xx family of SoCs. The AM33xx
-SoCs contain a single PRU-ICSS instance and is represented by a pruss
-node and other child nodes. PRU-ICSS is supported only on AM3356+ SoCs
-though in the AM33xx family, so the nodes are added under the
-corresponding disabled interconnect target module node in the common
-am33xx-l4 dtsi file. The target module node should be enabled in only
-those derivative board files that use a SoC containing PRU-ICSS.
-
-The PRUSS subsystem node contains the entire address space. The various
-sub-modules of the PRU-ICSS are represented as individual child nodes
-(so platform devices themselves) of the PRUSS subsystem node. These
-include the two PRU cores and the interrupt controller. All the Data
-RAMs are represented within a child node of its own named 'memories'
-without any compatible. The Real Time Media Independent Interface
-controller (MII_RT), and the CFG sub-module are represented as syscon
-nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk
-node is added under the CFG child node 'clocks'. The default source
-for this mux clock is the PRU_ICSS_IEP_GCLK clock.
-
-The DT nodes use all standard properties. The regs property in the PRU
-nodes define the addresses for the Instruction RAM, the Debug and Control
-sub-modules for that PRU core. The firmware for each PRU core is defined
-through a 'firmware-name' property.
-
-The default names for the firmware images for each PRU core are defined
-as follows (these can be adjusted either in derivative board dts files
-or through sysfs at runtime if required):
- PRU-ICSS PRU0 Core: am335x-pru1_0-fw
- PRU-ICSS PRU1 Core: am335x-pru1_1-fw
-
-Note:
-1. There are few more sub-modules like the Industrial Ethernet Peripheral
- (IEP), MDIO, UART, eCAP that do not have bindings and so will be added
- in the future.
-2. The PRUSS INTC on AM335x SoCs also connect the host interrupts 0 to
- TSC_ADC; 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved'
- property in derivative board dts files _if_ any of them should not be
- handled by the host OS.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am33xx-l4.dtsi | 71 ++++++++++++++++++++++++++++++++
- 1 file changed, 71 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
-index 859e760df4c8..148176361b4e 100644
---- a/arch/arm/boot/dts/am33xx-l4.dtsi
-+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
-@@ -853,6 +853,77 @@ pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
- #size-cells = <1>;
- ranges = <0x0 0x300000 0x80000>;
- status = "disabled";
-+
-+ pruss: pruss@0 {
-+ compatible = "ti,am3356-pruss";
-+ reg = <0x0 0x80000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ pruss_mem: memories@0 {
-+ reg = <0x0 0x2000>,
-+ <0x2000 0x2000>,
-+ <0x10000 0x3000>;
-+ reg-names = "dram0", "dram1",
-+ "shrdram2";
-+ };
-+
-+ pruss_cfg: cfg@26000 {
-+ compatible = "ti,pruss-cfg", "syscon";
-+ reg = <0x26000 0x2000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x26000 0x2000>;
-+
-+ clocks {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pruss_iepclk_mux: iepclk-mux@30 {
-+ reg = <0x30>;
-+ #clock-cells = <0>;
-+ clocks = <&l3_gclk>, /* icss_iep_gclk */
-+ <&pruss_ocp_gclk>; /* icss_ocp_gclk */
-+ };
-+ };
-+ };
-+
-+ pruss_mii_rt: mii-rt@32000 {
-+ compatible = "ti,pruss-mii", "syscon";
-+ reg = <0x32000 0x58>;
-+ };
-+
-+ pruss_intc: interrupt-controller@20000 {
-+ compatible = "ti,pruss-intc";
-+ reg = <0x20000 0x2000>;
-+ interrupts = <20 21 22 23 24 25 26 27>;
-+ interrupt-names = "host_intr0", "host_intr1",
-+ "host_intr2", "host_intr3",
-+ "host_intr4", "host_intr5",
-+ "host_intr6", "host_intr7";
-+ interrupt-controller;
-+ #interrupt-cells = <3>;
-+ };
-+
-+ pru0: pru@34000 {
-+ compatible = "ti,am3356-pru";
-+ reg = <0x34000 0x2000>,
-+ <0x22000 0x400>,
-+ <0x22400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am335x-pru0-fw";
-+ };
-+
-+ pru1: pru@38000 {
-+ compatible = "ti,am3356-pru";
-+ reg = <0x38000 0x2000>,
-+ <0x24000 0x400>,
-+ <0x24400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am335x-pru1-fw";
-+ };
-+ };
- };
- };
- };
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0002-ARM-dts-am33xx-l4-Add-PRUSS-MDIO-controller-node.patch b/patches/dts/omap_pruss/0002-ARM-dts-am33xx-l4-Add-PRUSS-MDIO-controller-node.patch
deleted file mode 100644
index 19fb572a87a39b14c3703cf1fd124e4fab965e25..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0002-ARM-dts-am33xx-l4-Add-PRUSS-MDIO-controller-node.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From e58a8c83926d9840c5db57967920f53b85bf1700 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:12 -0500
-Subject: [PATCH 02/11] ARM: dts: am33xx-l4: Add PRUSS MDIO controller node
-
-The PRUSS on AM335x SoCs has a MDIO sub-module that can be used
-to control external PHYs associated with the Industrial Ethernet
-peripherals within the PRUSS. The MDIO module used within the
-PRU-ICSS is an instance of the MDIO Controller used in TI Davinci
-SoCs. The same bus frequency of 1 MHz is chosen as the regular
-MDIO node.
-
-The node is added to the common am33xx-l4.dtsi file and is disabled.
-This needs to be enabled in the respective board files using the
-relevant AM335x SoCs supporting PRUSS and where the ethernet is
-pinned out and connected properly.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am33xx-l4.dtsi | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
-index 148176361b4e..c9629cb5ccd1 100644
---- a/arch/arm/boot/dts/am33xx-l4.dtsi
-+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
-@@ -923,6 +923,17 @@ pru1: pru@38000 {
- reg-names = "iram", "control", "debug";
- firmware-name = "am335x-pru1-fw";
- };
-+
-+ pruss_mdio: mdio@32400 {
-+ compatible = "ti,davinci_mdio";
-+ reg = <0x32400 0x90>;
-+ clocks = <&dpll_core_m4_ck>;
-+ clock-names = "fck";
-+ bus_freq = <1000000>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
- };
- };
- };
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0003-ARM-dts-am335x-bone-common-Enable-PRU-ICSS-node.patch b/patches/dts/omap_pruss/0003-ARM-dts-am335x-bone-common-Enable-PRU-ICSS-node.patch
deleted file mode 100644
index 269a446e22a0729daf65a344ac4ef261ea7bf4be..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0003-ARM-dts-am335x-bone-common-Enable-PRU-ICSS-node.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 697ee639f401b3b7f05ff38605016fcbbf3ecd66 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:13 -0500
-Subject: [PATCH 03/11] ARM: dts: am335x-bone-common: Enable PRU-ICSS node
-
-The PRU-ICSS target module node was left in disabled state in the base
-am33xx-l4.dtsi file. Enable this node on all the AM335x beaglebone
-boards as they mostly use a AM3358 or a AM3359 SoC which do contain
-the PRU-ICSS IP. The PRUSS node and most of its child nodes are already
-enabled in the base dts file, and so become effective automatically
-with the enabling of this PRU-ICSS target-module node.
-
-The corresponding PRU nodes can be disabled later on if there are
-no use-cases defined to use a particular PRU core or the whole
-PRU-ICSS subsystem itself if both its PRU cores are unused.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
-index 2d51d4bba6d4..34a0045b5f65 100644
---- a/arch/arm/boot/dts/am335x-bone-common.dtsi
-+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
-@@ -397,3 +397,7 @@ &rtc {
- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
- clock-names = "ext-clk", "int-clk";
- };
-+
-+&pruss_tm {
-+ status = "okay";
-+};
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0004-ARM-dts-am335x-evm-Enable-PRU-ICSS-module.patch b/patches/dts/omap_pruss/0004-ARM-dts-am335x-evm-Enable-PRU-ICSS-module.patch
deleted file mode 100644
index 5e2bdbe6f3cb72bbdc9dfe0f36cc0ebc8164fe03..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0004-ARM-dts-am335x-evm-Enable-PRU-ICSS-module.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From cb65e449de7cf179fe37acc55d28e808de2d1db0 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:14 -0500
-Subject: [PATCH 04/11] ARM: dts: am335x-evm: Enable PRU-ICSS module
-
-The PRU-ICSS target module node was left in disabled state in the
-base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x EVM,
-so enable this node on the AM335x EVM. The PRUSS node and most of
-its child nodes are already enabled in the base dts file, and so
-become effective automatically with the enabling of this PRU-ICSS
-target module node.
-
-The corresponding PRU nodes can be disabled later on if there are
-no use-cases defined to use a particular PRU core or the whole
-PRU-ICSS subsystem itself if both its PRU cores are unused.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am335x-evm.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
-index 9cf39c93defb..659e99eabe66 100644
---- a/arch/arm/boot/dts/am335x-evm.dts
-+++ b/arch/arm/boot/dts/am335x-evm.dts
-@@ -778,3 +778,7 @@ &rtc {
- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
- clock-names = "ext-clk", "int-clk";
- };
-+
-+&pruss_tm {
-+ status = "okay";
-+};
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0005-ARM-dts-am335x-evmsk-Enable-PRU-ICSS-module.patch b/patches/dts/omap_pruss/0005-ARM-dts-am335x-evmsk-Enable-PRU-ICSS-module.patch
deleted file mode 100644
index c52a9734c1cf2465ebf97daf85cc9d2fedae82a7..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0005-ARM-dts-am335x-evmsk-Enable-PRU-ICSS-module.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 41363f63d0e21e55202f947e8a70a5eede212394 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:15 -0500
-Subject: [PATCH 05/11] ARM: dts: am335x-evmsk: Enable PRU-ICSS module
-
-The PRU-ICSS target module node was left in disabled state in the
-base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x SK
-EVM board, so enable this node to support PRUSS on this board. The
-PRUSS node and most of its child nodes are already enabled in the
-base dts file, and so become effective automatically with the
-enabling of this PRU-ICSS target module node.
-
-The corresponding PRU nodes can be disabled later on if there are
-no use-cases defined to use a particular PRU core or the whole
-PRU-ICSS subsystem itself if both its PRU cores are unused.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
-index 001657be0381..a2db65538e51 100644
---- a/arch/arm/boot/dts/am335x-evmsk.dts
-+++ b/arch/arm/boot/dts/am335x-evmsk.dts
-@@ -715,3 +715,7 @@ &rtc {
- clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
- clock-names = "ext-clk", "int-clk";
- };
-+
-+&pruss_tm {
-+ status = "okay";
-+};
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0006-ARM-dts-am335x-icev2-Enable-PRU-ICSS-module.patch b/patches/dts/omap_pruss/0006-ARM-dts-am335x-icev2-Enable-PRU-ICSS-module.patch
deleted file mode 100644
index 7bb49f38f4cf1154b14f9460694fa761c706e0d9..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0006-ARM-dts-am335x-icev2-Enable-PRU-ICSS-module.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 6867f9ddaab94e73edf004ff849e4bf18c85c537 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:16 -0500
-Subject: [PATCH 06/11] ARM: dts: am335x-icev2: Enable PRU-ICSS module
-
-The PRU-ICSS target module node was left in disabled state in the
-base am33xx-l4.dtsi file. PRU-ICSS is supported on the AM335x ICEv2
-board, so enable this node to support PRUSS on this board. The PRUSS
-node and most of its child nodes are already enabled in the base dts
-file, and so become effective automatically with the enabling of
-this PRU-ICSS target module node.
-
-The corresponding PRU nodes can be disabled later on if there are
-no use-cases defined to use a particular PRU core or the whole
-PRU-ICSS subsystem itself if both its PRU cores are unused.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am335x-icev2.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
-index 5e598ac96dcc..e5ce89c8f54d 100644
---- a/arch/arm/boot/dts/am335x-icev2.dts
-+++ b/arch/arm/boot/dts/am335x-icev2.dts
-@@ -508,3 +508,7 @@ ethphy1: ethernet-phy@3 {
- reg = <3>;
- };
- };
-+
-+&pruss_tm {
-+ status = "okay";
-+};
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0007-ARM-dts-am4372-Add-the-PRU-ICSS1-DT-node.patch b/patches/dts/omap_pruss/0007-ARM-dts-am4372-Add-the-PRU-ICSS1-DT-node.patch
deleted file mode 100644
index 8b26e2d597aa9691f6afdb3cf94aee0cca010882..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0007-ARM-dts-am4372-Add-the-PRU-ICSS1-DT-node.patch
+++ /dev/null
@@ -1,147 +0,0 @@
-From 66caab85fcbdc2d924714e6a9d72ad46397a1442 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:17 -0500
-Subject: [PATCH 07/11] ARM: dts: am4372: Add the PRU-ICSS1 DT node
-
-Add the DT node for the PRU-ICSS1 instance on the AM437x family of SoCs.
-Each PRU-ICSS instance is represented by a pruss node and other child
-nodes. The nodes are added under the interconnect target module node in
-the common am4372 dtsi file. The PRU-ICSS instances are supported only
-on AM4376+ SoCs though in the AM437x family, so the interconnect target
-module node should be disabled in any derivative board dts file that
-uses AM4372 SoCs.
-
-The PRU-ICSS1 on AM437x is very similar to the PRUSS in AM33xx, except
-for variations in the RAM sizes, bus addresses and the number of
-interrupts coming into the MPU INTC (host interrupt 5 is routed to
-the other PRUSS instead of MPU).
-
-The PRUSS subsystem node contains the entire address space. The various
-sub-modules of the PRU-ICSS are represented as individual child nodes
-(so platform devices themselves) of the PRUSS subsystem node. These
-include the two PRU cores and the interrupt controller. All the Data
-RAMs are represented within a child node of its own named 'memories'
-without any compatible. The Real Time Media Independent Interface
-controller (MII_RT), and the CFG sub-module are represented as syscon
-nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk
-node is added under the CFG child node 'clocks'. The default source
-for this mux clock is the PRU_ICSS_IEP_GCLK clock.
-
-The DT nodes use all standard properties. The regs property in the PRU
-nodes define the addresses for the Instruction RAM, the Debug and Control
-sub-modules for that PRU core. The firmware for each PRU core is defined
-through a 'firmware-name' property.
-
-The default names for the firmware images for each PRU core are defined
-as follows (these can be adjusted either in derivative board dts files
-or through sysfs at runtime if required):
- PRU-ICSS1 PRU0 Core: am437x-pru1_0-fw
- PRU-ICSS1 PRU1 Core: am437x-pru1_1-fw
-
-Note:
-1. There are few more sub-modules like the Industrial Ethernet Peripheral
- (IEP), MDIO, UART, eCAP that do not have bindings and so will be added
- in the future.
-2. The PRUSS INTC on AM437x SoCs also connect the host interrupt 0 to ADC0
- and ADC1; 6 and 7 as possible DMA events, so use the 'ti,irqs-reserved'
- property in derivative board dts files _if_ any of them should not be
- handled by the host OS. Host interrupt 5 is already marked reserved as
- it is connected to the other PRUSS instance.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am4372.dtsi | 78 +++++++++++++++++++++++++++++++++++
- 1 file changed, 78 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
-index 57a85a6c34a2..ddfe58b1ae79 100644
---- a/arch/arm/boot/dts/am4372.dtsi
-+++ b/arch/arm/boot/dts/am4372.dtsi
-@@ -434,6 +434,84 @@ pruss_tm: target-module@54400000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x54400000 0x80000>;
-+
-+ pruss1: pruss@0 {
-+ compatible = "ti,am4376-pruss1";
-+ reg = <0x0 0x40000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ pruss1_mem: memories@0 {
-+ reg = <0x0 0x2000>,
-+ <0x2000 0x2000>,
-+ <0x10000 0x8000>;
-+ reg-names = "dram0", "dram1",
-+ "shrdram2";
-+ };
-+
-+ pruss1_cfg: cfg@26000 {
-+ compatible = "ti,pruss-cfg", "syscon";
-+ reg = <0x26000 0x2000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x26000 0x2000>;
-+
-+ clocks {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pruss1_iepclk_mux: iepclk-mux@30 {
-+ reg = <0x30>;
-+ #clock-cells = <0>;
-+ clocks = <&sysclk_div>, /* icss_iep_gclk */
-+ <&pruss_ocp_gclk>; /* icss_ocp_gclk */
-+ };
-+ };
-+ };
-+
-+ pruss1_mii_rt: mii-rt@32000 {
-+ compatible = "ti,pruss-mii", "syscon";
-+ reg = <0x32000 0x58>;
-+ };
-+
-+ pruss1_intc: interrupt-controller@20000 {
-+ compatible = "ti,pruss-intc";
-+ reg = <0x20000 0x2000>;
-+ interrupt-controller;
-+ #interrupt-cells = <3>;
-+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "host_intr0", "host_intr1",
-+ "host_intr2", "host_intr3",
-+ "host_intr4",
-+ "host_intr6", "host_intr7";
-+ ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
-+ };
-+
-+ pru1_0: pru@34000 {
-+ compatible = "ti,am4376-pru";
-+ reg = <0x34000 0x3000>,
-+ <0x22000 0x400>,
-+ <0x22400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am437x-pru1_0-fw";
-+ };
-+
-+ pru1_1: pru@38000 {
-+ compatible = "ti,am4376-pru";
-+ reg = <0x38000 0x3000>,
-+ <0x24000 0x400>,
-+ <0x24400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am437x-pru1_1-fw";
-+ };
-+ };
- };
-
- target-module@50000000 {
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0008-ARM-dts-am4372-Add-the-PRU-ICSS0-DT-node.patch b/patches/dts/omap_pruss/0008-ARM-dts-am4372-Add-the-PRU-ICSS0-DT-node.patch
deleted file mode 100644
index 89cc51622cc9a5bad635b13e7a5d95ebf77e95f3..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0008-ARM-dts-am4372-Add-the-PRU-ICSS0-DT-node.patch
+++ /dev/null
@@ -1,139 +0,0 @@
-From b622dbbd42f69e26c4df2485bebbf69fafcdefcd Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:18 -0500
-Subject: [PATCH 08/11] ARM: dts: am4372: Add the PRU-ICSS0 DT node
-
-The AM4376+ SoCs have a second smaller PRU-ICSS subsystem (PRUSS0) in
-addition to the primary PRUSS1 instance. The PRUSS0 has less DRAM
-per PRU, and no Shared DRAM among other minor differences. The IEP
-and MII_RT modules even though present within the IP are not pinned
-out.
-
-This PRUSS0 instance has a weird SoC integration. It shares the same
-L3 OCP interconnect interface with PRUSS1, and also shares its reset
-line and clocks. Any external accesses from PRUSS0 requires the PRUSS1's
-PRUSS_SYSCFG register to be programmed properly. That said, it is its
-own IP instance (a cut-down version), and so it has been added as an
-independent node (sibling node to PRUSS1 node) and a child node of the
-corresponding PRUSS target module interconnect node. This allows the
-PRUSS0 instance to be enabled/disabled independently of the PRUSS1
-instance.
-
-The nodes are added under the corresponding interconnect target module
-node in the common am4372 dtsi file. The PRU-ICSS instances are not
-supported on AM4372 SoC though in the AM437x family, so the interconnect
-target module node should be disabled in any derivative board dts file that
-uses AM4372 SoCs. The individual PRUSS node can be disabled in the
-corresponding board dts file if desired.
-
-The default names for the firmware images for each PRU core are defined
-as follows (these can be adjusted either in derivative board dts files or
-through sysfs at runtime if required):
- PRU-ICSS0 PRU0 Core: am437x-pru0_0-fw
- PRU-ICSS0 PRU1 Core: am437x-pru0_1-fw
-
-Note:
-1. There are few more sub-modules like the Industrial Ethernet Peripheral
- (IEP), eCAP, UART, that do not have bindings and so will be added in the
- future. Only UART is pinned out, so others should be added in disabled
- state if added.
-2. The PRUSS0 INTC on AM437x SoCs routes the host interrupt 5 to the other
- PRUSS1, so it is already marked reserved through the 'ti,irqs-reserved'
- property.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am4372.dtsi | 77 +++++++++++++++++++++++++++++++++++
- 1 file changed, 77 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
-index ddfe58b1ae79..2200a09c2065 100644
---- a/arch/arm/boot/dts/am4372.dtsi
-+++ b/arch/arm/boot/dts/am4372.dtsi
-@@ -512,6 +512,83 @@ pru1_1: pru@38000 {
- firmware-name = "am437x-pru1_1-fw";
- };
- };
-+
-+ pruss0: pruss@40000 {
-+ compatible = "ti,am4376-pruss0";
-+ reg = <0x40000 0x40000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ pruss0_mem: memories@40000 {
-+ reg = <0x40000 0x1000>,
-+ <0x42000 0x1000>;
-+ reg-names = "dram0", "dram1";
-+ };
-+
-+ pruss0_cfg: cfg@66000 {
-+ compatible = "ti,pruss-cfg", "syscon";
-+ reg = <0x66000 0x2000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x66000 0x2000>;
-+
-+ clocks {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pruss0_iepclk_mux: iepclk-mux@30 {
-+ reg = <0x30>;
-+ #clock-cells = <0>;
-+ clocks = <&sysclk_div>, /* icss_iep_gclk */
-+ <&pruss_ocp_gclk>; /* icss_ocp_gclk */
-+ };
-+ };
-+ };
-+
-+ pruss0_mii_rt: mii-rt@72000 {
-+ compatible = "ti,pruss-mii", "syscon";
-+ reg = <0x72000 0x58>;
-+ status = "disabled";
-+ };
-+
-+ pruss0_intc: interrupt-controller@60000 {
-+ compatible = "ti,pruss-intc";
-+ reg = <0x60000 0x2000>;
-+ interrupt-controller;
-+ #interrupt-cells = <3>;
-+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "host_intr0", "host_intr1",
-+ "host_intr2", "host_intr3",
-+ "host_intr4",
-+ "host_intr6", "host_intr7";
-+ ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
-+ };
-+
-+ pru0_0: pru@74000 {
-+ compatible = "ti,am4376-pru";
-+ reg = <0x74000 0x1000>,
-+ <0x62000 0x400>,
-+ <0x62400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am437x-pru0_0-fw";
-+ };
-+
-+ pru0_1: pru@78000 {
-+ compatible = "ti,am4376-pru";
-+ reg = <0x78000 0x1000>,
-+ <0x64000 0x400>,
-+ <0x64400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am437x-pru0_1-fw";
-+ };
-+ };
- };
-
- target-module@50000000 {
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0009-ARM-dts-am4372-Add-PRUSS-MDIO-controller-node.patch b/patches/dts/omap_pruss/0009-ARM-dts-am4372-Add-PRUSS-MDIO-controller-node.patch
deleted file mode 100644
index 2d941d3dc5b1efba0165a616525bb526a9ae9b73..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0009-ARM-dts-am4372-Add-PRUSS-MDIO-controller-node.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From b859f04a513fb55bc96aed8d8d4d19a709647740 Mon Sep 17 00:00:00 2001
-From: "Andrew F. Davis" <afd@ti.com>
-Date: Thu, 29 Jul 2021 17:46:19 -0500
-Subject: [PATCH 09/11] ARM: dts: am4372: Add PRUSS MDIO controller node
-
-The PRU-ICSS1 instance on AM437x SoCs has a MDIO sub-module that
-can be used to control external PHYs associated with the Industrial
-Ethernet peripherals within the PRUSS. The MDIO module used within
-this PRU-ICSS is an instance of the MDIO Controller used in TI
-Davinci SoCs. The same bus frequency of 1 MHz is chosen as the
-regular MDIO node. Note that there is no MDIO node added to the
-smaller PRU-ICSS0 instance as the MDIO pins are not pinned out.
-
-The node is added and enabled in the common am4372.dtsi file by
-default, and disabled in all the existing AM437x board dts files.
-This node needs pinctrl lines, and so should be enabled only on
-boards where they are actually wired and pinned out for PRUSS
-Ethernet. Any new board dts file should disable these if they
-are not sure.
-
-Signed-off-by: Andrew F. Davis <afd@ti.com>
-[s-anna@ti.com: fix reg address, add commit description]
-Signed-off-by: Suman Anna <s-anna@ti.com>
----
- arch/arm/boot/dts/am4372.dtsi | 10 ++++++++++
- arch/arm/boot/dts/am437x-cm-t43.dts | 4 ++++
- arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++++
- arch/arm/boot/dts/am437x-idk-evm.dts | 4 ++++
- arch/arm/boot/dts/am437x-sk-evm.dts | 4 ++++
- arch/arm/boot/dts/am43x-epos-evm.dts | 4 ++++
- 6 files changed, 30 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
-index 2200a09c2065..61a1d88f9df6 100644
---- a/arch/arm/boot/dts/am4372.dtsi
-+++ b/arch/arm/boot/dts/am4372.dtsi
-@@ -511,6 +511,16 @@ pru1_1: pru@38000 {
- reg-names = "iram", "control", "debug";
- firmware-name = "am437x-pru1_1-fw";
- };
-+
-+ pruss1_mdio: mdio@32400 {
-+ compatible = "ti,davinci_mdio";
-+ reg = <0x32400 0x90>;
-+ clocks = <&dpll_core_m4_ck>;
-+ clock-names = "fck";
-+ bus_freq = <1000000>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
- };
-
- pruss0: pruss@40000 {
-diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts
-index a83f46ed0c9a..5ce8e684e7d3 100644
---- a/arch/arm/boot/dts/am437x-cm-t43.dts
-+++ b/arch/arm/boot/dts/am437x-cm-t43.dts
-@@ -416,3 +416,7 @@ &cpu {
- <600000 1100000>,
- <300000 950000>;
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
-index e2677682b540..c2e4896076e7 100644
---- a/arch/arm/boot/dts/am437x-gp-evm.dts
-+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
-@@ -1118,3 +1118,7 @@ &rtc {
- &cpu {
- cpu0-supply = <&dcdc2>;
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
-index 2dc525512266..53f64e3ce735 100644
---- a/arch/arm/boot/dts/am437x-idk-evm.dts
-+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
-@@ -537,3 +537,7 @@ opp100-600000000 {
- opp-suspend;
- };
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
-index 496ed34f7755..20a34d2d85df 100644
---- a/arch/arm/boot/dts/am437x-sk-evm.dts
-+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
-@@ -892,3 +892,7 @@ vpfe0_ep: endpoint {
- };
- };
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
-index aae0af10a5b1..d16aa2221c91 100644
---- a/arch/arm/boot/dts/am43x-epos-evm.dts
-+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
-@@ -1018,3 +1018,7 @@ &mux_synctimer32k_ck {
- &cpu {
- cpu0-supply = <&dcdc2>;
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0010-ARM-dts-am57xx-Add-PRU-ICSS-nodes.patch b/patches/dts/omap_pruss/0010-ARM-dts-am57xx-Add-PRU-ICSS-nodes.patch
deleted file mode 100644
index b6e3fe412efadd42b24f11ce8c659d56876b2ce0..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0010-ARM-dts-am57xx-Add-PRU-ICSS-nodes.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From 5c6e11a998d259741154eada156be440d9b98037 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:20 -0500
-Subject: [PATCH 10/11] ARM: dts: am57xx: Add PRU-ICSS nodes
-
-Add the DT nodes for the PRU-ICSS1 and PRU-ICSS2 processor subsystems
-that are present on AM57xx family of SoCs. Each PRU-ICSS instance is
-represented by a pruss node and other child nodes. The two PRU-ICSSs
-are identical to each other. They are not supported on DRA7xx SoCs in
-general, so the nodes are added under the respective interconnect target
-module nodes in a common am57-pruss.dtsi file. The file is already
-included only in the AM57xx related board files.
-
-The PRU-ICSSs on AM57xx are very similar to the PRUSS in AM33xx and AM437x
-except for variations in the RAM sizes and the number of interrupts coming
-into the MPU INTC. The interrupt events into the PRU-ICSS also requires
-programming of the corresponding crossbars properly.
-
-The PRUSS subsystem node contains the entire address space. The various
-sub-modules of the PRU-ICSS are represented as individual child nodes
-(so platform devices themselves) of the PRUSS subsystem node. These
-include the two PRU cores and the interrupt controller. All the Data
-RAMs are represented within a child node of its own named 'memories'
-without any compatible. The Real Time Media Independent Interface
-controller (MII_RT), and the CFG sub-module are represented as syscon
-nodes. The PRUSS CFG module has a clock mux for IEP clock, this clk
-node is added under the CFG child node 'clocks'. The default source
-for this mux clock is the ICSS_IEP_CLK clock.
-
-The DT nodes use all standard properties. The regs property in the PRU
-nodes define the addresses for the Instruction RAM, the Debug and Control
-sub-modules for that PRU core. The firmware for each PRU core is defined
-through a 'firmware-name' property.
-
-The default names for the firmware images for each PRU core are defined
-as follows (these can be adjusted either in derivative board dts files or
-through sysfs at runtime if required):
- PRU-ICSS1 PRU0 Core: am57xx-pru1_0-fw
- PRU-ICSS1 PRU1 Core: am57xx-pru1_1-fw
- PRU-ICSS2 PRU0 Core: am57xx-pru2_0-fw
- PRU-ICSS2 PRU1 Core: am57xx-pru2_1-fw
-
-Note:
-1. There are few more sub-modules like the Industrial Ethernet Peripheral
- (IEPs), MDIO, UART, eCAP that do not have bindings and so will be added
- in the future.
-2. The PRUSS INTC on AM57xx SoCs also connect the host interrupts 6 and 7
- as possible DMA events, so use the 'ti,irqs-reserved' property in
- derivative board dts files _if_ any of them should not be handled by
- the host OS.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
-Signed-off-by: Roger Quadros <rogerq@ti.com>
----
- arch/arm/boot/dts/am57-pruss.dtsi | 158 +++++++++++++++++++++++++++++-
- 1 file changed, 157 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/am57-pruss.dtsi
-index 032c1acfcda3..494d56830b34 100644
---- a/arch/arm/boot/dts/am57-pruss.dtsi
-+++ b/arch/arm/boot/dts/am57-pruss.dtsi
-@@ -1,6 +1,6 @@
- // SPDX-License-Identifier: GPL-2.0-only
- /*
-- * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
-+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Common PRUSS data for TI AM57xx platforms
- */
-@@ -25,6 +25,84 @@ pruss1_tm: target-module@4b226000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x4b200000 0x80000>;
-+
-+ pruss1: pruss@0 {
-+ compatible = "ti,am5728-pruss";
-+ reg = <0x0 0x80000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ pruss1_mem: memories@0 {
-+ reg = <0x0 0x2000>,
-+ <0x2000 0x2000>,
-+ <0x10000 0x8000>;
-+ reg-names = "dram0", "dram1",
-+ "shrdram2";
-+ };
-+
-+ pruss1_cfg: cfg@26000 {
-+ compatible = "ti,pruss-cfg", "syscon";
-+ reg = <0x26000 0x2000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x26000 0x2000>;
-+
-+ clocks {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pruss1_iepclk_mux: iepclk-mux@30 {
-+ reg = <0x30>;
-+ #clock-cells = <0>;
-+ clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */
-+ <&dpll_gmac_h13x2_ck>; /* icss_clk */
-+ };
-+ };
-+ };
-+
-+ pruss1_mii_rt: mii-rt@32000 {
-+ compatible = "ti,pruss-mii", "syscon";
-+ reg = <0x32000 0x58>;
-+ };
-+
-+ pruss1_intc: interrupt-controller@20000 {
-+ compatible = "ti,pruss-intc";
-+ reg = <0x20000 0x2000>;
-+ interrupt-controller;
-+ #interrupt-cells = <3>;
-+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "host_intr0", "host_intr1",
-+ "host_intr2", "host_intr3",
-+ "host_intr4", "host_intr5",
-+ "host_intr6", "host_intr7";
-+ };
-+
-+ pru1_0: pru@34000 {
-+ compatible = "ti,am5728-pru";
-+ reg = <0x34000 0x3000>,
-+ <0x22000 0x400>,
-+ <0x22400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am57xx-pru1_0-fw";
-+ };
-+
-+ pru1_1: pru@38000 {
-+ compatible = "ti,am5728-pru";
-+ reg = <0x38000 0x3000>,
-+ <0x24000 0x400>,
-+ <0x24400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am57xx-pru1_1-fw";
-+ };
-+ };
- };
-
- pruss2_tm: target-module@4b2a6000 {
-@@ -46,5 +124,83 @@ pruss2_tm: target-module@4b2a6000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x4b280000 0x80000>;
-+
-+ pruss2: pruss@0 {
-+ compatible = "ti,am5728-pruss";
-+ reg = <0x0 0x80000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ pruss2_mem: memories@0 {
-+ reg = <0x0 0x2000>,
-+ <0x2000 0x2000>,
-+ <0x10000 0x8000>;
-+ reg-names = "dram0", "dram1",
-+ "shrdram2";
-+ };
-+
-+ pruss2_cfg: cfg@26000 {
-+ compatible = "ti,pruss-cfg", "syscon";
-+ reg = <0x26000 0x2000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x26000 0x2000>;
-+
-+ clocks {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pruss2_iepclk_mux: iepclk-mux@30 {
-+ reg = <0x30>;
-+ #clock-cells = <0>;
-+ clocks = <&dpll_gmac_m3x2_ck>, /* icss_iep_clk */
-+ <&dpll_gmac_h13x2_ck>; /* icss_clk */
-+ };
-+ };
-+ };
-+
-+ pruss2_mii_rt: mii-rt@32000 {
-+ compatible = "ti,pruss-mii", "syscon";
-+ reg = <0x32000 0x58>;
-+ };
-+
-+ pruss2_intc: interrupt-controller@20000 {
-+ compatible = "ti,pruss-intc";
-+ reg = <0x20000 0x2000>;
-+ interrupt-controller;
-+ #interrupt-cells = <3>;
-+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "host_intr0", "host_intr1",
-+ "host_intr2", "host_intr3",
-+ "host_intr4", "host_intr5",
-+ "host_intr6", "host_intr7";
-+ };
-+
-+ pru2_0: pru@34000 {
-+ compatible = "ti,am5728-pru";
-+ reg = <0x34000 0x3000>,
-+ <0x22000 0x400>,
-+ <0x22400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am57xx-pru2_0-fw";
-+ };
-+
-+ pru2_1: pru@38000 {
-+ compatible = "ti,am5728-pru";
-+ reg = <0x38000 0x3000>,
-+ <0x24000 0x400>,
-+ <0x24400 0x100>;
-+ reg-names = "iram", "control", "debug";
-+ firmware-name = "am57xx-pru2_1-fw";
-+ };
-+ };
- };
- };
---
-2.30.2
-
diff --git a/patches/dts/omap_pruss/0011-ARM-dts-am57xx-Add-PRUSS-MDIO-controller-nodes.patch b/patches/dts/omap_pruss/0011-ARM-dts-am57xx-Add-PRUSS-MDIO-controller-nodes.patch
deleted file mode 100644
index 98e5ace458a45a6a40a82aa88deb3e23d381f695..0000000000000000000000000000000000000000
--- a/patches/dts/omap_pruss/0011-ARM-dts-am57xx-Add-PRUSS-MDIO-controller-nodes.patch
+++ /dev/null
@@ -1,151 +0,0 @@
-From 175d80f8aab45e46470b2a9ce483f828c4453a79 Mon Sep 17 00:00:00 2001
-From: Suman Anna <s-anna@ti.com>
-Date: Thu, 29 Jul 2021 17:46:21 -0500
-Subject: [PATCH 11/11] ARM: dts: am57xx: Add PRUSS MDIO controller nodes
-
-The PRUSSs on AM57xx SoCs contain an MDIO controller that can
-be used to control external PHYs associated with the Industrial
-Ethernet peripherals within each PRUSS. The MDIO module used
-within the PRU-ICSS is an instance of the MDIO Controller used
-in TI Davinci SoCs. The same bus frequency of 1 MHz is chosen as
-the regular MDIO node.
-
-The nodes are added in the common am57-pruss.dtsi file and enabled
-by default, but are disabled in all the existing AM57xx board dts
-files. These nodes need pinctrl lines, and so should be enabled
-only on boards where they are actually wired and pinned out for
-PRUSS Ethernet. Any new board dts file should disable these if
-they are not sure.
-
-Signed-off-by: Suman Anna <s-anna@ti.com>
-Signed-off-by: Andrew F. Davis <afd@ti.com>
----
- arch/arm/boot/dts/am57-pruss.dtsi | 20 +++++++++++++++++++
- arch/arm/boot/dts/am571x-idk.dts | 8 ++++++++
- arch/arm/boot/dts/am572x-idk.dts | 8 ++++++++
- arch/arm/boot/dts/am574x-idk.dts | 8 ++++++++
- .../boot/dts/am57xx-beagle-x15-common.dtsi | 8 ++++++++
- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 8 ++++++++
- 6 files changed, 60 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/am57-pruss.dtsi
-index 494d56830b34..46c5383f0eee 100644
---- a/arch/arm/boot/dts/am57-pruss.dtsi
-+++ b/arch/arm/boot/dts/am57-pruss.dtsi
-@@ -102,6 +102,16 @@ pru1_1: pru@38000 {
- reg-names = "iram", "control", "debug";
- firmware-name = "am57xx-pru1_1-fw";
- };
-+
-+ pruss1_mdio: mdio@32400 {
-+ compatible = "ti,davinci_mdio";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ clocks = <&dpll_gmac_h13x2_ck>;
-+ clock-names = "fck";
-+ bus_freq = <1000000>;
-+ reg = <0x32400 0x90>;
-+ };
- };
- };
-
-@@ -201,6 +211,16 @@ pru2_1: pru@38000 {
- reg-names = "iram", "control", "debug";
- firmware-name = "am57xx-pru2_1-fw";
- };
-+
-+ pruss2_mdio: mdio@32400 {
-+ compatible = "ti,davinci_mdio";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ clocks = <&dpll_gmac_h13x2_ck>;
-+ clock-names = "fck";
-+ bus_freq = <1000000>;
-+ reg = <0x32400 0x90>;
-+ };
- };
- };
- };
-diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
-index e81078c2d00d..48425020281a 100644
---- a/arch/arm/boot/dts/am571x-idk.dts
-+++ b/arch/arm/boot/dts/am571x-idk.dts
-@@ -208,3 +208,11 @@ &mmc2 {
- pinctrl-1 = <&mmc2_pins_hs>;
- pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-+
-+&pruss2_mdio {
-+ status = "disabled";
-+};
-diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
-index 6504265f3f7e..94a738cb0a4d 100644
---- a/arch/arm/boot/dts/am572x-idk.dts
-+++ b/arch/arm/boot/dts/am572x-idk.dts
-@@ -27,3 +27,11 @@ &mmc2 {
- pinctrl-1 = <&mmc2_pins_hs>;
- pinctrl-2 = <&mmc2_pins_ddr_rev20>;
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-+
-+&pruss2_mdio {
-+ status = "disabled";
-+};
-diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts
-index 1b8f3a28af05..c4bf9cb2c9dc 100644
---- a/arch/arm/boot/dts/am574x-idk.dts
-+++ b/arch/arm/boot/dts/am574x-idk.dts
-@@ -43,3 +43,11 @@ &m_can0 {
- &emif1 {
- status = "okay";
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-+
-+&pruss2_mdio {
-+ status = "disabled";
-+};
-diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
-index 6b82ecf803c5..994e69ab38d7 100644
---- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
-+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
-@@ -637,3 +637,11 @@ &dsp2 {
- status = "okay";
- memory-region = <&dsp2_memory_region>;
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-+
-+&pruss2_mdio {
-+ status = "disabled";
-+};
-diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
-index aed81568a297..2e94f32d9dfc 100644
---- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
-+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
-@@ -618,3 +618,11 @@ &gpio2_target {
- status = "okay";
- ti,no-reset-on-init;
- };
-+
-+&pruss1_mdio {
-+ status = "disabled";
-+};
-+
-+&pruss2_mdio {
-+ status = "disabled";
-+};
---
-2.30.2
-
diff --git a/patches/dts/omap_sancloud/0001-ARM-dts-am335x-sancloud-bbe-Fix-missing-pinctrl-refs.patch b/patches/dts/omap_sancloud/0001-ARM-dts-am335x-sancloud-bbe-Fix-missing-pinctrl-refs.patch
deleted file mode 100644
index 392b2730499b4c48eb6a6b3c8ad10504465ea573..0000000000000000000000000000000000000000
--- a/patches/dts/omap_sancloud/0001-ARM-dts-am335x-sancloud-bbe-Fix-missing-pinctrl-refs.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From fda013ac3fdb43645cb92baea492440eae3a163d Mon Sep 17 00:00:00 2001
-From: Paul Barker <paul.barker@sancloud.com>
-Date: Fri, 6 Aug 2021 09:59:06 +0100
-Subject: [PATCH 1/2] ARM: dts: am335x-sancloud-bbe: Fix missing pinctrl refs
-
-pinctrl settings for the USB hub, barometer & accelerometer need to be
-referenced from the relevant nodes to work.
-
-Signed-off-by: Paul Barker <paul.barker@sancloud.com>
----
- arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi | 2 ++
- arch/arm/boot/dts/am335x-sancloud-bbe.dts | 4 ++++
- 2 files changed, 6 insertions(+)
-
-diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-index bd9c21813192..1d6fdd9de759 100644
---- a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-+++ b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-@@ -88,6 +88,8 @@ &cpsw_emac0 {
-
- &i2c0 {
- usb2512b: usb-hub@2c {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb_hub_ctrl>;
- compatible = "microchip,usb2512b";
- reg = <0x2c>;
- reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
-diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-index 2a0ac9f5dda7..efbe93135dbe 100644
---- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-+++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
-@@ -32,6 +32,8 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_
-
- &i2c0 {
- lps331ap: barometer@5c {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lps3331ap_pins>;
- compatible = "st,lps331ap-press";
- st,drdy-int-pin = <1>;
- reg = <0x5c>;
-@@ -40,6 +42,8 @@ lps331ap: barometer@5c {
- };
-
- mpu6050: accelerometer@68 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mpu6050_pins>;
- compatible = "invensense,mpu6050";
- reg = <0x68>;
- interrupt-parent = <&gpio0>;
---
-2.30.2
-
diff --git a/patches/dts/omap_sancloud/0002-ARM-dts-am335x-sancloud-bbe-Drop-usb-wifi-comment.patch b/patches/dts/omap_sancloud/0002-ARM-dts-am335x-sancloud-bbe-Drop-usb-wifi-comment.patch
deleted file mode 100644
index ab1376e39407f5cc8855043e3795cce5c94f0a63..0000000000000000000000000000000000000000
--- a/patches/dts/omap_sancloud/0002-ARM-dts-am335x-sancloud-bbe-Drop-usb-wifi-comment.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 1aa678f383102e4295cfe09611eb210840d45f6f Mon Sep 17 00:00:00 2001
-From: Paul Barker <paul.barker@sancloud.com>
-Date: Fri, 6 Aug 2021 09:59:07 +0100
-Subject: [PATCH 2/2] ARM: dts: am335x-sancloud-bbe: Drop usb wifi comment
-
-The wifi chip on USB port 4 may not be present on all BBE variants.
-
-Signed-off-by: Paul Barker <paul.barker@sancloud.com>
----
- arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-index 1d6fdd9de759..8fc869afbd25 100644
---- a/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-+++ b/arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi
-@@ -93,6 +93,5 @@ usb2512b: usb-hub@2c {
- compatible = "microchip,usb2512b";
- reg = <0x2c>;
- reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
-- /* wifi on port 4 */
- };
- };
---
-2.30.2
-
diff --git a/patches/fixes/gcc/0001-ARM-Fix-instruction-set-selection-for-GCC-11.patch b/patches/fixes/gcc/0001-ARM-Fix-instruction-set-selection-for-GCC-11.patch
deleted file mode 100644
index 7844246f6ac9e19aca9a86d7dae35fb256716100..0000000000000000000000000000000000000000
--- a/patches/fixes/gcc/0001-ARM-Fix-instruction-set-selection-for-GCC-11.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From de01d1487f4727770deb2e8cbed8fcf211682c5b Mon Sep 17 00:00:00 2001
-From: Juerg Haefliger <juerg.haefliger@canonical.com>
-Date: Tue, 10 Aug 2021 08:13:50 +0200
-Subject: [PATCH] ARM: Fix instruction set selection for GCC 11
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-GCC 11 on ARM now complains like the following when trying to determine if
-an arch is supported. Presumably because it enforces the default option
-'--with-float=hard' which GCC 10 didn't do?
-
- $ arm-linux-gnueabihf-gcc-11 -march=armv7-a -c -x c /dev/null
- cc1: error: ‘-mfloat-abi=hard’: selected architecture lacks an FPU
-
-Due to that, the kernel build system selects the wrong compiler options
-which throws errros like this during the build:
-
- /tmp/ccrHfZPj.s: Assembler messages:
- /tmp/ccrHfZPj.s:116: Error: selected processor does not support `dmb ish' in ARM mode
- /tmp/ccrHfZPj.s:150: Error: selected processor does not support `isb ' in ARM mode
- /tmp/ccrHfZPj.s:160: Error: selected processor does not support `mrrc p15,1,r4,r5,c14' in ARM mode
- /tmp/ccrHfZPj.s:245: Error: selected processor does not support `dmb ish' in ARM mode
- /tmp/ccrHfZPj.s:503: Error: selected processor does not support `dmb ish' in ARM mode
- /tmp/ccrHfZPj.s:527: Error: selected processor does not support `dmb ish' in ARM mode
- /tmp/ccrHfZPj.s:698: Error: selected processor does not support `dmb ish' in ARM mode
- /tmp/ccrHfZPj.s:731: Error: selected processor does not support `isb ' in ARM mode
-
-Fix that by adding '-msoft-float' to KBUILD_CFLAGS before the definition of
-the 'arch-$(CONFIG_CPU_<foo>)' instruction selection macros.
-
-Signed-off-by: Juerg Haefliger <juergh@canonical.com>
----
- arch/arm/Makefile | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/Makefile b/arch/arm/Makefile
-index 847c31e7c368..bd0148ee8338 100644
---- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -56,6 +56,9 @@ endif
- #
- KBUILD_CFLAGS += $(call cc-option,-fno-ipa-sra)
-
-+# Need -msoft-float for gcc 11 for the below instruction set selection
-+KBUILD_CFLAGS += -msoft-float
-+
- # This selects which instruction set is used.
- # Note that GCC does not numerically define an architecture version
- # macro, but instead defines a whole series of macros which makes
-@@ -125,7 +128,7 @@ AFLAGS_ISA :=$(CFLAGS_ISA)
- endif
-
- # Need -Uarm for gcc < 3.x
--KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
-+KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -Uarm
- KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
-
- CHECKFLAGS += -D__arm__
---
-2.30.2
-
diff --git a/patches/greybus/0001-change-MAX_NUM_UDC-from-2-to-4.patch b/patches/greybus/0001-change-MAX_NUM_UDC-from-2-to-4.patch
deleted file mode 100644
index 9db9efb9ce6ff2985883b51595486862ab4adad1..0000000000000000000000000000000000000000
--- a/patches/greybus/0001-change-MAX_NUM_UDC-from-2-to-4.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From eff9413c00851c3941899f3dd509023a13c566ac Mon Sep 17 00:00:00 2001
-From: Vaishnav M A <mavaishnav007@gmail.com>
-Date: Mon, 26 Aug 2019 02:06:27 +0530
-Subject: [PATCH] change MAX_NUM_UDC from 2 to 4
-
-The project clickboard support through greybus(https://github.com/vaishnav98/gbsim/wiki/Beagleboard-GSoC-'19:--Clickboard-Support-Under-Greybus) uses dummy_hcd emulated UDC for running the greybus simulator and requires an instance of emulated UDC for each mikrobus port, since the Beaglebone Black Mikrobus Cape has 4 Mikrobus Slots for serving all of the ports through greybus simulator at a time requires 4 emulated dummy_hcd UDC.
----
- drivers/usb/gadget/udc/dummy_hcd.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/usb/gadget/udc/dummy_hcd.c b/drivers/usb/gadget/udc/dummy_hcd.c
-index c0780e414534..4bebbdbdb626 100644
---- a/drivers/usb/gadget/udc/dummy_hcd.c
-+++ b/drivers/usb/gadget/udc/dummy_hcd.c
-@@ -2719,7 +2719,7 @@ static struct platform_driver dummy_hcd_driver = {
- };
-
- /*-------------------------------------------------------------------------*/
--#define MAX_NUM_UDC 2
-+#define MAX_NUM_UDC 4
- static struct platform_device *the_udc_pdev[MAX_NUM_UDC];
- static struct platform_device *the_hcd_pdev[MAX_NUM_UDC];
-
---
-2.23.0.rc1
-
diff --git a/patches/ref_omap2plus_defconfig b/patches/ref_omap2plus_defconfig
index cb41136fd96eb9e632ccf356d5ea0a4a4f037b0f..ec3b2fef3763a397918b01b8e8be99cc52c399fd 100644
--- a/patches/ref_omap2plus_defconfig
+++ b/patches/ref_omap2plus_defconfig
@@ -1,15 +1,15 @@
#
# Automatically generated file; DO NOT EDIT.
-# Linux/arm 6.1.0-rc5 Kernel Configuration
+# Linux/arm 6.1.0-rc7 Kernel Configuration
#
-CONFIG_CC_VERSION_TEXT="arm-linux-gnueabi-gcc (GCC) 11.3.0"
+CONFIG_CC_VERSION_TEXT="arm-linux-gnueabi-gcc (GCC) 12.2.0"
CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=110300
+CONFIG_GCC_VERSION=120200
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=23800
+CONFIG_AS_VERSION=23900
CONFIG_LD_IS_BFD=y
-CONFIG_LD_VERSION=23800
+CONFIG_LD_VERSION=23900
CONFIG_LLD_VERSION=0
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
@@ -149,6 +149,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC12_NO_ARRAY_BOUNDS=y
+CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
@@ -509,6 +510,7 @@ CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_PARAVIRT is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
# end of Kernel Features
#
@@ -921,6 +923,7 @@ CONFIG_NET_UDP_TUNNEL=m
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
+CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INET_TUNNEL=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
@@ -6929,10 +6932,12 @@ CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"
#
# Memory initialization
#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+# CONFIG_INIT_STACK_NONE is not set
+# CONFIG_INIT_STACK_ALL_PATTERN is not set
+CONFIG_INIT_STACK_ALL_ZERO=y
# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
diff --git a/patches/rt/0001-merge-CONFIG_PREEMPT_RT-Patch-Set.patch b/patches/rt/0001-merge-CONFIG_PREEMPT_RT-Patch-Set.patch
index c79759bb3d4284c0050a794819317c80aa8a0070..e2897c7b92dcfdda703f7f73af3b34f6d27c1b14 100644
--- a/patches/rt/0001-merge-CONFIG_PREEMPT_RT-Patch-Set.patch
+++ b/patches/rt/0001-merge-CONFIG_PREEMPT_RT-Patch-Set.patch
@@ -1,9 +1,9 @@
-From 6461f990edd4d9e184126f13bba2df1711b9a7e3 Mon Sep 17 00:00:00 2001
+From 8932d53043c0b50327c9344af0f2850042d1620a Mon Sep 17 00:00:00 2001
From: Robert Nelson <robertcnelson@gmail.com>
-Date: Mon, 14 Nov 2022 13:57:25 -0600
+Date: Fri, 23 Dec 2022 16:05:59 -0600
Subject: [PATCH] merge: CONFIG_PREEMPT_RT Patch Set
-patch-6.1-rc5-rt3.patch.xz
+patch-6.1-rc7-rt5.patch.xz
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
@@ -1221,7 +1221,7 @@ index 98d6386b7f39..48ae6d810f8f 100644
static void ena_queue_stats(struct ena_adapter *adapter, u64 **data)
diff --git a/drivers/net/ethernet/amazon/ena/ena_netdev.c b/drivers/net/ethernet/amazon/ena/ena_netdev.c
-index d350eeec8bad..df83f04b0980 100644
+index 5a454b58498f..a95529a69cbb 100644
--- a/drivers/net/ethernet/amazon/ena/ena_netdev.c
+++ b/drivers/net/ethernet/amazon/ena/ena_netdev.c
@@ -3268,10 +3268,10 @@ static void ena_get_stats64(struct net_device *netdev,
@@ -1698,10 +1698,10 @@ index d3e3ac242bfc..5a229a01f49d 100644
.stat_name = cpu_to_be32(TX_WAKE_CNT),
.value = cpu_to_be64(priv->tx[idx].wake_queue),
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
-index 4cb2421e71a7..813d5b3d7b58 100644
+index 028577943ec5..0ec5730b1788 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
-@@ -2486,7 +2486,7 @@ static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
+@@ -2488,7 +2488,7 @@ static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
unsigned int start;
do {
@@ -1710,7 +1710,7 @@ index 4cb2421e71a7..813d5b3d7b58 100644
if (is_tx) {
stats->tx_bytes += ring->stats.tx_bytes;
stats->tx_packets += ring->stats.tx_pkts;
-@@ -2520,7 +2520,7 @@ static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
+@@ -2522,7 +2522,7 @@ static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
stats->multicast += ring->stats.rx_multicast;
stats->rx_length_errors += ring->stats.err_pkt_len;
}
@@ -1925,7 +1925,7 @@ index a056e1545615..d79ead5e8d0c 100644
/* Once we successfully copy the stats in, update the data pointer */
*data += size;
diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c
-index 0f6718719453..73e02a8ffa9a 100644
+index ca2898467dcb..4b41e0c78b7e 100644
--- a/drivers/net/ethernet/intel/ice/ice_main.c
+++ b/drivers/net/ethernet/intel/ice/ice_main.c
@@ -6370,10 +6370,10 @@ ice_fetch_u64_stats_per_ring(struct u64_stats_sync *syncp,
@@ -2254,7 +2254,7 @@ index ff3e361e06e7..81dc57a69fd0 100644
es->skb_alloc_error += skb_alloc_error;
es->refill_error += refill_error;
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-index eb0fb8128096..116e53172072 100644
+index b399bdb1ca36..6d4c778b10fb 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -2008,7 +2008,7 @@ mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats)
@@ -2319,7 +2319,7 @@ index ab33ba1c3023..ff97b140886a 100644
stats->tx_packets = _packets;
stats->tx_bytes = _bytes;
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-index 7cd381530aa4..789268b15106 100644
+index 1d36619c5ec9..81349cf15ce0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -865,7 +865,7 @@ static void mtk_get_stats64(struct net_device *dev,
@@ -2340,7 +2340,7 @@ index 7cd381530aa4..789268b15106 100644
storage->tx_errors = dev->stats.tx_errors;
storage->rx_dropped = dev->stats.rx_dropped;
-@@ -3684,13 +3684,13 @@ static void mtk_get_ethtool_stats(struct net_device *dev,
+@@ -3688,13 +3688,13 @@ static void mtk_get_ethtool_stats(struct net_device *dev,
do {
data_dst = data;
@@ -2470,7 +2470,7 @@ index 27f4786ace4f..a5ca5c4a7896 100644
stats->tx_bytes += data[1];
stats->tx_errors += data[2];
diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c b/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
-index 22a5d2419084..f6b09eed73dc 100644
+index 991059d6cb32..e82ddb0677aa 100644
--- a/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
+++ b/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
@@ -686,7 +686,7 @@ static u64 *nfp_vnic_get_sw_stats(struct net_device *netdev, u64 *data)
@@ -2874,10 +2874,10 @@ index 1c64d5347b8e..78253ad57b2e 100644
*data += IFB_Q_STATS_LEN;
}
diff --git a/drivers/net/ipvlan/ipvlan_main.c b/drivers/net/ipvlan/ipvlan_main.c
-index 54c94a69c2bb..b6bfa9fdca62 100644
+index 796a38f9d7b2..b15dd9a3ad54 100644
--- a/drivers/net/ipvlan/ipvlan_main.c
+++ b/drivers/net/ipvlan/ipvlan_main.c
-@@ -299,13 +299,13 @@ static void ipvlan_get_stats64(struct net_device *dev,
+@@ -301,13 +301,13 @@ static void ipvlan_get_stats64(struct net_device *dev,
for_each_possible_cpu(idx) {
pcptr = per_cpu_ptr(ipvlan->pcpu_stats, idx);
do {
@@ -2911,7 +2911,7 @@ index 14e8d04cb434..c4ad98d39ea6 100644
*packets += tpackets;
}
diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c
-index 85376d2f24ca..a7b46219bab7 100644
+index f41f67b583db..d73b9d535b7a 100644
--- a/drivers/net/macsec.c
+++ b/drivers/net/macsec.c
@@ -2793,9 +2793,9 @@ static void get_rx_sc_stats(struct net_device *dev,
@@ -2951,7 +2951,7 @@ index 85376d2f24ca..a7b46219bab7 100644
sum->OutPktsUntagged += tmp.OutPktsUntagged;
sum->InPktsUntagged += tmp.InPktsUntagged;
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
-index 578897aaada0..28f9f917ff54 100644
+index b8cc55b2d721..99a971929c8e 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -948,13 +948,13 @@ static void macvlan_dev_get_stats64(struct net_device *dev,
@@ -2971,7 +2971,7 @@ index 578897aaada0..28f9f917ff54 100644
stats->rx_packets += rx_packets;
stats->rx_bytes += rx_bytes;
diff --git a/drivers/net/mhi_net.c b/drivers/net/mhi_net.c
-index 0b1b6f650104..ff302144029d 100644
+index 0b9d37979133..3d322ac4f6a5 100644
--- a/drivers/net/mhi_net.c
+++ b/drivers/net/mhi_net.c
@@ -104,19 +104,19 @@ static void mhi_ndo_get_stats64(struct net_device *ndev,
@@ -3102,7 +3102,7 @@ index 09682ea3354e..740506c44427 100644
result->xdp_tx_err += xdp_tx_err;
result->xdp_packets += packets;
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
-index 7106932c6f88..56dbd645d7c8 100644
+index 86e52454b5b5..19eee0655b99 100644
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -2069,18 +2069,18 @@ static void virtnet_stats(struct net_device *dev,
@@ -3599,19 +3599,19 @@ index fb1d5ec0940e..3e7203909d6a 100644
static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c
-index 41b8c6b27136..835b63793dd3 100644
+index 3f33014022f0..594378d3c065 100644
--- a/drivers/tty/serial/8250/8250_omap.c
+++ b/drivers/tty/serial/8250/8250_omap.c
-@@ -325,7 +325,7 @@ static void omap8250_restore_regs(struct uart_8250_port *up)
-
+@@ -328,7 +328,7 @@ static void omap8250_restore_regs(struct uart_8250_port *up)
/* drop TCR + TLR access, we setup XON/XOFF later */
- serial8250_out_MCR(up, up->mcr);
+ serial8250_out_MCR(up, mcr);
+
- serial_out(up, UART_IER, up->ier);
+ serial8250_set_IER(up, up->ier);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_dl_write(up, priv->quot);
-@@ -515,7 +515,7 @@ static void omap_8250_pm(struct uart_port *port, unsigned int state,
+@@ -518,7 +518,7 @@ static void omap_8250_pm(struct uart_port *port, unsigned int state,
serial_out(up, UART_EFR, efr | UART_EFR_ECB);
serial_out(up, UART_LCR, 0);
@@ -3620,7 +3620,7 @@ index 41b8c6b27136..835b63793dd3 100644
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, efr);
serial_out(up, UART_LCR, 0);
-@@ -636,7 +636,7 @@ static irqreturn_t omap8250_irq(int irq, void *dev_id)
+@@ -639,7 +639,7 @@ static irqreturn_t omap8250_irq(int irq, void *dev_id)
if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
unsigned long delay;
@@ -3629,7 +3629,7 @@ index 41b8c6b27136..835b63793dd3 100644
if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
port->ops->stop_rx(port);
} else {
-@@ -696,7 +696,7 @@ static int omap_8250_startup(struct uart_port *port)
+@@ -698,7 +698,7 @@ static int omap_8250_startup(struct uart_port *port)
goto err;
up->ier = UART_IER_RLSI | UART_IER_RDI;
@@ -3638,7 +3638,7 @@ index 41b8c6b27136..835b63793dd3 100644
#ifdef CONFIG_PM
up->capabilities |= UART_CAP_RPM;
-@@ -737,7 +737,7 @@ static void omap_8250_shutdown(struct uart_port *port)
+@@ -739,7 +739,7 @@ static void omap_8250_shutdown(struct uart_port *port)
serial_out(up, UART_OMAP_EFR2, 0x0);
up->ier = 0;
@@ -3647,7 +3647,7 @@ index 41b8c6b27136..835b63793dd3 100644
if (up->dma)
serial8250_release_dma(up);
-@@ -785,7 +785,7 @@ static void omap_8250_unthrottle(struct uart_port *port)
+@@ -787,7 +787,7 @@ static void omap_8250_unthrottle(struct uart_port *port)
up->dma->rx_dma(up);
up->ier |= UART_IER_RLSI | UART_IER_RDI;
port->read_status_mask |= UART_LSR_DR;
@@ -3656,7 +3656,7 @@ index 41b8c6b27136..835b63793dd3 100644
spin_unlock_irqrestore(&port->lock, flags);
pm_runtime_mark_last_busy(port->dev);
-@@ -876,7 +876,7 @@ static void __dma_rx_complete(void *param)
+@@ -878,7 +878,7 @@ static void __dma_rx_complete(void *param)
__dma_rx_do_complete(p);
if (!priv->throttled) {
p->ier |= UART_IER_RLSI | UART_IER_RDI;
@@ -3665,7 +3665,7 @@ index 41b8c6b27136..835b63793dd3 100644
if (!(priv->habit & UART_HAS_EFR2))
omap_8250_rx_dma(p);
}
-@@ -933,7 +933,7 @@ static int omap_8250_rx_dma(struct uart_8250_port *p)
+@@ -935,7 +935,7 @@ static int omap_8250_rx_dma(struct uart_8250_port *p)
* callback to run.
*/
p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
@@ -3674,7 +3674,7 @@ index 41b8c6b27136..835b63793dd3 100644
}
goto out;
}
-@@ -1146,12 +1146,12 @@ static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
+@@ -1148,12 +1148,12 @@ static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
* periodic timeouts, re-enable interrupts.
*/
up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
@@ -3690,7 +3690,7 @@ index 41b8c6b27136..835b63793dd3 100644
}
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
-index fe8662cd9402..2fc63f17deb1 100644
+index 388172289627..8dab3b7ab3c9 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -743,7 +743,7 @@ static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
@@ -3876,7 +3876,7 @@ index fe8662cd9402..2fc63f17deb1 100644
serial8250_rpm_put(up);
}
-@@ -2152,8 +2199,7 @@ static void serial8250_put_poll_char(struct uart_port *port,
+@@ -2155,8 +2202,7 @@ static void serial8250_put_poll_char(struct uart_port *port,
/*
* First save the IER then disable the interrupts
*/
@@ -3886,7 +3886,7 @@ index fe8662cd9402..2fc63f17deb1 100644
wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
/*
-@@ -2166,7 +2212,7 @@ static void serial8250_put_poll_char(struct uart_port *port,
+@@ -2169,7 +2215,7 @@ static void serial8250_put_poll_char(struct uart_port *port,
* and restore the IER
*/
wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
@@ -3895,7 +3895,7 @@ index fe8662cd9402..2fc63f17deb1 100644
serial8250_rpm_put(up);
}
-@@ -2175,8 +2221,10 @@ static void serial8250_put_poll_char(struct uart_port *port,
+@@ -2178,8 +2224,10 @@ static void serial8250_put_poll_char(struct uart_port *port,
int serial8250_do_startup(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
@@ -3906,7 +3906,7 @@ index fe8662cd9402..2fc63f17deb1 100644
int retval;
u16 lsr;
-@@ -2197,7 +2245,7 @@ int serial8250_do_startup(struct uart_port *port)
+@@ -2200,7 +2248,7 @@ int serial8250_do_startup(struct uart_port *port)
up->acr = 0;
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
serial_port_out(port, UART_EFR, UART_EFR_ECB);
@@ -3915,7 +3915,7 @@ index fe8662cd9402..2fc63f17deb1 100644
serial_port_out(port, UART_LCR, 0);
serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
-@@ -2207,7 +2255,7 @@ int serial8250_do_startup(struct uart_port *port)
+@@ -2210,7 +2258,7 @@ int serial8250_do_startup(struct uart_port *port)
if (port->type == PORT_DA830) {
/* Reset the port */
@@ -3924,7 +3924,7 @@ index fe8662cd9402..2fc63f17deb1 100644
serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
mdelay(10);
-@@ -2306,6 +2354,8 @@ int serial8250_do_startup(struct uart_port *port)
+@@ -2309,6 +2357,8 @@ int serial8250_do_startup(struct uart_port *port)
if (retval)
goto out;
@@ -3933,7 +3933,7 @@ index fe8662cd9402..2fc63f17deb1 100644
if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
unsigned char iir1;
-@@ -2322,6 +2372,9 @@ int serial8250_do_startup(struct uart_port *port)
+@@ -2325,6 +2375,9 @@ int serial8250_do_startup(struct uart_port *port)
*/
spin_lock_irqsave(&port->lock, flags);
@@ -3943,7 +3943,7 @@ index fe8662cd9402..2fc63f17deb1 100644
wait_for_xmitr(up, UART_LSR_THRE);
serial_port_out_sync(port, UART_IER, UART_IER_THRI);
udelay(1); /* allow THRE to set */
-@@ -2332,6 +2385,9 @@ int serial8250_do_startup(struct uart_port *port)
+@@ -2335,6 +2388,9 @@ int serial8250_do_startup(struct uart_port *port)
iir = serial_port_in(port, UART_IIR);
serial_port_out(port, UART_IER, 0);
@@ -3953,7 +3953,7 @@ index fe8662cd9402..2fc63f17deb1 100644
spin_unlock_irqrestore(&port->lock, flags);
if (port->irqflags & IRQF_SHARED)
-@@ -2386,10 +2442,14 @@ int serial8250_do_startup(struct uart_port *port)
+@@ -2389,10 +2445,14 @@ int serial8250_do_startup(struct uart_port *port)
* Do a quick test to see if we receive an interrupt when we enable
* the TX irq.
*/
@@ -3968,7 +3968,7 @@ index fe8662cd9402..2fc63f17deb1 100644
if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
if (!(up->bugs & UART_BUG_TXEN)) {
-@@ -2421,7 +2481,7 @@ int serial8250_do_startup(struct uart_port *port)
+@@ -2424,7 +2484,7 @@ int serial8250_do_startup(struct uart_port *port)
if (up->dma) {
const char *msg = NULL;
@@ -3977,7 +3977,7 @@ index fe8662cd9402..2fc63f17deb1 100644
msg = "forbid DMA for kernel console";
else if (serial8250_request_dma(up))
msg = "failed to request DMA";
-@@ -2472,7 +2532,7 @@ void serial8250_do_shutdown(struct uart_port *port)
+@@ -2475,7 +2535,7 @@ void serial8250_do_shutdown(struct uart_port *port)
*/
spin_lock_irqsave(&port->lock, flags);
up->ier = 0;
@@ -3986,7 +3986,7 @@ index fe8662cd9402..2fc63f17deb1 100644
spin_unlock_irqrestore(&port->lock, flags);
synchronize_irq(port->irq);
-@@ -2838,7 +2898,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
+@@ -2841,7 +2901,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
if (up->capabilities & UART_CAP_RTOIE)
up->ier |= UART_IER_RTOIE;
@@ -3995,7 +3995,7 @@ index fe8662cd9402..2fc63f17deb1 100644
if (up->capabilities & UART_CAP_EFR) {
unsigned char efr = 0;
-@@ -3303,7 +3363,7 @@ EXPORT_SYMBOL_GPL(serial8250_set_defaults);
+@@ -3306,7 +3366,7 @@ EXPORT_SYMBOL_GPL(serial8250_set_defaults);
#ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -4004,7 +4004,7 @@ index fe8662cd9402..2fc63f17deb1 100644
{
struct uart_8250_port *up = up_to_u8250p(port);
-@@ -3311,6 +3371,18 @@ static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
+@@ -3314,6 +3374,18 @@ static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
serial_port_out(port, UART_TX, ch);
}
@@ -4023,7 +4023,7 @@ index fe8662cd9402..2fc63f17deb1 100644
/*
* Restore serial console when h/w power-off detected
*/
-@@ -3337,6 +3409,32 @@ static void serial8250_console_restore(struct uart_8250_port *up)
+@@ -3340,6 +3412,32 @@ static void serial8250_console_restore(struct uart_8250_port *up)
serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
}
@@ -4056,7 +4056,7 @@ index fe8662cd9402..2fc63f17deb1 100644
/*
* Print a string to the serial port using the device FIFO
*
-@@ -3382,20 +3480,15 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
+@@ -3385,20 +3483,15 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
struct uart_port *port = &up->port;
unsigned long flags;
unsigned int ier, use_fifo;
@@ -4079,7 +4079,7 @@ index fe8662cd9402..2fc63f17deb1 100644
/* check scratch reg to see if port powered off during system sleep */
if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
-@@ -3429,10 +3522,12 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
+@@ -3432,10 +3525,12 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
*/
!(up->port.flags & UPF_CONS_FLOW);
@@ -4092,7 +4092,7 @@ index fe8662cd9402..2fc63f17deb1 100644
/*
* Finally, wait for transmitter to become empty
-@@ -3445,8 +3540,7 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
+@@ -3448,8 +3543,7 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
if (em485->tx_stopped)
up->rs485_stop_tx(up);
}
@@ -4102,7 +4102,7 @@ index fe8662cd9402..2fc63f17deb1 100644
/*
* The receive handling will happen properly because the
-@@ -3458,8 +3552,7 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
+@@ -3461,8 +3555,7 @@ void serial8250_console_write(struct uart_8250_port *up, const char *s,
if (up->msr_saved_flags)
serial8250_modem_status(up);
@@ -4112,7 +4112,7 @@ index fe8662cd9402..2fc63f17deb1 100644
}
static unsigned int probe_baud(struct uart_port *port)
-@@ -3479,6 +3572,7 @@ static unsigned int probe_baud(struct uart_port *port)
+@@ -3482,6 +3575,7 @@ static unsigned int probe_baud(struct uart_port *port)
int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
{
@@ -4120,7 +4120,7 @@ index fe8662cd9402..2fc63f17deb1 100644
int baud = 9600;
int bits = 8;
int parity = 'n';
-@@ -3488,6 +3582,8 @@ int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
+@@ -3491,6 +3585,8 @@ int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
if (!port->iobase && !port->membase)
return -ENODEV;
@@ -4705,7 +4705,7 @@ index 46040d66334a..ffe48e69b3f3 100644
-
#endif /* _LINUX_U64_STATS_SYNC_H */
diff --git a/init/Kconfig b/init/Kconfig
-index abf65098f1b6..d7287004b853 100644
+index 94125d3b6893..b0357269f4a5 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1581,6 +1581,10 @@ config PRINTK
@@ -6327,7 +6327,7 @@ index 3bba88c7ffc6..57cedc330660 100644
EXPORT_SYMBOL_GPL(hw_protection_shutdown);
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
-index cb2aa2b54c7a..f202b258230a 100644
+index daff72f00385..44d1c2133964 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -1040,6 +1040,46 @@ void resched_curr(struct rq *rq)
@@ -6510,7 +6510,7 @@ index cb2aa2b54c7a..f202b258230a 100644
ktime_t to = NSEC_PER_SEC / HZ;
set_current_state(TASK_UNINTERRUPTIBLE);
-@@ -4597,6 +4710,9 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p)
+@@ -4615,6 +4728,9 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p)
p->on_cpu = 0;
#endif
init_task_preempt_count(p);
@@ -6520,7 +6520,7 @@ index cb2aa2b54c7a..f202b258230a 100644
#ifdef CONFIG_SMP
plist_node_init(&p->pushable_tasks, MAX_PRIO);
RB_CLEAR_NODE(&p->pushable_dl_tasks);
-@@ -6466,6 +6582,7 @@ static void __sched notrace __schedule(unsigned int sched_mode)
+@@ -6484,6 +6600,7 @@ static void __sched notrace __schedule(unsigned int sched_mode)
next = pick_next_task(rq, prev, &rf);
clear_tsk_need_resched(prev);
@@ -6528,7 +6528,7 @@ index cb2aa2b54c7a..f202b258230a 100644
clear_preempt_need_resched();
#ifdef CONFIG_SCHED_DEBUG
rq->last_seen_need_resched_ns = 0;
-@@ -6680,6 +6797,30 @@ static void __sched notrace preempt_schedule_common(void)
+@@ -6698,6 +6815,30 @@ static void __sched notrace preempt_schedule_common(void)
} while (need_resched());
}
@@ -6559,7 +6559,7 @@ index cb2aa2b54c7a..f202b258230a 100644
#ifdef CONFIG_PREEMPTION
/*
* This is the entry point to schedule() from in-kernel preemption
-@@ -6693,6 +6834,8 @@ asmlinkage __visible void __sched notrace preempt_schedule(void)
+@@ -6711,6 +6852,8 @@ asmlinkage __visible void __sched notrace preempt_schedule(void)
*/
if (likely(!preemptible()))
return;
@@ -6568,7 +6568,7 @@ index cb2aa2b54c7a..f202b258230a 100644
preempt_schedule_common();
}
NOKPROBE_SYMBOL(preempt_schedule);
-@@ -6740,6 +6883,9 @@ asmlinkage __visible void __sched notrace preempt_schedule_notrace(void)
+@@ -6758,6 +6901,9 @@ asmlinkage __visible void __sched notrace preempt_schedule_notrace(void)
if (likely(!preemptible()))
return;
@@ -6578,7 +6578,7 @@ index cb2aa2b54c7a..f202b258230a 100644
do {
/*
* Because the function tracer can trace preempt_count_sub()
-@@ -8997,7 +9143,9 @@ void __init init_idle(struct task_struct *idle, int cpu)
+@@ -9015,7 +9161,9 @@ void __init init_idle(struct task_struct *idle, int cpu)
/* Set the preempt count _outside_ the spinlocks! */
init_idle_preempt_count(idle, cpu);
@@ -6887,7 +6887,7 @@ index 717fcb9fb14a..e6219da89933 100644
/*
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
-index 47a44b055a1d..ff803b85010c 100644
+index a7fe0e115272..a0a603784045 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -2640,11 +2640,19 @@ unsigned int tracing_gen_ctx_irq_test(unsigned int irqs_status)
@@ -7120,10 +7120,10 @@ index db4f2641d1cd..7e2a9fb5786c 100644
mcast_stats_add_dir(tdst.igmp_v1queries, temp.igmp_v1queries);
mcast_stats_add_dir(tdst.igmp_v2queries, temp.igmp_v2queries);
diff --git a/net/bridge/br_vlan.c b/net/bridge/br_vlan.c
-index 6e53dc991409..f2fc284abab3 100644
+index 9ffd40b8270c..bc75fa1e4666 100644
--- a/net/bridge/br_vlan.c
+++ b/net/bridge/br_vlan.c
-@@ -1378,12 +1378,12 @@ void br_vlan_get_stats(const struct net_bridge_vlan *v,
+@@ -1389,12 +1389,12 @@ void br_vlan_get_stats(const struct net_bridge_vlan *v,
cpu_stats = per_cpu_ptr(v->stats, i);
do {
@@ -7354,10 +7354,10 @@ index a9fde48cffd4..83e419afa89e 100644
data[1] += tx_bytes;
data[2] += rx_packets;
diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c
-index 4728087c42a5..378bcd777514 100644
+index 0da679411330..643a7597bc5b 100644
--- a/net/ipv4/af_inet.c
+++ b/net/ipv4/af_inet.c
-@@ -1708,9 +1708,9 @@ u64 snmp_get_cpu_field64(void __percpu *mib, int cpu, int offt,
+@@ -1699,9 +1699,9 @@ u64 snmp_get_cpu_field64(void __percpu *mib, int cpu, int offt,
bhptr = per_cpu_ptr(mib, cpu);
syncp = (struct u64_stats_sync *)(bhptr + syncp_offset);
do {
@@ -7454,7 +7454,7 @@ index 988222fff9f0..4d62059a6021 100644
seq_printf(seq, "%3X %8LX %8LX %8LX %16LX %16LX\n",
i, (u64)conns, (u64)inpkts,
diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
-index e7152d599d73..23e8ea7614ad 100644
+index 7a09421f19e1..6def1e17e69d 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -1534,10 +1534,10 @@ static int nft_dump_stats(struct sk_buff *skb, struct nft_stats __percpu *stats)
diff --git a/version.sh b/version.sh
index d9d2012ef7d2b9650cac9f8946aeeb31cfcde30e..76c02ec512aa9926efddf70e5967b2c9dbe7020a 100644
--- a/version.sh
+++ b/version.sh
@@ -17,8 +17,8 @@ DEBARCH=armhf
#toolchain="gcc_8_arm"
#toolchain="gcc_9_arm"
#toolchain="gcc_10_arm"
-toolchain="gcc_11_arm"
-#toolchain="gcc_12_arm"
+#toolchain="gcc_11_arm"
+toolchain="gcc_12_arm"
#arm64
#KERNEL_ARCH=arm64
#DEBARCH=arm64
@@ -41,10 +41,10 @@ toolchain="gcc_11_arm"
#Kernel
KERNEL_REL=6.1
-KERNEL_TAG=${KERNEL_REL}-rc5
-kernel_rt="-rc5-rt3"
+KERNEL_TAG=${KERNEL_REL}-rc7
+kernel_rt="-rc7-rt5"
#Kernel Build
-BUILD=${build_prefix}3
+BUILD=${build_prefix}3.1
#v6.X-rcX + upto SHA
#prev_KERNEL_SHA=""