From c3ea14f44fbf4bdde21dd80ee49e9c1398f61058 Mon Sep 17 00:00:00 2001
From: Robert Nelson <robertcnelson@gmail.com>
Date: Sun, 14 Jan 2024 20:46:41 -0600
Subject: [PATCH] kernel v6.7-arm64-k3-r15.1 rebase external git projects
BBDTBS:
https://openbeagle.org/beagleboard/BeagleBoard-DeviceTrees/-/commit/fb6f54ec2b36cac20da460d0e51164fa428625d6
WIRELESS_REGDB:
https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/commit/?id=37dcea0e6e5effb4228fe385e906edba3cbee389
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
patch.sh | 13 +-
...-backports-edt-ft5x06-from-linux.git.patch | 4 +-
.../0001-backports-gpu-from-linux.git.patch | 1905 +++++++++++++++--
...-BeagleBoard.org-Device-Tree-Changes.patch | 771 ++++++-
patches/external/git/BBDTBS | 2 +-
patches/get_debian_configs.sh | 4 +-
repo_maintenance/push-kernel-n-test.sh | 4 -
repo_maintenance/push-n-tag-release.sh | 4 -
tools/host_det.sh | 5 +
version.sh | 2 +-
10 files changed, 2401 insertions(+), 313 deletions(-)
diff --git a/patch.sh b/patch.sh
index 523b8d62..d386abdf 100644
--- a/patch.sh
+++ b/patch.sh
@@ -237,6 +237,17 @@ beagleboard_dtbs () {
cp -v ../${work_dir}/src/arm64/ti/*.h arch/arm64/boot/dts/ti/
cp -vr ../${work_dir}/include/dt-bindings/* ./include/dt-bindings/
+ device="AM335X-PRU-UIO-00A0" ; arm_dtbo_makefile_append
+ device="AM57XX-PRU-UIO-00A0" ; arm_dtbo_makefile_append
+ device="BB-ADC-00A0" ; arm_dtbo_makefile_append
+
+ device="BB-BONE-eMMC1-01-00A0" ; arm_dtbo_makefile_append
+
+ device="BBORG_COMMS-00A2" ; arm_dtbo_makefile_append
+ device="BBORG_FAN-A000" ; arm_dtbo_makefile_append
+
+ device="BONE-ADC" ; arm_dtbo_makefile_append
+
device="am335x-boneblack-uboot.dtb" ; arm_dtb_makefile_append
${git_bin} add -f arch/arm/boot/dts/
@@ -377,7 +388,7 @@ backports () {
dir 'eventfd'
- backport_tag_next="next-20240108"
+ backport_tag_next="next-20240109"
subsystem="gpu"
#regenerate="enable"
diff --git a/patches/backports/edt-ft5x06/0001-backports-edt-ft5x06-from-linux.git.patch b/patches/backports/edt-ft5x06/0001-backports-edt-ft5x06-from-linux.git.patch
index a07a86cc..bb446f54 100644
--- a/patches/backports/edt-ft5x06/0001-backports-edt-ft5x06-from-linux.git.patch
+++ b/patches/backports/edt-ft5x06/0001-backports-edt-ft5x06-from-linux.git.patch
@@ -1,6 +1,6 @@
-From 66c3422e4667c1910115d84ffc79660843f67f74 Mon Sep 17 00:00:00 2001
+From 546717ad2818072f5e0fc04286edce363010bd1f Mon Sep 17 00:00:00 2001
From: Robert Nelson <robertcnelson@gmail.com>
-Date: Mon, 8 Jan 2024 20:59:22 -0600
+Date: Sun, 14 Jan 2024 20:41:47 -0600
Subject: [PATCH] backports: edt-ft5x06: from: linux.git
Reference: rpi-6.7.y
diff --git a/patches/backports/gpu/0001-backports-gpu-from-linux.git.patch b/patches/backports/gpu/0001-backports-gpu-from-linux.git.patch
index 3a7e3a37..8a9223fe 100644
--- a/patches/backports/gpu/0001-backports-gpu-from-linux.git.patch
+++ b/patches/backports/gpu/0001-backports-gpu-from-linux.git.patch
@@ -1,9 +1,9 @@
-From ecb5bc1e74092b77fe6e6e88361ed0b0e7cb1076 Mon Sep 17 00:00:00 2001
+From b92b78b49b5b3fc5aceb1bb0c61191bded3fc18d Mon Sep 17 00:00:00 2001
From: Robert Nelson <robertcnelson@gmail.com>
-Date: Mon, 8 Jan 2024 21:03:30 -0600
+Date: Sun, 14 Jan 2024 20:45:26 -0600
Subject: [PATCH] backports: gpu: from: linux.git
-Reference: next-20240108
+Reference: next-20240109
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
drivers/gpu/drm/Kconfig | 38 +-
@@ -523,6 +523,7 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
drivers/gpu/drm/gma500/psb_intel_sdvo.c | 1 -
drivers/gpu/drm/gud/gud_pipe.c | 30 +-
.../gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c | 1 -
+ drivers/gpu/drm/hyperv/hyperv_drm_drv.c | 8 +-
drivers/gpu/drm/i915/Kconfig | 2 +-
drivers/gpu/drm/i915/Kconfig.debug | 18 +
drivers/gpu/drm/i915/Makefile | 184 +-
@@ -538,40 +539,41 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
drivers/gpu/drm/i915/display/intel_bios.c | 43 +-
drivers/gpu/drm/i915/display/intel_bios.h | 3 -
drivers/gpu/drm/i915/display/intel_bw.c | 7 +-
- drivers/gpu/drm/i915/display/intel_cdclk.c | 393 +-
+ drivers/gpu/drm/i915/display/intel_cdclk.c | 483 +-
drivers/gpu/drm/i915/display/intel_color.c | 70 +-
- drivers/gpu/drm/i915/display/intel_crt.c | 4 +-
+ drivers/gpu/drm/i915/display/intel_crt.c | 9 +-
drivers/gpu/drm/i915/display/intel_crtc.c | 9 +-
.../drm/i915/display/intel_crtc_state_dump.c | 10 +
drivers/gpu/drm/i915/display/intel_cursor.c | 42 +-
- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 374 +-
+ drivers/gpu/drm/i915/display/intel_cx0_phy.c | 381 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 16 +-
- drivers/gpu/drm/i915/display/intel_ddi.c | 229 +-
+ drivers/gpu/drm/i915/display/intel_ddi.c | 232 +-
drivers/gpu/drm/i915/display/intel_ddi.h | 8 +-
- drivers/gpu/drm/i915/display/intel_display.c | 598 +-
+ drivers/gpu/drm/i915/display/intel_display.c | 601 +-
drivers/gpu/drm/i915/display/intel_display.h | 9 +-
- .../gpu/drm/i915/display/intel_display_core.h | 26 +-
+ .../gpu/drm/i915/display/intel_display_core.h | 37 +-
.../drm/i915/display/intel_display_debugfs.c | 237 +-
.../display/intel_display_debugfs_params.c | 176 +
.../display/intel_display_debugfs_params.h | 13 +
.../drm/i915/display/intel_display_device.c | 15 +-
.../drm/i915/display/intel_display_device.h | 5 +-
- .../drm/i915/display/intel_display_driver.c | 14 +-
+ .../drm/i915/display/intel_display_driver.c | 163 +-
+ .../drm/i915/display/intel_display_driver.h | 6 +
.../gpu/drm/i915/display/intel_display_irq.c | 23 +-
.../drm/i915/display/intel_display_params.c | 217 +
.../drm/i915/display/intel_display_params.h | 61 +
.../drm/i915/display/intel_display_power.c | 24 +-
.../i915/display/intel_display_power_well.c | 23 +-
.../drm/i915/display/intel_display_reset.c | 2 +-
- .../drm/i915/display/intel_display_types.h | 41 +-
+ .../drm/i915/display/intel_display_types.h | 44 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 108 +-
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 1 +
- drivers/gpu/drm/i915/display/intel_dp.c | 580 +-
- drivers/gpu/drm/i915/display/intel_dp.h | 33 +-
- drivers/gpu/drm/i915/display/intel_dp_aux.c | 99 +-
+ drivers/gpu/drm/i915/display/intel_dp.c | 638 +-
+ drivers/gpu/drm/i915/display/intel_dp.h | 36 +-
+ drivers/gpu/drm/i915/display/intel_dp_aux.c | 128 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 4 +-
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 14 +-
- drivers/gpu/drm/i915/display/intel_dp_mst.c | 662 +-
+ drivers/gpu/drm/i915/display/intel_dp_mst.c | 666 +-
drivers/gpu/drm/i915/display/intel_dp_mst.h | 5 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 171 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.h | 5 +
@@ -588,6 +590,7 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
.../gpu/drm/i915/display/intel_dsb_buffer.h | 29 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 368 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.h | 1 -
+ drivers/gpu/drm/i915/display/intel_dvo.c | 5 +
drivers/gpu/drm/i915/display/intel_fb.c | 168 +-
drivers/gpu/drm/i915/display/intel_fb.h | 2 +
drivers/gpu/drm/i915/display/intel_fb_bo.c | 97 +
@@ -602,7 +605,9 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
drivers/gpu/drm/i915/display/intel_hdcp.c | 115 +-
drivers/gpu/drm/i915/display/intel_hdcp.h | 8 +-
.../gpu/drm/i915/display/intel_hdcp_regs.h | 28 +-
- drivers/gpu/drm/i915/display/intel_hdmi.c | 18 +-
+ drivers/gpu/drm/i915/display/intel_hdmi.c | 26 +-
+ drivers/gpu/drm/i915/display/intel_hotplug.c | 165 +-
+ drivers/gpu/drm/i915/display/intel_hotplug.h | 4 +
.../gpu/drm/i915/display/intel_hotplug_irq.c | 22 +-
drivers/gpu/drm/i915/display/intel_link_bw.c | 30 +-
drivers/gpu/drm/i915/display/intel_link_bw.h | 1 +
@@ -610,18 +615,19 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
.../drm/i915/display/intel_modeset_setup.c | 6 +
.../drm/i915/display/intel_modeset_verify.c | 2 +-
drivers/gpu/drm/i915/display/intel_opregion.c | 2 +-
- drivers/gpu/drm/i915/display/intel_panel.c | 4 +-
+ drivers/gpu/drm/i915/display/intel_panel.c | 8 +-
.../gpu/drm/i915/display/intel_pch_display.c | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 474 +-
drivers/gpu/drm/i915/display/intel_psr.h | 17 +-
drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +
.../gpu/drm/i915/display/intel_qp_tables.c | 3 -
- drivers/gpu/drm/i915/display/intel_sdvo.c | 25 +-
+ drivers/gpu/drm/i915/display/intel_sdvo.c | 31 +-
drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 7 +-
- drivers/gpu/drm/i915/display/intel_tc.c | 25 +-
- drivers/gpu/drm/i915/display/intel_tv.c | 8 +-
+ drivers/gpu/drm/i915/display/intel_tc.c | 49 +-
+ drivers/gpu/drm/i915/display/intel_tc.h | 2 +-
+ drivers/gpu/drm/i915/display/intel_tv.c | 13 +-
drivers/gpu/drm/i915/display/intel_vblank.c | 51 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 50 +-
.../drm/i915/display/skl_universal_plane.c | 106 +-
@@ -691,7 +697,7 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
drivers/gpu/drm/i915/gvt/handlers.c | 3 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 13 +-
drivers/gpu/drm/i915/i915_debugfs.c | 112 +-
- drivers/gpu/drm/i915/i915_driver.c | 14 +-
+ drivers/gpu/drm/i915/i915_driver.c | 39 +-
drivers/gpu/drm/i915/i915_drm_client.c | 108 +
drivers/gpu/drm/i915/i915_drm_client.h | 42 +
drivers/gpu/drm/i915/i915_drv.h | 20 +-
@@ -1509,8 +1515,9 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
sound/pci/hda/hda_controller.c | 10 +-
sound/pci/hda/hda_intel.c | 2 +
sound/pci/hda/patch_ca0132.c | 3 +-
+ sound/pci/hda/patch_conexant.c | 115 +-
sound/pci/hda/patch_hdmi.c | 6 +-
- sound/pci/hda/patch_realtek.c | 31 +
+ sound/pci/hda/patch_realtek.c | 32 +
sound/pci/hda/tas2781_hda_i2c.c | 117 +-
sound/soc/amd/acp-config.c | 39 +-
sound/soc/amd/acp/Kconfig | 13 +
@@ -1610,6 +1617,8 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
sound/soc/intel/avs/topology.c | 13 +-
sound/soc/intel/boards/Kconfig | 2 +
sound/soc/intel/boards/Makefile | 3 +-
+ sound/soc/intel/boards/bxt_da7219_max98357a.c | 6 +
+ sound/soc/intel/boards/bxt_rt298.c | 3 +-
sound/soc/intel/boards/bytcht_es8316.c | 71 +-
sound/soc/intel/boards/cht_bsw_rt5645.c | 8 +
sound/soc/intel/boards/cht_bsw_rt5672.c | 8 +-
@@ -1724,7 +1733,7 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
sound/usb/mixer_quirks.c | 3 +
sound/usb/mixer_scarlett2.c | 4841 ++++++++++---
sound/x86/intel_hdmi_audio.c | 1 +
- 1718 files changed, 138088 insertions(+), 25796 deletions(-)
+ 1727 files changed, 138721 insertions(+), 25915 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h
create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
@@ -44263,6 +44272,39 @@ index 410bd019bb35..e6e48651c15c 100644
snprintf(connector->adapter.name, I2C_NAME_SIZE, "HIS i2c bit bus");
connector->adapter.dev.parent = drm_dev->dev;
i2c_set_adapdata(&connector->adapter, connector);
+diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_drv.c b/drivers/gpu/drm/hyperv/hyperv_drm_drv.c
+index d511d17c5bdf..cff85086f2d6 100644
+--- a/drivers/gpu/drm/hyperv/hyperv_drm_drv.c
++++ b/drivers/gpu/drm/hyperv/hyperv_drm_drv.c
+@@ -7,7 +7,6 @@
+ #include <linux/hyperv.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/screen_info.h>
+
+ #include <drm/drm_aperture.h>
+ #include <drm/drm_atomic_helper.h>
+@@ -73,11 +72,6 @@ static int hyperv_setup_vram(struct hyperv_drm_device *hv,
+ struct drm_device *dev = &hv->dev;
+ int ret;
+
+- if (IS_ENABLED(CONFIG_SYSFB))
+- drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base,
+- screen_info.lfb_size,
+- &hyperv_driver);
+-
+ hv->fb_size = (unsigned long)hv->mmio_megabytes * 1024 * 1024;
+
+ ret = vmbus_allocate_mmio(&hv->mem, hdev, 0, -1, hv->fb_size, 0x100000,
+@@ -130,6 +124,8 @@ static int hyperv_vmbus_probe(struct hv_device *hdev,
+ goto err_hv_set_drv_data;
+ }
+
++ drm_aperture_remove_framebuffers(&hyperv_driver);
++
+ ret = hyperv_setup_vram(hv, hdev);
+ if (ret)
+ goto err_vmbus_close;
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index ce397a8797f7..b5d6e3352071 100644
--- a/drivers/gpu/drm/i915/Kconfig
@@ -45424,7 +45466,7 @@ index bef96db62c80..7f2a50b4f494 100644
else
idx = icl_max_bw_index(i915, num_active_planes, i);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
-index c4839c67cb0f..c5fecde7afa8 100644
+index c4839c67cb0f..26200ee3e23f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1180,7 +1180,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
@@ -45889,19 +45931,57 @@ index c4839c67cb0f..c5fecde7afa8 100644
/* make sure the mid clock came out sane */
-@@ -1878,9 +1906,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+@@ -1872,15 +1900,47 @@ static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
+ dev_priv->display.cdclk.hw.vco > 0;
+ }
+
++static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
++ const struct intel_cdclk_config *cdclk_config,
++ enum pipe pipe)
++{
++ int cdclk = cdclk_config->cdclk;
++ int vco = cdclk_config->vco;
++ int unsquashed_cdclk;
++ u16 waveform;
++ u32 val;
++
++ waveform = cdclk_squash_waveform(i915, cdclk);
++
++ unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len,
++ cdclk_squash_divider(waveform));
++
++ val = bxt_cdclk_cd2x_div_sel(i915, unsquashed_cdclk, vco) |
++ bxt_cdclk_cd2x_pipe(i915, pipe);
++
++ /*
++ * Disable SSA Precharge when CD clock frequency < 500 MHz,
++ * enable otherwise.
++ */
++ if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) &&
++ cdclk >= 500000)
++ val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
++
++ if (DISPLAY_VER(i915) >= 20)
++ val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
++ else
++ val |= skl_cdclk_decimal(cdclk);
++
++ return val;
++}
++
+ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
{
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
- u32 val;
-+ int unsquashed_cdclk;
u16 waveform;
- int clock;
-+ u32 val;
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
!cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
-@@ -1897,15 +1925,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+@@ -1897,31 +1957,10 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
waveform = cdclk_squash_waveform(dev_priv, cdclk);
@@ -45909,18 +45989,99 @@ index c4839c67cb0f..c5fecde7afa8 100644
- clock = vco / 2;
- else
- clock = cdclk;
-+ unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len,
-+ cdclk_squash_divider(waveform));
-
+-
if (HAS_CDCLK_SQUASH(dev_priv))
dg2_cdclk_squash_program(dev_priv, waveform);
- val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
-+ val = bxt_cdclk_cd2x_div_sel(dev_priv, unsquashed_cdclk, vco) |
- bxt_cdclk_cd2x_pipe(dev_priv, pipe);
+- bxt_cdclk_cd2x_pipe(dev_priv, pipe);
+-
+- /*
+- * Disable SSA Precharge when CD clock frequency < 500 MHz,
+- * enable otherwise.
+- */
+- if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
+- cdclk >= 500000)
+- val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+-
+- if (DISPLAY_VER(dev_priv) >= 20)
+- val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
+- else
+- val |= skl_cdclk_decimal(cdclk);
+-
+- intel_de_write(dev_priv, CDCLK_CTL, val);
++ intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe));
+
+ if (pipe != INVALID_PIPE)
+ intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
+@@ -2012,7 +2051,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
+ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
+ {
+ u32 cdctl, expected;
+- int cdclk, clock, vco;
++ int cdclk, vco;
+
+ intel_update_cdclk(dev_priv);
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
+@@ -2021,20 +2060,6 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
+ dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
+ goto sanitize;
+
+- /* DPLL okay; verify the cdclock
+- *
+- * Some BIOS versions leave an incorrect decimal frequency value and
+- * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
+- * so sanitize this register.
+- */
+- cdctl = intel_de_read(dev_priv, CDCLK_CTL);
+- /*
+- * Let's ignore the pipe field, since BIOS could have configured the
+- * dividers both synching to an active pipe, or asynchronously
+- * (PIPE_NONE).
+- */
+- cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
+-
+ /* Make sure this is a legal cdclk value for the platform */
+ cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
+ if (cdclk != dev_priv->display.cdclk.hw.cdclk)
+@@ -2045,24 +2070,21 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
+ if (vco != dev_priv->display.cdclk.hw.vco)
+ goto sanitize;
+
+- expected = skl_cdclk_decimal(cdclk);
+-
+- /* Figure out what CD2X divider we should be using for this cdclk */
+- if (HAS_CDCLK_SQUASH(dev_priv))
+- clock = dev_priv->display.cdclk.hw.vco / 2;
+- else
+- clock = dev_priv->display.cdclk.hw.cdclk;
+-
+- expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock,
+- dev_priv->display.cdclk.hw.vco);
++ /*
++ * Some BIOS versions leave an incorrect decimal frequency value and
++ * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
++ * so sanitize this register.
++ */
++ cdctl = intel_de_read(dev_priv, CDCLK_CTL);
++ expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE);
/*
-@@ -2075,7 +2101,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
+- * Disable SSA Precharge when CD clock frequency < 500 MHz,
+- * enable otherwise.
++ * Let's ignore the pipe field, since BIOS could have configured the
++ * dividers both synching to an active pipe, or asynchronously
++ * (PIPE_NONE).
+ */
+- if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
+- dev_priv->display.cdclk.hw.cdclk >= 500000)
+- expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
++ cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
++ expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
+
+ if (cdctl == expected)
+ /* All well; nothing to sanitize */
+@@ -2075,7 +2097,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
dev_priv->display.cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
@@ -45929,7 +46090,7 @@ index c4839c67cb0f..c5fecde7afa8 100644
}
static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
-@@ -2597,9 +2623,10 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
+@@ -2597,9 +2619,10 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
* Since PPC = 2 with bigjoiner
* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
*/
@@ -45943,7 +46104,7 @@ index c4839c67cb0f..c5fecde7afa8 100644
min_cdclk = max(min_cdclk, min_cdclk_bj);
}
-@@ -3439,15 +3466,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
+@@ -3439,15 +3462,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
{
u32 freq;
@@ -45962,7 +46123,7 @@ index c4839c67cb0f..c5fecde7afa8 100644
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
-@@ -3488,7 +3515,7 @@ static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+@@ -3488,7 +3511,7 @@ static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
@@ -46088,19 +46249,30 @@ index 1d26be54ddfc..c5092b7e87d5 100644
intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
-index 6f6b348b8a40..abaacea5c2cc 100644
+index 6f6b348b8a40..b9733a73e21d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
-@@ -846,7 +846,7 @@ intel_crt_detect(struct drm_connector *connector,
+@@ -42,6 +42,7 @@
+ #include "intel_ddi.h"
+ #include "intel_ddi_buf_trans.h"
+ #include "intel_de.h"
++#include "intel_display_driver.h"
+ #include "intel_display_types.h"
+ #include "intel_fdi.h"
+ #include "intel_fdi_regs.h"
+@@ -846,7 +847,10 @@ intel_crt_detect(struct drm_connector *connector,
if (!intel_display_device_enabled(dev_priv))
return connector_status_disconnected;
- if (dev_priv->params.load_detect_test) {
++ if (!intel_display_driver_check_access(dev_priv))
++ return connector->status;
++
+ if (dev_priv->display.params.load_detect_test) {
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
goto load_detect;
-@@ -906,7 +906,7 @@ intel_crt_detect(struct drm_connector *connector,
+@@ -906,7 +910,7 @@ intel_crt_detect(struct drm_connector *connector,
else if (DISPLAY_VER(dev_priv) < 4)
status = intel_crt_load_detect(crt,
to_intel_crtc(connector->state->crtc)->pipe);
@@ -46109,6 +46281,14 @@ index 6f6b348b8a40..abaacea5c2cc 100644
status = connector_status_disconnected;
else
status = connector_status_unknown;
+@@ -1069,6 +1073,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
+ } else {
+ intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
+ }
++ intel_connector->base.polled = intel_connector->polled;
+
+ if (HAS_DDI(dev_priv)) {
+ assert_port_valid(dev_priv, PORT_E);
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 1fd068e6e26c..8a84a31c7b48 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -46239,7 +46419,7 @@ index b342fad180ca..926e2de00eb5 100644
if (plane->cursor.base != base ||
plane->cursor.size != fbc_ctl ||
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
-index ccf225afeb2a..ce1bddf74a82 100644
+index ccf225afeb2a..e67c25975947 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -31,7 +31,7 @@
@@ -46485,17 +46665,23 @@ index ccf225afeb2a..ce1bddf74a82 100644
crtc_state->cx0pll_state.c20 = *tables[i];
return 0;
}
-@@ -2094,17 +2096,53 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
+@@ -2094,17 +2096,58 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
return intel_c20pll_calc_state(crtc_state, encoder);
}
-static bool intel_c20_use_mplla(u32 clock)
-+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
-+ const struct intel_c20pll_state *pll_state)
++static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
{
- /* 10G and 20G rates use MPLLA */
- if (clock == 312500 || clock == 625000)
- return true;
++ return state->tx[0] & C20_PHY_USE_MPLLB;
++}
+
+- return false;
++static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
++ const struct intel_c20pll_state *pll_state)
++{
+ unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
+ unsigned int multiplier, refclk = 38400;
+ unsigned int tx_clk_div;
@@ -46504,9 +46690,8 @@ index ccf225afeb2a..ce1bddf74a82 100644
+ unsigned int ref, vco;
+ unsigned int tx_rate_mult;
+ unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
-
-- return false;
-+ if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
++
++ if (intel_c20phy_use_mpllb(pll_state)) {
+ tx_rate_mult = 1;
+ frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
+ frac_quot = pll_state->mpllb[8];
@@ -46546,7 +46731,16 @@ index ccf225afeb2a..ce1bddf74a82 100644
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
bool cntx;
-@@ -2158,6 +2196,8 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
+@@ -2136,7 +2179,7 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
+ PHY_C20_A_CMN_CNTX_CFG(i));
+ }
+
+- if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
++ if (intel_c20phy_use_mpllb(pll_state)) {
+ /* MPLLB configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
+ if (cntx)
+@@ -2158,6 +2201,8 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
}
}
@@ -46555,7 +46749,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-@@ -2172,12 +2212,12 @@ void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
+@@ -2172,12 +2217,12 @@ void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
@@ -46563,7 +46757,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
- for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
- drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
- } else {
-+ if (hw_state->tx[0] & C20_PHY_USE_MPLLB) {
++ if (intel_c20phy_use_mpllb(hw_state)) {
for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
+ } else {
@@ -46572,7 +46766,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
}
}
-@@ -2200,11 +2240,11 @@ static u8 intel_c20_get_dp_rate(u32 clock)
+@@ -2200,11 +2245,11 @@ static u8 intel_c20_get_dp_rate(u32 clock)
return 6;
case 432000: /* 4.32 Gbps eDP */
return 7;
@@ -46587,7 +46781,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
return 10;
case 648000: /* 6.48 Gbps eDP*/
return 11;
-@@ -2222,13 +2262,13 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)
+@@ -2222,13 +2267,13 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)
return 0;
switch (clock) {
@@ -46606,7 +46800,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
return 3;
default:
MISSING_CASE(clock);
-@@ -2239,7 +2279,7 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)
+@@ -2239,7 +2284,7 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)
static bool is_dp2(u32 clock)
{
/* DP2.0 clock rates */
@@ -46615,7 +46809,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
return true;
return false;
-@@ -2248,11 +2288,11 @@ static bool is_dp2(u32 clock)
+@@ -2248,11 +2293,11 @@ static bool is_dp2(u32 clock)
static bool is_hdmi_frl(u32 clock)
{
switch (clock) {
@@ -46632,7 +46826,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
return true;
default:
return false;
-@@ -2285,6 +2325,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
+@@ -2285,6 +2330,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
bool dp = false;
int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
@@ -46640,13 +46834,13 @@ index ccf225afeb2a..ce1bddf74a82 100644
bool cntx;
int i;
-@@ -2323,50 +2364,50 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
+@@ -2323,50 +2369,50 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
}
/* 3.3 mpllb or mplla configuration */
- if (intel_c20_use_mplla(pll_state->clock)) {
- for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
-+ if (pll_state->tx[0] & C20_PHY_USE_MPLLB) {
++ if (intel_c20phy_use_mpllb(pll_state)) {
+ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
@@ -46706,7 +46900,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
MB_WRITE_COMMITTED);
}
-@@ -2378,8 +2419,8 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
+@@ -2378,8 +2424,8 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
}
@@ -46717,7 +46911,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
{
unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
-@@ -2405,51 +2446,6 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
+@@ -2405,51 +2451,6 @@ int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
return tmpclk;
}
@@ -46769,7 +46963,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool lane_reversal)
-@@ -3004,17 +3000,123 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
+@@ -3004,17 +3005,123 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
return ICL_PORT_DPLL_DEFAULT;
}
@@ -46837,8 +47031,8 @@ index ccf225afeb2a..ce1bddf74a82 100644
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ const struct intel_c20pll_state *mpll_sw_state = &state->cx0pll_state.c20;
-+ bool sw_use_mpllb = mpll_sw_state->tx[0] & C20_PHY_USE_MPLLB;
-+ bool hw_use_mpllb = mpll_hw_state->tx[0] & C20_PHY_USE_MPLLB;
++ bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
++ bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
+ int i;
+
+ I915_STATE_WARN(i915, mpll_hw_state->clock != mpll_sw_state->clock,
@@ -46897,7 +47091,7 @@ index ccf225afeb2a..ce1bddf74a82 100644
if (DISPLAY_VER(i915) < 14)
return;
-@@ -3030,27 +3132,13 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state,
+@@ -3030,27 +3137,13 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state,
encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
phy = intel_port_to_phy(i915, encoder->port);
@@ -46972,7 +47166,7 @@ index 0e0a38dac8cd..c6682677253a 100644
const struct intel_crtc_state *crtc_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
-index 9151d5add960..2746655bcb26 100644
+index 9151d5add960..922194b957be 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -25,6 +25,7 @@
@@ -47420,6 +47614,16 @@ index 9151d5add960..2746655bcb26 100644
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->sync_state = intel_ddi_sync_state;
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
+@@ -5000,6 +5117,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
+ encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;
+ encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;
+
++ dig_port->lock = intel_tc_port_lock;
++ dig_port->unlock = intel_tc_port_unlock;
++
+ if (intel_tc_port_init(dig_port, is_legacy) < 0)
+ goto err;
+ }
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 4999c0ee229b..434de7196875 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -47452,7 +47656,7 @@ index 4999c0ee229b..434de7196875 100644
enum transcoder cpu_transcoder,
bool enable, u32 hdcp_mask);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
-index df582ff81b45..927d124457b6 100644
+index df582ff81b45..31a6a82c1261 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -48,6 +48,7 @@
@@ -48213,7 +48417,17 @@ index df582ff81b45..927d124457b6 100644
new_crtc_state->update_pipe = true;
}
-@@ -6476,15 +6372,14 @@ int intel_atomic_check(struct drm_device *dev,
+@@ -6414,6 +6310,9 @@ int intel_atomic_check(struct drm_device *dev,
+ int ret, i;
+ bool any_ms = false;
+
++ if (!intel_display_driver_check_access(dev_priv))
++ return -ENODEV;
++
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ /*
+@@ -6476,15 +6375,14 @@ int intel_atomic_check(struct drm_device *dev,
if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
continue;
@@ -48234,7 +48448,7 @@ index df582ff81b45..927d124457b6 100644
}
if (is_trans_port_sync_mode(new_crtc_state)) {
-@@ -6493,21 +6388,13 @@ int intel_atomic_check(struct drm_device *dev,
+@@ -6493,21 +6391,13 @@ int intel_atomic_check(struct drm_device *dev,
if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
trans |= BIT(new_crtc_state->master_transcoder);
@@ -48260,7 +48474,7 @@ index df582ff81b45..927d124457b6 100644
}
}
-@@ -6528,10 +6415,6 @@ int intel_atomic_check(struct drm_device *dev,
+@@ -6528,10 +6418,6 @@ int intel_atomic_check(struct drm_device *dev,
goto fail;
}
@@ -48271,7 +48485,7 @@ index df582ff81b45..927d124457b6 100644
ret = intel_atomic_check_planes(state);
if (ret)
goto fail;
-@@ -6767,8 +6650,8 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
+@@ -6767,8 +6653,8 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
intel_crtc_enable_pipe_crc(crtc);
}
@@ -48282,7 +48496,7 @@ index df582ff81b45..927d124457b6 100644
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *old_crtc_state =
-@@ -6810,6 +6693,15 @@ static void intel_update_crtc(struct intel_atomic_state *state,
+@@ -6810,6 +6696,15 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_color_commit_noarm(new_crtc_state);
intel_crtc_planes_update_noarm(state, crtc);
@@ -48298,7 +48512,7 @@ index df582ff81b45..927d124457b6 100644
/* Perform vblank evasion around commit operation */
intel_pipe_update_start(state, crtc);
-@@ -6838,7 +6730,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
+@@ -6838,7 +6733,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
* valid pipe configuration from the BIOS we need to take care
* of enabling them on the CRTC's first fastset.
*/
@@ -48307,7 +48521,7 @@ index df582ff81b45..927d124457b6 100644
old_crtc_state->inherited)
intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
}
-@@ -6934,6 +6826,13 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
+@@ -6934,6 +6829,13 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state)
continue;
intel_enable_crtc(state, crtc);
@@ -48321,7 +48535,7 @@ index df582ff81b45..927d124457b6 100644
intel_update_crtc(state, crtc);
}
}
-@@ -6971,6 +6870,15 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
+@@ -6971,6 +6873,15 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
* So first lets enable all pipes that do not need a fullmodeset as
* those don't have any external dependency.
*/
@@ -48337,7 +48551,7 @@ index df582ff81b45..927d124457b6 100644
while (update_pipes) {
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
-@@ -7041,6 +6949,15 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
+@@ -7041,6 +6952,15 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
/*
* Finally we do the plane updates/etc. for all pipes that got enabled.
*/
@@ -48353,7 +48567,7 @@ index df582ff81b45..927d124457b6 100644
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
enum pipe pipe = crtc->pipe;
-@@ -7060,49 +6977,24 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
+@@ -7060,49 +6980,24 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
drm_WARN_ON(&dev_priv->drm, update_pipes);
}
@@ -48416,7 +48630,7 @@ index df582ff81b45..927d124457b6 100644
}
static void intel_atomic_cleanup_work(struct work_struct *work)
-@@ -7120,8 +7012,6 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
+@@ -7120,8 +7015,6 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
drm_atomic_helper_commit_cleanup_done(&state->base);
drm_atomic_state_put(&state->base);
@@ -48425,7 +48639,7 @@ index df582ff81b45..927d124457b6 100644
}
static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
-@@ -7394,32 +7284,6 @@ static void intel_atomic_commit_work(struct work_struct *work)
+@@ -7394,32 +7287,6 @@ static void intel_atomic_commit_work(struct work_struct *work)
intel_atomic_commit_tail(state);
}
@@ -48458,7 +48672,7 @@ index df582ff81b45..927d124457b6 100644
static void intel_atomic_track_fbs(struct intel_atomic_state *state)
{
struct intel_plane_state *old_plane_state, *new_plane_state;
-@@ -7442,10 +7306,6 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
+@@ -7442,10 +7309,6 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
@@ -48469,7 +48683,7 @@ index df582ff81b45..927d124457b6 100644
/*
* The intel_legacy_cursor_update() fast path takes care
* of avoiding the vblank waits for simple cursor
-@@ -7478,7 +7338,6 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
+@@ -7478,7 +7341,6 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
if (ret) {
drm_dbg_atomic(&dev_priv->drm,
"Preparing state failed with %i\n", ret);
@@ -48477,7 +48691,7 @@ index df582ff81b45..927d124457b6 100644
intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
return ret;
}
-@@ -7494,8 +7353,6 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
+@@ -7494,8 +7356,6 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
struct intel_crtc *crtc;
int i;
@@ -48486,7 +48700,7 @@ index df582ff81b45..927d124457b6 100644
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
intel_color_cleanup_commit(new_crtc_state);
-@@ -7509,7 +7366,6 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
+@@ -7509,7 +7369,6 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
drm_atomic_state_get(&state->base);
INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
@@ -48494,7 +48708,7 @@ index df582ff81b45..927d124457b6 100644
if (nonblock && state->modeset) {
queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
} else if (nonblock) {
-@@ -7909,7 +7765,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *de
+@@ -7909,7 +7768,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *de
* Cantiga+ cannot handle modes with a hsync front porch of 0.
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/
@@ -48545,7 +48759,7 @@ index a05c7e2b782e..f4a0773f0fca 100644
unlikely(__ret_warn_on); \
})
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
-index ccfe27630fb6..47297ed85822 100644
+index ccfe27630fb6..8853a05dc331 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -19,6 +19,7 @@
@@ -48556,7 +48770,29 @@ index ccfe27630fb6..47297ed85822 100644
#include "intel_display_power.h"
#include "intel_dpll_mgr.h"
#include "intel_fbc.h"
-@@ -297,12 +298,6 @@ struct intel_display {
+@@ -27,6 +28,8 @@
+ #include "intel_opregion.h"
+ #include "intel_wm_types.h"
+
++struct task_struct;
++
+ struct drm_i915_private;
+ struct drm_property;
+ struct drm_property_blob;
+@@ -171,6 +174,12 @@ struct intel_hotplug {
+ struct work_struct poll_init_work;
+ bool poll_enabled;
+
++ /*
++ * Queuing of hotplug_work, reenable_work and poll_init_work is
++ * enabled. Protected by drm_i915_private::irq_lock.
++ */
++ bool detection_work_enabled;
++
+ unsigned int hpd_storm_threshold;
+ /* Whether or not to count short HPD IRQs in HPD storms */
+ u8 hpd_short_storm_enabled;
+@@ -297,11 +306,10 @@ struct intel_display {
const struct intel_audio_funcs *audio;
} funcs;
@@ -48565,11 +48801,14 @@ index ccfe27630fb6..47297ed85822 100644
- struct llist_head free_list;
- struct work_struct free_work;
- } atomic_helper;
--
++ struct {
++ bool any_task_allowed;
++ struct task_struct *allowed_task;
++ } access;
+
struct {
/* backlight registers and fields in struct intel_panel */
- struct mutex lock;
-@@ -347,15 +342,6 @@ struct intel_display {
+@@ -347,15 +355,6 @@ struct intel_display {
struct intel_global_obj obj;
} dbuf;
@@ -48585,7 +48824,7 @@ index ccfe27630fb6..47297ed85822 100644
struct {
/*
* dkl.phy_lock protects against concurrent access of the
-@@ -443,6 +429,15 @@ struct intel_display {
+@@ -443,6 +442,15 @@ struct intel_display {
bool false_color;
} ips;
@@ -48601,7 +48840,7 @@ index ccfe27630fb6..47297ed85822 100644
struct {
struct i915_power_domains domains;
-@@ -520,6 +515,7 @@ struct intel_display {
+@@ -520,6 +528,7 @@ struct intel_display {
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
@@ -49337,10 +49576,18 @@ index 5b5c0e53307f..fe4268813786 100644
void intel_display_device_info_print(const struct intel_display_device_info *info,
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
-index 44b59ac301e6..9df9097a0255 100644
+index 44b59ac301e6..ecf9cb74734b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
-@@ -181,6 +181,13 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915)
+@@ -45,6 +45,7 @@
+ #include "intel_hdcp.h"
+ #include "intel_hotplug.h"
+ #include "intel_hti.h"
++#include "intel_modeset_lock.h"
+ #include "intel_modeset_setup.h"
+ #include "intel_opregion.h"
+ #include "intel_overlay.h"
+@@ -181,6 +182,13 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
@@ -49354,7 +49601,7 @@ index 44b59ac301e6..9df9097a0255 100644
intel_display_irq_init(i915);
intel_dkl_phy_init(i915);
intel_color_init_hooks(i915);
-@@ -252,10 +259,6 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
+@@ -252,10 +260,6 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
@@ -49365,7 +49612,181 @@ index 44b59ac301e6..9df9097a0255 100644
intel_init_quirks(i915);
intel_fbc_init(i915);
-@@ -423,9 +426,6 @@ void intel_display_driver_remove(struct drm_i915_private *i915)
+@@ -273,6 +277,139 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
+ return ret;
+ }
+
++static void set_display_access(struct drm_i915_private *i915,
++ bool any_task_allowed,
++ struct task_struct *allowed_task)
++{
++ struct drm_modeset_acquire_ctx ctx;
++ int err;
++
++ intel_modeset_lock_ctx_retry(&ctx, NULL, 0, err) {
++ err = drm_modeset_lock_all_ctx(&i915->drm, &ctx);
++ if (err)
++ continue;
++
++ i915->display.access.any_task_allowed = any_task_allowed;
++ i915->display.access.allowed_task = allowed_task;
++ }
++
++ drm_WARN_ON(&i915->drm, err);
++}
++
++/**
++ * intel_display_driver_enable_user_access - Enable display HW access for all threads
++ * @i915: i915 device instance
++ *
++ * Enable the display HW access for all threads. Examples for such accesses
++ * are modeset commits and connector probing.
++ *
++ * This function should be called during driver loading and system resume once
++ * all the HW initialization steps are done.
++ */
++void intel_display_driver_enable_user_access(struct drm_i915_private *i915)
++{
++ set_display_access(i915, true, NULL);
++
++ intel_hpd_enable_detection_work(i915);
++}
++
++/**
++ * intel_display_driver_disable_user_access - Disable display HW access for user threads
++ * @i915: i915 device instance
++ *
++ * Disable the display HW access for user threads. Examples for such accesses
++ * are modeset commits and connector probing. For the current thread the
++ * access is still enabled, which should only perform HW init/deinit
++ * programming (as the initial modeset during driver loading or the disabling
++ * modeset during driver unloading and system suspend/shutdown). This function
++ * should be followed by calling either intel_display_driver_enable_user_access()
++ * after completing the HW init programming or
++ * intel_display_driver_suspend_access() after completing the HW deinit
++ * programming.
++ *
++ * This function should be called during driver loading/unloading and system
++ * suspend/shutdown before starting the HW init/deinit programming.
++ */
++void intel_display_driver_disable_user_access(struct drm_i915_private *i915)
++{
++ intel_hpd_disable_detection_work(i915);
++
++ set_display_access(i915, false, current);
++}
++
++/**
++ * intel_display_driver_suspend_access - Suspend display HW access for all threads
++ * @i915: i915 device instance
++ *
++ * Disable the display HW access for all threads. Examples for such accesses
++ * are modeset commits and connector probing. This call should be either
++ * followed by calling intel_display_driver_resume_access(), or the driver
++ * should be unloaded/shutdown.
++ *
++ * This function should be called during driver unloading and system
++ * suspend/shutdown after completing the HW deinit programming.
++ */
++void intel_display_driver_suspend_access(struct drm_i915_private *i915)
++{
++ set_display_access(i915, false, NULL);
++}
++
++/**
++ * intel_display_driver_resume_access - Resume display HW access for the resume thread
++ * @i915: i915 device instance
++ *
++ * Enable the display HW access for the current resume thread, keeping the
++ * access disabled for all other (user) threads. Examples for such accesses
++ * are modeset commits and connector probing. The resume thread should only
++ * perform HW init programming (as the restoring modeset). This function
++ * should be followed by calling intel_display_driver_enable_user_access(),
++ * after completing the HW init programming steps.
++ *
++ * This function should be called during system resume before starting the HW
++ * init steps.
++ */
++void intel_display_driver_resume_access(struct drm_i915_private *i915)
++{
++ set_display_access(i915, false, current);
++}
++
++/**
++ * intel_display_driver_check_access - Check if the current thread has disaplay HW access
++ * @i915: i915 device instance
++ *
++ * Check whether the current thread has display HW access, print a debug
++ * message if it doesn't. Such accesses are modeset commits and connector
++ * probing. If the function returns %false any HW access should be prevented.
++ *
++ * Returns %true if the current thread has display HW access, %false
++ * otherwise.
++ */
++bool intel_display_driver_check_access(struct drm_i915_private *i915)
++{
++ char comm[TASK_COMM_LEN];
++ char current_task[TASK_COMM_LEN + 16];
++ char allowed_task[TASK_COMM_LEN + 16] = "none";
++
++ if (i915->display.access.any_task_allowed ||
++ i915->display.access.allowed_task == current)
++ return true;
++
++ snprintf(current_task, sizeof(current_task), "%s[%d]",
++ get_task_comm(comm, current),
++ task_pid_vnr(current));
++
++ if (i915->display.access.allowed_task)
++ snprintf(allowed_task, sizeof(allowed_task), "%s[%d]",
++ get_task_comm(comm, i915->display.access.allowed_task),
++ task_pid_vnr(i915->display.access.allowed_task));
++
++ drm_dbg_kms(&i915->drm,
++ "Reject display access from task %s (allowed to %s)\n",
++ current_task, allowed_task);
++
++ return false;
++}
++
+ /* part #2: call after irq install, but before gem init */
+ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
+ {
+@@ -323,6 +460,8 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
+ intel_vga_disable(i915);
+ intel_setup_outputs(i915);
+
++ intel_display_driver_disable_user_access(i915);
++
+ drm_modeset_lock_all(dev);
+ intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
+ intel_acpi_assign_connector_fwnodes(i915);
+@@ -371,7 +510,6 @@ int intel_display_driver_probe(struct drm_i915_private *i915)
+
+ /* Only enable hotplug handling once the fbdev is fully set up. */
+ intel_hpd_init(i915);
+- intel_hpd_poll_disable(i915);
+
+ skl_watermark_ipc_init(i915);
+
+@@ -391,6 +529,8 @@ void intel_display_driver_register(struct drm_i915_private *i915)
+
+ intel_audio_init(i915);
+
++ intel_display_driver_enable_user_access(i915);
++
+ intel_display_debugfs_register(i915);
+
+ /*
+@@ -409,6 +549,7 @@ void intel_display_driver_register(struct drm_i915_private *i915)
+ * fbdev->async_cookie.
+ */
+ drm_kms_helper_poll_init(&i915->drm);
++ intel_hpd_poll_disable(i915);
+
+ intel_display_device_info_print(DISPLAY_INFO(i915),
+ DISPLAY_RUNTIME_INFO(i915), &p);
+@@ -423,9 +564,6 @@ void intel_display_driver_remove(struct drm_i915_private *i915)
flush_workqueue(i915->display.wq.flip);
flush_workqueue(i915->display.wq.modeset);
@@ -49375,6 +49796,51 @@ index 44b59ac301e6..9df9097a0255 100644
/*
* MST topology needs to be suspended so we don't have any calls to
* fbdev after it's finalized. MST will be destroyed later as part of
+@@ -440,6 +578,8 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
+ if (!HAS_DISPLAY(i915))
+ return;
+
++ intel_display_driver_suspend_access(i915);
++
+ /*
+ * Due to the hpd irq storm handling the hotplug work can re-arm the
+ * poll handlers. Hence disable polling after hpd handling is shut down.
+@@ -486,14 +626,17 @@ void intel_display_driver_unregister(struct drm_i915_private *i915)
+ return;
+
+ intel_fbdev_unregister(i915);
+- intel_audio_deinit(i915);
+-
+ /*
+ * After flushing the fbdev (incl. a late async config which
+ * will have delayed queuing of a hotplug event), then flush
+ * the hotplug events.
+ */
+ drm_kms_helper_poll_fini(&i915->drm);
++
++ intel_display_driver_disable_user_access(i915);
++
++ intel_audio_deinit(i915);
++
+ drm_atomic_helper_shutdown(&i915->drm);
+
+ acpi_video_unregister();
+diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.h b/drivers/gpu/drm/i915/display/intel_display_driver.h
+index c276a58ee329..42cc4af6d3fd 100644
+--- a/drivers/gpu/drm/i915/display/intel_display_driver.h
++++ b/drivers/gpu/drm/i915/display/intel_display_driver.h
+@@ -32,5 +32,11 @@ int __intel_display_driver_resume(struct drm_i915_private *i915,
+ struct drm_atomic_state *state,
+ struct drm_modeset_acquire_ctx *ctx);
+
++void intel_display_driver_enable_user_access(struct drm_i915_private *i915);
++void intel_display_driver_disable_user_access(struct drm_i915_private *i915);
++void intel_display_driver_suspend_access(struct drm_i915_private *i915);
++void intel_display_driver_resume_access(struct drm_i915_private *i915);
++bool intel_display_driver_check_access(struct drm_i915_private *i915);
++
+ #endif /* __INTEL_DISPLAY_DRIVER_H__ */
+
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index bff4a76310c0..99843883cef7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -49903,7 +50369,7 @@ index 17178d5d7788..c2c347b22448 100644
return;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
-index 65ea37fe8cff..b9b9d9f2bc0b 100644
+index 65ea37fe8cff..3556ccedbe4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -198,6 +198,12 @@ struct intel_encoder {
@@ -50019,7 +50485,17 @@ index 65ea37fe8cff..b9b9d9f2bc0b 100644
};
enum lspcon_vendor {
-@@ -1992,17 +2006,6 @@ dp_to_lspcon(struct intel_dp *intel_dp)
+@@ -1876,6 +1890,9 @@ struct intel_digital_port {
+ u32 (*infoframes_enabled)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config);
+ bool (*connected)(struct intel_encoder *encoder);
++
++ void (*lock)(struct intel_digital_port *dig_port);
++ void (*unlock)(struct intel_digital_port *dig_port);
+ };
+
+ struct intel_dp_mst_encoder {
+@@ -1992,17 +2009,6 @@ dp_to_lspcon(struct intel_dp *intel_dp)
#define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
@@ -50207,10 +50683,18 @@ index cf10094acae3..90d0dbb41cfe 100644
#define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
-index 62ce92772367..9ff0cbd9c0df 100644
+index 62ce92772367..77ba6de6ba08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
-@@ -85,8 +85,8 @@
+@@ -56,6 +56,7 @@
+ #include "intel_cx0_phy.h"
+ #include "intel_ddi.h"
+ #include "intel_de.h"
++#include "intel_display_driver.h"
+ #include "intel_display_types.h"
+ #include "intel_dp.h"
+ #include "intel_dp_aux.h"
+@@ -85,8 +86,8 @@
#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
#define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
@@ -50221,7 +50705,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
/* Compliance test status bits */
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
-@@ -124,7 +124,31 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+@@ -124,7 +125,31 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
{
@@ -50254,7 +50738,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
}
static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
-@@ -331,6 +355,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
+@@ -331,6 +356,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
/*
* The required data bandwidth for a mode with given pixel clock and bpp. This
* is the required net bandwidth independent of the data bandwidth efficiency.
@@ -50264,7 +50748,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
*/
int
intel_dp_link_required(int pixel_clock, int bpp)
-@@ -339,6 +366,22 @@ intel_dp_link_required(int pixel_clock, int bpp)
+@@ -339,6 +367,22 @@ intel_dp_link_required(int pixel_clock, int bpp)
return DIV_ROUND_UP(pixel_clock * bpp, 8);
}
@@ -50287,7 +50771,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
/*
* Given a link rate and lanes, get the data bandwidth.
*
-@@ -362,29 +405,27 @@ intel_dp_link_required(int pixel_clock, int bpp)
+@@ -362,29 +406,27 @@ intel_dp_link_required(int pixel_clock, int bpp)
int
intel_dp_max_data_rate(int max_link_rate, int max_lanes)
{
@@ -50330,7 +50814,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
}
bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
-@@ -680,8 +721,22 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
+@@ -680,8 +722,22 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
{
@@ -50355,7 +50839,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
}
static int
-@@ -1373,9 +1428,9 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
+@@ -1373,9 +1429,9 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
return false;
}
@@ -50368,7 +50852,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
{
return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
drm_dp_sink_supports_fec(connector->dp.fec_capability);
-@@ -1388,6 +1443,7 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector,
+@@ -1388,6 +1444,7 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector,
return false;
return intel_dsc_source_support(crtc_state) &&
@@ -50376,7 +50860,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
}
-@@ -1721,15 +1777,15 @@ static bool intel_dp_dsc_supports_format(const struct intel_connector *connector
+@@ -1721,15 +1778,15 @@ static bool intel_dp_dsc_supports_format(const struct intel_connector *connector
return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
}
@@ -50395,7 +50879,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
return available_bw > required_bw;
}
-@@ -1737,7 +1793,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+@@ -1737,7 +1794,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
static int dsc_compute_link_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits,
@@ -50404,7 +50888,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
int timeslots)
{
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
-@@ -1752,8 +1808,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
+@@ -1752,8 +1809,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
@@ -50415,7 +50899,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
pipe_config->output_format,
timeslots))
continue;
-@@ -1795,7 +1851,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connec
+@@ -1795,7 +1852,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connec
return 0;
}
@@ -50424,7 +50908,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
{
/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
switch (pipe_config->output_format) {
-@@ -1812,9 +1868,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+@@ -1812,9 +1869,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
return 0;
}
@@ -50437,7 +50921,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
{
return intel_dp_dsc_max_sink_compressed_bppx16(connector,
pipe_config, bpc) >> 4;
-@@ -1834,7 +1890,7 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
+@@ -1834,7 +1891,7 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
* Max Compressed bpp for Gen 13+ is 27bpp.
* For earlier platform is 23bpp. (Bspec:49259).
*/
@@ -50446,7 +50930,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
return 23;
else
return 27;
-@@ -1866,10 +1922,11 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
+@@ -1866,10 +1923,11 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
@@ -50460,7 +50944,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
return 0;
}
}
-@@ -1885,6 +1942,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
+@@ -1885,6 +1943,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
*/
static int
xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
@@ -50468,7 +50952,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits,
int dsc_max_bpp,
-@@ -1892,22 +1950,38 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
+@@ -1892,22 +1951,38 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
int pipe_bpp,
int timeslots)
{
@@ -50515,7 +50999,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
return 0;
}
}
-@@ -1928,12 +2002,14 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+@@ -1928,12 +2003,14 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int dsc_joiner_max_bpp;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
@@ -50532,7 +51016,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
-@@ -1943,7 +2019,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+@@ -1943,7 +2020,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
if (DISPLAY_VER(i915) >= 13)
@@ -50541,7 +51025,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
-@@ -2088,19 +2164,22 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+@@ -2088,19 +2165,22 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
pipe_config->lane_count = limits->max_lane_count;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
@@ -50567,7 +51051,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
pipe_config->pipe_bpp = pipe_bpp;
-@@ -2122,8 +2201,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
+@@ -2122,8 +2202,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
&pipe_config->hw.adjusted_mode;
int ret;
@@ -50579,7 +51063,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
if (!intel_dp_supports_dsc(connector, pipe_config))
return -EINVAL;
-@@ -2188,18 +2268,18 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
+@@ -2188,18 +2269,18 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
ret = intel_dp_dsc_compute_params(connector, pipe_config);
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm,
@@ -50603,7 +51087,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
pipe_config->dsc.slice_count);
return 0;
-@@ -2311,6 +2391,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
+@@ -2311,6 +2392,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -50612,7 +51096,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-@@ -2319,6 +2401,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
+@@ -2319,6 +2402,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
@@ -50623,7 +51107,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
-@@ -2366,15 +2452,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
+@@ -2366,15 +2453,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
if (pipe_config->dsc.compression_enable) {
drm_dbg_kms(&i915->drm,
@@ -50642,7 +51126,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
intel_dp_max_data_rate(pipe_config->port_clock,
pipe_config->lane_count));
} else {
-@@ -2443,12 +2529,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
+@@ -2443,12 +2530,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -50671,7 +51155,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
vsc->length = 0x13;
/* DP 1.4a spec, Table 2-120 */
-@@ -2520,43 +2616,38 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+@@ -2520,43 +2617,38 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
@@ -50694,14 +51178,14 @@ index 62ce92772367..9ff0cbd9c0df 100644
- intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
- &crtc_state->infoframes.vsc);
-}
--
+
-void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state,
- struct drm_dp_vsc_sdp *vsc)
-{
- vsc->sdp_type = DP_SDP_VSC;
-
+-
- if (crtc_state->has_psr2) {
- if (intel_dp->psr.colorimetry_support &&
- intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
@@ -50740,7 +51224,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
} else {
/*
* [PSR1]
-@@ -2633,7 +2724,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
+@@ -2633,7 +2725,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
static void
intel_dp_drrs_compute_config(struct intel_connector *connector,
struct intel_crtc_state *pipe_config,
@@ -50749,7 +51233,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *downclock_mode =
-@@ -2658,9 +2749,10 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
+@@ -2658,9 +2750,10 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
if (pipe_config->splitter.enable)
pixel_clock /= pipe_config->splitter.link_count;
@@ -50763,7 +51247,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
-@@ -2736,19 +2828,12 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder,
+@@ -2736,19 +2829,12 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
@@ -50783,7 +51267,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
}
int
-@@ -2761,7 +2846,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
+@@ -2761,7 +2847,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct drm_display_mode *fixed_mode;
struct intel_connector *connector = intel_dp->attached_connector;
@@ -50792,7 +51276,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
pipe_config->has_pch_encoder = true;
-@@ -2810,10 +2895,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
+@@ -2810,10 +2896,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
drm_dp_enhanced_frame_cap(intel_dp->dpcd);
if (pipe_config->dsc.compression_enable)
@@ -50806,7 +51290,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;
-@@ -2837,12 +2922,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
+@@ -2837,12 +2923,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
@@ -50822,7 +51306,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
-@@ -2853,7 +2938,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
+@@ -2853,7 +2939,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_vrr_compute_config(pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
@@ -50831,7 +51315,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
-@@ -2921,24 +3006,179 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
+@@ -2921,24 +3007,179 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
@@ -51021,7 +51505,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
static void
intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
{
-@@ -3775,7 +4015,7 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
+@@ -3775,7 +4016,7 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -51030,7 +51514,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
intel_dp_mst_source_support(intel_dp) &&
drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
}
-@@ -3793,13 +4033,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
+@@ -3793,13 +4034,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
encoder->base.base.id, encoder->base.name,
str_yes_no(intel_dp_mst_source_support(intel_dp)),
str_yes_no(sink_can_mst),
@@ -51046,7 +51530,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
intel_dp->is_mst);
-@@ -3869,11 +4109,16 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+@@ -3869,11 +4110,16 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
@@ -51066,7 +51550,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
goto out;
/* VSC SDP Payload for DB16 through DB18 */
-@@ -4023,24 +4268,6 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
+@@ -4023,24 +4269,6 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,
dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
}
@@ -51091,7 +51575,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
-@@ -4053,7 +4280,10 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
+@@ -4053,7 +4281,10 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
@@ -51103,7 +51587,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
/* When PSR is enabled, this routine doesn't disable VSC DIP */
if (!crtc_state->has_psr)
val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
-@@ -4064,9 +4294,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
+@@ -4064,9 +4295,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
if (!enable)
return;
@@ -51114,7 +51598,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
-@@ -4197,10 +4425,6 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
+@@ -4197,10 +4426,6 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
struct dp_sdp sdp = {};
int ret;
@@ -51125,7 +51609,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
if ((crtc_state->infoframes.enable &
intel_hdmi_infoframe_enable(type)) == 0)
return;
-@@ -4411,31 +4635,36 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
+@@ -4411,31 +4636,36 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
struct drm_dp_phy_test_params *data =
&intel_dp->compliance.test_data.phytest;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -51167,7 +51651,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
/*
* FIXME: Ideally pattern should come from DPCD 0x250. As
* current firmware of DPR-100 could not set it, so hardcoding
-@@ -4453,7 +4682,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
+@@ -4453,7 +4683,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
DDI_DP_COMP_CTL_ENABLE |
DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -51176,7 +51660,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
/*
* FIXME: Ideally pattern should come from DPCD 0x24A. As
* current firmware of DPR-100 could not set it, so hardcoding
-@@ -4465,8 +4694,19 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
+@@ -4465,8 +4695,19 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
pattern_val);
break;
@@ -51197,7 +51681,91 @@ index 62ce92772367..9ff0cbd9c0df 100644
}
}
-@@ -5413,6 +5653,7 @@ intel_dp_detect(struct drm_connector *connector,
+@@ -5185,8 +5426,24 @@ edp_detect(struct intel_dp *intel_dp)
+ return connector_status_connected;
+ }
+
++void intel_digital_port_lock(struct intel_encoder *encoder)
++{
++ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
++
++ if (dig_port->lock)
++ dig_port->lock(dig_port);
++}
++
++void intel_digital_port_unlock(struct intel_encoder *encoder)
++{
++ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
++
++ if (dig_port->unlock)
++ dig_port->unlock(dig_port);
++}
++
+ /*
+- * intel_digital_port_connected - is the specified port connected?
++ * intel_digital_port_connected_locked - is the specified port connected?
+ * @encoder: intel_encoder
+ *
+ * In cases where there's a connector physically connected but it can't be used
+@@ -5194,21 +5451,44 @@ edp_detect(struct intel_dp *intel_dp)
+ * pretty much treat the port as disconnected. This is relevant for type-C
+ * (starting on ICL) where there's ownership involved.
+ *
++ * The caller must hold the lock acquired by calling intel_digital_port_lock()
++ * when calling this function.
++ *
+ * Return %true if port is connected, %false otherwise.
+ */
+-bool intel_digital_port_connected(struct intel_encoder *encoder)
++bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
+ {
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
++ bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
+ bool is_connected = false;
+ intel_wakeref_t wakeref;
+
+- with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+- is_connected = dig_port->connected(encoder);
++ with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
++ unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
++
++ do {
++ is_connected = dig_port->connected(encoder);
++ if (is_connected || is_glitch_free)
++ break;
++ usleep_range(10, 30);
++ } while (time_before(jiffies, wait_expires));
++ }
+
+ return is_connected;
+ }
+
++bool intel_digital_port_connected(struct intel_encoder *encoder)
++{
++ bool ret;
++
++ intel_digital_port_lock(encoder);
++ ret = intel_digital_port_connected_locked(encoder);
++ intel_digital_port_unlock(encoder);
++
++ return ret;
++}
++
+ static const struct drm_edid *
+ intel_dp_get_edid(struct intel_dp *intel_dp)
+ {
+@@ -5402,6 +5682,9 @@ intel_dp_detect(struct drm_connector *connector,
+ if (!intel_display_device_enabled(dev_priv))
+ return connector_status_disconnected;
+
++ if (!intel_display_driver_check_access(dev_priv))
++ return connector->status;
++
+ /* Can't disconnect eDP */
+ if (intel_dp_is_edp(intel_dp))
+ status = edp_detect(intel_dp);
+@@ -5413,6 +5696,7 @@ intel_dp_detect(struct drm_connector *connector,
if (status == connector_status_disconnected) {
memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
@@ -51205,7 +51773,35 @@ index 62ce92772367..9ff0cbd9c0df 100644
if (intel_dp->is_mst) {
drm_dbg_kms(&dev_priv->drm,
-@@ -6258,15 +6499,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
+@@ -5501,6 +5785,10 @@ intel_dp_force(struct drm_connector *connector)
+
+ drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
+ connector->base.id, connector->name);
++
++ if (!intel_display_driver_check_access(dev_priv))
++ return;
++
+ intel_dp_unset_edid(intel_dp);
+
+ if (connector->status != connector_status_connected)
+@@ -5785,7 +6073,7 @@ static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
+ spin_unlock_irq(&i915->irq_lock);
+
+ if (need_work)
+- queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0);
++ intel_hpd_schedule_detection(i915);
+ }
+
+ static const struct drm_connector_funcs intel_dp_connector_funcs = {
+@@ -6228,6 +6516,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
+ connector->interlace_allowed = true;
+
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
++ intel_connector->base.polled = intel_connector->polled;
+
+ intel_connector_attach_encoder(intel_connector, intel_encoder);
+
+@@ -6258,15 +6547,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
"HDCP init failed, skipping.\n");
}
@@ -51224,7 +51820,7 @@ index 62ce92772367..9ff0cbd9c0df 100644
intel_dp->frl.is_trained = false;
intel_dp->frl.trained_rate_gbps = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
-index 484aea215a25..b911706d2e95 100644
+index 484aea215a25..530cc97bc42f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -57,9 +57,12 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
@@ -51252,7 +51848,7 @@ index 484aea215a25..b911706d2e95 100644
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
bool long_hpd);
-@@ -98,17 +103,12 @@ bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
+@@ -98,24 +103,22 @@ bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
int intel_dp_link_required(int pixel_clock, int bpp);
@@ -51272,7 +51868,17 @@ index 484aea215a25..b911706d2e95 100644
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-@@ -125,6 +125,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ void intel_read_dp_sdp(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ unsigned int type);
++void intel_digital_port_lock(struct intel_encoder *encoder);
++void intel_digital_port_unlock(struct intel_encoder *encoder);
+ bool intel_digital_port_connected(struct intel_encoder *encoder);
++bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
+ int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
+ u8 dsc_max_bpc);
+ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+@@ -125,6 +128,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
@@ -51283,7 +51889,7 @@ index 484aea215a25..b911706d2e95 100644
u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
-@@ -136,7 +140,16 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
+@@ -136,7 +143,16 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
return ~((1 << lane_count) - 1) & 0xf;
}
@@ -51301,10 +51907,18 @@ index 484aea215a25..b911706d2e95 100644
void intel_ddi_update_pipe(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
-index 4431b6290c4c..2e2af71bcd5a 100644
+index 4431b6290c4c..4f4a0e3b3114 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
-@@ -74,7 +74,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
+@@ -9,6 +9,7 @@
+ #include "intel_bios.h"
+ #include "intel_de.h"
+ #include "intel_display_types.h"
++#include "intel_dp.h"
+ #include "intel_dp_aux.h"
+ #include "intel_dp_aux_regs.h"
+ #include "intel_pps.h"
+@@ -74,7 +75,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
@@ -51313,7 +51927,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
if (index)
return 0;
-@@ -83,12 +83,12 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+@@ -83,12 +84,12 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
* The clock divider is based off the hrawclk, and would like to run at
* 2MHz. So, take the hrawclk value and divide by 2000 and use that
*/
@@ -51328,7 +51942,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
u32 freq;
-@@ -101,18 +101,18 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+@@ -101,18 +102,18 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
* divide by 2000 and use that
*/
if (dig_port->aux_ch == AUX_CH_A)
@@ -51351,7 +51965,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
/* Workaround for non-ULT HSW */
switch (index) {
case 0: return 63;
-@@ -165,12 +165,11 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
+@@ -165,12 +166,11 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
u32 aux_clock_divider)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -51366,17 +51980,59 @@ index 4431b6290c4c..2e2af71bcd5a 100644
timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
else
timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
-@@ -229,8 +228,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
+@@ -229,10 +229,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
u32 aux_send_ctl_flags)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *i915 =
- to_i915(dig_port->base.base.dev);
+- enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+- bool is_tc_port = intel_phy_is_tc(i915, phy);
++ struct intel_encoder *encoder = &dig_port->base;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
- bool is_tc_port = intel_phy_is_tc(i915, phy);
i915_reg_t ch_ctl, ch_data[5];
-@@ -531,9 +529,40 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
+ u32 aux_clock_divider;
+ enum intel_display_power_domain aux_domain;
+@@ -247,18 +245,16 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
+ for (i = 0; i < ARRAY_SIZE(ch_data); i++)
+ ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
+
+- if (is_tc_port) {
+- intel_tc_port_lock(dig_port);
+- /*
+- * Abort transfers on a disconnected port as required by
+- * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX
+- * timeouts that would otherwise happen.
+- * TODO: abort the transfer on non-TC ports as well.
+- */
+- if (!intel_tc_port_connected_locked(&dig_port->base)) {
+- ret = -ENXIO;
+- goto out_unlock;
+- }
++ intel_digital_port_lock(encoder);
++ /*
++ * Abort transfers on a disconnected port as required by
++ * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX
++ * timeouts that would otherwise happen.
++ */
++ if (!intel_dp_is_edp(intel_dp) &&
++ !intel_digital_port_connected_locked(&dig_port->base)) {
++ ret = -ENXIO;
++ goto out_unlock;
+ }
+
+ aux_domain = intel_aux_power_domain(dig_port);
+@@ -425,8 +421,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
+ intel_pps_unlock(intel_dp, pps_wakeref);
+ intel_display_power_put_async(i915, aux_domain, aux_wakeref);
+ out_unlock:
+- if (is_tc_port)
+- intel_tc_port_unlock(dig_port);
++ intel_digital_port_unlock(encoder);
+
+ return ret;
+ }
+@@ -531,9 +526,40 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
return ret;
}
@@ -51418,7 +52074,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -550,7 +579,6 @@ static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
+@@ -550,7 +576,6 @@ static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
{
@@ -51426,7 +52082,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -567,7 +595,6 @@ static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
+@@ -567,7 +592,6 @@ static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
{
@@ -51434,7 +52090,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -586,7 +613,6 @@ static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
+@@ -586,7 +610,6 @@ static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
{
@@ -51442,7 +52098,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -605,7 +631,6 @@ static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
+@@ -605,7 +628,6 @@ static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
{
@@ -51450,7 +52106,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -625,7 +650,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
+@@ -625,7 +647,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
{
@@ -51458,7 +52114,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -645,7 +669,6 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
+@@ -645,7 +666,6 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
{
@@ -51466,7 +52122,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -668,7 +691,6 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+@@ -668,7 +688,6 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
{
@@ -51474,7 +52130,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -691,7 +713,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+@@ -691,7 +710,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
{
@@ -51483,7 +52139,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -702,16 +724,16 @@ static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
+@@ -702,16 +721,16 @@ static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
@@ -51503,7 +52159,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum aux_ch aux_ch = dig_port->aux_ch;
-@@ -722,10 +744,10 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
+@@ -722,10 +741,10 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
@@ -51516,7 +52172,7 @@ index 4431b6290c4c..2e2af71bcd5a 100644
}
}
-@@ -739,49 +761,52 @@ void intel_dp_aux_fini(struct intel_dp *intel_dp)
+@@ -739,49 +758,52 @@ void intel_dp_aux_fini(struct intel_dp *intel_dp)
void intel_dp_aux_init(struct intel_dp *intel_dp)
{
@@ -51643,7 +52299,7 @@ index 34f6e0a48ed2..e642445364d2 100644
_MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
_DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
-index aa1061262613..8a9432335030 100644
+index aa1061262613..5fa25a5a36b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -26,6 +26,7 @@
@@ -51654,7 +52310,15 @@ index aa1061262613..8a9432335030 100644
#include <drm/drm_probe_helper.h>
#include "i915_drv.h"
-@@ -43,6 +44,9 @@
+@@ -36,6 +37,7 @@
+ #include "intel_crtc.h"
+ #include "intel_ddi.h"
+ #include "intel_de.h"
++#include "intel_display_driver.h"
+ #include "intel_display_types.h"
+ #include "intel_dp.h"
+ #include "intel_dp_hdcp.h"
+@@ -43,6 +45,9 @@
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
@@ -51664,7 +52328,7 @@ index aa1061262613..8a9432335030 100644
#include "skl_scaler.h"
static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
-@@ -50,7 +54,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
+@@ -50,7 +55,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
struct intel_crtc_state *crtc_state,
bool dsc)
{
@@ -51673,7 +52337,7 @@ index aa1061262613..8a9432335030 100644
int output_bpp = bpp;
/* DisplayPort 2 128b/132b, bits per lane is always 32 */
int symbol_clock = crtc_state->port_clock / 32;
-@@ -66,6 +70,73 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
+@@ -66,6 +71,73 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
return 0;
}
@@ -51747,7 +52411,7 @@ index aa1061262613..8a9432335030 100644
static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
int max_bpp,
-@@ -94,20 +165,67 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
+@@ -94,20 +166,67 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->lane_count = limits->max_lane_count;
crtc_state->port_clock = limits->max_rate;
@@ -51818,7 +52482,7 @@ index aa1061262613..8a9432335030 100644
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
-@@ -116,13 +234,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
+@@ -116,13 +235,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
return slots;
if (slots >= 0) {
@@ -51835,7 +52499,7 @@ index aa1061262613..8a9432335030 100644
}
}
-@@ -137,7 +251,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
+@@ -137,7 +252,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
if (!dsc)
crtc_state->pipe_bpp = bpp;
else
@@ -51844,7 +52508,7 @@ index aa1061262613..8a9432335030 100644
drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
}
-@@ -149,10 +263,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
+@@ -149,10 +264,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state,
struct link_config_limits *limits)
{
@@ -51855,7 +52519,7 @@ index aa1061262613..8a9432335030 100644
/*
* FIXME: allocate the BW according to link_bpp, which in the case of
-@@ -167,16 +278,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
+@@ -167,16 +279,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
if (slots < 0)
return slots;
@@ -51872,7 +52536,7 @@ index aa1061262613..8a9432335030 100644
return 0;
}
-@@ -188,15 +289,12 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
+@@ -188,15 +290,12 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
@@ -51889,7 +52553,7 @@ index aa1061262613..8a9432335030 100644
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
if (DISPLAY_VER(i915) >= 12)
-@@ -232,45 +330,31 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
+@@ -232,45 +331,31 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
@@ -51955,7 +52619,7 @@ index aa1061262613..8a9432335030 100644
return 0;
}
-@@ -297,8 +381,103 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
+@@ -297,8 +382,103 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
return 0;
}
@@ -52059,7 +52723,7 @@ index aa1061262613..8a9432335030 100644
struct intel_crtc_state *crtc_state,
bool dsc,
struct link_config_limits *limits)
-@@ -326,10 +505,16 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
+@@ -326,10 +506,16 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
@@ -52080,7 +52744,7 @@ index aa1061262613..8a9432335030 100644
}
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
-@@ -339,12 +524,18 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
+@@ -339,12 +525,18 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_dp *intel_dp = &intel_mst->primary->dp;
@@ -52099,7 +52763,7 @@ index aa1061262613..8a9432335030 100644
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
-@@ -354,6 +545,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
+@@ -354,6 +546,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
dsc_needed = intel_dp->force_dsc_en ||
!intel_dp_mst_compute_config_limits(intel_dp,
@@ -52107,7 +52771,7 @@ index aa1061262613..8a9432335030 100644
pipe_config,
false,
&limits);
-@@ -375,7 +567,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
+@@ -375,7 +568,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
str_yes_no(ret),
str_yes_no(intel_dp->force_dsc_en));
@@ -52119,7 +52783,7 @@ index aa1061262613..8a9432335030 100644
pipe_config,
true,
&limits))
-@@ -418,7 +614,9 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
+@@ -418,7 +615,9 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
@@ -52130,7 +52794,7 @@ index aa1061262613..8a9432335030 100644
return 0;
}
-@@ -459,6 +657,130 @@ intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
+@@ -459,6 +658,130 @@ intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
return transcoders;
}
@@ -52261,7 +52925,7 @@ index aa1061262613..8a9432335030 100644
static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
-@@ -479,19 +801,23 @@ static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
+@@ -479,19 +802,23 @@ static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
* that shares the same MST stream as mode changed,
* intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
* a fastset when possible.
@@ -52290,7 +52954,7 @@ index aa1061262613..8a9432335030 100644
if (!intel_connector_needs_modeset(state, &connector->base))
return 0;
-@@ -545,7 +871,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
+@@ -545,7 +872,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
if (ret)
return ret;
@@ -52299,7 +52963,7 @@ index aa1061262613..8a9432335030 100644
if (ret)
return ret;
-@@ -587,10 +913,6 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
+@@ -587,10 +914,6 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
struct intel_dp *intel_dp = &dig_port->dp;
struct intel_connector *connector =
to_intel_connector(old_conn_state->connector);
@@ -52310,7 +52974,7 @@ index aa1061262613..8a9432335030 100644
struct drm_i915_private *i915 = to_i915(connector->base.dev);
drm_dbg_kms(&i915->drm, "active links %d\n",
-@@ -598,9 +920,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
+@@ -598,9 +921,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
intel_hdcp_disable(intel_mst->connector);
@@ -52321,7 +52985,7 @@ index aa1061262613..8a9432335030 100644
}
static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
-@@ -634,6 +954,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
+@@ -634,6 +955,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
intel_disable_transcoder(old_crtc_state);
@@ -52330,7 +52994,7 @@ index aa1061262613..8a9432335030 100644
clear_act_sent(encoder, old_crtc_state);
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
-@@ -646,6 +968,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
+@@ -646,6 +969,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
intel_ddi_disable_transcoder_func(old_crtc_state);
@@ -52339,7 +53003,7 @@ index aa1061262613..8a9432335030 100644
if (DISPLAY_VER(dev_priv) >= 9)
skl_scaler_disable(old_crtc_state);
else
-@@ -662,9 +986,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
+@@ -662,9 +987,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
* BSpec 4287: disable DIP after the transcoder is disabled and before
* the transcoder clock select is set to none.
*/
@@ -52351,7 +53015,7 @@ index aa1061262613..8a9432335030 100644
/*
* From TGL spec: "If multi-stream slave transcoder: Configure
* Transcoder Clock Select to direct no clock to the transcoder"
-@@ -754,6 +1077,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
+@@ -754,6 +1078,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
@@ -52360,7 +53024,7 @@ index aa1061262613..8a9432335030 100644
if (first_mst_stream)
dig_port->base.pre_enable(state, &dig_port->base,
pipe_config, NULL);
-@@ -776,6 +1101,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
+@@ -776,6 +1102,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
intel_ddi_enable_transcoder_clock(encoder, pipe_config);
@@ -52368,7 +53032,7 @@ index aa1061262613..8a9432335030 100644
intel_ddi_set_dp_msa(pipe_config, conn_state);
}
-@@ -792,11 +1118,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
+@@ -792,11 +1119,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
struct drm_dp_mst_topology_state *mst_state =
drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
enum transcoder trans = pipe_config->cpu_transcoder;
@@ -52381,7 +53045,7 @@ index aa1061262613..8a9432335030 100644
if (intel_dp_is_uhbr(pipe_config)) {
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
-@@ -810,6 +1135,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
+@@ -810,6 +1136,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
intel_ddi_enable_transcoder_func(encoder, pipe_config);
@@ -52390,7 +53054,7 @@ index aa1061262613..8a9432335030 100644
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
-@@ -818,15 +1145,16 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
+@@ -818,15 +1146,16 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
wait_for_act_sent(encoder, pipe_config);
@@ -52413,7 +53077,7 @@ index aa1061262613..8a9432335030 100644
intel_audio_sdp_split_update(pipe_config);
-@@ -834,12 +1162,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
+@@ -834,12 +1163,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
intel_crtc_vblank_on(pipe_config);
@@ -52427,7 +53091,7 @@ index aa1061262613..8a9432335030 100644
}
static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
-@@ -978,8 +1301,20 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
+@@ -978,8 +1302,20 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
if (ret)
return ret;
@@ -52449,7 +53113,17 @@ index aa1061262613..8a9432335030 100644
*status = MODE_CLOCK_HIGH;
return 0;
}
-@@ -1151,6 +1486,36 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
+@@ -1075,6 +1411,9 @@ intel_dp_mst_detect(struct drm_connector *connector,
+ if (drm_connector_is_unregistered(connector))
+ return connector_status_disconnected;
+
++ if (!intel_display_driver_check_access(i915))
++ return connector->status;
++
+ return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
+ intel_connector->port);
+ }
+@@ -1151,6 +1490,36 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
}
@@ -52486,7 +53160,7 @@ index aa1061262613..8a9432335030 100644
static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
const char *pathprop)
-@@ -1173,13 +1538,10 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
+@@ -1173,13 +1542,10 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_connector->port = port;
drm_dp_mst_get_port_malloc(port);
@@ -52503,7 +53177,7 @@ index aa1061262613..8a9432335030 100644
connector = &intel_connector->base;
ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
-@@ -1272,6 +1634,8 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
+@@ -1272,6 +1638,8 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
intel_encoder->pre_enable = intel_mst_pre_enable_dp;
intel_encoder->enable = intel_mst_enable_dp;
@@ -52512,7 +53186,7 @@ index aa1061262613..8a9432335030 100644
intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
intel_encoder->get_config = intel_dp_mst_enc_get_config;
intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
-@@ -1419,3 +1783,91 @@ int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
+@@ -1419,3 +1787,91 @@ int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
return 0;
}
@@ -55003,6 +55677,36 @@ index 468d873fab1a..3462fcc760e6 100644
void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
enum mipi_seq seq_id);
void intel_dsi_log_params(struct intel_dsi *intel_dsi);
+diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
+index 9111e9d46486..8ca9ae4798a8 100644
+--- a/drivers/gpu/drm/i915/display/intel_dvo.c
++++ b/drivers/gpu/drm/i915/display/intel_dvo.c
+@@ -35,6 +35,7 @@
+ #include "i915_reg.h"
+ #include "intel_connector.h"
+ #include "intel_de.h"
++#include "intel_display_driver.h"
+ #include "intel_display_types.h"
+ #include "intel_dvo.h"
+ #include "intel_dvo_dev.h"
+@@ -328,6 +329,9 @@ intel_dvo_detect(struct drm_connector *_connector, bool force)
+ if (!intel_display_device_enabled(i915))
+ return connector_status_disconnected;
+
++ if (!intel_display_driver_check_access(i915))
++ return connector->base.status;
++
+ return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
+ }
+
+@@ -536,6 +540,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
+ if (intel_dvo->dev.type == INTEL_DVO_CHIP_TMDS)
+ connector->polled = DRM_CONNECTOR_POLL_CONNECT |
+ DRM_CONNECTOR_POLL_DISCONNECT;
++ connector->base.polled = connector->polled;
+
+ drm_connector_init_with_ddc(&i915->drm, &connector->base,
+ &intel_dvo_connector_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 646f367a13f5..0c0144eaa8fa 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
@@ -56460,10 +57164,18 @@ index 8023c85c7fa0..a568a457e532 100644
PORT_HDCP2_AUTH_STREAM(port))
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
-index bfa456fa7d25..eedef8121ff7 100644
+index bfa456fa7d25..7020e5806109 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
-@@ -523,10 +523,12 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
+@@ -49,6 +49,7 @@
+ #include "intel_cx0_phy.h"
+ #include "intel_ddi.h"
+ #include "intel_de.h"
++#include "intel_display_driver.h"
+ #include "intel_display_types.h"
+ #include "intel_dp.h"
+ #include "intel_gmbus.h"
+@@ -523,10 +524,12 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
0);
/* Wa_14013475917 */
@@ -56479,7 +57191,35 @@ index bfa456fa7d25..eedef8121ff7 100644
intel_de_write(dev_priv, ctl_reg, val);
intel_de_posting_read(dev_priv, ctl_reg);
}
-@@ -3034,16 +3036,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
+@@ -2503,6 +2506,9 @@ intel_hdmi_detect(struct drm_connector *connector, bool force)
+ if (!intel_display_device_enabled(dev_priv))
+ return connector_status_disconnected;
+
++ if (!intel_display_driver_check_access(dev_priv))
++ return connector->status;
++
+ wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
+
+ if (DISPLAY_VER(dev_priv) >= 11 &&
+@@ -2531,6 +2537,9 @@ intel_hdmi_force(struct drm_connector *connector)
+ drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
+ connector->base.id, connector->name);
+
++ if (!intel_display_driver_check_access(i915))
++ return;
++
+ intel_hdmi_unset_edid(connector);
+
+ if (connector->status != connector_status_connected)
+@@ -3015,6 +3024,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
+ connector->ycbcr_420_allowed = true;
+
+ intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
++ intel_connector->base.polled = intel_connector->polled;
+
+ if (HAS_DDI(dev_priv))
+ intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
+@@ -3034,16 +3044,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
"HDCP init failed, skipping.\n");
}
@@ -56496,6 +57236,288 @@ index bfa456fa7d25..eedef8121ff7 100644
cec_fill_conn_info_from_drm(&conn_info, connector);
intel_hdmi->cec_notifier =
+diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
+index 0c0700c6ec66..d9ec349f3c8c 100644
+--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
++++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
+@@ -177,6 +177,46 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
+ return storm;
+ }
+
++static bool detection_work_enabled(struct drm_i915_private *i915)
++{
++ lockdep_assert_held(&i915->irq_lock);
++
++ return i915->display.hotplug.detection_work_enabled;
++}
++
++static bool
++mod_delayed_detection_work(struct drm_i915_private *i915, struct delayed_work *work, int delay)
++{
++ lockdep_assert_held(&i915->irq_lock);
++
++ if (!detection_work_enabled(i915))
++ return false;
++
++ return mod_delayed_work(i915->unordered_wq, work, delay);
++}
++
++static bool
++queue_delayed_detection_work(struct drm_i915_private *i915, struct delayed_work *work, int delay)
++{
++ lockdep_assert_held(&i915->irq_lock);
++
++ if (!detection_work_enabled(i915))
++ return false;
++
++ return queue_delayed_work(i915->unordered_wq, work, delay);
++}
++
++static bool
++queue_detection_work(struct drm_i915_private *i915, struct work_struct *work)
++{
++ lockdep_assert_held(&i915->irq_lock);
++
++ if (!detection_work_enabled(i915))
++ return false;
++
++ return queue_work(i915->unordered_wq, work);
++}
++
+ static void
+ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
+ {
+@@ -213,9 +253,9 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
+ /* Enable polling and queue hotplug re-enabling. */
+ if (hpd_disabled) {
+ drm_kms_helper_poll_reschedule(&dev_priv->drm);
+- mod_delayed_work(dev_priv->unordered_wq,
+- &dev_priv->display.hotplug.reenable_work,
+- msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
++ mod_delayed_detection_work(dev_priv,
++ &dev_priv->display.hotplug.reenable_work,
++ msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
+ }
+ }
+
+@@ -348,9 +388,9 @@ static void i915_digport_work_func(struct work_struct *work)
+ if (old_bits) {
+ spin_lock_irq(&dev_priv->irq_lock);
+ dev_priv->display.hotplug.event_bits |= old_bits;
++ queue_delayed_detection_work(dev_priv,
++ &dev_priv->display.hotplug.hotplug_work, 0);
+ spin_unlock_irq(&dev_priv->irq_lock);
+- queue_delayed_work(dev_priv->unordered_wq,
+- &dev_priv->display.hotplug.hotplug_work, 0);
+ }
+ }
+
+@@ -467,11 +507,11 @@ static void i915_hotplug_work_func(struct work_struct *work)
+ if (retry) {
+ spin_lock_irq(&dev_priv->irq_lock);
+ dev_priv->display.hotplug.retry_bits |= retry;
+- spin_unlock_irq(&dev_priv->irq_lock);
+
+- mod_delayed_work(dev_priv->unordered_wq,
+- &dev_priv->display.hotplug.hotplug_work,
+- msecs_to_jiffies(HPD_RETRY_DELAY));
++ mod_delayed_detection_work(dev_priv,
++ &dev_priv->display.hotplug.hotplug_work,
++ msecs_to_jiffies(HPD_RETRY_DELAY));
++ spin_unlock_irq(&dev_priv->irq_lock);
+ }
+ }
+
+@@ -590,7 +630,6 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
+ */
+ if (storm_detected)
+ intel_hpd_irq_setup(dev_priv);
+- spin_unlock(&dev_priv->irq_lock);
+
+ /*
+ * Our hotplug handler can grab modeset locks (by calling down into the
+@@ -601,8 +640,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
+ if (queue_dig)
+ queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work);
+ if (queue_hp)
+- queue_delayed_work(dev_priv->unordered_wq,
+- &dev_priv->display.hotplug.hotplug_work, 0);
++ queue_delayed_detection_work(dev_priv,
++ &dev_priv->display.hotplug.hotplug_work, 0);
++
++ spin_unlock(&dev_priv->irq_lock);
+ }
+
+ /**
+@@ -710,6 +751,8 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
+ cancel_work(&dev_priv->display.hotplug.poll_init_work);
+ }
+
++ spin_lock_irq(&dev_priv->irq_lock);
++
+ drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ enum hpd_pin pin;
+@@ -718,6 +761,9 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
+ if (pin == HPD_NONE)
+ continue;
+
++ if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
++ continue;
++
+ connector->base.polled = connector->polled;
+
+ if (enabled && connector->base.polled == DRM_CONNECTOR_POLL_HPD)
+@@ -726,6 +772,8 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
++ spin_unlock_irq(&dev_priv->irq_lock);
++
+ if (enabled)
+ drm_kms_helper_poll_reschedule(&dev_priv->drm);
+
+@@ -774,8 +822,10 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
+ * As well, there's no issue if we race here since we always reschedule
+ * this worker anyway
+ */
+- queue_work(dev_priv->unordered_wq,
+- &dev_priv->display.hotplug.poll_init_work);
++ spin_lock_irq(&dev_priv->irq_lock);
++ queue_detection_work(dev_priv,
++ &dev_priv->display.hotplug.poll_init_work);
++ spin_unlock_irq(&dev_priv->irq_lock);
+ }
+
+ /**
+@@ -803,8 +853,11 @@ void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
+ return;
+
+ WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, false);
+- queue_work(dev_priv->unordered_wq,
+- &dev_priv->display.hotplug.poll_init_work);
++
++ spin_lock_irq(&dev_priv->irq_lock);
++ queue_detection_work(dev_priv,
++ &dev_priv->display.hotplug.poll_init_work);
++ spin_unlock_irq(&dev_priv->irq_lock);
+ }
+
+ void intel_hpd_init_early(struct drm_i915_private *i915)
+@@ -826,6 +879,20 @@ void intel_hpd_init_early(struct drm_i915_private *i915)
+ i915->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(i915);
+ }
+
++static bool cancel_all_detection_work(struct drm_i915_private *i915)
++{
++ bool was_pending = false;
++
++ if (cancel_delayed_work_sync(&i915->display.hotplug.hotplug_work))
++ was_pending = true;
++ if (cancel_work_sync(&i915->display.hotplug.poll_init_work))
++ was_pending = true;
++ if (cancel_delayed_work_sync(&i915->display.hotplug.reenable_work))
++ was_pending = true;
++
++ return was_pending;
++}
++
+ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
+ {
+ if (!HAS_DISPLAY(dev_priv))
+@@ -841,9 +908,13 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
+ spin_unlock_irq(&dev_priv->irq_lock);
+
+ cancel_work_sync(&dev_priv->display.hotplug.dig_port_work);
+- cancel_delayed_work_sync(&dev_priv->display.hotplug.hotplug_work);
+- cancel_work_sync(&dev_priv->display.hotplug.poll_init_work);
+- cancel_delayed_work_sync(&dev_priv->display.hotplug.reenable_work);
++
++ /*
++ * All other work triggered by hotplug events should be canceled by
++ * now.
++ */
++ if (cancel_all_detection_work(dev_priv))
++ drm_dbg_kms(&dev_priv->drm, "Hotplug detection work still active\n");
+ }
+
+ bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
+@@ -873,6 +944,62 @@ void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
+ spin_unlock_irq(&dev_priv->irq_lock);
+ }
+
++static void queue_work_for_missed_irqs(struct drm_i915_private *i915)
++{
++ bool queue_work = false;
++ enum hpd_pin pin;
++
++ lockdep_assert_held(&i915->irq_lock);
++
++ if (i915->display.hotplug.event_bits ||
++ i915->display.hotplug.retry_bits)
++ queue_work = true;
++
++ for_each_hpd_pin(pin) {
++ switch (i915->display.hotplug.stats[pin].state) {
++ case HPD_MARK_DISABLED:
++ queue_work = true;
++ break;
++ case HPD_ENABLED:
++ break;
++ default:
++ MISSING_CASE(i915->display.hotplug.stats[pin].state);
++ }
++ }
++
++ if (queue_work)
++ queue_delayed_detection_work(i915, &i915->display.hotplug.hotplug_work, 0);
++}
++
++void intel_hpd_enable_detection_work(struct drm_i915_private *i915)
++{
++ spin_lock_irq(&i915->irq_lock);
++ i915->display.hotplug.detection_work_enabled = true;
++ queue_work_for_missed_irqs(i915);
++ spin_unlock_irq(&i915->irq_lock);
++}
++
++void intel_hpd_disable_detection_work(struct drm_i915_private *i915)
++{
++ spin_lock_irq(&i915->irq_lock);
++ i915->display.hotplug.detection_work_enabled = false;
++ spin_unlock_irq(&i915->irq_lock);
++
++ cancel_all_detection_work(i915);
++}
++
++bool intel_hpd_schedule_detection(struct drm_i915_private *i915)
++{
++ unsigned long flags;
++ bool ret;
++
++ spin_lock_irqsave(&i915->irq_lock, flags);
++ ret = queue_delayed_detection_work(i915, &i915->display.hotplug.hotplug_work, 0);
++ spin_unlock_irqrestore(&i915->irq_lock, flags);
++
++ return ret;
++}
++
+ static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
+ {
+ struct drm_i915_private *dev_priv = m->private;
+diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h
+index 424ae5dbf5a0..a17253ddec83 100644
+--- a/drivers/gpu/drm/i915/display/intel_hotplug.h
++++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
+@@ -30,4 +30,8 @@ bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
+ void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
+ void intel_hpd_debugfs_register(struct drm_i915_private *i915);
+
++void intel_hpd_enable_detection_work(struct drm_i915_private *i915);
++void intel_hpd_disable_detection_work(struct drm_i915_private *i915);
++bool intel_hpd_schedule_detection(struct drm_i915_private *i915);
++
+ #endif /* __INTEL_HOTPLUG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index f07047e9cb30..76076509f771 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -56739,10 +57761,18 @@ index 84078fb82b2f..1ce785db6a5e 100644
if (!name || !*name)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
-index 483beedac5b8..0d8e5320a4f8 100644
+index 483beedac5b8..073ea3166c36 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
-@@ -46,8 +46,8 @@
+@@ -37,6 +37,7 @@
+ #include "intel_backlight.h"
+ #include "intel_connector.h"
+ #include "intel_de.h"
++#include "intel_display_driver.h"
+ #include "intel_display_types.h"
+ #include "intel_drrs.h"
+ #include "intel_lvds_regs.h"
+@@ -46,8 +47,8 @@
bool intel_panel_use_ssc(struct drm_i915_private *i915)
{
@@ -56753,6 +57783,16 @@ index 483beedac5b8..0d8e5320a4f8 100644
return i915->display.vbt.lvds_use_ssc &&
!intel_has_quirk(i915, QUIRK_LVDS_SSC_DISABLE);
}
+@@ -683,6 +684,9 @@ intel_panel_detect(struct drm_connector *connector, bool force)
+ if (!intel_display_device_enabled(i915))
+ return connector_status_disconnected;
+
++ if (!intel_display_driver_check_access(i915))
++ return connector->status;
++
+ return connector_status_connected;
+ }
+
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 866786e6b32f..baf679759e00 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -57736,7 +58776,7 @@ index 543cdc46aa1d..600c815e37e4 100644
static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
-index a9ac7d45d1f3..acc6b6804105 100644
+index a9ac7d45d1f3..2571ef5a1b21 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -35,6 +35,7 @@
@@ -57747,7 +58787,15 @@ index a9ac7d45d1f3..acc6b6804105 100644
#include "i915_drv.h"
#include "i915_reg.h"
-@@ -1787,17 +1788,28 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
+@@ -43,6 +44,7 @@
+ #include "intel_connector.h"
+ #include "intel_crtc.h"
+ #include "intel_de.h"
++#include "intel_display_driver.h"
+ #include "intel_display_types.h"
+ #include "intel_fdi.h"
+ #include "intel_fifo_underrun.h"
+@@ -1787,17 +1789,28 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
intel_sdvo_get_eld(intel_sdvo, pipe_config);
}
@@ -57778,7 +58826,7 @@ index a9ac7d45d1f3..acc6b6804105 100644
intel_sdvo_set_audio_state(intel_sdvo, 0);
intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
-@@ -1818,8 +1830,7 @@ static void intel_disable_sdvo(struct intel_atomic_state *state,
+@@ -1818,8 +1831,7 @@ static void intel_disable_sdvo(struct intel_atomic_state *state,
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
u32 temp;
@@ -57788,7 +58836,7 @@ index a9ac7d45d1f3..acc6b6804105 100644
intel_sdvo_set_active_outputs(intel_sdvo, 0);
if (0)
-@@ -1913,8 +1924,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state,
+@@ -1913,8 +1925,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state,
DRM_MODE_DPMS_ON);
intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag);
@@ -57798,7 +58846,33 @@ index a9ac7d45d1f3..acc6b6804105 100644
}
static enum drm_mode_status
-@@ -3317,7 +3327,6 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
+@@ -2130,6 +2141,9 @@ intel_sdvo_detect(struct drm_connector *connector, bool force)
+ if (!intel_display_device_enabled(i915))
+ return connector_status_disconnected;
+
++ if (!intel_display_driver_check_access(i915))
++ return connector->status;
++
+ if (!intel_sdvo_set_target_output(intel_sdvo,
+ intel_sdvo_connector->output_flag))
+ return connector_status_unknown;
+@@ -2795,6 +2809,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type)
+ } else {
+ intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
+ }
++ intel_connector->base.polled = intel_connector->polled;
+ encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
+ connector->connector_type = DRM_MODE_CONNECTOR_DVID;
+
+@@ -2870,6 +2885,7 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type)
+ intel_connector = &intel_sdvo_connector->base;
+ connector = &intel_connector->base;
+ intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
++ intel_connector->base.polled = intel_connector->polled;
+ encoder->encoder_type = DRM_MODE_ENCODER_DAC;
+ connector->connector_type = DRM_MODE_CONNECTOR_VGA;
+
+@@ -3317,7 +3333,6 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
ddc->ddc_bus = ddc_bus;
ddc->ddc.owner = THIS_MODULE;
@@ -57806,7 +58880,7 @@ index a9ac7d45d1f3..acc6b6804105 100644
snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d",
port_name(sdvo->base.port), ddc_bus);
ddc->ddc.dev.parent = &pdev->dev;
-@@ -3396,6 +3405,8 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
+@@ -3396,6 +3411,8 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
}
intel_encoder->pre_enable = intel_sdvo_pre_enable;
intel_encoder->enable = intel_enable_sdvo;
@@ -57854,10 +58928,26 @@ index 1fb16510f750..d7b440c8caef 100644
if (ret)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
-index f64d348a969e..dcf05e00e505 100644
+index f64d348a969e..f34743e6eeed 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
-@@ -1030,18 +1030,25 @@ static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enabl
+@@ -122,6 +122,15 @@ bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port)
+ return intel_tc_port_in_mode(dig_port, TC_PORT_LEGACY);
+ }
+
++bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port)
++{
++ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
++ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
++ struct intel_tc_port *tc = to_tc_port(dig_port);
++
++ return intel_phy_is_tc(i915, phy) && !tc->legacy_port;
++}
++
+ /*
+ * The display power domains used for TC ports depending on the
+ * platform and TC mode (legacy, DP-alt, TBT):
+@@ -1030,18 +1039,25 @@ static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enabl
__xelpdp_tc_phy_enable_tcss_power(tc, enable);
@@ -57892,11 +58982,63 @@ index f64d348a969e..dcf05e00e505 100644
}
static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
+@@ -1583,7 +1599,7 @@ void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port,
+ * connected ports are usable, and avoids exposing to the users objects they
+ * can't really use.
+ */
+-bool intel_tc_port_connected_locked(struct intel_encoder *encoder)
++bool intel_tc_port_connected(struct intel_encoder *encoder)
+ {
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+@@ -1598,19 +1614,6 @@ bool intel_tc_port_connected_locked(struct intel_encoder *encoder)
+ return tc_phy_hpd_live_status(tc) & mask;
+ }
+
+-bool intel_tc_port_connected(struct intel_encoder *encoder)
+-{
+- struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+- struct intel_tc_port *tc = to_tc_port(dig_port);
+- bool is_connected;
+-
+- mutex_lock(&tc->lock);
+- is_connected = intel_tc_port_connected_locked(encoder);
+- mutex_unlock(&tc->lock);
+-
+- return is_connected;
+-}
+-
+ static bool __intel_tc_port_link_needs_reset(struct intel_tc_port *tc)
+ {
+ bool ret;
+diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
+index 80a61e52850e..26c4265368c1 100644
+--- a/drivers/gpu/drm/i915/display/intel_tc.h
++++ b/drivers/gpu/drm/i915/display/intel_tc.h
+@@ -15,9 +15,9 @@ struct intel_encoder;
+ bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port);
+ bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port);
+ bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port);
++bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port);
+
+ bool intel_tc_port_connected(struct intel_encoder *encoder);
+-bool intel_tc_port_connected_locked(struct intel_encoder *encoder);
+
+ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
+ int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
-index 2ee4f0d95851..9a217805d2f6 100644
+index 2ee4f0d95851..a96bcfcf90a3 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
-@@ -1327,7 +1327,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
+@@ -40,6 +40,7 @@
+ #include "intel_crtc.h"
+ #include "intel_de.h"
+ #include "intel_display_irq.h"
++#include "intel_display_driver.h"
+ #include "intel_display_types.h"
+ #include "intel_dpll.h"
+ #include "intel_hotplug.h"
+@@ -1327,7 +1328,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
* the active portion. Hence following this formula seems
* more trouble that it's worth.
*
@@ -57905,7 +59047,7 @@ index 2ee4f0d95851..9a217805d2f6 100644
* num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
* den = tv_mode->clock;
* } else {
-@@ -1417,9 +1417,6 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,
+@@ -1417,9 +1418,6 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,
static void set_color_conversion(struct drm_i915_private *dev_priv,
const struct color_conversion *color_conversion)
{
@@ -57915,7 +59057,7 @@ index 2ee4f0d95851..9a217805d2f6 100644
intel_de_write(dev_priv, TV_CSC_Y,
(color_conversion->ry << 16) | color_conversion->gy);
intel_de_write(dev_priv, TV_CSC_Y2,
-@@ -1454,9 +1451,6 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
+@@ -1454,9 +1452,6 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
int xpos, ypos;
unsigned int xsize, ysize;
@@ -57925,6 +59067,24 @@ index 2ee4f0d95851..9a217805d2f6 100644
tv_ctl = intel_de_read(dev_priv, TV_CTL);
tv_ctl &= TV_CTL_SAVE;
+@@ -1729,6 +1724,9 @@ intel_tv_detect(struct drm_connector *connector,
+ if (!intel_display_device_enabled(i915))
+ return connector_status_disconnected;
+
++ if (!intel_display_driver_check_access(i915))
++ return connector->status;
++
+ if (force) {
+ struct drm_atomic_state *state;
+
+@@ -1996,6 +1994,7 @@ intel_tv_init(struct drm_i915_private *dev_priv)
+ * More recent chipsets favour HDMI rather than integrated S-Video.
+ */
+ intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
++ intel_connector->base.polled = intel_connector->polled;
+
+ drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs,
+ DRM_MODE_CONNECTOR_SVIDEO);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 2cec2abf9746..fe256bf7b485 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -61052,7 +62212,7 @@ index e9b79c2c37d8..db99c2ef66db 100644
+ i915_gpu_error_debugfs_register(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
-index 802de2c6decb..c7d7c3b7ecc6 100644
+index 802de2c6decb..a951050f6a75 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -231,16 +231,10 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
@@ -61092,7 +62252,28 @@ index 802de2c6decb..c7d7c3b7ecc6 100644
}
static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
-@@ -1037,7 +1035,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
+@@ -1005,8 +1003,10 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
+ intel_runtime_pm_disable(&i915->runtime_pm);
+ intel_power_domains_disable(i915);
+
++ intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true);
+ if (HAS_DISPLAY(i915)) {
+ drm_kms_helper_poll_disable(&i915->drm);
++ intel_display_driver_disable_user_access(i915);
+
+ drm_atomic_helper_shutdown(&i915->drm);
+ }
+@@ -1016,6 +1016,9 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
+ intel_runtime_pm_disable_interrupts(i915);
+ intel_hpd_cancel_work(i915);
+
++ if (HAS_DISPLAY(i915))
++ intel_display_driver_suspend_access(i915);
++
+ intel_suspend_encoders(i915);
+ intel_shutdown_encoders(i915);
+
+@@ -1037,7 +1040,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915)
intel_power_domains_driver_remove(i915);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -61101,6 +62282,62 @@ index 802de2c6decb..c7d7c3b7ecc6 100644
}
static bool suspend_to_idle(struct drm_i915_private *dev_priv)
+@@ -1082,8 +1085,11 @@ static int i915_drm_suspend(struct drm_device *dev)
+ /* We do a lot of poking in a lot of registers, make sure they work
+ * properly. */
+ intel_power_domains_disable(dev_priv);
+- if (HAS_DISPLAY(dev_priv))
++ intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
++ if (HAS_DISPLAY(dev_priv)) {
+ drm_kms_helper_poll_disable(dev);
++ intel_display_driver_disable_user_access(dev_priv);
++ }
+
+ pci_save_state(pdev);
+
+@@ -1094,6 +1100,9 @@ static int i915_drm_suspend(struct drm_device *dev)
+ intel_runtime_pm_disable_interrupts(dev_priv);
+ intel_hpd_cancel_work(dev_priv);
+
++ if (HAS_DISPLAY(dev_priv))
++ intel_display_driver_suspend_access(dev_priv);
++
+ intel_suspend_encoders(dev_priv);
+
+ /* Must be called before GGTT is suspended. */
+@@ -1105,8 +1114,6 @@ static int i915_drm_suspend(struct drm_device *dev)
+ opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
+ intel_opregion_suspend(dev_priv, opregion_target_state);
+
+- intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
+-
+ dev_priv->suspend_count++;
+
+ intel_dmc_suspend(dev_priv);
+@@ -1245,15 +1252,21 @@ static int i915_drm_resume(struct drm_device *dev)
+ intel_display_driver_init_hw(dev_priv);
+
+ intel_clock_gating_init(dev_priv);
++
++ if (HAS_DISPLAY(dev_priv))
++ intel_display_driver_resume_access(dev_priv);
++
+ intel_hpd_init(dev_priv);
+
+ /* MST sideband requires HPD interrupts enabled */
+ intel_dp_mst_resume(dev_priv);
+ intel_display_driver_resume(dev_priv);
+
+- intel_hpd_poll_disable(dev_priv);
+- if (HAS_DISPLAY(dev_priv))
++ if (HAS_DISPLAY(dev_priv)) {
++ intel_display_driver_enable_user_access(dev_priv);
+ drm_kms_helper_poll_enable(dev);
++ }
++ intel_hpd_poll_disable(dev_priv);
+
+ intel_opregion_resume(dev_priv);
+
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
index 2a44b3876cb5..fa6852713bee 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
@@ -194482,6 +195719,174 @@ index 748a3c40966e..aa312441604f 100644
if (hda_format)
*hda_format = (unsigned short)format_val;
+diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
+index a889cccdd607..e8819e8a9876 100644
+--- a/sound/pci/hda/patch_conexant.c
++++ b/sound/pci/hda/patch_conexant.c
+@@ -21,6 +21,12 @@
+ #include "hda_jack.h"
+ #include "hda_generic.h"
+
++enum {
++ CX_HEADSET_NOPRESENT = 0,
++ CX_HEADSET_PARTPRESENT,
++ CX_HEADSET_ALLPRESENT,
++};
++
+ struct conexant_spec {
+ struct hda_gen_spec gen;
+
+@@ -42,7 +48,8 @@ struct conexant_spec {
+ unsigned int gpio_led;
+ unsigned int gpio_mute_led_mask;
+ unsigned int gpio_mic_led_mask;
+-
++ unsigned int headset_present_flag;
++ bool is_cx8070_sn6140;
+ };
+
+
+@@ -164,6 +171,27 @@ static void cxt_init_gpio_led(struct hda_codec *codec)
+ }
+ }
+
++static void cx_fixup_headset_recog(struct hda_codec *codec)
++{
++ unsigned int mic_persent;
++
++ /* fix some headset type recognize fail issue, such as EDIFIER headset */
++ /* set micbiasd output current comparator threshold from 66% to 55%. */
++ snd_hda_codec_write(codec, 0x1c, 0, 0x320, 0x010);
++ /* set OFF voltage for DFET from -1.2V to -0.8V, set headset micbias registor
++ * value adjustment trim from 2.2K ohms to 2.0K ohms.
++ */
++ snd_hda_codec_write(codec, 0x1c, 0, 0x3b0, 0xe10);
++ /* fix reboot headset type recognize fail issue */
++ mic_persent = snd_hda_codec_read(codec, 0x19, 0, AC_VERB_GET_PIN_SENSE, 0x0);
++ if (mic_persent & AC_PINSENSE_PRESENCE)
++ /* enable headset mic VREF */
++ snd_hda_codec_write(codec, 0x19, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x24);
++ else
++ /* disable headset mic VREF */
++ snd_hda_codec_write(codec, 0x19, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x20);
++}
++
+ static int cx_auto_init(struct hda_codec *codec)
+ {
+ struct conexant_spec *spec = codec->spec;
+@@ -174,6 +202,9 @@ static int cx_auto_init(struct hda_codec *codec)
+ cxt_init_gpio_led(codec);
+ snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
+
++ if (spec->is_cx8070_sn6140)
++ cx_fixup_headset_recog(codec);
++
+ return 0;
+ }
+
+@@ -192,6 +223,77 @@ static void cx_auto_free(struct hda_codec *codec)
+ snd_hda_gen_free(codec);
+ }
+
++static void cx_process_headset_plugin(struct hda_codec *codec)
++{
++ unsigned int val;
++ unsigned int count = 0;
++
++ /* Wait headset detect done. */
++ do {
++ val = snd_hda_codec_read(codec, 0x1c, 0, 0xca0, 0x0);
++ if (val & 0x080) {
++ codec_dbg(codec, "headset type detect done!\n");
++ break;
++ }
++ msleep(20);
++ count++;
++ } while (count < 3);
++ val = snd_hda_codec_read(codec, 0x1c, 0, 0xcb0, 0x0);
++ if (val & 0x800) {
++ codec_dbg(codec, "headset plugin, type is CTIA\n");
++ snd_hda_codec_write(codec, 0x19, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x24);
++ } else if (val & 0x400) {
++ codec_dbg(codec, "headset plugin, type is OMTP\n");
++ snd_hda_codec_write(codec, 0x19, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x24);
++ } else {
++ codec_dbg(codec, "headphone plugin\n");
++ }
++}
++
++static void cx_update_headset_mic_vref(struct hda_codec *codec, unsigned int res)
++{
++ unsigned int phone_present, mic_persent, phone_tag, mic_tag;
++ struct conexant_spec *spec = codec->spec;
++
++ /* In cx8070 and sn6140, the node 16 can only be config to headphone or disabled,
++ * the node 19 can only be config to microphone or disabled.
++ * Check hp&mic tag to process headset pulgin&plugout.
++ */
++ phone_tag = snd_hda_codec_read(codec, 0x16, 0, AC_VERB_GET_UNSOLICITED_RESPONSE, 0x0);
++ mic_tag = snd_hda_codec_read(codec, 0x19, 0, AC_VERB_GET_UNSOLICITED_RESPONSE, 0x0);
++ if ((phone_tag & (res >> AC_UNSOL_RES_TAG_SHIFT)) ||
++ (mic_tag & (res >> AC_UNSOL_RES_TAG_SHIFT))) {
++ phone_present = snd_hda_codec_read(codec, 0x16, 0, AC_VERB_GET_PIN_SENSE, 0x0);
++ if (!(phone_present & AC_PINSENSE_PRESENCE)) {/* headphone plugout */
++ spec->headset_present_flag = CX_HEADSET_NOPRESENT;
++ snd_hda_codec_write(codec, 0x19, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x20);
++ return;
++ }
++ if (spec->headset_present_flag == CX_HEADSET_NOPRESENT) {
++ spec->headset_present_flag = CX_HEADSET_PARTPRESENT;
++ } else if (spec->headset_present_flag == CX_HEADSET_PARTPRESENT) {
++ mic_persent = snd_hda_codec_read(codec, 0x19, 0,
++ AC_VERB_GET_PIN_SENSE, 0x0);
++ /* headset is present */
++ if ((phone_present & AC_PINSENSE_PRESENCE) &&
++ (mic_persent & AC_PINSENSE_PRESENCE)) {
++ cx_process_headset_plugin(codec);
++ spec->headset_present_flag = CX_HEADSET_ALLPRESENT;
++ }
++ }
++ }
++}
++
++static void cx_jack_unsol_event(struct hda_codec *codec, unsigned int res)
++{
++ struct conexant_spec *spec = codec->spec;
++
++ if (spec->is_cx8070_sn6140)
++ cx_update_headset_mic_vref(codec, res);
++
++ snd_hda_jack_unsol_event(codec, res);
++}
++
+ #ifdef CONFIG_PM
+ static int cx_auto_suspend(struct hda_codec *codec)
+ {
+@@ -205,7 +307,7 @@ static const struct hda_codec_ops cx_auto_patch_ops = {
+ .build_pcms = snd_hda_gen_build_pcms,
+ .init = cx_auto_init,
+ .free = cx_auto_free,
+- .unsol_event = snd_hda_jack_unsol_event,
++ .unsol_event = cx_jack_unsol_event,
+ #ifdef CONFIG_PM
+ .suspend = cx_auto_suspend,
+ .check_power_status = snd_hda_gen_check_power_status,
+@@ -1042,6 +1144,15 @@ static int patch_conexant_auto(struct hda_codec *codec)
+ codec->spec = spec;
+ codec->patch_ops = cx_auto_patch_ops;
+
++ /* init cx8070/sn6140 flag and reset headset_present_flag */
++ switch (codec->core.vendor_id) {
++ case 0x14f11f86:
++ case 0x14f11f87:
++ spec->is_cx8070_sn6140 = true;
++ spec->headset_present_flag = CX_HEADSET_NOPRESENT;
++ break;
++ }
++
+ cx_auto_parse_eapd(codec);
+ spec->gen.own_eapd_ctl = 1;
+
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 78cee53fee02..200779296a1b 100644
--- a/sound/pci/hda/patch_hdmi.c
@@ -194514,7 +195919,7 @@ index 78cee53fee02..200779296a1b 100644
if (err < 0)
return err;
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
-index 70b17b08d4ff..1dcfba27e075 100644
+index 70b17b08d4ff..b68c94757051 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -6956,6 +6956,11 @@ static void cs35l41_fixup_i2c_two(struct hda_codec *cdc, const struct hda_fixup
@@ -194599,7 +196004,15 @@ index 70b17b08d4ff..1dcfba27e075 100644
SND_PCI_QUIRK(0x1028, 0x0cbd, "Dell Oasis 13 CS MTL-U", ALC289_FIXUP_DELL_CS35L41_SPI_2),
SND_PCI_QUIRK(0x1028, 0x0cbe, "Dell Oasis 13 2-IN-1 MTL-U", ALC289_FIXUP_DELL_CS35L41_SPI_2),
SND_PCI_QUIRK(0x1028, 0x0cbf, "Dell Oasis 13 Low Weight MTU-L", ALC289_FIXUP_DELL_CS35L41_SPI_2),
-@@ -10221,6 +10247,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
+@@ -9816,6 +9842,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
+ SND_PCI_QUIRK(0x103c, 0x8735, "HP ProBook 435 G7", ALC236_FIXUP_HP_MUTE_LED_MICMUTE_VREF),
+ SND_PCI_QUIRK(0x103c, 0x8736, "HP", ALC285_FIXUP_HP_GPIO_AMP_INIT),
+ SND_PCI_QUIRK(0x103c, 0x8760, "HP", ALC285_FIXUP_HP_MUTE_LED),
++ SND_PCI_QUIRK(0x103c, 0x876e, "HP ENVY x360 Convertible 13-ay0xxx", ALC245_FIXUP_HP_X360_MUTE_LEDS),
+ SND_PCI_QUIRK(0x103c, 0x877a, "HP", ALC285_FIXUP_HP_MUTE_LED),
+ SND_PCI_QUIRK(0x103c, 0x877d, "HP", ALC236_FIXUP_HP_MUTE_LED),
+ SND_PCI_QUIRK(0x103c, 0x8780, "HP ZBook Fury 17 G7 Mobile Workstation",
+@@ -10221,6 +10248,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
SND_PCI_QUIRK(0x17aa, 0x3853, "Lenovo Yoga 7 15ITL5", ALC287_FIXUP_YOGA7_14ITL_SPEAKERS),
SND_PCI_QUIRK(0x17aa, 0x3855, "Legion 7 16ITHG6", ALC287_FIXUP_LEGION_16ITHG6),
SND_PCI_QUIRK(0x17aa, 0x3869, "Lenovo Yoga7 14IAL7", ALC287_FIXUP_YOGA9_14IAP7_BASS_SPK_PIN),
@@ -194607,7 +196020,7 @@ index 70b17b08d4ff..1dcfba27e075 100644
SND_PCI_QUIRK(0x17aa, 0x387d, "Yoga S780-16 pro Quad AAC", ALC287_FIXUP_TAS2781_I2C),
SND_PCI_QUIRK(0x17aa, 0x387e, "Yoga S780-16 pro Quad YC", ALC287_FIXUP_TAS2781_I2C),
SND_PCI_QUIRK(0x17aa, 0x3881, "YB9 dual power mode2 YC", ALC287_FIXUP_TAS2781_I2C),
-@@ -10229,6 +10256,10 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
+@@ -10229,6 +10257,10 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
SND_PCI_QUIRK(0x17aa, 0x3886, "Y780 VECO DUAL", ALC287_FIXUP_TAS2781_I2C),
SND_PCI_QUIRK(0x17aa, 0x38a7, "Y780P AMD YG dual", ALC287_FIXUP_TAS2781_I2C),
SND_PCI_QUIRK(0x17aa, 0x38a8, "Y780P AMD VECO dual", ALC287_FIXUP_TAS2781_I2C),
@@ -201843,6 +203256,44 @@ index 943bf8b80e01..bbf796a5f7ba 100644
sof_sdw_hdmi.o
obj-$(CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH) += snd-soc-sof_rt5682.o
obj-$(CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH) += snd-soc-sof_cs42l42.o
+diff --git a/sound/soc/intel/boards/bxt_da7219_max98357a.c b/sound/soc/intel/boards/bxt_da7219_max98357a.c
+index 816fad8c1ff0..540f7a29310a 100644
+--- a/sound/soc/intel/boards/bxt_da7219_max98357a.c
++++ b/sound/soc/intel/boards/bxt_da7219_max98357a.c
+@@ -797,6 +797,9 @@ static int broxton_audio_probe(struct platform_device *pdev)
+ broxton_audio_card.name = "glkda7219max";
+ /* Fixup the SSP entries for geminilake */
+ for (i = 0; i < ARRAY_SIZE(broxton_dais); i++) {
++ if (!broxton_dais[i].codecs->dai_name)
++ continue;
++
+ /* MAXIM_CODEC is connected to SSP1. */
+ if (!strcmp(broxton_dais[i].codecs->dai_name,
+ BXT_MAXIM_CODEC_DAI)) {
+@@ -822,6 +825,9 @@ static int broxton_audio_probe(struct platform_device *pdev)
+ broxton_audio_card.name = "cmlda7219max";
+
+ for (i = 0; i < ARRAY_SIZE(broxton_dais); i++) {
++ if (!broxton_dais[i].codecs->dai_name)
++ continue;
++
+ /* MAXIM_CODEC is connected to SSP1. */
+ if (!strcmp(broxton_dais[i].codecs->dai_name,
+ BXT_MAXIM_CODEC_DAI)) {
+diff --git a/sound/soc/intel/boards/bxt_rt298.c b/sound/soc/intel/boards/bxt_rt298.c
+index 4631106f2a28..c0eb65c14aa9 100644
+--- a/sound/soc/intel/boards/bxt_rt298.c
++++ b/sound/soc/intel/boards/bxt_rt298.c
+@@ -604,7 +604,8 @@ static int broxton_audio_probe(struct platform_device *pdev)
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(broxton_rt298_dais); i++) {
+- if (!strncmp(card->dai_link[i].codecs->name, "i2c-INT343A:00",
++ if (card->dai_link[i].codecs->name &&
++ !strncmp(card->dai_link[i].codecs->name, "i2c-INT343A:00",
+ I2C_NAME_SIZE)) {
+ if (!strncmp(card->name, "broxton-rt298",
+ PLATFORM_NAME_SIZE)) {
diff --git a/sound/soc/intel/boards/bytcht_es8316.c b/sound/soc/intel/boards/bytcht_es8316.c
index 8a0b0e864fbb..1564a88a885e 100644
--- a/sound/soc/intel/boards/bytcht_es8316.c
diff --git a/patches/external/bbb.io/0001-Add-BeagleBoard.org-Device-Tree-Changes.patch b/patches/external/bbb.io/0001-Add-BeagleBoard.org-Device-Tree-Changes.patch
index a7eb251b..896e1bc1 100644
--- a/patches/external/bbb.io/0001-Add-BeagleBoard.org-Device-Tree-Changes.patch
+++ b/patches/external/bbb.io/0001-Add-BeagleBoard.org-Device-Tree-Changes.patch
@@ -1,16 +1,23 @@
-From 0e9d8f0447a6893829b88b07d1b33c4471c06b4a Mon Sep 17 00:00:00 2001
+From ad80862996dfc63be9f96ae06ca894871fc69527 Mon Sep 17 00:00:00 2001
From: Robert Nelson <robertcnelson@gmail.com>
-Date: Mon, 8 Jan 2024 20:57:36 -0600
+Date: Sun, 14 Jan 2024 20:40:48 -0600
Subject: [PATCH] Add BeagleBoard.org Device Tree Changes
https://openbeagle.org/beagleboard/BeagleBoard-DeviceTrees/-/tree/v6.7.x
-https://openbeagle.org/beagleboard/BeagleBoard-DeviceTrees/-/commit/2baa426865df1d6f3e90bb91fa488bd168f45b75
+https://openbeagle.org/beagleboard/BeagleBoard-DeviceTrees/-/commit/fb6f54ec2b36cac20da460d0e51164fa428625d6
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
---
- arch/arm/boot/dts/ti/omap/Makefile | 6 +
- .../dts/ti/omap/am335x-bbb-bone-buses.dtsi | 85 ++++++++
- .../boot/dts/ti/omap/am335x-bone-common.dtsi | 25 ++-
+ .../boot/dts/ti/omap/AM335X-PRU-UIO-00A0.dtso | 28 +++
+ .../boot/dts/ti/omap/AM57XX-PRU-UIO-00A0.dtso | 55 +++++
+ arch/arm/boot/dts/ti/omap/BB-ADC-00A0.dtso | 112 ++++++++++
+ .../dts/ti/omap/BB-BONE-eMMC1-01-00A0.dtso | 61 ++++++
+ .../boot/dts/ti/omap/BBORG_COMMS-00A2.dtso | 39 ++++
+ arch/arm/boot/dts/ti/omap/BBORG_FAN-A000.dtso | 16 ++
+ arch/arm/boot/dts/ti/omap/BONE-ADC.dtso | 28 +++
+ arch/arm/boot/dts/ti/omap/Makefile | 13 ++
+ .../dts/ti/omap/am335x-bbb-bone-buses.dtsi | 69 +++++++
+ .../boot/dts/ti/omap/am335x-bone-common.dtsi | 27 ++-
arch/arm/boot/dts/ti/omap/am335x-bone.dts | 5 +
.../dts/ti/omap/am335x-boneblack-uboot.dts | 194 ++++++++++++++++++
.../dts/ti/omap/am335x-boneblack-wireless.dts | 5 +
@@ -18,17 +25,22 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
arch/arm/boot/dts/ti/omap/am335x-boneblue.dts | 2 +
.../dts/ti/omap/am335x-bonegreen-common.dtsi | 1 +
.../dts/ti/omap/am335x-bonegreen-wireless.dts | 5 +
- .../arm/boot/dts/ti/omap/am335x-bonegreen.dts | 5 +
+ .../arm/boot/dts/ti/omap/am335x-bonegreen.dts | 153 ++++++++++++++
.../dts/ti/omap/am335x-osd3358-sm-red.dts | 5 +
.../dts/ti/omap/am335x-osd335x-common.dtsi | 1 +
.../boot/dts/ti/omap/am335x-pocketbeagle.dts | 2 +
.../am335x-sancloud-bbe-extended-wifi.dts | 5 +
.../dts/ti/omap/am335x-sancloud-bbe-lite.dts | 6 +
.../boot/dts/ti/omap/am335x-sancloud-bbe.dts | 5 +
+ arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi | 2 +-
+ arch/arm/boot/dts/ti/omap/am33xx.dtsi | 5 +
.../boot/dts/ti/omap/am5729-beagleboneai.dts | 11 +-
.../dts/ti/omap/am57xx-beagle-x15-revb1.dts | 5 +
.../dts/ti/omap/am57xx-beagle-x15-revc.dts | 5 +
.../boot/dts/ti/omap/am57xx-beagle-x15.dts | 5 +
+ arch/arm/boot/dts/ti/omap/dra7.dtsi | 6 +
+ arch/arm/boot/dts/ti/omap/omap34xx.dtsi | 6 +
+ arch/arm/boot/dts/ti/omap/omap4.dtsi | 6 +
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 96 ++++++++-
.../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 23 ++-
.../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 16 ++
@@ -41,12 +53,400 @@ Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 102 +++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 9 +-
.../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 22 +-
- 33 files changed, 1067 insertions(+), 35 deletions(-)
+ 45 files changed, 1571 insertions(+), 36 deletions(-)
+ create mode 100644 arch/arm/boot/dts/ti/omap/AM335X-PRU-UIO-00A0.dtso
+ create mode 100644 arch/arm/boot/dts/ti/omap/AM57XX-PRU-UIO-00A0.dtso
+ create mode 100644 arch/arm/boot/dts/ti/omap/BB-ADC-00A0.dtso
+ create mode 100644 arch/arm/boot/dts/ti/omap/BB-BONE-eMMC1-01-00A0.dtso
+ create mode 100644 arch/arm/boot/dts/ti/omap/BBORG_COMMS-00A2.dtso
+ create mode 100644 arch/arm/boot/dts/ti/omap/BBORG_FAN-A000.dtso
+ create mode 100644 arch/arm/boot/dts/ti/omap/BONE-ADC.dtso
create mode 100644 arch/arm/boot/dts/ti/omap/am335x-bbb-bone-buses.dtsi
create mode 100644 arch/arm/boot/dts/ti/omap/am335x-boneblack-uboot.dts
+diff --git a/arch/arm/boot/dts/ti/omap/AM335X-PRU-UIO-00A0.dtso b/arch/arm/boot/dts/ti/omap/AM335X-PRU-UIO-00A0.dtso
+new file mode 100644
+index 000000000000..f3016efca2d7
+--- /dev/null
++++ b/arch/arm/boot/dts/ti/omap/AM335X-PRU-UIO-00A0.dtso
+@@ -0,0 +1,28 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
++ */
++
++/dts-v1/;
++/plugin/;
++
++/*
++ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
++ */
++&{/chosen} {
++ overlays {
++ AM335X-PRU-UIO-00A0.kernel = __TIMESTAMP__;
++ };
++};
++
++
++&pruss_tm {
++ status = "okay";
++};
++
++&pruss {
++ compatible = "ti,pruss-v2";
++ ti,pintc-offset = <0x20000>;
++ interrupt-parent = <&intc>;
++ interrupts = <20 21 22 23 24 25 26 27>;
++};
+diff --git a/arch/arm/boot/dts/ti/omap/AM57XX-PRU-UIO-00A0.dtso b/arch/arm/boot/dts/ti/omap/AM57XX-PRU-UIO-00A0.dtso
+new file mode 100644
+index 000000000000..b3f2aaf9abc0
+--- /dev/null
++++ b/arch/arm/boot/dts/ti/omap/AM57XX-PRU-UIO-00A0.dtso
+@@ -0,0 +1,55 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
++ */
++
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++
++/*
++ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
++ */
++&{/chosen} {
++ overlays {
++ AM57XX-PRU-UIO-00A0.kernel = __TIMESTAMP__;
++ };
++};
++
++&pruss1_tm {
++ status = "okay";
++};
++
++&pruss1 {
++ compatible = "ti,pruss-v2";
++ ti,pintc-offset = <0x20000>;
++ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++ pruss-instance = "pruss1";
++};
++
++&pruss2_tm {
++ status = "okay";
++};
++
++&pruss2 {
++ compatible = "ti,pruss-v2";
++ ti,pintc-offset = <0x20000>;
++ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
++ pruss-instance = "pruss2";
++};
+diff --git a/arch/arm/boot/dts/ti/omap/BB-ADC-00A0.dtso b/arch/arm/boot/dts/ti/omap/BB-ADC-00A0.dtso
+new file mode 100644
+index 000000000000..914b7aa3df43
+--- /dev/null
++++ b/arch/arm/boot/dts/ti/omap/BB-ADC-00A0.dtso
+@@ -0,0 +1,112 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
++ */
++
++/dts-v1/;
++/plugin/;
++
++/*
++ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
++ */
++&{/chosen} {
++ overlays {
++ BB-ADC-00A0.kernel = __TIMESTAMP__;
++ };
++};
++
++&tscadc {
++ status = "okay";
++ adc {
++ // Configure one or more (up to 8) steps for the adc to execute:
++
++
++ // For each step, the channel to sample.
++ // range: 0 .. 7
++ ti,adc-channels = <0 1 2 3 4 5 6 7>;
++ //
++ // BeagleBone Black (and most other variants):
++ // ch 0 P9.39
++ // ch 1 P9.40
++ // ch 2 P9.37
++ // ch 3 P9.38
++ // ch 4 P9.33
++ // ch 5 P9.36
++ // ch 6 P9.35
++ // ch 7 measures 0.5 * VDD_3V3B with 2.4 kΩ source impedance
++ //
++ // PocketBeagle:
++ // ch 0 P1.19
++ // ch 1 P1.21
++ // ch 2 P1.23
++ // ch 3 P1.25
++ // ch 4 P1.27
++ // ch 5 P2.35 via 10k/10k voltage divider
++ // ch 6 P1.02 via 10k/10k voltage divider
++ // ch 7 P2.36 via pmic mux
++ //
++ // The divider used on PocketBeagle channels 5 and 6 makes the effective voltage V_eff and
++ // source impedance Z_eff seen by the adc on these channels depend on the voltage V_src and
++ // impedance Z_src of the source connected to the corresponding pin as follows:
++ //
++ // V_eff = V_src / (2 + Z_src / (10 kΩ))
++ // Z_eff = 5 kΩ * (1 + Z_src / (Z_src + 20 kΩ))
++ // ≈ 5 kΩ + Z_src / 4 for small values of Z_src (up to 2 kΩ or so)
++
++
++ // For each step, number of adc clock cycles to wait between setting up muxes and sampling.
++ // range: 0 .. 262143
++ // optional, default is 152 (XXX but why?!)
++ ti,chan-step-opendelay = <152 152 152 152 152 152 152 152>;
++ //`
++ // XXX is there any purpose to set this nonzero other than to fine-tune the sample rate?
++
++
++ // For each step, how many times it should sample to average.
++ // range: 1 .. 16, must be power of two (i.e. 1, 2, 4, 8, or 16)
++ // optional, default is 16
++ ti,chan-step-avg = <16 16 16 16 16 16 16 16>;
++ //
++ // If you're using periodic sampling (using the iio block device rather than sysfs) then
++ // you should consider setting this to 1 and if desired reduce the samplerate in userspace
++ // instead since averaging isn't a particularly good low-pass filter.
++ //
++ // If you're using sysfs to occasionally read a value, then the default value of 16 will
++ // still get you the most accurate readings.
++
++
++ // For each step, number of adc clock cycles to sample minus two.
++ // range: 0 .. 255 (resulting in sampling time of 2 .. 257 cycles)
++ // optional, default is 0
++ ti,chan-step-sampledelay = <0 0 0 0 0 0 0 0>;
++ //
++ // If this is set too low, accuracy will deteriorate when the thing you're measuring has a
++ // high source impedance. The maximum source impedance recommended (by erratum 1.0.32) is:
++ // (2 + sampledelay) * 2.873 kΩ - 0.2 kΩ
++ // which means that the default should be fine for source impedance up to 5.5 kΩ.
++ //
++ // (This seems to ensure the sampling time is at least 21 times the RC constant, based on
++ // the 5.5 pF nominal capacitance specified in the datasheet.)
++
++
++ // After sampling, conversion time is 13 adc clock cycles.
++ //
++ // The adc clock frequency is 3 MHz, therefore the total time per step in microseconds is:
++ // ( opendelay + avg * ( 2 + sampledelay + 13 ) ) / 3
++ //
++ // If all steps use the same timings then the sample rate will be:
++ // 3 MHz / ( opendelay + avg * ( 2 + sampledelay + 13 ) ) / number_of_steps
++ //
++ // The highest samplerate obtainable (avg=1, opendelay=0, sampledelay=0) is therefore:
++ // 200 kHz / number_of_steps
++ // = 25 kHz when using all 8 steps.
++ //
++ // Using avg=16 reduces that to:
++ // 12.5 kHz / number_of_steps
++ // = 1.5625 kHz when using all 8 steps.
++ //
++ // Using the default values (avg=16, opendelay=152, sampledelay=0) reduces that to:
++ // 7.653 kHz / number_of_steps
++ // = 0.9566 kHz when using all 8 steps.
++ };
++};
+diff --git a/arch/arm/boot/dts/ti/omap/BB-BONE-eMMC1-01-00A0.dtso b/arch/arm/boot/dts/ti/omap/BB-BONE-eMMC1-01-00A0.dtso
+new file mode 100644
+index 000000000000..edc70070f278
+--- /dev/null
++++ b/arch/arm/boot/dts/ti/omap/BB-BONE-eMMC1-01-00A0.dtso
+@@ -0,0 +1,61 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
++ */
++
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/am33xx.h>
++
++/*
++ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
++ */
++&{/chosen} {
++ overlays {
++ BB-BONE-eMMC1-01-00A0.kernel = __TIMESTAMP__;
++ };
++};
++
++/*
++ * Free up the pins used by the cape from the pinmux helpers.
++ */
++&ocp {
++ P8_21_pinmux { status = "disabled"; }; /* mmc1_clk */
++ P8_20_pinmux { status = "disabled"; }; /* mmc1_cmd */
++ P8_25_pinmux { status = "disabled"; }; /* mmc1_dat0 */
++ P8_24_pinmux { status = "disabled"; }; /* mmc1_dat1 */
++ P8_05_pinmux { status = "disabled"; }; /* mmc1_dat2 */
++ P8_06_pinmux { status = "disabled"; }; /* mmc1_dat3 */
++ P8_23_pinmux { status = "disabled"; }; /* mmc1_dat4 */
++ P8_22_pinmux { status = "disabled"; }; /* mmc1_dat5 */
++ P8_03_pinmux { status = "disabled"; }; /* mmc1_dat6 */
++ P8_04_pinmux { status = "disabled"; }; /* mmc1_dat7 */
++};
++
++&am33xx_pinmux {
++ emmc_pins: pinmux_emmc_pins {
++ pinctrl-single,pins = <
++ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
++ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
++ >;
++ };
++};
++
++&mmc2 {
++ vmmc-supply = <&vmmcsd_fixed>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_pins>;
++ bus-width = <8>;
++ status = "okay";
++ non-removable;
++};
+diff --git a/arch/arm/boot/dts/ti/omap/BBORG_COMMS-00A2.dtso b/arch/arm/boot/dts/ti/omap/BBORG_COMMS-00A2.dtso
+new file mode 100644
+index 000000000000..b724d9426568
+--- /dev/null
++++ b/arch/arm/boot/dts/ti/omap/BBORG_COMMS-00A2.dtso
+@@ -0,0 +1,39 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2012,2019 Texas Instruments Incorporated - https://www.ti.com/
++ * Copyright (C) 2015 Robert Nelson <robertcnelson@gmail.com>
++ * Copyright (C) 2015 Sebastian Jegerås
++ */
++
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/pinctrl/am33xx.h>
++#include <dt-bindings/gpio/gpio.h>
++
++/*
++ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
++ */
++&{/chosen} {
++ overlays {
++ BBORG_COMMS-00A2.kernel = __TIMESTAMP__;
++ };
++};
++
++/*
++ * Free up the pins used by the cape from the pinmux helpers.
++ */
++&ocp {
++ P9_24_pinmux { status = "disabled"; }; /* P9_24: uart1_txd.d_can1_rx */
++ P9_26_pinmux { status = "disabled"; }; /* P9_26: uart1_rxd.d_can1_tx */
++ P9_13_pinmux { status = "disabled"; }; /* P9_13: gpmc_wpn.uart4_txd_mux2 */
++ P9_11_pinmux { status = "disabled"; }; /* P9_11: gpmc_wait0.uart4_rxd_mux2 */
++};
++
++&bone_can_1 {
++ status = "okay";
++};
++
++&bone_uart_4 {
++ status = "okay";
++};
+diff --git a/arch/arm/boot/dts/ti/omap/BBORG_FAN-A000.dtso b/arch/arm/boot/dts/ti/omap/BBORG_FAN-A000.dtso
+new file mode 100644
+index 000000000000..fb2b4ac4e44b
+--- /dev/null
++++ b/arch/arm/boot/dts/ti/omap/BBORG_FAN-A000.dtso
+@@ -0,0 +1,16 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2020 Robert Nelson <robercnelson@gmail.com>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/*
++ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
++ */
++&{/chosen} {
++ overlays {
++ BBORG_FAN-A000.kernel = __TIMESTAMP__;
++ };
++};
+diff --git a/arch/arm/boot/dts/ti/omap/BONE-ADC.dtso b/arch/arm/boot/dts/ti/omap/BONE-ADC.dtso
+new file mode 100644
+index 000000000000..dafd8a26fbe0
+--- /dev/null
++++ b/arch/arm/boot/dts/ti/omap/BONE-ADC.dtso
+@@ -0,0 +1,28 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) 2020 Deepak Khatri <deepaklorkhatri7@gmail.com>
++ * See Cape Interface Spec page for more info on Bone Buses
++ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
++ *
++ * Virtual cape for Bone ADC
++ */
++
++/dts-v1/;
++/plugin/;
++
++/*
++ * Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/
++ */
++&{/chosen} {
++ overlays {
++ BONE-ADC.kernel = __TIMESTAMP__;
++ };
++};
++
++/*
++ * See these files for the phandles (&bone_*) and other bone bus nodes
++ * am335x-bbb-bone-buses.dtsi
++ */
++&bone_adc {
++ status = "okay";
++};
diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile
-index d2b590004fed..8cb2512c578e 100644
+index d2b590004fed..31aec0fcb90f 100644
--- a/arch/arm/boot/dts/ti/omap/Makefile
+++ b/arch/arm/boot/dts/ti/omap/Makefile
@@ -1,4 +1,9 @@
@@ -59,26 +459,34 @@ index d2b590004fed..8cb2512c578e 100644
dtb-$(CONFIG_ARCH_OMAP2) += \
omap2420-h4.dtb \
omap2420-n800.dtb \
-@@ -87,6 +92,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
+@@ -87,6 +92,14 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-base0033.dtb \
am335x-bone.dtb \
am335x-boneblack.dtb \
+ am335x-boneblack-uboot.dtb \
++ BONE-ADC.dtbo \
++ BBORG_FAN-A000.dtbo \
++ BBORG_COMMS-00A2.dtbo \
++ BB-BONE-eMMC1-01-00A0.dtbo \
++ BB-ADC-00A0.dtbo \
++ AM57XX-PRU-UIO-00A0.dtbo \
++ AM335X-PRU-UIO-00A0.dtbo \
am335x-boneblack-wireless.dtb \
am335x-boneblue.dtb \
am335x-bonegreen.dtb \
diff --git a/arch/arm/boot/dts/ti/omap/am335x-bbb-bone-buses.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bbb-bone-buses.dtsi
new file mode 100644
-index 000000000000..5fc09cbd8840
+index 000000000000..01fa6b98a655
--- /dev/null
+++ b/arch/arm/boot/dts/ti/omap/am335x-bbb-bone-buses.dtsi
-@@ -0,0 +1,85 @@
+@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Deepak Khatri <deepaklorkhatri7@gmail.com>
+ * Copyright (C) 2021 Robert Nelson <robertcnelson@gmail.com>
+ * See Cape Interface Spec page for more info on Bone Buses
+ * https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec
++ * https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html
+ */
+
+#include <dt-bindings/gpio/gpio.h>
@@ -96,60 +504,17 @@ index 000000000000..5fc09cbd8840
+
+// For compatible bone pinmuxing
+bone_pinmux: &am33xx_pinmux {
-+ emmc_pins: emmc-pins {
++ bborg_comms_can_pins: pinmux_comms_can_pins {
+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
++ 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* P9_24: uart1_txd.d_can1_rx */
++ 0x180 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* P9_26: uart1_rxd.d_can1_tx */
+ >;
+ };
+
-+ nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins {
++ bborg_comms_rs485_pins: pinmux_comms_rs485_pins {
+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ >;
-+ };
-+
-+ nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins {
-+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-+ >;
-+ };
-+
-+ mcasp0_pins: mcasp0_pins {
-+ pinctrl-single,pins = <
-+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
-+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
-+ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-+ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
++ 0x074 (PIN_OUTPUT | MUX_MODE6) /* P9_13: gpmc_wpn.uart4_txd_mux2 */
++ 0x070 (PIN_INPUT | MUX_MODE6) /* P9_11: gpmc_wait0.uart4_rxd_mux2 */
+ >;
+ };
+};
@@ -158,11 +523,47 @@ index 000000000000..5fc09cbd8840
+bone_adc: &tscadc {
+
+};
++
++// CAN
++// https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#can
++bone_can_1: &dcan1 {
++ symlink = "bone/can/1";
++ status = "disabled";
++ pinctrl-names = "default";
++// pinctrl-0 = <
++// &P9_26_can_pin /* tx */
++// &P9_24_can_pin /* rx */
++// >;
++ pinctrl-0 = <&bborg_comms_can_pins>;
++};
++
++// UART
++// https://docs.beagleboard.io/latest/boards/capes/cape-interface-spec.html#uart
++bone_uart_4: &uart4 {
++ symlink = "bone/uart/4";
++ status = "disabled";
++ pinctrl-names = "default";
++ pinctrl-0 = <&bborg_comms_rs485_pins>;
++ //rs485-rts-delay = <0 0>;
++ //rts-gpio = <&gpio3 19 1>; /* GPIO_ACTIVE_HIGH>; */
++ //rs485-rts-active-high;
++ //linux,rs485-enabled-at-boot-time;
++};
+\ No newline at end of file
diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi
-index 96451c8a815c..509bd51b3e30 100644
+index 96451c8a815c..cc515a8cdb5d 100644
--- a/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi
-@@ -26,14 +26,14 @@ leds {
+@@ -3,6 +3,8 @@
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
++#include "am335x-bbb-bone-buses.dtsi"
++
+ / {
+ cpus {
+ cpu@0 {
+@@ -26,14 +28,14 @@ leds {
compatible = "gpio-leds";
led2 {
@@ -179,7 +580,7 @@ index 96451c8a815c..509bd51b3e30 100644
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
-@@ -63,9 +63,6 @@ vmmcsd_fixed: fixedregulator0 {
+@@ -63,9 +65,6 @@ vmmcsd_fixed: fixedregulator0 {
};
&am33xx_pinmux {
@@ -189,7 +590,7 @@ index 96451c8a815c..509bd51b3e30 100644
user_leds_s0: user-leds-s0-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
-@@ -96,12 +93,6 @@ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+@@ -96,12 +95,6 @@ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
>;
};
@@ -202,7 +603,7 @@ index 96451c8a815c..509bd51b3e30 100644
cpsw_default: cpsw-default-pins {
pinctrl-single,pins = <
/* Slave 1 */
-@@ -193,6 +184,7 @@ &uart0 {
+@@ -193,6 +186,7 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
status = "okay";
@@ -210,7 +611,7 @@ index 96451c8a815c..509bd51b3e30 100644
};
&usb0 {
-@@ -211,6 +203,7 @@ &i2c0 {
+@@ -211,6 +205,7 @@ &i2c0 {
status = "okay";
clock-frequency = <400000>;
@@ -218,7 +619,7 @@ index 96451c8a815c..509bd51b3e30 100644
tps: tps@24 {
reg = <0x24>;
-@@ -235,6 +228,7 @@ &i2c2 {
+@@ -235,6 +230,7 @@ &i2c2 {
status = "okay";
clock-frequency = <100000>;
@@ -226,7 +627,7 @@ index 96451c8a815c..509bd51b3e30 100644
cape_eeprom0: cape_eeprom0@54 {
compatible = "atmel,24c256";
-@@ -418,3 +412,12 @@ &pruss_tm {
+@@ -418,3 +414,12 @@ &pruss_tm {
&wkup_m3_ipc {
firmware-name = "am335x-bone-scale-data.bin";
};
@@ -538,10 +939,10 @@ index a4f5b5262645..860eeb03b70e 100644
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
diff --git a/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts b/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts
-index 18cc0f49e999..62ca9c8764bd 100644
+index 18cc0f49e999..769733f0b822 100644
--- a/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts
+++ b/arch/arm/boot/dts/ti/omap/am335x-bonegreen.dts
-@@ -11,4 +11,9 @@
+@@ -11,4 +11,157 @@
/ {
model = "TI AM335x BeagleBone Green";
compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
@@ -550,6 +951,154 @@ index 18cc0f49e999..62ca9c8764bd 100644
+ base_dtb = "am335x-bonegreen.dts";
+ base_dtb_timestamp = __TIMESTAMP__;
+ };
++};
++
++&gpio0 {
++ gpio-line-names =
++ "[mdio_data]",
++ "[mdio_clk]",
++ "P9_22 [spi0_sclk]",
++ "P9_21 [spi0_d0]",
++ "P9_18 [spi0_d1]",
++ "P9_17 [spi0_cs0]",
++ "[mmc0_cd]",
++ "P9_42A [ecappwm0]",
++ "P8_35 [lcd d12]",
++ "P8_33 [lcd d13]",
++ "P8_31 [lcd d14]",
++ "P8_32 [lcd d15]",
++ "P9_20 [i2c2_sda]",
++ "P9_19 [i2c2_scl]",
++ "P9_26 [uart1_rxd]",
++ "P9_24 [uart1_txd]",
++ "[rmii1_txd3]",
++ "[rmii1_txd2]",
++ "[usb0_drvvbus]",
++ "[hdmi cec]",
++ "P9_41B",
++ "[rmii1_txd1]",
++ "P8_19 [ehrpwm2a]",
++ "P8_13 [ehrpwm2b]",
++ "NC",
++ "NC",
++ "P8_14",
++ "P8_17",
++ "[rmii1_txd0]",
++ "[rmii1_refclk]",
++ "P9_11 [uart4_rxd]",
++ "P9_13 [uart4_txd]";
++};
++
++&gpio1 {
++ gpio-line-names =
++ "P8_25 [mmc1_dat0]",
++ "[mmc1_dat1]",
++ "P8_5 [mmc1_dat2]",
++ "P8_6 [mmc1_dat3]",
++ "P8_23 [mmc1_dat4]",
++ "P8_22 [mmc1_dat5]",
++ "P8_3 [mmc1_dat6]",
++ "P8_4 [mmc1_dat7]",
++ "NC",
++ "NC",
++ "NC",
++ "NC",
++ "P8_12",
++ "P8_11",
++ "P8_16",
++ "P8_15",
++ "P9_15A",
++ "P9_23",
++ "P9_14 [ehrpwm1a]",
++ "P9_16 [ehrpwm1b]",
++ "[emmc rst]",
++ "[usr0 led]",
++ "[usr1 led]",
++ "[usr2 led]",
++ "[usr3 led]",
++ "[hdmi irq]",
++ "[usb vbus oc]",
++ "[hdmi audio]",
++ "P9_12",
++ "P8_26",
++ "P8_21 [emmc]",
++ "P8_20 [emmc]";
++};
++
++&gpio2 {
++ gpio-line-names =
++ "P9_15B",
++ "P8_18",
++ "P8_7",
++ "P8_8",
++ "P8_10",
++ "P8_9",
++ "P8_45",
++ "P8_46",
++ "P8_43",
++ "P8_44",
++ "P8_41",
++ "P8_42",
++ "P8_39",
++ "P8_40",
++ "P8_37",
++ "P8_38",
++ "P8_36",
++ "P8_34",
++ "[rmii1_rxd3]",
++ "[rmii1_rxd2]",
++ "[rmii1_rxd1]",
++ "[rmii1_rxd0]",
++ "P8_27",
++ "P8_29",
++ "P8_28",
++ "P8_30",
++ "[mmc0_dat3]",
++ "[mmc0_dat2]",
++ "[mmc0_dat1]",
++ "[mmc0_dat0]",
++ "[mmc0_clk]",
++ "[mmc0_cmd]";
++};
++
++&gpio3 {
++ gpio-line-names =
++ "[mii col]",
++ "[mii crs]",
++ "[mii rx err]",
++ "[mii tx en]",
++ "[mii rx dv]",
++ "[i2c0 sda]",
++ "[i2c0 scl]",
++ "[jtag emu0]",
++ "[jtag emu1]",
++ "[mii tx clk]",
++ "[mii rx clk]",
++ "NC",
++ "NC",
++ "[usb vbus en]",
++ "P9_31 [spi1_sclk]",
++ "P9_29 [spi1_d0]",
++ "P9_30 [spi1_d1]",
++ "P9_28 [spi1_cs0]",
++ "P9_42B [ecappwm0]",
++ "P9_27",
++ "P9_41A",
++ "P9_25",
++ "NC",
++ "NC",
++ "NC",
++ "NC",
++ "NC",
++ "NC",
++ "NC",
++ "NC",
++ "NC",
++ "NC";
++};
++
++&baseboard_eeprom {
++ vcc-supply = <&ldo4_reg>;
};
diff --git a/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/ti/omap/am335x-osd3358-sm-red.dts
index d28d39728847..0c8a1a1d4fa3 100644
@@ -648,6 +1197,35 @@ index 32669346cefe..4110677c43bc 100644
};
&am33xx_pinmux {
+diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi
+index d6a143abae5f..ee795fd2832b 100644
+--- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi
++++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi
+@@ -854,7 +854,7 @@ pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x300000 0x80000>;
+- status = "disabled";
++ status = "okay";
+
+ pruss: pruss@0 {
+ compatible = "ti,am3356-pruss";
+diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi
+index 5b9e01a8aa5d..6657c9c4b040 100644
+--- a/arch/arm/boot/dts/ti/omap/am33xx.dtsi
++++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi
+@@ -644,6 +644,11 @@ target-module@56000000 {
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
++ gpu: gpu@0 {
++ compatible = "ti,am3352-sgx530", "img,sgx530";
++ reg = <0x0 0x10000>;
++ interrupts = <37>;
++ };
+ };
+ };
+ };
diff --git a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts
index 9a234dc1431d..6081cb88adc9 100644
--- a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts
@@ -749,6 +1327,57 @@ index 0a8b16505ed9..028928f8d43e 100644
};
&tpd12s015 {
+diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi
+index 6509c742fb58..0656e6306d03 100644
+--- a/arch/arm/boot/dts/ti/omap/dra7.dtsi
++++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi
+@@ -856,6 +856,12 @@ target-module@56000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x2000000>;
++
++ gpu: gpu@0 {
++ compatible = "ti,dra7-sgx544", "img,sgx544";
++ reg = <0x0 0x10000>;
++ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++ };
+ };
+
+ crossbar_mpu: crossbar@4a002a48 {
+diff --git a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi
+index fc7233ac183a..d646b61546af 100644
+--- a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi
++++ b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi
+@@ -170,6 +170,12 @@ sgx_module: target-module@50000000 {
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
++
++ sgx: gpu@0 {
++ compatible = "ti,omap3530-sgx530", "img,sgx530";
++ reg = <0x0 0x10000>; /* 64kB */
++ interrupts = <21>;
++ };
+ };
+ };
+
+diff --git a/arch/arm/boot/dts/ti/omap/omap4.dtsi b/arch/arm/boot/dts/ti/omap/omap4.dtsi
+index 2bbff9032be3..a2c71e04ace2 100644
+--- a/arch/arm/boot/dts/ti/omap/omap4.dtsi
++++ b/arch/arm/boot/dts/ti/omap/omap4.dtsi
+@@ -505,6 +505,12 @@ sgx_module: target-module@56000000 {
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
++
++ gpu@0 {
++ compatible = "ti,omap4430-sgx540", "img,sgx540";
++ reg = <0x0 0x2000000>; /* 32MB */
++ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++ };
+ };
+
+ /*
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index e5c64c86d1d5..464b7565d085 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
diff --git a/patches/external/git/BBDTBS b/patches/external/git/BBDTBS
index b8132213..a0504d1b 100644
--- a/patches/external/git/BBDTBS
+++ b/patches/external/git/BBDTBS
@@ -1 +1 @@
-BBDTBS: https://openbeagle.org/beagleboard/BeagleBoard-DeviceTrees/-/commit/2baa426865df1d6f3e90bb91fa488bd168f45b75
+BBDTBS: https://openbeagle.org/beagleboard/BeagleBoard-DeviceTrees/-/commit/fb6f54ec2b36cac20da460d0e51164fa428625d6
diff --git a/patches/get_debian_configs.sh b/patches/get_debian_configs.sh
index dfa25628..6daf0d1f 100755
--- a/patches/get_debian_configs.sh
+++ b/patches/get_debian_configs.sh
@@ -3,8 +3,8 @@
#
#https://packages.debian.org/source/sid/linux
#
-abi="6.6.9"
-kernel="6.6.9-1"
+abi="6.6.11"
+kernel="6.6.11-1"
#
debian_site="http://ftp.us.debian.org/debian/pool/main/l/linux"
diff --git a/repo_maintenance/push-kernel-n-test.sh b/repo_maintenance/push-kernel-n-test.sh
index e3a02171..ea58a28e 100755
--- a/repo_maintenance/push-kernel-n-test.sh
+++ b/repo_maintenance/push-kernel-n-test.sh
@@ -18,10 +18,6 @@ cat_files () {
cat ./patches/external/git/WIRELESS_REGDB >> ${wfile}
fi
- if [ -f ./patches/external/git/KSMBD ] ; then
- cat ./patches/external/git/KSMBD >> ${wfile}
- fi
-
if [ -f ./patches/external/git/TI_AMX3_CM3 ] ; then
cat ./patches/external/git/TI_AMX3_CM3 >> ${wfile}
fi
diff --git a/repo_maintenance/push-n-tag-release.sh b/repo_maintenance/push-n-tag-release.sh
index 9451c364..4eb1ec22 100755
--- a/repo_maintenance/push-n-tag-release.sh
+++ b/repo_maintenance/push-n-tag-release.sh
@@ -18,10 +18,6 @@ cat_files () {
cat ./patches/external/git/WIRELESS_REGDB >> ${wfile}
fi
- if [ -f ./patches/external/git/KSMBD ] ; then
- cat ./patches/external/git/KSMBD >> ${wfile}
- fi
-
if [ -f ./patches/external/git/TI_AMX3_CM3 ] ; then
cat ./patches/external/git/TI_AMX3_CM3 >> ${wfile}
fi
diff --git a/tools/host_det.sh b/tools/host_det.sh
index 577a48d0..cbdba7d0 100755
--- a/tools/host_det.sh
+++ b/tools/host_det.sh
@@ -447,6 +447,11 @@ debian_regs () {
#http://packages.linuxmint.com/index.php
deb_distro="jammy"
;;
+ virginia)
+ #21.3
+ #http://packages.linuxmint.com/index.php
+ deb_distro="jammy"
+ ;;
esac
#Devuan: Compatibility Matrix
diff --git a/version.sh b/version.sh
index 4048f932..e2f4fc37 100644
--- a/version.sh
+++ b/version.sh
@@ -47,7 +47,7 @@ KERNEL_REL=6.7
KERNEL_TAG=${KERNEL_REL}
kernel_rt="-rt6"
#Kernel Build
-BUILD=${build_prefix}15
+BUILD=${build_prefix}15.1
#v6.X-rcX + upto SHA
#prev_KERNEL_SHA=""
--
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