script_support/components/BVF_GATEWARE.tcl → sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl

@@ -149,7 +149,7 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:ADC_CSn" "A
 sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:ADC_MOSI" "ADC_MOSI" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:ADC_MISO" "ADC_MISO" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"ADC_IRQn" "BVF_RISCV_SUBSYSTEM:ADC_IRQn" }
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CLOCKS_AND_RESETS:ADC_MCLK_4_915MHz} -port_name {ADC_MCLK} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:ADC_MCLK_4_915MHz" "ADC_MCLK"} 
 
 #-------------------------------------------------------------------------------
 #sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_0A_REFCLK_N" "CLOCKS_AND_RESETS:XCVR_0A_REFCLK_N" }
@@ -271,6 +271,29 @@ sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {M2_W_DISABLE1} -value {GND} 
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {M2_W_DISABLE2} -value {GND} 
 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_3_RXD} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_2_RXD} -value {GND} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_3_TXD} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_2_TXD} 
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_DI} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_DI} -value {GND} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_DO} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_CLK} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_DO} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_SS1} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_SS1} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_CLK} 
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_56_58} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_3_7} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_F} -value {GND} 
+
 #-------------------------------------------------------------------------------
 
 source script_support/components/SYZYGY/$syzygy_option/ADD_HIGH_SPEED_CONNECTOR.tcl 

script_support/components/BVF_RISCV_SUBSYSTEM.tcl → sources/FPGA-design/script_support/components/BVF_RISCV_SUBSYSTEM.tcl

@@ -83,6 +83,10 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_IRQn} -port_direction
 #-------------------------------------------------------------------------------
 # Cape pins
 #-------------------------------------------------------------------------------
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_2_RXD} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_2_TXD} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_3_RXD} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_3_TXD} -port_direction {OUT}
 sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_4_RXD} -port_direction {IN}
 sd_create_scalar_port -sd_name ${sd_name} -port_name {MMUART_4_TXD} -port_direction {OUT}
 sd_create_scalar_port -sd_name ${sd_name} -port_name {I2C0_SCL} -port_direction {INOUT}
@@ -98,6 +102,21 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDC} -port_direction {
 sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDIO} -port_direction {INOUT}
 
 
+#-------------------------------------------------------------------------------
+# Fabric interrupts
+#-------------------------------------------------------------------------------
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_3_7} -port_direction {IN} -port_range {[7:3]} 
+
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_A} -port_direction {IN} -port_range {[15:8]} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_B} -port_direction {IN} -port_range {[23:16]} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_C} -port_direction {IN} -port_range {[31:24]} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_D} -port_direction {IN} -port_range {[39:32]} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_E} -port_direction {IN} -port_range {[47:40]} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_F} -port_direction {IN} -port_range {[55:48]} 
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_56_58} -port_direction {IN} -port_range {[58:56]} 
+
 #-------------------------------------------------------------------------------
 # User LEDs
 #-------------------------------------------------------------------------------
@@ -137,15 +156,29 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SOC_MSS} -insta
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[0]}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[1]}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[2]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[3]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[4]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[58:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[7:3]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[15:8]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[23:16]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[31:24]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[39:32]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[47:40]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[55:48]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[58:56]"} 
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[59]}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[60]}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[61]}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[62]}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[63]}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:MSS_INT_F2M[58:5]} -value {GND}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_3_7" "PF_SOC_MSS:MSS_INT_F2M[7:3]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_A" "PF_SOC_MSS:MSS_INT_F2M[15:8]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_B" "PF_SOC_MSS:MSS_INT_F2M[23:16]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_C" "PF_SOC_MSS:MSS_INT_F2M[31:24]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_D" "PF_SOC_MSS:MSS_INT_F2M[39:32]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_E" "PF_SOC_MSS:MSS_INT_F2M[47:40]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_F" "PF_SOC_MSS:MSS_INT_F2M[55:48]"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_56_58" "PF_SOC_MSS:MSS_INT_F2M[58:56]"} 
+
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:MSS_INT_M2F}
 #sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:FIC_2_AXI4_TARGET}
 
@@ -295,10 +328,15 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_INT" "PF_SOC_MSS:MSS_INT_F
 #-------------------------------------------------------------------------------
 # Cape
 #-------------------------------------------------------------------------------
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:MMUART_2_TXD_M2F" "MMUART_2_TXD"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:MMUART_2_RXD_F2M" "MMUART_2_RXD"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:MMUART_3_TXD_M2F" "MMUART_3_TXD"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:MMUART_3_RXD_F2M" "MMUART_3_RXD"}
+
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:MMUART_4_TXD_M2F" "MMUART_4_TXD"}
 sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:MMUART_4_RXD_F2M" "MMUART_4_RXD"}
 
-
 #-------------------------------------------------------------------------------
 # User LEDs
 #-------------------------------------------------------------------------------
@@ -545,12 +583,45 @@ sd_rename_port -sd_name ${sd_name} -current_port_name {APBmslave2} -new_port_nam
 sd_rename_port -sd_name ${sd_name} -current_port_name {APBmslave4} -new_port_name {HSI_APB_MTARGET} 
 sd_rename_port -sd_name ${sd_name} -current_port_name {APBmslave16} -new_port_name {M2_APB_MTARGET} 
 
+#-------------------------------------------------------------------------------
+# Additional cape peripherals WIP.
+#-------------------------------------------------------------------------------
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_0_SS1_OE_M2F} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_0_CLK_OE_M2F} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_0_DO_OE_M2F} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_1_CLK_M2F} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_1_DO_M2F} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_1_SS1_M2F} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_1_SS_F2M} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_0_CLK_F2M} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_0_SS_F2M} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:SPI_1_CLK_F2M} -value {GND} 
+
+sd_connect_pin_to_port -sd_name {BVF_RISCV_SUBSYSTEM} -pin_name {PF_SOC_MSS:SPI_0_DI_F2M} -port_name {} 
+sd_connect_pin_to_port -sd_name {BVF_RISCV_SUBSYSTEM} -pin_name {PF_SOC_MSS:SPI_1_DI_F2M} -port_name {} 
+sd_connect_pin_to_port -sd_name {BVF_RISCV_SUBSYSTEM} -pin_name {PF_SOC_MSS:SPI_0_CLK_M2F} -port_name {} 
+sd_connect_pin_to_port -sd_name {BVF_RISCV_SUBSYSTEM} -pin_name {PF_SOC_MSS:SPI_0_DO_M2F} -port_name {} 
+sd_connect_pin_to_port -sd_name {BVF_RISCV_SUBSYSTEM} -pin_name {PF_SOC_MSS:SPI_0_SS1_M2F} -port_name {} 
+
+sd_rename_port -sd_name {BVF_RISCV_SUBSYSTEM} -current_port_name {SPI_0_DI_F2M} -new_port_name {SPI_0_DI} 
+sd_rename_port -sd_name {BVF_RISCV_SUBSYSTEM} -current_port_name {SPI_1_DI_F2M} -new_port_name {SPI_1_DI} 
+
+sd_rename_port -sd_name {BVF_RISCV_SUBSYSTEM} -current_port_name {SPI_0_CLK_M2F} -new_port_name {SPI_0_CLK} 
+sd_rename_port -sd_name {BVF_RISCV_SUBSYSTEM} -current_port_name {SPI_0_DO_M2F} -new_port_name {SPI_0_DO} 
+sd_rename_port -sd_name {BVF_RISCV_SUBSYSTEM} -current_port_name {SPI_0_SS1_M2F} -new_port_name {SPI_0_SS1}
+
+sd_connect_pin_to_port -sd_name {BVF_RISCV_SUBSYSTEM} -pin_name {PF_SOC_MSS:SPI_1_SS1_M2F} -port_name {} 
+sd_connect_pin_to_port -sd_name {BVF_RISCV_SUBSYSTEM} -pin_name {PF_SOC_MSS:SPI_1_CLK_M2F} -port_name {} 
+sd_connect_pin_to_port -sd_name {BVF_RISCV_SUBSYSTEM} -pin_name {PF_SOC_MSS:SPI_1_DO_M2F} -port_name {} 
+
+sd_rename_port -sd_name {BVF_RISCV_SUBSYSTEM} -current_port_name {SPI_1_SS1_M2F} -new_port_name {SPI_1_SS1} 
+sd_rename_port -sd_name {BVF_RISCV_SUBSYSTEM} -current_port_name {SPI_1_DO_M2F} -new_port_name {SPI_1_DO} 
+sd_rename_port -sd_name {BVF_RISCV_SUBSYSTEM} -current_port_name {SPI_1_CLK_M2F} -new_port_name {SPI_1_CLK} 
 
 #-------------------------------------------------------------------------------
 # Temporary connections to allow running through complete flow.
 #-------------------------------------------------------------------------------
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:MSS_INT_F2M[4:4]} -value {GND} 
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:MSS_INT_F2M[3:3]} -value {GND} 
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:MSS_INT_F2M[0:0]} -value {GND} 
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:MSS_RESET_N_F2M} -value {VCC}
 #-------------------------------------------------------------------------------

script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl → sources/FPGA-design/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl

@@ -5,9 +5,9 @@ puts "======== Add cape option: DEFAULT ========"
 #-------------------------------------------------------------------------------
 source script_support/components/CAPE/DEFAULT/APB_BUS_CONVERTER.tcl
 source script_support/components/CAPE/DEFAULT/CoreAPB3_CAPE.tcl
-#source script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl
 source script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl
-source script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+#source script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+source script_support/components/CAPE/DEFAULT/P8_GPIO_UPPER.tcl
 source script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl
 source script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
 source script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
@@ -62,3 +62,43 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_PIN42" "P9_PIN42"}
 
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A" "CAPE:INT_A"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B" "CAPE:INT_B"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C" "CAPE:INT_C"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D" "CAPE:INT_D"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E" "CAPE:INT_E"} 
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_2_TXD} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MMUART_2_TXD} -port_name {} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {MMUART_2_TXD} -new_port_name {P9_24} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_2_RXD} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MMUART_2_RXD} -port_name {} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {MMUART_2_RXD} -new_port_name {P9_26} 
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_CLK} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_DO} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_SS1} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_DI} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_DI} -port_name {} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_SS1} -port_name {} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_CLK} -port_name {} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_DO} -port_name {} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_DI} -new_port_name {P9_18} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_CLK} -new_port_name {P9_22} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_DO} -new_port_name {P9_21} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_SS1} -new_port_name {P9_17} 
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_SS1} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_CLK} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_DO} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_DO} -port_name {} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_SS1} -port_name {} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_CLK} -port_name {} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_SS1} -new_port_name {P9_28} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_CLK} -new_port_name {P9_31} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_DO} -new_port_name {P9_29} 

script_support/components/CAPE/DEFAULT/CAPE.tcl → sources/FPGA-design/script_support/components/CAPE/DEFAULT/CAPE.tcl

-# Creating SmartDesign CAPE
+# Creating SmartDesign "CAPE"
 set sd_name {CAPE}
 create_smartdesign -sd_name ${sd_name}
 
@@ -78,6 +78,11 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {IN
 
 sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PRDATA} -port_direction {OUT} -port_range {[31:0]}
 sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_A} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_B} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_C} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_D} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_E} -port_direction {OUT} -port_range {[7:0]}
 
 
 # Create top level Bus interface Ports
@@ -91,6 +96,9 @@ sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AM
 "PREADY:APB_SLAVE_SLAVE_PREADY" \
 "PSLVERR:APB_SLAVE_SLAVE_PSLVERR" } 
 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT_E} -pin_slices {[4:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT_E} -pin_slices {[7:5]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {INT_E[7:5]} -value {GND}
 # Add APB_BUS_CONVERTER_0 instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
 
@@ -108,11 +116,16 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_CAPE} -in
 
 # Add P8_GPIO_UPPER_0 instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[7:0]}
 
 
 
 # Add P9_GPIO_0 instance
 sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance_name {P9_GPIO_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[20:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[7:0]}
 
 
 
@@ -194,6 +207,11 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN42" "PWM_0:PWM_0" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_IN" "GPIO_IN" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OE" "GPIO_OE" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OUT" "GPIO_OUT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_A" "P8_GPIO_UPPER_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_B" "P8_GPIO_UPPER_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_C" "P9_GPIO_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_D" "P9_GPIO_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_E[4:0]" "P9_GPIO_0:INT[20:16]" }
 
 # Add bus interface net connections
 sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster" }
@@ -206,7 +224,7 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave5" "PW
 
 # Re-enable auto promotion of pins of type 'pad'
 auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
+# Save the SmartDesign 
 save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE
+# Generate SmartDesign "CAPE"
 generate_component -component_name ${sd_name}

script_support/components/CAPE/GPIOS/CoreGPIO_P9.tcl → sources/FPGA-design/script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl

@@ -90,7 +90,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
 "IO_TYPE_17:2"  \
 "IO_TYPE_18:2"  \
 "IO_TYPE_19:2"  \
-"IO_TYPE_20:0"  \
+"IO_TYPE_20:2"  \
 "IO_TYPE_21:0"  \
 "IO_TYPE_22:0"  \
 "IO_TYPE_23:0"  \

script_support/components/CAPE/DEFAULT/P9_GPIO.tcl → sources/FPGA-design/script_support/components/CAPE/DEFAULT/P9_GPIO.tcl

-# Creating SmartDesign P9_GPIO
+# Creating SmartDesign "P9_GPIO"
 set sd_name {P9_GPIO}
 create_smartdesign -sd_name ${sd_name}
 
@@ -28,6 +28,7 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PADDR} -port_directio
 sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PWDATA} -port_direction {IN} -port_range {[31:0]}
 
 sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT} -port_direction {OUT} -port_range {[20:0]}
 
 
 # Create top level Bus interface Ports
@@ -148,7 +149,6 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[8:8]}
 sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[9:9]}
 sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[9:9]}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:INT}
 
 
 
@@ -219,13 +219,15 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_19_BIBUF:PAD" "GPIO_19_PAD
 sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_1_BIBUF:PAD" "GPIO_1_PAD" }
 sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_4_BIBUF:PAD" "GPIO_4_PAD" }
 
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:INT" "INT" }
 
 # Add bus interface net connections
 sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_bif" "CoreGPIO_P9_0:APB_bif" }
 
 # Re-enable auto promotion of pins of type 'pad'
 auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
+# Save the SmartDesign 
 save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign P9_GPIO
+# Generate SmartDesign "P9_GPIO"
 generate_component -component_name ${sd_name}

sources/FPGA-design/script_support/components/CAPE/DEFAULT/Readme.md

+#  Default Cape
+
+## P8 Header
+
+| Signal | Control                    | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P8_1   | n/a                        |  n/a  | GND         |
+| P8_2   | n/a                        |  n/a  | GND         |
+| P8_3   | MSS GPIO_2[0]              |   53  | User LED 0  |
+| P8_4   | MSS GPIO_2[1]              |   53  | User LED 1  |
+| P8_5   | MSS GPIO_2[2]              |   53  | User LED 2  |
+| P8_6   | MSS GPIO_2[3]              |   53  | User LED 3  |
+| P8_7   | MSS GPIO_2[4]              |   53  | User LED 4  |
+| P8_8   | MSS GPIO_2[5]              |   53  | User LED 5  |
+| P8_9   | MSS GPIO_2[6]              |   53  | User LED 6  |
+| P8_10  | MSS GPIO_2[7]              |   53  | User LED 7  |
+| P8_11  | MSS GPIO_2[8]              |   53  | User LED 8  |
+| P8_12  | MSS GPIO_2[9]              |   53  | User LED 9  |
+| P8_13  | core_pwm[1] @ 0x41500000   |  n/a  | PWM_2:1     |
+| P8_14  | MSS GPIO_2[11]             |   53  | User LED 11 |
+| P8_15  | MSS GPIO_2[12]             |   53  | GPIO        |
+| P8_16  | MSS GPIO_2[13]             |   53  | GPIO        |
+| P8_17  | MSS GPIO_2[14]             |   53  | GPIO        |
+| P8_18  | MSS GPIO_2[15]             |   53  | GPIO        |
+| P8_19  | core_pwm[0] @ 0x41500000   |  n/a  | PWM_2:0     |
+| P8_20  | MSS GPIO_2[17]             |   53  | GPIO        |
+| P8_21  | MSS GPIO_2[18]             |   53  | GPIO        |
+| P8_22  | MSS GPIO_2[19]             |   53  | GPIO        |
+| P8_23  | MSS GPIO_2[20]             |   53  | GPIO        |
+| P8_24  | MSS GPIO_2[21]             |   53  | GPIO        |
+| P8_25  | MSS GPIO_2[22]             |   53  | GPIO        |
+| P8_26  | MSS GPIO_2[23]             |   53  | GPIO        |
+| P8_27  | MSS GPIO_2[24]             |   53  | GPIO        |
+| P8_28  | MSS GPIO_2[25]             |   53  | GPIO        |
+| P8_29  | MSS GPIO_2[26]             |   53  | GPIO        |
+| P8_30  | MSS GPIO_2[27]             |   53  | GPIO        |
+| P8_31  | core_gpio[0] @ 0x41100000  |  126  | GPIO        |
+| P8_32  | core_gpio[1] @ 0x41100000  |  127  | GPIO        |
+| P8_33  | core_gpio[2] @ 0x41100000  |  128  | GPIO        |
+| P8_34  | core_gpio[3] @ 0x41100000  |  129  | GPIO        |
+| P8_35  | core_gpio[4] @ 0x41100000  |  130  | GPIO        |
+| P8_36  | core_gpio[5] @ 0x41100000  |  131  | GPIO        |
+| P8_37  | core_gpio[6] @ 0x41100000  |  132  | GPIO        |
+| P8_38  | core_gpio[7] @ 0x41100000  |  133  | GPIO        |
+| P8_39  | core_gpio[8] @ 0x41100000  |  134  | GPIO        |
+| P8_40  | core_gpio[9] @ 0x41100000  |  135  | GPIO        |
+| P8_41  | core_gpio[10] @ 0x41100000 |  136  | GPIO        |
+| P8_42  | core_gpio[11] @ 0x41100000 |  137  | GPIO        |
+| P8_43  | core_gpio[12] @ 0x41100000 |  138  | GPIO        |
+| P8_44  | core_gpio[13] @ 0x41100000 |  139  | GPIO        |
+| P8_45  | core_gpio[14] @ 0x41100000 |  140  | GPIO        |
+| P8_46  | core_gpio[15] @ 0x41100000 |  141  | GPIO        |
+
+## P9 Header
+
+| Signal | Control                    | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P9_1   | n/a                        |  n/a  | GND         |
+| P9_2   | n/a                        |  n/a  | GND         |
+| P9_3   | n/a                        |  n/a  | VCC 3.3V    |
+| P9_4   | n/a                        |  n/a  | VCC 3.3V    |
+| P9_5   | n/a                        |  n/a  | VDD 5V      |
+| P9_6   | n/a                        |  n/a  | VDD 5V      |
+| P9_7   | n/a                        |  n/a  | SYS 5V      |
+| P9_8   | n/a                        |  n/a  | SYS 5V      |
+| P9_9   | n/a                        |  n/a  | NC          |
+| P9_10  | n/a                        |  n/a  | SYS_RSTN    |
+| P9_11  | MMUART4                    |   94  | UART4 RX    |
+| P9_12  | core_gpio[1] @ 0x41200000  |  143  | GPIO        |
+| P9_13  | MMUART4                    |   94  | UART4 TX    |
+| P9_14  | core_pwm[0] @ 0x41400000   |  n/a  | PWM_1:0     |
+| P9_15  | core_gpio[4] @ 0x41200000  |  146  | GPIO        |
+| P9_16  | core_pwm[1] @ 0x41400000   |  n/a  | PWM_1:1     |
+| P9_17  | MSS SPI0                   |   54  | SPI0 CS     |
+| P9_18  | MSS SPI0                   |   54  | SPI0 DI     |
+| P9_19  | MSS I2C0                   |   58  | I2C0 SCL    |
+| P9_20  | MSS I2C0                   |   58  | I2C0 SDA    |
+| P9_21  | MSS SPI0                   |   54  | SPI0 DO     |
+| P9_22  | MSS SPI0                   |   54  | SPI0 SCLK   |
+| P9_23  | core_gpio[10] @ 0x41200000 |  152  | GPIO        |
+| P9_24  | MMUART2                    |   92  | UART1 TX    |
+| P9_25  | core_gpio[12] @ 0x41200000 |  154  | GPIO        |
+| P9_26  | MMUART2                    |   92  | UART2 RX    |
+| P9_27  | core_gpio[14] @ 0x41200000 |  156  | GPIO        |
+| P9_28  | MSS SPI1                   |   55  | SPI1 CS     |
+| P9_29  | MSS SPI1                   |   55  | SPI1 DO     |
+| P9_30  | core_gpio[17] @ 0x41200000 |  159  | GPIO        |
+| P9_31  | MSS SPI1                   |   55  | SPI1 SCLK   |
+| P9_32  | n/a                        |  n/a  | VDD ADC     |
+| P9_33  | n/a                        |  n/a  | ADC input 4 |
+| P9_34  | n/a                        |  n/a  | AGND        |
+| P9_35  | n/a                        |  n/a  | ADC input 6 |
+| P9_36  | n/a                        |  n/a  | ADC input 5 |
+| P9_37  | n/a                        |  n/a  | ADC input 2 |
+| P9_38  | n/a                        |  n/a  | ADC input 3 |
+| P9_39  | n/a                        |  n/a  | ADC input 0 |
+| P9_40  | n/a                        |  n/a  | ADC input 1 |
+| P9_41  | core_gpio[19] @ 0x41200000 |  161  | GPIO        |
+| P9_42  | core_pwm[0] @ 0x41000000   |  n/a  | PWM_0:0     |
+| P9_43  | n/a                        |  n/a  | GND         |
+| P9_44  | n/a                        |  n/a  | GND         |
+| P9_45  | n/a                        |  n/a  | GND         |
+| P9_46  | n/a                        |  n/a  | GND         |

script_support/components/CAPE/DEFAULT/constraints/cape.pdc → sources/FPGA-design/script_support/components/CAPE/DEFAULT/constraints/cape.pdc

@@ -35,30 +35,85 @@ set_io -port_name P9_PIN16	\
     -io_std LVCMOS33  \
     -DIRECTION OUT
 
+set_io -port_name P9_17	\
+    -pin_name C9	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_18	\
+    -pin_name C10	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INPUT
+
+set_io -port_name P9_21	\
+    -pin_name B8	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_22	\
+    -pin_name A8	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+
 set_io -port_name P9_PIN23	\
     -pin_name C12	\
     -fixed true	\
     -io_std LVCMOS33  \
     -DIRECTION INOUT
 
+set_io -port_name P9_24	\
+    -pin_name B12	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
 set_io -port_name P9_PIN25	\
     -pin_name B7	\
     -fixed true	\
     -io_std LVCMOS33  \
     -DIRECTION INOUT
 
+set_io -port_name P9_26	\
+    -pin_name A7	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INPUT
+
 set_io -port_name P9_PIN27	\
     -pin_name D11	\
     -fixed true	\
     -io_std LVCMOS33  \
     -DIRECTION INOUT
 
+set_io -port_name P9_28	\
+    -pin_name C11	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_29	\
+    -pin_name F17	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
 set_io -port_name P9_PIN30	\
     -pin_name F16	\
     -fixed true	\
     -io_std LVCMOS33  \
     -DIRECTION INOUT
 
+set_io -port_name P9_31	\
+    -pin_name E18	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
 set_io -port_name P9_PIN41	\
     -pin_name E15	\
     -fixed true	\
@@ -76,119 +131,165 @@ set_io -port_name P9_PIN42	\
 set_io -port_name P8_PIN3_USER_LED_0  \
     -pin_name V22       \
     -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN4_USER_LED_1  \
     -pin_name W22        \
     -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN5_USER_LED_2  \
     -pin_name V19       \
     -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN6_USER_LED_3  \
     -pin_name V20        \
     -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN7_USER_LED_4  \
     -pin_name V15        \
     -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN8_USER_LED_5  \
     -pin_name V14       \
     -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN9_USER_LED_6  \
     -pin_name V21       \
     -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN10_USER_LED_7  \
     -pin_name W21       \
     -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN11_USER_LED_8	\
     -pin_name Y21	\
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN12_USER_LED_9	\
     -pin_name Y20        \
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN13_USER_LED_10	\
     -pin_name B10	\
     -fixed true	\
     -io_std LVCMOS33  \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN14_USER_LED_11  \
     -pin_name B9	\
     -io_std LVCMOS33  \
     -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 
 set_io -port_name P8_PIN15  \
     -pin_name T12       \
     -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN16  \
     -pin_name U12        \
     -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN17  \
     -pin_name W13        \
     -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN18  \
     -pin_name T16       \
     -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN19	\
     -pin_name W18	\
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN20	\
     -pin_name R16	\
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN21	\
     -pin_name AA21	\
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN22	\
     -pin_name AA22	\
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN23	\
     -pin_name AB18	\
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN24	\
     -pin_name AA18	\
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN25	\
     -pin_name V17	\
     -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
     -DIRECTION INOUT
 
 set_io -port_name P8_PIN26  \