diff --git a/script_support/components/CAPE/GPIOS/constraints/cape.pdc b/script_support/components/CAPE/GPIOS/constraints/cape.pdc
index 5fa4c39d7fe8157b9f32abe9f2f03739b5eb0031..ec6d976b26e213df99bcad85140e2cee9bd50656 100644
--- a/script_support/components/CAPE/GPIOS/constraints/cape.pdc
+++ b/script_support/components/CAPE/GPIOS/constraints/cape.pdc
@@ -1,374 +1,502 @@
-
-set_io -port_name P9_PIN11 \
- -pin_name B5 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN12 \
- -pin_name C5 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN13 \
- -pin_name D19 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN14 \
- -pin_name C6 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN15 \
- -pin_name A5 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN16 \
- -pin_name A6 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN17 \
- -pin_name C9 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN18 \
- -pin_name C10 \
- -io_std LVCMOS33 \
- -fixed true \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN21 \
- -pin_name B8 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN22 \
- -pin_name A8 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN23 \
- -pin_name C12 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN24 \
- -pin_name B12 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN25 \
- -pin_name B7 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN26 \
- -pin_name A7 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN27 \
- -pin_name D11 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN28 \
- -pin_name C11 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN29 \
- -pin_name F17 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN30 \
- -pin_name F16 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN31 \
- -pin_name E18 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_PIN41 \
- -pin_name E15 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P9_PIN42 \
- -pin_name E14 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-#-------------------------------------------------------------------------------
-
-set_io -port_name P8_PIN3_USER_LED_0 \
- -pin_name V22 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN4_USER_LED_1 \
- -pin_name W22 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN5_USER_LED_2 \
- -pin_name V19 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN6_USER_LED_3 \
- -pin_name V20 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN7_USER_LED_4 \
- -pin_name V15 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN8_USER_LED_5 \
- -pin_name V14 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN9_USER_LED_6 \
- -pin_name V21 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN10_USER_LED_7 \
- -pin_name W21 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN11_USER_LED_8 \
- -pin_name Y21 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN12_USER_LED_9 \
- -pin_name Y20 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN13_USER_LED_10 \
- -pin_name B10 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN14_USER_LED_11 \
- -pin_name B9 \
- -io_std LVCMOS33 \
- -fixed true \
- -DIRECTION INOUT
-
-
-
-set_io -port_name P8_PIN15 \
- -pin_name T12 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN16 \
- -pin_name U12 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN17 \
- -pin_name W13 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN18 \
- -pin_name T16 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN19 \
- -pin_name W18 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN20 \
- -pin_name R16 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN21 \
- -pin_name AA21 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN22 \
- -pin_name AA22 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN23 \
- -pin_name AB18 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN24 \
- -pin_name AA18 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN25 \
- -pin_name V17 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN26 \
- -pin_name A12 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN27 \
- -pin_name A13 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN28 \
- -pin_name B14 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN29 \
- -pin_name B13 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN30 \
- -pin_name D14 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN31 \
- -pin_name D13 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN32 \
- -pin_name B15 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN33 \
- -pin_name A15 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN34 \
- -pin_name C15 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN35 \
- -pin_name C14 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN36 \
- -pin_name B4 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN37 \
- -pin_name C4 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN38 \
- -pin_name C17 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN39 \
- -pin_name B17 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN40 \
- -pin_name B18 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN41 \
- -pin_name A18 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN42 \
- -pin_name D6 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN43 \
- -pin_name D7 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN44 \
- -pin_name D8 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN45 \
- -pin_name D9 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN46 \
- -pin_name D18 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
+# Microchip I/O Physical Design Constraints file
+
+# User I/O Constraints file
+
+# Version: 2022.3 2022.3.0.8
+
+# Family: PolarFireSoC , Die: MPFS025T , Package: FCVG484
+
+# Date generated: Wed Oct 18 09:59:26 2023
+
+
+#
+# User Locked I/O Bank Settings
+#
+
+
+#
+# Unlocked I/O Bank Settings
+# The I/O Bank Settings can be locked by directly editing this file
+# or by making changes in the I/O Attribute Editor
+#
+
+
+#
+# User Locked I/O settings
+#
+
+set_io -port_name P8_PIN10_USER_LED_7 \
+ -pin_name W21 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN11_USER_LED_8 \
+ -pin_name Y21 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN12_USER_LED_9 \
+ -pin_name Y20 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN13_USER_LED_10 \
+ -pin_name B10 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN14_USER_LED_11 \
+ -pin_name B9 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN15 \
+ -pin_name T12 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN16 \
+ -pin_name U12 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN17 \
+ -pin_name W13 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN18 \
+ -pin_name T16 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN19 \
+ -pin_name W18 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN20 \
+ -pin_name R16 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN21 \
+ -pin_name AA21 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN22 \
+ -pin_name AA22 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN23 \
+ -pin_name AB18 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN24 \
+ -pin_name AA18 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN25 \
+ -pin_name V17 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN26 \
+ -pin_name A12 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN27 \
+ -pin_name A13 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN28 \
+ -pin_name B14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN29 \
+ -pin_name B13 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN30 \
+ -pin_name D14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN31 \
+ -pin_name D13 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN32 \
+ -pin_name B15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN33 \
+ -pin_name A15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN34 \
+ -pin_name C15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN35 \
+ -pin_name C14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN36 \
+ -pin_name B4 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN37 \
+ -pin_name C4 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN38 \
+ -pin_name C17 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN39 \
+ -pin_name B17 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN3_USER_LED_0 \
+ -pin_name V22 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN40 \
+ -pin_name B18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN41 \
+ -pin_name A18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN42 \
+ -pin_name D6 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN43 \
+ -pin_name D7 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN44 \
+ -pin_name D8 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN45 \
+ -pin_name D9 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN46 \
+ -pin_name D18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN4_USER_LED_1 \
+ -pin_name W22 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN5_USER_LED_2 \
+ -pin_name V19 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN6_USER_LED_3 \
+ -pin_name V20 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN7_USER_LED_4 \
+ -pin_name V15 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN8_USER_LED_5 \
+ -pin_name V14 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN9_USER_LED_6 \
+ -pin_name V21 \
+ -fixed true \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN11 \
+ -pin_name B5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN12 \
+ -pin_name C5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN13 \
+ -pin_name D19 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN14 \
+ -pin_name C6 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN15 \
+ -pin_name A5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN16 \
+ -pin_name A6 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN17 \
+ -pin_name C9 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN18 \
+ -pin_name C10 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN21 \
+ -pin_name B8 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN22 \
+ -pin_name A8 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN23 \
+ -pin_name C12 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN24 \
+ -pin_name B12 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN25 \
+ -pin_name B7 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN26 \
+ -pin_name A7 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN27 \
+ -pin_name D11 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN28 \
+ -pin_name C11 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN29 \
+ -pin_name F17 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN30 \
+ -pin_name F16 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN31 \
+ -pin_name E18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN41 \
+ -pin_name E15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+set_io -port_name P9_PIN42 \
+ -pin_name E14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+
+
+#
+# Dedicated Peripheral I/O Settings
+#
+
+
+#
+# Unlocked I/O settings
+# The I/Os in this section are unplaced or placed but are not locked
+# the other listed attributes have been applied
+#
+
+
+#
+#Ports using Dedicated Pins
+
+#
+
diff --git a/script_support/components/M2/BOARD_TESTS/ADD_M2_INTERFACE.tcl b/script_support/components/M2/BOARD_TESTS/ADD_M2_INTERFACE.tcl
index 8a2dea35dc5c13941a214375fd73aedc60b90c7f..8b3d38a9825d68b719993ff5c59251711be06119 100644
--- a/script_support/components/M2/BOARD_TESTS/ADD_M2_INTERFACE.tcl
+++ b/script_support/components/M2/BOARD_TESTS/ADD_M2_INTERFACE.tcl
@@ -26,6 +26,8 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_UART_CTS} -port_directi
sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PERST0n} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI1_PWND} -port_direction {OUT}
+
#-------------------------------------------------------------------------------
sd_instantiate_component -sd_name ${sd_name} -component_name {M2_INTERFACE} -instance_name {M2_INTERFACE_0}
@@ -52,6 +54,9 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {M2_INTERFACE_0:M2_PEWAKEN}
sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_INTERFACE_0:M2_UART_RTS" "M2_UART_RTS"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_INTERFACE_0:M2_UART_CTS" "M2_UART_CTS"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI1_PWND" "M2_INTERFACE_0:CSI_PWND"}
+sd_invert_pins -sd_name ${sd_name} -pin_names {"CSI1_PWND"}
+
#-------------------------------------------------------------------------------
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_CTS} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_W_DISABLE2}
diff --git a/script_support/components/M2/BOARD_TESTS/CoreGPIO_M2.tcl b/script_support/components/M2/BOARD_TESTS/CoreGPIO_M2.tcl
index bd8dc931d1d15d0432cd9f4dd333fcd47196233d..682e215224be2084a35ffae1743644885335c239 100644
--- a/script_support/components/M2/BOARD_TESTS/CoreGPIO_M2.tcl
+++ b/script_support/components/M2/BOARD_TESTS/CoreGPIO_M2.tcl
@@ -13,7 +13,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"FIXED_CONFIG_6:true" \
"FIXED_CONFIG_7:true" \
"FIXED_CONFIG_8:true" \
-"FIXED_CONFIG_9:false" \
+"FIXED_CONFIG_9:true" \
"FIXED_CONFIG_10:false" \
"FIXED_CONFIG_11:false" \
"FIXED_CONFIG_12:false" \
@@ -69,7 +69,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"IO_INT_TYPE_29:7" \
"IO_INT_TYPE_30:7" \
"IO_INT_TYPE_31:7" \
-"IO_NUM:9" \
+"IO_NUM:10" \
"IO_TYPE_0:2" \
"IO_TYPE_1:2" \
"IO_TYPE_2:2" \
@@ -79,7 +79,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"IO_TYPE_6:2" \
"IO_TYPE_7:2" \
"IO_TYPE_8:2" \
-"IO_TYPE_9:0" \
+"IO_TYPE_9:2" \
"IO_TYPE_10:0" \
"IO_TYPE_11:0" \
"IO_TYPE_12:0" \
diff --git a/script_support/components/M2/BOARD_TESTS/M2_INTERFACE.tcl b/script_support/components/M2/BOARD_TESTS/M2_INTERFACE.tcl
index d3ef6ba6daf8289097e03d979a98c72826e08bad..87f34b9a546caa975e8b07bc07138a0ea837bd60 100644
--- a/script_support/components/M2/BOARD_TESTS/M2_INTERFACE.tcl
+++ b/script_support/components/M2/BOARD_TESTS/M2_INTERFACE.tcl
@@ -14,6 +14,7 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI_PWND} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {H_M2_CLKREQ0N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_I2C_ALTN} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PERST0n} -port_direction {OUT}
@@ -54,6 +55,7 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_IN} -pin_
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_IN} -pin_slices {[6:6]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_IN} -pin_slices {[7:7]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_IN} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_IN} -pin_slices {[9:9]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_OUT} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_OUT} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_OUT} -pin_slices {[2:2]}
@@ -63,12 +65,14 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_OUT} -pin
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_OUT} -pin_slices {[6:6]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_OUT} -pin_slices {[7:7]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_M2_0:GPIO_OUT} -pin_slices {[9:9]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_M2_0:INT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_M2_0:GPIO_OE}
# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI_PWND" "CoreGPIO_M2_0:GPIO_IN[9:9]" "CoreGPIO_M2_0:GPIO_OUT[9:9]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_M2_0:GPIO_IN[0:0]" "CoreGPIO_M2_0:GPIO_OUT[0:0]" "M2_PERST0n" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_M2_0:GPIO_IN[1:1]" "CoreGPIO_M2_0:GPIO_OUT[1:1]" "M2_UART_WAKEN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_M2_0:GPIO_IN[2:2]" "CoreGPIO_M2_0:GPIO_OUT[2:2]" "M2_W_DISABLE1" }
diff --git a/script_support/components/M2/BOARD_TESTS/constraints/M2.pdc b/script_support/components/M2/BOARD_TESTS/constraints/M2.pdc
index 5b6e85b18b9e53880ffe9c0fa7a1b0336a1b3986..99522c0fc3e95f904a380ea173bbe6dd30689ebb 100644
--- a/script_support/components/M2/BOARD_TESTS/constraints/M2.pdc
+++ b/script_support/components/M2/BOARD_TESTS/constraints/M2.pdc
@@ -49,3 +49,8 @@ set_io -port_name H_M2_CLKREQ0N \
-pin_name W19 \
-fixed true \
-DIRECTION OUTPUT
+
+set_io -port_name CSI1_PWND \
+ -pin_name Y13 \
+ -fixed true \
+ -DIRECTION OUTPUT
diff --git a/script_support/components/M2/BOARD_TESTS/device-tree-overlay/pcie.dtso b/script_support/components/M2/BOARD_TESTS/device-tree-overlay/pcie.dtso
index a786b1b2f8fb03e7b917125933d09936e6e6d19a..41ae7d268b120e623ce196e9ea258ac836e77216 100644
--- a/script_support/components/M2/BOARD_TESTS/device-tree-overlay/pcie.dtso
+++ b/script_support/components/M2/BOARD_TESTS/device-tree-overlay/pcie.dtso
@@ -19,10 +19,10 @@
clocks = <&fabric_clk3>;
gpio-controller;
#gpio-cells = <2>;
- ngpios=<9>;
+ ngpios=<10>;
status = "okay";
gpio-line-names = "M2_PERST0N", "M2_UART_WAKEN", "M2_W_DISABLE1_BT", "M2_W_DISABLE2_BT",
- "M2_CLKREQ0N", "M2_PEWAKEN", "M2_I2C_ALTN", "M2_UART_RTS", "M2_UART_CTS";
+ "M2_CLKREQ0N", "M2_PEWAKEN", "M2_I2C_ALTN", "M2_UART_RTS", "M2_UART_CTS","CSI1_PWND";
};
};
};
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
index ef59270b60b57e6ebc4520ff418a07eeed63e004..79740765d4aac4b12797bc0dc6d7da1d44018535 100644
--- a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
@@ -16,13 +16,13 @@ source script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
set sd_name ${top_level_name}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI1_PWND} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI1_PWND} -port_direction {OUT}
sd_instantiate_component -sd_name ${sd_name} -component_name {IMX219_IF_TOP} -instance_name {IMX219_IF_TOP_0}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "IMX219_IF_TOP_0:INIT_DONE"}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CSI1_PWND} -value {VCC}
+#sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CSI1_PWND} -value {VCC}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "IMX219_IF_TOP_0:PCLK"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "IMX219_IF_TOP_0:PRESETN"}
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
index e6909e4b332906d80ff6b6005e4078652a830837..6f9ec3014a08eafc0919700963736d807804d0be 100644
--- a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
@@ -1,7 +1,7 @@
-set_io -port_name CSI1_PWND \
- -pin_name Y13 \
- -fixed true \
- -DIRECTION OUTPUT
+#set_io -port_name CSI1_PWND \
+# -pin_name Y13 \
+# -fixed true \
+# -DIRECTION OUTPUT
set_io -port_name CAM_C_N \