From 91d9a981b105573d4f427ca435942f63ca1df40f Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Tue, 23 May 2023 17:56:22 +0100
Subject: [PATCH] PCIe: Add APB PSTR signals to PCIe block.
---
script_support/components/BVF_RISCV_SUBSYSTEM.tcl | 2 +-
script_support/components/M2/DEFAULT/ADD_M2_INTERFACE.tcl | 3 ++-
script_support/components/M2/DEFAULT/M2_INTERFACE.tcl | 2 ++
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/script_support/components/BVF_RISCV_SUBSYSTEM.tcl b/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
index 2103ea4..8c85360 100644
--- a/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
+++ b/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
@@ -327,6 +327,7 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {PF_SOC_MSS:FIC_0_ACLK} -po
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {PF_SOC_MSS:FIC_1_ACLK} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {PF_SOC_MSS:FIC_2_ACLK} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_RESET_N_M2F} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {PF_SOC_MSS:FIC_3_APB_M_PSTRB} -port_name {}
#-------------------------------------------------------------------------------
@@ -551,7 +552,6 @@ sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SOC_MSS:MSS_RESET
# Mark pins unused
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:FIC_3_APB_M_PSTRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:PLL_CPU_LOCK_M2F}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:PLL_DDR_LOCK_M2F}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:PLL_SGMII_LOCK_M2F}
diff --git a/script_support/components/M2/DEFAULT/ADD_M2_INTERFACE.tcl b/script_support/components/M2/DEFAULT/ADD_M2_INTERFACE.tcl
index 2602990..da40f5c 100644
--- a/script_support/components/M2/DEFAULT/ADD_M2_INTERFACE.tcl
+++ b/script_support/components/M2/DEFAULT/ADD_M2_INTERFACE.tcl
@@ -39,8 +39,9 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {M2_INTERFACE} -ins
#-------------------------------------------------------------------------------
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_1_ACLK" "M2_INTERFACE_0:ACLK"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_1_AXI4_TARGET" "M2_INTERFACE_0:AXI4_INITIATOR"}
-sd_connect_pins -sd_name {BVF_GATEWARE} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_1_AXI4_INITIATOR" "M2_INTERFACE_0:AXI_TARGET"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_1_AXI4_INITIATOR" "M2_INTERFACE_0:AXI_TARGET"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:M2_APB_MTARGET" "M2_INTERFACE_0:APB_TARGET"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_3_APB_M_PSTRB" "M2_INTERFACE_0:PSTRB"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:CLKS_TO_XCVR" "M2_INTERFACE_0:CLKS_FROM_TXPLL_TO_PCIE_0"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "M2_INTERFACE_0:PCLK"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "M2_INTERFACE_0:PRESETN"}
diff --git a/script_support/components/M2/DEFAULT/M2_INTERFACE.tcl b/script_support/components/M2/DEFAULT/M2_INTERFACE.tcl
index ad3126d..e28e75d 100644
--- a/script_support/components/M2/DEFAULT/M2_INTERFACE.tcl
+++ b/script_support/components/M2/DEFAULT/M2_INTERFACE.tcl
@@ -88,6 +88,8 @@ sd_rename_port -sd_name ${sd_name} -current_port_name {INIT_DONE} -new_port_name
sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_PERST0n" "PCIE:PCIE_0_PERST_OUT_N"}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {RECONFIGURATION_INTERFACE_0:PSTRB} -port_name {}
+
#-------------------------------------------------------------------------------
# Re-enable auto promotion of pins of type 'pad'
--
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