From 6b4365ddccf79d3f9526cf9f8aa5b903846731c1 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 14 May 2023 18:09:24 +0100
Subject: [PATCH] PCIe: Adjust PCIe block configuration.
Adjust PCIe block configuration to match Microchip 2023.02 release.
---
script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl b/script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl
index 061da1b..b7d45d1 100644
--- a/script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl
+++ b/script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl
@@ -20,7 +20,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:*} -component_name {P
"UI_PCIE_0_DE_EMPHASIS:-3.5 dB" \
"UI_PCIE_0_DEVICE_ID:0x1556" \
"UI_PCIE_0_EXPOSE_WAKE_SIG:Disabled" \
-"UI_PCIE_0_INTERRUPTS:MSI1" \
+"UI_PCIE_0_INTERRUPTS:MSI8" \
"UI_PCIE_0_L0_ACC_LATENCY:No limit" \
"UI_PCIE_0_L0_EXIT_LATENCY:64 ns to less than 128 ns" \
"UI_PCIE_0_L1_ACC_LATENCY:No limit" \
@@ -63,7 +63,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:*} -component_name {P
"UI_PCIE_0_PORT_TYPE:Root Port" \
"UI_PCIE_0_REF_CLK_FREQ:100" \
"UI_PCIE_0_REVISION_ID:0x0000" \
-"UI_PCIE_0_SLAVE_SIZE_TABLE_0:4 KB" \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_0:2 GB" \
"UI_PCIE_0_SLAVE_SIZE_TABLE_1:4 KB" \
"UI_PCIE_0_SLAVE_SIZE_TABLE_2:4 KB" \
"UI_PCIE_0_SLAVE_SIZE_TABLE_3:4 KB" \
--
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